1 /*
2  * Copyright (c) 2023, Ambiq Micro, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  *
31  * @file     apollo4p.h
32  * @brief    CMSIS HeaderFile
33  * @version  1.0
34  * @date     01. June 2023
35  * @note     Generated by SVDConv V3.3.42 on Thursday, 01.06.2023 11:06:52
36  *           from File './apollo4p.svd',
37  *           last modified on Thursday, 01.06.2023 16:06:52
38  */
39 
40 
41 
42 /** @addtogroup Ambiq Micro
43   * @{
44   */
45 
46 
47 /** @addtogroup apollo4p
48   * @{
49   */
50 
51 
52 #ifndef APOLLO4P_H
53 #define APOLLO4P_H
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 
60 /** @addtogroup Configuration_of_CMSIS
61   * @{
62   */
63 
64 
65 
66 /* =========================================================================================================================== */
67 /* ================                                Interrupt Number Definition                                ================ */
68 /* =========================================================================================================================== */
69 
70 typedef enum {
71 /* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
72   Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
73   NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
74   HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
75   MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
76                                                      and No Match                                                              */
77   BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
78                                                      related Fault                                                             */
79   UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
80   SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
81   DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
82   PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
83   SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
84 /* ==========================================  apollo4p Specific Interrupt Numbers  ========================================== */
85   BROWNOUT_IRQn             =   0,              /*!< 0  BROWNOUT_IRQ                                                           */
86   WDT_IRQn                  =   1,              /*!< 1  WDT_IRQ                                                                */
87   RTC_IRQn                  =   2,              /*!< 2  RTC_IRQ                                                                */
88   VCOMP_IRQn                =   3,              /*!< 3  VCOMP_IRQ                                                              */
89   IOSLAVE_IRQn              =   4,              /*!< 4  IOSLAVE_IRQ                                                            */
90   IOSLAVEACC_IRQn           =   5,              /*!< 5  IOSLAVEACC_IRQ                                                         */
91   IOMSTR0_IRQn              =   6,              /*!< 6  IOMSTR0_IRQ                                                            */
92   IOMSTR1_IRQn              =   7,              /*!< 7  IOMSTR1_IRQ                                                            */
93   IOMSTR2_IRQn              =   8,              /*!< 8  IOMSTR2_IRQ                                                            */
94   IOMSTR3_IRQn              =   9,              /*!< 9  IOMSTR3_IRQ                                                            */
95   IOMSTR4_IRQn              =  10,              /*!< 10 IOMSTR4_IRQ                                                            */
96   IOMSTR5_IRQn              =  11,              /*!< 11 IOMSTR5_IRQ                                                            */
97   IOMSTR6_IRQn              =  12,              /*!< 12 IOMSTR6_IRQ                                                            */
98   IOMSTR7_IRQn              =  13,              /*!< 13 IOMSTR7_IRQ                                                            */
99   TIMER_IRQn                =  14,              /*!< 14 TIMER_IRQ                                                              */
100   UART0_IRQn                =  15,              /*!< 15 UART0_IRQ                                                              */
101   UART1_IRQn                =  16,              /*!< 16 UART1_IRQ                                                              */
102   UART2_IRQn                =  17,              /*!< 17 UART2_IRQ                                                              */
103   UART3_IRQn                =  18,              /*!< 18 UART3_IRQ                                                              */
104   ADC_IRQn                  =  19,              /*!< 19 ADC_IRQ                                                                */
105   MSPI0_IRQn                =  20,              /*!< 20 MSPI0_IRQ                                                              */
106   MSPI1_IRQn                =  21,              /*!< 21 MSPI1_IRQ                                                              */
107   MSPI2_IRQn                =  22,              /*!< 22 MSPI2_IRQ                                                              */
108   CLKGEN_IRQn               =  23,              /*!< 23 CLKGEN_IRQ                                                             */
109   CRYPTOSEC_IRQn            =  24,              /*!< 24 CRYPTOSEC_IRQ                                                          */
110   SDIO_IRQn                 =  26,              /*!< 26 SDIO_IRQ                                                               */
111   USB0_IRQn                 =  27,              /*!< 27 USB0_IRQ                                                               */
112   GPU_IRQn                  =  28,              /*!< 28 GPU_IRQ                                                                */
113   DC_IRQn                   =  29,              /*!< 29 DC_IRQ                                                                 */
114   DSI_IRQn                  =  30,              /*!< 30 DSI_IRQ                                                                */
115   STIMER_CMPR0_IRQn         =  32,              /*!< 32 STIMER_CMPR0_IRQ                                                       */
116   STIMER_CMPR1_IRQn         =  33,              /*!< 33 STIMER_CMPR1_IRQ                                                       */
117   STIMER_CMPR2_IRQn         =  34,              /*!< 34 STIMER_CMPR2_IRQ                                                       */
118   STIMER_CMPR3_IRQn         =  35,              /*!< 35 STIMER_CMPR3_IRQ                                                       */
119   STIMER_CMPR4_IRQn         =  36,              /*!< 36 STIMER_CMPR4_IRQ                                                       */
120   STIMER_CMPR5_IRQn         =  37,              /*!< 37 STIMER_CMPR5_IRQ                                                       */
121   STIMER_CMPR6_IRQn         =  38,              /*!< 38 STIMER_CMPR6_IRQ                                                       */
122   STIMER_CMPR7_IRQn         =  39,              /*!< 39 STIMER_CMPR7_IRQ                                                       */
123   STIMER_OVF_IRQn           =  40,              /*!< 40 STIMER_OVF_IRQ                                                         */
124   AUDADC0_IRQn              =  42,              /*!< 42 AUDADC0_IRQ                                                            */
125   I2S0_IRQn                 =  44,              /*!< 44 I2S0_IRQ                                                               */
126   I2S1_IRQn                 =  45,              /*!< 45 I2S1_IRQ                                                               */
127   PDM0_IRQn                 =  48,              /*!< 48 PDM0_IRQ                                                               */
128   PDM1_IRQn                 =  49,              /*!< 49 PDM1_IRQ                                                               */
129   PDM2_IRQn                 =  50,              /*!< 50 PDM2_IRQ                                                               */
130   PDM3_IRQn                 =  51,              /*!< 51 PDM3_IRQ                                                               */
131   GPIO0_001F_IRQn           =  56,              /*!< 56 GPIO0_001F_IRQ                                                         */
132   GPIO0_203F_IRQn           =  57,              /*!< 57 GPIO0_203F_IRQ                                                         */
133   GPIO0_405F_IRQn           =  58,              /*!< 58 GPIO0_405F_IRQ                                                         */
134   GPIO0_607F_IRQn           =  59,              /*!< 59 GPIO0_607F_IRQ                                                         */
135   GPIO1_001F_IRQn           =  60,              /*!< 60 GPIO1_001F_IRQ                                                         */
136   GPIO1_203F_IRQn           =  61,              /*!< 61 GPIO1_203F_IRQ                                                         */
137   GPIO1_405F_IRQn           =  62,              /*!< 62 GPIO1_405F_IRQ                                                         */
138   GPIO1_607F_IRQn           =  63,              /*!< 63 GPIO1_607F_IRQ                                                         */
139   TIMER0_IRQn               =  67,              /*!< 67 TIMER0_IRQ                                                             */
140   TIMER1_IRQn               =  68,              /*!< 68 TIMER1_IRQ                                                             */
141   TIMER2_IRQn               =  69,              /*!< 69 TIMER2_IRQ                                                             */
142   TIMER3_IRQn               =  70,              /*!< 70 TIMER3_IRQ                                                             */
143   TIMER4_IRQn               =  71,              /*!< 71 TIMER4_IRQ                                                             */
144   TIMER5_IRQn               =  72,              /*!< 72 TIMER5_IRQ                                                             */
145   TIMER6_IRQn               =  73,              /*!< 73 TIMER6_IRQ                                                             */
146   TIMER7_IRQn               =  74,              /*!< 74 TIMER7_IRQ                                                             */
147   TIMER8_IRQn               =  75,              /*!< 75 TIMER8_IRQ                                                             */
148   TIMER9_IRQn               =  76,              /*!< 76 TIMER9_IRQ                                                             */
149   TIMER10_IRQn              =  77,              /*!< 77 TIMER10_IRQ                                                            */
150   TIMER11_IRQn              =  78,              /*!< 78 TIMER11_IRQ                                                            */
151   TIMER12_IRQn              =  79,              /*!< 79 TIMER12_IRQ                                                            */
152   TIMER13_IRQn              =  80,              /*!< 80 TIMER13_IRQ                                                            */
153   TIMER14_IRQn              =  81,              /*!< 81 TIMER14_IRQ                                                            */
154   TIMER15_IRQn              =  82,              /*!< 82 TIMER15_IRQ                                                            */
155   CACHE_IRQn                =  83,              /*!< 83 CACHE_IRQ                                                              */
156   MAX_IRQn                  =  84               /*!< 84 Not a valid IRQ. The maximum IRQ is this value - 1.                    */
157 } IRQn_Type;
158 
159 
160 
161 /* =========================================================================================================================== */
162 /* ================                           Processor and Core Peripheral Section                           ================ */
163 /* =========================================================================================================================== */
164 
165 /* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
166 #define __CM4_REV                 0x0100U       /*!< CM4 Core Revision                                                         */
167 #define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */
168 #define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
169 #define __MPU_PRESENT                  1        /*!< MPU present                                                               */
170 #define __FPU_PRESENT                  1        /*!< FPU present                                                               */
171 
172 
173 /** @} */ /* End of group Configuration_of_CMSIS */
174 
175 #include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */
176 #include "system_apollo4p.h"                    /*!< apollo4p System                                                           */
177 
178 #ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
179   #define __IM   __I
180 #endif
181 #ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
182   #define __OM   __O
183 #endif
184 #ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
185   #define __IOM  __IO
186 #endif
187 
188 
189 /* ========================================  Start of section using anonymous unions  ======================================== */
190 #if defined (__CC_ARM)
191   #pragma push
192   #pragma anon_unions
193 #elif defined (__ICCARM__)
194   #pragma language=extended
195 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
196   #pragma clang diagnostic push
197   #pragma clang diagnostic ignored "-Wc11-extensions"
198   #pragma clang diagnostic ignored "-Wreserved-id-macro"
199   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
200   #pragma clang diagnostic ignored "-Wnested-anon-types"
201 #elif defined (__GNUC__)
202   /* anonymous unions are enabled by default */
203 #elif defined (__TMS470__)
204   /* anonymous unions are enabled by default */
205 #elif defined (__TASKING__)
206   #pragma warning 586
207 #elif defined (__CSMC__)
208   /* anonymous unions are enabled by default */
209 #else
210   #warning Not supported compiler type
211 #endif
212 
213 
214 /* =========================================================================================================================== */
215 /* ================                            Device Specific Peripheral Section                             ================ */
216 /* =========================================================================================================================== */
217 
218 
219 /** @addtogroup Device_Peripheral_peripherals
220   * @{
221   */
222 
223 
224 
225 /* =========================================================================================================================== */
226 /* ================                                            ADC                                            ================ */
227 /* =========================================================================================================================== */
228 
229 
230 /**
231   * @brief Analog Digital Converter Control (ADC)
232   */
233 
234 typedef struct {                                /*!< (@ 0x40038000) ADC Structure                                              */
235 
236   union {
237     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The ADC Configuration Register contains the software
238                                                                     control for selecting the clock frequency
239                                                                     used for the SAR conversions, the trigger
240                                                                     polarity, the trigger select, the reference
241                                                                     voltage select, the low power mode, the
242                                                                     operating mode (single scan per trigger
243                                                                     vs. repeating mode) and ADC enable.                        */
244 
245     struct {
246       __IOM uint32_t ADCEN      : 1;            /*!< [0..0] This bit enables the ADC module. While the ADC is enabled,
247                                                      the ADCCFG and SLOT Configuration regsiter settings must
248                                                      remain stable and unchanged. All configuration register
249                                                      settings, slot configuration settings and window comparison
250                                                      settings should be written prior to setting the ADCEN bit
251                                                      to '1'.                                                                   */
252             uint32_t            : 1;
253       __IOM uint32_t RPTEN      : 1;            /*!< [2..2] This bit enables Repeating Scan Mode.                              */
254       __IOM uint32_t LPMODE     : 1;            /*!< [3..3] Select power mode to enter between active scans.                   */
255       __IOM uint32_t CKMODE     : 1;            /*!< [4..4] Clock mode register                                                */
256             uint32_t            : 7;
257       __IOM uint32_t DFIFORDEN  : 1;            /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable
258                                                      FIFO pop upon reading the FIFOPR register.                                */
259             uint32_t            : 3;
260       __IOM uint32_t TRIGSEL    : 3;            /*!< [18..16] Select the ADC trigger source.                                   */
261       __IOM uint32_t TRIGPOL    : 1;            /*!< [19..19] This bit selects the ADC trigger polarity for external
262                                                      off chip triggers.                                                        */
263       __IOM uint32_t RPTTRIGSEL : 1;            /*!< [20..20] This bit selects which periodic trigger to use with
264                                                      RPTEN = 1.                                                                */
265             uint32_t            : 3;
266       __IOM uint32_t CLKSEL     : 2;            /*!< [25..24] Select the source and frequency for the general purpose
267                                                      ADC clock. HFRC_24MHZ is the only valid GP ADC clock selection
268                                                      and must be configured for proper operation.                              */
269             uint32_t            : 6;
270     } CFG_b;
271   } ;
272 
273   union {
274     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) This register indicates the basic power status
275                                                                     for the ADC. For detailed power status,
276                                                                     see the power control power status register.
277                                                                     ADC power mode 0 indicates the ADC is in
278                                                                     its full power state and is ready to process
279                                                                     scans. ADC Power mode 1 indicates the ADC
280                                                                     enabled and in a low power state.                          */
281 
282     struct {
283       __IOM uint32_t PWDSTAT    : 1;            /*!< [0..0] Indicates the power-status of the ADC.                             */
284             uint32_t            : 31;
285     } STAT_b;
286   } ;
287 
288   union {
289     __IOM uint32_t SWT;                         /*!< (@ 0x00000008) This register enables initiating an ADC scan
290                                                                     through software.                                          */
291 
292     struct {
293       __IOM uint32_t SWT        : 8;            /*!< [7..0] Writing 0x37 to this register generates a software trigger.        */
294             uint32_t            : 24;
295     } SWT_b;
296   } ;
297 
298   union {
299     __IOM uint32_t SL0CFG;                      /*!< (@ 0x0000000C) Slot 0 Configuration                                       */
300 
301     struct {
302       __IOM uint32_t SLEN0      : 1;            /*!< [0..0] This bit enables slot 0 for ADC conversions.                       */
303       __IOM uint32_t WCEN0      : 1;            /*!< [1..1] This bit enables the window compare function for slot
304                                                      0.                                                                        */
305             uint32_t            : 6;
306       __IOM uint32_t CHSEL0     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
307             uint32_t            : 4;
308       __IOM uint32_t PRMODE0    : 2;            /*!< [17..16] Set the Precision Mode For Slot 0.                               */
309       __IOM uint32_t TRKCYC0    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
310                                                      to the specified number of ADC clock cycles. (Note that
311                                                      a value of 0 in this register specifies the minimum required
312                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
313       __IOM uint32_t ADSEL0     : 3;            /*!< [26..24] Select the number of measurements to average in the
314                                                      accumulate divide module for this slot.                                   */
315             uint32_t            : 5;
316     } SL0CFG_b;
317   } ;
318 
319   union {
320     __IOM uint32_t SL1CFG;                      /*!< (@ 0x00000010) Slot 1 Configuration                                       */
321 
322     struct {
323       __IOM uint32_t SLEN1      : 1;            /*!< [0..0] This bit enables slot 1 for ADC conversions.                       */
324       __IOM uint32_t WCEN1      : 1;            /*!< [1..1] This bit enables the window compare function for slot
325                                                      1.                                                                        */
326             uint32_t            : 6;
327       __IOM uint32_t CHSEL1     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
328             uint32_t            : 4;
329       __IOM uint32_t PRMODE1    : 2;            /*!< [17..16] Set the Precision Mode For Slot 1.                               */
330       __IOM uint32_t TRKCYC1    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
331                                                      to the specified number of ADC clock cycles. (Note that
332                                                      a value of 0 in this register specifies the minimum required
333                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
334       __IOM uint32_t ADSEL1     : 3;            /*!< [26..24] Select the number of measurements to average in the
335                                                      accumulate divide module for this slot.                                   */
336             uint32_t            : 5;
337     } SL1CFG_b;
338   } ;
339 
340   union {
341     __IOM uint32_t SL2CFG;                      /*!< (@ 0x00000014) Slot 2 Configuration                                       */
342 
343     struct {
344       __IOM uint32_t SLEN2      : 1;            /*!< [0..0] This bit enables slot 2 for ADC conversions.                       */
345       __IOM uint32_t WCEN2      : 1;            /*!< [1..1] This bit enables the window compare function for slot
346                                                      2.                                                                        */
347             uint32_t            : 6;
348       __IOM uint32_t CHSEL2     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
349             uint32_t            : 4;
350       __IOM uint32_t PRMODE2    : 2;            /*!< [17..16] Set the Precision Mode For Slot 2.                               */
351       __IOM uint32_t TRKCYC2    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
352                                                      to the specified number of ADC clock cycles. (Note that
353                                                      a value of 0 in this register specifies the minimum required
354                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
355       __IOM uint32_t ADSEL2     : 3;            /*!< [26..24] Select the number of measurements to average in the
356                                                      accumulate divide module for this slot.                                   */
357             uint32_t            : 5;
358     } SL2CFG_b;
359   } ;
360 
361   union {
362     __IOM uint32_t SL3CFG;                      /*!< (@ 0x00000018) Slot 3 Configuration                                       */
363 
364     struct {
365       __IOM uint32_t SLEN3      : 1;            /*!< [0..0] This bit enables slot 3 for ADC conversions.                       */
366       __IOM uint32_t WCEN3      : 1;            /*!< [1..1] This bit enables the window compare function for slot
367                                                      3.                                                                        */
368             uint32_t            : 6;
369       __IOM uint32_t CHSEL3     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
370             uint32_t            : 4;
371       __IOM uint32_t PRMODE3    : 2;            /*!< [17..16] Set the Precision Mode For Slot 3.                               */
372       __IOM uint32_t TRKCYC3    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
373                                                      to the specified number of ADC clock cycles. (Note that
374                                                      a value of 0 in this register specifies the minimum required
375                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
376       __IOM uint32_t ADSEL3     : 3;            /*!< [26..24] Select the number of measurements to average in the
377                                                      accumulate divide module for this slot.                                   */
378             uint32_t            : 5;
379     } SL3CFG_b;
380   } ;
381 
382   union {
383     __IOM uint32_t SL4CFG;                      /*!< (@ 0x0000001C) Slot 4 Configuration                                       */
384 
385     struct {
386       __IOM uint32_t SLEN4      : 1;            /*!< [0..0] This bit enables slot 4 for ADC conversions.                       */
387       __IOM uint32_t WCEN4      : 1;            /*!< [1..1] This bit enables the window compare function for slot
388                                                      4.                                                                        */
389             uint32_t            : 6;
390       __IOM uint32_t CHSEL4     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
391             uint32_t            : 4;
392       __IOM uint32_t PRMODE4    : 2;            /*!< [17..16] Set the Precision Mode For Slot 4.                               */
393       __IOM uint32_t TRKCYC4    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
394                                                      to the specified number of ADC clock cycles. (Note that
395                                                      a value of 0 in this register specifies the minimum required
396                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
397       __IOM uint32_t ADSEL4     : 3;            /*!< [26..24] Select the number of measurements to average in the
398                                                      accumulate divide module for this slot.                                   */
399             uint32_t            : 5;
400     } SL4CFG_b;
401   } ;
402 
403   union {
404     __IOM uint32_t SL5CFG;                      /*!< (@ 0x00000020) Slot 5 Configuration                                       */
405 
406     struct {
407       __IOM uint32_t SLEN5      : 1;            /*!< [0..0] This bit enables slot 5 for ADC conversions.                       */
408       __IOM uint32_t WCEN5      : 1;            /*!< [1..1] This bit enables the window compare function for slot
409                                                      5.                                                                        */
410             uint32_t            : 6;
411       __IOM uint32_t CHSEL5     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
412             uint32_t            : 4;
413       __IOM uint32_t PRMODE5    : 2;            /*!< [17..16] Set the Precision Mode For Slot 5.                               */
414       __IOM uint32_t TRKCYC5    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
415                                                      to the specified number of ADC clock cycles. (Note that
416                                                      a value of 0 in this register specifies the minimum required
417                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
418       __IOM uint32_t ADSEL5     : 3;            /*!< [26..24] Select the number of measurements to average in the
419                                                      accumulate divide module for this slot.                                   */
420             uint32_t            : 5;
421     } SL5CFG_b;
422   } ;
423 
424   union {
425     __IOM uint32_t SL6CFG;                      /*!< (@ 0x00000024) Slot 6 Configuration                                       */
426 
427     struct {
428       __IOM uint32_t SLEN6      : 1;            /*!< [0..0] This bit enables slot 6 for ADC conversions.                       */
429       __IOM uint32_t WCEN6      : 1;            /*!< [1..1] This bit enables the window compare function for slot
430                                                      6.                                                                        */
431             uint32_t            : 6;
432       __IOM uint32_t CHSEL6     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
433             uint32_t            : 4;
434       __IOM uint32_t PRMODE6    : 2;            /*!< [17..16] Set the Precision Mode For Slot 6.                               */
435       __IOM uint32_t TRKCYC6    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
436                                                      to the specified number of ADC clock cycles. (Note that
437                                                      a value of 0 in this register specifies the minimum required
438                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
439       __IOM uint32_t ADSEL6     : 3;            /*!< [26..24] Select the number of measurements to average in the
440                                                      accumulate divide module for this slot.                                   */
441             uint32_t            : 5;
442     } SL6CFG_b;
443   } ;
444 
445   union {
446     __IOM uint32_t SL7CFG;                      /*!< (@ 0x00000028) Slot 7 Configuration                                       */
447 
448     struct {
449       __IOM uint32_t SLEN7      : 1;            /*!< [0..0] This bit enables slot 7 for ADC conversions.                       */
450       __IOM uint32_t WCEN7      : 1;            /*!< [1..1] This bit enables the window compare function for slot
451                                                      7.                                                                        */
452             uint32_t            : 6;
453       __IOM uint32_t CHSEL7     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
454             uint32_t            : 4;
455       __IOM uint32_t PRMODE7    : 2;            /*!< [17..16] Set the Precision Mode For Slot 7.                               */
456       __IOM uint32_t TRKCYC7    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
457                                                      to the specified number of ADC clock cycles. (Note that
458                                                      a value of 0 in this register specifies the minimum required
459                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
460       __IOM uint32_t ADSEL7     : 3;            /*!< [26..24] Select the number of measurements to average in the
461                                                      accumulate divide module for this slot.                                   */
462             uint32_t            : 5;
463     } SL7CFG_b;
464   } ;
465 
466   union {
467     __IOM uint32_t WULIM;                       /*!< (@ 0x0000002C) Window Comparator Upper Limits                             */
468 
469     struct {
470       __IOM uint32_t ULIM       : 20;           /*!< [19..0] Sets the upper limit for the window comparator.                   */
471             uint32_t            : 12;
472     } WULIM_b;
473   } ;
474 
475   union {
476     __IOM uint32_t WLLIM;                       /*!< (@ 0x00000030) Window Comparator Lower Limits                             */
477 
478     struct {
479       __IOM uint32_t LLIM       : 20;           /*!< [19..0] Sets the lower limit for the window comparator.                   */
480             uint32_t            : 12;
481     } WLLIM_b;
482   } ;
483 
484   union {
485     __IOM uint32_t SCWLIM;                      /*!< (@ 0x00000034) Scale Window Comparator Limits                             */
486 
487     struct {
488       __IOM uint32_t SCWLIMEN   : 1;            /*!< [0..0] Scale the window limits compare values per precision
489                                                      mode. When set to 0x0 (default), the values in the 20-bit
490                                                      limits registers will compare directly with the FIFO values
491                                                      regardless of the precision mode the slot is configured
492                                                      to. When set to 0x1, the compare values will be divided
493                                                      by the difference in precision bits while performing the
494                                                      window limit comparisons.                                                 */
495             uint32_t            : 31;
496     } SCWLIM_b;
497   } ;
498 
499   union {
500     __IOM uint32_t FIFO;                        /*!< (@ 0x00000038) The ADC FIFO Register contains the slot number
501                                                                     and fifo data for the oldest conversion
502                                                                     data in the FIFO. The COUNT field indicates
503                                                                     the total number of valid entries in the
504                                                                     FIFO. A write to this register will pop
505                                                                     one of the FIFO entries off the FIFO and
506                                                                     decrease the COUNT by 1 if the COUNT is
507                                                                     greater than zero.                                         */
508 
509     struct {
510       __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
511       __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
512       __IOM uint32_t SLOTNUM    : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
513       __IOM uint32_t RSVD       : 1;            /*!< [31..31] RESERVED.                                                        */
514     } FIFO_b;
515   } ;
516 
517   union {
518     __IOM uint32_t FIFOPR;                      /*!< (@ 0x0000003C) This is a Pop Read mirrored copy of the ADCFIFO
519                                                                     register with the only difference being
520                                                                     that reading this register will result in
521                                                                     a simultaneous FIFO POP which is also achieved
522                                                                     by writing to the ADCFIFO Register. Note:
523                                                                     The DFIFORDEN bit must be set in the CFG
524                                                                     register for the the destructive read to
525                                                                     be enabled.                                                */
526 
527     struct {
528       __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
529       __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
530       __IOM uint32_t SLOTNUMPR  : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
531       __IOM uint32_t RSVDPR     : 1;            /*!< [31..31] RESERVED.                                                        */
532     } FIFOPR_b;
533   } ;
534 
535   union {
536     __IOM uint32_t INTTRIGTIMER;                /*!< (@ 0x00000040) ADC-Internal Repeating Trigger Timer Configuration         */
537 
538     struct {
539       __IOM uint32_t TIMERMAX   : 10;           /*!< [9..0] Trigger counter count max, used as initial condition
540                                                      to trigger. Also used repeatedly each time counter reaches
541                                                      it to restart trigger timer at zero. To update this value,
542                                                      first disable the INTTRIGTIMER by setting TIMEREN to DIS,
543                                                      change TIMERMAX, and then reenable it INTTRIGTIMER by setting
544                                                      TIMEREN to EN again.                                                      */
545             uint32_t            : 6;
546       __IOM uint32_t CLKDIV     : 3;            /*!< [18..16] Configure number of divide-by-2 of clock source as
547                                                      input to trigger counter. (Max value of 5.) A value of
548                                                      0 in this register would not divide down the ADC input
549                                                      clock. A value of 1 would divide the ADC input clock frequency
550                                                      by 2. A value of 5 would divide the ADC input clock frequency
551                                                      by 2^5 = 32. To update this value, first disable the INTTRIGTIMER
552                                                      by setting TIMEREN to DIS, change CLKDIV, and then reenable
553                                                      it INTTRIGTIMER by setting TIMEREN to EN again.                           */
554             uint32_t            : 12;
555       __IOM uint32_t TIMEREN    : 1;            /*!< [31..31] ADC-internal trigger timer enable.                               */
556     } INTTRIGTIMER_b;
557   } ;
558   __IM  uint32_t  RESERVED[7];
559 
560   union {
561     __IOM uint32_t ZXCFG;                       /*!< (@ 0x00000060) Zero Crossing Comparator Configuration                     */
562 
563     struct {
564       __IOM uint32_t ZXEN       : 1;            /*!< [0..0] Enable the ZX comparator                                           */
565             uint32_t            : 3;
566       __IOM uint32_t ZXCHANSEL  : 1;            /*!< [4..4] Select which slots to use for zero crossing measurement.
567                                                      0 enables zero crossing detection on slots 0 and 2. 1 enables
568                                                      zero crossing detection on slots 1 and 3.                                 */
569             uint32_t            : 27;
570     } ZXCFG_b;
571   } ;
572 
573   union {
574     __IOM uint32_t ZXLIM;                       /*!< (@ 0x00000064) Zero Crossing Comparator Limits                            */
575 
576     struct {
577       __IOM uint32_t LZXC       : 12;           /*!< [11..0] Sets the lower integer sample limit for the ZX comparator.
578                                                      Note that these values are raw ADC values whose bounds
579                                                      are specified by PRMODE but not maniupulated by accumulate/divide
580                                                      logic. Therefore, there is no oversampling and no binary
581                                                      point in this value. Samples must enter the range between
582                                                      UZXC and LZXC in order for a zero crossing to be recognized.              */
583             uint32_t            : 4;
584       __IOM uint32_t UZXC       : 12;           /*!< [27..16] Sets the upper integer sample limit for the ZX comparator.
585                                                      Note that these values are raw ADC values whose bounds
586                                                      are specified by PRMODE but not maniupulated by accumulate/divide
587                                                      logic. Therefore, there is no oversampling and no binary
588                                                      point in this value. Samples must enter the range between
589                                                      UZXC and LZXC in order for a zero crossing to be recognized.              */
590             uint32_t            : 4;
591     } ZXLIM_b;
592   } ;
593 
594   union {
595     __IOM uint32_t GAINCFG;                     /*!< (@ 0x00000068) PGA Gain Configuration                                     */
596 
597     struct {
598       __IOM uint32_t PGACTRLEN  : 1;            /*!< [0..0] Enable PGA gain updates.                                           */
599             uint32_t            : 3;
600       __IOM uint32_t UPDATEMODE : 1;            /*!< [4..4] PGA update mode                                                    */
601             uint32_t            : 27;
602     } GAINCFG_b;
603   } ;
604 
605   union {
606     __IOM uint32_t GAIN;                        /*!< (@ 0x0000006C) PGA Gain Codes                                             */
607 
608     struct {
609       __IOM uint32_t LGA        : 7;            /*!< [6..0] Specifies the low gain code (0 to 102 decimal specifies
610                                                      -6.0 dB to 45.0 dB in half-dB increments) for channel A
611                                                      (slot 0).                                                                 */
612             uint32_t            : 1;
613       __IOM uint32_t HGADELTA   : 7;            /*!< [14..8] Specifies the high gain code as an delta from the LGA
614                                                      field for channel A (slot 1).                                             */
615             uint32_t            : 1;
616       __IOM uint32_t LGB        : 7;            /*!< [22..16] Specifies the low gain code (0 to 102 decimal specifies
617                                                      -6.0 dB to 45.0 dB in half-dB increments) for channel B
618                                                      (slot 2).                                                                 */
619             uint32_t            : 1;
620       __IOM uint32_t HGBDELTA   : 7;            /*!< [30..24] Specifies the high gain code as an delta from the LGB
621                                                      field for channel B (slot 3).                                             */
622             uint32_t            : 1;
623     } GAIN_b;
624   } ;
625   __IM  uint32_t  RESERVED1[13];
626 
627   union {
628     __IOM uint32_t SATCFG;                      /*!< (@ 0x000000A4) Saturation Comparator Configuration                        */
629 
630     struct {
631       __IOM uint32_t SATEN      : 1;            /*!< [0..0] Enable the saturation comparator                                   */
632             uint32_t            : 3;
633       __IOM uint32_t SATCHANSEL : 1;            /*!< [4..4] Select which slots to use for saturation measurement.
634                                                      0 enables saturation on slots 0 and 2. 1 enables saturation
635                                                      on slots 1 and 3.                                                         */
636             uint32_t            : 27;
637     } SATCFG_b;
638   } ;
639 
640   union {
641     __IOM uint32_t SATLIM;                      /*!< (@ 0x000000A8) Saturation Comparator Limits                               */
642 
643     struct {
644       __IOM uint32_t LSATC      : 12;           /*!< [11..0] Sets the lower integer sample limit for the saturation
645                                                      comparator. Note that these values are raw ADC values whose
646                                                      bounds are specified by PRMODE but not manipulated by accumulate/divide
647                                                      logic. Therefore, there is no oversampling and no binary
648                                                      point in this value.                                                      */
649             uint32_t            : 4;
650       __IOM uint32_t USATC      : 12;           /*!< [27..16] Sets the upper integer sample limit for the saturation
651                                                      comparator. Note that these values are raw ADC values whose
652                                                      bounds are specified by PRMODE but not manipulated by accumulate/divide
653                                                      logic. Therefore, there is no oversampling and no binary
654                                                      point in this value.                                                      */
655             uint32_t            : 4;
656     } SATLIM_b;
657   } ;
658 
659   union {
660     __IOM uint32_t SATMAX;                      /*!< (@ 0x000000AC) Saturation Comparator Event Counter Limits                 */
661 
662     struct {
663       __IOM uint32_t SATCAMAX   : 12;           /*!< [11..0] Sets the number of saturation events that may occur
664                                                      before a SATCA interrupt occurs. Once this interrupt occurs,
665                                                      the saturation event counter must be cleared by writing
666                                                      the SATCLR register. A value of 0 is invalid and will cause
667                                                      the saturation interrupt to assert immediately.                           */
668             uint32_t            : 4;
669       __IOM uint32_t SATCBMAX   : 12;           /*!< [27..16] Sets the number of saturation events that may occur
670                                                      before a SATCB interrupt occurs. Once this interrupt occurs,
671                                                      the saturation event counter must be cleared by writing
672                                                      the SATCLR register. A value of 0 is invalid and will cause
673                                                      the saturation interrupt to assert immediately.                           */
674             uint32_t            : 4;
675     } SATMAX_b;
676   } ;
677 
678   union {
679     __IOM uint32_t SATCLR;                      /*!< (@ 0x000000B0) Clears the saturation event counter registers              */
680 
681     struct {
682       __IOM uint32_t SATCACLR   : 1;            /*!< [0..0] Clear saturation event counter register for channel A
683                                                      (slots 0 or 1, depending on SATCHANSEL)                                   */
684       __IOM uint32_t SATCBCLR   : 1;            /*!< [1..1] Clear saturation event counter register for channel B
685                                                      (slots 2 or 3, depending on SATCHANSEL)                                   */
686             uint32_t            : 30;
687     } SATCLR_b;
688   } ;
689   __IM  uint32_t  RESERVED2[83];
690 
691   union {
692     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
693                                                                     to generate the corresponding interrupt.                   */
694 
695     struct {
696       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
697       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
698       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
699       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
700       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
701       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
702       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
703       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
704       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
705       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
706       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
707       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
708             uint32_t            : 20;
709     } INTEN_b;
710   } ;
711 
712   union {
713     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
714                                                                     cause of a recent interrupt.                               */
715 
716     struct {
717       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
718       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
719       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
720       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
721       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
722       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
723       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
724       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
725       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
726       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
727       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
728       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
729             uint32_t            : 20;
730     } INTSTAT_b;
731   } ;
732 
733   union {
734     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
735                                                                     the interrupt status associated with that
736                                                                     bit.                                                       */
737 
738     struct {
739       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
740       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
741       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
742       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
743       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
744       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
745       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
746       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
747       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
748       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
749       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
750       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
751             uint32_t            : 20;
752     } INTCLR_b;
753   } ;
754 
755   union {
756     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
757                                                                     generate an interrupt from this module.
758                                                                     (Generally used for testing purposes).                     */
759 
760     struct {
761       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
762       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
763       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
764       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
765       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
766       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
767       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
768       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
769       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
770       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
771       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
772       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
773             uint32_t            : 20;
774     } INTSET_b;
775   } ;
776   __IM  uint32_t  RESERVED3[12];
777 
778   union {
779     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) DMA Trigger Enable                                         */
780 
781     struct {
782       __IOM uint32_t DFIFO75    : 1;            /*!< [0..0] Trigger DMA upon FIFO 75 percent Full                              */
783       __IOM uint32_t DFIFOFULL  : 1;            /*!< [1..1] Trigger DMA upon FIFO 100 percent Full                             */
784             uint32_t            : 30;
785     } DMATRIGEN_b;
786   } ;
787 
788   union {
789     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) DMA Trigger Status                                         */
790 
791     struct {
792       __IOM uint32_t D75STAT    : 1;            /*!< [0..0] Triggered DMA from FIFO 75 percent Full                            */
793       __IOM uint32_t DFULLSTAT  : 1;            /*!< [1..1] Triggered DMA from FIFO 100 percent Full                           */
794             uint32_t            : 30;
795     } DMATRIGSTAT_b;
796   } ;
797   __IM  uint32_t  RESERVED4[14];
798 
799   union {
800     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) DMA Configuration                                          */
801 
802     struct {
803       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
804             uint32_t            : 1;
805       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
806             uint32_t            : 5;
807       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
808       __IOM uint32_t DMADYNPRI  : 1;            /*!< [9..9] Enables dynamic priority based on FIFO fullness. When
809                                                      FIFO is full, priority is automatically set to HIGH. Otherwise,
810                                                      DMAPRI is used.                                                           */
811             uint32_t            : 7;
812       __IOM uint32_t DMAMSK     : 1;            /*!< [17..17] Mask the FIFOCNT and SLOTNUM when transferring FIFO
813                                                      contents to memory                                                        */
814       __IOM uint32_t DPWROFF    : 1;            /*!< [18..18] Power Off the ADC System upon DMACPL.                            */
815             uint32_t            : 13;
816     } DMACFG_b;
817   } ;
818   __IM  uint32_t  RESERVED5;
819 
820   union {
821     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) DMA Total Transfer Count                                   */
822 
823     struct {
824             uint32_t            : 2;
825       __IOM uint32_t TOTCOUNT   : 16;           /*!< [17..2] Total Transfer Count                                              */
826             uint32_t            : 14;
827     } DMATOTCOUNT_b;
828   } ;
829 
830   union {
831     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) DMA Target Address                                         */
832 
833     struct {
834       __IOM uint32_t LTARGADDR  : 28;           /*!< [27..0] DMA Target Address                                                */
835       __IOM uint32_t UTARGADDR  : 4;            /*!< [31..28] SRAM Target                                                      */
836     } DMATARGADDR_b;
837   } ;
838 
839   union {
840     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) DMA Status                                                 */
841 
842     struct {
843       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
844       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
845       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
846             uint32_t            : 29;
847     } DMASTAT_b;
848   } ;
849 } ADC_Type;                                     /*!< Size = 660 (0x294)                                                        */
850 
851 
852 
853 /* =========================================================================================================================== */
854 /* ================                                          APBDMA                                           ================ */
855 /* =========================================================================================================================== */
856 
857 
858 /**
859   * @brief APB DMA Register Interfaces (APBDMA)
860   */
861 
862 typedef struct {                                /*!< (@ 0x40011000) APBDMA Structure                                           */
863 
864   union {
865     __IOM uint32_t BBVALUE;                     /*!< (@ 0x00000000) Control                                                    */
866 
867     struct {
868       __IOM uint32_t DATAOUT    : 8;            /*!< [7..0] Data Output Values                                                 */
869             uint32_t            : 8;
870       __IOM uint32_t PIN        : 8;            /*!< [23..16] PIO values                                                       */
871             uint32_t            : 8;
872     } BBVALUE_b;
873   } ;
874 
875   union {
876     __IOM uint32_t BBSETCLEAR;                  /*!< (@ 0x00000004) Set/Clear                                                  */
877 
878     struct {
879       __IOM uint32_t SET        : 8;            /*!< [7..0] Write 1 to Set PIO value (set hier priority than clear
880                                                      if both bit set)                                                          */
881             uint32_t            : 8;
882       __IOM uint32_t CLEAR      : 8;            /*!< [23..16] Write 1 to Clear PIO value                                       */
883             uint32_t            : 8;
884     } BBSETCLEAR_b;
885   } ;
886 
887   union {
888     __IOM uint32_t BBINPUT;                     /*!< (@ 0x00000008) PIO Input Values                                           */
889 
890     struct {
891       __IOM uint32_t DATAIN     : 8;            /*!< [7..0] PIO values                                                         */
892             uint32_t            : 24;
893     } BBINPUT_b;
894   } ;
895   __IM  uint32_t  RESERVED[5];
896 
897   union {
898     __IOM uint32_t DEBUGDATA;                   /*!< (@ 0x00000020) PIO Input Values                                           */
899 
900     struct {
901       __IOM uint32_t DEBUGDATA  : 32;           /*!< [31..0] Debug Data                                                        */
902     } DEBUGDATA_b;
903   } ;
904   __IM  uint32_t  RESERVED1[7];
905 
906   union {
907     __IOM uint32_t DEBUG;                       /*!< (@ 0x00000040) PIO Input Values                                           */
908 
909     struct {
910       __IOM uint32_t DEBUGEN    : 4;            /*!< [3..0] Debug Enable                                                       */
911             uint32_t            : 28;
912     } DEBUG_b;
913   } ;
914 } APBDMA_Type;                                  /*!< Size = 68 (0x44)                                                          */
915 
916 
917 
918 /* =========================================================================================================================== */
919 /* ================                                          AUDADC                                           ================ */
920 /* =========================================================================================================================== */
921 
922 
923 /**
924   * @brief Audio Analog Digital Converter Control (AUDADC)
925   */
926 
927 typedef struct {                                /*!< (@ 0x40210000) AUDADC Structure                                           */
928 
929   union {
930     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The Audio ADC Configuration Register contains
931                                                                     the software control for selecting the clock
932                                                                     frequency used for the SAR conversions,
933                                                                     the trigger polarity, the trigger select,
934                                                                     the reference voltage select, the low power
935                                                                     mode, the operating mode (single scan per
936                                                                     trigger vs. repeating mode) and AUDADC enable.             */
937 
938     struct {
939       __IOM uint32_t ADCEN      : 1;            /*!< [0..0] This bit enables the AUDADC module. While the AUDADC
940                                                      is enabled, the ADCCFG and SLOT Configuration regsiter
941                                                      settings must remain stable and unchanged. All configuration
942                                                      register settings, slot configuration settings and window
943                                                      comparison settings should be written prior to setting
944                                                      the ADCEN bit to '1'.                                                     */
945             uint32_t            : 1;
946       __IOM uint32_t RPTEN      : 1;            /*!< [2..2] This bit enables Repeating Scan Mode.                              */
947       __IOM uint32_t LPMODE     : 1;            /*!< [3..3] Select power mode to enter between active scans.                   */
948       __IOM uint32_t CKMODE     : 1;            /*!< [4..4] Clock mode register                                                */
949             uint32_t            : 7;
950       __IOM uint32_t DFIFORDEN  : 1;            /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable
951                                                      FIFO pop upon reading the FIFOPR register.                                */
952       __IOM uint32_t SAMPMODE   : 1;            /*!< [13..13] Audio ADC sampling mode. Changes to this control bit
953                                                      are applied when the audio ADC is not performing conversions.
954                                                      This is the only control bit which is properly synchronized
955                                                      to AUDADC operation.                                                      */
956             uint32_t            : 2;
957       __IOM uint32_t TRIGSEL    : 3;            /*!< [18..16] Select the AUDADC trigger source.                                */
958       __IOM uint32_t TRIGPOL    : 1;            /*!< [19..19] This bit selects the AUDADC trigger polarity for external
959                                                      off chip triggers.                                                        */
960       __IOM uint32_t RPTTRIGSEL : 1;            /*!< [20..20] This bit selects which periodic trigger to use with
961                                                      RPTEN = 1.                                                                */
962             uint32_t            : 3;
963       __IOM uint32_t CLKSEL     : 2;            /*!< [25..24] Select the source and frequency for the AUDADC clock.This
964                                                      field should be left as is because HFRC_48MHz is the only
965                                                      clock selection and it is selected by default. All values
966                                                      enumerated below as 'RSVD' are undefined. The AUDADC controller
967                                                      automatically shuts off the clock in its low power modes.
968                                                      When setting ADCEN to '0', CLKSEL should remain set to
969                                                      0x0 or 0x1 for proper power down sequencing.                              */
970             uint32_t            : 6;
971     } CFG_b;
972   } ;
973 
974   union {
975     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) This register indicates the basic power status
976                                                                     for the AUDADC. For detailed power status,
977                                                                     see the power control power status register.
978                                                                     AUDADC power mode 0 indicates the AUDADC
979                                                                     is in its full power state and is ready
980                                                                     to process scans. AUDADC Power mode 1 indicates
981                                                                     the AUDADC enabled and in a low power state.               */
982 
983     struct {
984       __IOM uint32_t PWDSTAT    : 1;            /*!< [0..0] Indicates the power-status of the AUDADC.                          */
985             uint32_t            : 31;
986     } STAT_b;
987   } ;
988 
989   union {
990     __IOM uint32_t SWT;                         /*!< (@ 0x00000008) This register enables initiating an AUDADC scan
991                                                                     through software.                                          */
992 
993     struct {
994       __IOM uint32_t SWT        : 8;            /*!< [7..0] Writing 0x37 to this register generates a software trigger.        */
995             uint32_t            : 24;
996     } SWT_b;
997   } ;
998 
999   union {
1000     __IOM uint32_t SL0CFG;                      /*!< (@ 0x0000000C) Slot 0 Configuration                                       */
1001 
1002     struct {
1003       __IOM uint32_t SLEN0      : 1;            /*!< [0..0] This bit enables slot 0 for AUDADC conversions.                    */
1004       __IOM uint32_t WCEN0      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1005                                                      0.                                                                        */
1006             uint32_t            : 6;
1007       __IOM uint32_t CHSEL0     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1008             uint32_t            : 4;
1009       __IOM uint32_t PRMODE0    : 2;            /*!< [17..16] Set the Precision Mode For Slot 0.                               */
1010       __IOM uint32_t TRKCYC0    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1011                                                      to the specified number of AUDADC clock cycles. (Note that
1012                                                      a value of 0 in this register specifies the minimum required
1013                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1014       __IOM uint32_t ADSEL0     : 3;            /*!< [26..24] Select the number of measurements to average in the
1015                                                      accumulate divide module for this slot.                                   */
1016             uint32_t            : 5;
1017     } SL0CFG_b;
1018   } ;
1019 
1020   union {
1021     __IOM uint32_t SL1CFG;                      /*!< (@ 0x00000010) Slot 1 Configuration                                       */
1022 
1023     struct {
1024       __IOM uint32_t SLEN1      : 1;            /*!< [0..0] This bit enables slot 1 for AUDADC conversions.                    */
1025       __IOM uint32_t WCEN1      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1026                                                      1.                                                                        */
1027             uint32_t            : 6;
1028       __IOM uint32_t CHSEL1     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1029             uint32_t            : 4;
1030       __IOM uint32_t PRMODE1    : 2;            /*!< [17..16] Set the Precision Mode For Slot 1.                               */
1031       __IOM uint32_t TRKCYC1    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1032                                                      to the specified number of AUDADC clock cycles. (Note that
1033                                                      a value of 0 in this register specifies the minimum required
1034                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1035       __IOM uint32_t ADSEL1     : 3;            /*!< [26..24] Select the number of measurements to average in the
1036                                                      accumulate divide module for this slot.                                   */
1037             uint32_t            : 5;
1038     } SL1CFG_b;
1039   } ;
1040 
1041   union {
1042     __IOM uint32_t SL2CFG;                      /*!< (@ 0x00000014) Slot 2 Configuration                                       */
1043 
1044     struct {
1045       __IOM uint32_t SLEN2      : 1;            /*!< [0..0] This bit enables slot 2 for AUDADC conversions.                    */
1046       __IOM uint32_t WCEN2      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1047                                                      2.                                                                        */
1048             uint32_t            : 6;
1049       __IOM uint32_t CHSEL2     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1050             uint32_t            : 4;
1051       __IOM uint32_t PRMODE2    : 2;            /*!< [17..16] Set the Precision Mode For Slot 2.                               */
1052       __IOM uint32_t TRKCYC2    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1053                                                      to the specified number of AUDADC clock cycles. (Note that
1054                                                      a value of 0 in this register specifies the minimum required
1055                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1056       __IOM uint32_t ADSEL2     : 3;            /*!< [26..24] Select the number of measurements to average in the
1057                                                      accumulate divide module for this slot.                                   */
1058             uint32_t            : 5;
1059     } SL2CFG_b;
1060   } ;
1061 
1062   union {
1063     __IOM uint32_t SL3CFG;                      /*!< (@ 0x00000018) Slot 3 Configuration                                       */
1064 
1065     struct {
1066       __IOM uint32_t SLEN3      : 1;            /*!< [0..0] This bit enables slot 3 for AUDADC conversions.                    */
1067       __IOM uint32_t WCEN3      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1068                                                      3.                                                                        */
1069             uint32_t            : 6;
1070       __IOM uint32_t CHSEL3     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1071             uint32_t            : 4;
1072       __IOM uint32_t PRMODE3    : 2;            /*!< [17..16] Set the Precision Mode For Slot 3.                               */
1073       __IOM uint32_t TRKCYC3    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1074                                                      to the specified number of AUDADC clock cycles. (Note that
1075                                                      a value of 0 in this register specifies the minimum required
1076                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1077       __IOM uint32_t ADSEL3     : 3;            /*!< [26..24] Select the number of measurements to average in the
1078                                                      accumulate divide module for this slot.                                   */
1079             uint32_t            : 5;
1080     } SL3CFG_b;
1081   } ;
1082 
1083   union {
1084     __IOM uint32_t SL4CFG;                      /*!< (@ 0x0000001C) Slot 4 Configuration                                       */
1085 
1086     struct {
1087       __IOM uint32_t SLEN4      : 1;            /*!< [0..0] This bit enables slot 4 for AUDADC conversions.                    */
1088       __IOM uint32_t WCEN4      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1089                                                      4.                                                                        */
1090             uint32_t            : 6;
1091       __IOM uint32_t CHSEL4     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1092             uint32_t            : 4;
1093       __IOM uint32_t PRMODE4    : 2;            /*!< [17..16] Set the Precision Mode For Slot 4.                               */
1094       __IOM uint32_t TRKCYC4    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1095                                                      to the specified number of AUDADC clock cycles. (Note that
1096                                                      a value of 0 in this register specifies the minimum required
1097                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1098       __IOM uint32_t ADSEL4     : 3;            /*!< [26..24] Select the number of measurements to average in the
1099                                                      accumulate divide module for this slot.                                   */
1100             uint32_t            : 5;
1101     } SL4CFG_b;
1102   } ;
1103 
1104   union {
1105     __IOM uint32_t SL5CFG;                      /*!< (@ 0x00000020) Slot 5 Configuration                                       */
1106 
1107     struct {
1108       __IOM uint32_t SLEN5      : 1;            /*!< [0..0] This bit enables slot 5 for AUDADC conversions.                    */
1109       __IOM uint32_t WCEN5      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1110                                                      5.                                                                        */
1111             uint32_t            : 6;
1112       __IOM uint32_t CHSEL5     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1113             uint32_t            : 4;
1114       __IOM uint32_t PRMODE5    : 2;            /*!< [17..16] Set the Precision Mode For Slot 5.                               */
1115       __IOM uint32_t TRKCYC5    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1116                                                      to the specified number of AUDADC clock cycles. (Note that
1117                                                      a value of 0 in this register specifies the minimum required
1118                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1119       __IOM uint32_t ADSEL5     : 3;            /*!< [26..24] Select the number of measurements to average in the
1120                                                      accumulate divide module for this slot.                                   */
1121             uint32_t            : 5;
1122     } SL5CFG_b;
1123   } ;
1124 
1125   union {
1126     __IOM uint32_t SL6CFG;                      /*!< (@ 0x00000024) Slot 6 Configuration                                       */
1127 
1128     struct {
1129       __IOM uint32_t SLEN6      : 1;            /*!< [0..0] This bit enables slot 6 for AUDADC conversions.                    */
1130       __IOM uint32_t WCEN6      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1131                                                      6.                                                                        */
1132             uint32_t            : 6;
1133       __IOM uint32_t CHSEL6     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1134             uint32_t            : 4;
1135       __IOM uint32_t PRMODE6    : 2;            /*!< [17..16] Set the Precision Mode For Slot 6.                               */
1136       __IOM uint32_t TRKCYC6    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1137                                                      to the specified number of AUDADC clock cycles. (Note that
1138                                                      a value of 0 in this register specifies the minimum required
1139                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1140       __IOM uint32_t ADSEL6     : 3;            /*!< [26..24] Select the number of measurements to average in the
1141                                                      accumulate divide module for this slot.                                   */
1142             uint32_t            : 5;
1143     } SL6CFG_b;
1144   } ;
1145 
1146   union {
1147     __IOM uint32_t SL7CFG;                      /*!< (@ 0x00000028) Slot 7 Configuration                                       */
1148 
1149     struct {
1150       __IOM uint32_t SLEN7      : 1;            /*!< [0..0] This bit enables slot 7 for AUDADC conversions.                    */
1151       __IOM uint32_t WCEN7      : 1;            /*!< [1..1] This bit enables the window compare function for slot
1152                                                      7.                                                                        */
1153             uint32_t            : 6;
1154       __IOM uint32_t CHSEL7     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
1155             uint32_t            : 4;
1156       __IOM uint32_t PRMODE7    : 2;            /*!< [17..16] Set the Precision Mode For Slot 7.                               */
1157       __IOM uint32_t TRKCYC7    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
1158                                                      to the specified number of AUDADC clock cycles. (Note that
1159                                                      a value of 0 in this register specifies the minimum required
1160                                                      5 cycles. A maximum of 64 specifies 69 cycles.)                           */
1161       __IOM uint32_t ADSEL7     : 3;            /*!< [26..24] Select the number of measurements to average in the
1162                                                      accumulate divide module for this slot.                                   */
1163             uint32_t            : 5;
1164     } SL7CFG_b;
1165   } ;
1166 
1167   union {
1168     __IOM uint32_t WULIM;                       /*!< (@ 0x0000002C) Window Comparator Upper Limits                             */
1169 
1170     struct {
1171       __IOM uint32_t ULIM       : 20;           /*!< [19..0] Sets the upper limit for the window comparator.                   */
1172             uint32_t            : 12;
1173     } WULIM_b;
1174   } ;
1175 
1176   union {
1177     __IOM uint32_t WLLIM;                       /*!< (@ 0x00000030) Window Comparator Lower Limits                             */
1178 
1179     struct {
1180       __IOM uint32_t LLIM       : 20;           /*!< [19..0] Sets the lower limit for the window comparator.                   */
1181             uint32_t            : 12;
1182     } WLLIM_b;
1183   } ;
1184 
1185   union {
1186     __IOM uint32_t SCWLIM;                      /*!< (@ 0x00000034) Scale Window Comparator Limits                             */
1187 
1188     struct {
1189       __IOM uint32_t SCWLIMEN   : 1;            /*!< [0..0] Scale the window limits compare values per precision
1190                                                      mode. When set to 0x0 (default), the values in the 20-bit
1191                                                      limits registers will compare directly with the FIFO values
1192                                                      regardless of the precision mode the slot is configured
1193                                                      to. When set to 0x1, the compare values will be divided
1194                                                      by the difference in precision bits while performing the
1195                                                      window limit comparisons.                                                 */
1196             uint32_t            : 31;
1197     } SCWLIM_b;
1198   } ;
1199 
1200   union {
1201     __IOM uint32_t FIFO;                        /*!< (@ 0x00000038) The AUDADC FIFO Register contains up to 2 samples
1202                                                                     for a single channel (high and low gain
1203                                                                     PGA samples), each sample up to 12-bits.
1204                                                                     It also contains meta data in the form of
1205                                                                     which audio channel the sample(s) are from
1206                                                                     along with the PGA gain code for that sample
1207                                                                     pair. When no data is present, FIFO entry
1208                                                                     reads back as all 1s (0xFFFFFFFF).                         */
1209 
1210     struct {
1211       __IOM uint32_t METALO     : 4;            /*!< [3..0] Meta data about this sample which represents the lower
1212                                                      4 bits of the PGA gain code                                               */
1213       __IOM uint32_t LGDATA     : 12;           /*!< [15..4] Low-gain PGA sample data                                          */
1214       __IOM uint32_t METAHI     : 3;            /*!< [18..16] Meta data about this sample which represents the upper
1215                                                      3 bits of the PGA gain code                                               */
1216       __IOM uint32_t MIC        : 1;            /*!< [19..19] Which audio channel this data is from encoded as int(slot
1217                                                      number/2). In other words, this is 1 if data is from slots
1218                                                      2 or 3, or 0 if from slots 0 or 1.                                        */
1219       __IOM uint32_t HGDATA     : 12;           /*!< [31..20] High-gain PGA sample data                                        */
1220     } FIFO_b;
1221   } ;
1222 
1223   union {
1224     __IOM uint32_t FIFOPR;                      /*!< (@ 0x0000003C) This is a pop-on-read mirrored copy of the ADCFIFO
1225                                                                     register with the only difference being
1226                                                                     that reading this register will result in
1227                                                                     a simultaneous FIFO POP which is also achieved
1228                                                                     by writing to the ADCFIFO Register. Note:
1229                                                                     The DFIFORDEN bit must be set in the CFG
1230                                                                     register for the the destructive read to
1231                                                                     be enabled.                                                */
1232 
1233     struct {
1234       __IOM uint32_t METALOPR   : 4;            /*!< [3..0] Meta data about this sample which represents the lower
1235                                                      4 bits of the PGA gain code                                               */
1236       __IOM uint32_t LGDATAPR   : 12;           /*!< [15..4] Low-gain PGA sample data                                          */
1237       __IOM uint32_t METAHIPR   : 3;            /*!< [18..16] Meta data about this sample which represents the upper
1238                                                      3 bits of the PGA gain code                                               */
1239       __IOM uint32_t MICPR      : 1;            /*!< [19..19] Which audio channel this data is from encoded as int(slot
1240                                                      number/2). In other words, this is 1 if data is from slots
1241                                                      2 or 3, or 0 if from slots 0 or 1.                                        */
1242       __IOM uint32_t HGDATAPR   : 12;           /*!< [31..20] High-gain PGA sample data                                        */
1243     } FIFOPR_b;
1244   } ;
1245 
1246   union {
1247     __IOM uint32_t INTTRIGTIMER;                /*!< (@ 0x00000040) AUDADC-Internal Repeating Trigger Timer Configuration      */
1248 
1249     struct {
1250       __IOM uint32_t TIMERMAX   : 10;           /*!< [9..0] Trigger counter count max, used as initial condition
1251                                                      to trigger. Also used repeatedly each time counter reaches
1252                                                      it to restart trigger timer at zero. To update this value,
1253                                                      first disable the INTTRIGTIMER by setting TIMEREN to DIS,
1254                                                      change TIMERMAX, and then reenable it INTTRIGTIMER by setting
1255                                                      TIMEREN to EN again.                                                      */
1256             uint32_t            : 6;
1257       __IOM uint32_t CLKDIV     : 3;            /*!< [18..16] Configure number of divide-by-2 of clock source as
1258                                                      input to trigger counter. (Max value of 5.) A value of
1259                                                      0 in this register would not divide down the AUDADC input
1260                                                      clock. A value of 1 would divide the AUDADC input clock
1261                                                      frequency by 2. A value of 5 would divide the AUDADC input
1262                                                      clock frequency by 2^5 = 32. To update this value, first
1263                                                      disable the INTTRIGTIMER by setting TIMEREN to DIS, change
1264                                                      CLKDIV, and then reenable it INTTRIGTIMER by setting TIMEREN
1265                                                      to EN again.                                                              */
1266             uint32_t            : 12;
1267       __IOM uint32_t TIMEREN    : 1;            /*!< [31..31] AUDADC-internal trigger timer enable.                            */
1268     } INTTRIGTIMER_b;
1269   } ;
1270 
1271   union {
1272     __IOM uint32_t FIFOSTAT;                    /*!< (@ 0x00000044) This register contains status of the data FIFO.            */
1273 
1274     struct {
1275       __IOM uint32_t FIFOCNT    : 8;            /*!< [7..0] Number of valid entries in the AUDADC FIFO.                        */
1276             uint32_t            : 24;
1277     } FIFOSTAT_b;
1278   } ;
1279 
1280   union {
1281     __IOM uint32_t DATAOFFSET;                  /*!< (@ 0x00000048) ERROR: reg_brief VALUE MISSING                             */
1282 
1283     struct {
1284       __IOM uint32_t OFFSET     : 13;           /*!< [12..0] Add this signed offset to data before being written
1285                                                      to the FIFO. This enables the user to convert unsigned
1286                                                      samples to signed or remove a DC offset on the samples.
1287                                                      Note that this does NOT affect the comparator limits, which
1288                                                      still operate on original unsigned samples.                               */
1289             uint32_t            : 19;
1290     } DATAOFFSET_b;
1291   } ;
1292   __IM  uint32_t  RESERVED[5];
1293 
1294   union {
1295     __IOM uint32_t ZXCFG;                       /*!< (@ 0x00000060) Zero Crossing Comparator Configuration                     */
1296 
1297     struct {
1298       __IOM uint32_t ZXEN       : 1;            /*!< [0..0] Enable the ZX comparator                                           */
1299             uint32_t            : 3;
1300       __IOM uint32_t ZXCHANSEL  : 1;            /*!< [4..4] Select which slots to use for zero crossing measurement.
1301                                                      0 enables zero crossing detection on slots 0 and 2. 1 enables
1302                                                      zero crossing detection on slots 1 and 3.                                 */
1303             uint32_t            : 27;
1304     } ZXCFG_b;
1305   } ;
1306 
1307   union {
1308     __IOM uint32_t ZXLIM;                       /*!< (@ 0x00000064) Zero Crossing Comparator Limits                            */
1309 
1310     struct {
1311       __IOM uint32_t LZXC       : 12;           /*!< [11..0] Sets the lower integer sample limit for the ZX comparator.
1312                                                      Note that these values are raw AUDADC values whose bounds
1313                                                      are specified by PRMODE but not maniupulated by accumulate/divide
1314                                                      logic. Therefore, there is no oversampling and no binary
1315                                                      point in this value. Samples must enter the range between
1316                                                      UZXC and LZXC in order for a zero crossing to be recognized.              */
1317             uint32_t            : 4;
1318       __IOM uint32_t UZXC       : 12;           /*!< [27..16] Sets the upper integer sample limit for the ZX comparator.
1319                                                      Note that these values are raw AUDADC values whose bounds
1320                                                      are specified by PRMODE but not maniupulated by accumulate/divide
1321                                                      logic. Therefore, there is no oversampling and no binary
1322                                                      point in this value. Samples must enter the range between
1323                                                      UZXC and LZXC in order for a zero crossing to be recognized.              */
1324             uint32_t            : 4;
1325     } ZXLIM_b;
1326   } ;
1327 
1328   union {
1329     __IOM uint32_t GAINCFG;                     /*!< (@ 0x00000068) PGA Gain Configuration                                     */
1330 
1331     struct {
1332       __IOM uint32_t PGACTRLEN  : 1;            /*!< [0..0] Enable PGA gain updates.                                           */
1333             uint32_t            : 3;
1334       __IOM uint32_t UPDATEMODE : 1;            /*!< [4..4] PGA update mode                                                    */
1335             uint32_t            : 27;
1336     } GAINCFG_b;
1337   } ;
1338 
1339   union {
1340     __IOM uint32_t GAIN;                        /*!< (@ 0x0000006C) PGA Gain Codes                                             */
1341 
1342     struct {
1343       __IOM uint32_t LGA        : 7;            /*!< [6..0] Specifies the low gain code (0 to 60 decimal specifies
1344                                                      -6.0 dB to 24.0 dB in half-dB increments) for channel A
1345                                                      (slot 0).                                                                 */
1346             uint32_t            : 1;
1347       __IOM uint32_t HGADELTA   : 7;            /*!< [14..8] Specifies the high gain code (0 to 60 decimal specifies
1348                                                      0 dB to 30.0 dB in half-dB increments) as the delta from
1349                                                      the LGA field for channel A (slot 1). Note that HGADELTA
1350                                                      must be LE (24 - LGA) dB.                                                 */
1351             uint32_t            : 1;
1352       __IOM uint32_t LGB        : 7;            /*!< [22..16] Specifies the low gain code (0 to 60 decimal specifies
1353                                                      -6.0 dB to 24.0 dB in half-dB increments) for channel B
1354                                                      (slot 2).                                                                 */
1355             uint32_t            : 1;
1356       __IOM uint32_t HGBDELTA   : 7;            /*!< [30..24] Specifies the high gain code (0 to 60 decimal specifies
1357                                                      0 dB to 30.0 dB in half-dB increments) as the delta from
1358                                                      the LGB field for channel B (slot 3). Note that HGBDELTA
1359                                                      must be LE (24 - LGB) dB.                                                 */
1360             uint32_t            : 1;
1361     } GAIN_b;
1362   } ;
1363   __IM  uint32_t  RESERVED1[13];
1364 
1365   union {
1366     __IOM uint32_t SATCFG;                      /*!< (@ 0x000000A4) Saturation Comparator Configuration                        */
1367 
1368     struct {
1369       __IOM uint32_t SATEN      : 1;            /*!< [0..0] Enable the saturation comparator                                   */
1370             uint32_t            : 3;
1371       __IOM uint32_t SATCHANSEL : 1;            /*!< [4..4] Select which slots to use for saturation measurement.
1372                                                      0 enables saturation on slots 0 and 2. 1 enables saturation
1373                                                      on slots 1 and 3.                                                         */
1374             uint32_t            : 27;
1375     } SATCFG_b;
1376   } ;
1377 
1378   union {
1379     __IOM uint32_t SATLIM;                      /*!< (@ 0x000000A8) Saturation Comparator Limits                               */
1380 
1381     struct {
1382       __IOM uint32_t LSATC      : 12;           /*!< [11..0] Sets the lower integer sample limit for the saturation
1383                                                      comparator. Note that these values are raw AUDADC values
1384                                                      whose bounds are specified by PRMODE but not manipulated
1385                                                      by accumulate/divide logic. Therefore, there is no oversampling
1386                                                      and no binary point in this value.                                        */
1387             uint32_t            : 4;
1388       __IOM uint32_t USATC      : 12;           /*!< [27..16] Sets the upper integer sample limit for the saturation
1389                                                      comparator. Note that these values are raw AUDADC values
1390                                                      whose bounds are specified by PRMODE but not manipulated
1391                                                      by accumulate/divide logic. Therefore, there is no oversampling
1392                                                      and no binary point in this value.                                        */
1393             uint32_t            : 4;
1394     } SATLIM_b;
1395   } ;
1396 
1397   union {
1398     __IOM uint32_t SATMAX;                      /*!< (@ 0x000000AC) Saturation Comparator Event Counter Limits                 */
1399 
1400     struct {
1401       __IOM uint32_t SATCAMAX   : 12;           /*!< [11..0] Sets the number of saturation events that may occur
1402                                                      before a SATCA interrupt occurs. Once this interrupt occurs,
1403                                                      the saturation event counter must be cleared by writing
1404                                                      the SATCLR register. A value of 0 is invalid and will cause
1405                                                      the saturation interrupt to assert immediately.                           */
1406             uint32_t            : 4;
1407       __IOM uint32_t SATCBMAX   : 12;           /*!< [27..16] Sets the number of saturation events that may occur
1408                                                      before a SATCB interrupt occurs. Once this interrupt occurs,
1409                                                      the saturation event counter must be cleared by writing
1410                                                      the SATCLR register. A value of 0 is invalid and will cause
1411                                                      the saturation interrupt to assert immediately.                           */
1412             uint32_t            : 4;
1413     } SATMAX_b;
1414   } ;
1415 
1416   union {
1417     __IOM uint32_t SATCLR;                      /*!< (@ 0x000000B0) Clears the saturation event counter registers              */
1418 
1419     struct {
1420       __IOM uint32_t SATCACLR   : 1;            /*!< [0..0] Clear saturation event counter register for channel A
1421                                                      (slots 0 or 1, depending on SATCHANSEL)                                   */
1422       __IOM uint32_t SATCBCLR   : 1;            /*!< [1..1] Clear saturation event counter register for channel B
1423                                                      (slots 2 or 3, depending on SATCHANSEL)                                   */
1424             uint32_t            : 30;
1425     } SATCLR_b;
1426   } ;
1427   __IM  uint32_t  RESERVED2[83];
1428 
1429   union {
1430     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
1431                                                                     to generate the corresponding interrupt.                   */
1432 
1433     struct {
1434       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] AUDADC conversion complete interrupt.                              */
1435       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] AUDADC scan complete interrupt.                                    */
1436       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
1437       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
1438       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
1439       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
1440       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
1441       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
1442       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
1443       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
1444       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
1445       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
1446             uint32_t            : 20;
1447     } INTEN_b;
1448   } ;
1449 
1450   union {
1451     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
1452                                                                     cause of a recent interrupt.                               */
1453 
1454     struct {
1455       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] AUDADC conversion complete interrupt.                              */
1456       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] AUDADC scan complete interrupt.                                    */
1457       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
1458       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
1459       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
1460       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
1461       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
1462       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
1463       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
1464       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
1465       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
1466       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
1467             uint32_t            : 20;
1468     } INTSTAT_b;
1469   } ;
1470 
1471   union {
1472     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
1473                                                                     the interrupt status associated with that
1474                                                                     bit.                                                       */
1475 
1476     struct {
1477       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] AUDADC conversion complete interrupt.                              */
1478       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] AUDADC scan complete interrupt.                                    */
1479       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
1480       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
1481       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
1482       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
1483       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
1484       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
1485       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
1486       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
1487       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
1488       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
1489             uint32_t            : 20;
1490     } INTCLR_b;
1491   } ;
1492 
1493   union {
1494     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
1495                                                                     generate an interrupt from this module.
1496                                                                     (Generally used for testing purposes).                     */
1497 
1498     struct {
1499       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] AUDADC conversion complete interrupt.                              */
1500       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] AUDADC scan complete interrupt.                                    */
1501       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
1502       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
1503       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
1504       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
1505       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
1506       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
1507       __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
1508       __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
1509       __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
1510       __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
1511             uint32_t            : 20;
1512     } INTSET_b;
1513   } ;
1514   __IM  uint32_t  RESERVED3[12];
1515 
1516   union {
1517     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) DMA Trigger Enable                                         */
1518 
1519     struct {
1520       __IOM uint32_t DFIFO75    : 1;            /*!< [0..0] Trigger DMA upon FIFO 75 percent Full                              */
1521       __IOM uint32_t DFIFOFULL  : 1;            /*!< [1..1] Trigger DMA upon FIFO 100 percent Full                             */
1522             uint32_t            : 30;
1523     } DMATRIGEN_b;
1524   } ;
1525 
1526   union {
1527     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) DMA Trigger Status                                         */
1528 
1529     struct {
1530       __IOM uint32_t D75STAT    : 1;            /*!< [0..0] Triggered DMA from FIFO 75 percent Full                            */
1531       __IOM uint32_t DFULLSTAT  : 1;            /*!< [1..1] Triggered DMA from FIFO 100 percent Full                           */
1532             uint32_t            : 30;
1533     } DMATRIGSTAT_b;
1534   } ;
1535   __IM  uint32_t  RESERVED4[14];
1536 
1537   union {
1538     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) DMA Configuration                                          */
1539 
1540     struct {
1541       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
1542             uint32_t            : 1;
1543       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
1544             uint32_t            : 5;
1545       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
1546       __IOM uint32_t DMADYNPRI  : 1;            /*!< [9..9] Enables dynamic priority based on FIFO fullness. When
1547                                                      FIFO is full, priority is automatically set to HIGH. Otherwise,
1548                                                      DMAPRI is used.                                                           */
1549             uint32_t            : 8;
1550       __IOM uint32_t DPWROFF    : 1;            /*!< [18..18] Power Off the AUDADC System upon DMACPL.                         */
1551             uint32_t            : 13;
1552     } DMACFG_b;
1553   } ;
1554   __IM  uint32_t  RESERVED5;
1555 
1556   union {
1557     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) DMA Total Transfer Count                                   */
1558 
1559     struct {
1560             uint32_t            : 2;
1561       __IOM uint32_t TOTCOUNT   : 16;           /*!< [17..2] Total Transfer Count                                              */
1562             uint32_t            : 14;
1563     } DMATOTCOUNT_b;
1564   } ;
1565 
1566   union {
1567     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) DMA Target Address                                         */
1568 
1569     struct {
1570       __IOM uint32_t LTARGADDR  : 28;           /*!< [27..0] DMA Target Address                                                */
1571       __IOM uint32_t UTARGADDR  : 4;            /*!< [31..28] SRAM Target                                                      */
1572     } DMATARGADDR_b;
1573   } ;
1574 
1575   union {
1576     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) DMA Status                                                 */
1577 
1578     struct {
1579       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
1580       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
1581       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
1582             uint32_t            : 29;
1583     } DMASTAT_b;
1584   } ;
1585 } AUDADC_Type;                                  /*!< Size = 660 (0x294)                                                        */
1586 
1587 
1588 
1589 /* =========================================================================================================================== */
1590 /* ================                                          CLKGEN                                           ================ */
1591 /* =========================================================================================================================== */
1592 
1593 
1594 /**
1595   * @brief Clock Generator (CLKGEN)
1596   */
1597 
1598 typedef struct {                                /*!< (@ 0x40004000) CLKGEN Structure                                           */
1599   __IM  uint32_t  RESERVED[3];
1600 
1601   union {
1602     __IOM uint32_t OCTRL;                       /*!< (@ 0x0000000C) This register includes controls for autocalibration
1603                                                                     in addition to the RTC oscillator controls.                */
1604 
1605     struct {
1606             uint32_t            : 7;
1607       __IOM uint32_t OSEL       : 1;            /*!< [7..7] Selects the RTC oscillator (1=LFRC, 0=XT)This selection
1608                                                      bit and clocking the RTC with the external crystal (XT)
1609                                                      are inoperable in silicon revisions A and B0.                             */
1610             uint32_t            : 24;
1611     } OCTRL_b;
1612   } ;
1613 
1614   union {
1615     __IOM uint32_t CLKOUT;                      /*!< (@ 0x00000010) This register enables the CLKOUT to the GPIOs,
1616                                                                     and selects the clock source to that.                      */
1617 
1618     struct {
1619       __IOM uint32_t CKSEL      : 6;            /*!< [5..0] CLKOUT signal select                                               */
1620             uint32_t            : 1;
1621       __IOM uint32_t CKEN       : 1;            /*!< [7..7] Enable the CLKOUT signal                                           */
1622             uint32_t            : 24;
1623     } CLKOUT_b;
1624   } ;
1625   __IM  uint32_t  RESERVED1[3];
1626 
1627   union {
1628     __IOM uint32_t HFADJ;                       /*!< (@ 0x00000020) This register controls the HFRC adjustment. The
1629                                                                     HFRC clock can change with temperature and
1630                                                                     process corners, and this register controls
1631                                                                     the HFRC adjustment logic which reduces
1632                                                                     the fluctuations to the clock.                             */
1633 
1634     struct {
1635       __IOM uint32_t HFADJEN    : 1;            /*!< [0..0] HFRC adjustment control                                            */
1636       __IOM uint32_t HFADJCK    : 3;            /*!< [3..1] Repeat period for HFRC adjustment                                  */
1637             uint32_t            : 4;
1638       __IOM uint32_t HFXTADJ    : 12;           /*!< [19..8] Target HFRC adjustment value.                                     */
1639       __IOM uint32_t HFWARMUP   : 1;            /*!< [20..20] XT warmup period for HFRC adjustment                             */
1640       __IOM uint32_t HFADJGAIN  : 3;            /*!< [23..21] Gain control for HFRC adjustment                                 */
1641       __IOM uint32_t HFADJMAXDELTA : 5;         /*!< [28..24] Maximum delta for HF Adjustments. 0=Disabled, 1-31=maximum
1642                                                      delta step                                                                */
1643             uint32_t            : 3;
1644     } HFADJ_b;
1645   } ;
1646   __IM  uint32_t  RESERVED2[3];
1647 
1648   union {
1649     __IOM uint32_t CLOCKENSTAT;                 /*!< (@ 0x00000030) This register provides the enable status to all
1650                                                                     the peripheral clocks.                                     */
1651 
1652     struct {
1653       __IOM uint32_t CLOCKENSTAT : 32;          /*!< [31..0] Clock enable status                                               */
1654     } CLOCKENSTAT_b;
1655   } ;
1656 
1657   union {
1658     __IOM uint32_t CLOCKEN2STAT;                /*!< (@ 0x00000034) This is a continuation of the clock enable status.         */
1659 
1660     struct {
1661       __IOM uint32_t CLOCKEN2STAT : 32;         /*!< [31..0] Clock enable status 2                                             */
1662     } CLOCKEN2STAT_b;
1663   } ;
1664 
1665   union {
1666     __IOM uint32_t CLOCKEN3STAT;                /*!< (@ 0x00000038) This is a continuation of the clock enable status.         */
1667 
1668     struct {
1669       __IOM uint32_t CLOCKEN3STAT : 32;         /*!< [31..0] Clock enable status 3                                             */
1670     } CLOCKEN3STAT_b;
1671   } ;
1672   __IM  uint32_t  RESERVED3[2];
1673 
1674   union {
1675     __IOM uint32_t MISC;                        /*!< (@ 0x00000044) This register controls a 'safe' mode for burst,
1676                                                                     which disables the clock when burst transition
1677                                                                     is happening. It also includes a register
1678                                                                     to force the HFRC during deep sleep. It
1679                                                                     is mainly used for debug and testing.                      */
1680 
1681     struct {
1682       __IOM uint32_t FRCHFRC    : 1;            /*!< [0..0] Force HFRC On .                                                    */
1683       __IOM uint32_t FRCBURSTOFF : 1;           /*!< [1..1] Force fclk, hclk, fclk_wic and fclk_pmu to be turned
1684                                                      off during burst transition.                                              */
1685       __IOM uint32_t USEHFRC2FQ48MHZ : 1;       /*!< [2..2] Use HFRC-48MHz or HFRC2-48MHz for DSP                              */
1686       __IOM uint32_t USEHFRC2FQ96MHZ : 1;       /*!< [3..3] Use HFRC-96MHz or HFRC2-96MHz for DSP                              */
1687       __IOM uint32_t USEHFRC2FQ192MHZ : 1;      /*!< [4..4] Use HFRC-192MHz or HFRC2-192MHz for MCU                            */
1688       __IOM uint32_t FRCHFRC2   : 1;            /*!< [5..5] Force HFRC2 On.Setting this bit forces HFRC2 to remain
1689                                                      on, including in deep sleep. When changing a module's clock
1690                                                      source to HFRC2, this bit must be set and remain set when
1691                                                      any module is using HFRC2 as its clock.                                   */
1692       __IOM uint32_t PWRONCLKENDISP : 1;        /*!< [6..6] Chicken bit to disable Rev B clock enable during reset             */
1693       __IOM uint32_t PWRONCLKENDISPPHY : 1;     /*!< [7..7] Chicken bit to disable Rev B clock enable during reset             */
1694       __IOM uint32_t PWRONCLKENGFX : 1;         /*!< [8..8] Chicken bit to disable Rev B clock enable during reset             */
1695       __IOM uint32_t PWRONCLKENUSB : 1;         /*!< [9..9] Chicken bit to disable Rev B clock enable during reset             */
1696       __IOM uint32_t PWRONCLKENSDIO : 1;        /*!< [10..10] Chicken bit to disable Rev B clock enable during reset           */
1697       __IOM uint32_t PWRONCLKENCRYPTO : 1;      /*!< [11..11] Chicken bit to disable Rev B clock enable during reset           */
1698       __IOM uint32_t PWRONCLKENI2S0 : 1;        /*!< [12..12] Chicken bit to disable Rev B clock enable during reset           */
1699       __IOM uint32_t PWRONCLKENI2S1 : 1;        /*!< [13..13] Chicken bit to disable Rev B clock enable during reset           */
1700       __IOM uint32_t AXIXACLKENOVRRIDE : 1;     /*!< [14..14] Chicken bit to disable Rev B added clock gating                  */
1701       __IOM uint32_t PWRONCLKENI2S0REFCLK : 1;  /*!< [15..15] Chicken bit to disable Rev B clock enable during reset           */
1702       __IOM uint32_t PWRONCLKENI2S1REFCLK : 1;  /*!< [16..16] Chicken bit to disable Rev B clock enable during reset           */
1703       __IOM uint32_t PWRONCLKENUSBREFCLK : 1;   /*!< [17..17] Chicken bit to disable Rev B clock enable during reset           */
1704       __IOM uint32_t CM4DAXICLKGATEEN : 1;      /*!< [18..18] Chicken bit to enable clock gating on CM4 DAXI CLK               */
1705       __IOM uint32_t GFXCLKCLKGATEEN : 1;       /*!< [19..19] Chicken bit to enable clock gating on GFX CLK                    */
1706       __IOM uint32_t GFXAXICLKCLKGATEEN : 1;    /*!< [20..20] Chicken bit to enable clock gating on GFX AXI CLK                */
1707       __IOM uint32_t APBDMACPUCLKCLKGATEEN : 1; /*!< [21..21] Chicken bit to enable clock gating on APB DMA CPU CLK            */
1708       __IOM uint32_t ETMTRACECLKCLKGATEEN : 1;  /*!< [22..22] Chicken bit to enable clock gating on ETM TRACE CLK              */
1709       __IOM uint32_t HFRCFUNCCLKGATEEN : 1;     /*!< [23..23] Chicken bit to enable clock gating on HFRC_FUNC_CLK              */
1710       __IOM uint32_t HFRC96TRUNKGATE : 1;       /*!< [24..24] DO NOT USE. HFRC96_TRUNK_GATE. Setting this bit when
1711                                                      BIT23=0, will kill HFRC root clock.                                       */
1712       __IOM uint32_t CLKGENMISCSPARE : 1;       /*!< [25..25] Spare/Unused Chicken Bit                                         */
1713             uint32_t            : 6;
1714     } MISC_b;
1715   } ;
1716 
1717   union {
1718     __IOM uint32_t HF2ADJ0;                     /*!< (@ 0x00000048) This register controls hf2adj enable, fast_start
1719                                                                     enable, fast_start_delay setting and counter
1720                                                                     input offset.                                              */
1721 
1722     struct {
1723       __IOM uint32_t HF2ADJEN   : 1;            /*!< [0..0] HF2ADJ control                                                     */
1724       __IOM uint32_t HF2ADJFASTSTREN : 1;       /*!< [1..1] Fast_start_delay control                                           */
1725       __IOM uint32_t HF2ADJFASTSTRDLY : 13;     /*!< [14..2] Fast_start_delay value setting                                    */
1726       __IOM uint32_t HF2ADJCNTINOFFSET : 14;    /*!< [28..15] Counter input offset                                             */
1727       __IOM uint32_t HF2ADJXTHSMUXSEL : 1;      /*!< [29..29] 0=XTHS 1=EXTREF select                                           */
1728             uint32_t            : 2;
1729     } HF2ADJ0_b;
1730   } ;
1731 
1732   union {
1733     __IOM uint32_t HF2ADJ1;                     /*!< (@ 0x0000004C) This register controls hf2adj trimming enable
1734                                                                     and trimming offset.                                       */
1735 
1736     struct {
1737       __IOM uint32_t HF2ADJTRIMEN : 3;          /*!< [2..0] HF2ADJ output selection                                            */
1738       __IOM uint32_t HF2ADJTRIMOFFSET : 11;     /*!< [13..3] HF2ADJ trimming offset. (signed number)                           */
1739             uint32_t            : 18;
1740     } HF2ADJ1_b;
1741   } ;
1742 
1743   union {
1744     __IOM uint32_t HF2ADJ2;                     /*!< (@ 0x00000050) This register controls xtal32m divider ratio
1745                                                                     and HF2ADJ ration setting.                                 */
1746 
1747     struct {
1748       __IOM uint32_t HF2ADJXTALDIVRATIO : 2;    /*!< [1..0] XTAL32MHz divider ratio for HF2ADJ.                                */
1749       __IOM uint32_t HF2ADJRATIO : 29;          /*!< [30..2] HF2ADJ ratio setting.                                             */
1750             uint32_t            : 1;
1751     } HF2ADJ2_b;
1752   } ;
1753 
1754   union {
1755     __IOM uint32_t HF2VAL;                      /*!< (@ 0x00000054) This register provides the read back of the HF2TUNE        */
1756 
1757     struct {
1758       __IOM uint32_t HF2ADJTRIMOUT : 11;        /*!< [10..0] HF2ADJ trimming output                                            */
1759             uint32_t            : 21;
1760     } HF2VAL_b;
1761   } ;
1762   __IM  uint32_t  RESERVED4[8];
1763 
1764   union {
1765     __IOM uint32_t LFRCCTRL;                    /*!< (@ 0x00000078) LFRC control                                               */
1766 
1767     struct {
1768       __IOM uint32_t LFRCOUT    : 1;            /*!< [0..0] Disable LFRC output                                                */
1769       __IOM uint32_t LFRCPWD    : 1;            /*!< [1..1] Power down LFRC                                                    */
1770             uint32_t            : 30;
1771     } LFRCCTRL_b;
1772   } ;
1773   __IM  uint32_t  RESERVED5[2];
1774 
1775   union {
1776     __IOM uint32_t DISPCLKCTRL;                 /*!< (@ 0x00000084) Provides ability to select the PLL reference
1777                                                                     clock, and derivative of the display clock                 */
1778 
1779     struct {
1780       __IOM uint32_t PLLCLKSEL  : 2;            /*!< [1..0] Selection for PLL reference clock.                                 */
1781             uint32_t            : 1;
1782       __IOM uint32_t PLLCLKEN   : 1;            /*!< [3..3] Enable for the PLL clock through clkgen                            */
1783       __IOM uint32_t DISPCLKSEL : 2;            /*!< [5..4] Selection for PLL reference clock.                                 */
1784             uint32_t            : 1;
1785       __IOM uint32_t DCCLKEN    : 1;            /*!< [7..7] Enable for the PLL clock through clkgen                            */
1786             uint32_t            : 24;
1787     } DISPCLKCTRL_b;
1788   } ;
1789 
1790   union {
1791     __IOM uint32_t CLKGENSPARES;                /*!< (@ 0x00000088) CLKGEN Spare Regs                                          */
1792 
1793     struct {
1794       __IOM uint32_t CLKGENSPARES : 32;         /*!< [31..0] Placeholer spare registes that can be used as needed
1795                                                      for future use                                                            */
1796     } CLKGENSPARES_b;
1797   } ;
1798 
1799   union {
1800     __IOM uint32_t HFRCIDLECOUNTERS;            /*!< (@ 0x0000008C) Provides SW controlled # idle cycles before powering
1801                                                                     down HFRC, HFRC2., core clock enable(s)                    */
1802 
1803     struct {
1804       __IOM uint32_t HFRCPWRDOWNDELAY : 6;      /*!< [5..0] Idle counter for HFRC POWER DOWN DELAY                             */
1805             uint32_t            : 2;
1806       __IOM uint32_t HFRCCLKREQDELAY : 6;       /*!< [13..8] Idle counter for HFRC CLK REQ DELAY                               */
1807             uint32_t            : 2;
1808       __IOM uint32_t HFRC2PWRDOWNDELAY : 6;     /*!< [21..16] Idle counter for HFRC2 POWER DOWN DELAY                          */
1809             uint32_t            : 2;
1810       __IOM uint32_t HFRC2CLKREQDELAY : 6;      /*!< [29..24] Enable for the PLL clock through clkgen                          */
1811             uint32_t            : 1;
1812       __IOM uint32_t UPDATEENABLE : 1;          /*!< [31..31] usage : Clear UPDATEENABLE or 1'b0; Update other bits
1813                                                      fields of this register. Set this register to 1'b1 for
1814                                                      HW to update.                                                             */
1815     } HFRCIDLECOUNTERS_b;
1816   } ;
1817   __IM  uint32_t  RESERVED6[28];
1818 
1819   union {
1820     __IOM uint32_t INTRPTEN;                    /*!< (@ 0x00000100) Set bits in this register to allow this module
1821                                                                     to generate the corresponding interrupt.                   */
1822 
1823     struct {
1824       __IOM uint32_t OF         : 1;            /*!< [0..0] XT Oscillator Fail interrupt                                       */
1825             uint32_t            : 31;
1826     } INTRPTEN_b;
1827   } ;
1828 
1829   union {
1830     __IOM uint32_t INTRPTSTAT;                  /*!< (@ 0x00000104) Read bits from this register to discover the
1831                                                                     cause of a recent interrupt.                               */
1832 
1833     struct {
1834       __IOM uint32_t OF         : 1;            /*!< [0..0] XT Oscillator Fail interrupt                                       */
1835             uint32_t            : 31;
1836     } INTRPTSTAT_b;
1837   } ;
1838 
1839   union {
1840     __IOM uint32_t INTRPTCLR;                   /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
1841                                                                     the interrupt status associated with that
1842                                                                     bit.                                                       */
1843 
1844     struct {
1845       __IOM uint32_t OF         : 1;            /*!< [0..0] XT Oscillator Fail interrupt                                       */
1846             uint32_t            : 31;
1847     } INTRPTCLR_b;
1848   } ;
1849 
1850   union {
1851     __IOM uint32_t INTRPTSET;                   /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
1852                                                                     generate an interrupt from this module.
1853                                                                     (Generally used for testing purposes).                     */
1854 
1855     struct {
1856       __IOM uint32_t OF         : 1;            /*!< [0..0] XT Oscillator Fail interrupt                                       */
1857             uint32_t            : 31;
1858     } INTRPTSET_b;
1859   } ;
1860 } CLKGEN_Type;                                  /*!< Size = 272 (0x110)                                                        */
1861 
1862 
1863 
1864 /* =========================================================================================================================== */
1865 /* ================                                            CPU                                            ================ */
1866 /* =========================================================================================================================== */
1867 
1868 
1869 /**
1870   * @brief CM4 Complex Registers (Cache, TCM, DAXI) (CPU)
1871   */
1872 
1873 typedef struct {                                /*!< (@ 0x48000000) CPU Structure                                              */
1874 
1875   union {
1876     __IOM uint32_t CACHECFG;                    /*!< (@ 0x00000000) CM4 Cache Control                                          */
1877 
1878     struct {
1879       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Enables the CM4 cache controller and enables power to
1880                                                      the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should
1881                                                      be set to enable caching for each type of access.                         */
1882       __IOM uint32_t LRU        : 1;            /*!< [1..1] Sets the cache repleacment policy. 0=LRR (least recently
1883                                                      replaced), 1=LRU (least recently used). LRR minimizes writes
1884                                                      to the TAG SRAM.                                                          */
1885       __IOM uint32_t NC0ENABLE  : 1;            /*!< [2..2] Enable Non-cacheable region 0. See NCR0 registers to
1886                                                      define the region.                                                        */
1887       __IOM uint32_t NC1ENABLE  : 1;            /*!< [3..3] Enable Non-cacheable region 1. See NCR1 registers to
1888                                                      define the region.                                                        */
1889       __IOM uint32_t CONFIG     : 4;            /*!< [7..4] Sets the cache configuration                                       */
1890       __IOM uint32_t IENABLE    : 1;            /*!< [8..8] Enable CM4 Instruction Caching                                     */
1891       __IOM uint32_t DENABLE    : 1;            /*!< [9..9] Enable CM4 Data Caching.                                           */
1892       __IOM uint32_t CLKGATE    : 1;            /*!< [10..10] Enable clock gating of cache TAG RAM. Software should
1893                                                      enable this bit for optimal power efficiency.                             */
1894       __IOM uint32_t LS         : 1;            /*!< [11..11] Enable LS (light sleep) of cache RAMs. Software should
1895                                                      DISABLE this bit since cache activity is too high to benefit
1896                                                      from LS usage.                                                            */
1897       __IOM uint32_t NC1CACHELOCK : 1;          /*!< [12..12] Only valid when Cache Mode D is set. When high sets
1898                                                      the mode of the the NC1 region such that all accesse to
1899                                                      this region are cached in to the upper half of the cache.
1900                                                      When set low then NCR1 is non cacheable.                                  */
1901       __IOM uint32_t NC0CACHELOCK : 1;          /*!< [13..13] Only valid when Cache Mode D is set. When high sets
1902                                                      the mode of the the NC0 region such that all accesse to
1903                                                      this region are cached in to the lower half of the cache.
1904                                                      When set low then NCR0 is non cacheable.                                  */
1905             uint32_t            : 6;
1906       __IOM uint32_t DATACLKGATE : 1;           /*!< [20..20] Enable aggressive clock gating of entire data array.
1907                                                      This bit should be set to 1 for optimal power efficiency.                 */
1908             uint32_t            : 3;
1909       __IOM uint32_t ENABLEMONITOR : 1;         /*!< [24..24] Enable Cache Monitoring Stats. Cache monitoring consumes
1910                                                      additional power and should only be enabled when profiling
1911                                                      code and counters will increment when this bit is set.
1912                                                      Counter values will be retained when this is set to 0,
1913                                                      allowing software to enable/disable counting for multiple
1914                                                      code segments.                                                            */
1915             uint32_t            : 7;
1916     } CACHECFG_b;
1917   } ;
1918   __IM  uint32_t  RESERVED;
1919 
1920   union {
1921     __IOM uint32_t CACHECTRL;                   /*!< (@ 0x00000008) Cache Control                                              */
1922 
1923     struct {
1924       __IOM uint32_t INVALIDATE : 1;            /*!< [0..0] Writing a 1 to this bitfield invalidates the CM4 cache
1925                                                      contents.                                                                 */
1926       __IOM uint32_t RESETSTAT  : 1;            /*!< [1..1] Reset Cache Statistics. When written to a 1, the cache
1927                                                      monitor counters will be cleared. The monitor counters
1928                                                      can be reset only when the CACHECFG.ENABLE_MONITOR bit
1929                                                      is set.                                                                   */
1930       __IOM uint32_t CACHEREADY : 1;            /*!< [2..2] Cache Ready Status (enabled and not processing an invalidate
1931                                                      operation)                                                                */
1932             uint32_t            : 29;
1933     } CACHECTRL_b;
1934   } ;
1935   __IM  uint32_t  RESERVED1;
1936 
1937   union {
1938     __IOM uint32_t NCR0START;                   /*!< (@ 0x00000010) CM4 Cache Noncachable Region 0 Start                       */
1939 
1940     struct {
1941             uint32_t            : 4;
1942       __IOM uint32_t ADDR       : 25;           /*!< [28..4] Start address for non-cacheable region 0                          */
1943             uint32_t            : 3;
1944     } NCR0START_b;
1945   } ;
1946 
1947   union {
1948     __IOM uint32_t NCR0END;                     /*!< (@ 0x00000014) CM4 Cache Noncachable Region 0 End                         */
1949 
1950     struct {
1951             uint32_t            : 4;
1952       __IOM uint32_t ADDR       : 25;           /*!< [28..4] End address for non-cacheable region 0                            */
1953             uint32_t            : 3;
1954     } NCR0END_b;
1955   } ;
1956 
1957   union {
1958     __IOM uint32_t NCR1START;                   /*!< (@ 0x00000018) CM4 Cache Noncachable Region 1 Start                       */
1959 
1960     struct {
1961             uint32_t            : 4;
1962       __IOM uint32_t ADDR       : 25;           /*!< [28..4] Start address for non-cacheable region 1                          */
1963             uint32_t            : 3;
1964     } NCR1START_b;
1965   } ;
1966 
1967   union {
1968     __IOM uint32_t NCR1END;                     /*!< (@ 0x0000001C) CM4 Cache Noncachable Region 1 End                         */
1969 
1970     struct {
1971             uint32_t            : 4;
1972       __IOM uint32_t ADDR       : 25;           /*!< [28..4] End address for non-cacheable region 1                            */
1973             uint32_t            : 3;
1974     } NCR1END_b;
1975   } ;
1976   __IM  uint32_t  RESERVED2[12];
1977 
1978   union {
1979     __IOM uint32_t DAXICFG;                     /*!< (@ 0x00000050) DAXI Config                                                */
1980 
1981     struct {
1982       __IOM uint32_t FLUSHLEVEL : 1;            /*!< [0..0] Level of free buffers to flush out dirty buffers.                  */
1983       __IOM uint32_t AGINGSENABLE : 1;          /*!< [1..1] Enables flushing out shared lines using the aging mechanism.       */
1984       __IOM uint32_t DAXIPASSTHROUGH : 1;       /*!< [2..2] Passes requests through DAXI logic, disables caching
1985                                                      lines in the DAXI line buffers.                                           */
1986       __IOM uint32_t DAXIBECLKGATEEN : 1;       /*!< [3..3] Enables clock gating of DAXI line buffer byte enables.             */
1987       __IOM uint32_t DAXIDATACLKGATEEN : 1;     /*!< [4..4] Enables clock gating of DAXI line buffer data.                     */
1988       __IOM uint32_t DAXISTATECLKGATEEN : 1;    /*!< [5..5] Enables clock gating of DAXI state.                                */
1989             uint32_t            : 2;
1990       __IOM uint32_t BUFFERENABLE : 4;          /*!< [11..8] Enables DAXI buffers                                              */
1991             uint32_t            : 4;
1992       __IOM uint32_t AGINGCOUNTER : 5;          /*!< [20..16] Specifies the relative time that DAXI buffers may remain
1993                                                      unused before being flushed. Counter is based on CPU clock
1994                                                      cycles and buffers will generally be flushed in 1-2 AGINGCOUNTER
1995                                                      timesteps.                                                                */
1996             uint32_t            : 3;
1997       __IOM uint32_t MRUGROUPLEVEL : 2;         /*!< [25..24] Sets the MRU group population limit.                             */
1998             uint32_t            : 6;
1999     } DAXICFG_b;
2000   } ;
2001 
2002   union {
2003     __IOM uint32_t DAXICTRL;                    /*!< (@ 0x00000054) DAXI Control                                               */
2004 
2005     struct {
2006       __IOM uint32_t DAXIFLUSHWRITE : 1;        /*!< [0..0] Writing a 1 to this bitfield forces a flush of WRITE
2007                                                      (W->I) or MODIFIED buffers (M->S).                                        */
2008       __IOM uint32_t DAXIINVALIDATE : 1;        /*!< [1..1] Writing a 1 to this bitfield invalidates any SHARED data
2009                                                      buffers (S->I).                                                           */
2010       __IOM uint32_t DAXIREADY  : 1;            /*!< [2..2] DAXI Ready Status (enabled and not processing a flush
2011                                                      of WRITE or MODIFIED buffers)                                             */
2012       __IOM uint32_t DAXIBUSY   : 1;            /*!< [3..3] DAXI status indicating DAXI is busy.                               */
2013       __IOM uint32_t DAXIAHBBUSY : 1;           /*!< [4..4] DAXI status indicating DAXI AHB interface is busy.                 */
2014       __IOM uint32_t DAXISHARED : 1;            /*!< [5..5] DAXI status indicating at least one full buffer is shared.         */
2015       __IOM uint32_t DAXIMODIFIED : 1;          /*!< [6..6] DAXI status indicating at least one full buffer has modified
2016                                                      data.                                                                     */
2017       __IOM uint32_t DAXIWRITE  : 1;            /*!< [7..7] DAXI status indicating at least one partially written
2018                                                      buffer has modified data.                                                 */
2019       __IOM uint32_t DAXIWALLOC : 1;            /*!< [8..8] DAXI status indicating at least one write allocation
2020                                                      is waiting for prior store to complete.                                   */
2021       __IOM uint32_t DAXIWRLOAD : 1;            /*!< [9..9] DAXI status indicating at least one partially written
2022                                                      buffer is waiting for load to convert to modified.                        */
2023       __IOM uint32_t DAXISTORE  : 1;            /*!< [10..10] DAXI status indicating at least one buffer has outstanding
2024                                                      store waiting to complete.                                                */
2025       __IOM uint32_t DAXIBRESPPENDING : 1;      /*!< [11..11] DAXI status indicating at least one AXI B repsonse
2026                                                      for a store is pending.                                                   */
2027       __IOM uint32_t DAXIRAXIBUSY : 1;          /*!< [12..12] DAXI status indicating the DAXI RAXI interface is busy.          */
2028             uint32_t            : 19;
2029     } DAXICTRL_b;
2030   } ;
2031   __IM  uint32_t  RESERVED3[10];
2032 
2033   union {
2034     __IOM uint32_t ICODEFAULTADDR;              /*!< (@ 0x00000080) ICODE bus address which was present when a bus
2035                                                                     fault occurred.                                            */
2036 
2037     struct {
2038       __IOM uint32_t ICODEFAULTADDR : 32;       /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred.
2039                                                      Once an address is captured in this field, it is held until
2040                                                      the corresponding Fault Observed bit is cleared in the
2041                                                      FAULTSTATUS register.                                                     */
2042     } ICODEFAULTADDR_b;
2043   } ;
2044 
2045   union {
2046     __IOM uint32_t DCODEFAULTADDR;              /*!< (@ 0x00000084) DCODE bus address which was present when a bus
2047                                                                     fault occurred.                                            */
2048 
2049     struct {
2050       __IOM uint32_t DCODEFAULTADDR : 32;       /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred.
2051                                                      Once an address is captured in this field, it is held until
2052                                                      the corresponding Fault Observed bit is cleared in the
2053                                                      FAULTSTATUS register.                                                     */
2054     } DCODEFAULTADDR_b;
2055   } ;
2056 
2057   union {
2058     __IOM uint32_t SYSFAULTADDR;                /*!< (@ 0x00000088) System bus address which was present when a bus
2059                                                                     fault occurred.                                            */
2060 
2061     struct {
2062       __IOM uint32_t SYSFAULTADDR : 32;         /*!< [31..0] SYS bus address observed when a Bus Fault occurred.
2063                                                      Once an address is captured in this field, it is held until
2064                                                      the corresponding Fault Observed bit is cleared in the
2065                                                      FAULTSTATUS register.                                                     */
2066     } SYSFAULTADDR_b;
2067   } ;
2068 
2069   union {
2070     __IOM uint32_t FAULTSTATUS;                 /*!< (@ 0x0000008C) Reflects the status of the bus decoders' fault
2071                                                                     detection. Any write to this register will
2072                                                                     clear all of the status bits within the
2073                                                                     register.                                                  */
2074 
2075     struct {
2076       __IOM uint32_t ICODEFAULT : 1;            /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a
2077                                                      fault has been detected, and the ICODEFAULTADDR register
2078                                                      will contain the bus address which generated the fault.                   */
2079       __IOM uint32_t DCODEFAULT : 1;            /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault
2080                                                      has been detected, and the DCODEFAULTADDR register will
2081                                                      contain the bus address which generated the fault.                        */
2082       __IOM uint32_t SYSFAULT   : 1;            /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault
2083                                                      has been detected, and the SYSFAULTADDR register will contain
2084                                                      the bus address which generated the fault.                                */
2085             uint32_t            : 29;
2086     } FAULTSTATUS_b;
2087   } ;
2088 
2089   union {
2090     __IOM uint32_t FAULTCAPTUREEN;              /*!< (@ 0x00000090) Enable the fault capture registers                         */
2091 
2092     struct {
2093       __IOM uint32_t FAULTCAPTUREEN : 1;        /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture
2094                                                      monitors are enabled and addresses which generate a hard
2095                                                      fault are captured into the FAULTADDR registers.                          */
2096             uint32_t            : 31;
2097     } FAULTCAPTUREEN_b;
2098   } ;
2099   __IM  uint32_t  RESERVED4[11];
2100 
2101   union {
2102     __IOM uint32_t INTEN;                       /*!< (@ 0x000000C0) Set bits in this register to allow this module
2103                                                                     to generate the corresponding interrupt.                   */
2104 
2105     struct {
2106       __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
2107             uint32_t            : 31;
2108     } INTEN_b;
2109   } ;
2110 
2111   union {
2112     __IOM uint32_t INTSTAT;                     /*!< (@ 0x000000C4) Read bits from this register to discover the
2113                                                                     cause of a recent interrupt.                               */
2114 
2115     struct {
2116       __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
2117             uint32_t            : 31;
2118     } INTSTAT_b;
2119   } ;
2120 
2121   union {
2122     __IOM uint32_t INTCLR;                      /*!< (@ 0x000000C8) Write a 1 to a bit in this register to clear
2123                                                                     the interrupt status associated with that
2124                                                                     bit.                                                       */
2125 
2126     struct {
2127       __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
2128             uint32_t            : 31;
2129     } INTCLR_b;
2130   } ;
2131 
2132   union {
2133     __IOM uint32_t INTSET;                      /*!< (@ 0x000000CC) Write a 1 to a bit in this register to instantly
2134                                                                     generate an interrupt from this module.
2135                                                                     (Generally used for testing purposes).                     */
2136 
2137     struct {
2138       __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
2139             uint32_t            : 31;
2140     } INTSET_b;
2141   } ;
2142 
2143   union {
2144     __IOM uint32_t WRITEERRADDR;                /*!< (@ 0x000000D0) DAXI Write Error Address                                   */
2145 
2146     struct {
2147       __IOM uint32_t WERRADDR   : 32;           /*!< [31..0] This address will be approximate since multiple write
2148                                                      transactions might be in flight at any given time. However,
2149                                                      it should be accurate when debugging/single-stepping                      */
2150     } WRITEERRADDR_b;
2151   } ;
2152   __IM  uint32_t  RESERVED5[11];
2153 
2154   union {
2155     __IOM uint32_t DMON0;                       /*!< (@ 0x00000100) Data Cache Total Accesses                                  */
2156 
2157     struct {
2158       __IOM uint32_t DACCESS    : 32;           /*!< [31..0] Total accesses to data cache. All performance metrics
2159                                                      should be relative to the number of accesses performed.                   */
2160     } DMON0_b;
2161   } ;
2162 
2163   union {
2164     __IOM uint32_t DMON1;                       /*!< (@ 0x00000104) Data Cache Tag Lookups                                     */
2165 
2166     struct {
2167       __IOM uint32_t DLOOKUP    : 32;           /*!< [31..0] Total tag lookups from data cache.                                */
2168     } DMON1_b;
2169   } ;
2170 
2171   union {
2172     __IOM uint32_t DMON2;                       /*!< (@ 0x00000108) Data Cache Hits                                            */
2173 
2174     struct {
2175       __IOM uint32_t DHIT       : 32;           /*!< [31..0] Cache hits from lookup operations.                                */
2176     } DMON2_b;
2177   } ;
2178 
2179   union {
2180     __IOM uint32_t DMON3;                       /*!< (@ 0x0000010C) Data Cache Line Hits                                       */
2181 
2182     struct {
2183       __IOM uint32_t DLINE      : 32;           /*!< [31..0] Cache hits from line cache                                        */
2184     } DMON3_b;
2185   } ;
2186 
2187   union {
2188     __IOM uint32_t IMON0;                       /*!< (@ 0x00000110) Instruction Cache Total Accesses                           */
2189 
2190     struct {
2191       __IOM uint32_t IACCESS    : 32;           /*!< [31..0] Total accesses to Instruction cache                               */
2192     } IMON0_b;
2193   } ;
2194 
2195   union {
2196     __IOM uint32_t IMON1;                       /*!< (@ 0x00000114) Instruction Cache Tag Lookups                              */
2197 
2198     struct {
2199       __IOM uint32_t ILOOKUP    : 32;           /*!< [31..0] Total tag lookups from Instruction cache                          */
2200     } IMON1_b;
2201   } ;
2202 
2203   union {
2204     __IOM uint32_t IMON2;                       /*!< (@ 0x00000118) Instruction Cache Hits                                     */
2205 
2206     struct {
2207       __IOM uint32_t IHIT       : 32;           /*!< [31..0] Cache hits from lookup operations                                 */
2208     } IMON2_b;
2209   } ;
2210 
2211   union {
2212     __IOM uint32_t IMON3;                       /*!< (@ 0x0000011C) Instruction Cache Line Hits                                */
2213 
2214     struct {
2215       __IOM uint32_t ILINE      : 32;           /*!< [31..0] Cache hits from line cache                                        */
2216     } IMON3_b;
2217   } ;
2218 } CPU_Type;                                     /*!< Size = 288 (0x120)                                                        */
2219 
2220 
2221 
2222 /* =========================================================================================================================== */
2223 /* ================                                          CRYPTO                                           ================ */
2224 /* =========================================================================================================================== */
2225 
2226 
2227 /**
2228   * @brief Embedded security and cryptographic services (CRYPTO)
2229   */
2230 
2231 typedef struct {                                /*!< (@ 0x400C0000) CRYPTO Structure                                           */
2232 
2233   union {
2234     __IOM uint32_t MEMORYMAP0;                  /*!< (@ 0x00000000) This register maps the virtual register R0 to
2235                                                                     a physical address in memory.                              */
2236 
2237     struct {
2238             uint32_t            : 1;
2239       __IOM uint32_t PHYSADDRMAP0 : 10;         /*!< [10..1] Contains the physical address in memory to map the R0
2240                                                      register.                                                                 */
2241             uint32_t            : 21;
2242     } MEMORYMAP0_b;
2243   } ;
2244 
2245   union {
2246     __IOM uint32_t MEMORYMAP1;                  /*!< (@ 0x00000004) This register maps the virtual register R1 to
2247                                                                     a physical address in memory.                              */
2248 
2249     struct {
2250             uint32_t            : 1;
2251       __IOM uint32_t PHYSADDRMAP1 : 10;         /*!< [10..1] Contains the physical address in memory to map the R1
2252                                                      register.                                                                 */
2253             uint32_t            : 21;
2254     } MEMORYMAP1_b;
2255   } ;
2256 
2257   union {
2258     __IOM uint32_t MEMORYMAP2;                  /*!< (@ 0x00000008) This register maps the virtual register R2 to
2259                                                                     a physical address in memory.                              */
2260 
2261     struct {
2262             uint32_t            : 1;
2263       __IOM uint32_t PHYSADDRMAP2 : 10;         /*!< [10..1] Contains the physical address in memory to map the R2
2264                                                      register.                                                                 */
2265             uint32_t            : 21;
2266     } MEMORYMAP2_b;
2267   } ;
2268 
2269   union {
2270     __IOM uint32_t MEMORYMAP3;                  /*!< (@ 0x0000000C) This register maps the virtual register R3 to
2271                                                                     a physical address in memory.                              */
2272 
2273     struct {
2274             uint32_t            : 1;
2275       __IOM uint32_t PHYSADDRMAP3 : 10;         /*!< [10..1] Contains the physical address in memory to map the R3
2276                                                      register.                                                                 */
2277             uint32_t            : 21;
2278     } MEMORYMAP3_b;
2279   } ;
2280 
2281   union {
2282     __IOM uint32_t MEMORYMAP4;                  /*!< (@ 0x00000010) This register maps the virtual register R4 to
2283                                                                     a physical address in memory.                              */
2284 
2285     struct {
2286             uint32_t            : 1;
2287       __IOM uint32_t PHYSADDRMAP4 : 10;         /*!< [10..1] Contains the physical address in memory to map the R4
2288                                                      register.                                                                 */
2289             uint32_t            : 21;
2290     } MEMORYMAP4_b;
2291   } ;
2292 
2293   union {
2294     __IOM uint32_t MEMORYMAP5;                  /*!< (@ 0x00000014) This register maps the virtual register R5 to
2295                                                                     a physical address in memory.                              */
2296 
2297     struct {
2298             uint32_t            : 1;
2299       __IOM uint32_t PHYSADDRMAP5 : 10;         /*!< [10..1] Contains the physical address in memory to map the R5
2300                                                      register.                                                                 */
2301             uint32_t            : 21;
2302     } MEMORYMAP5_b;
2303   } ;
2304 
2305   union {
2306     __IOM uint32_t MEMORYMAP6;                  /*!< (@ 0x00000018) This register maps the virtual register R6 to
2307                                                                     a physical address in memory.                              */
2308 
2309     struct {
2310             uint32_t            : 1;
2311       __IOM uint32_t PHYSADDRMAP6 : 10;         /*!< [10..1] Contains the physical address in memory to map the R6
2312                                                      register.                                                                 */
2313             uint32_t            : 21;
2314     } MEMORYMAP6_b;
2315   } ;
2316 
2317   union {
2318     __IOM uint32_t MEMORYMAP7;                  /*!< (@ 0x0000001C) This register maps the virtual register R7 to
2319                                                                     a physical address in memory.                              */
2320 
2321     struct {
2322             uint32_t            : 1;
2323       __IOM uint32_t PHYSADDRMAP7 : 10;         /*!< [10..1] Contains the physical address in memory to map the R7
2324                                                      register.                                                                 */
2325             uint32_t            : 21;
2326     } MEMORYMAP7_b;
2327   } ;
2328 
2329   union {
2330     __IOM uint32_t MEMORYMAP8;                  /*!< (@ 0x00000020) This register maps the virtual register R8 to
2331                                                                     a physical address in memory.                              */
2332 
2333     struct {
2334             uint32_t            : 1;
2335       __IOM uint32_t PHYSADDRMAP8 : 10;         /*!< [10..1] Contains the physical address in memory to map the R8
2336                                                      register.                                                                 */
2337             uint32_t            : 21;
2338     } MEMORYMAP8_b;
2339   } ;
2340 
2341   union {
2342     __IOM uint32_t MEMORYMAP9;                  /*!< (@ 0x00000024) This register maps the virtual register R9 to
2343                                                                     a physical address in memory.                              */
2344 
2345     struct {
2346             uint32_t            : 1;
2347       __IOM uint32_t PHYSADDRMAP9 : 10;         /*!< [10..1] Contains the physical address in memory to map the R9
2348                                                      register.                                                                 */
2349             uint32_t            : 21;
2350     } MEMORYMAP9_b;
2351   } ;
2352 
2353   union {
2354     __IOM uint32_t MEMORYMAP10;                 /*!< (@ 0x00000028) This register maps the virtual register R10 to
2355                                                                     a physical address in memory.                              */
2356 
2357     struct {
2358             uint32_t            : 1;
2359       __IOM uint32_t PHYSADDRMAP10 : 10;        /*!< [10..1] Contains the physical address in memory to map the R10
2360                                                      register.                                                                 */
2361             uint32_t            : 21;
2362     } MEMORYMAP10_b;
2363   } ;
2364 
2365   union {
2366     __IOM uint32_t MEMORYMAP11;                 /*!< (@ 0x0000002C) This register maps the virtual register R11 to
2367                                                                     a physical address in memory.                              */
2368 
2369     struct {
2370             uint32_t            : 1;
2371       __IOM uint32_t PHYSADDRMAP11 : 10;        /*!< [10..1] Contains the physical address in memory to map the R11
2372                                                      register.                                                                 */
2373             uint32_t            : 21;
2374     } MEMORYMAP11_b;
2375   } ;
2376 
2377   union {
2378     __IOM uint32_t MEMORYMAP12;                 /*!< (@ 0x00000030) This register maps the virtual register R12 to
2379                                                                     a physical address in memory.                              */
2380 
2381     struct {
2382             uint32_t            : 1;
2383       __IOM uint32_t PHYSADDRMAP12 : 10;        /*!< [10..1] Contains the physical address in memory to map the R12
2384                                                      register.                                                                 */
2385             uint32_t            : 21;
2386     } MEMORYMAP12_b;
2387   } ;
2388 
2389   union {
2390     __IOM uint32_t MEMORYMAP13;                 /*!< (@ 0x00000034) This register maps the virtual register R13 to
2391                                                                     a physical address in memory.                              */
2392 
2393     struct {
2394             uint32_t            : 1;
2395       __IOM uint32_t PHYSADDRMAP13 : 10;        /*!< [10..1] Contains the physical address in memory to map the R13
2396                                                      register.                                                                 */
2397             uint32_t            : 21;
2398     } MEMORYMAP13_b;
2399   } ;
2400 
2401   union {
2402     __IOM uint32_t MEMORYMAP14;                 /*!< (@ 0x00000038) This register maps the virtual register R14 to
2403                                                                     a physical address in memory.                              */
2404 
2405     struct {
2406             uint32_t            : 1;
2407       __IOM uint32_t PHYSADDRMAP14 : 10;        /*!< [10..1] Contains the physical address in memory to map the R14
2408                                                      register.                                                                 */
2409             uint32_t            : 21;
2410     } MEMORYMAP14_b;
2411   } ;
2412 
2413   union {
2414     __IOM uint32_t MEMORYMAP15;                 /*!< (@ 0x0000003C) This register maps the virtual register R15 to
2415                                                                     a physical address in memory.                              */
2416 
2417     struct {
2418             uint32_t            : 1;
2419       __IOM uint32_t PHYSADDRMAP15 : 10;        /*!< [10..1] Contains the physical address in memory to map the R15
2420                                                      registero.                                                                */
2421             uint32_t            : 21;
2422     } MEMORYMAP15_b;
2423   } ;
2424 
2425   union {
2426     __IOM uint32_t MEMORYMAP16;                 /*!< (@ 0x00000040) This register maps the virtual register R16 to
2427                                                                     a physical address in memory.                              */
2428 
2429     struct {
2430             uint32_t            : 1;
2431       __IOM uint32_t PHYSADDRMAP16 : 10;        /*!< [10..1] Contains the physical address in memory to map the R16
2432                                                      register.                                                                 */
2433             uint32_t            : 21;
2434     } MEMORYMAP16_b;
2435   } ;
2436 
2437   union {
2438     __IOM uint32_t MEMORYMAP17;                 /*!< (@ 0x00000044) This register maps the virtual register R17 to
2439                                                                     a physical address in memory.                              */
2440 
2441     struct {
2442             uint32_t            : 1;
2443       __IOM uint32_t PHYSADDRMAP17 : 10;        /*!< [10..1] Contains the physical address in memory to map the R17
2444                                                      registero.                                                                */
2445             uint32_t            : 21;
2446     } MEMORYMAP17_b;
2447   } ;
2448 
2449   union {
2450     __IOM uint32_t MEMORYMAP18;                 /*!< (@ 0x00000048) This register maps the virtual register R18 to
2451                                                                     a physical address in memory.                              */
2452 
2453     struct {
2454             uint32_t            : 1;
2455       __IOM uint32_t PHYSADDRMAP18 : 10;        /*!< [10..1] Contains the physical address in memory to map the R18
2456                                                      register.                                                                 */
2457             uint32_t            : 21;
2458     } MEMORYMAP18_b;
2459   } ;
2460 
2461   union {
2462     __IOM uint32_t MEMORYMAP19;                 /*!< (@ 0x0000004C) This register maps the virtual register R19 to
2463                                                                     a physical address in memory.                              */
2464 
2465     struct {
2466             uint32_t            : 1;
2467       __IOM uint32_t PHYSADDRMAP19 : 10;        /*!< [10..1] Contains the physical address in memory to map the R19
2468                                                      register to.                                                              */
2469             uint32_t            : 21;
2470     } MEMORYMAP19_b;
2471   } ;
2472 
2473   union {
2474     __IOM uint32_t MEMORYMAP20;                 /*!< (@ 0x00000050) This register maps the virtual register R20 to
2475                                                                     a physical address in memory.                              */
2476 
2477     struct {
2478             uint32_t            : 1;
2479       __IOM uint32_t PHYSADDRMAP20 : 10;        /*!< [10..1] Contains the physical address in memory to map the R20
2480                                                      register to.                                                              */
2481             uint32_t            : 21;
2482     } MEMORYMAP20_b;
2483   } ;
2484 
2485   union {
2486     __IOM uint32_t MEMORYMAP21;                 /*!< (@ 0x00000054) This register maps the virtual register R21 to
2487                                                                     a physical address in memory.                              */
2488 
2489     struct {
2490             uint32_t            : 1;
2491       __IOM uint32_t PHYSADDRMAP21 : 10;        /*!< [10..1] Contains the physical address in memory to map the R21
2492                                                      register to.                                                              */
2493             uint32_t            : 21;
2494     } MEMORYMAP21_b;
2495   } ;
2496 
2497   union {
2498     __IOM uint32_t MEMORYMAP22;                 /*!< (@ 0x00000058) This register maps the virtual register R22 to
2499                                                                     a physical address in memory.                              */
2500 
2501     struct {
2502             uint32_t            : 1;
2503       __IOM uint32_t PHYSADDRMAP22 : 10;        /*!< [10..1] Contains the physical address in memory to map the R22
2504                                                      register to.                                                              */
2505             uint32_t            : 21;
2506     } MEMORYMAP22_b;
2507   } ;
2508 
2509   union {
2510     __IOM uint32_t MEMORYMAP23;                 /*!< (@ 0x0000005C) This register maps the virtual register R23 to
2511                                                                     a physical address in memory.                              */
2512 
2513     struct {
2514             uint32_t            : 1;
2515       __IOM uint32_t PHYSADDRMAP23 : 10;        /*!< [10..1] Contains the physical address in memory to map the R23
2516                                                      register to.                                                              */
2517             uint32_t            : 21;
2518     } MEMORYMAP23_b;
2519   } ;
2520 
2521   union {
2522     __IOM uint32_t MEMORYMAP24;                 /*!< (@ 0x00000060) This register maps the virtual register R24 to
2523                                                                     a physical address in memory.                              */
2524 
2525     struct {
2526             uint32_t            : 1;
2527       __IOM uint32_t PHYSADDRMAP24 : 10;        /*!< [10..1] Contains the physical address in memory to map the R24
2528                                                      register to.                                                              */
2529             uint32_t            : 21;
2530     } MEMORYMAP24_b;
2531   } ;
2532 
2533   union {
2534     __IOM uint32_t MEMORYMAP25;                 /*!< (@ 0x00000064) This register maps the virtual register R25 to
2535                                                                     a physical address in memory.                              */
2536 
2537     struct {
2538             uint32_t            : 1;
2539       __IOM uint32_t PHYSADDRMAP25 : 10;        /*!< [10..1] Contains the physical address in memory to map the R25
2540                                                      register to.                                                              */
2541             uint32_t            : 21;
2542     } MEMORYMAP25_b;
2543   } ;
2544 
2545   union {
2546     __IOM uint32_t MEMORYMAP26;                 /*!< (@ 0x00000068) This register maps the virtual register R26 to
2547                                                                     a physical address in memory.                              */
2548 
2549     struct {
2550             uint32_t            : 1;
2551       __IOM uint32_t PHYSADDRMAP26 : 10;        /*!< [10..1] Contains the physical address in memory to map the R26
2552                                                      register to.                                                              */
2553             uint32_t            : 21;
2554     } MEMORYMAP26_b;
2555   } ;
2556 
2557   union {
2558     __IOM uint32_t MEMORYMAP27;                 /*!< (@ 0x0000006C) This register maps the virtual register R27 to
2559                                                                     a physical address in memory.                              */
2560 
2561     struct {
2562             uint32_t            : 1;
2563       __IOM uint32_t PHYSADDRMAP27 : 10;        /*!< [10..1] Contains the physical address in memory to map the R27
2564                                                      register to.                                                              */
2565             uint32_t            : 21;
2566     } MEMORYMAP27_b;
2567   } ;
2568 
2569   union {
2570     __IOM uint32_t MEMORYMAP28;                 /*!< (@ 0x00000070) This register maps the virtual register R28 to
2571                                                                     a physical address in memory.                              */
2572 
2573     struct {
2574             uint32_t            : 1;
2575       __IOM uint32_t PHYSADDRMAP28 : 10;        /*!< [10..1] Contains the physical address in memory to map the R28
2576                                                      register.                                                                 */
2577             uint32_t            : 21;
2578     } MEMORYMAP28_b;
2579   } ;
2580 
2581   union {
2582     __IOM uint32_t MEMORYMAP29;                 /*!< (@ 0x00000074) This register maps the virtual register R29 to
2583                                                                     a physical address in memory.                              */
2584 
2585     struct {
2586             uint32_t            : 1;
2587       __IOM uint32_t PHYSADDRMAP29 : 10;        /*!< [10..1] Contains the physical address in memory to map the R29
2588                                                      register.                                                                 */
2589             uint32_t            : 21;
2590     } MEMORYMAP29_b;
2591   } ;
2592 
2593   union {
2594     __IOM uint32_t MEMORYMAP30;                 /*!< (@ 0x00000078) This register maps the virtual register R30 to
2595                                                                     a physical address in memory.                              */
2596 
2597     struct {
2598             uint32_t            : 1;
2599       __IOM uint32_t PHYSADDRMAP30 : 10;        /*!< [10..1] Contains the physical address in memory to map the R30
2600                                                      register.                                                                 */
2601             uint32_t            : 21;
2602     } MEMORYMAP30_b;
2603   } ;
2604 
2605   union {
2606     __IOM uint32_t MEMORYMAP31;                 /*!< (@ 0x0000007C) This register maps the virtual register R31 to
2607                                                                     a physical address in memory.                              */
2608 
2609     struct {
2610             uint32_t            : 1;
2611       __IOM uint32_t PHYSADDRMAP31 : 10;        /*!< [10..1] Contains the physical address in memory to map the R31
2612                                                      register.                                                                 */
2613             uint32_t            : 21;
2614     } MEMORYMAP31_b;
2615   } ;
2616 
2617   union {
2618     __IOM uint32_t OPCODE;                      /*!< (@ 0x00000080) This register holds the PKAs OPCODE.                       */
2619 
2620     struct {
2621       __IOM uint32_t TAG        : 6;            /*!< [5..0] Holds the operations tag or the operand C virtual address.         */
2622       __IOM uint32_t REGR       : 6;            /*!< [11..6] Result register virtual address 0-15.                             */
2623       __IOM uint32_t REGB       : 6;            /*!< [17..12] Operand B virtual address 0-15.                                  */
2624       __IOM uint32_t REGA       : 6;            /*!< [23..18] Operand A virtual address 0-15.                                  */
2625       __IOM uint32_t LEN        : 3;            /*!< [26..24] The length of the operation. The value serves as a
2626                                                      pointer to PKA length register, for example, if the value
2627                                                      is 0, PKA_L0 holds the size of the operation.                             */
2628       __IOM uint32_t OPCODE     : 5;            /*!< [31..27] Defines the PKA operation:                                       */
2629     } OPCODE_b;
2630   } ;
2631 
2632   union {
2633     __IOM uint32_t NNPT0T1ADDR;                 /*!< (@ 0x00000084) This register maps N_NP_T0_T1 to a virtual address.        */
2634 
2635     struct {
2636       __IOM uint32_t NVIRTUALADDR : 5;          /*!< [4..0] Virtual address of register N.                                     */
2637       __IOM uint32_t NPVIRTUALADDR : 5;         /*!< [9..5] Virtual address of register NP.                                    */
2638       __IOM uint32_t T0VIRTUALADDR : 5;         /*!< [14..10] Virtual address of temporary register number 0                   */
2639       __IOM uint32_t T1VIRTUALADDR : 5;         /*!< [19..15] Virtual address of temporary register number 1                   */
2640             uint32_t            : 12;
2641     } NNPT0T1ADDR_b;
2642   } ;
2643 
2644   union {
2645     __IOM uint32_t PKASTATUS;                   /*!< (@ 0x00000088) This register holds the PKA pipe status.                   */
2646 
2647     struct {
2648       __IOM uint32_t ALUMSB4BITS : 4;           /*!< [3..0] The most significant 4-bits of the operand updated in
2649                                                      shift operation.                                                          */
2650       __IOM uint32_t ALULSB4BITS : 4;           /*!< [7..4] The least significant 4-bits of the operand updated in
2651                                                      shift operation.                                                          */
2652       __IOM uint32_t ALUSIGNOUT : 1;            /*!< [8..8] Indicates the last operations sign (MSB).                          */
2653       __IOM uint32_t ALUCARRY   : 1;            /*!< [9..9] Holds the carry of the last ALU operation.                         */
2654       __IOM uint32_t ALUCARRYMOD : 1;           /*!< [10..10] holds the carry of the last Modular operation.                   */
2655       __IOM uint32_t ALUSUBISZERO : 1;          /*!< [11..11] Indicates the last subtraction operations sign .                 */
2656       __IOM uint32_t ALUOUTZERO : 1;            /*!< [12..12] Indicates if the result of ALU OUT is zero.                      */
2657       __IOM uint32_t ALUMODOVRFLW : 1;          /*!< [13..13] Modular overflow flag.                                           */
2658       __IOM uint32_t DIVBYZERO  : 1;            /*!< [14..14] Indication if the division is done by zero.                      */
2659       __IOM uint32_t MODINVOFZERO : 1;          /*!< [15..15] Indicates the Modular inverse of zero.                           */
2660       __IOM uint32_t OPCODE     : 5;            /*!< [20..16] Opcode of the last operation                                     */
2661             uint32_t            : 11;
2662     } PKASTATUS_b;
2663   } ;
2664 
2665   union {
2666     __IOM uint32_t PKASWRESET;                  /*!< (@ 0x0000008C) Writing to this register triggers a software
2667                                                                     reset of the PKA.                                          */
2668 
2669     struct {
2670       __IOM uint32_t PKASWRESET : 1;            /*!< [0..0] The reset mechanism takes about four PKA clock cycles
2671                                                      until the reset line is deasserted                                        */
2672             uint32_t            : 31;
2673     } PKASWRESET_b;
2674   } ;
2675 
2676   union {
2677     __IOM uint32_t PKAL0;                       /*!< (@ 0x00000090) This register holds one of the optional size
2678                                                                     of the operation.                                          */
2679 
2680     struct {
2681       __IOM uint32_t PKAL0      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2682             uint32_t            : 19;
2683     } PKAL0_b;
2684   } ;
2685 
2686   union {
2687     __IOM uint32_t PKAL1;                       /*!< (@ 0x00000094) This register holds one of the optional size
2688                                                                     of the operation.                                          */
2689 
2690     struct {
2691       __IOM uint32_t PKAL1      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2692             uint32_t            : 19;
2693     } PKAL1_b;
2694   } ;
2695 
2696   union {
2697     __IOM uint32_t PKAL2;                       /*!< (@ 0x00000098) This register holds one of the optional size
2698                                                                     of the operation.                                          */
2699 
2700     struct {
2701       __IOM uint32_t PKAL2      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2702             uint32_t            : 19;
2703     } PKAL2_b;
2704   } ;
2705 
2706   union {
2707     __IOM uint32_t PKAL3;                       /*!< (@ 0x0000009C) This register holds one of the optional size
2708                                                                     of the operation.                                          */
2709 
2710     struct {
2711       __IOM uint32_t PKAL3      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2712             uint32_t            : 19;
2713     } PKAL3_b;
2714   } ;
2715 
2716   union {
2717     __IOM uint32_t PKAL4;                       /*!< (@ 0x000000A0) This register holds one of the optional size
2718                                                                     of the operation.                                          */
2719 
2720     struct {
2721       __IOM uint32_t PKAL4      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2722             uint32_t            : 19;
2723     } PKAL4_b;
2724   } ;
2725 
2726   union {
2727     __IOM uint32_t PKAL5;                       /*!< (@ 0x000000A4) This register holds one of the optional size
2728                                                                     of the operation.                                          */
2729 
2730     struct {
2731       __IOM uint32_t PKAL5      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2732             uint32_t            : 19;
2733     } PKAL5_b;
2734   } ;
2735 
2736   union {
2737     __IOM uint32_t PKAL6;                       /*!< (@ 0x000000A8) This register holds one of the optional size
2738                                                                     of the operation.                                          */
2739 
2740     struct {
2741       __IOM uint32_t PKAL6      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2742             uint32_t            : 19;
2743     } PKAL6_b;
2744   } ;
2745 
2746   union {
2747     __IOM uint32_t PKAL7;                       /*!< (@ 0x000000AC) This register holds one of the optional size
2748                                                                     of the operation.                                          */
2749 
2750     struct {
2751       __IOM uint32_t PKAL7      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
2752             uint32_t            : 19;
2753     } PKAL7_b;
2754   } ;
2755 
2756   union {
2757     __IOM uint32_t PKAPIPERDY;                  /*!< (@ 0x000000B0) This register indicates whether the PKA pipe
2758                                                                     is ready to receive a new OPCODE.                          */
2759 
2760     struct {
2761       __IOM uint32_t PKAPIPERDY : 1;            /*!< [0..0] Indication whether PKA pipe is ready for new OPCODE.               */
2762             uint32_t            : 31;
2763     } PKAPIPERDY_b;
2764   } ;
2765 
2766   union {
2767     __IOM uint32_t PKADONE;                     /*!< (@ 0x000000B4) This register indicates whether PKA operation
2768                                                                     is completed.                                              */
2769 
2770     struct {
2771       __IOM uint32_t PKADONE    : 1;            /*!< [0..0] Indicates if PKA operation is completed, and pipe is
2772                                                      empty.                                                                    */
2773             uint32_t            : 31;
2774     } PKADONE_b;
2775   } ;
2776 
2777   union {
2778     __IOM uint32_t PKAMONSELECT;                /*!< (@ 0x000000B8) This register defines which PKA FSM monitor is
2779                                                                     being output.                                              */
2780 
2781     struct {
2782       __IOM uint32_t PKAMONSELECT : 4;          /*!< [3..0] Defines which PKA FSM monitor is being output.                     */
2783             uint32_t            : 28;
2784     } PKAMONSELECT_b;
2785   } ;
2786   __IM  uint32_t  RESERVED[2];
2787 
2788   union {
2789     __IOM uint32_t PKAVERSION;                  /*!< (@ 0x000000C4) This register holds the pka version                        */
2790 
2791     struct {
2792       __IOM uint32_t PKAVERSION : 32;           /*!< [31..0] This is the PKA version                                           */
2793     } PKAVERSION_b;
2794   } ;
2795   __IM  uint32_t  RESERVED1[2];
2796 
2797   union {
2798     __IOM uint32_t PKAMONREAD;                  /*!< (@ 0x000000D0) The PKA monitor bus register.                              */
2799 
2800     struct {
2801       __IOM uint32_t PKAMONREAD : 32;           /*!< [31..0] This is the PKA monitor bus register output                       */
2802     } PKAMONREAD_b;
2803   } ;
2804 
2805   union {
2806     __IOM uint32_t PKASRAMADDR;                 /*!< (@ 0x000000D4) first address given to PKA SRAM for write transactions.    */
2807 
2808     struct {
2809       __IOM uint32_t PKASRAMADDR : 32;          /*!< [31..0] PKA SRAM write starting address                                   */
2810     } PKASRAMADDR_b;
2811   } ;
2812 
2813   union {
2814     __IOM uint32_t PKASRAMWDATA;                /*!< (@ 0x000000D8) Write data to PKA SRAM.                                    */
2815 
2816     struct {
2817       __IOM uint32_t PKASRAMWDATA : 32;         /*!< [31..0] 32 bit write to PKA SRAM: triggers the SRAM write DMA
2818                                                      address automatically incremented                                         */
2819     } PKASRAMWDATA_b;
2820   } ;
2821 
2822   union {
2823     __IOM uint32_t PKASRAMRDATA;                /*!< (@ 0x000000DC) Read data from PKA SRAM.                                   */
2824 
2825     struct {
2826       __IOM uint32_t PKASRAMRDATA : 32;         /*!< [31..0] 32 bit read from PKA SRAM: read - triggers the SRAM
2827                                                      read DMA address automatically incremented                                */
2828     } PKASRAMRDATA_b;
2829   } ;
2830 
2831   union {
2832     __IOM uint32_t PKASRAMWRCLR;                /*!< (@ 0x000000E0) Write buffer clean.                                        */
2833 
2834     struct {
2835       __IOM uint32_t PKASRAMWRCLR : 32;         /*!< [31..0] Clear the write buffer.                                           */
2836     } PKASRAMWRCLR_b;
2837   } ;
2838 
2839   union {
2840     __IOM uint32_t PKASRAMRADDR;                /*!< (@ 0x000000E4) first address given to PKA SRAM for read transactions.     */
2841 
2842     struct {
2843       __IOM uint32_t PKASRAMRADDR : 32;         /*!< [31..0] PKA SRAM read starting address                                    */
2844     } PKASRAMRADDR_b;
2845   } ;
2846   __IM  uint32_t  RESERVED2[2];
2847 
2848   union {
2849     __IOM uint32_t PKAWORDACCESS;               /*!< (@ 0x000000F0) This register holds the data written to PKA memory
2850                                                                     using the wop opcode.                                      */
2851 
2852     struct {
2853       __IOM uint32_t PKAWORDACCESS : 32;        /*!< [31..0] 32 bit read_write data.                                           */
2854     } PKAWORDACCESS_b;
2855   } ;
2856   __IM  uint32_t  RESERVED3;
2857 
2858   union {
2859     __IOM uint32_t PKABUFFADDR;                 /*!< (@ 0x000000F8) This register maps the virtual buffer registers
2860                                                                     to a physical address in memory.                           */
2861 
2862     struct {
2863       __IOM uint32_t PKABUFADDR : 12;           /*!< [11..0] Contains the physical address in memory to map the buffer
2864                                                      registers.                                                                */
2865             uint32_t            : 20;
2866     } PKABUFFADDR_b;
2867   } ;
2868   __IM  uint32_t  RESERVED4;
2869 
2870   union {
2871     __IOM uint32_t RNGIMR;                      /*!< (@ 0x00000100) Interrupt masking register. Consists of {prng_imr
2872                                                                     trng_imr} bit[31-16] - PRNG_IMR bit[15-0]
2873                                                                     - TRNG_IMR(Ws - PRNG bit exists only if
2874                                                                     PRNG_EXISTS flag)                                          */
2875 
2876     struct {
2877       __IOM uint32_t EHRVALIDINTMASK : 1;       /*!< [0..0] 0x1 - masks the EHR interrupt. No interrupt is generated.          */
2878       __IOM uint32_t AUTOCORRERRINTMASK : 1;    /*!< [1..1] 0x1 - masks the autocorrelation interrupt. No interrupt
2879                                                      is generated.                                                             */
2880       __IOM uint32_t CRNGTERRINTMASK : 1;       /*!< [2..2] 0x1 - masks the CRNGT error interrupt. No interrupt is
2881                                                      generated.                                                                */
2882       __IOM uint32_t VNERRINTMASK : 1;          /*!< [3..3] 0x1 - masks the Von-Neumann error interrupt. No interrupt
2883                                                      is generated.                                                             */
2884       __IOM uint32_t WATCHDOGINTMASK : 1;       /*!< [4..4] 0x1 - masks the watchdog interrupt. No interrupt is generated.     */
2885       __IOM uint32_t RNGDMADONEINT : 1;         /*!< [5..5] 0x1 - masks the RNG DMA completion interrupt. No interrupt
2886                                                      is generated.                                                             */
2887             uint32_t            : 26;
2888     } RNGIMR_b;
2889   } ;
2890 
2891   union {
2892     __IOM uint32_t RNGISR;                      /*!< (@ 0x00000104) Status register. If corresponding RNG_IMR bit
2893                                                                     is unmasked, an interrupt is generated.Consists
2894                                                                     of trng_isr and prng_isr bit[15-0] - TRNG
2895                                                                     bit[31-16] - PRNG                                          */
2896 
2897     struct {
2898       __IOM uint32_t EHRVALID   : 1;            /*!< [0..0] 0x1 indicates that 192 bits have been collected in the
2899                                                      TRNG and are ready to be read.                                            */
2900       __IOM uint32_t AUTOCORRERR : 1;           /*!< [1..1] 0x1 indicates Autocorrelation test failed four times
2901                                                      in a row. When it set ,TRNG ceases to function until next
2902                                                      reset.                                                                    */
2903       __IOM uint32_t CRNGTERR   : 1;            /*!< [2..2] 0x1 indicates CRNGT in the TRNG test failed. Failure
2904                                                      occurs when two consecutive blocks of 16 collected bits
2905                                                      are equal.                                                                */
2906       __IOM uint32_t VNERR      : 1;            /*!< [3..3] 0x1 indicates Von Neumann error. Error in von Neumann
2907                                                      occurs if 32 consecutive collected bits are identical,
2908                                                      ZERO, or ONE.                                                             */
2909             uint32_t            : 1;
2910       __IOM uint32_t RNGDMADONE : 1;            /*!< [5..5] 0x1 indicates RNG DMA to SRAM is completed.                        */
2911             uint32_t            : 10;
2912       __IOM uint32_t RESEEDINGDONE : 1;         /*!< [16..16] 0x1 indicates completion of reseeding algorithm with
2913                                                      no errors.                                                                */
2914       __IOM uint32_t INSTANTIATIONDONE : 1;     /*!< [17..17] 0x1 indicates completion of instantiation algorithm
2915                                                      with no errors.                                                           */
2916       __IOM uint32_t FINALUPDATEDONE : 1;       /*!< [18..18] 0x1 indicates completion of final update algorithm.              */
2917       __IOM uint32_t OUTPUTREADY : 1;           /*!< [19..19] 0x1 indicates that the result of PRNG is valid and
2918                                                      ready to be read. The result can be read from the RNG_READOUT
2919                                                      register.                                                                 */
2920       __IOM uint32_t RESEEDCNTRFULL : 1;        /*!< [20..20] 0x1 indicates that the reseed counter has reached 2^48,
2921                                                      requiring to run the reseed algorithm before generating
2922                                                      new random numbers.                                                       */
2923       __IOM uint32_t RESEEDCNTRTOP40 : 1;       /*!< [21..21] 0x1 indicates that the top 40 bits of the reseed counter
2924                                                      are set (that is the reseed counter is larger than 2^48-2^8).
2925                                                      This is a recommendation for running the reseed algorithm
2926                                                      before the counter reaches its max value.                                 */
2927       __IOM uint32_t PRNGCRNGTERR : 1;          /*!< [22..22] 0x1 indicates CRNGT in the PRNG test failed. Failure
2928                                                      occurs when two consecutive results of AES are equal                      */
2929       __IOM uint32_t REQSIZE    : 1;            /*!< [23..23] 0x1 indicates that the request size counter (which
2930                                                      represents how many generations of random bits in the PRNG
2931                                                      have been produced) has reached 2^12, thus requiring a
2932                                                      working state update before generating new random numbers.                */
2933       __IOM uint32_t KATERR     : 1;            /*!< [24..24] 0x1 indicates that one of the KAT (Known Answer Tests)
2934                                                      tests has failed. When set, the entire engine ceases to
2935                                                      function.                                                                 */
2936       __IOM uint32_t WHICHKATERR : 2;           /*!< [26..25] When the KAT_ERR bit is set, these bits represent which
2937                                                      Known Answer Test had failed:                                             */
2938             uint32_t            : 5;
2939     } RNGISR_b;
2940   } ;
2941 
2942   union {
2943     __IOM uint32_t RNGICR;                      /*!< (@ 0x00000108) Interrupt_status bit clear Register. Consists
2944                                                                     of trng_icr and prng_icr bit[15-0] - TRNG
2945                                                                     bit[31-16] - PRNG                                          */
2946 
2947     struct {
2948       __IOM uint32_t EHRVALID   : 1;            /*!< [0..0] Writing value 0x1 - clears corresponding bit in RNGISR             */
2949       __IOM uint32_t AUTOCORRERR : 1;           /*!< [1..1] Cannot be cleared by SW! Only RNG reset clears this bit.           */
2950       __IOM uint32_t CRNGTERR   : 1;            /*!< [2..2] Writing value 0x1 - clears corresponding bit in RNGISR             */
2951       __IOM uint32_t VNERR      : 1;            /*!< [3..3] Writing value 0x1 - clears corresponding bit in RNGISR             */
2952       __IOM uint32_t RNGWATCHDOG : 1;           /*!< [4..4] Writing value 0x1 - clears corresponding bit in RNGISR             */
2953       __IOM uint32_t RNGDMADONE : 1;            /*!< [5..5] Writing value 0x1 - clears corresponding bit in RNGISR             */
2954             uint32_t            : 10;
2955       __IOM uint32_t RESEEDINGDONE : 1;         /*!< [16..16] Writing value 0x1 - clears corresponding bit in RNGISR           */
2956       __IOM uint32_t INSTANTIATIONDONE : 1;     /*!< [17..17] Writing value 0x1 - clears corresponding bit in RNGISR           */
2957       __IOM uint32_t FINALUPDATEDONE : 1;       /*!< [18..18] Writing value 0x1 - clears corresponding bit in RNGISR           */
2958       __IOM uint32_t OUTPUTREADY : 1;           /*!< [19..19] Writing value 0x1 - clears corresponding bit in RNGISR           */
2959       __IOM uint32_t RESEEDCNTRFULL : 1;        /*!< [20..20] Writing value 0x1 - clears corresponding bit in RNGISR           */
2960       __IOM uint32_t RESEEDCNTRTOP40 : 1;       /*!< [21..21] Writing value 0x1 - clears corresponding bit in RNGISR           */
2961       __IOM uint32_t PRNGCRNGTERR : 1;          /*!< [22..22] Writing value 0x1 - clears corresponding bit in RNGISR           */
2962       __IOM uint32_t REQSIZE    : 1;            /*!< [23..23] Writing value 0x1 - clears corresponding bit in RNGISR           */
2963       __IOM uint32_t KATERR     : 1;            /*!< [24..24] Cannot be cleared by SW! Only RNG reset clears this
2964                                                      bit.                                                                      */
2965       __IOM uint32_t WHICHKATERR : 2;           /*!< [26..25] Cannot be cleared by SW! Only RNG reset clears this
2966                                                      bit.                                                                      */
2967             uint32_t            : 5;
2968     } RNGICR_b;
2969   } ;
2970 
2971   union {
2972     __IOM uint32_t TRNGCONFIG;                  /*!< (@ 0x0000010C) This register handles TRNG configuration                   */
2973 
2974     struct {
2975       __IOM uint32_t RNDSRCSEL  : 2;            /*!< [1..0] Defines the length of the oscillator ring (= the number
2976                                                      of inverters) out of four possible selections.                            */
2977       __IOM uint32_t SOPSEL     : 1;            /*!< [2..2] Secure Output Port selection:                                      */
2978             uint32_t            : 29;
2979     } TRNGCONFIG_b;
2980   } ;
2981 
2982   union {
2983     __IOM uint32_t TRNGVALID;                   /*!< (@ 0x00000110) This register indicates that the TRNG data is
2984                                                                     valid.                                                     */
2985 
2986     struct {
2987       __IOM uint32_t EHRVALID   : 1;            /*!< [0..0] 0x1 indicates that collection of bits in the TRNG is
2988                                                      completed, and data can be read from the EHR_DATA register.               */
2989             uint32_t            : 31;
2990     } TRNGVALID_b;
2991   } ;
2992 
2993   union {
2994     __IOM uint32_t EHRDATA0;                    /*!< (@ 0x00000114) This register contains the data collected in
2995                                                                     the TRNG[31_0]. Note: can only be set while
2996                                                                     in debug mode (rng_debug_enable input is
2997                                                                     set).                                                      */
2998 
2999     struct {
3000       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[31_0]. Note:
3001                                                      can only be set while in debug mode (rng_debug_enable input
3002                                                      is set).                                                                  */
3003     } EHRDATA0_b;
3004   } ;
3005 
3006   union {
3007     __IOM uint32_t EHRDATA1;                    /*!< (@ 0x00000118) This register contains the data collected in
3008                                                                     the TRNG[63_32]. Note: can only be set while
3009                                                                     in debug mode (rng_debug_enable input is
3010                                                                     set).                                                      */
3011 
3012     struct {
3013       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[63_32]. Note:
3014                                                      can only be set while in debug mode (rng_debug_enable input
3015                                                      is set).                                                                  */
3016     } EHRDATA1_b;
3017   } ;
3018 
3019   union {
3020     __IOM uint32_t EHRDATA2;                    /*!< (@ 0x0000011C) This register contains the data collected in
3021                                                                     the TRNG[95_64]. Note: can only be set while
3022                                                                     in debug mode (rng_debug_enable input is
3023                                                                     set).                                                      */
3024 
3025     struct {
3026       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[95_64]. Note:
3027                                                      can only be set while in debug mode (rng_debug_enable input
3028                                                      is set).                                                                  */
3029     } EHRDATA2_b;
3030   } ;
3031 
3032   union {
3033     __IOM uint32_t EHRDATA3;                    /*!< (@ 0x00000120) This register contains the data collected in
3034                                                                     the TRNG[127_96]. Note: can only be set
3035                                                                     while in debug mode (rng_debug_enable input
3036                                                                     is set).                                                   */
3037 
3038     struct {
3039       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[127_96]. Note:
3040                                                      can only be set while in debug mode (rng_debug_enable input
3041                                                      is set).                                                                  */
3042     } EHRDATA3_b;
3043   } ;
3044 
3045   union {
3046     __IOM uint32_t EHRDATA4;                    /*!< (@ 0x00000124) This register contains the data collected in
3047                                                                     the TRNG[159_128]. Note: can only be set
3048                                                                     while in debug mode (rng_debug_enable input
3049                                                                     is set).                                                   */
3050 
3051     struct {
3052       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[159_128]. Note:
3053                                                      can only be set while in debug mode (rng_debug_enable input
3054                                                      is set).                                                                  */
3055     } EHRDATA4_b;
3056   } ;
3057 
3058   union {
3059     __IOM uint32_t EHRDATA5;                    /*!< (@ 0x00000128) This register contains the data collected in
3060                                                                     the TRNG[191_160]. Note: can only be set
3061                                                                     while in debug mode (rng_debug_enable input
3062                                                                     is set).                                                   */
3063 
3064     struct {
3065       __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[191_160]. Note:
3066                                                      can only be set while in debug mode (rng_debug_enable input
3067                                                      is set).                                                                  */
3068     } EHRDATA5_b;
3069   } ;
3070 
3071   union {
3072     __IOM uint32_t RNDSOURCEENABLE;             /*!< (@ 0x0000012C) This register holds the enable signal for the
3073                                                                     random source.                                             */
3074 
3075     struct {
3076       __IOM uint32_t RNDSRCEN   : 1;            /*!< [0..0] Enable signal for the random source.                               */
3077             uint32_t            : 31;
3078     } RNDSOURCEENABLE_b;
3079   } ;
3080 
3081   union {
3082     __IOM uint32_t SAMPLECNT1;                  /*!< (@ 0x00000130) Counts clocks between sampling of random bit.              */
3083 
3084     struct {
3085       __IOM uint32_t SAMPLECNTR1 : 32;          /*!< [31..0] Sets the number of rng_clk cycles between two consecutive
3086                                                      ring oscillator samples. Note: If the Von-Neumann is bypassed,
3087                                                      the minimum value for sample counter must not be less than
3088                                                      decimal seventeen.                                                        */
3089     } SAMPLECNT1_b;
3090   } ;
3091 
3092   union {
3093     __IOM uint32_t AUTOCORRSTATISTIC;           /*!< (@ 0x00000134) Statistics about autocorrelation test activations.         */
3094 
3095     struct {
3096       __IOM uint32_t AUTOCORRTRYS : 14;         /*!< [13..0] Count each time an autocorrelation test starts. Any
3097                                                      write to the register resets the counter. Stops collecting
3098                                                      statistics if one of the counters has reached the limit.                  */
3099       __IOM uint32_t AUTOCORRFAILS : 8;         /*!< [21..14] Count each time an autocorrelation test fails. Any
3100                                                      write to the register resets the counter. Stops collecting
3101                                                      statistics if one of the counters has reached the limit.                  */
3102             uint32_t            : 10;
3103     } AUTOCORRSTATISTIC_b;
3104   } ;
3105 
3106   union {
3107     __IOM uint32_t TRNGDEBUGCONTROL;            /*!< (@ 0x00000138) This register is used to debug the TRNG                    */
3108 
3109     struct {
3110             uint32_t            : 1;
3111       __IOM uint32_t VNCBYPASS  : 1;            /*!< [1..1] When this bit is set, the Von-Neumann balancer is bypassed
3112                                                      (including the 32 consecutive bits test). Note: Can only
3113                                                      be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW
3114                                                      flag is defined, this bit can be set while not in debug
3115                                                      mode.                                                                     */
3116       __IOM uint32_t TRNGCRNGTBYPASS : 1;       /*!< [2..2] When this bit is set, the CRNGT test in the TRNG is bypassed.
3117                                                      Note: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN
3118                                                      HW flag is defined, this bit can be set while not in debug
3119                                                      mode.                                                                     */
3120       __IOM uint32_t AUTOCORRELATEBYPASS : 1;   /*!< [3..3] When this bit is set, the autocorrelation test in the
3121                                                      TRNG module is bypassed. Note: Can only be set while in
3122                                                      debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined,
3123                                                      this bit can be set while not in debug mode.                              */
3124             uint32_t            : 28;
3125     } TRNGDEBUGCONTROL_b;
3126   } ;
3127   __IM  uint32_t  RESERVED5;
3128 
3129   union {
3130     __IOM uint32_t RNGSWRESET;                  /*!< (@ 0x00000140) Generate SW reset solely to RNG block.                     */
3131 
3132     struct {
3133       __IOM uint32_t RNGSWRESET : 1;            /*!< [0..0] Any value written (0x0 or 0x1) causes a reset cycle to
3134                                                      the TRNG block.                                                           */
3135             uint32_t            : 31;
3136     } RNGSWRESET_b;
3137   } ;
3138   __IM  uint32_t  RESERVED6[28];
3139 
3140   union {
3141     __IOM uint32_t RNGDEBUGENINPUT;             /*!< (@ 0x000001B4) Defines the RNG in debug mode                              */
3142 
3143     struct {
3144       __IOM uint32_t RNGDEBUGEN : 1;            /*!< [0..0] Reflects the rng_debug_enable input port                           */
3145             uint32_t            : 31;
3146     } RNGDEBUGENINPUT_b;
3147   } ;
3148 
3149   union {
3150     __IOM uint32_t RNGBUSY;                     /*!< (@ 0x000001B8) RNG busy indication                                        */
3151 
3152     struct {
3153       __IOM uint32_t RNGBUSY    : 1;            /*!< [0..0] Reflects rng_busy output port which Consists of trng_busy
3154                                                      and prng_busy.                                                            */
3155       __IOM uint32_t TRNGBUSY   : 1;            /*!< [1..1] Reflects trng_busy.                                                */
3156       __IOM uint32_t PRNGBUSY   : 1;            /*!< [2..2] Reflects prng_busy.                                                */
3157             uint32_t            : 29;
3158     } RNGBUSY_b;
3159   } ;
3160 
3161   union {
3162     __IOM uint32_t RSTBITSCOUNTER;              /*!< (@ 0x000001BC) Resets the counter of collected bits in the TRNG           */
3163 
3164     struct {
3165       __IOM uint32_t RSTBITSCOUNTER : 1;        /*!< [0..0] Writing any value to this address resets the bits counter
3166                                                      and trng valid registers.                                                 */
3167             uint32_t            : 31;
3168     } RSTBITSCOUNTER_b;
3169   } ;
3170 
3171   union {
3172     __IOM uint32_t RNGVERSION;                  /*!< (@ 0x000001C0) This register holds the RNG version                        */
3173 
3174     struct {
3175       __IOM uint32_t EHRWIDTH192 : 1;           /*!< [0..0] EHR width selection.                                               */
3176       __IOM uint32_t CRNGTEXISTS : 1;           /*!< [1..1] CRNGT exists.                                                      */
3177       __IOM uint32_t AUTOCORREXISTS : 1;        /*!< [2..2] Auto correct exists.                                               */
3178       __IOM uint32_t TRNGTESTSBYPASSEN : 1;     /*!< [3..3] TRNG tests bypass enable.                                          */
3179       __IOM uint32_t PRNGEXISTS : 1;            /*!< [4..4] PRNG Exists.                                                       */
3180       __IOM uint32_t KATEXISTS  : 1;            /*!< [5..5] KAT exists.                                                        */
3181       __IOM uint32_t RESEEDINGEXISTS : 1;       /*!< [6..6] Reseeding exists.                                                  */
3182       __IOM uint32_t RNGUSE5SBOXES : 1;         /*!< [7..7] RNG use 5 (or 20) SBOX AES                                         */
3183             uint32_t            : 24;
3184     } RNGVERSION_b;
3185   } ;
3186 
3187   union {
3188     __IOM uint32_t RNGCLKENABLE;                /*!< (@ 0x000001C4) Writing to this register enables_disables the
3189                                                                     RNG clock.                                                 */
3190 
3191     struct {
3192       __IOM uint32_t EN         : 1;            /*!< [0..0] Writing value 0x1 enables RNG clock.                               */
3193             uint32_t            : 31;
3194     } RNGCLKENABLE_b;
3195   } ;
3196 
3197   union {
3198     __IOM uint32_t RNGDMAENABLE;                /*!< (@ 0x000001C8) Writing to this register enables_disables the
3199                                                                     RNG DMA.                                                   */
3200 
3201     struct {
3202       __IOM uint32_t EN         : 1;            /*!< [0..0] Writing value 0x1 enables RNG DMA to SRAM. The Value
3203                                                      is cleared when DMA completes its operation.                              */
3204             uint32_t            : 31;
3205     } RNGDMAENABLE_b;
3206   } ;
3207 
3208   union {
3209     __IOM uint32_t RNGDMASRCMASK;               /*!< (@ 0x000001CC) This register defines which ring-oscillator length
3210                                                                     should be used when using the RNG DMA.                     */
3211 
3212     struct {
3213       __IOM uint32_t ENSRCSEL0  : 1;            /*!< [0..0] Writing value 0x1 enables SRC_SEL 0.                               */
3214       __IOM uint32_t ENSRCSEL1  : 1;            /*!< [1..1] Writing value 0x1 enables SRC_SEL 1.                               */
3215       __IOM uint32_t ENSRCSEL2  : 1;            /*!< [2..2] Writing value 0x1 enables SRC_SEL 2.                               */
3216       __IOM uint32_t ENSRCSEL3  : 1;            /*!< [3..3] Writing value 0x1 enables SRC_SEL 3.                               */
3217             uint32_t            : 28;
3218     } RNGDMASRCMASK_b;
3219   } ;
3220 
3221   union {
3222     __IOM uint32_t RNGDMASRAMADDR;              /*!< (@ 0x000001D0) This register defines the start address of the
3223                                                                     DMA for the TRNG data.                                     */
3224 
3225     struct {
3226       __IOM uint32_t RNGSRAMDMAADDR : 11;       /*!< [10..0] Defines the start address of the DMA for the TRNG data.           */
3227             uint32_t            : 21;
3228     } RNGDMASRAMADDR_b;
3229   } ;
3230   __IM  uint32_t  RESERVED7;
3231 
3232   union {
3233     __IOM uint32_t RNGWATCHDOGVAL;              /*!< (@ 0x000001D8) This register defines the number of 192-bits
3234                                                                     samples that the DMA collects per RNG configuration.bitfie
3235                                                                     d 7:0 RNG_SAMPLES_NUM rw 0x0 Defines the
3236                                                                     number of 192-bits samples that the DMA
3237                                                                     collects per RNG configuration.bitfield
3238                                                                     31:8 RESERVED rw 0x0 ReservedThis register
3239                                                                     defines the maximum number of clock cycles
3240                                                                     per TRNG collection of 192 samples. If the
3241                                                                     number of cycles for a collection exceeds
3242                                                                     this threshold, TRNG signals an interrupt.                 */
3243 
3244     struct {
3245       __IOM uint32_t RNGWATCHDOGVAL : 32;       /*!< [31..0] Defines the maximum number of clock cycles per TRNG
3246                                                      collection of 192 samples. If the number of cycles for
3247                                                      a collection exceeds this threshold, TRNG signals an interrupt.           */
3248     } RNGWATCHDOGVAL_b;
3249   } ;
3250 
3251   union {
3252     __IOM uint32_t RNGDMASTATUS;                /*!< (@ 0x000001DC) This register holds the RNG DMA status.                    */
3253 
3254     struct {
3255       __IOM uint32_t RNGDMABUSY : 1;            /*!< [0..0] Indicates whether DMA is busy.                                     */
3256       __IOM uint32_t DMASRCSEL  : 2;            /*!< [2..1] The active ring oscillator length using by DMA                     */
3257       __IOM uint32_t NUMOFSAMPLES : 8;          /*!< [10..3] Number of samples already collected in the current ring
3258                                                      oscillator chain length.                                                  */
3259             uint32_t            : 21;
3260     } RNGDMASTATUS_b;
3261   } ;
3262   __IM  uint32_t  RESERVED8[104];
3263 
3264   union {
3265     __IOM uint32_t CHACHACONTROLREG;            /*!< (@ 0x00000380) CHACHA general configuration.                              */
3266 
3267     struct {
3268       __IOM uint32_t CHACHAORSALSA : 1;         /*!< [0..0] Core:                                                              */
3269       __IOM uint32_t INITFROMHOST : 1;          /*!< [1..1] Start init for new Message:                                        */
3270       __IOM uint32_t CALCKEYFORPOLY1305 : 1;    /*!< [2..2] Only if ChaCha core:                                               */
3271       __IOM uint32_t KEYLEN     : 1;            /*!< [3..3] For All Core:                                                      */
3272       __IOM uint32_t NUMOFROUNDS : 2;           /*!< [5..4] The core of ChaCha is a hash function which based on
3273                                                      rotation operations. The hash function consist in application
3274                                                      of 20 rounds (default value). In additional, ChaCha have
3275                                                      two variants (they work exactly as the original algorithm):
3276                                                      ChaCha20_8 and ChaCha20_12 (using 8 and 12 rounds).                       */
3277             uint32_t            : 3;
3278       __IOM uint32_t RESETBLOCKCNT : 1;         /*!< [9..9] For new message                                                    */
3279       __IOM uint32_t USEIV96BIT : 1;            /*!< [10..10] If use 96bit IV                                                  */
3280             uint32_t            : 21;
3281     } CHACHACONTROLREG_b;
3282   } ;
3283 
3284   union {
3285     __IOM uint32_t CHACHAVERSION;               /*!< (@ 0x00000384) CHACHA Version                                             */
3286 
3287     struct {
3288       __IOM uint32_t CHACHAVERSION : 32;        /*!< [31..0] CHACHA version.                                                   */
3289     } CHACHAVERSION_b;
3290   } ;
3291 
3292   union {
3293     __IOM uint32_t CHACHAKEY0;                  /*!< (@ 0x00000388) bits 255:224 of CHACHA Key                                 */
3294 
3295     struct {
3296       __IOM uint32_t CHACHAKEY0 : 32;           /*!< [31..0] bits 255:224 of CHACHA Key                                        */
3297     } CHACHAKEY0_b;
3298   } ;
3299 
3300   union {
3301     __IOM uint32_t CHACHAKEY1;                  /*!< (@ 0x0000038C) bits 223:192 of CHACHA Key                                 */
3302 
3303     struct {
3304       __IOM uint32_t CHACHAKEY1 : 32;           /*!< [31..0] bits 223:192 of CHACHA Key                                        */
3305     } CHACHAKEY1_b;
3306   } ;
3307 
3308   union {
3309     __IOM uint32_t CHACHAKEY2;                  /*!< (@ 0x00000390) bits 191:160 of CHACHA Key                                 */
3310 
3311     struct {
3312       __IOM uint32_t CHACHAKEY2 : 32;           /*!< [31..0] bits191:160 of CHACHA Key                                         */
3313     } CHACHAKEY2_b;
3314   } ;
3315 
3316   union {
3317     __IOM uint32_t CHACHAKEY3;                  /*!< (@ 0x00000394) bits159:128 of CHACHA Key                                  */
3318 
3319     struct {
3320       __IOM uint32_t CHACHAKEY3 : 32;           /*!< [31..0] bits 159:128 of CHACHA Key                                        */
3321     } CHACHAKEY3_b;
3322   } ;
3323 
3324   union {
3325     __IOM uint32_t CHACHAKEY4;                  /*!< (@ 0x00000398) bits 127:96 of CHACHA Key                                  */
3326 
3327     struct {
3328       __IOM uint32_t CHACHAKEY4 : 32;           /*!< [31..0] bits 127:96 of CHACHA Key                                         */
3329     } CHACHAKEY4_b;
3330   } ;
3331 
3332   union {
3333     __IOM uint32_t CHACHAKEY5;                  /*!< (@ 0x0000039C) bits 95:64 of CHACHA Key                                   */
3334 
3335     struct {
3336       __IOM uint32_t CHACHAKEY5 : 32;           /*!< [31..0] bits 95:64 of CHACHA Key                                          */
3337     } CHACHAKEY5_b;
3338   } ;
3339 
3340   union {
3341     __IOM uint32_t CHACHAKEY6;                  /*!< (@ 0x000003A0) bits 63:32 of CHACHA Key                                   */
3342 
3343     struct {
3344       __IOM uint32_t CHACHAKEY6 : 32;           /*!< [31..0] bits 63:32 of CHACHA Key                                          */
3345     } CHACHAKEY6_b;
3346   } ;
3347 
3348   union {
3349     __IOM uint32_t CHACHAKEY7;                  /*!< (@ 0x000003A4) bits 31:0 of CHACHA Key                                    */
3350 
3351     struct {
3352       __IOM uint32_t CHACHAKEY7 : 32;           /*!< [31..0] bits 31:0 of CHACHA Key                                           */
3353     } CHACHAKEY7_b;
3354   } ;
3355 
3356   union {
3357     __IOM uint32_t CHACHAIV0;                   /*!< (@ 0x000003A8) bits 31:0 of CHACHA_IV0 register                           */
3358 
3359     struct {
3360       __IOM uint32_t CHACHAIV0  : 32;           /*!< [31..0] bits 31:0 of CHACHA_IV0 register                                  */
3361     } CHACHAIV0_b;
3362   } ;
3363 
3364   union {
3365     __IOM uint32_t CHACHAIV1;                   /*!< (@ 0x000003AC) bits 31:0 of CHACHA_IV1 register                           */
3366 
3367     struct {
3368       __IOM uint32_t CHACHAIV1  : 32;           /*!< [31..0] bits 31:0 of CHACHA_IV1 register                                  */
3369     } CHACHAIV1_b;
3370   } ;
3371 
3372   union {
3373     __IOM uint32_t CHACHABUSY;                  /*!< (@ 0x000003B0) This register is set when the CHACHA_SALSA core
3374                                                                     is active                                                  */
3375 
3376     struct {
3377       __IOM uint32_t CHACHABUSY : 1;            /*!< [0..0] CHACHA_BUSY Register. This register is set when the CHACHA_SALSA
3378                                                      core is active.                                                           */
3379             uint32_t            : 31;
3380     } CHACHABUSY_b;
3381   } ;
3382 
3383   union {
3384     __IOM uint32_t CHACHAHWFLAGS;               /*!< (@ 0x000003B4) This register holds the pre-synthesis HW flag
3385                                                                     configuration of the CHACHA_SALSA engine                   */
3386 
3387     struct {
3388       __IOM uint32_t CHACHAEXISTS : 1;          /*!< [0..0] If this flag is set, the Salsa_ChaCha engine include
3389                                                      ChaCha implementation:                                                    */
3390       __IOM uint32_t SALSAEXISTS : 1;           /*!< [1..1] If this flag is set, the Salsa_ChaCha engine include
3391                                                      Salsa implementation:                                                     */
3392       __IOM uint32_t FASTCHACHA : 1;            /*!< [2..2] If this flag is set, the next matrix calculated when
3393                                                      the current one is written to data output path (same flag
3394                                                      for Salsa core):                                                          */
3395             uint32_t            : 29;
3396     } CHACHAHWFLAGS_b;
3397   } ;
3398 
3399   union {
3400     __IOM uint32_t CHACHABLOCKCNTLSB;           /*!< (@ 0x000003B8) The two first words (n) in the last row of the
3401                                                                     cipher matrix are the block counter. At
3402                                                                     the end of each block (512b), the block_cnt
3403                                                                     for the next block is written by HW to the
3404                                                                     block_cnt_lsb and block_cnt_msb registers.
3405                                                                     Need reset block counter , if start new
3406                                                                     message.                                                   */
3407 
3408     struct {
3409       __IOM uint32_t CHACHABLOCKCNTLSB : 32;    /*!< [31..0] bits 31:0 of CHACHA_BLOCK_CNT_LSB register.                       */
3410     } CHACHABLOCKCNTLSB_b;
3411   } ;
3412 
3413   union {
3414     __IOM uint32_t CHACHABLOCKCNTMSB;           /*!< (@ 0x000003BC) The two first words (n) in the last row of the
3415                                                                     cipher matrix are the block counter. At
3416                                                                     the end of each block (512b), the block_cnt
3417                                                                     for the next block is written by HW to the
3418                                                                     block_cnt_lsb and block_cnt_msb registers.
3419                                                                     Need reset block counter , if start new
3420                                                                     message.                                                   */
3421 
3422     struct {
3423       __IOM uint32_t CHACHABLOCKCNTMSB : 32;    /*!< [31..0] bits 31:0 of CHACHA_BLOCK_CNT_MSB register.                       */
3424     } CHACHABLOCKCNTMSB_b;
3425   } ;
3426 
3427   union {
3428     __IOM uint32_t CHACHASWRESET;               /*!< (@ 0x000003C0) Resets CHACHA_SALSA engine.                                */
3429 
3430     struct {
3431       __IOM uint32_t CHACHSWRESET : 1;          /*!< [0..0] Writing to this address resets the only FSM of CHACHA
3432                                                      engine. The reset takes 4 CORE_CLK cycles.                                */
3433             uint32_t            : 31;
3434     } CHACHASWRESET_b;
3435   } ;
3436 
3437   union {
3438     __IOM uint32_t CHACHAFORPOLYKEY0;           /*!< (@ 0x000003C4) bits 255:224 of CHACHA_FOR_POLY_KEY                        */
3439 
3440     struct {
3441       __IOM uint32_t CHACHAFORPOLYKEY0 : 32;    /*!< [31..0] bits 255:224 of CHACHA_FOR_POLY_KEY                               */
3442     } CHACHAFORPOLYKEY0_b;
3443   } ;
3444 
3445   union {
3446     __IOM uint32_t CHACHAFORPOLYKEY1;           /*!< (@ 0x000003C8) bits 223:192 of CHACHA_FOR_POLY_KEY                        */
3447 
3448     struct {
3449       __IOM uint32_t CHACHAFORPOLYKEY1 : 32;    /*!< [31..0] bits 223:192 of CHACHA_FOR_POLY_KEY                               */
3450     } CHACHAFORPOLYKEY1_b;
3451   } ;
3452 
3453   union {
3454     __IOM uint32_t CHACHAFORPOLYKEY2;           /*!< (@ 0x000003CC) bits191:160 of CHACHA_FOR_POLY_KEY                         */
3455 
3456     struct {
3457       __IOM uint32_t CHACHAFORPOLYKEY2 : 32;    /*!< [31..0] bits191:160 of CHACHA_FOR_POLY_KEY                                */
3458     } CHACHAFORPOLYKEY2_b;
3459   } ;
3460 
3461   union {
3462     __IOM uint32_t CHACHAFORPOLYKEY3;           /*!< (@ 0x000003D0) bits159:128 of CHACHA_FOR_POLY_KEY                         */
3463 
3464     struct {
3465       __IOM uint32_t CHACHAFORPOLYKEY3 : 32;    /*!< [31..0] bits 159:128 of CHACHA_FOR_POLY_KEY                               */
3466     } CHACHAFORPOLYKEY3_b;
3467   } ;
3468 
3469   union {
3470     __IOM uint32_t CHACHAFORPOLYKEY4;           /*!< (@ 0x000003D4) bits 127:96 of CHACHA_FOR_POLY_KEY                         */
3471 
3472     struct {
3473       __IOM uint32_t CHACHAFORPOLYKEY4 : 32;    /*!< [31..0] bits 127:96 of CHACHA_FOR_POLY_KEY                                */
3474     } CHACHAFORPOLYKEY4_b;
3475   } ;
3476 
3477   union {
3478     __IOM uint32_t CHACHAFORPOLYKEY5;           /*!< (@ 0x000003D8) bits 95:64 of CHACHA_FOR_POLY_KEY                          */
3479 
3480     struct {
3481       __IOM uint32_t CHACHAFORPOLYKEY5 : 32;    /*!< [31..0] bits 95:64 of CHACHA_FOR_POLY_KEY                                 */
3482     } CHACHAFORPOLYKEY5_b;
3483   } ;
3484 
3485   union {
3486     __IOM uint32_t CHACHAFORPOLYKEY6;           /*!< (@ 0x000003DC) bits 63:32 of CHACHA_FOR_POLY_KEY                          */
3487 
3488     struct {
3489       __IOM uint32_t CHACHAFORPOLYKEY6 : 32;    /*!< [31..0] bits 63:32 of CHACHA_FOR_POLY_KEY                                 */
3490     } CHACHAFORPOLYKEY6_b;
3491   } ;
3492 
3493   union {
3494     __IOM uint32_t CHACHAFORPOLYKEY7;           /*!< (@ 0x000003E0) bits 31:0 of CHACHA_FOR_POLY_KEY                           */
3495 
3496     struct {
3497       __IOM uint32_t CHACHAFORPOLYKEY7 : 32;    /*!< [31..0] bits 31:0 of CHACHA_FOR_POLY_KEY                                  */
3498     } CHACHAFORPOLYKEY7_b;
3499   } ;
3500 
3501   union {
3502     __IOM uint32_t CHACHABYTEWORDORDERCNTLREG;  /*!< (@ 0x000003E4) CHACHA_SALSA DATA ORDER configuration.                     */
3503 
3504     struct {
3505       __IOM uint32_t CHACHADINWORDORDER : 1;    /*!< [0..0] Change the words order of the input data.                          */
3506       __IOM uint32_t CHACHADINBYTEORDER : 1;    /*!< [1..1] Change the byte order of the input data.                           */
3507       __IOM uint32_t CHACHACOREMATRIXLBEORDER : 1;/*!< [2..2] Change the quarter of a matrix order in core                     */
3508       __IOM uint32_t CHACHADOUTWORDORDER : 1;   /*!< [3..3] Change the words order of the output data.                         */
3509       __IOM uint32_t CHACHADOUTBYTEORDER : 1;   /*!< [4..4] Change the byte order of the output data.                          */
3510             uint32_t            : 27;
3511     } CHACHABYTEWORDORDERCNTLREG_b;
3512   } ;
3513 
3514   union {
3515     __IOM uint32_t CHACHADEBUGREG;              /*!< (@ 0x000003E8) This register is used to debug the CHACHA engine           */
3516 
3517     struct {
3518       __IOM uint32_t CHACHADEBUGFSMSTATE : 2;   /*!< [1..0] CHACHA_DEBUG_FSM_STATE                                             */
3519             uint32_t            : 30;
3520     } CHACHADEBUGREG_b;
3521   } ;
3522   __IM  uint32_t  RESERVED9[5];
3523 
3524   union {
3525     __IOM uint32_t AESKEY00;                    /*!< (@ 0x00000400) bits 31:0 of AES Key0 (used as the AES key in
3526                                                                     non-tunneling operations, and as the first
3527                                                                     tunnel stage key in tunneling operations).                 */
3528 
3529     struct {
3530       __IOM uint32_t AESKEY00   : 32;           /*!< [31..0] bits 31:0 of AES Key0.                                            */
3531     } AESKEY00_b;
3532   } ;
3533 
3534   union {
3535     __IOM uint32_t AESKEY01;                    /*!< (@ 0x00000404) bits 63:32 of AES Key0 (used as the AES key in
3536                                                                     non-tunneling operations, and as the first
3537                                                                     tunnel stage key in tunneling operations).                 */
3538 
3539     struct {
3540       __IOM uint32_t AESKEY01   : 32;           /*!< [31..0] bits 63:32 of AES Key0.                                           */
3541     } AESKEY01_b;
3542   } ;
3543 
3544   union {
3545     __IOM uint32_t AESKEY02;                    /*!< (@ 0x00000408) bits 95:64 of AES Key0 (used as the AES key in
3546                                                                     non-tunneling operations, and as the first
3547                                                                     tunnel stage key in tunneling operations).                 */
3548 
3549     struct {
3550       __IOM uint32_t AESKEY02   : 32;           /*!< [31..0] bits 95:64 of AES Key0.                                           */
3551     } AESKEY02_b;
3552   } ;
3553 
3554   union {
3555     __IOM uint32_t AESKEY03;                    /*!< (@ 0x0000040C) bits 127:96 of AES Key0 (used as the AES key
3556                                                                     in non-tunneling operations, and as the
3557                                                                     first tunnel stage key in tunneling operations).           */
3558 
3559     struct {
3560       __IOM uint32_t AESKEY03   : 32;           /*!< [31..0] bits 127:96 of AES Key0.                                          */
3561     } AESKEY03_b;
3562   } ;
3563 
3564   union {
3565     __IOM uint32_t AESKEY04;                    /*!< (@ 0x00000410) bits 159:128 of AES Key0 (used as the AES key
3566                                                                     in non-tunneling operations, and as the
3567                                                                     first tunnel stage key in tunneling operations).           */
3568 
3569     struct {
3570       __IOM uint32_t AESKEY04   : 32;           /*!< [31..0] bits 159:128 of AES Key0 .                                        */
3571     } AESKEY04_b;
3572   } ;
3573 
3574   union {
3575     __IOM uint32_t AESKEY05;                    /*!< (@ 0x00000414) bits 191:160 of AES Key0 (used as the AES key
3576                                                                     in non-tunneling operations, and as the
3577                                                                     first tunnel stage key in tunneling operations).           */
3578 
3579     struct {
3580       __IOM uint32_t AESKEY05   : 32;           /*!< [31..0] bits 191:160 of AES Key0.                                         */
3581     } AESKEY05_b;
3582   } ;
3583 
3584   union {
3585     __IOM uint32_t AESKEY06;                    /*!< (@ 0x00000418) bits 223:192 of AES Key0 (used as the AES key
3586                                                                     in non-tunneling operations, and as the
3587                                                                     first tunnel stage key in tunneling operations).           */
3588 
3589     struct {
3590       __IOM uint32_t AESKEY06   : 32;           /*!< [31..0] bits 223:192 of AES Key0.                                         */
3591     } AESKEY06_b;
3592   } ;
3593 
3594   union {
3595     __IOM uint32_t AESKEY07;                    /*!< (@ 0x0000041C) bits 255:224 of AES Key0 (used as the AES key
3596                                                                     in non-tunneling operations, and as the
3597                                                                     first tunnel stage key in tunneling operations).           */
3598 
3599     struct {
3600       __IOM uint32_t AESKEY07   : 32;           /*!< [31..0] bits 255:224 of AES Key0.                                         */
3601     } AESKEY07_b;
3602   } ;
3603 
3604   union {
3605     __IOM uint32_t AESKEY10;                    /*!< (@ 0x00000420) bits 31:0 of AES Key1 (used as the second AES
3606                                                                     tunnel stage key in tunneling operations).                 */
3607 
3608     struct {
3609       __IOM uint32_t AESKEY10   : 32;           /*!< [31..0] bits 31:0 of AES Key1.                                            */
3610     } AESKEY10_b;
3611   } ;
3612 
3613   union {
3614     __IOM uint32_t AESKEY11;                    /*!< (@ 0x00000424) bits 63:32 of AES Key1 (used as the second AES
3615                                                                     tunnel stage key in tunneling operations).                 */
3616 
3617     struct {
3618       __IOM uint32_t AESKEY11   : 32;           /*!< [31..0] bits 63:32 of AES Key1.                                           */
3619     } AESKEY11_b;
3620   } ;
3621 
3622   union {
3623     __IOM uint32_t AESKEY12;                    /*!< (@ 0x00000428) bits 95:64 of AES Key1 (used as the second AES
3624                                                                     tunnel stage key in tunneling operations).                 */
3625 
3626     struct {
3627       __IOM uint32_t AESKEY12   : 32;           /*!< [31..0] bits 95:64 of AES Key1.                                           */
3628     } AESKEY12_b;
3629   } ;
3630 
3631   union {
3632     __IOM uint32_t AESKEY13;                    /*!< (@ 0x0000042C) bits 127:96 of AES Key1 (used as the second AES
3633                                                                     tunnel stage key in tunneling operations).                 */
3634 
3635     struct {
3636       __IOM uint32_t AESKEY13   : 32;           /*!< [31..0] bits 127:96 of AES Key1.                                          */
3637     } AESKEY13_b;
3638   } ;
3639 
3640   union {
3641     __IOM uint32_t AESKEY14;                    /*!< (@ 0x00000430) bits 159:128 of AES Key1 (used as the second
3642                                                                     AES tunnel stage key in tunneling operations).             */
3643 
3644     struct {
3645       __IOM uint32_t AESKEY14   : 32;           /*!< [31..0] bits 159:128 of AES Key1.                                         */
3646     } AESKEY14_b;
3647   } ;
3648 
3649   union {
3650     __IOM uint32_t AESKEY15;                    /*!< (@ 0x00000434) bits 191:160 of AES Key1 (used as the second
3651                                                                     AES tunnel stage key in tunneling operations).             */
3652 
3653     struct {
3654       __IOM uint32_t AESKEY15   : 32;           /*!< [31..0] bits 191:160 of AES Key1.                                         */
3655     } AESKEY15_b;
3656   } ;
3657 
3658   union {
3659     __IOM uint32_t AESKEY16;                    /*!< (@ 0x00000438) bits 223:192 of AES Key1 (used as the second
3660                                                                     AES tunnel stage key in tunneling operations).             */
3661 
3662     struct {
3663       __IOM uint32_t AESKEY16   : 32;           /*!< [31..0] bits 223:192 of AES Key1.                                         */
3664     } AESKEY16_b;
3665   } ;
3666 
3667   union {
3668     __IOM uint32_t AESKEY17;                    /*!< (@ 0x0000043C) bits 255:224 of AES Key1 (used as the second
3669                                                                     AES tunnel stage key in tunneling operations).             */
3670 
3671     struct {
3672       __IOM uint32_t AESKEY17   : 32;           /*!< [31..0] bits 255:224 of AES Key1.                                         */
3673     } AESKEY17_b;
3674   } ;
3675 
3676   union {
3677     __IOM uint32_t AESIV00;                     /*!< (@ 0x00000440) bits 31:0 of AES_IV0 register. AES IV0 is used
3678                                                                     as the AES IV (Initialization Value) register
3679                                                                     in non-tunneling operations,and as the first
3680                                                                     tunnel stage IV register in tunneling operations.The
3681                                                                     IV register should be loaded according to
3682                                                                     the AES mode:in AES CBC_CBC-MAC - the AES
3683                                                                     IV register should be loaded with the IV
3684                                                                     (initialization vector).in XTS-AES - the
3685                                                                     AES IV register should be loaded with the
3686                                                                     T value (unless the HW T calculation mode
3687                                                                     is active, in which the T value is calculated
3688                                                                     by the HW                                                  */
3689 
3690     struct {
3691       __IOM uint32_t AESIV00    : 32;           /*!< [31..0] bits 31:0 of AES_IV0 register.                                    */
3692     } AESIV00_b;
3693   } ;
3694 
3695   union {
3696     __IOM uint32_t AESIV01;                     /*!< (@ 0x00000444) bits 63:32 of AES_IV0 128b register.For the description
3697                                                                     of AES_IV0, see the AES_IV_0_0 register
3698                                                                     description                                                */
3699 
3700     struct {
3701       __IOM uint32_t AESIV01    : 32;           /*!< [31..0] bits 63:32 of AES_IV0 register.                                   */
3702     } AESIV01_b;
3703   } ;
3704 
3705   union {
3706     __IOM uint32_t AESIV02;                     /*!< (@ 0x00000448) bits 95:64 of AES_IV0 128b register.For the description
3707                                                                     of AES_IV0, see the AES_IV_0_0 register
3708                                                                     description                                                */
3709 
3710     struct {
3711       __IOM uint32_t AESIV02    : 32;           /*!< [31..0] bits 95:64 of AES_IV0 register.                                   */
3712     } AESIV02_b;
3713   } ;
3714 
3715   union {
3716     __IOM uint32_t AESIV03;                     /*!< (@ 0x0000044C) bits 127:96 of AES_IV0 128b register.For the
3717                                                                     description of AES_IV0, see the AES_IV_0_0
3718                                                                     register description                                       */
3719 
3720     struct {
3721       __IOM uint32_t AESIV03    : 32;           /*!< [31..0] bits 127:96 of AES_IV0 register.                                  */
3722     } AESIV03_b;
3723   } ;
3724 
3725   union {
3726     __IOM uint32_t AESIV10;                     /*!< (@ 0x00000450) bits 31:0 of AES_IV1 128b register.AES IV1 is
3727                                                                     used as the AES IV (Initialization Value)
3728                                                                     register as the second tunnel stage IV register
3729                                                                     in tunneling operations.The IV register
3730                                                                     should be loaded according to the AES mode:in
3731                                                                     AES CBC_CBC-MAC - the AES IV register should
3732                                                                     be loaded with the IV (initialization vector).in
3733                                                                     XTS-AES - the AES IV register should be
3734                                                                     loaded with the T value (unless the HW T
3735                                                                     calculation mode is active, in which the
3736                                                                     T value is calculated by the HW.                           */
3737 
3738     struct {
3739       __IOM uint32_t AESIV10    : 32;           /*!< [31..0] bits 31:0 of AES_IV1 register.                                    */
3740     } AESIV10_b;
3741   } ;
3742 
3743   union {
3744     __IOM uint32_t AESIV11;                     /*!< (@ 0x00000454) bits 63:32 of AES_IV1 128b register.For the description
3745                                                                     of AES_IV1, see the AES_IV_1_0 register
3746                                                                     description                                                */
3747 
3748     struct {
3749       __IOM uint32_t AESIV11    : 32;           /*!< [31..0] bits 63:32 of AES_IV1 register.                                   */
3750     } AESIV11_b;
3751   } ;
3752 
3753   union {
3754     __IOM uint32_t AESIV12;                     /*!< (@ 0x00000458) bits 95:64 of AES_IV1 128b register.For the description
3755                                                                     of AES_IV1, see the AES_IV_1_0 register
3756                                                                     description                                                */
3757 
3758     struct {
3759       __IOM uint32_t AESIV12    : 32;           /*!< [31..0] bits 95:64 of AES_IV1 register.                                   */
3760     } AESIV12_b;
3761   } ;
3762 
3763   union {
3764     __IOM uint32_t AESIV13;                     /*!< (@ 0x0000045C) bits 127:96 of AES_IV1 128b register.For the
3765                                                                     description of AES_IV1, see the AES_IV_1_0
3766                                                                     register description                                       */
3767 
3768     struct {
3769       __IOM uint32_t AESIV13    : 32;           /*!< [31..0] bits 127:96 of AES_IV1 register.                                  */
3770     } AESIV13_b;
3771   } ;
3772 
3773   union {
3774     __IOM uint32_t AESCTR00;                    /*!< (@ 0x00000460) bits 31:0 of AES_CTR0 128b register.AES CTR0
3775                                                                     is used as the AES CTR (counter) register
3776                                                                     in non-tunneling operations, and as the
3777                                                                     first tunnel stage CTR register in tunneling
3778                                                                     operations.The CTR register should be loaded
3779                                                                     according to the AES mode:in AES CTR_GCTR
3780                                                                     - the AES CTR register should be loaded
3781                                                                     with the counter value.in XTS-AES - the
3782                                                                     AES CTR register should be loaded with the
3783                                                                     i value (in order to calculate the T value
3784                                                                     from it, if HW T calculation is supported).                */
3785 
3786     struct {
3787       __IOM uint32_t AESCTR00   : 32;           /*!< [31..0] bits 31:0 of AES_CTR0 register.                                   */
3788     } AESCTR00_b;
3789   } ;
3790 
3791   union {
3792     __IOM uint32_t AESCTR01;                    /*!< (@ 0x00000464) bits 63:32 of AES_CTR0 128b register.For the
3793                                                                     description of AES_CTR0, see the AES_CTR_0_0
3794                                                                     register description.                                      */
3795 
3796     struct {
3797       __IOM uint32_t AESCTR01   : 32;           /*!< [31..0] bits 63:32 of AES_CTR0 register.                                  */
3798     } AESCTR01_b;
3799   } ;
3800 
3801   union {
3802     __IOM uint32_t AESCTR02;                    /*!< (@ 0x00000468) bits 95:64 of AES_CTR0 128b register.For the
3803                                                                     description of AES_CTR0, see the AES_CTR_0_0
3804                                                                     register description.                                      */
3805 
3806     struct {
3807       __IOM uint32_t AESCTR02   : 32;           /*!< [31..0] bits 95:64 of AES_CTR0 register.                                  */
3808     } AESCTR02_b;
3809   } ;
3810 
3811   union {
3812     __IOM uint32_t AESCTR03;                    /*!< (@ 0x0000046C) bits 127:96 of AES_CTR0 128b register.For the
3813                                                                     description of AES_CTR0, see the AES_CTR_0_0
3814                                                                     register description.                                      */
3815 
3816     struct {
3817       __IOM uint32_t AESCTR03   : 32;           /*!< [31..0] bits 127:96 of AES_CTR0 register.                                 */
3818     } AESCTR03_b;
3819   } ;
3820 
3821   union {
3822     __IOM uint32_t AESBUSY;                     /*!< (@ 0x00000470) This register is set when the AES core is active           */
3823 
3824     struct {
3825       __IOM uint32_t AESBUSY    : 1;            /*!< [0..0] AES_BUSY register. This register is set when the AES
3826                                                      core is active                                                            */
3827             uint32_t            : 31;
3828     } AESBUSY_b;
3829   } ;
3830   __IM  uint32_t  RESERVED10;
3831 
3832   union {
3833     __IOM uint32_t AESSK;                       /*!< (@ 0x00000478) writing to this address causes sampling of the
3834                                                                     HW key to the AES_KEY0 register                            */
3835 
3836     struct {
3837       __IOM uint32_t AESSK      : 1;            /*!< [0..0] writing to this address causes sampling of the HW key
3838                                                      to the AES_KEY0 register                                                  */
3839             uint32_t            : 31;
3840     } AESSK_b;
3841   } ;
3842 
3843   union {
3844     __IOM uint32_t AESCMACINIT;                 /*!< (@ 0x0000047C) Writing to this address triggers the AES engine
3845                                                                     generating of K1 and K2 for AES CMAC operations.
3846                                                                     Note: This is a special register, affected
3847                                                                     by internal logic. Test result of this register
3848                                                                     is NA.                                                     */
3849 
3850     struct {
3851       __IOM uint32_t AESCMACINIT : 1;           /*!< [0..0] Writing to this address starts the generating of K1 and
3852                                                      K2 for AES CMAC operations                                                */
3853             uint32_t            : 31;
3854     } AESCMACINIT_b;
3855   } ;
3856   __IM  uint32_t  RESERVED11[13];
3857 
3858   union {
3859     __IOM uint32_t AESSK1;                      /*!< (@ 0x000004B4) writing to this address causes sampling of the
3860                                                                     HW key to the AES_KEY1 register                            */
3861 
3862     struct {
3863       __IOM uint32_t AESSK1     : 1;            /*!< [0..0] writing to this address causes sampling of the HW key
3864                                                      to the AES_KEY1 register                                                  */
3865             uint32_t            : 31;
3866     } AESSK1_b;
3867   } ;
3868   __IM  uint32_t  RESERVED12;
3869 
3870   union {
3871     __IOM uint32_t AESREMAININGBYTES;           /*!< (@ 0x000004BC) This register should be set with the amount of
3872                                                                     remaining bytes until the end of the current
3873                                                                     AES operation. The AES engine counts down
3874                                                                     from this value to determine the last _
3875                                                                     one before last blocks in AES CMAC, XTS
3876                                                                     AES and AES CCM.                                           */
3877 
3878     struct {
3879       __IOM uint32_t AESREMAININGBYTES : 32;    /*!< [31..0] This register should be set with the amount of remaining
3880                                                      bytes until the end of the current AES operation. The AES
3881                                                      engine counts down from this value to determine the last
3882                                                      _ one before last blocks in AES CMAC, XTS AES and AES CCM.                */
3883     } AESREMAININGBYTES_b;
3884   } ;
3885 
3886   union {
3887     __IOM uint32_t AESCONTROL;                  /*!< (@ 0x000004C0) This register holds the configuration of the
3888                                                                     AES engine. Note: This is a special register,
3889                                                                     affected by internal logic. Test result
3890                                                                     of this register is NA.                                    */
3891 
3892     struct {
3893       __IOM uint32_t DECKEY0    : 1;            /*!< [0..0] This field determines whether the AES performs Decrypt_Encrypt
3894                                                      operations, in non-tunneling operations:                                  */
3895       __IOM uint32_t MODE0ISCBCCTS : 1;         /*!< [1..1] If MODE_KEY0 is set to 3b001 (CBC), and this field is
3896                                                      set - the mode is CBC-CTS. In addition, If MODE_KEY0 is
3897                                                      set to 3b010 (CTR), and this field is set - the mode is
3898                                                      GCTR.                                                                     */
3899       __IOM uint32_t MODEKEY0   : 3;            /*!< [4..2] This field determines the AES mode in non tunneling operations,
3900                                                      and the AES mode of the first stage in tunneling operations:              */
3901       __IOM uint32_t MODEKEY1   : 3;            /*!< [7..5] This field determines the AES mode of the second stage
3902                                                      operation in tunneling operations:                                        */
3903       __IOM uint32_t CBCISESSIV : 1;            /*!< [8..8] If MODE_KEY0 is set to 3b001 (CBC), and this field is
3904                                                      set - the mode is CBC with ESSIV.                                         */
3905             uint32_t            : 1;
3906       __IOM uint32_t AESTUNNELISON : 1;         /*!< [10..10] This field determines whether the AES performs dual-tunnel
3907                                                      operations or standard non-tunneling operations:                          */
3908       __IOM uint32_t CBCISBITLOCKER : 1;        /*!< [11..11] If MODE_KEY0 is set to 3b001 (CBC), and this field
3909                                                      is set - the mode isBITLOCKER.                                            */
3910       __IOM uint32_t NKKEY0     : 2;            /*!< [13..12] This field determines the AES Key length in non tunneling
3911                                                      operations, and the AES key length of the first stage in
3912                                                      tunneling operations:                                                     */
3913       __IOM uint32_t NKKEY1     : 2;            /*!< [15..14] This field determines the AES key length of the second
3914                                                      stage operation in tunneling operations:                                  */
3915             uint32_t            : 6;
3916       __IOM uint32_t AESTUNNEL1DECRYPT : 1;     /*!< [22..22] This field determines whether the second tunnel stage
3917                                                      performs encrypt or decrypt operation :                                   */
3918       __IOM uint32_t AESTUNB1USESPADDEDDATAIN : 1;/*!< [23..23] This field determines, for tunneling operations, the
3919                                                      data that is fed to the second tunneling stage:                           */
3920       __IOM uint32_t AESTUNNEL0ENCRYPT : 1;     /*!< [24..24] This field determines whether the first tunnel stage
3921                                                      performs encrypt or decrypt operation :                                   */
3922       __IOM uint32_t AESOUTPUTMIDTUNNELDATA : 1;/*!< [25..25] This fields determines whether the AES output is the
3923                                                      result of the first or second tunneling stage:                            */
3924       __IOM uint32_t AESTUNNELB1PADEN : 1;      /*!< [26..26] This field determines whether the input data to the
3925                                                      second tunnel stage is padded with zeroes (according to
3926                                                      the remaining_bytes value) or not:                                        */
3927             uint32_t            : 1;
3928       __IOM uint32_t AESOUTMIDTUNTOHASH : 1;    /*!< [28..28] This field determines for AES-TO-HASH-AND-DOUT tunneling
3929                                                      operations, whether the AES outputs to the HASH the result
3930                                                      of the first or the second tunneling stage:                               */
3931       __IOM uint32_t AESXORCRYPTOKEY : 1;       /*!< [29..29] This field determines the value that is written to
3932                                                      AES_KEY0, when AES_SK is kicked:                                          */
3933             uint32_t            : 1;
3934       __IOM uint32_t DIRECTACCESS : 1;          /*!< [31..31] Using direct access and not the din-dout interface               */
3935     } AESCONTROL_b;
3936   } ;
3937   __IM  uint32_t  RESERVED13;
3938 
3939   union {
3940     __IOM uint32_t AESHWFLAGS;                  /*!< (@ 0x000004C8) This register holds the pre-synthesis HW flag
3941                                                                     configuration of the AES engine                            */
3942 
3943     struct {
3944       __IOM uint32_t SUPPORT256192KEY : 1;      /*!< [0..0] the SUPPORT_256_192_KEY flag                                       */
3945       __IOM uint32_t AESLARGERKEK : 1;          /*!< [1..1] the AES_LARGE_RKEK flag                                            */
3946       __IOM uint32_t DPACNTRMSREXIST : 1;       /*!< [2..2] the DPA_CNTRMSR_EXIST flag                                         */
3947       __IOM uint32_t CTREXIST   : 1;            /*!< [3..3] the CTR_EXIST flag                                                 */
3948       __IOM uint32_t ONLYENCRYPT : 1;           /*!< [4..4] the ONLY_ENCRYPT flag                                              */
3949       __IOM uint32_t USESBOXTABLE : 1;          /*!< [5..5] the USE_SBOX_TABLE flag                                            */
3950             uint32_t            : 2;
3951       __IOM uint32_t USE5SBOXES : 1;            /*!< [8..8] the USE_5_SBOXES flag                                              */
3952       __IOM uint32_t AESSUPPORTPREVIV : 1;      /*!< [9..9] the AES_SUPPORT_PREV_IV flag                                       */
3953       __IOM uint32_t aestunnelexists : 1;       /*!< [10..10] the aes_tunnel_exists flag                                       */
3954       __IOM uint32_t SECONDREGSSETEXIST : 1;    /*!< [11..11] the SECOND_REGS_SET_EXIST flag                                   */
3955       __IOM uint32_t DFACNTRMSREXIST : 1;       /*!< [12..12] the DFA_CNTRMSR_EXIST flag                                       */
3956             uint32_t            : 19;
3957     } AESHWFLAGS_b;
3958   } ;
3959   __IM  uint32_t  RESERVED14[3];
3960 
3961   union {
3962     __IOM uint32_t AESCTRNOINCREMENT;           /*!< (@ 0x000004D8) This register enables the AES CTR no increment
3963                                                                     mode (in which the counter mode is not incremented
3964                                                                     between 2 blocks)                                          */
3965 
3966     struct {
3967       __IOM uint32_t AESCTRNOINCREMENT : 1;     /*!< [0..0] This field enables the AES CTR 'no increment' mode (in
3968                                                      which the counter mode is not incremented between 2 blocks)               */
3969             uint32_t            : 31;
3970     } AESCTRNOINCREMENT_b;
3971   } ;
3972   __IM  uint32_t  RESERVED15[5];
3973 
3974   union {
3975     __IOM uint32_t AESDFAISON;                  /*!< (@ 0x000004F0) This register disable_enable the AES dfa. Note:
3976                                                                     This is a special register, affected by
3977                                                                     internal logic. Test result of this register
3978                                                                     is NA.                                                     */
3979 
3980     struct {
3981       __IOM uint32_t AESDFAISON : 1;            /*!< [0..0] writing to this register turns the DFA counter-measures
3982                                                      on. this register exists only if DFA countermeasures are
3983                                                      supported                                                                 */
3984             uint32_t            : 31;
3985     } AESDFAISON_b;
3986   } ;
3987   __IM  uint32_t  RESERVED16;
3988 
3989   union {
3990     __IOM uint32_t AESDFAERRSTATUS;             /*!< (@ 0x000004F8) dfa error status register.                                 */
3991 
3992     struct {
3993       __IOM uint32_t AESDFAERRSTATUS : 1;       /*!< [0..0] after a DFA violation this register is set and the AES
3994                                                      block is disabled) until the next reset. this register
3995                                                      only exists if DFA countermeasures is are supported                       */
3996             uint32_t            : 31;
3997     } AESDFAERRSTATUS_b;
3998   } ;
3999   __IM  uint32_t  RESERVED17[10];
4000 
4001   union {
4002     __IOM uint32_t AESCMACSIZE0KICK;            /*!< (@ 0x00000524) writing to this address triggers the AES engine
4003                                                                     to perform a CMAC operation with size 0.
4004                                                                     The CMAC result can be read from the AES_IV0
4005                                                                     register.                                                  */
4006 
4007     struct {
4008       __IOM uint32_t AESCMACSIZE0KICK : 1;      /*!< [0..0] writing to this address triggers the AES engine to perform
4009                                                      a CMAC operation with size 0. The CMAC result can be read
4010                                                      from the AES_IV0 register.                                                */
4011             uint32_t            : 31;
4012     } AESCMACSIZE0KICK_b;
4013   } ;
4014   __IM  uint32_t  RESERVED18[70];
4015 
4016   union {
4017     __IOM uint32_t HASHH0;                      /*!< (@ 0x00000640) H0 data. can only be written in the following
4018                                                                     HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
4019                                                                     SHA384 SHA512                                              */
4020 
4021     struct {
4022       __IOM uint32_t HASHH0     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4023     } HASHH0_b;
4024   } ;
4025 
4026   union {
4027     __IOM uint32_t HASHH1;                      /*!< (@ 0x00000644) H1 data. can only be written in the following
4028                                                                     HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
4029                                                                     SHA384 SHA512                                              */
4030 
4031     struct {
4032       __IOM uint32_t HASHH1     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4033     } HASHH1_b;
4034   } ;
4035 
4036   union {
4037     __IOM uint32_t HASHH2;                      /*!< (@ 0x00000648) H2 data. can only be written in the following
4038                                                                     HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
4039                                                                     SHA384 SHA512                                              */
4040 
4041     struct {
4042       __IOM uint32_t HASHH2     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4043     } HASHH2_b;
4044   } ;
4045 
4046   union {
4047     __IOM uint32_t HASHH3;                      /*!< (@ 0x0000064C) H3 data. can only be written in the following
4048                                                                     HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
4049                                                                     SHA384 SHA512                                              */
4050 
4051     struct {
4052       __IOM uint32_t HASHH3     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4053     } HASHH3_b;
4054   } ;
4055 
4056   union {
4057     __IOM uint32_t HASHH4;                      /*!< (@ 0x00000650) H4 data. can only be written in the following
4058                                                                     HASH_CONTROL modes: SHA1 SHA224 SHA256 SHA384
4059                                                                     SHA512                                                     */
4060 
4061     struct {
4062       __IOM uint32_t HASHH4     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4063     } HASHH4_b;
4064   } ;
4065 
4066   union {
4067     __IOM uint32_t HASHH5;                      /*!< (@ 0x00000654) H5 data. can only be written in the following
4068                                                                     HASH_CONTROL modes: SHA224 SHA256 SHA384
4069                                                                     SHA512                                                     */
4070 
4071     struct {
4072       __IOM uint32_t HASHH5     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4073     } HASHH5_b;
4074   } ;
4075 
4076   union {
4077     __IOM uint32_t HASHH6;                      /*!< (@ 0x00000658) H6 data. can only be written in the following
4078                                                                     HASH_CONTROL modes: SHA224 SHA256 SHA384
4079                                                                     SHA512                                                     */
4080 
4081     struct {
4082       __IOM uint32_t HASHH6     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4083     } HASHH6_b;
4084   } ;
4085 
4086   union {
4087     __IOM uint32_t HASHH7;                      /*!< (@ 0x0000065C) H7 data. can only be written in the following
4088                                                                     HASH_CONTROL modes: SHA224 SHA256 SHA384
4089                                                                     SHA512                                                     */
4090 
4091     struct {
4092       __IOM uint32_t HASHH7     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4093     } HASHH7_b;
4094   } ;
4095 
4096   union {
4097     __IOM uint32_t HASHH8;                      /*!< (@ 0x00000660) H8 data. can only be written in the following
4098                                                                     HASH_CONTROL modes: SHA384 SHA512                          */
4099 
4100     struct {
4101       __IOM uint32_t HASHH8     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
4102     } HASHH8_b;
4103   } ;
4104   __IM  uint32_t  RESERVED19[8];
4105 
4106   union {
4107     __IOM uint32_t AUTOHWPADDING;               /*!< (@ 0x00000684) HW padding automatically activated by engine.
4108                                                                     For the special case of ZERO bytes data
4109                                                                     vector this register should not be used!
4110                                                                     instead use HASH_PAD_CFG                                   */
4111 
4112     struct {
4113       __IOM uint32_t EN         : 1;            /*!< [0..0] 0x1 - Enable Automatic HW padding (No need for SW intervention
4114                                                      by writing PAD_CFG). Note: Not supported for 0 bytes !
4115                                                      Note: Disable this register when HASH op is done                          */
4116             uint32_t            : 31;
4117     } AUTOHWPADDING_b;
4118   } ;
4119 
4120   union {
4121     __IOM uint32_t HASHXORDIN;                  /*!< (@ 0x00000688) This register is always xored with the input
4122                                                                     to the hash engine,it should be 0 if xored
4123                                                                     is not reqiured .                                          */
4124 
4125     struct {
4126       __IOM uint32_t HASHXORDATA : 32;          /*!< [31..0] This register holds the value to be xor-ed with hash
4127                                                      input data.                                                               */
4128     } HASHXORDIN_b;
4129   } ;
4130   __IM  uint32_t  RESERVED20[2];
4131 
4132   union {
4133     __IOM uint32_t LOADINITSTATE;               /*!< (@ 0x00000694) Indication to HASH that the following data is
4134                                                                     to be loaded into initial value registers
4135                                                                     in HASH(H0:H15) or IV to AES MAC                           */
4136 
4137     struct {
4138       __IOM uint32_t LOAD       : 1;            /*!< [0..0] Load data to initial state registers. digest_iv for hash_aes_mac.
4139                                                      When done loading data this bit should be reset                           */
4140             uint32_t            : 31;
4141     } LOADINITSTATE_b;
4142   } ;
4143   __IM  uint32_t  RESERVED21[3];
4144 
4145   union {
4146     __IOM uint32_t HASHSELAESMAC;               /*!< (@ 0x000006A4) select the AES MAC module rather than the hash
4147                                                                     module                                                     */
4148 
4149     struct {
4150       __IOM uint32_t HASHSELAESMAC : 1;         /*!< [0..0] Hash or AES MAC module select.                                     */
4151       __IOM uint32_t GHASHSEL   : 1;            /*!< [1..1] GHASH select.                                                      */
4152             uint32_t            : 30;
4153     } HASHSELAESMAC_b;
4154   } ;
4155   __IM  uint32_t  RESERVED22[66];
4156 
4157   union {
4158     __IOM uint32_t HASHVERSION;                 /*!< (@ 0x000007B0) HASH VERSION Register                                      */
4159 
4160     struct {
4161       __IOM uint32_t FIXES      : 8;            /*!< [7..0] Fixes field.                                                       */
4162       __IOM uint32_t MINORVERSIONNUMBER : 4;    /*!< [11..8] minor version number                                              */
4163       __IOM uint32_t MAJORVERSIONNUMBER : 4;    /*!< [15..12] major version number                                             */
4164             uint32_t            : 16;
4165     } HASHVERSION_b;
4166   } ;
4167   __IM  uint32_t  RESERVED23[3];
4168 
4169   union {
4170     __IOM uint32_t HASHCONTROL;                 /*!< (@ 0x000007C0) Selects which HASH mode to run                             */
4171 
4172     struct {
4173       __IOM uint32_t MODE01     : 2;            /*!< [1..0] bits 1:0 of the HASH mode field. The hash mode field
4174                                                      possible values are:                                                      */
4175             uint32_t            : 1;
4176       __IOM uint32_t MODE3      : 1;            /*!< [3..3] bit 3 of the HASH mode field. The hash mode field possible
4177                                                      values are:4b0000 - MD5 if present 0x0001 SHA 1 4b0010
4178                                                      - SHA-256 4b1010 - SHA-224                                                */
4179             uint32_t            : 28;
4180     } HASHCONTROL_b;
4181   } ;
4182 
4183   union {
4184     __IOM uint32_t HASHPADEN;                   /*!< (@ 0x000007C4) Enables the hash hw padding.                               */
4185 
4186     struct {
4187       __IOM uint32_t EN         : 1;            /*!< [0..0] 0x1 : Enable generation of padding by HW Pad block. 0x0
4188                                                      : Disable generation of padding by HW Pad block.                          */
4189             uint32_t            : 31;
4190     } HASHPADEN_b;
4191   } ;
4192 
4193   union {
4194     __IOM uint32_t HASHPADCFG;                  /*!< (@ 0x000007C8) This is a special register, affected by internal
4195                                                                     logic. Test result of this register is NA.                 */
4196 
4197     struct {
4198             uint32_t            : 2;
4199       __IOM uint32_t DOPAD      : 1;            /*!< [2..2] Enable Padding generation. must be reset upon completion
4200                                                      of padding.                                                               */
4201             uint32_t            : 29;
4202     } HASHPADCFG_b;
4203   } ;
4204 
4205   union {
4206     __IOM uint32_t HASHCURLEN0;                 /*!< (@ 0x000007CC) This register holds the length of current hash
4207                                                                     operation bit 31:0.                                        */
4208 
4209     struct {
4210       __IOM uint32_t Length     : 32;           /*!< [31..0] Represent the current length of valid bits where digest
4211                                                      need to be computed In Bytes.                                             */
4212     } HASHCURLEN0_b;
4213   } ;
4214 
4215   union {
4216     __IOM uint32_t HASHCURLEN1;                 /*!< (@ 0x000007D0) This register holds the length of current hash
4217                                                                     operation bit 63:32.                                       */
4218 
4219     struct {
4220       __IOM uint32_t Length     : 32;           /*!< [31..0] Represent the current length of valid bits where digest
4221                                                      need to be computed In Bytes.                                             */
4222     } HASHCURLEN1_b;
4223   } ;
4224   __IM  uint32_t  RESERVED24[2];
4225 
4226   union {
4227     __IOM uint32_t HASHPARAM;                   /*!< (@ 0x000007DC) HASH_PARAM Register.                                       */
4228 
4229     struct {
4230       __IOM uint32_t CW         : 4;            /*!< [3..0] Indicates the number of concurrent words the hash is
4231                                                      using to compute signature. 1 - One concurrent w(t). 2
4232                                                      - Two concurrent w(t).                                                    */
4233       __IOM uint32_t CH         : 4;            /*!< [7..4] Indicate if Hi adders are present for each Hi value or
4234                                                      1 adder is shared for all Hi. 0 - One Hi value is updated
4235                                                      at a time 1 - All Hi values are updated at the same time.                 */
4236       __IOM uint32_t DW         : 4;            /*!< [11..8] Determine the granularity of word size. 0 - 32 bit word
4237                                                      data. 1 - 64 bit word data.                                               */
4238       __IOM uint32_t SHA512EXISTS : 1;          /*!< [12..12] Indicate if SHA-512 is present in the design. By default
4239                                                      SHA-1 and SHA-256 are present. 0 - SHA-1 and SHA-256 are
4240                                                      present only 1 - SHA-1 and all SHA-2 are present (SHA-256
4241                                                      SHA-512).                                                                 */
4242       __IOM uint32_t PADEXISTS  : 1;            /*!< [13..13] Indicate if pad block is present in the design. 0 -
4243                                                      pad function is not supported by hardware. 1 - pad function
4244                                                      is supported by hardware.                                                 */
4245       __IOM uint32_t MD5EXISTS  : 1;            /*!< [14..14] Indicate if MD5 is present in HW                                 */
4246       __IOM uint32_t HMACEXISTS : 1;            /*!< [15..15] Indicate if HMAC logic is present in the design                  */
4247       __IOM uint32_t SHA256EXISTS : 1;          /*!< [16..16] Indicate if SHA-256 is present in the design                     */
4248       __IOM uint32_t HASHCOMPAREEXISTS : 1;     /*!< [17..17] Indicate if COMPARE digest logic is present in the
4249                                                      design                                                                    */
4250       __IOM uint32_t DUMPHASHTODOUTEXISTS : 1;  /*!< [18..18] Indicate if HASH to dout is present in the design                */
4251             uint32_t            : 13;
4252     } HASHPARAM_b;
4253   } ;
4254   __IM  uint32_t  RESERVED25;
4255 
4256   union {
4257     __IOM uint32_t HASHAESSWRESET;              /*!< (@ 0x000007E4) Software reset of the AES.                                 */
4258 
4259     struct {
4260       __IOM uint32_t HASHAESSWRESET : 1;        /*!< [0..0] Hash receive reset internally.                                     */
4261             uint32_t            : 31;
4262     } HASHAESSWRESET_b;
4263   } ;
4264 
4265   union {
4266     __IOM uint32_t HASHENDIANESS;               /*!< (@ 0x000007E8) This register holds the HASH_ENDIANESS configuration.      */
4267 
4268     struct {
4269       __IOM uint32_t ENDIAN     : 1;            /*!< [0..0] The default value is little-endian. The data and generation
4270                                                      of padding can be swapped to be big-endian.                               */
4271             uint32_t            : 31;
4272     } HASHENDIANESS_b;
4273   } ;
4274   __IM  uint32_t  RESERVED26[9];
4275 
4276   union {
4277     __IOM uint32_t AESCLKENABLE;                /*!< (@ 0x00000810) This is a special register, affected by internal
4278                                                                     logic. Test result of this register is NA.                 */
4279 
4280     struct {
4281       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the AES clock.                                              */
4282             uint32_t            : 31;
4283     } AESCLKENABLE_b;
4284   } ;
4285   __IM  uint32_t  RESERVED27;
4286 
4287   union {
4288     __IOM uint32_t HASHCLKENABLE;               /*!< (@ 0x00000818) The HASH clock enable register. Note: This is
4289                                                                     a special register, affected by internal
4290                                                                     logic. Test result of this register is NA.                 */
4291 
4292     struct {
4293       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the hash clock.                                             */
4294             uint32_t            : 31;
4295     } HASHCLKENABLE_b;
4296   } ;
4297 
4298   union {
4299     __IOM uint32_t PKACLKENABLE;                /*!< (@ 0x0000081C) The PKA clock enable register. Note: This is
4300                                                                     a special register, affected by internal
4301                                                                     logic. Test result of this register is NA.                 */
4302 
4303     struct {
4304       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the PKA clock.                                              */
4305             uint32_t            : 31;
4306     } PKACLKENABLE_b;
4307   } ;
4308 
4309   union {
4310     __IOM uint32_t DMACLKENABLE;                /*!< (@ 0x00000820) DMA_CLK enable register. Note: This is a special
4311                                                                     register, affected by internal logic. Test
4312                                                                     result of this register is NA.                             */
4313 
4314     struct {
4315       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the DMA clock.                                              */
4316             uint32_t            : 31;
4317     } DMACLKENABLE_b;
4318   } ;
4319 
4320   union {
4321     __IOM uint32_t CLKSTATUS;                   /*!< (@ 0x00000824) The CryptoCell clocks status register. Note:
4322                                                                     This is a special register, affected by
4323                                                                     internal logic. Test result of this register
4324                                                                     is NA.                                                     */
4325 
4326     struct {
4327       __IOM uint32_t AESCLKSTATUS : 1;          /*!< [0..0] Status of AES clock enable.                                        */
4328             uint32_t            : 1;
4329       __IOM uint32_t HASHCLKSTATUS : 1;         /*!< [2..2] Status of HASH clock clock enable.                                 */
4330       __IOM uint32_t PKACLKSTATUS : 1;          /*!< [3..3] Status of PKA clock enable.                                        */
4331             uint32_t            : 3;
4332       __IOM uint32_t CHACHACLKSTATUS : 1;       /*!< [7..7] Status of CHACHA clock enable.                                     */
4333       __IOM uint32_t DMACLKSTATUS : 1;          /*!< [8..8] Status of DMA clock enable.                                        */
4334             uint32_t            : 23;
4335     } CLKSTATUS_b;
4336   } ;
4337   __IM  uint32_t  RESERVED28[12];
4338 
4339   union {
4340     __IOM uint32_t CHACHACLKENABLE;             /*!< (@ 0x00000858) CHACHA _SALSA clock enable register. Note: This
4341                                                                     is a special register, affected by internal
4342                                                                     logic. Test result of this register is NA.                 */
4343 
4344     struct {
4345       __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the CHACHA SALSA clock enable.                              */
4346             uint32_t            : 31;
4347     } CHACHACLKENABLE_b;
4348   } ;
4349   __IM  uint32_t  RESERVED29[41];
4350 
4351   union {
4352     __IOM uint32_t CRYPTOCTL;                   /*!< (@ 0x00000900) Defines the cryptographic flow.                            */
4353 
4354     struct {
4355       __IOM uint32_t MODE       : 5;            /*!< [4..0] Determines the active cryptographic engine:                        */
4356             uint32_t            : 27;
4357     } CRYPTOCTL_b;
4358   } ;
4359   __IM  uint32_t  RESERVED30[3];
4360 
4361   union {
4362     __IOM uint32_t CRYPTOBUSY;                  /*!< (@ 0x00000910) This register is set when the cryptographic core
4363                                                                     is busy.                                                   */
4364 
4365     struct {
4366       __IOM uint32_t CRYPTOBUSY : 1;            /*!< [0..0] Crypto busy status.                                                */
4367             uint32_t            : 31;
4368     } CRYPTOBUSY_b;
4369   } ;
4370   __IM  uint32_t  RESERVED31[2];
4371 
4372   union {
4373     __IOM uint32_t HASHBUSY;                    /*!< (@ 0x0000091C) This register is set when the Hash engine is
4374                                                                     busy.                                                      */
4375 
4376     struct {
4377       __IOM uint32_t HASHBUSY   : 1;            /*!< [0..0] Hash busy status.                                                  */
4378             uint32_t            : 31;
4379     } HASHBUSY_b;
4380   } ;
4381   __IM  uint32_t  RESERVED32[4];
4382 
4383   union {
4384     __IOM uint32_t CONTEXTID;                   /*!< (@ 0x00000930) A general RD_WR register. For Firmware use.                */
4385 
4386     struct {
4387       __IOM uint32_t CONTEXTID  : 8;            /*!< [7..0] Context ID                                                         */
4388             uint32_t            : 24;
4389     } CONTEXTID_b;
4390   } ;
4391   __IM  uint32_t  RESERVED33[11];
4392 
4393   union {
4394     __IOM uint32_t GHASHSUBKEY00;               /*!< (@ 0x00000960) Bits 31:0 of GHASH Key0 (used as the GHASH module
4395                                                                     key).                                                      */
4396 
4397     struct {
4398       __IOM uint32_t GHASHSUBKEY00 : 32;        /*!< [31..0] Bits 31:0 of GHASH Key0.                                          */
4399     } GHASHSUBKEY00_b;
4400   } ;
4401 
4402   union {
4403     __IOM uint32_t GHASHSUBKEY01;               /*!< (@ 0x00000964) Bits 63:32 of GHASH Key0 (used as the GHASH module
4404                                                                     key).                                                      */
4405 
4406     struct {
4407       __IOM uint32_t GHASHSUBKEY01 : 32;        /*!< [31..0] Bits 63:32 of GHASH Key0.                                         */
4408     } GHASHSUBKEY01_b;
4409   } ;
4410 
4411   union {
4412     __IOM uint32_t GHASHSUBKEY02;               /*!< (@ 0x00000968) Bits 95:64 of GHASH Key0 (used as the GHASH module
4413                                                                     key).                                                      */
4414 
4415     struct {
4416       __IOM uint32_t GHASHSUBKEY02 : 32;        /*!< [31..0] Bits 95:64 of GHASH Key0.                                         */
4417     } GHASHSUBKEY02_b;
4418   } ;
4419 
4420   union {
4421     __IOM uint32_t GHASHSUBKEY03;               /*!< (@ 0x0000096C) Bits 127:96 of GHASH Key0 (used as the GHASH
4422                                                                     module key).                                               */
4423 
4424     struct {
4425       __IOM uint32_t GHASHSUBKEY03 : 32;        /*!< [31..0] Bits 127:96 of GHASH Key0.                                        */
4426     } GHASHSUBKEY03_b;
4427   } ;
4428 
4429   union {
4430     __IOM uint32_t GHASHIV00;                   /*!< (@ 0x00000970) Bits 31:0 of GHASH_IV0 register. GHASH IV0 is
4431                                                                     used as the GHASH IV (Initialization Value)
4432                                                                     register.                                                  */
4433 
4434     struct {
4435       __IOM uint32_t GHASHIV00  : 32;           /*!< [31..0] Bits 31:0 of GHASH_IV0 register of the GHASH module.
4436                                                      For the description of GHASH_IV0, see the GHASH_0_0 register
4437                                                      description                                                               */
4438     } GHASHIV00_b;
4439   } ;
4440 
4441   union {
4442     __IOM uint32_t GHASHIV01;                   /*!< (@ 0x00000974) Bits 63:32 of GHASH_IV0 register. GHASH IV0 is
4443                                                                     used as the GHASH IV (Initialization Value)
4444                                                                     register.                                                  */
4445 
4446     struct {
4447       __IOM uint32_t GHASHIV01  : 32;           /*!< [31..0] Bits 63:32 of GHASH_IV0 register of the GHASH module.             */
4448     } GHASHIV01_b;
4449   } ;
4450 
4451   union {
4452     __IOM uint32_t GHASHIV02;                   /*!< (@ 0x00000978) Bits 95:64 of GHASH_IV0 register. GHASH IV0 is
4453                                                                     used as the GHASH IV (Initialization Value)
4454                                                                     register.                                                  */
4455 
4456     struct {
4457       __IOM uint32_t GHASHIV02  : 32;           /*!< [31..0] Bits 95:64 of GHASH_IV0 register of the GHASH module.             */
4458     } GHASHIV02_b;
4459   } ;
4460 
4461   union {
4462     __IOM uint32_t GHASHIV03;                   /*!< (@ 0x0000097C) Bits 127:96 of GHASH_IV0 register.GHASH IV0 is
4463                                                                     used as the GHASH IV (Initialization Value)
4464                                                                     register.                                                  */
4465 
4466     struct {
4467       __IOM uint32_t GHASHIV03  : 32;           /*!< [31..0] Bits 127:96 of GHASH_IV0 register of the GHASH module.            */
4468     } GHASHIV03_b;
4469   } ;
4470 
4471   union {
4472     __IOM uint32_t GHASHBUSY;                   /*!< (@ 0x00000980) The GHASH module GHASH_BUSY Register. This register
4473                                                                     is set when the GHASH core is active.                      */
4474 
4475     struct {
4476       __IOM uint32_t GHASHBUSY  : 1;            /*!< [0..0] GHASH_BUSY Register. This register is set when the GHASH
4477                                                      core is active                                                            */
4478             uint32_t            : 31;
4479     } GHASHBUSY_b;
4480   } ;
4481 
4482   union {
4483     __IOM uint32_t GHASHINIT;                   /*!< (@ 0x00000984) Writing to this address sets the GHASH engine
4484                                                                     to be ready to a new GHASH operation.                      */
4485 
4486     struct {
4487       __IOM uint32_t GHASHINIT  : 1;            /*!< [0..0] Writing to this address sets the GHASH engine to be ready
4488                                                      to a new GHASH operation.                                                 */
4489             uint32_t            : 31;
4490     } GHASHINIT_b;
4491   } ;
4492   __IM  uint32_t  RESERVED34[30];
4493 
4494   union {
4495     __IOM uint32_t HOSTRGFIRR;                  /*!< (@ 0x00000A00) The Interrupt Request register. Each bit of this
4496                                                                     register holds the interrupt status of a
4497                                                                     single interrupt source.                                   */
4498 
4499     struct {
4500             uint32_t            : 4;
4501       __IOM uint32_t SRAMTODININT : 1;          /*!< [4..4] The SRAM to DIN DMA done interrupt status. This interrupt
4502                                                      is asserted when all data was delivered to DIN buffer from
4503                                                      SRAM.                                                                     */
4504       __IOM uint32_t DOUTTOSRAMINT : 1;         /*!< [5..5] The DOUT to SRAM DMA done interrupt status. This interrupt
4505                                                      is asserted when all data was delivered to SRAM buffer
4506                                                      from DOUT.                                                                */
4507       __IOM uint32_t MEMTODININT : 1;           /*!< [6..6] The memory to DIN DMA done interrupt status. This interrupt
4508                                                      is asserted when all data was delivered to DIN buffer from
4509                                                      memory.                                                                   */
4510       __IOM uint32_t DOUTTOMEMINT : 1;          /*!< [7..7] The DOUT to memory DMA done interrupt status. This interrupt
4511                                                      is asserted when all data was delivered to memory buffer
4512                                                      from DOUT.                                                                */
4513       __IOM uint32_t AHBERRINT  : 1;            /*!< [8..8] The AXI error interrupt status.                                    */
4514       __IOM uint32_t PKAEXPINT  : 1;            /*!< [9..9] The PKA end of operation interrupt status.                         */
4515       __IOM uint32_t RNGINT     : 1;            /*!< [10..10] The RNG interrupt status.                                        */
4516       __IOM uint32_t SYMDMACOMPLETED : 1;       /*!< [11..11] The GPR interrupt status.                                        */
4517             uint32_t            : 20;
4518     } HOSTRGFIRR_b;
4519   } ;
4520 
4521   union {
4522     __IOM uint32_t HOSTRGFIMR;                  /*!< (@ 0x00000A04) The Interrupt Mask register. Each bit of this
4523                                                                     register holds the mask of a single interrupt
4524                                                                     source.                                                    */
4525 
4526     struct {
4527             uint32_t            : 4;
4528       __IOM uint32_t SRAMTODINMASK : 1;         /*!< [4..4] The SRAM to DIN DMA done interrupt mask.                           */
4529       __IOM uint32_t DOUTTOSRAMMASK : 1;        /*!< [5..5] The DOUT to SRAM DMA done interrupt mask.                          */
4530       __IOM uint32_t MEMTODINMASK : 1;          /*!< [6..6] The memory to DIN DMA done interrupt mask.                         */
4531       __IOM uint32_t DOUTTOMEMMASK : 1;         /*!< [7..7] The DOUT to memory DMA done interrupt mask.                        */
4532       __IOM uint32_t AXIERRMASK : 1;            /*!< [8..8] The AXI error interrupt mask.                                      */
4533       __IOM uint32_t PKAEXPMASK : 1;            /*!< [9..9] The PKA end of operation interrupt mask.                           */
4534       __IOM uint32_t RNGINTMASK : 1;            /*!< [10..10] The RNG interrupt mask.                                          */
4535       __IOM uint32_t SYMDMACOMPLETEDMASK : 1;   /*!< [11..11] The GPR interrupt mask.                                          */
4536             uint32_t            : 20;
4537     } HOSTRGFIMR_b;
4538   } ;
4539 
4540   union {
4541     __IOM uint32_t HOSTRGFICR;                  /*!< (@ 0x00000A08) Interrupt Clear Register.                                  */
4542 
4543     struct {
4544             uint32_t            : 4;
4545       __IOM uint32_t SRAMTODINCLEAR : 1;        /*!< [4..4] The SRAM to DIN DMA done interrupt clear.                          */
4546       __IOM uint32_t DOUTTOSRAMCLEAR : 1;       /*!< [5..5] The DOUT to SRAM DMA done interrupt clear.                         */
4547       __IOM uint32_t MEMTODINCLEAR : 1;         /*!< [6..6] The memory to DIN DMA done interrupt clear.                        */
4548       __IOM uint32_t DOUTTOMEMCLEAR : 1;        /*!< [7..7] The DOUT to memory DMA done interrupt clear.                       */
4549       __IOM uint32_t AXIERRCLEAR : 1;           /*!< [8..8] The AXI error interrupt clear.                                     */
4550       __IOM uint32_t PKAEXPCLEAR : 1;           /*!< [9..9] The PKA end of operation interrupt clear.                          */
4551       __IOM uint32_t RNGINTCLEAR : 1;           /*!< [10..10] The RNG interrupt clear.                                         */
4552       __IOM uint32_t SYMDMACOMPLETEDCLEAR : 1;  /*!< [11..11] The GPR interrupt clear.                                         */
4553             uint32_t            : 20;
4554     } HOSTRGFICR_b;
4555   } ;
4556 
4557   union {
4558     __IOM uint32_t HOSTRGFENDIAN;               /*!< (@ 0x00000A0C) This register defines the endianness of the Host-accessible
4559                                                                     registers. Note: This is a special register,
4560                                                                     affected by internal logic. Test result
4561                                                                     of this register is NA.                                    */
4562 
4563     struct {
4564             uint32_t            : 3;
4565       __IOM uint32_t DOUTWRBG   : 1;            /*!< [3..3] DOUT write endianness:                                             */
4566             uint32_t            : 3;
4567       __IOM uint32_t DINRDBG    : 1;            /*!< [7..7] DIN write endianness:                                              */
4568             uint32_t            : 3;
4569       __IOM uint32_t DOUTWRWBG  : 1;            /*!< [11..11] DOUT write word endianness:                                      */
4570             uint32_t            : 3;
4571       __IOM uint32_t DINRDWBG   : 1;            /*!< [15..15] DIN write word endianness:                                       */
4572             uint32_t            : 16;
4573     } HOSTRGFENDIAN_b;
4574   } ;
4575   __IM  uint32_t  RESERVED35[5];
4576 
4577   union {
4578     __IOM uint32_t HOSTRGFSIGNATURE;            /*!< (@ 0x00000A24) This register holds the CryptoCell product signature.      */
4579 
4580     struct {
4581       __IOM uint32_t HOSTSIGNATURE : 32;        /*!< [31..0] Identification 'signature': always returns a fixed value,
4582                                                      used by Host driver to verify CryptoCell presence at this
4583                                                      address.                                                                  */
4584     } HOSTRGFSIGNATURE_b;
4585   } ;
4586 
4587   union {
4588     __IOM uint32_t HOSTBOOT;                    /*!< (@ 0x00000A28) This register holds the values of CryptoCells
4589                                                                     pre-synthesis flags                                        */
4590 
4591     struct {
4592       __IOM uint32_t SYNTHESISCONFIG : 1;       /*!< [0..0] POWER_GATING_EXISTS_LOCAL                                          */
4593       __IOM uint32_t LARGERKEKLOCAL : 1;        /*!< [1..1] LARGE_RKEK_LOCAL                                                   */
4594       __IOM uint32_t HASHINFUSESLOCAL : 1;      /*!< [2..2] HASH_IN_FUSES_LOCAL                                                */
4595       __IOM uint32_t EXTMEMSECUREDLOCAL : 1;    /*!< [3..3] EXT_MEM_SECURED_LOCAL                                              */
4596             uint32_t            : 1;
4597       __IOM uint32_t RKEKECCEXISTSLOCALN : 1;   /*!< [5..5] RKEK_ECC_EXISTS_LOCAL_N                                            */
4598       __IOM uint32_t SRAMSIZELOCAL : 3;         /*!< [8..6] SRAM_SIZE_LOCAL                                                    */
4599       __IOM uint32_t DSCRPTREXISTSLOCAL : 1;    /*!< [9..9] DSCRPTR_EXISTS_LOCAL                                               */
4600       __IOM uint32_t PAUEXISTSLOCAL : 1;        /*!< [10..10] PAU_EXISTS_LOCAL                                                 */
4601       __IOM uint32_t RNGEXISTSLOCAL : 1;        /*!< [11..11] RNG_EXISTS_LOCAL                                                 */
4602       __IOM uint32_t PKAEXISTSLOCAL : 1;        /*!< [12..12] PKA_EXISTS_LOCAL                                                 */
4603       __IOM uint32_t RC4EXISTSLOCAL : 1;        /*!< [13..13] RC4_EXISTS_LOCAL                                                 */
4604       __IOM uint32_t SHA512PRSNTLOCAL : 1;      /*!< [14..14] SHA_512_PRSNT_LOCAL                                              */
4605       __IOM uint32_t SHA256PRSNTLOCAL : 1;      /*!< [15..15] SHA_256_PRSNT_LOCAL                                              */
4606       __IOM uint32_t MD5PRSNTLOCAL : 1;         /*!< [16..16] MD5_PRSNT_LOCAL                                                  */
4607       __IOM uint32_t HASHEXISTSLOCAL : 1;       /*!< [17..17] HASH_EXISTS_LOCAL                                                */
4608       __IOM uint32_t C2EXISTSLOCAL : 1;         /*!< [18..18] C2_EXISTS_LOCAL                                                  */
4609       __IOM uint32_t DESEXISTSLOCAL : 1;        /*!< [19..19] DES_EXISTS_LOCAL                                                 */
4610       __IOM uint32_t AESXCBCMACEXISTSLOCAL : 1; /*!< [20..20] AES_XCBC_MAC_EXISTS_LOCAL                                        */
4611       __IOM uint32_t AESCMACEXISTSLOCAL : 1;    /*!< [21..21] AES_CMAC_EXISTS_LOCAL                                            */
4612       __IOM uint32_t AESCCMEXISTSLOCAL : 1;     /*!< [22..22] AES_CCM_EXISTS_LOCAL                                             */
4613       __IOM uint32_t AESXEXHWTCALCLOCAL : 1;    /*!< [23..23] AES_XEX_HW_T_CALC_LOCAL                                          */
4614       __IOM uint32_t AESXEXEXISTSLOCAL : 1;     /*!< [24..24] AES_XEX_EXISTS_LOCAL                                             */
4615       __IOM uint32_t CTREXISTSLOCAL : 1;        /*!< [25..25] CTR_EXISTS_LOCAL                                                 */
4616       __IOM uint32_t AESDINBYTERESOLUTIONLOCAL : 1;/*!< [26..26] AES_DIN_BYTE_RESOLUTION_LOCAL                                 */
4617       __IOM uint32_t TUNNELINGENBLOCAL : 1;     /*!< [27..27] TUNNELING_ENB_LOCAL                                              */
4618       __IOM uint32_t SUPPORT256192KEYLOCAL : 1; /*!< [28..28] SUPPORT_256_192_KEY_LOCAL                                        */
4619       __IOM uint32_t ONLYENCRYPTLOCAL : 1;      /*!< [29..29] ONLY_ENCRYPT_LOCAL                                               */
4620       __IOM uint32_t AESEXISTSLOCAL : 1;        /*!< [30..30] AES_EXISTS_LOCAL                                                 */
4621             uint32_t            : 1;
4622     } HOSTBOOT_b;
4623   } ;
4624   __IM  uint32_t  RESERVED36[3];
4625 
4626   union {
4627     __IOM uint32_t HOSTCRYPTOKEYSEL;            /*!< (@ 0x00000A38) AES hardware key select. Note: This is a special
4628                                                                     register, affected by internal logic. Test
4629                                                                     result of this register is NA.                             */
4630 
4631     struct {
4632       __IOM uint32_t SELCRYPTOKEY : 3;          /*!< [2..0] Select the source of the HW key that is used by the AES
4633                                                      engine:                                                                   */
4634             uint32_t            : 29;
4635     } HOSTCRYPTOKEYSEL_b;
4636   } ;
4637   __IM  uint32_t  RESERVED37[15];
4638 
4639   union {
4640     __IOM uint32_t HOSTCORECLKGATINGENABLE;     /*!< (@ 0x00000A78) This register enables the core clk gating by
4641                                                                     masking_enabling the cc_idle_state output
4642                                                                     signal.                                                    */
4643 
4644     struct {
4645       __IOM uint32_t HOSTCORECLKGATINGENABLE : 1;/*!< [0..0] Enable the core clk gating,                                       */
4646             uint32_t            : 31;
4647     } HOSTCORECLKGATINGENABLE_b;
4648   } ;
4649 
4650   union {
4651     __IOM uint32_t HOSTCCISIDLE;                /*!< (@ 0x00000A7C) This register holds the idle indication of CC
4652                                                                     . Note: This is a special register, affected
4653                                                                     by internal logic. Test result of this register
4654                                                                     is NA.                                                     */
4655 
4656     struct {
4657       __IOM uint32_t HOSTCCISIDLE : 1;          /*!< [0..0] Read if CC is idle.                                                */
4658       __IOM uint32_t HOSTCCISIDLEEVENT : 1;     /*!< [1..1] The event that indicates that CC is idle.                          */
4659       __IOM uint32_t SYMISBUSY  : 1;            /*!< [2..2] symetric flow is busy                                              */
4660       __IOM uint32_t AHBISIDLE  : 1;            /*!< [3..3] ahb stste machine is idle                                          */
4661       __IOM uint32_t NVMARBISIDLE : 1;          /*!< [4..4] nvm arbiter is idle                                                */
4662       __IOM uint32_t NVMISIDLE  : 1;            /*!< [5..5] nvm is idle                                                        */
4663       __IOM uint32_t FATALWR    : 1;            /*!< [6..6] fatal write                                                        */
4664       __IOM uint32_t RNGISIDLE  : 1;            /*!< [7..7] rng is idle                                                        */
4665       __IOM uint32_t PKAISIDLE  : 1;            /*!< [8..8] pka is idle                                                        */
4666       __IOM uint32_t CRYPTOISIDLE : 1;          /*!< [9..9] crypto flow is done                                                */
4667             uint32_t            : 22;
4668     } HOSTCCISIDLE_b;
4669   } ;
4670 
4671   union {
4672     __IOM uint32_t HOSTPOWERDOWN;               /*!< (@ 0x00000A80) This register start the power-down sequence.
4673                                                                     Note: This is a special register, affected
4674                                                                     by internal logic. Test result of this register
4675                                                                     is NA.                                                     */
4676 
4677     struct {
4678       __IOM uint32_t HOSTPOWERDOWN : 1;         /*!< [0..0] Power down enable register.                                        */
4679             uint32_t            : 31;
4680     } HOSTPOWERDOWN_b;
4681   } ;
4682 
4683   union {
4684     __IOM uint32_t HOSTREMOVEGHASHENGINE;       /*!< (@ 0x00000A84) These inputs are to be statically tied to 0 or
4685                                                                     1 by the customers. When such an input is
4686                                                                     set, the matching engines inputs are tied
4687                                                                     to zero and its outputs are disconnected,
4688                                                                     so that the engine will be entirely removed
4689                                                                     by Synthesis                                               */
4690 
4691     struct {
4692       __IOM uint32_t HOSTREMOVEGHASHENGINE : 1; /*!< [0..0] Read the Remove_chacha_engine input                                */
4693             uint32_t            : 31;
4694     } HOSTREMOVEGHASHENGINE_b;
4695   } ;
4696 
4697   union {
4698     __IOM uint32_t HOSTREMOVECHACHAENGINE;      /*!< (@ 0x00000A88) These inputs are to be statically tied to 0 or
4699                                                                     1 by the customers. When such an input is
4700                                                                     set, the matching engines inputs are tied
4701                                                                     to zero and its outputs are disconnected,
4702                                                                     so that the engine will be entirely removed
4703                                                                     by Synthesis                                               */
4704 
4705     struct {
4706       __IOM uint32_t HOSTREMOVECHACHAENGINE : 1;/*!< [0..0] Read the Remove_ghash_engine input                                 */
4707             uint32_t            : 31;
4708     } HOSTREMOVECHACHAENGINE_b;
4709   } ;
4710   __IM  uint32_t  RESERVED38[29];
4711 
4712   union {
4713     __IOM uint32_t AHBMSINGLES;                 /*!< (@ 0x00000B00) This register forces the ahb transactions to
4714                                                                     be always singles.                                         */
4715 
4716     struct {
4717       __IOM uint32_t AHBSINGLES : 1;            /*!< [0..0] Force ahb singles                                                  */
4718             uint32_t            : 31;
4719     } AHBMSINGLES_b;
4720   } ;
4721 
4722   union {
4723     __IOM uint32_t AHBMHPROT;                   /*!< (@ 0x00000B04) This register holds the ahb prot value                     */
4724 
4725     struct {
4726       __IOM uint32_t AHBPROT    : 4;            /*!< [3..0] The ahb prot value                                                 */
4727             uint32_t            : 28;
4728     } AHBMHPROT_b;
4729   } ;
4730 
4731   union {
4732     __IOM uint32_t AHBMHMASTLOCK;               /*!< (@ 0x00000B08) This register holds ahb hmastlock value                    */
4733 
4734     struct {
4735       __IOM uint32_t AHBHMASTLOCK : 1;          /*!< [0..0] The hmastlock value.                                               */
4736             uint32_t            : 31;
4737     } AHBMHMASTLOCK_b;
4738   } ;
4739 
4740   union {
4741     __IOM uint32_t AHBMHNONSEC;                 /*!< (@ 0x00000B0C) This register holds ahb hnonsec value                      */
4742 
4743     struct {
4744       __IOM uint32_t AHBWRITEHNONSEC : 1;       /*!< [0..0] The hnonsec value for write transaction.                           */
4745       __IOM uint32_t AHBREADHNONSEC : 1;        /*!< [1..1] The hnonsec value for read transaction.                            */
4746             uint32_t            : 30;
4747     } AHBMHNONSEC_b;
4748   } ;
4749   __IM  uint32_t  RESERVED39[60];
4750 
4751   union {
4752     __IOM uint32_t DINBUFFER;                   /*!< (@ 0x00000C00) This address can be used by the CPU to write
4753                                                                     data directly to the DIN buffer to be sent
4754                                                                     to engines.                                                */
4755 
4756     struct {
4757       __IOM uint32_t DINBUFFERDATA : 32;        /*!< [31..0] This register is mapped into 8 addresses in order to
4758                                                      enable a CPU burst.                                                       */
4759     } DINBUFFER_b;
4760   } ;
4761   __IM  uint32_t  RESERVED40[7];
4762 
4763   union {
4764     __IOM uint32_t DINMEMDMABUSY;               /*!< (@ 0x00000C20) Indicates whether memory (AXI) source DMA (DIN)
4765                                                                     is busy.                                                   */
4766 
4767     struct {
4768       __IOM uint32_t DINMEMDMABUSY : 1;         /*!< [0..0] DIN memory DMA busy                                                */
4769             uint32_t            : 31;
4770     } DINMEMDMABUSY_b;
4771   } ;
4772   __IM  uint32_t  RESERVED41;
4773 
4774   union {
4775     __IOM uint32_t SRCLLIWORD0;                 /*!< (@ 0x00000C28) This register is used in direct LLI mode - holds
4776                                                                     the location of the data source in the memory
4777                                                                     (AXI).                                                     */
4778 
4779     struct {
4780       __IOM uint32_t SRCLLIWORD0 : 32;          /*!< [31..0] Source address within memory.                                     */
4781     } SRCLLIWORD0_b;
4782   } ;
4783 
4784   union {
4785     __IOM uint32_t SRCLLIWORD1;                 /*!< (@ 0x00000C2C) This register is used in direct LLI mode - holds
4786                                                                     the number of bytes to be read from the
4787                                                                     memory (AXI). Writing to this register triggers
4788                                                                     the DMA. Note: This is a special register,
4789                                                                     affected by internal logic. Test result
4790                                                                     of this register is NA.                                    */
4791 
4792     struct {
4793       __IOM uint32_t BYTESNUM   : 30;           /*!< [29..0] Total number of bytes to read using DMA in this entry             */
4794       __IOM uint32_t FIRST      : 1;            /*!< [30..30] 0x1 - Indicates the first LLI entry                              */
4795       __IOM uint32_t LAST       : 1;            /*!< [31..31] 0x1 - Indicates the last LLI entry                               */
4796     } SRCLLIWORD1_b;
4797   } ;
4798 
4799   union {
4800     __IOM uint32_t SRAMSRCADDR;                 /*!< (@ 0x00000C30) Location of data (start address) to be read from
4801                                                                     SRAM. Note: This is a special register,
4802                                                                     affected by internal logic. Test result
4803                                                                     of this register is NA.                                    */
4804 
4805     struct {
4806       __IOM uint32_t SRAMSOURCE : 32;           /*!< [31..0] SRAM source base address of data                                  */
4807     } SRAMSRCADDR_b;
4808   } ;
4809 
4810   union {
4811     __IOM uint32_t DINSRAMBYTESLEN;             /*!< (@ 0x00000C34) This register holds the size of the data (in
4812                                                                     bytes) to be read from the SRAM. Note: This
4813                                                                     is a special register, affected by internal
4814                                                                     logic. Test result of this register is NA.                 */
4815 
4816     struct {
4817       __IOM uint32_t BYTESLEN   : 32;           /*!< [31..0] Size of data to read from SRAM (bytes). This is the
4818                                                      trigger to the SRAM SRC DMA.                                              */
4819     } DINSRAMBYTESLEN_b;
4820   } ;
4821 
4822   union {
4823     __IOM uint32_t DINSRAMDMABUSY;              /*!< (@ 0x00000C38) This register holds the status of the SRAM DMA
4824                                                                     DIN.                                                       */
4825 
4826     struct {
4827       __IOM uint32_t BUSY       : 1;            /*!< [0..0] DIN SRAM DMA busy:                                                 */
4828             uint32_t            : 31;
4829     } DINSRAMDMABUSY_b;
4830   } ;
4831 
4832   union {
4833     __IOM uint32_t DINSRAMENDIANNESS;           /*!< (@ 0x00000C3C) This register defines the endianness of the DIN
4834                                                                     interface to SRAM.                                         */
4835 
4836     struct {
4837       __IOM uint32_t SRAMDINENDIANNESS : 1;     /*!< [0..0] Defines the endianness of DIN interface to SRAM:                   */
4838             uint32_t            : 31;
4839     } DINSRAMENDIANNESS_b;
4840   } ;
4841   __IM  uint32_t  RESERVED42[2];
4842 
4843   union {
4844     __IOM uint32_t DINCPUDATASIZE;              /*!< (@ 0x00000C48) This register hold the number of bytes to be
4845                                                                     transmited using external DMA. Note: This
4846                                                                     is a special register, affected by internal
4847                                                                     logic. Test result of this register is NA.                 */
4848 
4849     struct {
4850       __IOM uint32_t CPUDINSIZE : 16;           /*!< [15..0] When using external DMA, the size of transmited data
4851                                                      in bytes should be written to this register.                              */
4852             uint32_t            : 16;
4853     } DINCPUDATASIZE_b;
4854   } ;
4855   __IM  uint32_t  RESERVED43;
4856 
4857   union {
4858     __IOM uint32_t FIFOINEMPTY;                 /*!< (@ 0x00000C50) DIN FIFO empty indication                                  */
4859 
4860     struct {
4861       __IOM uint32_t EMPTY      : 1;            /*!< [0..0] 0x1 - FIFO empty                                                   */
4862             uint32_t            : 31;
4863     } FIFOINEMPTY_b;
4864   } ;
4865   __IM  uint32_t  RESERVED44;
4866 
4867   union {
4868     __IOM uint32_t DINFIFORSTPNTR;              /*!< (@ 0x00000C58) Writing to this register resets the DIN_FIFO
4869                                                                     pointers.                                                  */
4870 
4871     struct {
4872       __IOM uint32_t RST        : 1;            /*!< [0..0] Writing any value to this address resets the DIN_FIFO
4873                                                      pointers.                                                                 */
4874             uint32_t            : 31;
4875     } DINFIFORSTPNTR_b;
4876   } ;
4877   __IM  uint32_t  RESERVED45[41];
4878 
4879   union {
4880     __IOM uint32_t DOUTBUFFER;                  /*!< (@ 0x00000D00) Cryptographic result - CPU can directly access
4881                                                                     it. Note: This is a special register, affected
4882                                                                     by internal logic. Test result of this register
4883                                                                     is NA.                                                     */
4884 
4885     struct {
4886       __IOM uint32_t DATA       : 32;           /*!< [31..0] DOUT This address can be used by the CPU to read data
4887                                                      directly from the DOUT buffer.                                            */
4888     } DOUTBUFFER_b;
4889   } ;
4890   __IM  uint32_t  RESERVED46[7];
4891 
4892   union {
4893     __IOM uint32_t DOUTMEMDMABUSY;              /*!< (@ 0x00000D20) DOUT memory DMA busy - Indicates that memory
4894                                                                     (AXI) destination DMA (DOUT) is busy,                      */
4895 
4896     struct {
4897       __IOM uint32_t DOUTMEMDMABUSY : 1;        /*!< [0..0] DOUT memory DMA busy:                                              */
4898             uint32_t            : 31;
4899     } DOUTMEMDMABUSY_b;
4900   } ;
4901   __IM  uint32_t  RESERVED47;
4902 
4903   union {
4904     __IOM uint32_t DSTLLIWORD0;                 /*!< (@ 0x00000D28) This register is used in direct LLI mode - holds
4905                                                                     the location of the data destination in
4906                                                                     the memory (AXI)                                           */
4907 
4908     struct {
4909       __IOM uint32_t DSTLLIWORD0 : 32;          /*!< [31..0] Destination address within memory                                 */
4910     } DSTLLIWORD0_b;
4911   } ;
4912 
4913   union {
4914     __IOM uint32_t DSTLLIWORD1;                 /*!< (@ 0x00000D2C) This register is used in direct LLI mode - holds
4915                                                                     the number of bytes to be written to the
4916                                                                     memory (AXI). Note: This is a special register,
4917                                                                     affected by internal logic. Test result
4918                                                                     of this register is NA.                                    */
4919 
4920     struct {
4921       __IOM uint32_t BYTESNUM   : 30;           /*!< [29..0] Total byte number to be written by DMA in this entry              */
4922       __IOM uint32_t FIRST      : 1;            /*!< [30..30] 0x1 - Indicates the first LLI entry                              */
4923       __IOM uint32_t LAST       : 1;            /*!< [31..31] 0x1 - Indicates the last LLI entry                               */
4924     } DSTLLIWORD1_b;
4925   } ;
4926 
4927   union {
4928     __IOM uint32_t SRAMDESTADDR;                /*!< (@ 0x00000D30) Location of result to be sent to in SRAM. Note:
4929                                                                     This is a special register, affected by
4930                                                                     internal logic. Test result of this register
4931                                                                     is NA.                                                     */
4932 
4933     struct {
4934       __IOM uint32_t SRAMDEST   : 32;           /*!< [31..0] SRAM destination base address for data.                           */
4935     } SRAMDESTADDR_b;
4936   } ;
4937 
4938   union {
4939     __IOM uint32_t DOUTSRAMBYTESLEN;            /*!< (@ 0x00000D34) This register holds the size of the data (in
4940                                                                     bytes) to be written to the SRAM. Note:
4941                                                                     This is a special register, affected by
4942                                                                     internal logic. Test result of this register
4943                                                                     is NA.                                                     */
4944 
4945     struct {
4946       __IOM uint32_t BYTESLEN   : 32;           /*!< [31..0] Size of data to write to SRAM (bytes). This is the trigger
4947                                                      to the SRAM DST DMA.                                                      */
4948     } DOUTSRAMBYTESLEN_b;
4949   } ;
4950 
4951   union {
4952     __IOM uint32_t DOUTSRAMDMABUSY;             /*!< (@ 0x00000D38) This register holds the status of the SRAM DMA
4953                                                                     DOUT.                                                      */
4954 
4955     struct {
4956       __IOM uint32_t BUSY       : 1;            /*!< [0..0] DOUT SRAM DMA busy status.                                         */
4957             uint32_t            : 31;
4958     } DOUTSRAMDMABUSY_b;
4959   } ;
4960 
4961   union {
4962     __IOM uint32_t DOUTSRAMENDIANNESS;          /*!< (@ 0x00000D3C) This register defines the endianness of the DOUT
4963                                                                     interface from SRAM.                                       */
4964 
4965     struct {
4966       __IOM uint32_t DOUTSRAMENDIANNESS : 1;    /*!< [0..0] Defines the endianness of DOUT interface from SRAM:                */
4967             uint32_t            : 31;
4968     } DOUTSRAMENDIANNESS_b;
4969   } ;
4970   __IM  uint32_t  RESERVED48;
4971 
4972   union {
4973     __IOM uint32_t READALIGNLAST;               /*!< (@ 0x00000D44) Indication that the next read from the CPU is
4974                                                                     the last one. This is needed only when the
4975                                                                     data size is NOT modulo 4 (e.g. HASH padding).             */
4976 
4977     struct {
4978       __IOM uint32_t LAST       : 1;            /*!< [0..0] 0x1 - Flush the read aligner content (used for reading
4979                                                      the last data).                                                           */
4980             uint32_t            : 31;
4981     } READALIGNLAST_b;
4982   } ;
4983   __IM  uint32_t  RESERVED49[2];
4984 
4985   union {
4986     __IOM uint32_t DOUTFIFOEMPTY;               /*!< (@ 0x00000D50) DOUT_FIFO_EMPTY Register.                                  */
4987 
4988     struct {
4989       __IOM uint32_t DOUTFIFOEMPTY : 1;         /*!< [0..0] DOUT FIFO empty status.                                            */
4990             uint32_t            : 31;
4991     } DOUTFIFOEMPTY_b;
4992   } ;
4993   __IM  uint32_t  RESERVED50[107];
4994 
4995   union {
4996     __IOM uint32_t SRAMDATA;                    /*!< (@ 0x00000F00) READ WRITE DATA FROM SRAM. Note: This is a special
4997                                                                     register, affected by internal logic. Test
4998                                                                     result of this register is NA.                             */
4999 
5000     struct {
5001       __IOM uint32_t SRAMDATA   : 32;           /*!< [31..0] 32 bit write or read from SRAM: read - triggers the
5002                                                      SRAM read DMA address automatically incremented write -
5003                                                      triggers the SRAM write DMA address automatically incremented             */
5004     } SRAMDATA_b;
5005   } ;
5006 
5007   union {
5008     __IOM uint32_t SRAMADDR;                    /*!< (@ 0x00000F04) first address given to SRAM DMA for read_write
5009                                                                     transactions from SRAM                                     */
5010 
5011     struct {
5012       __IOM uint32_t SRAMADDR   : 15;           /*!< [14..0] SRAM starting address                                             */
5013             uint32_t            : 17;
5014     } SRAMADDR_b;
5015   } ;
5016 
5017   union {
5018     __IOM uint32_t SRAMDATAREADY;               /*!< (@ 0x00000F08) The SRAM content is ready for read in SRAM_DATA.           */
5019 
5020     struct {
5021       __IOM uint32_t SRAMREADY  : 1;            /*!< [0..0] SRAM content is ready for read in SRAM_DATA.                       */
5022             uint32_t            : 31;
5023     } SRAMDATAREADY_b;
5024   } ;
5025   __IM  uint32_t  RESERVED51[49];
5026 
5027   union {
5028     __IOM uint32_t PERIPHERALID4;               /*!< (@ 0x00000FD0) Peripheral ID 4 (PID4).                                    */
5029 
5030     struct {
5031       __IOM uint32_t DES2JEP106 : 4;            /*!< [3..0] for ARM products.                                                  */
5032             uint32_t            : 28;
5033     } PERIPHERALID4_b;
5034   } ;
5035   __IM  uint32_t  RESERVED52[3];
5036 
5037   union {
5038     __IOM uint32_t PERIPHERALID0;               /*!< (@ 0x00000FE0) Peripheral ID 0 (PID0).                                    */
5039 
5040     struct {
5041       __IOM uint32_t PART0      : 8;            /*!< [7..0] Identification register part number, bits[7:0]                     */
5042             uint32_t            : 24;
5043     } PERIPHERALID0_b;
5044   } ;
5045 
5046   union {
5047     __IOM uint32_t PERIPHERALID1;               /*!< (@ 0x00000FE4) Peripheral ID 1 (PID1).                                    */
5048 
5049     struct {
5050       __IOM uint32_t PART1      : 4;            /*!< [3..0] Identification register part number, bits[11:8]                    */
5051       __IOM uint32_t DES0JEP106 : 4;            /*!< [7..4] for ARM products.                                                  */
5052             uint32_t            : 24;
5053     } PERIPHERALID1_b;
5054   } ;
5055 
5056   union {
5057     __IOM uint32_t PERIPHERALID2;               /*!< (@ 0x00000FE8) Peripheral ID 2 (PID2).                                    */
5058 
5059     struct {
5060       __IOM uint32_t DES1JEP106 : 3;            /*!< [2..0] for ARM products.                                                  */
5061       __IOM uint32_t JEDEC      : 1;            /*!< [3..3] constant 0x1. Indicates that a JEDEC assigned value is
5062                                                      used.                                                                     */
5063       __IOM uint32_t REVISION   : 4;            /*!< [7..4] starts at zero and increments for every new IP release.            */
5064             uint32_t            : 24;
5065     } PERIPHERALID2_b;
5066   } ;
5067 
5068   union {
5069     __IOM uint32_t PERIPHERALID3;               /*!< (@ 0x00000FEC) Peripheral ID 3 (PID3).                                    */
5070 
5071     struct {
5072       __IOM uint32_t CMOD       : 4;            /*!< [3..0] Customer Modified, normally zero, but if a partner applies
5073                                                      any changes themselves, they must change this value.                      */
5074       __IOM uint32_t REVAND     : 4;            /*!< [7..4] starts at zero for every Revision, and increments if
5075                                                      metal fixes are applied between 2 IP releases.                            */
5076             uint32_t            : 24;
5077     } PERIPHERALID3_b;
5078   } ;
5079 
5080   union {
5081     __IOM uint32_t COMPONENTID0;                /*!< (@ 0x00000FF0) Component ID0.                                             */
5082 
5083     struct {
5084       __IOM uint32_t PRMBL0     : 8;            /*!< [7..0] constant 0xD                                                       */
5085             uint32_t            : 24;
5086     } COMPONENTID0_b;
5087   } ;
5088 
5089   union {
5090     __IOM uint32_t COMPONENTID1;                /*!< (@ 0x00000FF4) Component ID1.                                             */
5091 
5092     struct {
5093       __IOM uint32_t PRMBL1     : 4;            /*!< [3..0] constant 0x0                                                       */
5094       __IOM uint32_t CLASS      : 4;            /*!< [7..4] component type 0 0xF for Cryptocell                                */
5095             uint32_t            : 24;
5096     } COMPONENTID1_b;
5097   } ;
5098 
5099   union {
5100     __IOM uint32_t COMPONENTID2;                /*!< (@ 0x00000FF8) Component ID2.                                             */
5101 
5102     struct {
5103       __IOM uint32_t PRMBL2     : 8;            /*!< [7..0] constant 0x5                                                       */
5104             uint32_t            : 24;
5105     } COMPONENTID2_b;
5106   } ;
5107 
5108   union {
5109     __IOM uint32_t COMPONENTID3;                /*!< (@ 0x00000FFC) Component ID3.                                             */
5110 
5111     struct {
5112       __IOM uint32_t PRMBL3     : 8;            /*!< [7..0] constant 0xB1                                                      */
5113             uint32_t            : 24;
5114     } COMPONENTID3_b;
5115   } ;
5116   __IM  uint32_t  RESERVED53[896];
5117 
5118   union {
5119     __IOM uint32_t HOSTDCUEN0;                  /*!< (@ 0x00001E00) The DCU [31:0] enable register. Note: This is
5120                                                                     a special register, affected by internal
5121                                                                     logic. Test result of this register is NA.                 */
5122 
5123     struct {
5124       __IOM uint32_t HOSTDCUEN0 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
5125     } HOSTDCUEN0_b;
5126   } ;
5127 
5128   union {
5129     __IOM uint32_t HOSTDCUEN1;                  /*!< (@ 0x00001E04) The DCU [63:32] enable register. Note: This is
5130                                                                     a special register, affected by internal
5131                                                                     logic. Test result of this register is NA.                 */
5132 
5133     struct {
5134       __IOM uint32_t HOSTDCUEN1 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
5135     } HOSTDCUEN1_b;
5136   } ;
5137 
5138   union {
5139     __IOM uint32_t HOSTDCUEN2;                  /*!< (@ 0x00001E08) The DCU [95:64] enable register. Note: This is
5140                                                                     a special register, affected by internal
5141                                                                     logic. Test result of this register is NA.                 */
5142 
5143     struct {
5144       __IOM uint32_t HOSTDCUEN2 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
5145     } HOSTDCUEN2_b;
5146   } ;
5147 
5148   union {
5149     __IOM uint32_t HOSTDCUEN3;                  /*!< (@ 0x00001E0C) The DCU [1271:96] enable register. Note: This
5150                                                                     is a special register, affected by internal
5151                                                                     logic. Test result of this register is NA.                 */
5152 
5153     struct {
5154       __IOM uint32_t HOSTDCUEN3 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
5155     } HOSTDCUEN3_b;
5156   } ;
5157 
5158   union {
5159     __IOM uint32_t HOSTDCULOCK0;                /*!< (@ 0x00001E10) The DCU lock register. Note: This is a special
5160                                                                     register, affected by internal logic. Test
5161                                                                     result of this register is NA.                             */
5162 
5163     struct {
5164       __IOM uint32_t HOSTDCULOCK0 : 32;         /*!< [31..0] DCU_lock [31:0] register (a dedicated lock register
5165                                                      per DCU bit).                                                             */
5166     } HOSTDCULOCK0_b;
5167   } ;
5168 
5169   union {
5170     __IOM uint32_t HOSTDCULOCK1;                /*!< (@ 0x00001E14) The DCU lock register. Note: This is a special
5171                                                                     register, affected by internal logic. Test
5172                                                                     result of this register is NA.                             */
5173 
5174     struct {
5175       __IOM uint32_t HOSTDCULOCK1 : 32;         /*!< [31..0] DCU_lock [63:32] register (a dedicated lock register
5176                                                      per DCU bit).                                                             */
5177     } HOSTDCULOCK1_b;
5178   } ;
5179 
5180   union {
5181     __IOM uint32_t HOSTDCULOCK2;                /*!< (@ 0x00001E18) The DCU lock register. Note: This is a special
5182                                                                     register, affected by internal logic. Test
5183                                                                     result of this register is NA.                             */
5184 
5185     struct {
5186       __IOM uint32_t HOSTDCULOCK2 : 32;         /*!< [31..0] DCU_lock [95:64] register (a dedicated lock register
5187                                                      per DCU bit).                                                             */
5188     } HOSTDCULOCK2_b;
5189   } ;
5190 
5191   union {
5192     __IOM uint32_t HOSTDCULOCK3;                /*!< (@ 0x00001E1C) The DCU lock register. Note: This is a special
5193                                                                     register, affected by internal logic. Test
5194                                                                     result of this register is NA.                             */
5195 
5196     struct {
5197       __IOM uint32_t HOSTDCULOCK3 : 32;         /*!< [31..0] DCU_lock [127:96] register (a dedicated lock register
5198                                                      per DCU bit).                                                             */
5199     } HOSTDCULOCK3_b;
5200   } ;
5201 
5202   union {
5203     __IOM uint32_t AOICVDCURESTRICTIONMASK0;    /*!< (@ 0x00001E20) The DCU lock register.                                     */
5204 
5205     struct {
5206       __IOM uint32_t AOICVDCURESTRICTIONMASK0 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [31:0] parameter, that will
5207                                                      be a customer modifiable.                                                 */
5208     } AOICVDCURESTRICTIONMASK0_b;
5209   } ;
5210 
5211   union {
5212     __IOM uint32_t AOICVDCURESTRICTIONMASK1;    /*!< (@ 0x00001E24) The 'ICV_DCU_restriction_mask' parameter is read
5213                                                                     by FW during the secure debug verification
5214                                                                     to prevent OEM from setting specific DCUs
5215                                                                     that protect ICV secrets                                   */
5216 
5217     struct {
5218       __IOM uint32_t AOICVDCURESTRICTIONMASK1 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [63:32] parameter, that
5219                                                      will be a customer modifiable.                                            */
5220     } AOICVDCURESTRICTIONMASK1_b;
5221   } ;
5222 
5223   union {
5224     __IOM uint32_t AOICVDCURESTRICTIONMASK2;    /*!< (@ 0x00001E28) The 'ICV_DCU_restriction_mask' parameter is read
5225                                                                     by FW during the secure debug verification
5226                                                                     to prevent OEM from setting specific DCUs
5227                                                                     that protect ICV secrets                                   */
5228 
5229     struct {
5230       __IOM uint32_t AOICVDCURESTRICTIONMASK2 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [95:64] parameter, that
5231                                                      will be a customer modifiable.                                            */
5232     } AOICVDCURESTRICTIONMASK2_b;
5233   } ;
5234 
5235   union {
5236     __IOM uint32_t AOICVDCURESTRICTIONMASK3;    /*!< (@ 0x00001E2C) The 'ICV_DCU_restriction_mask' parameter is read
5237                                                                     by FW during the secure debug verification
5238                                                                     to prevent OEM from setting specific DCUs
5239                                                                     that protect ICV secrets                                   */
5240 
5241     struct {
5242       __IOM uint32_t AOICVDCURESTRICTIONMASK3 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [127:96] parameter, that
5243                                                      will be a customer modifiable.                                            */
5244     } AOICVDCURESTRICTIONMASK3_b;
5245   } ;
5246 
5247   union {
5248     __IOM uint32_t AOCCSECDEBUGRESET;           /*!< (@ 0x00001E30) The reset-upon-debug indication                            */
5249 
5250     struct {
5251       __IOM uint32_t AOCCSECDEBUGRESET : 1;     /*!< [0..0] For resets Cerberus, and prevents loading the HW keys
5252                                                      after that reset                                                          */
5253             uint32_t            : 31;
5254     } AOCCSECDEBUGRESET_b;
5255   } ;
5256 
5257   union {
5258     __IOM uint32_t HOSTAOLOCKBITS;              /*!< (@ 0x00001E34) These masks will define, per LCS, which DCU bits
5259                                                                     will be tied to zero, even if the Host tries
5260                                                                     to set them. Note: This is a special register,
5261                                                                     affected by internal logic. Test result
5262                                                                     of this register is NA.                                    */
5263 
5264     struct {
5265       __IOM uint32_t HOSTFATALERR : 1;          /*!< [0..0] When the 'FATAL_ERROR' register is asserted - HW keys
5266                                                      will not be copied from OTP                                               */
5267       __IOM uint32_t HOSTKPICVLOCK : 1;         /*!< [1..1] When this FW controlled register is set, the Kpicv HW
5268                                                      key is masked (to zero).                                                  */
5269       __IOM uint32_t HOSTKCEICVLOCK : 1;        /*!< [2..2] When this FW controlled register is set, the Kceicv HW
5270                                                      key is masked (to zero).                                                  */
5271       __IOM uint32_t HOSTKCPLOCK : 1;           /*!< [3..3] When this FW controlled register is set, the Kcp HW key
5272                                                      is masked (to zero).                                                      */
5273       __IOM uint32_t HOSTKCELOCK : 1;           /*!< [4..4] When this FW controlled register is set, the Kce HW key
5274                                                      is masked (to zero).                                                      */
5275       __IOM uint32_t HOSTICVRMALOCK : 1;        /*!< [5..5] The ICV_RMA_LOCK register is set-once (per POR).                   */
5276       __IOM uint32_t RESETUPONDEBUGDISABLE : 1; /*!< [6..6] The RESET_UPON_DEBUG_DISABLE register is set-once (per
5277                                                      POR).                                                                     */
5278       __IOM uint32_t HOSTFORCEDFAENABLE : 1;    /*!< [7..7] When this FW controlled register is set, the AES DFA
5279                                                      countermeasures are enabled_disabled (regardless of the
5280                                                      AES_DFA_IS_ON register value).                                            */
5281       __IOM uint32_t HOSTDFAENABLELOCK : 1;     /*!< [8..8] When this FW control is set, the DFA_ENABLE register
5282                                                      cant be written until the next POR. The DFA_ENABLE_LOCK
5283                                                      register is set-once (per POR).                                           */
5284             uint32_t            : 23;
5285     } HOSTAOLOCKBITS_b;
5286   } ;
5287 
5288   union {
5289     __IOM uint32_t AOAPBFILTERING;              /*!< (@ 0x00001E38) This register holds the AO_APB_FILTERING data.
5290                                                                     Note: This is a special register, affected
5291                                                                     by internal logic. Test result of this register
5292                                                                     is NA.                                                     */
5293 
5294     struct {
5295       __IOM uint32_t ONLYSECACCESSALLOW : 1;    /*!< [0..0] when this FW controlled register is set, the APB slave
5296                                                      accepts only secure accesses                                              */
5297       __IOM uint32_t ONLYSECACCESSALLOWLOCK : 1;/*!< [1..1] when this FW controlled register is set, the ONLY_SEC_ACCESS_ALLOWED
5298                                                      register cant be modified (until the next POR).                           */
5299       __IOM uint32_t ONLYPRIVACCESSALLOW : 1;   /*!< [2..2] when this FW controlled register is set, the APB slave
5300                                                      accepts only privileged accesses                                          */
5301       __IOM uint32_t ONLYPRIVACCESSALLOWLOCK : 1;/*!< [3..3] when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLO
5302                                                      ED register cant be modified (until the next POR)                         */
5303       __IOM uint32_t APBCONLYSECACCESSALLOW : 1;/*!< [4..4] when this FW controlled register is set, the APB-C slave
5304                                                      accepts only secure accesses                                              */
5305       __IOM uint32_t APBCONLYSECACCESSALLOWLOCK : 1;/*!< [5..5] when this FW controlled register is set, the APBC_ONLY_SEC_ACCESS_ALLOW
5306                                                      D register cant be modified (until the next POR).                         */
5307       __IOM uint32_t APBCONLYPRIVACCESSALLOW : 1;/*!< [6..6] when this FW controlled register is set, the APB-C slave
5308                                                      accepts only privileged accesses                                          */
5309       __IOM uint32_t APBCONLYPRIVACCESSALLOWLOCK : 1;/*!< [7..7] when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLO
5310                                                      ED register cant be modified (until the next POR)                         */
5311       __IOM uint32_t APBCONLYINSTACCESSALLOW : 1;/*!< [8..8] when this FW controlled register is set, the APB-C slave
5312                                                      accepts only instruction accesses                                         */
5313       __IOM uint32_t APBCONLYINSTACCESSALLOWLOCK : 1;/*!< [9..9] when this FW controlled register is set, the APBC_ONLY_INST_ACCESS_ALLO
5314                                                      ED register cant be modified (until the next POR)                         */
5315             uint32_t            : 22;
5316     } AOAPBFILTERING_b;
5317   } ;
5318 
5319   union {
5320     __IOM uint32_t AOCCGPPC;                    /*!< (@ 0x00001E3C) holds the AO_CC_GPPC value from AONote: This
5321                                                                     is a special register, affected by internal
5322                                                                     logic. Test result of this register is NA.                 */
5323 
5324     struct {
5325       __IOM uint32_t AOCCGPPC   : 8;            /*!< [7..0] The AO_CC_GPPC value                                               */
5326             uint32_t            : 24;
5327     } AOCCGPPC_b;
5328   } ;
5329 
5330   union {
5331     __IOM uint32_t HOSTRGFCCSWRST;              /*!< (@ 0x00001E40) Writing to this register generates a general
5332                                                                     reset to CryptoCell. This reset takes about
5333                                                                     4 core clock cycles.Note: This is a special
5334                                                                     register, affected by internal logic. Test
5335                                                                     result of this register is NA.                             */
5336 
5337     struct {
5338       __IOM uint32_t HOSTRGFCCSWRST : 1;        /*!< [0..0] Writing 1 to this field generates a general reset to
5339                                                      CryptoCell.                                                               */
5340             uint32_t            : 31;
5341     } HOSTRGFCCSWRST_b;
5342   } ;
5343   __IM  uint32_t  RESERVED54[48];
5344 
5345   union {
5346     __IOM uint32_t AIBFUSEPROGCOMPLETED;        /*!< (@ 0x00001F04) This register reflects the fuse_aib_prog_completed
5347                                                                     input, which indicates that the fuse programming
5348                                                                     was completed.Note: This is a special register,
5349                                                                     affected by internal logic. Test result
5350                                                                     of this register is NA.                                    */
5351 
5352     struct {
5353       __IOM uint32_t AIBFUSEPROGCOMPLETED : 1;  /*!< [0..0] Indicates if the fuse programming operation has been
5354                                                      completed.                                                                */
5355             uint32_t            : 31;
5356     } AIBFUSEPROGCOMPLETED_b;
5357   } ;
5358 
5359   union {
5360     __IOM uint32_t NVMDEBUGSTATUS;              /*!< (@ 0x00001F08) AIB debug status register. Note: This is a special
5361                                                                     register, affected by internal logic. Test
5362                                                                     result of this register is NA.                             */
5363 
5364     struct {
5365             uint32_t            : 1;
5366       __IOM uint32_t NVMSM      : 3;            /*!< [3..1] Main nvm fsm                                                       */
5367             uint32_t            : 28;
5368     } NVMDEBUGSTATUS_b;
5369   } ;
5370 
5371   union {
5372     __IOM uint32_t LCSISVALID;                  /*!< (@ 0x00001F0C) Indicates that the LCS register holds a valid
5373                                                                     value.Note: This is a special register,
5374                                                                     affected by internal logic. Test result
5375                                                                     of this register is NA.                                    */
5376 
5377     struct {
5378       __IOM uint32_t LCSISVALIDREG : 1;         /*!< [0..0] Indicates whether LCS is valid.                                    */
5379             uint32_t            : 31;
5380     } LCSISVALID_b;
5381   } ;
5382 
5383   union {
5384     __IOM uint32_t NVMISIDLE;                   /*!< (@ 0x00001F10) Indicates that the LCS register holds a valid
5385                                                                     value.Note: This is a special register,
5386                                                                     affected by internal logic. Test result
5387                                                                     of this register is NA.                                    */
5388 
5389     struct {
5390       __IOM uint32_t NVMISIDLEREG : 1;          /*!< [0..0] Indicates whether the NVM manager finishes its operation,
5391                                                      calculates the LCS, reads the HW keys, compares the number
5392                                                      of zeros and clears the keys                                              */
5393             uint32_t            : 31;
5394     } NVMISIDLE_b;
5395   } ;
5396 
5397   union {
5398     __IOM uint32_t LCSREG;                      /*!< (@ 0x00001F14) The lifecycle state register. Note: This is a
5399                                                                     special register, affected by internal logic.
5400                                                                     Test result of this register is NA.                        */
5401 
5402     struct {
5403       __IOM uint32_t LCSREG     : 3;            /*!< [2..0] Indicates the LCS (Lifecycle State) value.                         */
5404             uint32_t            : 5;
5405       __IOM uint32_t ERRORKDRZEROCNT : 1;       /*!< [8..8] Indication that the number of zeroes in the loaded KDR
5406                                                      is not equal to the value set in the manufacture flag.                    */
5407       __IOM uint32_t ERRORPROVZEROCNT : 1;      /*!< [9..9] Indication that the number of zeroes in the loaded KCP
5408                                                      is not equal to the value set in the OEM flag.                            */
5409       __IOM uint32_t ERRORKCEZEROCNT : 1;       /*!< [10..10] Indication that the number of zeroes in the loaded
5410                                                      KCE is not equal to the value set in the OEM flag.                        */
5411       __IOM uint32_t ERRORKPICVZEROCNT : 1;     /*!< [11..11] Indication that the number of zeroes in the loaded
5412                                                      KPICV is not equal to the value set in the manufacture
5413                                                      flag.                                                                     */
5414       __IOM uint32_t ERRORKCEICVZEROCNT : 1;    /*!< [12..12] Indication that the number of zeroes in the loaded
5415                                                      KCEICV is not equal to the value set in the manufacture
5416                                                      flag.                                                                     */
5417             uint32_t            : 19;
5418     } LCSREG_b;
5419   } ;
5420 
5421   union {
5422     __IOM uint32_t HOSTSHADOWKDRREG;            /*!< (@ 0x00001F18) This register interface is used to update the
5423                                                                     RKEK(KDR) registers when the device is in
5424                                                                     CM or DM mode , it is Write-once (per warm
5425                                                                     boot) in RMA LCS, The RKEK is updated by
5426                                                                     shifting .                                                 */
5427 
5428     struct {
5429       __IOM uint32_t HOSTSHADOWKDRREG : 1;      /*!< [0..0] This field is used to update the KDR registers when the
5430                                                      device is in CM , DM or RMA mode, The KDR is updated by
5431                                                      shifting .                                                                */
5432             uint32_t            : 31;
5433     } HOSTSHADOWKDRREG_b;
5434   } ;
5435 
5436   union {
5437     __IOM uint32_t HOSTSHADOWKCPREG;            /*!< (@ 0x00001F1C) This register interface is used to update the
5438                                                                     KCP registers when the device is in CM or
5439                                                                     DM mode, The KCP is updated by shifting                    */
5440 
5441     struct {
5442       __IOM uint32_t HOSTSHADOWKCPREG : 1;      /*!< [0..0] This field is used to update the KCP registers when the
5443                                                      device is in CM or DM mode, The KCP is updated by shifting                */
5444             uint32_t            : 31;
5445     } HOSTSHADOWKCPREG_b;
5446   } ;
5447 
5448   union {
5449     __IOM uint32_t HOSTSHADOWKCEREG;            /*!< (@ 0x00001F20) This register interface is used to update the
5450                                                                     KCE registers when the device is in CM or
5451                                                                     DM mode, The KCE is updated by shifting                    */
5452 
5453     struct {
5454       __IOM uint32_t HOSTSHADOWKCEREG : 1;      /*!< [0..0] This field is used to update the KCE registers when the
5455                                                      device is in CM or DM mode, The KCE is updated by shifting                */
5456             uint32_t            : 31;
5457     } HOSTSHADOWKCEREG_b;
5458   } ;
5459 
5460   union {
5461     __IOM uint32_t HOSTSHADOWKPICVREG;          /*!< (@ 0x00001F24) This register interface is used to update the
5462                                                                     KPICV registers when the device is in CM
5463                                                                     or DM mode, The KPICV is updated by shifting               */
5464 
5465     struct {
5466       __IOM uint32_t HOSTSHADOWKPICVREG : 1;    /*!< [0..0] This field is used to update the KPICV registers when
5467                                                      the device is in CM or DM mode, The KPICV is updated by
5468                                                      shifting                                                                  */
5469             uint32_t            : 31;
5470     } HOSTSHADOWKPICVREG_b;
5471   } ;
5472 
5473   union {
5474     __IOM uint32_t HOSTSHADOWKCEICVREG;         /*!< (@ 0x00001F28) This register interface is used to update the
5475                                                                     KCEICV registers when the device is in CM
5476                                                                     or DM mode, The KCEICV is updated by shifting              */
5477 
5478     struct {
5479       __IOM uint32_t HOSTSHADOWKCEICVREG : 1;   /*!< [0..0] This field is used to update the KCEICV registers when
5480                                                      the device is in CM or DM mode, The KCEICV is updated by
5481                                                      shifting                                                                  */
5482             uint32_t            : 31;
5483     } HOSTSHADOWKCEICVREG_b;
5484   } ;
5485 
5486   union {
5487     __IOM uint32_t OTPADDRWIDTHDEF;             /*!< (@ 0x00001F2C) OTP_ADDR_WIDTH parameter, that will define the
5488                                                                     integrated OTP address width (address in
5489                                                                     words). The supported sizes are 6 (for 2
5490                                                                     Kbits),7,8,9,11 (for 64 Kbits). The default
5491                                                                     value in the provided RTL will be 6.Note:
5492                                                                     This is a special register, affected by
5493                                                                     internal logic. Test result of this register
5494                                                                     is NA.                                                     */
5495 
5496     struct {
5497       __IOM uint32_t OTPADDRWIDTHDEF : 4;       /*!< [3..0] Holds the OTP_ADDR_WIDTH_DEF value.                                */
5498             uint32_t            : 28;
5499     } OTPADDRWIDTHDEF_b;
5500   } ;
5501 } CRYPTO_Type;                                  /*!< Size = 7984 (0x1f30)                                                      */
5502 
5503 
5504 
5505 /* =========================================================================================================================== */
5506 /* ================                                            DC                                             ================ */
5507 /* =========================================================================================================================== */
5508 
5509 
5510 /**
5511   * @brief Display Controller (DC)
5512   */
5513 
5514 typedef struct {                                /*!< (@ 0x400A0000) DC Structure                                               */
5515 
5516   union {
5517     __IOM uint32_t MODE;                        /*!< (@ 0x00000000) General control register that activates the NEMAp|dc400
5518                                                                     controller and various parameters, sets
5519                                                                     the timing signals' polarity, activates
5520                                                                     the global look-up table for gamma correction
5521                                                                     and chooses the output display formats to
5522                                                                     meet LCD color specifications.                             */
5523 
5524     struct {
5525       __IOM uint32_t TSTMODEN   : 1;            /*!< [0..0] When set to 1, test mode is enabled                                */
5526       __IOM uint32_t DBLHORSCANEN : 1;          /*!< [1..1] When set to 1, double horizontal scan is enabled                   */
5527       __IOM uint32_t LVDSINTEN  : 1;            /*!< [2..2] When set to 1, LVDS interface is enabled                           */
5528       __IOM uint32_t YUYVEN     : 1;            /*!< [3..3] When set to 1, the following output color formats are
5529                                                      enabled : Byte-3 beat Interface enabled, Byte-4 beat (RGBX)
5530                                                      Interface enabled, Two phase serial 12-bit enabled, YUYV
5531                                                      (16-bit mode) enabled, BT.656 enabled, JDI MIP enabled                    */
5532       __IOM uint32_t DBITYPEBEN : 1;            /*!< [4..4] When set to 1, DBI Type-B interface is enabled                     */
5533       __IOM uint32_t DISPFMT    : 4;            /*!< [8..5] Display data format                                                */
5534       __IOM uint32_t COLFMT     : 1;            /*!< [9..9] Output color format:                                               */
5535       __IOM uint32_t LVDSPADSEN : 1;            /*!< [10..10] When set to 1, LVDS output pads are enabled                      */
5536       __IOM uint32_t PLLCLKNDIV : 1;            /*!< [11..11] When set to 1, PLL_CLK is not divided                            */
5537       __IOM uint32_t RSVD0      : 5;            /*!< [16..12] This field is reserved.                                          */
5538       __IOM uint32_t FRAMEUPDTEN : 1;           /*!< [17..17] When set to 1, single frame update is enabled                    */
5539       __IOM uint32_t RSVD1      : 1;            /*!< [18..18] This field is reserved.                                          */
5540       __IOM uint32_t BLANKFRC   : 1;            /*!< [19..19] When set to 1, forces output to blank                            */
5541       __IOM uint32_t GAMARAMPEN : 1;            /*!< [20..20] When set to 1, gamma ramp is enabled                             */
5542       __IOM uint32_t RSVD2      : 1;            /*!< [21..21] This field is reserved.                                          */
5543       __IOM uint32_t PIXCLKPOL  : 1;            /*!< [22..22] Defines Pixel Clock out polarity                                 */
5544       __IOM uint32_t VSYNCEN    : 1;            /*!< [23..23] When set to 1, VSYNC for a single cycle per line is
5545                                                      enabled                                                                   */
5546       __IOM uint32_t DITHEREN   : 1;            /*!< [24..24] When set to 1, dithering is enabled                              */
5547       __IOM uint32_t RSVD3      : 1;            /*!< [25..25] This field is reserved.                                          */
5548       __IOM uint32_t DEPOL      : 1;            /*!< [26..26] Defines DE polarity                                              */
5549       __IOM uint32_t HSYNCPOL   : 1;            /*!< [27..27] Defines HSYNC polarity                                           */
5550       __IOM uint32_t VSYNCPOL   : 1;            /*!< [28..28] Defines VSYNC polarity                                           */
5551       __IOM uint32_t RSVD4      : 1;            /*!< [29..29] This field is reserved.                                          */
5552       __IOM uint32_t CUSOREN    : 1;            /*!< [30..30] When set to 1, programmable cursor is enabled                    */
5553       __IOM uint32_t DC400ACT   : 1;            /*!< [31..31] When set to 1, the dc400 controller is activated                 */
5554     } MODE_b;
5555   } ;
5556 
5557   union {
5558     __IOM uint32_t CLKCTRL;                     /*!< (@ 0x00000004) Setup proper timing with divisor control bits
5559                                                                     and specify the number of lines to be prefetched
5560                                                                     before the start of frame.                                 */
5561 
5562     struct {
5563       __IOM uint32_t DIVIDEVALUE : 6;           /*!< [5..0] Value of first clock divider                                       */
5564       __IOM uint32_t RSVD0      : 2;            /*!< [7..6] This field is reserved.                                            */
5565       __IOM uint32_t LINENUM    : 6;            /*!< [13..8] Number of lines to be prefetched before starting the
5566                                                      frame through DMA. Maximum value is 32                                    */
5567       __IOM uint32_t RSVD1      : 2;            /*!< [15..14] This field is reserved.                                          */
5568       __IOM uint32_t PLL        : 8;            /*!< [23..16] Select PLL Clock                                                 */
5569       __IOM uint32_t LVDS       : 3;            /*!< [26..24] Clock phase shift value for LVDS operation                       */
5570       __IOM uint32_t SECCLKDIV  : 5;            /*!< [31..27] Value of secondary clock divider                                 */
5571     } CLKCTRL_b;
5572   } ;
5573 
5574   union {
5575     __IOM uint32_t BGCOLOR;                     /*!< (@ 0x00000008) Specifies the main background color.                       */
5576 
5577     struct {
5578       __IOM uint32_t ALPHACOLOR : 8;            /*!< [7..0] Color alpha is used as background color                            */
5579       __IOM uint32_t BLUECOLOR  : 8;            /*!< [15..8] Color blue is used as background color                            */
5580       __IOM uint32_t GREENCOLOR : 8;            /*!< [23..16] Color green is used as background color                          */
5581       __IOM uint32_t REDCOLOR   : 8;            /*!< [31..24] Color red is used as background color                            */
5582     } BGCOLOR_b;
5583   } ;
5584 
5585   union {
5586     __IOM uint32_t RESXY;                       /*!< (@ 0x0000000C) Specifies the main X and Y resolutions.                    */
5587 
5588     struct {
5589       __IOM uint32_t YRES       : 16;           /*!< [15..0] Value of Y resolution in pixels                                   */
5590       __IOM uint32_t XRES       : 16;           /*!< [31..16] Value of X resolution in pixels                                  */
5591     } RESXY_b;
5592   } ;
5593   __IM  uint32_t  RESERVED;
5594 
5595   union {
5596     __IOM uint32_t FRONTPORCHXY;                /*!< (@ 0x00000014) Specifies the X and Y dimensions for the Front
5597                                                                     Porch.                                                     */
5598 
5599     struct {
5600       __IOM uint32_t FLINES     : 16;           /*!< [15..0] Specify the number of lines for the front porch Y dimension       */
5601       __IOM uint32_t FPCLKCYCLES : 16;          /*!< [31..16] Specify the pixel clock cycles for the front porch
5602                                                      X dimension                                                               */
5603     } FRONTPORCHXY_b;
5604   } ;
5605 
5606   union {
5607     __IOM uint32_t BLANKINGXY;                  /*!< (@ 0x00000018) Specifies the X and Y dimensions for the Blanking
5608                                                                     Period.                                                    */
5609 
5610     struct {
5611       __IOM uint32_t VSYNCLINES : 16;           /*!< [15..0] Specify the VSYNC lines for the Y dimension blanking
5612                                                      period                                                                    */
5613       __IOM uint32_t HSYNCPULSE : 16;           /*!< [31..16] Specify the HSYNC pulse length for the X dimension
5614                                                      blanking period                                                           */
5615     } BLANKINGXY_b;
5616   } ;
5617 
5618   union {
5619     __IOM uint32_t BACKPORCHXY;                 /*!< (@ 0x0000001C) Specifies the X and Y dimensions for the Back
5620                                                                     Porch.                                                     */
5621 
5622     struct {
5623       __IOM uint32_t BLINES     : 16;           /*!< [15..0] Specify the number of lines for the back porch Y dimension        */
5624       __IOM uint32_t BPCLKCYCLES : 16;          /*!< [31..16] Specify the pixel clock cycles for the back porch X
5625                                                      dimension                                                                 */
5626     } BACKPORCHXY_b;
5627   } ;
5628 
5629   union {
5630     __IOM uint32_t CURSORXY;                    /*!< (@ 0x00000020) Specifies the cursor's start X and Y coordinates.          */
5631 
5632     struct {
5633       __IOM uint32_t CURSORY    : 16;           /*!< [15..0] Specify cursor's Y dimension                                      */
5634       __IOM uint32_t CURSORX    : 16;           /*!< [31..16] Specify cursor's X dimension                                     */
5635     } CURSORXY_b;
5636   } ;
5637   __IM  uint32_t  RESERVED1;
5638 
5639   union {
5640     __IOM uint32_t DBICFG;                      /*!< (@ 0x00000028) Register for the configuration DBI Type-B interface
5641                                                                     and the activation of SPI 3-/4-wire interfaces.            */
5642 
5643     struct {
5644       __IOM uint32_t DBICOLORFMT : 3;           /*!< [2..0] Set the color format for DBI interface                             */
5645       __IOM uint32_t DATAWDORDER : 3;           /*!< [5..3] Set the data order of the 8-bit data word:                         */
5646       __IOM uint32_t TYPEBWIDTH : 2;            /*!< [7..6] Set DBI Type-B interface width (8, 9 or 16 bits) and
5647                                                      the serial interface:                                                     */
5648       __IOM uint32_t RSVD0      : 3;            /*!< [10..8] This field is reserved.                                           */
5649       __IOM uint32_t BACKPRESSUREEN : 1;        /*!< [11..11] When set to 1, back pressure support is enabled (not
5650                                                      currently supported)                                                      */
5651       __IOM uint32_t RSVD1      : 4;            /*!< [15..12] This field is reserved.                                          */
5652       __IOM uint32_t INVHRZLINE : 1;            /*!< [16..16] When set to 1, inverts the bit-order of the horizontal
5653                                                      line address (used along with DBI_CFG[17] register bit)                   */
5654       __IOM uint32_t BINDCMDS   : 1;            /*!< [17..17] When set to 1, binds the store commands with the RGB
5655                                                      data and two-byte address is sent with each horizontal
5656                                                      line                                                                      */
5657       __IOM uint32_t RSVD2      : 4;            /*!< [21..18] This field is reserved.                                          */
5658       __IOM uint32_t SPI4       : 1;            /*!< [22..22] When set to 1, SPI 4-wire interface is enabled                   */
5659       __IOM uint32_t SPI3       : 1;            /*!< [23..23] When set to 1, SPI 3-wire interface is enabled                   */
5660       __IOM uint32_t RSVD3      : 1;            /*!< [24..24] This field is reserved.                                          */
5661       __IOM uint32_t RESXLOW    : 1;            /*!< [25..25] When set to 1, drives RESX signal low to reset DBI
5662                                                      Type-B interface                                                          */
5663       __IOM uint32_t RSVD4      : 2;            /*!< [27..26] This field is reserved.                                          */
5664       __IOM uint32_t DBIBTEDIS  : 1;            /*!< [28..28] When set to 1, the DBIB_TE signal is disabled                    */
5665       __IOM uint32_t CSXSET     : 1;            /*!< [29..29] Sets the value of DBIB_CSX signal:                               */
5666       __IOM uint32_t CSXCFG     : 1;            /*!< [30..30] When set to 1, the value of the CSX signal of the DBI
5667                                                      interface can be configured from the DBI_CFG[29] register
5668                                                      bit                                                                       */
5669       __IOM uint32_t DBIINTACT  : 1;            /*!< [31..31] When set to 1, the DBI interface is activated                    */
5670     } DBICFG_b;
5671   } ;
5672 
5673   union {
5674     __IOM uint32_t DCGPIO;                      /*!< (@ 0x0000002C) General Purpose register: read/write GPIO external
5675                                                                     pins. This is accumulated as- {CGBYPASS_in,13'd0,ADVANCE_A
5676                                                                     YWAY_in,5'd0,GPIO_in}                                      */
5677 
5678     struct {
5679       __IOM uint32_t RWPINS     : 2;            /*!< [1..0] These are not implemented                                          */
5680       __IOM uint32_t RSVD0      : 5;            /*!< [6..2] This field is reserved.                                            */
5681       __IOM uint32_t ADVANCEANYWAY : 2;         /*!< [8..7] No idea what this is                                               */
5682       __IOM uint32_t RSVD1      : 13;           /*!< [21..9] This field is reserved.                                           */
5683       __IOM uint32_t CGBYPASS   : 10;           /*!< [31..22] No idea what this is                                             */
5684     } DCGPIO_b;
5685   } ;
5686 
5687   union {
5688     __IOM uint32_t LAYER0MODE;                  /*!< (@ 0x00000030) LAYER0_MODE: Activate and set-up layer 0.                  */
5689 
5690     struct {
5691       __IOM uint32_t LAYER0COLMODE : 5;         /*!< [4..0] Color mode                                                         */
5692       __IOM uint32_t RSVD0      : 3;            /*!< [7..5] This field is reserved.                                            */
5693       __IOM uint32_t LAYER0SBLEND : 4;          /*!< [11..8] Source blending function                                          */
5694       __IOM uint32_t LAYER0DBLEND : 4;          /*!< [15..12] Destination blending function                                    */
5695       __IOM uint32_t LAYER0ALPHA : 8;           /*!< [23..16] Alpha layer global value (0x00-0xFF range)                       */
5696       __IOM uint32_t RSVD1      : 2;            /*!< [25..24] This field is reserved.                                          */
5697       __IOM uint32_t LAYER0GAMMA : 1;           /*!< [26..26] When set to 1, Gamma Look Up Table is enabled                    */
5698       __IOM uint32_t LAYER0HLOCK : 1;           /*!< [27..27] When set to 1, HLOCK signal on AHB DMAs is asserted              */
5699       __IOM uint32_t LAYER0PREMULT : 1;         /*!< [28..28] When set to 1, premultiply image alpha is enabled                */
5700       __IOM uint32_t LAYER0BFILTER : 1;         /*!< [29..29] When set to 1, bilinear filtering is enabled                     */
5701       __IOM uint32_t LAYER0FORCE : 1;           /*!< [30..30] When set to 1, force alpha with global alpha is enabled          */
5702       __IOM uint32_t LAYER0EN   : 1;            /*!< [31..31] When set to 1, layer n is enabled                                */
5703     } LAYER0MODE_b;
5704   } ;
5705 
5706   union {
5707     __IOM uint32_t LAYER0STARTXY;               /*!< (@ 0x00000034) X and Y start dimensions of layer 0.                       */
5708 
5709     struct {
5710       __IOM uint32_t LAYER0YOFF : 16;           /*!< [15..0] Specify the pixel offset of the starting Y dimension
5711                                                      of layer 0                                                                */
5712       __IOM uint32_t LAYER0XOFF : 16;           /*!< [31..16] Specify the pixel offset of the starting X dimension
5713                                                      of layer 0                                                                */
5714     } LAYER0STARTXY_b;
5715   } ;
5716 
5717   union {
5718     __IOM uint32_t LAYER0SIZEXY;                /*!< (@ 0x00000038) X and Y size of layer 0.                                   */
5719 
5720     struct {
5721       __IOM uint32_t LAYER0PIXSZEY : 16;        /*!< [15..0] Specify the pixel size of the layer 0 in the Y dimension          */
5722       __IOM uint32_t LAYER0PIXSZEX : 16;        /*!< [31..16] Specify the pixel size of the layer 0 in the X dimension         */
5723     } LAYER0SIZEXY_b;
5724   } ;
5725 
5726   union {
5727     __IOM uint32_t LAYER0ADDR;                  /*!< (@ 0x0000003C) The start address of the framebuffer to be accessed
5728                                                                     by layer 0.                                                */
5729 
5730     struct {
5731       __IOM uint32_t LAYER0STARTADDRFBUF : 32;  /*!< [31..0] Specify the start address of framebuffer for each layer
5732                                                      0.                                                                        */
5733     } LAYER0ADDR_b;
5734   } ;
5735 
5736   union {
5737     __IOM uint32_t LAYER0STRIDE;                /*!< (@ 0x00000040) Specify the stride and the AXI bus burst of layer
5738                                                                     0.                                                         */
5739 
5740     struct {
5741       __IOM uint32_t LAYER0STRIDEDIST : 16;     /*!< [15..0] Specify the stride, which is the distance from line
5742                                                      to line in bytes for each layer 0 memory                                  */
5743       __IOM uint32_t LAYER0AXIBURSTBITS : 3;    /*!< [18..16] Specify the AXI bits per burst in layer 0                        */
5744       __IOM uint32_t LAYER0AXIFIFOTHLD : 2;     /*!< [20..19] Specify the AXI fifo threshold burst start in layer
5745                                                      0                                                                         */
5746       __IOM uint32_t RSVD       : 11;           /*!< [31..21] This field is reserved.                                          */
5747     } LAYER0STRIDE_b;
5748   } ;
5749 
5750   union {
5751     __IOM uint32_t LAYER0RESXY;                 /*!< (@ 0x00000044) X and Y dimensions for the resolution of layer
5752                                                                     0.                                                         */
5753 
5754     struct {
5755       __IOM uint32_t LAYER0PIXRESY : 16;        /*!< [15..0] Specify the layer n pixel resolution in the Y dimension           */
5756       __IOM uint32_t LAYER0PIXRESX : 16;        /*!< [31..16] Specify the layer n pixel resolution in the X dimension          */
5757     } LAYER0RESXY_b;
5758   } ;
5759 
5760   union {
5761     __IOM uint32_t LAYER0SCALEX;                /*!< (@ 0x00000048) Scale X factor of layer 0.                                 */
5762 
5763     struct {
5764       __IOM uint32_t LAYER0XFACTOR : 32;        /*!< [31..0] Specify the scale X factor of layer n (4.14 fixed point
5765                                                      number)                                                                   */
5766     } LAYER0SCALEX_b;
5767   } ;
5768 
5769   union {
5770     __IOM uint32_t LAYER0SCALEY;                /*!< (@ 0x0000004C) Scale Y factor of layer 0.                                 */
5771 
5772     struct {
5773       __IOM uint32_t LAYER0YFACTOR : 32;        /*!< [31..0] Specify the scale Y factor of layer n (4.14 fixed point
5774                                                      number)                                                                   */
5775     } LAYER0SCALEY_b;
5776   } ;
5777 
5778   union {
5779     __IOM uint32_t LAYER1MODE;                  /*!< (@ 0x00000050) Activate and set-up layer 1.                               */
5780 
5781     struct {
5782       __IOM uint32_t LAYER1COLORMODE : 5;       /*!< [4..0] Color mode                                                         */
5783       __IOM uint32_t RSVD0      : 3;            /*!< [7..5] This field is reserved.                                            */
5784       __IOM uint32_t LAYER1SBLEND : 4;          /*!< [11..8] Source blending function                                          */
5785       __IOM uint32_t LAYER1DBLEND : 4;          /*!< [15..12] Destination blending function                                    */
5786       __IOM uint32_t LAYER1ALPHA : 8;           /*!< [23..16] Alpha layer global value (0x00-0xFF range)                       */
5787       __IOM uint32_t RSVD1      : 2;            /*!< [25..24] This field is reserved.                                          */
5788       __IOM uint32_t LAYER1GAMMA : 1;           /*!< [26..26] When set to 1, Gamma Look Up Table is enabled                    */
5789       __IOM uint32_t LAYER1HLOCK : 1;           /*!< [27..27] When set to 1, HLOCK signal on AHB DMAs is asserted              */
5790       __IOM uint32_t LAYER1PREMULT : 1;         /*!< [28..28] When set to 1, premultiply image alpha is enabled                */
5791       __IOM uint32_t LAYER1BFILTER : 1;         /*!< [29..29] When set to 1, bilinear filtering is enabled                     */
5792       __IOM uint32_t LAYER1FORCE : 1;           /*!< [30..30] When set to 1, force alpha with global alpha is enabled          */
5793       __IOM uint32_t LAYER1EN   : 1;            /*!< [31..31] When set to 1, layer n is enabled                                */
5794     } LAYER1MODE_b;
5795   } ;
5796 
5797   union {
5798     __IOM uint32_t LAYER1STARTXY;               /*!< (@ 0x00000054) X and Y start dimensions of layer 1.                       */
5799 
5800     struct {
5801       __IOM uint32_t LAYER1YOFF : 16;           /*!< [15..0] Specify the pixel offset of the starting Y dimension
5802                                                      of layer 1                                                                */
5803       __IOM uint32_t LAYER1XOFF : 16;           /*!< [31..16] Specify the pixel offset of the starting X dimension
5804                                                      of layer 1                                                                */
5805     } LAYER1STARTXY_b;
5806   } ;
5807 
5808   union {
5809     __IOM uint32_t LAYER1SIZEXY;                /*!< (@ 0x00000058) X and Y size of layer 1.                                   */
5810 
5811     struct {
5812       __IOM uint32_t LAYER1PIXSZEY : 16;        /*!< [15..0] Specify the pixel size of the layer 1 in the Y dimension          */
5813       __IOM uint32_t LAYER1PIXSZEX : 16;        /*!< [31..16] Specify the pixel size of the layer 1 in the X dimension         */
5814     } LAYER1SIZEXY_b;
5815   } ;
5816 
5817   union {
5818     __IOM uint32_t LAYER1ADDR;                  /*!< (@ 0x0000005C) The start address of the framebuffer to be accessed
5819                                                                     by layer 1.                                                */
5820 
5821     struct {
5822       __IOM uint32_t LAYER1STARTADDRFBUF : 32;  /*!< [31..0] Specify the start address of framebuffer for each layer
5823                                                      1.                                                                        */
5824     } LAYER1ADDR_b;
5825   } ;
5826 
5827   union {
5828     __IOM uint32_t LAYER1STRIDE;                /*!< (@ 0x00000060) Specify the stride and the AXI bus burst of layer
5829                                                                     1.                                                         */
5830 
5831     struct {
5832       __IOM uint32_t LAYER1STRIDEDIST : 16;     /*!< [15..0] Specify the stride, which is the distance from line
5833                                                      to line in bytes for each layer 1 memory                                  */
5834       __IOM uint32_t LAYER1AXIBURSTBITS : 3;    /*!< [18..16] Specify the AXI bits per burst in layer 1                        */
5835       __IOM uint32_t LAYER1AXIFIFOTHLD : 2;     /*!< [20..19] Specify the AXI fifo threshold burst start in layer
5836                                                      1                                                                         */
5837       __IOM uint32_t RSVD       : 11;           /*!< [31..21] This field is reserved.                                          */
5838     } LAYER1STRIDE_b;
5839   } ;
5840 
5841   union {
5842     __IOM uint32_t LAYER1RESXY;                 /*!< (@ 0x00000064) X and Y dimensions for the resolution of layer
5843                                                                     1.                                                         */
5844 
5845     struct {
5846       __IOM uint32_t LAYER1PIXRESY : 16;        /*!< [15..0] Specify the layer n pixel resolution in the Y dimension           */
5847       __IOM uint32_t LAYER1PIXRESX : 16;        /*!< [31..16] Specify the layer n pixel resolution in the X dimension          */
5848     } LAYER1RESXY_b;
5849   } ;
5850 
5851   union {
5852     __IOM uint32_t LAYER1SCALEX;                /*!< (@ 0x00000068) Scale X factor of layer 1.                                 */
5853 
5854     struct {
5855       __IOM uint32_t LAYER1XFACTOR : 32;        /*!< [31..0] Specify the scale X factor of layer n (4.14 fixed point
5856                                                      number)                                                                   */
5857     } LAYER1SCALEX_b;
5858   } ;
5859 
5860   union {
5861     __IOM uint32_t LAYER1SCALEY;                /*!< (@ 0x0000006C) Scale Y factor of layer 1.                                 */
5862 
5863     struct {
5864       __IOM uint32_t LAYER1YFACTOR : 32;        /*!< [31..0] Specify the scale Y factor of layer n (4.14 fixed point
5865                                                      number)                                                                   */
5866     } LAYER1SCALEY_b;
5867   } ;
5868 
5869   union {
5870     __IOM uint32_t LAYER2MODE;                  /*!< (@ 0x00000070) Activate and set-up layer 2.                               */
5871 
5872     struct {
5873       __IOM uint32_t LAYER2COLORMODE : 5;       /*!< [4..0] Color mode                                                         */
5874       __IOM uint32_t RSVD0      : 3;            /*!< [7..5] This field is reserved.                                            */
5875       __IOM uint32_t LAYER2SBLEND : 4;          /*!< [11..8] Source blending function                                          */
5876       __IOM uint32_t LAYER2DBLEND : 4;          /*!< [15..12] Destination blending function                                    */
5877       __IOM uint32_t LAYER2ALPHA : 8;           /*!< [23..16] Alpha layer global value (0x00-0xFF range)                       */
5878       __IOM uint32_t RSVD1      : 2;            /*!< [25..24] This field is reserved.                                          */
5879       __IOM uint32_t LAYER2GAMMA : 1;           /*!< [26..26] When set to 1, Gamma Look Up Table is enabled                    */
5880       __IOM uint32_t LAYER2HLOCK : 1;           /*!< [27..27] When set to 1, HLOCK signal on AHB DMAs is asserted              */
5881       __IOM uint32_t LAYER2PREMULT : 1;         /*!< [28..28] When set to 1, premultiply image alpha is enabled                */
5882       __IOM uint32_t LAYER2BFILTER : 1;         /*!< [29..29] When set to 1, bilinear filtering is enabled                     */
5883       __IOM uint32_t LAYER2FORCE : 1;           /*!< [30..30] When set to 1, force alpha with global alpha is enabled          */
5884       __IOM uint32_t LAYER2EN   : 1;            /*!< [31..31] When set to 1, layer n is enabled                                */
5885     } LAYER2MODE_b;
5886   } ;
5887 
5888   union {
5889     __IOM uint32_t LAYER2STARTXY;               /*!< (@ 0x00000074) X and Y start dimensions of layer 2.                       */
5890 
5891     struct {
5892       __IOM uint32_t LAYER2YOFF : 16;           /*!< [15..0] Specify the pixel offset of the starting Y dimension
5893                                                      of layer 2                                                                */
5894       __IOM uint32_t LAYER2XOFF : 16;           /*!< [31..16] Specify the pixel offset of the starting X dimension
5895                                                      of layer 2                                                                */
5896     } LAYER2STARTXY_b;
5897   } ;
5898 
5899   union {
5900     __IOM uint32_t LAYER2SIZEXY;                /*!< (@ 0x00000078) X and Y size of layer 2.                                   */
5901 
5902     struct {
5903       __IOM uint32_t LAYER2PIXSZEY : 16;        /*!< [15..0] Specify the pixel size of the layer 2 in the Y dimension          */
5904       __IOM uint32_t LAYER2PIXSZEX : 16;        /*!< [31..16] Specify the pixel size of the layer 2 in the X dimension         */
5905     } LAYER2SIZEXY_b;
5906   } ;
5907 
5908   union {
5909     __IOM uint32_t LAYER2ADDR;                  /*!< (@ 0x0000007C) The start address of the framebuffer to be accessed
5910                                                                     by layer 2.                                                */
5911 
5912     struct {
5913       __IOM uint32_t LAYER2STARTADDRFBUF : 32;  /*!< [31..0] Specify the start address of framebuffer for each layer
5914                                                      2.                                                                        */
5915     } LAYER2ADDR_b;
5916   } ;
5917 
5918   union {
5919     __IOM uint32_t LAYER2STRIDE;                /*!< (@ 0x00000080) Specify the stride and the AXI bus burst of layer
5920                                                                     2.                                                         */
5921 
5922     struct {
5923       __IOM uint32_t LAYER2STRIDEDIST : 16;     /*!< [15..0] Specify the stride, which is the distance from line
5924                                                      to line in bytes for each layer 2 memory                                  */
5925       __IOM uint32_t LAYER2AXIBURSTBITS : 3;    /*!< [18..16] Specify the AXI bits per burst in layer 2                        */
5926       __IOM uint32_t LAYER2AXIFIFOTHLD : 2;     /*!< [20..19] Specify the AXI fifo threshold burst start in layer
5927                                                      2                                                                         */
5928       __IOM uint32_t RSVD       : 11;           /*!< [31..21] This field is reserved.                                          */
5929     } LAYER2STRIDE_b;
5930   } ;
5931 
5932   union {
5933     __IOM uint32_t LAYER2RESXY;                 /*!< (@ 0x00000084) X and Y dimensions for the resolution of layer
5934                                                                     2.                                                         */
5935 
5936     struct {
5937       __IOM uint32_t LAYER2PIXRESY : 16;        /*!< [15..0] Specify the layer n pixel resolution in the Y dimension           */
5938       __IOM uint32_t LAYER2PIXRESX : 16;        /*!< [31..16] Specify the layer n pixel resolution in the X dimension          */
5939     } LAYER2RESXY_b;
5940   } ;
5941 
5942   union {
5943     __IOM uint32_t LAYER2SCALEX;                /*!< (@ 0x00000088) Scale X factor of layer 2.                                 */
5944 
5945     struct {
5946       __IOM uint32_t LAYER2XFACTOR : 32;        /*!< [31..0] Specify the scale X factor of layer n (4.14 fixed point
5947                                                      number)                                                                   */
5948     } LAYER2SCALEX_b;
5949   } ;
5950 
5951   union {
5952     __IOM uint32_t LAYER2SCALEY;                /*!< (@ 0x0000008C) Scale Y factor of layer 2.                                 */
5953 
5954     struct {
5955       __IOM uint32_t LAYER2YFACTOR : 32;        /*!< [31..0] Specify the scale Y factor of layer n (4.14 fixed point
5956                                                      number)                                                                   */
5957     } LAYER2SCALEY_b;
5958   } ;
5959 
5960   union {
5961     __IOM uint32_t LAYER3MODE;                  /*!< (@ 0x00000090) Activate and set-up layer 3.                               */
5962 
5963     struct {
5964       __IOM uint32_t LAYER3COLORMODE : 5;       /*!< [4..0] Color mode                                                         */
5965       __IOM uint32_t RSVD0      : 3;            /*!< [7..5] This field is reserved.                                            */
5966       __IOM uint32_t LAYER3SBLEND : 4;          /*!< [11..8] Source blending function                                          */
5967       __IOM uint32_t LAYER3DBLEND : 4;          /*!< [15..12] Destination blending function                                    */
5968       __IOM uint32_t LAYER3ALPHA : 8;           /*!< [23..16] Alpha layer global value (0x00-0xFF range)                       */
5969       __IOM uint32_t RSVD1      : 2;            /*!< [25..24] This field is reserved.                                          */
5970       __IOM uint32_t LAYER3GAMMA : 1;           /*!< [26..26] When set to 1, Gamma Look Up Table is enabled                    */
5971       __IOM uint32_t LAYER3HLOCK : 1;           /*!< [27..27] When set to 1, HLOCK signal on AHB DMAs is asserted              */
5972       __IOM uint32_t LAYER3PREMULT : 1;         /*!< [28..28] When set to 1, premultiply image alpha is enabled                */
5973       __IOM uint32_t LAYER3BFILTER : 1;         /*!< [29..29] When set to 1, bilinear filtering is enabled                     */
5974       __IOM uint32_t LAYER3FORCE : 1;           /*!< [30..30] When set to 1, force alpha with global alpha is enabled          */
5975       __IOM uint32_t LAYER3EN   : 1;            /*!< [31..31] When set to 1, layer n is enabled                                */
5976     } LAYER3MODE_b;
5977   } ;
5978 
5979   union {
5980     __IOM uint32_t LAYER3STARTXY;               /*!< (@ 0x00000094) X and Y start dimensions of layer 3.                       */
5981 
5982     struct {
5983       __IOM uint32_t LAYER3YOFF : 16;           /*!< [15..0] Specify the pixel offset of the starting Y dimension
5984                                                      of layer 3                                                                */
5985       __IOM uint32_t LAYER3XOFF : 16;           /*!< [31..16] Specify the pixel offset of the starting X dimension
5986                                                      of layer 3                                                                */
5987     } LAYER3STARTXY_b;
5988   } ;
5989 
5990   union {
5991     __IOM uint32_t LAYER3SIZEXY;                /*!< (@ 0x00000098) X and Y size of layer 3.                                   */
5992 
5993     struct {
5994       __IOM uint32_t LAYER3PIXSZEY : 16;        /*!< [15..0] Specify the pixel size of the layer 3 in the Y dimension          */
5995       __IOM uint32_t LAYER3PIXSZEX : 16;        /*!< [31..16] Specify the pixel size of the layer 3 in the X dimension         */
5996     } LAYER3SIZEXY_b;
5997   } ;
5998 
5999   union {
6000     __IOM uint32_t LAYER3ADDR;                  /*!< (@ 0x0000009C) The start address of the framebuffer to be accessed
6001                                                                     by layer 3.                                                */
6002 
6003     struct {
6004       __IOM uint32_t LAYER3STARTADDRFBUF : 32;  /*!< [31..0] Specify the start address of framebuffer for each layer
6005                                                      3.                                                                        */
6006     } LAYER3ADDR_b;
6007   } ;
6008 
6009   union {
6010     __IOM uint32_t LAYER3STRIDE;                /*!< (@ 0x000000A0) Specify the stride and the AXI bus burst of layer
6011                                                                     3.                                                         */
6012 
6013     struct {
6014       __IOM uint32_t LAYER3STRIDEDIST : 16;     /*!< [15..0] Specify the stride, which is the distance from line
6015                                                      to line in bytes for each layer 3 memory                                  */
6016       __IOM uint32_t LAYER3AXIBURSTBITS : 3;    /*!< [18..16] Specify the AXI bits per burst in layer 3                        */
6017       __IOM uint32_t LAYER3AXIFIFOTHLD : 2;     /*!< [20..19] Specify the AXI fifo threshold burst start in layer
6018                                                      3                                                                         */
6019       __IOM uint32_t RSVD       : 11;           /*!< [31..21] This field is reserved.                                          */
6020     } LAYER3STRIDE_b;
6021   } ;
6022 
6023   union {
6024     __IOM uint32_t LAYER3RESXY;                 /*!< (@ 0x000000A4) X and Y dimensions for the resolution of layer
6025                                                                     3.                                                         */
6026 
6027     struct {
6028       __IOM uint32_t LAYER3PIXRESY : 16;        /*!< [15..0] Specify the layer n pixel resolution in the Y dimension           */
6029       __IOM uint32_t LAYER3PIXRESX : 16;        /*!< [31..16] Specify the layer n pixel resolution in the X dimension          */
6030     } LAYER3RESXY_b;
6031   } ;
6032 
6033   union {
6034     __IOM uint32_t LAYER3SCALEX;                /*!< (@ 0x000000A8) Scale X factor of layer 3.                                 */
6035 
6036     struct {
6037       __IOM uint32_t LAYER3XFACTOR : 32;        /*!< [31..0] Specify the scale X factor of layer n (4.14 fixed point
6038                                                      number)                                                                   */
6039     } LAYER3SCALEX_b;
6040   } ;
6041 
6042   union {
6043     __IOM uint32_t LAYER3SCALEY;                /*!< (@ 0x000000AC) Scale Y factor of layer 3.                                 */
6044 
6045     struct {
6046       __IOM uint32_t LAYER3YFACTOR : 32;        /*!< [31..0] Specify the scale Y factor of layer n (4.14 fixed point
6047                                                      number)                                                                   */
6048     } LAYER3SCALEY_b;
6049   } ;
6050   __IM  uint32_t  RESERVED2[14];
6051 
6052   union {
6053     __IOM uint32_t DBICMD;                      /*!< (@ 0x000000E8) Register to read/write commands from/to DBI Type-B
6054                                                                     interface.                                                 */
6055 
6056     struct {
6057       __IOM uint32_t DATA2DBI   : 16;           /*!< [15..0] Data to send to the DBI interface                                 */
6058       __IOM uint32_t RSVD0      : 11;           /*!< [26..16] This field is reserved.                                          */
6059       __IOM uint32_t LOCALSTORE : 1;            /*!< [27..27] When set to 1, bits [15:0] are locally stored as base
6060                                                      address of the horizontal line; it is used along with the
6061                                                      DBI_CFG[17:16] register bits for the SPI interface                        */
6062       __IOM uint32_t READDBI    : 1;            /*!< [28..28] Read from DBI interface                                          */
6063       __IOM uint32_t RSVD1      : 1;            /*!< [29..29] This field is reserved.                                          */
6064       __IOM uint32_t DIRECTDATA : 1;            /*!< [30..30] Send direct data of type 'command' to the DBI interface          */
6065       __IOM uint32_t RSVD2      : 1;            /*!< [31..31] This field is reserved.                                          */
6066     } DBICMD_b;
6067   } ;
6068 
6069   union {
6070     __IOM uint32_t DBIRDAT;                     /*!< (@ 0x000000EC) Data read by DBI Type-B interface are stored
6071                                                                     in the DBI_RDAT register.                                  */
6072 
6073     struct {
6074       __IOM uint32_t READTYPEB  : 32;           /*!< [31..0] Read data from DBI Type-B interface                               */
6075     } DBIRDAT_b;
6076   } ;
6077 
6078   union {
6079     __IOM uint32_t CONFG;                       /*!< (@ 0x000000F0) Information of the layers n activation and setup.          */
6080 
6081     struct {
6082       __IOM uint32_t CFGGLBGAMMAEN : 1;         /*!< [0..0] Indicates that Global Gamma/Palette is enabled                     */
6083       __IOM uint32_t CFGFCURSOREN : 1;          /*!< [1..1] Indicates that fixed cursor is enabled                             */
6084       __IOM uint32_t CFGPCURSOREN : 1;          /*!< [2..2] Indicates that programmable cursor is enabled                      */
6085       __IOM uint32_t CFGDITHEREN : 1;           /*!< [3..3] Indicates that dithering is enabled                                */
6086       __IOM uint32_t CFGFORMATTEN : 1;          /*!< [4..4] Indicates that formatting is enabled                               */
6087       __IOM uint32_t CFGYUVCNVTEN : 1;          /*!< [5..5] Indicates that high quality YUV converter is enabled               */
6088       __IOM uint32_t CFGDBITYPEBEN : 1;         /*!< [6..6] Indicates that DBI Type-B interface is enabled                     */
6089       __IOM uint32_t CFGRGB2YUVEN : 1;          /*!< [7..7] Indicates that RGB to YUV converter is enabled                     */
6090       __IOM uint32_t CFGLAYER0EN : 1;           /*!< [8..8] Indicates that layer 0 is enabled                                  */
6091       __IOM uint32_t CFGLAYER0BLENDER : 1;      /*!< [9..9] Indicates that layer 0 has blender                                 */
6092       __IOM uint32_t CFGLAYER0SCALAR : 1;       /*!< [10..10] Indicates that layer 0 has scaler                                */
6093       __IOM uint32_t CFGLAYER0GAMMALUT : 1;     /*!< [11..11] Indicates that layer 0 has gamma LUT                             */
6094       __IOM uint32_t CFGLAYER1EN : 1;           /*!< [12..12] Indicates that layer 1 is enabled                                */
6095       __IOM uint32_t CFGLAYER1BLENDER : 1;      /*!< [13..13] Indicates that layer 1 has blender                               */
6096       __IOM uint32_t CFGLAYER1SCALAR : 1;       /*!< [14..14] Indicates that layer 1 has scaler                                */
6097       __IOM uint32_t CFGLAYER1GAMMALUT : 1;     /*!< [15..15] Indicates that layer 1 has gamma LUT                             */
6098       __IOM uint32_t CFGLAYER2EN : 1;           /*!< [16..16] Indicates that layer 2 is enabled                                */
6099       __IOM uint32_t CFGLAYER2BLENDER : 1;      /*!< [17..17] Indicates that layer 2 has blender                               */
6100       __IOM uint32_t CFGLAYER2SCALAR : 1;       /*!< [18..18] Indicates that layer 2 has scaler                                */
6101       __IOM uint32_t CFGLAYER2GAMMALUT : 1;     /*!< [19..19] Indicates that layer 2 has gamma LUT                             */
6102       __IOM uint32_t CFGLAYER3EN : 1;           /*!< [20..20] Indicates that layer 3 is enabled                                */
6103       __IOM uint32_t CFGLAYER3BLENDER : 1;      /*!< [21..21] Indicates that layer 3 has blender                               */
6104       __IOM uint32_t CFGLAYER3SCALAR : 1;       /*!< [22..22] Indicates that layer 3 has scaler                                */
6105       __IOM uint32_t CFGLAYER3GAMMALUT : 1;     /*!< [23..23] Indicates that layer 3 has gamma LUT                             */
6106       __IOM uint32_t RSVD       : 8;            /*!< [31..24] This field is reserved.                                          */
6107     } CONFG_b;
6108   } ;
6109 
6110   union {
6111     __IOM uint32_t IDREG;                       /*!< (@ 0x000000F4) Identification Register.                                   */
6112 
6113     struct {
6114       __IOM uint32_t DCID       : 32;           /*!< [31..0] Fixed value for DC ID                                             */
6115     } IDREG_b;
6116   } ;
6117 
6118   union {
6119     __IOM uint32_t INTERRUPT;                   /*!< (@ 0x000000F8) Register interrupts enabled, level or edge enabled.        */
6120 
6121     struct {
6122       __IOM uint32_t INTVSYNCEN : 1;            /*!< [0..0] When set to 1, VSYNC interrupt enabled                             */
6123       __IOM uint32_t INTHSYNCEN : 1;            /*!< [1..1] When set to 1, HSYNC interrupt enabled                             */
6124       __IOM uint32_t INTMMUERR  : 1;            /*!< [2..2] When set to 1, MMU error interrupt enabled                         */
6125       __IOM uint32_t INTTEEN    : 1;            /*!< [3..3] When set to 1, TE interrupt enabled                                */
6126             uint32_t            : 27;
6127       __IOM uint32_t INTTRIGGER : 1;            /*!< [31..31] Interrupt request trigger control                                */
6128     } INTERRUPT_b;
6129   } ;
6130 
6131   union {
6132     __IOM uint32_t STATUS;                      /*!< (@ 0x000000FC) DSI Status register (interrupt and pending activity)       */
6133 
6134     struct {
6135       __IOM uint32_t STATNOTBLANK : 1;          /*!< [0..0] Indicates that the controller is not in active vertical
6136                                                      blanking                                                                  */
6137       __IOM uint32_t STATDE     : 1;            /*!< [1..1] Indicates the DE signal status (0 or 1) at the current
6138                                                      time of reading                                                           */
6139       __IOM uint32_t STATHSYNC  : 1;            /*!< [2..2] Indicates the HSYNC signal status (0 or 1) at the current
6140                                                      time of reading                                                           */
6141       __IOM uint32_t STATVSYNC  : 1;            /*!< [3..3] Indicates the VSYNC signal status and the tearing e?ect
6142                                                      signal status (0 or 1) at the current time of reading                     */
6143       __IOM uint32_t STATCSYNC  : 1;            /*!< [4..4] Indicates the CSYNC signal status (0 or 1) at the current
6144                                                      time of reading                                                           */
6145       __IOM uint32_t STATLAST   : 1;            /*!< [5..5] Indicates that the last row is currently displayed                 */
6146       __IOM uint32_t STATUF     : 1;            /*!< [6..6] Indicates current underflow                                        */
6147       __IOM uint32_t STATSTICKY : 1;            /*!< [7..7] Indicates sticky underflow. This bit clears when interrupt
6148                                                      register is written                                                       */
6149       __IOM uint32_t STATTEAR   : 1;            /*!< [8..8] Indicates DBI Type-B tearing effect                                */
6150             uint32_t            : 1;
6151       __IOM uint32_t STATDBIRGB : 1;            /*!< [10..10] Indicates pending RGB data in DBI interface                      */
6152       __IOM uint32_t STATDBIPENDCOM : 1;        /*!< [11..11] Indicates pending commands in DBI interface                      */
6153       __IOM uint32_t STATDBIPENDTRANS : 1;      /*!< [12..12] Indicates pending output transaction in DBI interface            */
6154             uint32_t            : 19;
6155     } STATUS_b;
6156   } ;
6157 
6158   union {
6159     __IOM uint32_t COLMOD;                      /*!< (@ 0x00000100) Color mode status register indicating formats/back
6160                                                                     pressure are enabled.                                      */
6161 
6162     struct {
6163       __IOM uint32_t CLMDTSC4TSC6 : 1;          /*!< [0..0] Indicates that the TSc4/TSc6 propietary color format
6164                                                      is enabled                                                                */
6165       __IOM uint32_t CLMDTLYUV420 : 1;          /*!< [1..1] Indicates that the TLYUV420 color format is enabled                */
6166       __IOM uint32_t CLMDVYUV420 : 1;           /*!< [2..2] Indicates that the V_YUV420 color format is enabled                */
6167       __IOM uint32_t CLMDBGRA8888 : 1;          /*!< [3..3] Indicates that the BGRA8888 32-bit color format is enabled         */
6168       __IOM uint32_t CLMDABGR8888 : 1;          /*!< [4..4] Indicates that the ABGR8888 32-bit color format is enabled         */
6169       __IOM uint32_t CLMDYUY2   : 1;            /*!< [5..5] Indicates that the YUY2 color format is enabled                    */
6170       __IOM uint32_t CLMDRGB888 : 1;            /*!< [6..6] Indicates that the RGB888 24-bit color format is enabled           */
6171       __IOM uint32_t CLMDYUYV   : 1;            /*!< [7..7] Indicates that the YUYV color format is enabled                    */
6172       __IOM uint32_t CLMDL4     : 1;            /*!< [8..8] Indicates that the L4 color format is enabled                      */
6173       __IOM uint32_t CLMDL1     : 1;            /*!< [9..9] Indicates that the L1 color format is enabled                      */
6174       __IOM uint32_t CLMDL8     : 1;            /*!< [10..10] Indicates that the L8 color format is enabled                    */
6175       __IOM uint32_t CLMDARGB8888 : 1;          /*!< [11..11] Indicates that the ARGB8888 32-bit color format is
6176                                                      enabled                                                                   */
6177       __IOM uint32_t CLMDRGB565 : 1;            /*!< [12..12] Indicates that the RGB565 16-bit color format is enabled         */
6178       __IOM uint32_t CLMDRGB332 : 1;            /*!< [13..13] Indicates that the RGB332 8-bit color format is enabled          */
6179       __IOM uint32_t CLMDRGBA8888 : 1;          /*!< [14..14] Indicates that the RGBA8888 32-bit color format is
6180                                                      enabled                                                                   */
6181       __IOM uint32_t CLMDRGBA5551 : 1;          /*!< [15..15] Indicates that the RGBA5551 16-bit color format is
6182                                                      enabled                                                                   */
6183       __IOM uint32_t CLMDLUT8   : 1;            /*!< [16..16] Indicates that the LUT8 color format is enabled                  */
6184       __IOM uint32_t CLMDTSC    : 1;            /*!< [17..17] Indicates that back pressure support for the DBI Type
6185                                                      B interface is enabled                                                    */
6186       __IOM uint32_t CLMDTSC6   : 1;            /*!< [18..18] Indicates that back pressure support for the DBI Type
6187                                                      B interface is enabled                                                    */
6188       __IOM uint32_t CLMDDBIBEXTCTRL : 1;       /*!< [19..19] Indicates that back pressure support for the DBI Type
6189                                                      B interface is enabled                                                    */
6190       __IOM uint32_t CLMDQPI    : 1;            /*!< [20..20] Indicates that back pressure support for the DBI Type
6191                                                      B interface is enabled                                                    */
6192       __IOM uint32_t CLMDRGBA4444 : 1;          /*!< [21..21] Indicates that back pressure support for the DBI Type
6193                                                      B interface is enabled                                                    */
6194       __IOM uint32_t CLMDARGB4444 : 1;          /*!< [22..22] Indicates that back pressure support for the DBI Type
6195                                                      B interface is enabled                                                    */
6196             uint32_t            : 6;
6197       __IOM uint32_t CLMDJDI    : 1;            /*!< [29..29] Indicates that back pressure support for the DBI Type
6198                                                      B interface is enabled                                                    */
6199       __IOM uint32_t CLMDLVDS   : 1;            /*!< [30..30] Indicates that back pressure support for the DBI Type
6200                                                      B interface is enabled                                                    */
6201       __IOM uint32_t CLMDBKPRESSURE : 1;        /*!< [31..31] Indicates that back pressure support for the DBI Type
6202                                                      B interface is enabled                                                    */
6203     } COLMOD_b;
6204   } ;
6205   __IM  uint32_t  RESERVED3[32];
6206 
6207   union {
6208     __IOM uint32_t CRC;                         /*!< (@ 0x00000184) if cyclic redundancy errors occur, they are written
6209                                                                     in the CRC register.                                       */
6210 
6211     struct {
6212       __IOM uint32_t CRCREG     : 32;           /*!< [31..0] CRC value if CRC error exists                                     */
6213     } CRC_b;
6214   } ;
6215   __IM  uint32_t  RESERVED4[158];
6216 
6217   union {
6218     __IOM uint32_t GLLUT;                       /*!< (@ 0x00000400) R[0]G[0]B[0] thru R[255]G[255]B[255] Global palette,
6219                                                                     gamma correction memory region where x starts
6220                                                                     at 0 thru 255.Access to all 256 registers
6221                                                                     is best accomplished by passing an index
6222                                                                     via a macro. e.g. pseudocode #define DC_L0LUT(n)
6223                                                                     (*((volatile uint32_t*)(&L0LUT + (4*n))))                  */
6224 
6225     struct {
6226       __IOM uint32_t GLLUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6227       __IOM uint32_t GLLUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6228       __IOM uint32_t GLLUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6229             uint32_t            : 8;
6230     } GLLUT_b;
6231   } ;
6232   __IM  uint32_t  RESERVED5[255];
6233 
6234   union {
6235     __IOM uint32_t CURSORDATA;                  /*!< (@ 0x00000800) Color values for the pixel cursor that are used
6236                                                                     with the Cursor LUT where x starts at 0
6237                                                                     thru 127.Access to all 16 registers is best
6238                                                                     accomplished by passing an index via a macro.
6239                                                                     e.g. pseudocode #define DC_CURSORDATA(n)
6240                                                                     (*((volatile uint32_t*)(&CURSORDATA + (4*n))))             */
6241 
6242     struct {
6243       __IOM uint32_t CURDATA70  : 8;            /*!< [7..0] Pixel 'xy' color look up bits                                      */
6244             uint32_t            : 4;
6245       __IOM uint32_t CURDATA3112 : 20;          /*!< [31..12] Pixel 'xy' color look up bits                                    */
6246     } CURSORDATA_b;
6247   } ;
6248   __IM  uint32_t  RESERVED6[127];
6249 
6250   union {
6251     __IOM uint32_t CURSORLUT;                   /*!< (@ 0x00000A00) R[0]G[0]B[0] thru R[15]G[15]B[15] Cursor Look-up
6252                                                                     Table where x starts at 0 thru 15.Access
6253                                                                     to all 16 registers is best accomplished
6254                                                                     by passing an index via a macro. e.g. pseudocode
6255                                                                     #define DC_CURSORLUT(n) (*((volatile uint32_t*)(&CURSORLUT
6256                                                                     + (4*n))))                                                 */
6257 
6258     struct {
6259       __IOM uint32_t CURLUT0B   : 8;            /*!< [7..0] Cursor LUT blue bits                                               */
6260       __IOM uint32_t CURLUT0G   : 8;            /*!< [15..8] Cursor LUT green bits                                             */
6261       __IOM uint32_t CURLUT0R   : 8;            /*!< [23..16] Cursor LUT red bits                                              */
6262             uint32_t            : 8;
6263     } CURSORLUT_b;
6264   } ;
6265   __IM  uint32_t  RESERVED7[383];
6266 
6267   union {
6268     __IOM uint32_t L0LUT;                       /*!< (@ 0x00001000) A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255].
6269                                                                     Layer 0 palette,gamma correction memory
6270                                                                     region where x starts at 0 thru 255.                       */
6271 
6272     struct {
6273       __IOM uint32_t L0LUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6274       __IOM uint32_t L0LUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6275       __IOM uint32_t L0LUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6276       __IOM uint32_t L0LUT0GAMRAMPA : 8;        /*!< [31..24] Gamma ramp alpha bits                                            */
6277     } L0LUT_b;
6278   } ;
6279   __IM  uint32_t  RESERVED8[255];
6280 
6281   union {
6282     __IOM uint32_t L1LUT;                       /*!< (@ 0x00001400) A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255]
6283                                                                     Layer 1 palette,gamma correction memory
6284                                                                     region where x starts at 0 thru 255.Access
6285                                                                     to all 256 registers is best accomplished
6286                                                                     by passing an index via a macro. e.g. pseudocode
6287                                                                     #define DC_L1LUT(n) (*((volatile uint32_t*)(&L1LUT
6288                                                                     + (4*n))))                                                 */
6289 
6290     struct {
6291       __IOM uint32_t L1LUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6292       __IOM uint32_t L1LUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6293       __IOM uint32_t L1LUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6294       __IOM uint32_t L1LUT0GAMRAMPA : 8;        /*!< [31..24] Gamma ramp alpha bits                                            */
6295     } L1LUT_b;
6296   } ;
6297   __IM  uint32_t  RESERVED9[255];
6298 
6299   union {
6300     __IOM uint32_t L2LUT0;                      /*!< (@ 0x00001800) A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255]
6301                                                                     Layer 2 palette,gamma correction memory
6302                                                                     region where x starts at 0 thru 255.Access
6303                                                                     to all 256 registers is best accomplished
6304                                                                     by passing an index via a macro. e.g. pseudocode
6305                                                                     #define DC_L2LUT(n) (*((volatile uint32_t*)(&L2LUT
6306                                                                     + (4*n))))                                                 */
6307 
6308     struct {
6309       __IOM uint32_t L2LUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6310       __IOM uint32_t L2LUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6311       __IOM uint32_t L2LUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6312       __IOM uint32_t L2LUT0GAMRAMPA : 8;        /*!< [31..24] Gamma ramp alpha bits                                            */
6313     } L2LUT0_b;
6314   } ;
6315   __IM  uint32_t  RESERVED10[255];
6316 
6317   union {
6318     __IOM uint32_t L3LUT;                       /*!< (@ 0x00001C00) A[0]R[0]G[0]B[0] thru A[255]R[255]G[255]B[255]
6319                                                                     Layer 3 palette,gamma correction memory
6320                                                                     region where x starts at 0 thru 255.Access
6321                                                                     to all 256 registers is best accomplished
6322                                                                     by passing an index via a macro. e.g. pseudocode
6323                                                                     #define DC_L3LUT(n) (*((volatile uint32_t*)(&L3LUT
6324                                                                     + (4*n))))                                                 */
6325 
6326     struct {
6327       __IOM uint32_t L3LUT0GAMRAMPB : 8;        /*!< [7..0] Gamma ramp blue bits                                               */
6328       __IOM uint32_t L3LUT0GAMRAMPG : 8;        /*!< [15..8] Gamma ramp green bits                                             */
6329       __IOM uint32_t L3LUT0GAMRAMPR : 8;        /*!< [23..16] Gamma ramp red bits                                              */
6330       __IOM uint32_t L3LUT0GAMRAMPA : 8;        /*!< [31..24] Gamma ramp alpha bits                                            */
6331     } L3LUT_b;
6332   } ;
6333 } DC_Type;                                      /*!< Size = 7172 (0x1c04)                                                      */
6334 
6335 
6336 
6337 /* =========================================================================================================================== */
6338 /* ================                                            DSI                                            ================ */
6339 /* =========================================================================================================================== */
6340 
6341 
6342 /**
6343   * @brief Digital Serial Interface Unit (DSI)
6344   */
6345 
6346 typedef struct {                                /*!< (@ 0x400A8000) DSI Structure                                              */
6347 
6348   union {
6349     __IOM uint32_t DEVICEREADY;                 /*!< (@ 0x00000000) Devide Ready register                                      */
6350 
6351     struct {
6352       __IOM uint32_t READY      : 1;            /*!< [0..0] Ready for programming after all count registers and timeout.       */
6353       __IOM uint32_t ULPS       : 2;            /*!< [2..1] ULPS field of the DEVICEREADY register.                            */
6354       __IOM uint32_t DISPLAYBUSPOSSESSEN : 1;   /*!< [3..3] Inform DSI receiver has to be given the bus possession
6355                                                      for receiving the tearing effect trigger message; Reset
6356                                                      by the processor to stop the bus possession of the DSI
6357                                                      receiver; Note: Tearing effect is supported only in Type1;
6358                                                      Display Architecture (command mode only) as suggested by
6359                                                      Display Command Set Specification; Note1: Even if the processor
6360                                                      does not clear the display_bus_possession bit after receiving
6361                                                      the interrupt for tearing effect, DSI-tx controller starts
6362                                                      the activities on the DSI link once the TE t                              */
6363             uint32_t            : 28;
6364     } DEVICEREADY_b;
6365   } ;
6366 
6367   union {
6368     __IOM uint32_t INTRSTAT;                    /*!< (@ 0x00000004) The interrupt status register.                             */
6369 
6370     struct {
6371       __IOM uint32_t RXSOTERROR : 1;            /*!< [0..0] (RW1C) Set to 1 if a start of transmission sequence error
6372                                                      is reported in the Acknowledge packet by the display device               */
6373       __IOM uint32_t RXSOTSYNCERROR : 1;        /*!< [1..1] (RW1C) Set to 1 if synchronisation error occurrence in
6374                                                      the start of transmission sequence is reported in the acknowledge
6375                                                      packet by the display device                                              */
6376       __IOM uint32_t RXEOTSYNCERROR : 1;        /*!< [2..2] (RW1C) Set to 1 if End of transmission synchronisation
6377                                                      Error is reported in the acknowledgment packet by the display
6378                                                      device                                                                    */
6379       __IOM uint32_t RXESCAPEMODE : 1;          /*!< [3..3] (RW1C) Entry Error; Set to 1 if Escape Mode Entry command
6380                                                      is not understandable by the display device and is reported
6381                                                      in the Acknowledge packet by the display device.                          */
6382       __IOM uint32_t RXLPTXSYNCERR : 1;         /*!< [4..4] (RW1C) Rx LP tx sync error; Set to 1 if Low power transmission
6383                                                      sync error occurs in the display device and is reported
6384                                                      in the Acknowledge packet by the display device                           */
6385       __IOM uint32_t RXPERIPHERAL : 1;          /*!< [5..5] (RW1C) Rx Peripheral timeout Error; Set to 1 if the high
6386                                                      speed receive timer value or LP Tx timer value are expired,
6387                                                      display device is reported in the Acknowledge packet                      */
6388       __IOM uint32_t RXFALSECNTRL : 1;          /*!< [6..6] (RW1C) RxFalse Control Error; Set to 1 if a control error
6389                                                      is reported in the acknowledge packet by the display device               */
6390       __IOM uint32_t RxECCS     : 1;            /*!< [7..7] (RW1C) RRxECC single bit error; Set to 1 if ECC syndrome
6391                                                      was computed and corrected for one bit error is reported
6392                                                      in the Acknowledge packet by the display device                           */
6393       __IOM uint32_t RxECCM     : 1;            /*!< [8..8] (RW1C) RxECC multibit error; Set to 1 if there is no
6394                                                      ECC correction for the packet or there are more than 2
6395                                                      bit errors in the packet isreported in the Acknowledge
6396                                                      packet by the display device                                              */
6397       __IOM uint32_t RXCHECKSUM : 1;            /*!< [9..9] (RW1C) Set to 1 if the computed CRC differs from the
6398                                                      received CRC value and is reported in the acknowledge packet
6399                                                      by the display device                                                     */
6400       __IOM uint32_t RxDSINR    : 1;            /*!< [10..10] (RW1C) RxDSI data type not recognised; Set to 1 if
6401                                                      the data type is not recognised by the display device is
6402                                                      reported in the Acknowledge packet by the display device                  */
6403       __IOM uint32_t RxDSIDI    : 1;            /*!< [11..11] (RW1C) RxDSI VC ID invalid; Set to 1 if the virtual
6404                                                      channel ID is invalid by the display device is reported
6405                                                      in the Acknowledge packet by the display device                           */
6406       __IOM uint32_t TXFALSECNTRL : 1;          /*!< [12..12] (RW1C) TxFalse Control Error; Set to 1 if a control
6407                                                      error is observed on the lanes by the Arasan_DSI_host                     */
6408       __IOM uint32_t TXECCS     : 1;            /*!< [13..13] (RW1C) Set to 1 if ECC syndrome was computed and is
6409                                                      corrected for one bit error during the reception of packets
6410                                                      by the Arasan_DSI_host.                                                   */
6411       __IOM uint32_t TXECCM     : 1;            /*!< [14..14] (RW1C) Set to 1 if there is no ECC correction for the
6412                                                      packet or there are more than 2 bit errors in the packet
6413                                                      received by Arasan_DSI_host.                                              */
6414       __IOM uint32_t TXCHECKSUM : 1;            /*!< [15..15] (RW1C) Txchecksum error; Set to 1 if the computed CRC
6415                                                      differs from the received CRC value during the reception
6416                                                      of packets by Arasan_DSI host                                             */
6417       __IOM uint32_t TxDSIN     : 1;            /*!< [16..16] (RW1C) TxDSI data type not recognised; Set to 1 if
6418                                                      the received data type is not recognised                                  */
6419       __IOM uint32_t TxDSII     : 1;            /*!< [17..17] (RW1C) TxDSI VC ID invalid; Set to 1 if the received
6420                                                      virtual channel ID is invalid                                             */
6421       __IOM uint32_t HIGHC      : 1;            /*!< [18..18] (RW1C) High contention;Set to 1 if a LP high fault
6422                                                      is registered by at the D-PHY contention detector. If this
6423                                                      interrupt is set device should be re-enumerated                           */
6424       __IOM uint32_t LOWC       : 1;            /*!< [19..19] (RW1C) Low contention; Set to 1 if a LP low fault is
6425                                                      registered by at the D-PHY contention detector. If this
6426                                                      interrupt is set device should be re-enumerated                           */
6427       __IOM uint32_t FIFOEMPTY  : 1;            /*!< [20..20] (RW1C) Set to 1 if all FIFOs are empty                           */
6428       __IOM uint32_t HSTXTIMEOUT : 1;           /*!< [21..21] (RW1C) Set if a high speed transmission prevails for
6429                                                      more than the expected count value this interrupt is raised               */
6430       __IOM uint32_t LPRXTIMEOUT : 1;           /*!< [22..22] (RW1C) Set if a low power reception count expires this
6431                                                      interrupt is generated                                                    */
6432       __IOM uint32_t TURNARNDACK : 1;           /*!< [23..23] (RW1C) Turn around acknowledge. Set if a turn around
6433                                                      acknowledgement sequence is timeout not received from the
6434                                                      display device                                                            */
6435       __IOM uint32_t ACKWNOERR  : 1;            /*!< [24..24] (RW1C) T ACK_with No_error; Set if acknowledge trigger
6436                                                      message is received with out any error.                                   */
6437       __IOM uint32_t RXINVALID  : 1;            /*!< [25..25] (RW1C) Rx Invalid; Set if acknowledge short packet
6438                                                      shows an invalid transmission count                                       */
6439       __IOM uint32_t RXDSIPROT  : 1;            /*!< [26..26] (RW1C) Rx DSI protocol violation; Set if acknowledge
6440                                                      short packet shows DSI protocol violation error                           */
6441       __IOM uint32_t SPECIALPACK : 1;           /*!< [27..27] (RW1C) Special packet command sent; Set to confirm
6442                                                      the transmission of the DPI event specific commands set
6443                                                      in the dpi control and dpi data                                           */
6444       __IOM uint32_t INITDONE   : 1;            /*!< [28..28] (RW1C) Set 1 indicates that the DSI initialization
6445                                                      is done. DSI Tx is ready to accept the DPI or DBI or Generic
6446                                                      transfer                                                                  */
6447       __IOM uint32_t RXCNT      : 1;            /*!< [29..29] (RW1C) Rx Contention; Set to 1 if contention detected
6448                                                      in the display                                                            */
6449       __IOM uint32_t DPILINETO  : 1;            /*!< [30..30] (RW1C) DPI line time out. Set to 1 indicates that the
6450                                                      line time out during the DPI transfer                                     */
6451       __IOM uint32_t DPIPRGERR  : 1;            /*!< [31..31] (RW1C) Set to 1 indicates that the error in DPI parameters
6452                                                      programming                                                               */
6453     } INTRSTAT_b;
6454   } ;
6455 
6456   union {
6457     __IOM uint32_t INTREN;                      /*!< (@ 0x00000008) Interrupt enable register.                                 */
6458 
6459     struct {
6460       __IOM uint32_t RXSOTERROR : 1;            /*!< [0..0] RX start of transmission; set to enable the interrupt
6461                                                      for start of transmission                                                 */
6462       __IOM uint32_t RXSOTSYNCERROR : 1;        /*!< [1..1] RX start of transmission; Set to enable the interrupt
6463                                                      for start of transmission synchronization error in the
6464                                                      acknowledgement packet reports                                            */
6465       __IOM uint32_t RXEOTSYNCRR : 1;           /*!< [2..2] RxEot Sync Error l set to enable the interrupt for the
6466                                                      end of transmission synchronisation Error in the acknowledgment
6467                                                      packet reports                                                            */
6468       __IOM uint32_t RXESCPMDETRYERR : 1;       /*!< [3..3] RxEscape Mode Entry Error; Set to enable the interrupt
6469                                                      for Escape Mode Entry command error in the acknowledgment
6470                                                      packet reports                                                            */
6471       __IOM uint32_t RXLPTXSYNCERR : 1;         /*!< [4..4] Rx LP tx sync error; Set to enable the interrupt for
6472                                                      Low power transmission sync error in the acknowledgment
6473                                                      packet reports                                                            */
6474       __IOM uint32_t RXPERIPHRCVTOE : 1;        /*!< [5..5] Peripheral receive timeout Error; Set to enable the interrupt
6475                                                      for the high speed timeout Error or Lp tx timeout error
6476                                                      in the acknowledgment packet reports                                      */
6477       __IOM uint32_t RXFALSE    : 1;            /*!< [6..6] RxFalse Control error; set to enable the interrupt for
6478                                                      control error in the acknowledgment packet reports.                       */
6479       __IOM uint32_t RXECCS     : 1;            /*!< [7..7] RxECC single bit error; Set to enable the interrupt for
6480                                                      ECC syndrome computation and one bit error correction for
6481                                                      the acknowledgment packet                                                 */
6482       __IOM uint32_t RXECCM     : 1;            /*!< [8..8] RxECC multibit error; Set to enable the interrupt for
6483                                                      no ECC correction for the packet or there are more than
6484                                                      2 bit errors reported in the acknowledgment packet                        */
6485       __IOM uint32_t RXCHECKSUM : 1;            /*!< [9..9] Rxchecksum error; Set to enable the interrupt for the
6486                                                      computed CRC differs from the received CRC value in the
6487                                                      acknowledgment packet reports                                             */
6488       __IOM uint32_t RxDSIData  : 1;            /*!< [10..10] RxDSI data type not recognised; Set to enable the interrupt
6489                                                      for the un recognised data type in the acknowledgment packet
6490                                                      reports                                                                   */
6491       __IOM uint32_t RxDSIV     : 1;            /*!< [11..11] RxDSI VC ID invalid virtual channel; Set to enable
6492                                                      the interrupt for invalid ID in the acknowledgment packet
6493                                                      reports                                                                   */
6494       __IOM uint32_t TxFalseCntrl : 1;          /*!< [12..12] TxFalse Control; Set to enable the interrupt for the
6495                                                      control error observed on the lanes by the Arasan_DSI_host                */
6496       __IOM uint32_t TxECCS     : 1;            /*!< [13..13] TxECC single bit; Set to enable the interrupt if ECC
6497                                                      syndrome was computed and is corrected for one bit error
6498                                                      during the reception of packets by the Arasan DSI Host                    */
6499       __IOM uint32_t TxECCM     : 1;            /*!< [14..14] TxECC multibit; Set to enable the interrupt if there
6500                                                      is no ECC correction for the packet or there are more than
6501                                                      2 bit errors in the packet received by Arasan DSI host                    */
6502       __IOM uint32_t TXCHCKSUM  : 1;            /*!< [15..15] Txchecksum error; Set to enable the interrupt if the
6503                                                      computed CRC differs from the received CRC value for the
6504                                                      received packets                                                          */
6505       __IOM uint32_t TxDSID     : 1;            /*!< [16..16] TxDSI data type not recognised; Set to enable the interrupt
6506                                                      if the received packets data type is not recognised                       */
6507       __IOM uint32_t TxDSIV     : 1;            /*!< [17..17] TxDSI VC ID invalid; Set to enable the interrupt if
6508                                                      the received packets virtual channel ID is invalid                        */
6509       __IOM uint32_t HIGHC      : 1;            /*!< [18..18] High contention; Set to enable a LP high fault interrupt         */
6510       __IOM uint32_t LOWC       : 1;            /*!< [19..19] Low contention; Set to enable a LP low fault interrupt           */
6511       __IOM uint32_t FIFOEMPTY  : 1;            /*!< [20..20] Set to enable a FIFO empty interrupt                             */
6512       __IOM uint32_t HSTXTIMEOUT : 1;           /*!< [21..21] Set to enable a high speed transmission timeout                  */
6513       __IOM uint32_t LPRXTIMEOUT : 1;           /*!< [22..22] Set to enable low power reception count timeouts                 */
6514       __IOM uint32_t TURNARNDACK : 1;           /*!< [23..23] Set to enable turn around acknowledgement sequence
6515                                                      timeout                                                                   */
6516       __IOM uint32_t ACKWITHNOERR : 1;          /*!< [24..24] ACK with No_error; Set to enable acknowledge trigger
6517                                                      message reception with out any error                                      */
6518       __IOM uint32_t RXINV      : 1;            /*!< [25..25] Rx Invalid transmission count error; Set to enable
6519                                                      acknowledge invalid transmission counterror                               */
6520       __IOM uint32_t RXDSI      : 1;            /*!< [26..26] Rx DSI protocol violation; Set to enable DSI protocol
6521                                                      violation error                                                           */
6522       __IOM uint32_t SPECIALPACK : 1;           /*!< [27..27] Special packet command sent; Set to enable the confirmation
6523                                                      interrupt for transmitting DPI events set in the dpi data
6524                                                      and dpi control registers                                                 */
6525       __IOM uint32_t INITDONE   : 1;            /*!< [28..28] Set 1 indicates that the DSI initialisation is done
6526                                                      DSI Tx is ready to accept the DPI or DBI or Generic transfer              */
6527       __IOM uint32_t RXCONTENT  : 1;            /*!< [29..29] Detected Rx Contention Detected; Set to enable the
6528                                                      interrupt for contention detected error in the acknowledgment
6529                                                      packet reports                                                            */
6530       __IOM uint32_t DPILINETO  : 1;            /*!< [30..30] Dpi line timeout; Set to 1 indicates that the line
6531                                                      time out during the DPI transfer                                          */
6532       __IOM uint32_t DPI        : 1;            /*!< [31..31] PGRMERR DPI program error; Set to 1 indicates that
6533                                                      the error in DPI parameters programming                                   */
6534     } INTREN_b;
6535   } ;
6536 
6537   union {
6538     __IOM uint32_t DSIFUNCPRG;                  /*!< (@ 0x0000000C) DSI function programming register                          */
6539 
6540     struct {
6541       __IOM uint32_t DATALANES  : 3;            /*!< [2..0] The number Data lanes to be supported is programmed by
6542                                                      the processor                                                             */
6543       __IOM uint32_t CHNUMVM    : 2;            /*!< [4..3] Channel number for video mode                                      */
6544       __IOM uint32_t CHNUMCMODE : 2;            /*!< [6..5] Channel Number for command mode is programmed by the
6545                                                      processor                                                                 */
6546       __IOM uint32_t SUPCOLVIDMODE : 3;         /*!< [9..7] Supported colour format for video mode.                            */
6547             uint32_t            : 3;
6548       __IOM uint32_t REGNAME    : 3;            /*!< [15..13] Field description needed here.                                   */
6549             uint32_t            : 16;
6550     } DSIFUNCPRG_b;
6551   } ;
6552 
6553   union {
6554     __IOM uint32_t HSTXTIMEOUT;                 /*!< (@ 0x00000010) Maximum duration allow for the DSi host to remain
6555                                                                     in High speed mode for transmission.                       */
6556 
6557     struct {
6558       __IOM uint32_t MAXDURTOCNT : 24;          /*!< [23..0] The maximum duration allowed for the DSI host to remain
6559                                                      in high speed mode for a transmission. If the counter expires,
6560                                                      processor is interrupted with HS_Tx_timeout interrupt                     */
6561             uint32_t            : 8;
6562     } HSTXTIMEOUT_b;
6563   } ;
6564 
6565   union {
6566     __IOM uint32_t LPRXTO;                      /*!< (@ 0x00000014) Timeout value to be checked for reverse communicationl     */
6567 
6568     struct {
6569       __IOM uint32_t TOCHKRVS   : 24;           /*!< [23..0] Timeout value to be checked for reverse communication.
6570                                                      If the counter expires, processor is interrupted with LP_Rx_timeout
6571                                                      interrupt.The timeout value is protocol specific. Time
6572                                                      out value is calculated from txclkesc(50ns).                              */
6573             uint32_t            : 8;
6574     } LPRXTO_b;
6575   } ;
6576 
6577   union {
6578     __IOM uint32_t TURNARNDTO;                  /*!< (@ 0x00000018) Timeout value to be checked after the DSI host
6579                                                                     makes a trun around in the direction of
6580                                                                     transfers.                                                 */
6581 
6582     struct {
6583       __IOM uint32_t TIMOUT     : 6;            /*!< [5..0] If the counter expires, processor is interrupted with
6584                                                      Turn_around_ack timeout interrupt; this specified period
6585                                                      shall be longer then the maximum possible turnaround delay
6586                                                      for the unit to which the turnaround request was sent,
6587                                                      which is 23 clock cycles of txclkesc; any number greater
6588                                                      than or equal to 23 is an acceptable number.                              */
6589             uint32_t            : 26;
6590     } TURNARNDTO_b;
6591   } ;
6592 
6593   union {
6594     __IOM uint32_t DEVICERESETTIMER;            /*!< (@ 0x0000001C) Timeout value to be checked for device to be
6595                                                                     reset after issuing reset entry command                    */
6596 
6597     struct {
6598       __IOM uint32_t TIMOUT     : 16;           /*!< [15..0] If the timer expires the DSI Host enters normal operation;
6599                                                      This time out value is used while contention recovery procedure;
6600                                                      the time out value is equal to a value longer than the
6601                                                      specified time required to complete the reset sequence                    */
6602             uint32_t            : 16;
6603     } DEVICERESETTIMER_b;
6604   } ;
6605 
6606   union {
6607     __IOM uint32_t DPIRESOLUTION;               /*!< (@ 0x00000020) Shows the horizontal address count in pixels               */
6608 
6609     struct {
6610       __IOM uint32_t DPIRESOLUTION : 32;        /*!< [31..0] DPIRESOLUTION register description needed here.                   */
6611     } DPIRESOLUTION_b;
6612   } ;
6613   __IM  uint32_t  RESERVED;
6614 
6615   union {
6616     __IOM uint32_t HSYNCCNT;                    /*!< (@ 0x00000028) Shows the horizontal sync value in terms of byte
6617                                                                     clock.                                                     */
6618 
6619     struct {
6620       __IOM uint32_t HORZCNT    : 16;           /*!< [15..0] Shows the horizontal sync value in terms of byte clock
6621                                                      (txbyteclkhs); Minimum HSA period should be sufficient
6622                                                      to transmit a Hsync start short packet(4 bytes) i) For
6623                                                      Non-burst Mode with sync pulse, Min value - 4 in decimal
6624                                                      (plus an optional 6 bytes for a zero payload blanking packet);
6625                                                      But if the value is less than 10 but more than 4, then
6626                                                      this count will be added to the HBP's count for one lane;
6627                                                      ii) For Non-Burst Sync Event and Burst Mode, there is no
6628                                                      HSA, so you can program this to zero. If you program thi                  */
6629             uint32_t            : 16;
6630     } HSYNCCNT_b;
6631   } ;
6632 
6633   union {
6634     __IOM uint32_t HORIZBKPORCHCNT;             /*!< (@ 0x0000002C) Shows the horizontal back porch value in terms
6635                                                                     of txbyteclkhs.                                            */
6636 
6637     struct {
6638       __IOM uint32_t HORZBKPCNT : 16;           /*!< [15..0] For Non Burst Sync pulse mode, for one lane. Minimum
6639                                                      HBP count = Hsync End short packet + HBP Blanking packet
6640                                                      overhead (header(4) + crc (2)) + RGB packet header For
6641                                                      other lane counts minimum value = Minimum HBPcount / lane_count.
6642                                                      For Non Burst Sync event / Burst Mode there is no HSA.
6643                                                      Minimum HBP count = (Hsync Start short packet + HBP Blanking
6644                                                      packet overhead + RGB packet header) / lane_count Min value
6645                                                      - 14 in decimal (accounted with zero payloads for blanking
6646                                                      packet] for one lane. Max value - any 12 bit v                            */
6647             uint32_t            : 16;
6648     } HORIZBKPORCHCNT_b;
6649   } ;
6650 
6651   union {
6652     __IOM uint32_t HORIZFPORCHCNT;              /*!< (@ 0x00000030) Shows the horizontal front porch value in terms
6653                                                                     of txbyteclkhs.                                            */
6654 
6655     struct {
6656       __IOM uint32_t HORZFTPCNT : 16;           /*!< [15..0] Minimum HFP period should be sufficient to transmit
6657                                                      RGB Data packet footer (2 bytes) + Blanking packet overhead
6658                                                      (6 bytes) +adjustable count (16 bytes) for non burst mode;
6659                                                      For other lane counts Minimum value = (RGB Data packet
6660                                                      footer(2 bytes) + Blanking packet overhead(6 bytes)) /
6661                                                      (lane_count) + adjustable count(16 bytes) For burst mode,
6662                                                      Minimum HFP period should be sufficient to transmit Blanking
6663                                                      packet overhead(6 bytes) +adjustable count (16 bytes) for
6664                                                      one lane for other lane counts Minimum value = ( Blan                     */
6665             uint32_t            : 16;
6666     } HORIZFPORCHCNT_b;
6667   } ;
6668 
6669   union {
6670     __IOM uint32_t HORZACTIVEAREACNT;           /*!< (@ 0x00000034) Horizontal active area count / time for active
6671                                                                     image data / Horizontal Address                            */
6672 
6673     struct {
6674       __IOM uint32_t HORACTCNT  : 16;           /*!< [15..0] Shows the horizontal active area value in terms of txbyteclkhs.
6675                                                      In Non Burst Mode, Count equal to RGB word count value
6676                                                      In Burst Mode, RGB pixel packets are time compressed, leaving
6677                                                      more time during a scan line for LP mode (saving power)
6678                                                      or for multiplexing other transmissions onto the DSI link.
6679                                                      Hence, the count equals the time in txbyteclkhs for sending
6680                                                      time compressed RGB pixels plus the time needed for moving
6681                                                      to power save mode or the time needed for secondary channel
6682                                                      to use the DSI link. But if the lef                                       */
6683             uint32_t            : 16;
6684     } HORZACTIVEAREACNT_b;
6685   } ;
6686 
6687   union {
6688     __IOM uint32_t VSYNCCNT;                    /*!< (@ 0x00000038) Shows the vertical sync value                              */
6689 
6690     struct {
6691       __IOM uint32_t VSC        : 16;           /*!< [15..0] Shows the vertical sync value in terms of lines. Min
6692                                                      value - 2 Max value - any 12 bit value greater than 2 based
6693                                                      on DPI resolution                                                         */
6694             uint32_t            : 16;
6695     } VSYNCCNT_b;
6696   } ;
6697 
6698   union {
6699     __IOM uint32_t VERTBKPORCHCNT;              /*!< (@ 0x0000003C) Shows the vertical back porch value                        */
6700 
6701     struct {
6702       __IOM uint32_t VBPSC      : 16;           /*!< [15..0] Shows the vertical back porch value in terms of lines.
6703                                                      Min value - 1; Max value - any 12 bit value greater than
6704                                                      1 based on DPI resolution                                                 */
6705             uint32_t            : 16;
6706     } VERTBKPORCHCNT_b;
6707   } ;
6708 
6709   union {
6710     __IOM uint32_t VERTFPORCHCNT;               /*!< (@ 0x00000040) Shows the vertical front porch value                       */
6711 
6712     struct {
6713       __IOM uint32_t VFPSC      : 16;           /*!< [15..0] Shows the vertical front porch value in terms of lines.
6714                                                      Min value - 1; Max value - any 12 bit value greater than
6715                                                      1 based on DPI resolution                                                 */
6716             uint32_t            : 16;
6717     } VERTFPORCHCNT_b;
6718   } ;
6719 
6720   union {
6721     __IOM uint32_t DATALANEHILOSWCNT;           /*!< (@ 0x00000044) High speed to low power or Low power to high
6722                                                                     speed switching time                                       */
6723 
6724     struct {
6725       __IOM uint32_t DATALHLSWCNT : 16;         /*!< [15..0] High speed to low power or Low power to high speed power
6726                                                      or Low switching time in terms byte clock (txbyteclkhs).
6727                                                      This power to high speed switch count value is based on
6728                                                      the byte clock (txbyteclkhs) and low power clock frequency
6729                                                      (txclkesc); Data lane Switch count = 4 * Tlpx + programmed
6730                                                      THS_prep + programmed THS_zero + 4 byteclk Tlpx = Low power
6731                                                      clock equivalence in of terms byte clock programmed in
6732                                                      AHB reg 68h; THS_prep = programmed value of dln_cnt_hs_prep
6733                                                      in AHB Reg 6ch bit (7:0) THS_zero = programmed v                          */
6734             uint32_t            : 16;
6735     } DATALANEHILOSWCNT_b;
6736   } ;
6737 
6738   union {
6739     __IOM uint32_t DPI;                         /*!< (@ 0x00000048) DPI control register.                                      */
6740 
6741     struct {
6742       __IOM uint32_t SHUTDOWN   : 1;            /*!< [0..0] Set to 1 to indicate a shut down short packet has to
6743                                                      be packetised for the DPIs virtual channel                                */
6744       __IOM uint32_t TURNON1    : 1;            /*!< [1..1] Set to 1 to indicate a Turn ON short packet has to be
6745                                                      packetised for the DPIs virtual channel                                   */
6746       __IOM uint32_t COLOR      : 1;            /*!< [2..2] MODEON Set to 1 to indicate a color Mode ON short packet
6747                                                      has to be packetised for the DPIs virtual channel.                        */
6748       __IOM uint32_t COLORMODEOFF : 1;          /*!< [3..3] Set to 1 to indicate a Color Mode OFF short packet has
6749                                                      to be packetised for the DPIs virtual channel                             */
6750             uint32_t            : 28;
6751     } DPI_b;
6752   } ;
6753 
6754   union {
6755     __IOM uint32_t PLLLOCKCNT;                  /*!< (@ 0x0000004C) The PLL counter value                                      */
6756 
6757     struct {
6758       __IOM uint32_t PLLCNTVAL  : 16;           /*!< [15..0] Pll counter value in terms of low power clock.                    */
6759             uint32_t            : 16;
6760     } PLLLOCKCNT_b;
6761   } ;
6762 
6763   union {
6764     __IOM uint32_t INITCNT;                     /*!< (@ 0x00000050) Count register to initialize the DSI HOST IP               */
6765 
6766     struct {
6767       __IOM uint32_t MSTR       : 16;           /*!< [15..0] Counter value in terms of low power clock to initialise
6768                                                      the DSI Host IP (TINIT) that drives a stop state on the
6769                                                      mipis D-PHY bus; DPHY Initialization period min 100 x B5s;
6770                                                      Time out value is calculated by txclkesc and the count
6771                                                      value is 7d0h(2000 in decimal)                                            */
6772             uint32_t            : 16;
6773     } INITCNT_b;
6774   } ;
6775 
6776   union {
6777     __IOM uint32_t MAXRETPACSZE;                /*!< (@ 0x00000054) MAXRETPACSZE register description needed here.             */
6778 
6779     struct {
6780       __IOM uint32_t COUNTVAL   : 11;           /*!< [10..0] Set the count value in bytes to collect the return data
6781                                                      packet for reverse direction data flow in data lane0 in
6782                                                      response to a DBI read operation; Count value equals the
6783                                                      maximum size of the payload in a Long packet transmitted
6784                                                      from peripheral back to; for DBI and DPI interleaving Min
6785                                                      value - 1; Max value - Maximum payload for a long packet
6786                                                      size is 1K bytes Note: DCS short Read Response or Long
6787                                                      read response with 1 or 2 parameters is applicable in this
6788                                                      mode; For DBI only, Min value - 1 Max value - Maximum pa                  */
6789             uint32_t            : 4;
6790       __IOM uint32_t HSLP       : 1;            /*!< [15..15] Indicates the data transfer type                                 */
6791             uint32_t            : 16;
6792     } MAXRETPACSZE_b;
6793   } ;
6794 
6795   union {
6796     __IOM uint32_t VIDEOMODEFMT;                /*!< (@ 0x00000058) Sets the Video mode format (packet sequence)
6797                                                                     to be supported in DSI.                                    */
6798 
6799     struct {
6800       __IOM uint32_t VIDEMDFMT  : 2;            /*!< [1..0] Sets the Video mode format (packet sequence) to be supported
6801                                                      in DSI; in Non Burst Mode, in addition to programming this
6802                                                      register the horizontal active area count register value
6803                                                      should also be programmed equal to RGB word count value;
6804                                                      in Burst Mode, in addition to programming this register
6805                                                      the horizontal active area count register value should
6806                                                      also be programmed greater than the RGB word count value,
6807                                                      leaving more time during a scan line for LP mode (saving
6808                                                      power) or for multiplexing other transmissions onto                       */
6809             uint32_t            : 30;
6810     } VIDEOMODEFMT_b;
6811   } ;
6812 
6813   union {
6814     __IOM uint32_t CLKEOT;                      /*!< (@ 0x0000005C) The EOT clock register disables the video.                 */
6815 
6816     struct {
6817       __IOM uint32_t EOT        : 1;            /*!< [0..0] Set by the processor to enable or disable EOT short disable_register
6818                                                      packet transmission; vy default this register value is
6819                                                      0; for backward compatibility of earlier DSI systems, EOT
6820                                                      short packet transmission can be disabled; 0 EOT short
6821                                                      packet transmission enabled, 1 EOT short packet transmission
6822                                                      disabled                                                                  */
6823       __IOM uint32_t CLOCK      : 1;            /*!< [1..1] Set by the processor to enable or disable clock; Stopping
6824                                                      feature during BLLP timing in a DPI transfer in dual channel
6825                                                      mode or during DPI only mode and also when there is no
6826                                                      traffic in the DBI interface in DBI only enabled mode.
6827                                                      By default this register value is 0.                                      */
6828       __IOM uint32_t BTA        : 1;            /*!< [2..2] Disable video; Set by the processor to inform the DSI
6829                                                      controller to disable the BTA sent at the last blanking
6830                                                      line of VFP. By default, this bit is set to 0; 0 BTA sending
6831                                                      at the last blanking line of VFP is enabled; 1 BTA sending
6832                                                      at the last blanking line of VFP is disabled                              */
6833             uint32_t            : 29;
6834     } CLKEOT_b;
6835   } ;
6836 
6837   union {
6838     __IOM uint32_t POLARITY;                    /*!< (@ 0x00000060) Polarity Register                                          */
6839 
6840     struct {
6841       __IOM uint32_t PBITS      : 4;            /*!< [3..0] Polarity bits                                                      */
6842             uint32_t            : 28;
6843     } POLARITY_b;
6844   } ;
6845 
6846   union {
6847     __IOM uint32_t CLKLANESWT;                  /*!< (@ 0x00000064) High speed to low power switching time in terms
6848                                                                     ofbyte clock (txbyteclkhs)                                 */
6849 
6850     struct {
6851       __IOM uint32_t HISPLPSW   : 16;           /*!< [15..0] High speed to low power switching time in terms byte
6852                                                      clock (txbyteclkhs). This value is based on the byte clock
6853                                                      (txbyteclkhs) and low power clock frequency; HS to LP switch
6854                                                      count = Tclk_trail + THS_Exit + 3 byteclk Tclk_trail =
6855                                                      programmed value of cln_cnt_hs_trail in AHB Reg 70h bit
6856                                                      (23:16) THS_Exit = programmed value of cln_cnt_hs_exit
6857                                                      in AHB Reg 70h bit (31:24) Typical value - Number of byte
6858                                                      clocks request to switch from high speed mode to low power
6859                                                      mode after txrequesths_clk is de-asserted.                                */
6860       __IOM uint32_t LOWPWR2HI  : 16;           /*!< [31..16] This value is based on the byte clock (txbyteclkhs)
6861                                                      and low power clock frequency (txclkesc)LP to HS switch
6862                                                      count = 4 * Tlpx + (programmed Tclk_prep + extracount (1
6863                                                      byteclk) ) + (programmed Tclk_zero + extracount (1 byteclk)
6864                                                      ) + Tclk_pre + 2 byteclk Tlpx = Low power clock equivalence
6865                                                      in terms of byte clock programmed in AHB reg 68h Tclk_prep
6866                                                      = programmed value of cln_cnt_prep in AHB Reg 70h bit (7:0)
6867                                                      Tclk_zero = programmed value of cln_cnt_zero in AHB Reg
6868                                                      70h bit (15:8) Tclk_pre = 8 UI Typical value x96 Nu                       */
6869     } CLKLANESWT_b;
6870   } ;
6871 
6872   union {
6873     __IOM uint32_t LPBYTECLK;                   /*!< (@ 0x00000068) Low power clock equivalence in terms of byte
6874                                                                     clock.                                                     */
6875 
6876     struct {
6877       __IOM uint32_t VALBYTECLK : 16;           /*!< [15..0] The value programmed in this register is equal to the
6878                                                      number of byte clocks occupied in one low power clock;
6879                                                      this value is based on the byte clock (txbyteclkhs) and
6880                                                      low power clock frequency (txclkesc)                                      */
6881             uint32_t            : 16;
6882     } LPBYTECLK_b;
6883   } ;
6884 
6885   union {
6886     __IOM uint32_t DPHYPARAM;                   /*!< (@ 0x0000006C) This field provides the timing requirement in
6887                                                                     byte clocks for the high speed preparation
6888                                                                     time.                                                      */
6889 
6890     struct {
6891       __IOM uint32_t HSPREP     : 8;            /*!< [7..0] This field provides the timing requirement in byte clocks
6892                                                      for the high speed preparation time. This corresponds to
6893                                                      the THS-PREP parameter specified in the DPHY specificaton                 */
6894       __IOM uint32_t HSZERO     : 8;            /*!< [15..8] This field provides the timing requirement in byte clocks
6895                                                      for the high speed drive zero time. This corresponds to
6896                                                      the THS-ZERO parameter specified in the DPHY specification                */
6897       __IOM uint32_t HSTRAIL    : 8;            /*!< [23..16] This field provides the timing requirement in byte
6898                                                      clocks for the high speed trail time; this corresponds
6899                                                      to the THS-TRAIL parameter specified in the DPHY specification            */
6900       __IOM uint32_t HSEXIT     : 8;            /*!< [31..24] This field provides the timing requirement in byte
6901                                                      clocks for the high speed exit time; this corresponds to
6902                                                      the THS-EXIT parameter specified in the DPHY specification                */
6903     } DPHYPARAM_b;
6904   } ;
6905 
6906   union {
6907     __IOM uint32_t CLKLANETIMPARM;              /*!< (@ 0x00000070) This field provides the timing requirement in
6908                                                                     byte clocks                                                */
6909 
6910     struct {
6911       __IOM uint32_t HSPREP     : 8;            /*!< [7..0] This field provides the timing requirement in byte corresponds
6912                                                      to the TCLK-PREP parameter specified in the DPHY specificatio             */
6913       __IOM uint32_t HSZERO     : 8;            /*!< [15..8] This field provides the timing requirement in byte clocks
6914                                                      for the high speed drive zero time; this corresponds to
6915                                                      the TCLK-ZERO parameter specified in the DPHY specification               */
6916       __IOM uint32_t HSTRAIL    : 8;            /*!< [23..16] This field provides the timing requirement in byte
6917                                                      clocks for the high speed trail time; This corresponds
6918                                                      to the TCLK-TRAIL parameter specified in the DPHY specification           */
6919       __IOM uint32_t HSEXIT     : 8;            /*!< [31..24] This field provides the timing requirement in byte
6920                                                      clocks for the high speed exit time; This corresponds to
6921                                                      the THS-EXIT parameter specified in the DPHY specification.               */
6922     } CLKLANETIMPARM_b;
6923   } ;
6924 
6925   union {
6926     __IOM uint32_t RSTENBDFE;                   /*!< (@ 0x00000074) This field provides the reset (enable) to the
6927                                                                     DFE                                                        */
6928 
6929     struct {
6930       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] This field provides the reset (enable) to the DFE.                 */
6931             uint32_t            : 31;
6932     } RSTENBDFE_b;
6933   } ;
6934 
6935   union {
6936     __IOM uint32_t AFETRIM0;                    /*!< (@ 0x00000078) Afe Trim reg0                                              */
6937 
6938     struct {
6939       __IOM uint32_t AFETRIM0   : 32;           /*!< [31..0] Afe Trim reg0.                                                    */
6940     } AFETRIM0_b;
6941   } ;
6942 
6943   union {
6944     __IOM uint32_t AFETRIM1;                    /*!< (@ 0x0000007C) Afe Trim reg1                                              */
6945 
6946     struct {
6947       __IOM uint32_t AFETRIM1   : 32;           /*!< [31..0] Afe Trim reg1.                                                    */
6948     } AFETRIM1_b;
6949   } ;
6950 
6951   union {
6952     __IOM uint32_t AFETRIM2;                    /*!< (@ 0x00000080) Afe Trim reg2                                              */
6953 
6954     struct {
6955       __IOM uint32_t AFETRIM2   : 32;           /*!< [31..0] Afe Trim reg2.                                                    */
6956     } AFETRIM2_b;
6957   } ;
6958 
6959   union {
6960     __IOM uint32_t AFETRIM3;                    /*!< (@ 0x00000084) Afe Trim reg3                                              */
6961 
6962     struct {
6963       __IOM uint32_t AFETRIM3   : 32;           /*!< [31..0] Afe Trim reg3.                                                    */
6964     } AFETRIM3_b;
6965   } ;
6966   __IM  uint32_t  RESERVED1[4];
6967 
6968   union {
6969     __IOM uint32_t ERRORAUTORCOV;               /*!< (@ 0x00000098) Errir ayti recivert register                               */
6970 
6971     struct {
6972       __IOM uint32_t ECCMULERRCLR : 1;          /*!< [0..0] if this bit is set to 1, Ecc_mul_err_clr error recovery
6973                                                      action is taken immediately by DSI TX                                     */
6974       __IOM uint32_t INVLDDTCLR : 1;            /*!< [1..1] If this bit is set to 1, Invld_dt_clr error recovery
6975                                                      action is taken immediately by DSI TX                                     */
6976       __IOM uint32_t HICONTCLR  : 1;            /*!< [2..2] If this bit is set to 1, Hi_cont_clr error recover action
6977                                                      is taken immediately by DSI TX                                            */
6978       __IOM uint32_t LOCONTCLR  : 1;            /*!< [3..3] If this bit is set to 1, lo_cont_clr error recovery action
6979                                                      is taken immediately by DSI TX                                            */
6980       __IOM uint32_t HSRXTIMEOUTCLR : 1;        /*!< [4..4] If this bit is set to 1, Hs_rx_timeout_clr error recovery
6981                                                      action is taken immediately by DSI TX                                     */
6982       __IOM uint32_t LPRXTIMEOUTCLR : 1;        /*!< [5..5] If this bit is set to 1, lp_rx_timeout_clr error recovery
6983                                                      action is taken immediately by DSI TX                                     */
6984             uint32_t            : 26;
6985     } ERRORAUTORCOV_b;
6986   } ;
6987 
6988   union {
6989     __IOM uint32_t MIPIDIRDPIDIFF;              /*!< (@ 0x0000009C) Mipi direction DPI difference                              */
6990 
6991     struct {
6992       __IOM uint32_t MIPIDIR    : 1;            /*!< [0..0] This field provides the direction of MIPI bus;                     */
6993             uint32_t            : 14;
6994       __IOM uint32_t DPIHIGH    : 1;            /*!< [15..15] This field provides information to check DPI line time
6995                                                      is greater or DSI line time is greater                                    */
6996       __IOM uint32_t DPIDIFF    : 16;           /*!< [31..16] This field provides the difference in one line time
6997                                                      between DPI and DSI                                                       */
6998     } MIPIDIRDPIDIFF_b;
6999   } ;
7000 
7001   union {
7002     __IOM uint32_t DATALANEPOLSWAP;             /*!< (@ 0x000000A0) Data lane polarity swap register                           */
7003 
7004     struct {
7005       __IOM uint32_t DATALNPOLSWAP : 4;         /*!< [3..0] Data lane Polarity sw                                              */
7006             uint32_t            : 28;
7007     } DATALANEPOLSWAP_b;
7008   } ;
7009 } DSI_Type;                                     /*!< Size = 164 (0xa4)                                                         */
7010 
7011 
7012 
7013 /* =========================================================================================================================== */
7014 /* ================                                            DSP                                            ================ */
7015 /* =========================================================================================================================== */
7016 
7017 
7018 /**
7019   * @brief DSP Control Interface (DSP)
7020   */
7021 
7022 typedef struct {                                /*!< (@ 0x40100000) DSP Structure                                              */
7023   __IM  uint32_t  RESERVED[16];
7024 
7025   union {
7026     __IOM uint32_t MUTEX0;                      /*!< (@ 0x00000040) MUTEX 0                                                    */
7027 
7028     struct {
7029       __IOM uint32_t MUTEX0     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
7030                                                      owns mutex, 100=DSP1 owns mutex)                                          */
7031             uint32_t            : 29;
7032     } MUTEX0_b;
7033   } ;
7034 
7035   union {
7036     __IOM uint32_t MUTEX1;                      /*!< (@ 0x00000044) MUTEX 1                                                    */
7037 
7038     struct {
7039       __IOM uint32_t MUTEX1     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
7040                                                      owns mutex, 100=DSP1 owns mutex)                                          */
7041             uint32_t            : 29;
7042     } MUTEX1_b;
7043   } ;
7044 
7045   union {
7046     __IOM uint32_t MUTEX2;                      /*!< (@ 0x00000048) MUTEX 2                                                    */
7047 
7048     struct {
7049       __IOM uint32_t MUTEX2     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
7050                                                      owns mutex, 100=DSP1 owns mutex)                                          */
7051             uint32_t            : 29;
7052     } MUTEX2_b;
7053   } ;
7054 
7055   union {
7056     __IOM uint32_t MUTEX3;                      /*!< (@ 0x0000004C) MUTEX 3                                                    */
7057 
7058     struct {
7059       __IOM uint32_t MUTEX3     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
7060                                                      owns mutex, 100=DSP1 owns mutex)                                          */
7061             uint32_t            : 29;
7062     } MUTEX3_b;
7063   } ;
7064 
7065   union {
7066     __IOM uint32_t MUTEX4;                      /*!< (@ 0x00000050) MUTEX 4                                                    */
7067 
7068     struct {
7069       __IOM uint32_t MUTEX4     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
7070                                                      owns mutex, 100=DSP1 owns mutex)                                          */
7071             uint32_t            : 29;
7072     } MUTEX4_b;
7073   } ;
7074 
7075   union {
7076     __IOM uint32_t MUTEX5;                      /*!< (@ 0x00000054) MUTEX 5                                                    */
7077 
7078     struct {
7079       __IOM uint32_t MUTEX5     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
7080                                                      owns mutex, 100=DSP1 owns mutex)                                          */
7081             uint32_t            : 29;
7082     } MUTEX5_b;
7083   } ;
7084 
7085   union {
7086     __IOM uint32_t MUTEX6;                      /*!< (@ 0x00000058) MUTEX 6                                                    */
7087 
7088     struct {
7089       __IOM uint32_t MUTEX6     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
7090                                                      owns mutex, 100=DSP1 owns mutex)                                          */
7091             uint32_t            : 29;
7092     } MUTEX6_b;
7093   } ;
7094 
7095   union {
7096     __IOM uint32_t MUTEX7;                      /*!< (@ 0x0000005C) MUTEX 7                                                    */
7097 
7098     struct {
7099       __IOM uint32_t MUTEX7     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
7100                                                      owns mutex, 100=DSP1 owns mutex)                                          */
7101             uint32_t            : 29;
7102     } MUTEX7_b;
7103   } ;
7104   __IM  uint32_t  RESERVED1[8];
7105 
7106   union {
7107     __IOM uint32_t CPUMBINTSET;                 /*!< (@ 0x00000080) CPU Mailbox Interrupt Set                                  */
7108 
7109     struct {
7110       __IOM uint32_t CPUMBINTSET : 32;          /*!< [31..0] CPU Mailbox interrupt Set. The corresponding data bit
7111                                                      will set the interrupt.                                                   */
7112     } CPUMBINTSET_b;
7113   } ;
7114 
7115   union {
7116     __IOM uint32_t CPUMBINTCLR;                 /*!< (@ 0x00000084) CPU Mailbox Interrupt Clear                                */
7117 
7118     struct {
7119       __IOM uint32_t CPUMBINTCLR : 32;          /*!< [31..0] CPU Mailbox interrupt Clear. The corresponding data
7120                                                      bit will clear the interrupt.                                             */
7121     } CPUMBINTCLR_b;
7122   } ;
7123 
7124   union {
7125     __IOM uint32_t CPUMBINTSTAT;                /*!< (@ 0x00000088) CPU Mailbox Interrupt Status                               */
7126 
7127     struct {
7128       __IOM uint32_t CPUMBINTSTAT : 32;         /*!< [31..0] CPU CPU Mailbox interrupt status                                  */
7129     } CPUMBINTSTAT_b;
7130   } ;
7131 
7132   union {
7133     __IOM uint32_t CPUCPUMBDATA;                /*!< (@ 0x0000008C) CPU CPU Mailbox Data                                       */
7134 
7135     struct {
7136       __IOM uint32_t CPUCPUMBDATA : 32;         /*!< [31..0] CPU CPU Mailbox data                                              */
7137     } CPUCPUMBDATA_b;
7138   } ;
7139 
7140   union {
7141     __IOM uint32_t DSP0CPUMBDATA;               /*!< (@ 0x00000090) DSP0 to CPU Mailbox Data                                   */
7142 
7143     struct {
7144       __IOM uint32_t DSP0CPUMBDATA : 32;        /*!< [31..0] DSP0 to CPU Mailbox data                                          */
7145     } DSP0CPUMBDATA_b;
7146   } ;
7147 
7148   union {
7149     __IOM uint32_t DSP1CPUMBDATA;               /*!< (@ 0x00000094) DSP1 to CPU Mailbox Data                                   */
7150 
7151     struct {
7152       __IOM uint32_t DSP1CPUMBDATA : 32;        /*!< [31..0] DSP1 to CPU Mailbox data                                          */
7153     } DSP1CPUMBDATA_b;
7154   } ;
7155   __IM  uint32_t  RESERVED2[2];
7156 
7157   union {
7158     __IOM uint32_t DSP0MBINTSET;                /*!< (@ 0x000000A0) DSP0 Mailbox Interrupt Set                                 */
7159 
7160     struct {
7161       __IOM uint32_t DSP0MBINTSET : 32;         /*!< [31..0] DSP0 Mailbox interrupt Set. The corresponding data bit
7162                                                      will set the interrupt.                                                   */
7163     } DSP0MBINTSET_b;
7164   } ;
7165 
7166   union {
7167     __IOM uint32_t DSP0MBINTCLR;                /*!< (@ 0x000000A4) DSP0 Mailbox Interrupt Clear                               */
7168 
7169     struct {
7170       __IOM uint32_t DSP0MBINTCLR : 32;         /*!< [31..0] DSP0 Mailbox interrupt Clear. The corresponding data
7171                                                      bit will clear the interrupt.                                             */
7172     } DSP0MBINTCLR_b;
7173   } ;
7174 
7175   union {
7176     __IOM uint32_t DSP0MBINTSTAT;               /*!< (@ 0x000000A8) DSP 0 Mailbox Interrupt Status                             */
7177 
7178     struct {
7179       __IOM uint32_t DSP0MBINTSTAT : 32;        /*!< [31..0] DSP 0 CPU Mailbox interrupt                                       */
7180     } DSP0MBINTSTAT_b;
7181   } ;
7182 
7183   union {
7184     __IOM uint32_t CPUDSP0MBDATA;               /*!< (@ 0x000000AC) CPU to DSP 0 Mailbox Data                                  */
7185 
7186     struct {
7187       __IOM uint32_t CPUDSP0MBDATA : 32;        /*!< [31..0] DSP 0 CPU Mailbox data                                            */
7188     } CPUDSP0MBDATA_b;
7189   } ;
7190 
7191   union {
7192     __IOM uint32_t DSP0DSP0MBDATA;              /*!< (@ 0x000000B0) DSP0 to DSP 0 Mailbox Data                                 */
7193 
7194     struct {
7195       __IOM uint32_t DSP0DSP0MBDATA : 32;       /*!< [31..0] DSP0 to DSP 0 Mailbox data                                        */
7196     } DSP0DSP0MBDATA_b;
7197   } ;
7198 
7199   union {
7200     __IOM uint32_t DSP1DSP0MBDATA;              /*!< (@ 0x000000B4) DSP1 to DSP 0 Mailbox Data                                 */
7201 
7202     struct {
7203       __IOM uint32_t DSP1DSP0MBDATA : 32;       /*!< [31..0] DSP1 to DSP 0 Mailbox data                                        */
7204     } DSP1DSP0MBDATA_b;
7205   } ;
7206   __IM  uint32_t  RESERVED3[2];
7207 
7208   union {
7209     __IOM uint32_t DSP1MBINTSET;                /*!< (@ 0x000000C0) DSP1 Mailbox Interrupt Set                                 */
7210 
7211     struct {
7212       __IOM uint32_t DSP1MBINTSET : 32;         /*!< [31..0] DSP1 Mailbox interrupt Set. The corresponding data bit
7213                                                      will set the interrupt.                                                   */
7214     } DSP1MBINTSET_b;
7215   } ;
7216 
7217   union {
7218     __IOM uint32_t DSP1MBINTCLR;                /*!< (@ 0x000000C4) DSP1 Mailbox Interrupt Clear                               */
7219 
7220     struct {
7221       __IOM uint32_t DSP1MBINTCLR : 32;         /*!< [31..0] DSP1 Mailbox interrupt Clear. The corresponding data
7222                                                      bit will clear the interrupt.                                             */
7223     } DSP1MBINTCLR_b;
7224   } ;
7225 
7226   union {
7227     __IOM uint32_t DSP1MBINTSTAT;               /*!< (@ 0x000000C8) DSP 1 Mailbox Interrupt Status                             */
7228 
7229     struct {
7230       __IOM uint32_t DSP1MBINTSTAT : 32;        /*!< [31..0] DSP 1 CPU Mailbox interrupt                                       */
7231     } DSP1MBINTSTAT_b;
7232   } ;
7233 
7234   union {
7235     __IOM uint32_t CPUDSP1MBDATA;               /*!< (@ 0x000000CC) CPU to DSP 1 Mailbox Data                                  */
7236 
7237     struct {
7238       __IOM uint32_t CPUDSP1MBDATA : 32;        /*!< [31..0] DSP 1 CPU Mailbox data                                            */
7239     } CPUDSP1MBDATA_b;
7240   } ;
7241 
7242   union {
7243     __IOM uint32_t DSP0DSP1MBDATA;              /*!< (@ 0x000000D0) DSP0 to DSP 1 Mailbox Data                                 */
7244 
7245     struct {
7246       __IOM uint32_t DSP0DSP1MBDATA : 32;       /*!< [31..0] DSP0 to DSP 1 Mailbox data                                        */
7247     } DSP0DSP1MBDATA_b;
7248   } ;
7249 
7250   union {
7251     __IOM uint32_t DSP1DSP1MBDATA;              /*!< (@ 0x000000D4) DSP1 to DSP 1 Mailbox Data                                 */
7252 
7253     struct {
7254       __IOM uint32_t DSP1DSP1MBDATA : 32;       /*!< [31..0] DSP1 to DSP 1 Mailbox data                                        */
7255     } DSP1DSP1MBDATA_b;
7256   } ;
7257   __IM  uint32_t  RESERVED4[10];
7258 
7259   union {
7260     __IOM uint32_t DSP0CONTROL;                 /*!< (@ 0x00000100) DSP 0 control settings                                     */
7261 
7262     struct {
7263       __IOM uint32_t DSP0STATVECSEL : 1;        /*!< [0..0] DSP 0 StatVectorSel                                                */
7264       __IOM uint32_t DSP0BRESET : 1;            /*!< [1..1] DSP0 BReset. This is the reset used for Xtensa core.
7265                                                      S/w must clear this reset to use Dsp.                                     */
7266       __IOM uint32_t DSP0DRESET : 1;            /*!< [2..2] DSP0 DReset. This is the reset used for debug functionality
7267                                                      like OCD/TRAX etc.                                                        */
7268       __IOM uint32_t DSP0RUNSTALL : 1;          /*!< [3..3] DSP 0 RunStall. When asserted, DSP 0 will stall until
7269                                                      bit is cleared.                                                           */
7270       __IOM uint32_t DSP0IDMATRIG : 2;          /*!< [5..4] DSP 0 IDMA Trigger Control                                         */
7271             uint32_t            : 2;
7272       __IOM uint32_t DSP0IDMAXTRIGSRC : 23;     /*!< [30..8] DSP 0 IDMA Cross Trigger Source. All enabled sources
7273                                                      are ANDed to generate a trigger enable.
7274                                                      Bit30-12:IRQ18-0 Bit11: IDMATRIGPULSE, Bit10: DSP Timer1,
7275                                                      Bit9: DSP Timer0, Bit8: alternate DSP iDMA trigger out                    */
7276             uint32_t            : 1;
7277     } DSP0CONTROL_b;
7278   } ;
7279 
7280   union {
7281     __IOM uint32_t DSP0RESETVEC;                /*!< (@ 0x00000104) DSP 0 Reset Vector                                         */
7282 
7283     struct {
7284       __IOM uint32_t DSP0RESETVEC : 32;         /*!< [31..0] DSP 0 Reset Vector Address.                                       */
7285     } DSP0RESETVEC_b;
7286   } ;
7287 
7288   union {
7289     __IOM uint32_t DSP0IRQMASK;                 /*!< (@ 0x00000108) DSP 0 IRQ Mask                                             */
7290 
7291     struct {
7292       __IOM uint32_t DSP0IRQMASK : 23;          /*!< [22..0] DSP 0 IRQ Mask                                                    */
7293             uint32_t            : 9;
7294     } DSP0IRQMASK_b;
7295   } ;
7296 
7297   union {
7298     __IOM uint32_t DSP0WAKEMASK;                /*!< (@ 0x0000010C) DSP 0 IRQ Wake Mask                                        */
7299 
7300     struct {
7301       __IOM uint32_t DSP0WAKEMASK : 23;         /*!< [22..0] DSP 0 IRQ Wake Mask                                               */
7302             uint32_t            : 9;
7303     } DSP0WAKEMASK_b;
7304   } ;
7305 
7306   union {
7307     __IOM uint32_t DSP0RAWIRQSTAT31to0;         /*!< (@ 0x00000110) DSP 0 Raw IRQ31-0 Status                                   */
7308 
7309     struct {
7310       __IOM uint32_t DSP0RAWIRQSTAT31to0 : 32;  /*!< [31..0] DSP 0 Raw IRQ31-0 Status                                          */
7311     } DSP0RAWIRQSTAT31to0_b;
7312   } ;
7313 
7314   union {
7315     __IOM uint32_t DSP0RAWIRQSTAT63to32;        /*!< (@ 0x00000114) DSP 0 Raw IRQ63-32 Status                                  */
7316 
7317     struct {
7318       __IOM uint32_t DSP0RAWIRQSTAT63to32 : 32; /*!< [31..0] DSP 0 Raw IRQ63-32 Status                                         */
7319     } DSP0RAWIRQSTAT63to32_b;
7320   } ;
7321 
7322   union {
7323     __IOM uint32_t DSP0RAWIRQSTAT95to64;        /*!< (@ 0x00000118) DSP 0 Raw IRQ95-64 Status                                  */
7324 
7325     struct {
7326       __IOM uint32_t DSP0RAWIRQSTAT95to64 : 32; /*!< [31..0] DSP 0 Raw IRQ95-64 Status                                         */
7327     } DSP0RAWIRQSTAT95to64_b;
7328   } ;
7329   __IM  uint32_t  RESERVED5;
7330 
7331   union {
7332     __IOM uint32_t DSP0L2LVLINT;                /*!< (@ 0x00000120) DSP 0 L2 Level Interrupt Mux                               */
7333 
7334     struct {
7335       __IOM uint32_t DSP0L2LVLINT : 19;         /*!< [18..0] DSP 0 L2 Level Interrupt Mux                                      */
7336             uint32_t            : 13;
7337     } DSP0L2LVLINT_b;
7338   } ;
7339 
7340   union {
7341     __IOM uint32_t DSP0L3LVLINT;                /*!< (@ 0x00000124) DSP 0 L3 Level Interrupt Mux                               */
7342 
7343     struct {
7344       __IOM uint32_t DSP0L3LVLINT : 19;         /*!< [18..0] DSP 0 L3 Level Interrupt Mux                                      */
7345             uint32_t            : 13;
7346     } DSP0L3LVLINT_b;
7347   } ;
7348 
7349   union {
7350     __IOM uint32_t DSP0L4LVLINT;                /*!< (@ 0x00000128) DSP 0 L4 Level Interrupt Mux                               */
7351 
7352     struct {
7353       __IOM uint32_t DSP0L4LVLINT : 19;         /*!< [18..0] DSP 0 L4 Level Interrupt Mux                                      */
7354             uint32_t            : 13;
7355     } DSP0L4LVLINT_b;
7356   } ;
7357 
7358   union {
7359     __IOM uint32_t DSP0L5LVLINT;                /*!< (@ 0x0000012C) DSP 0 L5 Level Interrupt Mux                               */
7360 
7361     struct {
7362       __IOM uint32_t DSP0L5LVLINT : 19;         /*!< [18..0] DSP 0 L5 Level Interrupt Mux                                      */
7363             uint32_t            : 13;
7364     } DSP0L5LVLINT_b;
7365   } ;
7366 
7367   union {
7368     __IOM uint32_t DSP0IDMATRIGCTL;             /*!< (@ 0x00000130) DSP 0 IDMA Trigger Control and Status                      */
7369 
7370     struct {
7371       __IOM uint32_t DSP0IDMATRIGSTAT : 1;      /*!< [0..0] DSP 0 iDMA Trigger Status                                          */
7372             uint32_t            : 3;
7373       __IOM uint32_t DSP0IDMATRIGPULSE : 1;     /*!< [4..4] DSP 0 iDMA Trigger Pulse - When written a '1', this will
7374                                                      cause a single step enable (valid only when IDMATRIG is
7375                                                      set to SSTEP)                                                             */
7376             uint32_t            : 27;
7377     } DSP0IDMATRIGCTL_b;
7378   } ;
7379   __IM  uint32_t  RESERVED6[3];
7380 
7381   union {
7382     __IOM uint32_t DSP0INTORMASK31TO0A;         /*!< (@ 0x00000140) DSP0 Interrupt OR Mask A for IRQ31-0                       */
7383 
7384     struct {
7385       __IOM uint32_t DSP0INTMCUIOORMASKA : 32;  /*!< [31..0] DSP0 MCU IO Interrupt OR Mask A                                   */
7386     } DSP0INTORMASK31TO0A_b;
7387   } ;
7388 
7389   union {
7390     __IOM uint32_t DSP0INTORMASK63TO32A;        /*!< (@ 0x00000144) DSP0 Interrupt OR Mask A for IRQ63-32                      */
7391 
7392     struct {
7393       __IOM uint32_t DSP0TMRORMASKA : 10;       /*!< [9..0] DSP0 Timer Interrupt OR Mask A                                     */
7394             uint32_t            : 2;
7395       __IOM uint32_t DSP0I2SORMASKA : 4;        /*!< [15..12] DSP0 I2S Interrupt OR Mask A                                     */
7396       __IOM uint32_t DSP0PDMORMASKA : 4;        /*!< [19..16] DSP0 PDM Interrupt OR Mask A                                     */
7397             uint32_t            : 4;
7398       __IOM uint32_t DSP0GPIOORMASKA : 6;       /*!< [29..24] DSP0 GPIO Interrupt OR Mask A                                    */
7399             uint32_t            : 2;
7400     } DSP0INTORMASK63TO32A_b;
7401   } ;
7402 
7403   union {
7404     __IOM uint32_t DSP0INTORMASK95TO64A;        /*!< (@ 0x00000148) DSP0 Interrupt OR Mask A for IRQ95-64                      */
7405 
7406     struct {
7407       __IOM uint32_t DSP0MBINTORMASKA : 32;     /*!< [31..0] DSP0 Mailbox Interrupt OR Mask A                                  */
7408     } DSP0INTORMASK95TO64A_b;
7409   } ;
7410   __IM  uint32_t  RESERVED7;
7411 
7412   union {
7413     __IOM uint32_t DSP0INTORMASK31to0B;         /*!< (@ 0x00000150) DSP0 Interrupt OR Mask B for IRQ31-0                       */
7414 
7415     struct {
7416       __IOM uint32_t DSP0INTMCUIOORMASKB : 32;  /*!< [31..0] DSP0 MCU IO Interrupt OR Mask B                                   */
7417     } DSP0INTORMASK31to0B_b;
7418   } ;
7419 
7420   union {
7421     __IOM uint32_t DSP0INTORMASK63TO32B;        /*!< (@ 0x00000154) DSP0 Interrupt OR Mask A for IRQ63-32                      */
7422 
7423     struct {
7424       __IOM uint32_t DSP0TMRORMASKB : 10;       /*!< [9..0] DSP0 Timer Interrupt OR Mask B                                     */
7425             uint32_t            : 2;
7426       __IOM uint32_t DSP0I2SORMASKB : 4;        /*!< [15..12] DSP0 I2S Interrupt OR Mask B                                     */
7427       __IOM uint32_t DSP0PDMORMASKB : 4;        /*!< [19..16] DSP0 PDM Interrupt OR Mask B                                     */
7428             uint32_t            : 4;
7429       __IOM uint32_t DSP0GPIOORMASKB : 6;       /*!< [29..24] DSP0 GPIO Interrupt OR Mask B                                    */
7430             uint32_t            : 2;
7431     } DSP0INTORMASK63TO32B_b;
7432   } ;
7433 
7434   union {
7435     __IOM uint32_t DSP0INTORMASK95TO64B;        /*!< (@ 0x00000158) DSP0 Interrupt OR Mask B for IRQ95-64                      */
7436 
7437     struct {
7438       __IOM uint32_t DSP0MBINTORMASKB : 32;     /*!< [31..0] DSP0 Mailbox Interrupt OR Mask B                                  */
7439     } DSP0INTORMASK95TO64B_b;
7440   } ;
7441   __IM  uint32_t  RESERVED8;
7442 
7443   union {
7444     __IOM uint32_t DSP0INTENIRQ31TO0;           /*!< (@ 0x00000160) DSP0 INT Enable for IRQ31-0                                */
7445 
7446     struct {
7447       __IOM uint32_t DSP0INTENIRQ31TO0 : 32;    /*!< [31..0] DSP0 INT Enable for IRQ31-0                                       */
7448     } DSP0INTENIRQ31TO0_b;
7449   } ;
7450 
7451   union {
7452     __IOM uint32_t DSP0INTENIRQ63TO32;          /*!< (@ 0x00000164) DSP0 INT Enable for IRQ63-32                               */
7453 
7454     struct {
7455       __IOM uint32_t DSP0INTENIRQ63TO32 : 32;   /*!< [31..0] DSP0 INT Enable for IRQ63-32                                      */
7456     } DSP0INTENIRQ63TO32_b;
7457   } ;
7458 
7459   union {
7460     __IOM uint32_t DSP0INTENIRQ95TO64;          /*!< (@ 0x00000168) DSP0 INT Enable for IRQ95-64                               */
7461 
7462     struct {
7463       __IOM uint32_t DSP0INTENIRQ95TO64 : 32;   /*!< [31..0] DSP0 INT Enable for IRQ95-64                                      */
7464     } DSP0INTENIRQ95TO64_b;
7465   } ;
7466   __IM  uint32_t  RESERVED9[37];
7467 
7468   union {
7469     __IOM uint32_t DSP1CONTROL;                 /*!< (@ 0x00000200) DSP 1 control settings                                     */
7470 
7471     struct {
7472       __IOM uint32_t DSP1STATVECSEL : 1;        /*!< [0..0] DSP 1 StatVectorSel                                                */
7473       __IOM uint32_t DSP1BRESET : 1;            /*!< [1..1] DSP1 BReset. This is the reset used for Xtensa core.
7474                                                      S/w must clear this reset to use Dsp.                                     */
7475       __IOM uint32_t DSP1DRESET : 1;            /*!< [2..2] DSP1 DReset. This is the reset used for debug functionality
7476                                                      like OCD/TRAX etc.                                                        */
7477       __IOM uint32_t DSP1RUNSTALL : 1;          /*!< [3..3] DSP 1 RunStall. When asserted, DSP 1 will stall until
7478                                                      bit is cleared.                                                           */
7479       __IOM uint32_t DSP1IDMATRIG : 2;          /*!< [5..4] DSP 1 IDMA Trigger Control                                         */
7480             uint32_t            : 2;
7481       __IOM uint32_t DSP1IDMAXTRIGSRC : 23;     /*!< [30..8] DSP 1 IDMA Cross Trigger Source. All enabled sources
7482                                                      are ANDed to generate a trigger enable.
7483                                                      Bit30-12:IRQ18-0 Bit11: IDMATRIGPULSE, Bit10: DSP Timer1,
7484                                                      Bit9: DSP Timer0, Bit8: alternate DSP iDMA trigger out                    */
7485             uint32_t            : 1;
7486     } DSP1CONTROL_b;
7487   } ;
7488 
7489   union {
7490     __IOM uint32_t DSP1RESETVEC;                /*!< (@ 0x00000204) DSP 1 Reset Vector                                         */
7491 
7492     struct {
7493       __IOM uint32_t DSP1RESETVEC : 32;         /*!< [31..0] DSP 1 Reset Vector Address.                                       */
7494     } DSP1RESETVEC_b;
7495   } ;
7496 
7497   union {
7498     __IOM uint32_t DSP1IRQMASK;                 /*!< (@ 0x00000208) DSP 1 IRQ Mask                                             */
7499 
7500     struct {
7501       __IOM uint32_t DSP1IRQMASK : 23;          /*!< [22..0] DSP 1 IRQ Mask                                                    */
7502             uint32_t            : 9;
7503     } DSP1IRQMASK_b;
7504   } ;
7505 
7506   union {
7507     __IOM uint32_t DSP1WAKEMASK;                /*!< (@ 0x0000020C) DSP 1 IRQ Wake Mask                                        */
7508 
7509     struct {
7510       __IOM uint32_t DSP1WAKEMASK : 23;         /*!< [22..0] DSP 1 IRQ Wake Mask                                               */
7511             uint32_t            : 9;
7512     } DSP1WAKEMASK_b;
7513   } ;
7514 
7515   union {
7516     __IOM uint32_t DSP1RAWIRQSTAT31to0;         /*!< (@ 0x00000210) DSP 1 Raw IRQ31-0 Status                                   */
7517 
7518     struct {
7519       __IOM uint32_t DSP1RAWIRQSTAT31to0 : 32;  /*!< [31..0] DSP 1 Raw IRQ31-0 Status                                          */
7520     } DSP1RAWIRQSTAT31to0_b;
7521   } ;
7522 
7523   union {
7524     __IOM uint32_t DSP1RAWIRQSTAT63to32;        /*!< (@ 0x00000214) DSP 1 Raw IRQ63-32 Status                                  */
7525 
7526     struct {
7527       __IOM uint32_t DSP1RAWIRQSTAT63to32 : 32; /*!< [31..0] DSP 1 Raw IRQ63-32 Status                                         */
7528     } DSP1RAWIRQSTAT63to32_b;
7529   } ;
7530 
7531   union {
7532     __IOM uint32_t DSP1RAWIRQSTAT95to64;        /*!< (@ 0x00000218) DSP 1 Raw IRQ95-64 Status                                  */
7533 
7534     struct {
7535       __IOM uint32_t DSP1RAWIRQSTAT95to64 : 32; /*!< [31..0] DSP 1 Raw IRQ95-64 Status                                         */
7536     } DSP1RAWIRQSTAT95to64_b;
7537   } ;
7538   __IM  uint32_t  RESERVED10;
7539 
7540   union {
7541     __IOM uint32_t DSP1L2LVLINT;                /*!< (@ 0x00000220) DSP 1 L2 Level Interrupt Mux                               */
7542 
7543     struct {
7544       __IOM uint32_t DSP1L2LVLINT : 19;         /*!< [18..0] DSP 1 L2 Level Interrupt Mux                                      */
7545             uint32_t            : 13;
7546     } DSP1L2LVLINT_b;
7547   } ;
7548 
7549   union {
7550     __IOM uint32_t DSP1L3LVLINT;                /*!< (@ 0x00000224) DSP 1 L3 Level Interrupt Mux                               */
7551 
7552     struct {
7553       __IOM uint32_t DSP1L3LVLINT : 19;         /*!< [18..0] DSP 1 L3 Level Interrupt Mux                                      */
7554             uint32_t            : 13;
7555     } DSP1L3LVLINT_b;
7556   } ;
7557 
7558   union {
7559     __IOM uint32_t DSP1L4LVLINT;                /*!< (@ 0x00000228) DSP 1 L4 Level Interrupt Mux                               */
7560 
7561     struct {
7562       __IOM uint32_t DSP1L4LVLINT : 19;         /*!< [18..0] DSP 1 L4 Level Interrupt Mux                                      */
7563             uint32_t            : 13;
7564     } DSP1L4LVLINT_b;
7565   } ;
7566 
7567   union {
7568     __IOM uint32_t DSP1L5LVLINT;                /*!< (@ 0x0000022C) DSP 1 L5 Level Interrupt Mux                               */
7569 
7570     struct {
7571       __IOM uint32_t DSP1L5LVLINT : 19;         /*!< [18..0] DSP 1 L5 Level Interrupt Mux                                      */
7572             uint32_t            : 13;
7573     } DSP1L5LVLINT_b;
7574   } ;
7575 
7576   union {
7577     __IOM uint32_t DSP1IDMATRIGCTL;             /*!< (@ 0x00000230) DSP 1 IDMA Trigger Control and Status                      */
7578 
7579     struct {
7580       __IOM uint32_t DSP1IDMATRIGSTAT : 1;      /*!< [0..0] DSP 1 iDMA Trigger Status                                          */
7581             uint32_t            : 3;
7582       __IOM uint32_t DSP1IDMATRIGPULSE : 1;     /*!< [4..4] DSP 1 iDMA Trigger Pulse - When written a '1', this will
7583                                                      cause a single step enable (valid only when IDMATRIG is
7584                                                      set to SSTEP)                                                             */
7585             uint32_t            : 27;
7586     } DSP1IDMATRIGCTL_b;
7587   } ;
7588   __IM  uint32_t  RESERVED11[3];
7589 
7590   union {
7591     __IOM uint32_t DSP1INTORMASK31TO0A;         /*!< (@ 0x00000240) DSP1 Interrupt OR Mask A for IRQ31-0                       */
7592 
7593     struct {
7594       __IOM uint32_t DSP1INTMCUIOORMASKA : 32;  /*!< [31..0] DSP1 MCU IO Interrupt OR Mask A                                   */
7595     } DSP1INTORMASK31TO0A_b;
7596   } ;
7597 
7598   union {
7599     __IOM uint32_t DSP1INTORMASK63TO32A;        /*!< (@ 0x00000244) DSP1 Interrupt OR Mask A for IRQ63-32                      */
7600 
7601     struct {
7602       __IOM uint32_t DSP1TMRORMASKA : 10;       /*!< [9..0] DSP1 Timer Interrupt OR Mask A                                     */
7603             uint32_t            : 2;
7604       __IOM uint32_t DSP1I2SORMASKA : 4;        /*!< [15..12] DSP1 I2S Interrupt OR Mask A                                     */
7605       __IOM uint32_t DSP1PDMORMASKA : 4;        /*!< [19..16] DSP1 PDM Interrupt OR Mask A                                     */
7606             uint32_t            : 4;
7607       __IOM uint32_t DSP1GPIOORMASKA : 6;       /*!< [29..24] DSP1 GPIO Interrupt OR Mask A                                    */
7608             uint32_t            : 2;
7609     } DSP1INTORMASK63TO32A_b;
7610   } ;
7611 
7612   union {
7613     __IOM uint32_t DSP1INTORMASK95TO64A;        /*!< (@ 0x00000248) DSP1 Interrupt OR Mask A for IRQ95-64                      */
7614 
7615     struct {
7616       __IOM uint32_t DSP1MBINTORMASKA : 32;     /*!< [31..0] DSP1 Mailbox Interrupt OR Mask A                                  */
7617     } DSP1INTORMASK95TO64A_b;
7618   } ;
7619   __IM  uint32_t  RESERVED12;
7620 
7621   union {
7622     __IOM uint32_t DSP1INTORMASK31to0B;         /*!< (@ 0x00000250) DSP1 Interrupt OR Mask B for IRQ31-0                       */
7623 
7624     struct {
7625       __IOM uint32_t DSP1INTMCUIOORMASKB : 32;  /*!< [31..0] DSP1 MCU IO Interrupt OR Mask B                                   */
7626     } DSP1INTORMASK31to0B_b;
7627   } ;
7628 
7629   union {
7630     __IOM uint32_t DSP1INTORMASK63TO32B;        /*!< (@ 0x00000254) DSP1 Interrupt OR Mask A for IRQ63-32                      */
7631 
7632     struct {
7633       __IOM uint32_t DSP1TMRORMASKB : 10;       /*!< [9..0] DSP1 Timer Interrupt OR Mask B                                     */
7634             uint32_t            : 2;
7635       __IOM uint32_t DSP1I2SORMASKB : 4;        /*!< [15..12] DSP1 I2S Interrupt OR Mask B                                     */
7636       __IOM uint32_t DSP1PDMORMASKB : 4;        /*!< [19..16] DSP1 PDM Interrupt OR Mask B                                     */
7637             uint32_t            : 4;
7638       __IOM uint32_t DSP1GPIOORMASKB : 6;       /*!< [29..24] DSP1 GPIO Interrupt OR Mask B                                    */
7639             uint32_t            : 2;
7640     } DSP1INTORMASK63TO32B_b;
7641   } ;
7642 
7643   union {
7644     __IOM uint32_t DSP1INTORMASK95TO64B;        /*!< (@ 0x00000258) DSP1 Interrupt OR Mask B for IRQ95-64                      */
7645 
7646     struct {
7647       __IOM uint32_t DSP1MBINTORMASKB : 32;     /*!< [31..0] DSP1 Mailbox Interrupt OR Mask B                                  */
7648     } DSP1INTORMASK95TO64B_b;
7649   } ;
7650   __IM  uint32_t  RESERVED13;
7651 
7652   union {
7653     __IOM uint32_t DSP1INTENIRQ31TO0;           /*!< (@ 0x00000260) DSP1 INT Enable for IRQ31-0                                */
7654 
7655     struct {
7656       __IOM uint32_t DSP1INTENIRQ31TO0 : 32;    /*!< [31..0] DSP1 INT Enable for IRQ31-0                                       */
7657     } DSP1INTENIRQ31TO0_b;
7658   } ;
7659 
7660   union {
7661     __IOM uint32_t DSP1INTENIRQ63TO32;          /*!< (@ 0x00000264) DSP1 INT Enable for IRQ63-32                               */
7662 
7663     struct {
7664       __IOM uint32_t DSP1INTENIRQ63TO32 : 32;   /*!< [31..0] DSP1 INT Enable for IRQ63-32                                      */
7665     } DSP1INTENIRQ63TO32_b;
7666   } ;
7667 
7668   union {
7669     __IOM uint32_t DSP1INTENIRQ95TO64;          /*!< (@ 0x00000268) DSP1 INT Enable for IRQ95-64                               */
7670 
7671     struct {
7672       __IOM uint32_t DSP1INTENIRQ95TO64 : 32;   /*!< [31..0] DSP1 INT Enable for IRQ95-64                                      */
7673     } DSP1INTENIRQ95TO64_b;
7674   } ;
7675 } DSP_Type;                                     /*!< Size = 620 (0x26c)                                                        */
7676 
7677 
7678 
7679 /* =========================================================================================================================== */
7680 /* ================                                           FPIO                                            ================ */
7681 /* =========================================================================================================================== */
7682 
7683 
7684 /**
7685   * @brief Fast PIO access (FPIO)
7686   */
7687 
7688 typedef struct {                                /*!< (@ 0x48001000) FPIO Structure                                             */
7689 
7690   union {
7691     __IOM uint32_t RD0;                         /*!< (@ 0x00000000) GPIO Input 0 (31-0)                                        */
7692 
7693     struct {
7694       __IOM uint32_t RD0        : 32;           /*!< [31..0] GPIO31-0 Reads pin state - read only. Returns the pad
7695                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
7696                                                      is active and RDZERO is inactive.                                         */
7697     } RD0_b;
7698   } ;
7699 
7700   union {
7701     __IOM uint32_t RD1;                         /*!< (@ 0x00000004) GPIO Input 1 (63-32)                                       */
7702 
7703     struct {
7704       __IOM uint32_t RD1        : 32;           /*!< [31..0] GPIO63-32 Reads pin state - read only. Returns the pad
7705                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
7706                                                      is active and RDZERO is inactive.                                         */
7707     } RD1_b;
7708   } ;
7709 
7710   union {
7711     __IOM uint32_t RD2;                         /*!< (@ 0x00000008) GPIO Input 2 (95-64)                                       */
7712 
7713     struct {
7714       __IOM uint32_t RD2        : 32;           /*!< [31..0] GPIO95-64 Reads pin state - read only. Returns the pad
7715                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
7716                                                      is active and RDZERO is inactive.                                         */
7717     } RD2_b;
7718   } ;
7719 
7720   union {
7721     __IOM uint32_t RD3;                         /*!< (@ 0x0000000C) GPIO Input 3 (127-96)                                      */
7722 
7723     struct {
7724       __IOM uint32_t RD3        : 32;           /*!< [31..0] GPIO127-96 Reads pin state - read only. Returns the
7725                                                      pad pin state for pins 0-31 if the PINCFG's input enable
7726                                                      (INPEN) is active and RDZERO is inactive.                                 */
7727     } RD3_b;
7728   } ;
7729 
7730   union {
7731     __IOM uint32_t WT0;                         /*!< (@ 0x00000010) GPIO Output 0 (31-0)                                       */
7732 
7733     struct {
7734       __IOM uint32_t WT0        : 32;           /*!< [31..0] GPIO31-0 Reads or writes pin state. Writes of 1 bits
7735                                                      set output pad signal if the GPIO is enabled for output.
7736                                                      Reads return status, including sets/clears through the
7737                                                      WTS and WTC registers.                                                    */
7738     } WT0_b;
7739   } ;
7740 
7741   union {
7742     __IOM uint32_t WT1;                         /*!< (@ 0x00000014) GPIO Output 1 (63-32)                                      */
7743 
7744     struct {
7745       __IOM uint32_t WT1        : 32;           /*!< [31..0] GPIO63-32 Reads or writes pin state. Writes of 1 bits
7746                                                      set output pad signal if the GPIO is enabled for output.
7747                                                      Reads return status, including sets/clears through the
7748                                                      WTS and WTC registers.                                                    */
7749     } WT1_b;
7750   } ;
7751 
7752   union {
7753     __IOM uint32_t WT2;                         /*!< (@ 0x00000018) GPIO Output 2 (95-64)                                      */
7754 
7755     struct {
7756       __IOM uint32_t WT2        : 32;           /*!< [31..0] GPIO95-64 Reads or writes pin state. Writes of 1 bits
7757                                                      set output pad signal if the GPIO is enabled for output.
7758                                                      Reads return status, including sets/clears through the
7759                                                      WTS and WTC registers.                                                    */
7760     } WT2_b;
7761   } ;
7762 
7763   union {
7764     __IOM uint32_t WT3;                         /*!< (@ 0x0000001C) GPIO Output 3 (127-96)                                     */
7765 
7766     struct {
7767       __IOM uint32_t WT3        : 32;           /*!< [31..0] GPIO127-96 Reads or writes pin state. Writes of 1 bits
7768                                                      set output pad signal if the GPIO is enabled for output.
7769                                                      Reads return status, including sets/clears through the
7770                                                      WTS and WTC registers.                                                    */
7771     } WT3_b;
7772   } ;
7773 
7774   union {
7775     __IOM uint32_t WTS0;                        /*!< (@ 0x00000020) GPIO Output Set 0 (31-0)                                   */
7776 
7777     struct {
7778       __IOM uint32_t WTS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin state. Writing a 1 to any bit sets
7779                                                      the corresponding bit in the WT register if the GPIO is
7780                                                      enabled for output. Writing a value of 0 has no effect
7781                                                      on the corresponding bit in the WT register. Status reads
7782                                                      should be made via the WT Register.                                       */
7783     } WTS0_b;
7784   } ;
7785 
7786   union {
7787     __IOM uint32_t WTS1;                        /*!< (@ 0x00000024) GPIO Output Set 1 (63-32)                                  */
7788 
7789     struct {
7790       __IOM uint32_t WTS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin state. Writing a 1 to any bit sets
7791                                                      the corresponding bit in the WT register if the GPIO is
7792                                                      enabled for output. Writing a value of 0 has no effect
7793                                                      on the corresponding bit in the WT register. Status reads
7794                                                      should be made via the WT Register.                                       */
7795     } WTS1_b;
7796   } ;
7797 
7798   union {
7799     __IOM uint32_t WTS2;                        /*!< (@ 0x00000028) GPIO Output Set 2 (95-64)                                  */
7800 
7801     struct {
7802       __IOM uint32_t WTS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin state. Writing a 1 to any bit sets
7803                                                      the corresponding bit in the WT register if the GPIO is
7804                                                      enabled for output. Writing a value of 0 has no effect
7805                                                      on the corresponding bit in the WT register. Status reads
7806                                                      should be made via the WT Register.                                       */
7807     } WTS2_b;
7808   } ;
7809 
7810   union {
7811     __IOM uint32_t WTS3;                        /*!< (@ 0x0000002C) GPIO Output Set 3 (127-96)                                 */
7812 
7813     struct {
7814       __IOM uint32_t WTS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin state. Writing a 1 to any bit sets
7815                                                      the corresponding bit in the WT register if the GPIO is
7816                                                      enabled for output. Writing a value of 0 has no effect
7817                                                      on the corresponding bit in the WT register. Status reads
7818                                                      should be made via the WT Register.                                       */
7819     } WTS3_b;
7820   } ;
7821 
7822   union {
7823     __IOM uint32_t WTC0;                        /*!< (@ 0x00000030) GPIO Output Clear 0 (31-0)                                 */
7824 
7825     struct {
7826       __IOM uint32_t WTC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin state. Writing a 1 to any bit clears
7827                                                      the corresponding bit in the WT register if the GPIO is
7828                                                      enabled for output. Writing a value of 0 has no effect
7829                                                      on the corresponding bit in the WT register. Status reads
7830                                                      should be made via the WT register.                                       */
7831     } WTC0_b;
7832   } ;
7833 
7834   union {
7835     __IOM uint32_t WTC1;                        /*!< (@ 0x00000034) GPIO Output Clear 1 (63-32)                                */
7836 
7837     struct {
7838       __IOM uint32_t WTC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin state. Writing a 1 to any bit clears
7839                                                      the corresponding bit in the WT register if the GPIO is
7840                                                      enabled for output. Writing a value of 0 has no effect
7841                                                      on the corresponding bit in the WT register. Status reads
7842                                                      should be made via the WT register.                                       */
7843     } WTC1_b;
7844   } ;
7845 
7846   union {
7847     __IOM uint32_t WTC2;                        /*!< (@ 0x00000038) GPIO Output Clear 2 (95-64)                                */
7848 
7849     struct {
7850       __IOM uint32_t WTC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin state. Writing a 1 to any bit clears
7851                                                      the corresponding bit in the WT register if the GPIO is
7852                                                      enabled for output. Writing a value of 0 has no effect
7853                                                      on the corresponding bit in the WT register. Status reads
7854                                                      should be made via the WT register.                                       */
7855     } WTC2_b;
7856   } ;
7857 
7858   union {
7859     __IOM uint32_t WTC3;                        /*!< (@ 0x0000003C) GPIO Output Clear 3 (127-96)                               */
7860 
7861     struct {
7862       __IOM uint32_t WTC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin state. Writing a 1 to any bit
7863                                                      clears the corresponding bit in the WT register if the
7864                                                      GPIO is enabled for output. Writing a value of 0 has no
7865                                                      effect on the corresponding bit in the WT register. Status
7866                                                      reads should be made via the WT register.                                 */
7867     } WTC3_b;
7868   } ;
7869 
7870   union {
7871     __IOM uint32_t EN0;                         /*!< (@ 0x00000040) GPIO Enable 0 (31-0)                                       */
7872 
7873     struct {
7874       __IOM uint32_t EN0        : 32;           /*!< [31..0] GPIO31-0 Enables tri-state pin output. Writing a 1 to
7875                                                      any bit enables, and writing a 0 to any bit disables, the
7876                                                      output for the corresponding GPIO. Reads return output
7877                                                      enable/disable status of GPIO.                                            */
7878     } EN0_b;
7879   } ;
7880 
7881   union {
7882     __IOM uint32_t EN1;                         /*!< (@ 0x00000044) GPIO Enable 1 (63-32)                                      */
7883 
7884     struct {
7885       __IOM uint32_t EN1        : 32;           /*!< [31..0] GPIO63-32 Enables tri-state pin output. Writing a 1
7886                                                      to any bit enables, and writing a 0 to any bit disables,
7887                                                      the output for the corresponding GPIO. Reads return output
7888                                                      enable/disable status of GPIO.                                            */
7889     } EN1_b;
7890   } ;
7891 
7892   union {
7893     __IOM uint32_t EN2;                         /*!< (@ 0x00000048) GPIO Enable 2 (95-64)                                      */
7894 
7895     struct {
7896       __IOM uint32_t EN2        : 32;           /*!< [31..0] GPIO95-64 Enables tri-state pin output. Writing a 1
7897                                                      to any bit enables, and writing a 0 to any bit disables,
7898                                                      the output for the corresponding GPIO. Reads return output
7899                                                      enable/disable status of GPIO.                                            */
7900     } EN2_b;
7901   } ;
7902 
7903   union {
7904     __IOM uint32_t EN3;                         /*!< (@ 0x0000004C) GPIO Enable 3 (127-96)                                     */
7905 
7906     struct {
7907       __IOM uint32_t EN3        : 32;           /*!< [31..0] GPIO127-96 Enables tri-state pin output. Writing a 1
7908                                                      to any bit enables, and writing a 0 to any bit disables,
7909                                                      the output for the corresponding GPIO. Reads return output
7910                                                      enable/disable status of GPIO.                                            */
7911     } EN3_b;
7912   } ;
7913 
7914   union {
7915     __IOM uint32_t ENS0;                        /*!< (@ 0x00000050) GPIO Enable Set 0 (31-0)                                   */
7916 
7917     struct {
7918       __IOM uint32_t ENS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin tri-state output enables. Writing
7919                                                      a 1 to any bit sets the corresponding bit in the EN register.
7920                                                      Writing a value of 0 has no effect on the corresponding
7921                                                      bit in the EN register. Status reads should be made to
7922                                                      the EN Register.                                                          */
7923     } ENS0_b;
7924   } ;
7925 
7926   union {
7927     __IOM uint32_t ENS1;                        /*!< (@ 0x00000054) GPIO Enable Set 1 (63-32)                                  */
7928 
7929     struct {
7930       __IOM uint32_t ENS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin tri-state output enables. Writing
7931                                                      a 1 to any bit sets the corresponding bit in the EN register.
7932                                                      Writing a value of 0 has no effect on the corresponding
7933                                                      bit in the EN register. Status reads should be made to
7934                                                      the EN Register.                                                          */
7935     } ENS1_b;
7936   } ;
7937 
7938   union {
7939     __IOM uint32_t ENS2;                        /*!< (@ 0x00000058) GPIO Enable Set 2 (95-64)                                  */
7940 
7941     struct {
7942       __IOM uint32_t ENS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin tri-state output enables. Writing
7943                                                      a 1 to any bit sets the corresponding bit in the EN register.
7944                                                      Writing a value of 0 has no effect on the corresponding
7945                                                      bit in the EN register. Status reads should be made to
7946                                                      the EN Register.                                                          */
7947     } ENS2_b;
7948   } ;
7949 
7950   union {
7951     __IOM uint32_t ENS3;                        /*!< (@ 0x0000005C) GPIO Enable Set 3 (127-96)                                 */
7952 
7953     struct {
7954       __IOM uint32_t ENS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin tri-state output enables. Writing
7955                                                      a 1 to any bit sets the corresponding bit in the EN register.
7956                                                      Writing a value of 0 has no effect on the corresponding
7957                                                      bit in the EN register. Status reads should be made to
7958                                                      the EN Register.                                                          */
7959     } ENS3_b;
7960   } ;
7961 
7962   union {
7963     __IOM uint32_t ENC0;                        /*!< (@ 0x00000060) GPIO Enable Clear 0 (31-0)                                 */
7964 
7965     struct {
7966       __IOM uint32_t ENC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin tri-state output enables. Writing
7967                                                      a 1 to any bit clears the corresponding bit in the EN register.
7968                                                      Writing a value of 0 has no effect on the corresponding
7969                                                      bit in the EN register. Status reads should be made to
7970                                                      the EN Register.                                                          */
7971     } ENC0_b;
7972   } ;
7973 
7974   union {
7975     __IOM uint32_t ENC1;                        /*!< (@ 0x00000064) GPIO Enable Clear 1 (63-32)                                */
7976 
7977     struct {
7978       __IOM uint32_t ENC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin tri-state output enables. Writing
7979                                                      a 1 to any bit clears the corresponding bit in the EN register.
7980                                                      Writing a value of 0 has no effect on the corresponding
7981                                                      bit in the EN register. Status reads should be made to
7982                                                      the EN Register.                                                          */
7983     } ENC1_b;
7984   } ;
7985 
7986   union {
7987     __IOM uint32_t ENC2;                        /*!< (@ 0x00000068) GPIO Enable Clear 2 (95-64)                                */
7988 
7989     struct {
7990       __IOM uint32_t ENC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin tri-state output enables. Writing
7991                                                      a 1 to any bit clears the corresponding bit in the EN register.
7992                                                      Writing a value of 0 has no effect on the corresponding
7993                                                      bit in the EN register. Status reads should be made to
7994                                                      the EN Register.                                                          */
7995     } ENC2_b;
7996   } ;
7997 
7998   union {
7999     __IOM uint32_t ENC3;                        /*!< (@ 0x0000006C) GPIO Enable Clear 3 (127-96)                               */
8000 
8001     struct {
8002       __IOM uint32_t ENC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin tri-state output enables. Writing
8003                                                      a 1 to any bit clears the corresponding bit in the EN register.
8004                                                      Writing a value of 0 has no effect on the corresponding
8005                                                      bit in the EN register. Status reads should be made to
8006                                                      the EN Register.                                                          */
8007     } ENC3_b;
8008   } ;
8009 } FPIO_Type;                                    /*!< Size = 112 (0x70)                                                         */
8010 
8011 
8012 
8013 /* =========================================================================================================================== */
8014 /* ================                                           GPIO                                            ================ */
8015 /* =========================================================================================================================== */
8016 
8017 
8018 /**
8019   * @brief General Purpose IO (GPIO)
8020   */
8021 
8022 typedef struct {                                /*!< (@ 0x40010000) GPIO Structure                                             */
8023 
8024   union {
8025     __IOM uint32_t PINCFG0;                     /*!< (@ 0x00000000) Controls the operation of GPIO pin 0.                      */
8026 
8027     struct {
8028       __IOM uint32_t FNCSEL0    : 4;            /*!< [3..0] Function select for GPIO pin 0                                     */
8029       __IOM uint32_t INPEN0     : 1;            /*!< [4..4] Input enable for GPIO 0                                            */
8030       __IOM uint32_t RDZERO0    : 1;            /*!< [5..5] Return 0 for read data on GPIO 0                                   */
8031       __IOM uint32_t IRPTEN0    : 2;            /*!< [7..6] Interrupt enable for GPIO 0                                        */
8032       __IOM uint32_t OUTCFG0    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 0                               */
8033       __IOM uint32_t DS0        : 2;            /*!< [11..10] Drive strength selection for GPIO 0                              */
8034       __IOM uint32_t SR0        : 1;            /*!< [12..12] Configure the slew rate                                          */
8035       __IOM uint32_t PULLCFG0   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 0                         */
8036       __IOM uint32_t NCESRC0    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 0, DISP control signals DE,
8037                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8038       __IOM uint32_t NCEPOL0    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 0                               */
8039             uint32_t            : 3;
8040       __IOM uint32_t FIEN0      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8041                                                      Otherwise the selected function will enable the input only
8042                                                      when needed                                                               */
8043       __IOM uint32_t FOEN0      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8044                                                      Otherwise the selected function will enable the output
8045                                                      only when needed                                                          */
8046             uint32_t            : 4;
8047     } PINCFG0_b;
8048   } ;
8049 
8050   union {
8051     __IOM uint32_t PINCFG1;                     /*!< (@ 0x00000004) Controls the operation of GPIO pin 1.                      */
8052 
8053     struct {
8054       __IOM uint32_t FNCSEL1    : 4;            /*!< [3..0] Function select for GPIO pin 1                                     */
8055       __IOM uint32_t INPEN1     : 1;            /*!< [4..4] Input enable for GPIO 1                                            */
8056       __IOM uint32_t RDZERO1    : 1;            /*!< [5..5] Return 0 for read data on GPIO 1                                   */
8057       __IOM uint32_t IRPTEN1    : 2;            /*!< [7..6] Interrupt enable for GPIO 1                                        */
8058       __IOM uint32_t OUTCFG1    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 1                               */
8059       __IOM uint32_t DS1        : 2;            /*!< [11..10] Drive strength selection for GPIO 1                              */
8060       __IOM uint32_t SR1        : 1;            /*!< [12..12] Configure the slew rate                                          */
8061       __IOM uint32_t PULLCFG1   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 1                         */
8062       __IOM uint32_t NCESRC1    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 1, DISP control signals DE,
8063                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8064       __IOM uint32_t NCEPOL1    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 1                               */
8065             uint32_t            : 3;
8066       __IOM uint32_t FIEN1      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8067                                                      Otherwise the selected function will enable the input only
8068                                                      when needed                                                               */
8069       __IOM uint32_t FOEN1      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8070                                                      Otherwise the selected function will enable the output
8071                                                      only when needed                                                          */
8072             uint32_t            : 4;
8073     } PINCFG1_b;
8074   } ;
8075 
8076   union {
8077     __IOM uint32_t PINCFG2;                     /*!< (@ 0x00000008) Controls the operation of GPIO pin 2.                      */
8078 
8079     struct {
8080       __IOM uint32_t FNCSEL2    : 4;            /*!< [3..0] Function select for GPIO pin 2                                     */
8081       __IOM uint32_t INPEN2     : 1;            /*!< [4..4] Input enable for GPIO 2                                            */
8082       __IOM uint32_t RDZERO2    : 1;            /*!< [5..5] Return 0 for read data on GPIO 2                                   */
8083       __IOM uint32_t IRPTEN2    : 2;            /*!< [7..6] Interrupt enable for GPIO 2                                        */
8084       __IOM uint32_t OUTCFG2    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 2                               */
8085       __IOM uint32_t DS2        : 2;            /*!< [11..10] Drive strength selection for GPIO 2                              */
8086       __IOM uint32_t SR2        : 1;            /*!< [12..12] Configure the slew rate                                          */
8087       __IOM uint32_t PULLCFG2   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 2                         */
8088       __IOM uint32_t NCESRC2    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 2, DISP control signals DE,
8089                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8090       __IOM uint32_t NCEPOL2    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 2                               */
8091             uint32_t            : 3;
8092       __IOM uint32_t FIEN2      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8093                                                      Otherwise the selected function will enable the input only
8094                                                      when needed                                                               */
8095       __IOM uint32_t FOEN2      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8096                                                      Otherwise the selected function will enable the output
8097                                                      only when needed                                                          */
8098             uint32_t            : 4;
8099     } PINCFG2_b;
8100   } ;
8101 
8102   union {
8103     __IOM uint32_t PINCFG3;                     /*!< (@ 0x0000000C) Controls the operation of GPIO pin 3.                      */
8104 
8105     struct {
8106       __IOM uint32_t FNCSEL3    : 4;            /*!< [3..0] Function select for GPIO pin 3                                     */
8107       __IOM uint32_t INPEN3     : 1;            /*!< [4..4] Input enable for GPIO 3                                            */
8108       __IOM uint32_t RDZERO3    : 1;            /*!< [5..5] Return 0 for read data on GPIO 3                                   */
8109       __IOM uint32_t IRPTEN3    : 2;            /*!< [7..6] Interrupt enable for GPIO 3                                        */
8110       __IOM uint32_t OUTCFG3    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 3                               */
8111       __IOM uint32_t DS3        : 2;            /*!< [11..10] Drive strength selection for GPIO 3                              */
8112       __IOM uint32_t SR3        : 1;            /*!< [12..12] Configure the slew rate                                          */
8113       __IOM uint32_t PULLCFG3   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 3                         */
8114       __IOM uint32_t NCESRC3    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 3, DISP control signals DE,
8115                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8116       __IOM uint32_t NCEPOL3    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 3                               */
8117             uint32_t            : 3;
8118       __IOM uint32_t FIEN3      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8119                                                      Otherwise the selected function will enable the input only
8120                                                      when needed                                                               */
8121       __IOM uint32_t FOEN3      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8122                                                      Otherwise the selected function will enable the output
8123                                                      only when needed                                                          */
8124             uint32_t            : 4;
8125     } PINCFG3_b;
8126   } ;
8127 
8128   union {
8129     __IOM uint32_t PINCFG4;                     /*!< (@ 0x00000010) Controls the operation of GPIO pin 4.                      */
8130 
8131     struct {
8132       __IOM uint32_t FNCSEL4    : 4;            /*!< [3..0] Function select for GPIO pin 4                                     */
8133       __IOM uint32_t INPEN4     : 1;            /*!< [4..4] Input enable for GPIO 4                                            */
8134       __IOM uint32_t RDZERO4    : 1;            /*!< [5..5] Return 0 for read data on GPIO 4                                   */
8135       __IOM uint32_t IRPTEN4    : 2;            /*!< [7..6] Interrupt enable for GPIO 4                                        */
8136       __IOM uint32_t OUTCFG4    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 4                               */
8137       __IOM uint32_t DS4        : 2;            /*!< [11..10] Drive strength selection for GPIO 4                              */
8138       __IOM uint32_t SR4        : 1;            /*!< [12..12] Configure the slew rate                                          */
8139       __IOM uint32_t PULLCFG4   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 4                         */
8140       __IOM uint32_t NCESRC4    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 4, DISP control signals DE,
8141                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8142       __IOM uint32_t NCEPOL4    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 4                               */
8143             uint32_t            : 3;
8144       __IOM uint32_t FIEN4      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8145                                                      Otherwise the selected function will enable the input only
8146                                                      when needed                                                               */
8147       __IOM uint32_t FOEN4      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8148                                                      Otherwise the selected function will enable the output
8149                                                      only when needed                                                          */
8150             uint32_t            : 4;
8151     } PINCFG4_b;
8152   } ;
8153 
8154   union {
8155     __IOM uint32_t PINCFG5;                     /*!< (@ 0x00000014) Controls the operation of GPIO pin 5.                      */
8156 
8157     struct {
8158       __IOM uint32_t FNCSEL5    : 4;            /*!< [3..0] Function select for GPIO pin 5                                     */
8159       __IOM uint32_t INPEN5     : 1;            /*!< [4..4] Input enable for GPIO 5                                            */
8160       __IOM uint32_t RDZERO5    : 1;            /*!< [5..5] Return 0 for read data on GPIO 5                                   */
8161       __IOM uint32_t IRPTEN5    : 2;            /*!< [7..6] Interrupt enable for GPIO 5                                        */
8162       __IOM uint32_t OUTCFG5    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 5                               */
8163       __IOM uint32_t DS5        : 2;            /*!< [11..10] Drive strength selection for GPIO 5                              */
8164       __IOM uint32_t SR5        : 1;            /*!< [12..12] Configure the slew rate                                          */
8165       __IOM uint32_t PULLCFG5   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 5                         */
8166       __IOM uint32_t NCESRC5    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 5, DISP control signals DE,
8167                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8168       __IOM uint32_t NCEPOL5    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 5                               */
8169             uint32_t            : 3;
8170       __IOM uint32_t FIEN5      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8171                                                      Otherwise the selected function will enable the input only
8172                                                      when needed                                                               */
8173       __IOM uint32_t FOEN5      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8174                                                      Otherwise the selected function will enable the output
8175                                                      only when needed                                                          */
8176             uint32_t            : 4;
8177     } PINCFG5_b;
8178   } ;
8179 
8180   union {
8181     __IOM uint32_t PINCFG6;                     /*!< (@ 0x00000018) Controls the operation of GPIO pin 6.                      */
8182 
8183     struct {
8184       __IOM uint32_t FNCSEL6    : 4;            /*!< [3..0] Function select for GPIO pin 6                                     */
8185       __IOM uint32_t INPEN6     : 1;            /*!< [4..4] Input enable for GPIO 6                                            */
8186       __IOM uint32_t RDZERO6    : 1;            /*!< [5..5] Return 0 for read data on GPIO 6                                   */
8187       __IOM uint32_t IRPTEN6    : 2;            /*!< [7..6] Interrupt enable for GPIO 6                                        */
8188       __IOM uint32_t OUTCFG6    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 6                               */
8189       __IOM uint32_t DS6        : 2;            /*!< [11..10] Drive strength selection for GPIO 6                              */
8190       __IOM uint32_t SR6        : 1;            /*!< [12..12] Configure the slew rate                                          */
8191       __IOM uint32_t PULLCFG6   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 6                         */
8192       __IOM uint32_t NCESRC6    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 6, DISP control signals DE,
8193                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8194       __IOM uint32_t NCEPOL6    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 6                               */
8195             uint32_t            : 3;
8196       __IOM uint32_t FIEN6      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8197                                                      Otherwise the selected function will enable the input only
8198                                                      when needed                                                               */
8199       __IOM uint32_t FOEN6      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8200                                                      Otherwise the selected function will enable the output
8201                                                      only when needed                                                          */
8202             uint32_t            : 4;
8203     } PINCFG6_b;
8204   } ;
8205 
8206   union {
8207     __IOM uint32_t PINCFG7;                     /*!< (@ 0x0000001C) Controls the operation of GPIO pin 7.                      */
8208 
8209     struct {
8210       __IOM uint32_t FNCSEL7    : 4;            /*!< [3..0] Function select for GPIO pin 7                                     */
8211       __IOM uint32_t INPEN7     : 1;            /*!< [4..4] Input enable for GPIO 7                                            */
8212       __IOM uint32_t RDZERO7    : 1;            /*!< [5..5] Return 0 for read data on GPIO 7                                   */
8213       __IOM uint32_t IRPTEN7    : 2;            /*!< [7..6] Interrupt enable for GPIO 7                                        */
8214       __IOM uint32_t OUTCFG7    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 7                               */
8215       __IOM uint32_t DS7        : 2;            /*!< [11..10] Drive strength selection for GPIO 7                              */
8216       __IOM uint32_t SR7        : 1;            /*!< [12..12] Configure the slew rate                                          */
8217       __IOM uint32_t PULLCFG7   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 7                         */
8218       __IOM uint32_t NCESRC7    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 7, DISP control signals DE,
8219                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8220       __IOM uint32_t NCEPOL7    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 7                               */
8221             uint32_t            : 3;
8222       __IOM uint32_t FIEN7      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8223                                                      Otherwise the selected function will enable the input only
8224                                                      when needed                                                               */
8225       __IOM uint32_t FOEN7      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8226                                                      Otherwise the selected function will enable the output
8227                                                      only when needed                                                          */
8228             uint32_t            : 4;
8229     } PINCFG7_b;
8230   } ;
8231 
8232   union {
8233     __IOM uint32_t PINCFG8;                     /*!< (@ 0x00000020) Controls the operation of GPIO pin 8.                      */
8234 
8235     struct {
8236       __IOM uint32_t FNCSEL8    : 4;            /*!< [3..0] Function select for GPIO pin 8                                     */
8237       __IOM uint32_t INPEN8     : 1;            /*!< [4..4] Input enable for GPIO 8                                            */
8238       __IOM uint32_t RDZERO8    : 1;            /*!< [5..5] Return 0 for read data on GPIO 8                                   */
8239       __IOM uint32_t IRPTEN8    : 2;            /*!< [7..6] Interrupt enable for GPIO 8                                        */
8240       __IOM uint32_t OUTCFG8    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 8                               */
8241       __IOM uint32_t DS8        : 2;            /*!< [11..10] Drive strength selection for GPIO 8                              */
8242       __IOM uint32_t SR8        : 1;            /*!< [12..12] Configure the slew rate                                          */
8243       __IOM uint32_t PULLCFG8   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 8                         */
8244       __IOM uint32_t NCESRC8    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 8, DISP control signals DE,
8245                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8246       __IOM uint32_t NCEPOL8    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 8                               */
8247             uint32_t            : 3;
8248       __IOM uint32_t FIEN8      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8249                                                      Otherwise the selected function will enable the input only
8250                                                      when needed                                                               */
8251       __IOM uint32_t FOEN8      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8252                                                      Otherwise the selected function will enable the output
8253                                                      only when needed                                                          */
8254             uint32_t            : 4;
8255     } PINCFG8_b;
8256   } ;
8257 
8258   union {
8259     __IOM uint32_t PINCFG9;                     /*!< (@ 0x00000024) Controls the operation of GPIO pin 9.                      */
8260 
8261     struct {
8262       __IOM uint32_t FNCSEL9    : 4;            /*!< [3..0] Function select for GPIO pin 9                                     */
8263       __IOM uint32_t INPEN9     : 1;            /*!< [4..4] Input enable for GPIO 9                                            */
8264       __IOM uint32_t RDZERO9    : 1;            /*!< [5..5] Return 0 for read data on GPIO 9                                   */
8265       __IOM uint32_t IRPTEN9    : 2;            /*!< [7..6] Interrupt enable for GPIO 9                                        */
8266       __IOM uint32_t OUTCFG9    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 9                               */
8267       __IOM uint32_t DS9        : 2;            /*!< [11..10] Drive strength selection for GPIO 9                              */
8268       __IOM uint32_t SR9        : 1;            /*!< [12..12] Configure the slew rate                                          */
8269       __IOM uint32_t PULLCFG9   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 9                         */
8270       __IOM uint32_t NCESRC9    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 9, DISP control signals DE,
8271                                                      CSX, and CS. Polarity is determined by CE_POLARITY field                  */
8272       __IOM uint32_t NCEPOL9    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 9                               */
8273             uint32_t            : 3;
8274       __IOM uint32_t FIEN9      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8275                                                      Otherwise the selected function will enable the input only
8276                                                      when needed                                                               */
8277       __IOM uint32_t FOEN9      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8278                                                      Otherwise the selected function will enable the output
8279                                                      only when needed                                                          */
8280             uint32_t            : 4;
8281     } PINCFG9_b;
8282   } ;
8283 
8284   union {
8285     __IOM uint32_t PINCFG10;                    /*!< (@ 0x00000028) Controls the operation of GPIO pin 10.                     */
8286 
8287     struct {
8288       __IOM uint32_t FNCSEL10   : 4;            /*!< [3..0] Function select for GPIO pin 10                                    */
8289       __IOM uint32_t INPEN10    : 1;            /*!< [4..4] Input enable for GPIO 10                                           */
8290       __IOM uint32_t RDZERO10   : 1;            /*!< [5..5] Return 0 for read data on GPIO 10                                  */
8291       __IOM uint32_t IRPTEN10   : 2;            /*!< [7..6] Interrupt enable for GPIO 10                                       */
8292       __IOM uint32_t OUTCFG10   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 10                              */
8293       __IOM uint32_t DS10       : 2;            /*!< [11..10] Drive strength selection for GPIO 10                             */
8294       __IOM uint32_t SR10       : 1;            /*!< [12..12] Configure the slew rate                                          */
8295       __IOM uint32_t PULLCFG10  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 10                        */
8296       __IOM uint32_t NCESRC10   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 10, DISP control signals
8297                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8298                                                      field                                                                     */
8299       __IOM uint32_t NCEPOL10   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 10                              */
8300             uint32_t            : 3;
8301       __IOM uint32_t FIEN10     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8302                                                      Otherwise the selected function will enable the input only
8303                                                      when needed                                                               */
8304       __IOM uint32_t FOEN10     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8305                                                      Otherwise the selected function will enable the output
8306                                                      only when needed                                                          */
8307             uint32_t            : 4;
8308     } PINCFG10_b;
8309   } ;
8310 
8311   union {
8312     __IOM uint32_t PINCFG11;                    /*!< (@ 0x0000002C) Controls the operation of GPIO pin 11.                     */
8313 
8314     struct {
8315       __IOM uint32_t FNCSEL11   : 4;            /*!< [3..0] Function select for GPIO pin 11                                    */
8316       __IOM uint32_t INPEN11    : 1;            /*!< [4..4] Input enable for GPIO 11                                           */
8317       __IOM uint32_t RDZERO11   : 1;            /*!< [5..5] Return 0 for read data on GPIO 11                                  */
8318       __IOM uint32_t IRPTEN11   : 2;            /*!< [7..6] Interrupt enable for GPIO 11                                       */
8319       __IOM uint32_t OUTCFG11   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 11                              */
8320       __IOM uint32_t DS11       : 2;            /*!< [11..10] Drive strength selection for GPIO 11                             */
8321       __IOM uint32_t SR11       : 1;            /*!< [12..12] Configure the slew rate                                          */
8322       __IOM uint32_t PULLCFG11  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 11                        */
8323       __IOM uint32_t NCESRC11   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 11, DISP control signals
8324                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8325                                                      field                                                                     */
8326       __IOM uint32_t NCEPOL11   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 11                              */
8327             uint32_t            : 3;
8328       __IOM uint32_t FIEN11     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8329                                                      Otherwise the selected function will enable the input only
8330                                                      when needed                                                               */
8331       __IOM uint32_t FOEN11     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8332                                                      Otherwise the selected function will enable the output
8333                                                      only when needed                                                          */
8334             uint32_t            : 4;
8335     } PINCFG11_b;
8336   } ;
8337 
8338   union {
8339     __IOM uint32_t PINCFG12;                    /*!< (@ 0x00000030) Controls the operation of GPIO pin 12.                     */
8340 
8341     struct {
8342       __IOM uint32_t FNCSEL12   : 4;            /*!< [3..0] Function select for GPIO pin 12                                    */
8343       __IOM uint32_t INPEN12    : 1;            /*!< [4..4] Input enable for GPIO 12                                           */
8344       __IOM uint32_t RDZERO12   : 1;            /*!< [5..5] Return 0 for read data on GPIO 12                                  */
8345       __IOM uint32_t IRPTEN12   : 2;            /*!< [7..6] Interrupt enable for GPIO 12                                       */
8346       __IOM uint32_t OUTCFG12   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 12                              */
8347       __IOM uint32_t DS12       : 2;            /*!< [11..10] Drive strength selection for GPIO 12                             */
8348       __IOM uint32_t SR12       : 1;            /*!< [12..12] Configure the slew rate                                          */
8349       __IOM uint32_t PULLCFG12  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 12                        */
8350       __IOM uint32_t NCESRC12   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 12, DISP control signals
8351                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8352                                                      field                                                                     */
8353       __IOM uint32_t NCEPOL12   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 12                              */
8354             uint32_t            : 3;
8355       __IOM uint32_t FIEN12     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8356                                                      Otherwise the selected function will enable the input only
8357                                                      when needed                                                               */
8358       __IOM uint32_t FOEN12     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8359                                                      Otherwise the selected function will enable the output
8360                                                      only when needed                                                          */
8361             uint32_t            : 4;
8362     } PINCFG12_b;
8363   } ;
8364 
8365   union {
8366     __IOM uint32_t PINCFG13;                    /*!< (@ 0x00000034) Controls the operation of GPIO pin 13.                     */
8367 
8368     struct {
8369       __IOM uint32_t FNCSEL13   : 4;            /*!< [3..0] Function select for GPIO pin 13                                    */
8370       __IOM uint32_t INPEN13    : 1;            /*!< [4..4] Input enable for GPIO 13                                           */
8371       __IOM uint32_t RDZERO13   : 1;            /*!< [5..5] Return 0 for read data on GPIO 13                                  */
8372       __IOM uint32_t IRPTEN13   : 2;            /*!< [7..6] Interrupt enable for GPIO 13                                       */
8373       __IOM uint32_t OUTCFG13   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 13                              */
8374       __IOM uint32_t DS13       : 2;            /*!< [11..10] Drive strength selection for GPIO 13                             */
8375       __IOM uint32_t SR13       : 1;            /*!< [12..12] Configure the slew rate                                          */
8376       __IOM uint32_t PULLCFG13  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 13                        */
8377       __IOM uint32_t NCESRC13   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 13, DISP control signals
8378                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8379                                                      field                                                                     */
8380       __IOM uint32_t NCEPOL13   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 13                              */
8381             uint32_t            : 3;
8382       __IOM uint32_t FIEN13     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8383                                                      Otherwise the selected function will enable the input only
8384                                                      when needed                                                               */
8385       __IOM uint32_t FOEN13     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8386                                                      Otherwise the selected function will enable the output
8387                                                      only when needed                                                          */
8388             uint32_t            : 4;
8389     } PINCFG13_b;
8390   } ;
8391 
8392   union {
8393     __IOM uint32_t PINCFG14;                    /*!< (@ 0x00000038) Controls the operation of GPIO pin 14.                     */
8394 
8395     struct {
8396       __IOM uint32_t FNCSEL14   : 4;            /*!< [3..0] Function select for GPIO pin 14                                    */
8397       __IOM uint32_t INPEN14    : 1;            /*!< [4..4] Input enable for GPIO 14                                           */
8398       __IOM uint32_t RDZERO14   : 1;            /*!< [5..5] Return 0 for read data on GPIO 14                                  */
8399       __IOM uint32_t IRPTEN14   : 2;            /*!< [7..6] Interrupt enable for GPIO 14                                       */
8400       __IOM uint32_t OUTCFG14   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 14                              */
8401       __IOM uint32_t DS14       : 2;            /*!< [11..10] Drive strength selection for GPIO 14                             */
8402       __IOM uint32_t SR14       : 1;            /*!< [12..12] Configure the slew rate                                          */
8403       __IOM uint32_t PULLCFG14  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 14                        */
8404       __IOM uint32_t NCESRC14   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 14, DISP control signals
8405                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8406                                                      field                                                                     */
8407       __IOM uint32_t NCEPOL14   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 14                              */
8408             uint32_t            : 3;
8409       __IOM uint32_t FIEN14     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8410                                                      Otherwise the selected function will enable the input only
8411                                                      when needed                                                               */
8412       __IOM uint32_t FOEN14     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8413                                                      Otherwise the selected function will enable the output
8414                                                      only when needed                                                          */
8415             uint32_t            : 4;
8416     } PINCFG14_b;
8417   } ;
8418 
8419   union {
8420     __IOM uint32_t PINCFG15;                    /*!< (@ 0x0000003C) Controls the operation of GPIO pin 15.                     */
8421 
8422     struct {
8423       __IOM uint32_t FNCSEL15   : 4;            /*!< [3..0] Function select for GPIO pin 15                                    */
8424       __IOM uint32_t INPEN15    : 1;            /*!< [4..4] Input enable for GPIO 15                                           */
8425       __IOM uint32_t RDZERO15   : 1;            /*!< [5..5] Return 0 for read data on GPIO 15                                  */
8426       __IOM uint32_t IRPTEN15   : 2;            /*!< [7..6] Interrupt enable for GPIO 15                                       */
8427       __IOM uint32_t OUTCFG15   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 15                              */
8428       __IOM uint32_t DS15       : 2;            /*!< [11..10] Drive strength selection for GPIO 15                             */
8429       __IOM uint32_t SR15       : 1;            /*!< [12..12] Configure the slew rate                                          */
8430       __IOM uint32_t PULLCFG15  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 15                        */
8431       __IOM uint32_t NCESRC15   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 15, DISP control signals
8432                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8433                                                      field                                                                     */
8434       __IOM uint32_t NCEPOL15   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 15                              */
8435             uint32_t            : 3;
8436       __IOM uint32_t FIEN15     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8437                                                      Otherwise the selected function will enable the input only
8438                                                      when needed                                                               */
8439       __IOM uint32_t FOEN15     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8440                                                      Otherwise the selected function will enable the output
8441                                                      only when needed                                                          */
8442             uint32_t            : 4;
8443     } PINCFG15_b;
8444   } ;
8445 
8446   union {
8447     __IOM uint32_t PINCFG16;                    /*!< (@ 0x00000040) Controls the operation of GPIO pin 16.                     */
8448 
8449     struct {
8450       __IOM uint32_t FNCSEL16   : 4;            /*!< [3..0] Function select for GPIO pin 16                                    */
8451       __IOM uint32_t INPEN16    : 1;            /*!< [4..4] Input enable for GPIO 16                                           */
8452       __IOM uint32_t RDZERO16   : 1;            /*!< [5..5] Return 0 for read data on GPIO 16                                  */
8453       __IOM uint32_t IRPTEN16   : 2;            /*!< [7..6] Interrupt enable for GPIO 16                                       */
8454       __IOM uint32_t OUTCFG16   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 16                              */
8455       __IOM uint32_t DS16       : 2;            /*!< [11..10] Drive strength selection for GPIO 16                             */
8456       __IOM uint32_t SR16       : 1;            /*!< [12..12] Configure the slew rate                                          */
8457       __IOM uint32_t PULLCFG16  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 16                        */
8458       __IOM uint32_t NCESRC16   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 16, DISP control signals
8459                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8460                                                      field                                                                     */
8461       __IOM uint32_t NCEPOL16   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 16                              */
8462             uint32_t            : 3;
8463       __IOM uint32_t FIEN16     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8464                                                      Otherwise the selected function will enable the input only
8465                                                      when needed                                                               */
8466       __IOM uint32_t FOEN16     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8467                                                      Otherwise the selected function will enable the output
8468                                                      only when needed                                                          */
8469             uint32_t            : 4;
8470     } PINCFG16_b;
8471   } ;
8472 
8473   union {
8474     __IOM uint32_t PINCFG17;                    /*!< (@ 0x00000044) Controls the operation of GPIO pin 17.                     */
8475 
8476     struct {
8477       __IOM uint32_t FNCSEL17   : 4;            /*!< [3..0] Function select for GPIO pin 17                                    */
8478       __IOM uint32_t INPEN17    : 1;            /*!< [4..4] Input enable for GPIO 17                                           */
8479       __IOM uint32_t RDZERO17   : 1;            /*!< [5..5] Return 0 for read data on GPIO 17                                  */
8480       __IOM uint32_t IRPTEN17   : 2;            /*!< [7..6] Interrupt enable for GPIO 17                                       */
8481       __IOM uint32_t OUTCFG17   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 17                              */
8482       __IOM uint32_t DS17       : 2;            /*!< [11..10] Drive strength selection for GPIO 17                             */
8483       __IOM uint32_t SR17       : 1;            /*!< [12..12] Configure the slew rate                                          */
8484       __IOM uint32_t PULLCFG17  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 17                        */
8485       __IOM uint32_t NCESRC17   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 17, DISP control signals
8486                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8487                                                      field                                                                     */
8488       __IOM uint32_t NCEPOL17   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 17                              */
8489             uint32_t            : 3;
8490       __IOM uint32_t FIEN17     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8491                                                      Otherwise the selected function will enable the input only
8492                                                      when needed                                                               */
8493       __IOM uint32_t FOEN17     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8494                                                      Otherwise the selected function will enable the output
8495                                                      only when needed                                                          */
8496             uint32_t            : 4;
8497     } PINCFG17_b;
8498   } ;
8499 
8500   union {
8501     __IOM uint32_t PINCFG18;                    /*!< (@ 0x00000048) Controls the operation of GPIO pin 18.                     */
8502 
8503     struct {
8504       __IOM uint32_t FNCSEL18   : 4;            /*!< [3..0] Function select for GPIO pin 18                                    */
8505       __IOM uint32_t INPEN18    : 1;            /*!< [4..4] Input enable for GPIO 18                                           */
8506       __IOM uint32_t RDZERO18   : 1;            /*!< [5..5] Return 0 for read data on GPIO 18                                  */
8507       __IOM uint32_t IRPTEN18   : 2;            /*!< [7..6] Interrupt enable for GPIO 18                                       */
8508       __IOM uint32_t OUTCFG18   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 18                              */
8509       __IOM uint32_t DS18       : 2;            /*!< [11..10] Drive strength selection for GPIO 18                             */
8510       __IOM uint32_t SR18       : 1;            /*!< [12..12] Configure the slew rate                                          */
8511       __IOM uint32_t PULLCFG18  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 18                        */
8512       __IOM uint32_t NCESRC18   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 18, DISP control signals
8513                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8514                                                      field                                                                     */
8515       __IOM uint32_t NCEPOL18   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 18                              */
8516             uint32_t            : 3;
8517       __IOM uint32_t FIEN18     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8518                                                      Otherwise the selected function will enable the input only
8519                                                      when needed                                                               */
8520       __IOM uint32_t FOEN18     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8521                                                      Otherwise the selected function will enable the output
8522                                                      only when needed                                                          */
8523             uint32_t            : 4;
8524     } PINCFG18_b;
8525   } ;
8526 
8527   union {
8528     __IOM uint32_t PINCFG19;                    /*!< (@ 0x0000004C) Controls the operation of GPIO pin 19.                     */
8529 
8530     struct {
8531       __IOM uint32_t FNCSEL19   : 4;            /*!< [3..0] Function select for GPIO pin 19                                    */
8532       __IOM uint32_t INPEN19    : 1;            /*!< [4..4] Input enable for GPIO 19                                           */
8533       __IOM uint32_t RDZERO19   : 1;            /*!< [5..5] Return 0 for read data on GPIO 19                                  */
8534       __IOM uint32_t IRPTEN19   : 2;            /*!< [7..6] Interrupt enable for GPIO 19                                       */
8535       __IOM uint32_t OUTCFG19   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 19                              */
8536       __IOM uint32_t DS19       : 2;            /*!< [11..10] Drive strength selection for GPIO 19                             */
8537       __IOM uint32_t SR19       : 1;            /*!< [12..12] Configure the slew rate                                          */
8538       __IOM uint32_t PULLCFG19  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 19                        */
8539       __IOM uint32_t NCESRC19   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 19, DISP control signals
8540                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8541                                                      field                                                                     */
8542       __IOM uint32_t NCEPOL19   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 19                              */
8543             uint32_t            : 3;
8544       __IOM uint32_t FIEN19     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8545                                                      Otherwise the selected function will enable the input only
8546                                                      when needed                                                               */
8547       __IOM uint32_t FOEN19     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8548                                                      Otherwise the selected function will enable the output
8549                                                      only when needed                                                          */
8550             uint32_t            : 4;
8551     } PINCFG19_b;
8552   } ;
8553 
8554   union {
8555     __IOM uint32_t PINCFG20;                    /*!< (@ 0x00000050) Controls the operation of GPIO pin 20.                     */
8556 
8557     struct {
8558       __IOM uint32_t FNCSEL20   : 4;            /*!< [3..0] Function select for GPIO pin 20                                    */
8559       __IOM uint32_t INPEN20    : 1;            /*!< [4..4] Input enable for GPIO 20                                           */
8560       __IOM uint32_t RDZERO20   : 1;            /*!< [5..5] Return 0 for read data on GPIO 20                                  */
8561       __IOM uint32_t IRPTEN20   : 2;            /*!< [7..6] Interrupt enable for GPIO 20                                       */
8562       __IOM uint32_t OUTCFG20   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 20                              */
8563       __IOM uint32_t DS20       : 2;            /*!< [11..10] Drive strength selection for GPIO 20                             */
8564       __IOM uint32_t SR20       : 1;            /*!< [12..12] Configure the slew rate                                          */
8565       __IOM uint32_t PULLCFG20  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 20                        */
8566       __IOM uint32_t NCESRC20   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 20, DISP control signals
8567                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8568                                                      field                                                                     */
8569       __IOM uint32_t NCEPOL20   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 20                              */
8570             uint32_t            : 3;
8571       __IOM uint32_t FIEN20     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8572                                                      Otherwise the selected function will enable the input only
8573                                                      when needed                                                               */
8574       __IOM uint32_t FOEN20     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8575                                                      Otherwise the selected function will enable the output
8576                                                      only when needed                                                          */
8577             uint32_t            : 4;
8578     } PINCFG20_b;
8579   } ;
8580 
8581   union {
8582     __IOM uint32_t PINCFG21;                    /*!< (@ 0x00000054) Controls the operation of GPIO pin 21.                     */
8583 
8584     struct {
8585       __IOM uint32_t FNCSEL21   : 4;            /*!< [3..0] Function select for GPIO pin 21                                    */
8586       __IOM uint32_t INPEN21    : 1;            /*!< [4..4] Input enable for GPIO 21                                           */
8587       __IOM uint32_t RDZERO21   : 1;            /*!< [5..5] Return 0 for read data on GPIO 21                                  */
8588       __IOM uint32_t IRPTEN21   : 2;            /*!< [7..6] Interrupt enable for GPIO 21                                       */
8589       __IOM uint32_t OUTCFG21   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 21                              */
8590       __IOM uint32_t DS21       : 2;            /*!< [11..10] Drive strength selection for GPIO 21                             */
8591       __IOM uint32_t SR21       : 1;            /*!< [12..12] Configure the slew rate                                          */
8592       __IOM uint32_t PULLCFG21  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 21                        */
8593       __IOM uint32_t NCESRC21   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 21, DISP control signals
8594                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8595                                                      field                                                                     */
8596       __IOM uint32_t NCEPOL21   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 21                              */
8597             uint32_t            : 3;
8598       __IOM uint32_t FIEN21     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8599                                                      Otherwise the selected function will enable the input only
8600                                                      when needed                                                               */
8601       __IOM uint32_t FOEN21     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8602                                                      Otherwise the selected function will enable the output
8603                                                      only when needed                                                          */
8604             uint32_t            : 4;
8605     } PINCFG21_b;
8606   } ;
8607 
8608   union {
8609     __IOM uint32_t PINCFG22;                    /*!< (@ 0x00000058) Controls the operation of GPIO pin 22.                     */
8610 
8611     struct {
8612       __IOM uint32_t FNCSEL22   : 4;            /*!< [3..0] Function select for GPIO pin 22                                    */
8613       __IOM uint32_t INPEN22    : 1;            /*!< [4..4] Input enable for GPIO 22                                           */
8614       __IOM uint32_t RDZERO22   : 1;            /*!< [5..5] Return 0 for read data on GPIO 22                                  */
8615       __IOM uint32_t IRPTEN22   : 2;            /*!< [7..6] Interrupt enable for GPIO 22                                       */
8616       __IOM uint32_t OUTCFG22   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 22                              */
8617       __IOM uint32_t DS22       : 2;            /*!< [11..10] Drive strength selection for GPIO 22                             */
8618       __IOM uint32_t SR22       : 1;            /*!< [12..12] Configure the slew rate                                          */
8619       __IOM uint32_t PULLCFG22  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 22                        */
8620       __IOM uint32_t NCESRC22   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 22, DISP control signals
8621                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8622                                                      field                                                                     */
8623       __IOM uint32_t NCEPOL22   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 22                              */
8624             uint32_t            : 3;
8625       __IOM uint32_t FIEN22     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8626                                                      Otherwise the selected function will enable the input only
8627                                                      when needed                                                               */
8628       __IOM uint32_t FOEN22     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8629                                                      Otherwise the selected function will enable the output
8630                                                      only when needed                                                          */
8631             uint32_t            : 4;
8632     } PINCFG22_b;
8633   } ;
8634 
8635   union {
8636     __IOM uint32_t PINCFG23;                    /*!< (@ 0x0000005C) Controls the operation of GPIO pin 23.                     */
8637 
8638     struct {
8639       __IOM uint32_t FNCSEL23   : 4;            /*!< [3..0] Function select for GPIO pin 23                                    */
8640       __IOM uint32_t INPEN23    : 1;            /*!< [4..4] Input enable for GPIO 23                                           */
8641       __IOM uint32_t RDZERO23   : 1;            /*!< [5..5] Return 0 for read data on GPIO 23                                  */
8642       __IOM uint32_t IRPTEN23   : 2;            /*!< [7..6] Interrupt enable for GPIO 23                                       */
8643       __IOM uint32_t OUTCFG23   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 23                              */
8644       __IOM uint32_t DS23       : 2;            /*!< [11..10] Drive strength selection for GPIO 23                             */
8645       __IOM uint32_t SR23       : 1;            /*!< [12..12] Configure the slew rate                                          */
8646       __IOM uint32_t PULLCFG23  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 23                        */
8647       __IOM uint32_t NCESRC23   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 23, DISP control signals
8648                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8649                                                      field                                                                     */
8650       __IOM uint32_t NCEPOL23   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 23                              */
8651             uint32_t            : 3;
8652       __IOM uint32_t FIEN23     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8653                                                      Otherwise the selected function will enable the input only
8654                                                      when needed                                                               */
8655       __IOM uint32_t FOEN23     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8656                                                      Otherwise the selected function will enable the output
8657                                                      only when needed                                                          */
8658             uint32_t            : 4;
8659     } PINCFG23_b;
8660   } ;
8661 
8662   union {
8663     __IOM uint32_t PINCFG24;                    /*!< (@ 0x00000060) Controls the operation of GPIO pin 24.                     */
8664 
8665     struct {
8666       __IOM uint32_t FNCSEL24   : 4;            /*!< [3..0] Function select for GPIO pin 24                                    */
8667       __IOM uint32_t INPEN24    : 1;            /*!< [4..4] Input enable for GPIO 24                                           */
8668       __IOM uint32_t RDZERO24   : 1;            /*!< [5..5] Return 0 for read data on GPIO 24                                  */
8669       __IOM uint32_t IRPTEN24   : 2;            /*!< [7..6] Interrupt enable for GPIO 24                                       */
8670       __IOM uint32_t OUTCFG24   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 24                              */
8671       __IOM uint32_t DS24       : 2;            /*!< [11..10] Drive strength selection for GPIO 24                             */
8672       __IOM uint32_t SR24       : 1;            /*!< [12..12] Configure the slew rate                                          */
8673       __IOM uint32_t PULLCFG24  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 24                        */
8674       __IOM uint32_t NCESRC24   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 24, DISP control signals
8675                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8676                                                      field                                                                     */
8677       __IOM uint32_t NCEPOL24   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 24                              */
8678             uint32_t            : 3;
8679       __IOM uint32_t FIEN24     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8680                                                      Otherwise the selected function will enable the input only
8681                                                      when needed                                                               */
8682       __IOM uint32_t FOEN24     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8683                                                      Otherwise the selected function will enable the output
8684                                                      only when needed                                                          */
8685             uint32_t            : 4;
8686     } PINCFG24_b;
8687   } ;
8688 
8689   union {
8690     __IOM uint32_t PINCFG25;                    /*!< (@ 0x00000064) Controls the operation of GPIO pin 25.                     */
8691 
8692     struct {
8693       __IOM uint32_t FNCSEL25   : 4;            /*!< [3..0] Function select for GPIO pin 25                                    */
8694       __IOM uint32_t INPEN25    : 1;            /*!< [4..4] Input enable for GPIO 25                                           */
8695       __IOM uint32_t RDZERO25   : 1;            /*!< [5..5] Return 0 for read data on GPIO 25                                  */
8696       __IOM uint32_t IRPTEN25   : 2;            /*!< [7..6] Interrupt enable for GPIO 25                                       */
8697       __IOM uint32_t OUTCFG25   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 25                              */
8698       __IOM uint32_t DS25       : 2;            /*!< [11..10] Drive strength selection for GPIO 25                             */
8699       __IOM uint32_t SR25       : 1;            /*!< [12..12] Configure the slew rate                                          */
8700       __IOM uint32_t PULLCFG25  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 25                        */
8701       __IOM uint32_t NCESRC25   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 25, DISP control signals
8702                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8703                                                      field                                                                     */
8704       __IOM uint32_t NCEPOL25   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 25                              */
8705             uint32_t            : 3;
8706       __IOM uint32_t FIEN25     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8707                                                      Otherwise the selected function will enable the input only
8708                                                      when needed                                                               */
8709       __IOM uint32_t FOEN25     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8710                                                      Otherwise the selected function will enable the output
8711                                                      only when needed                                                          */
8712             uint32_t            : 4;
8713     } PINCFG25_b;
8714   } ;
8715 
8716   union {
8717     __IOM uint32_t PINCFG26;                    /*!< (@ 0x00000068) Controls the operation of GPIO pin 26.                     */
8718 
8719     struct {
8720       __IOM uint32_t FNCSEL26   : 4;            /*!< [3..0] Function select for GPIO pin 26                                    */
8721       __IOM uint32_t INPEN26    : 1;            /*!< [4..4] Input enable for GPIO 26                                           */
8722       __IOM uint32_t RDZERO26   : 1;            /*!< [5..5] Return 0 for read data on GPIO 26                                  */
8723       __IOM uint32_t IRPTEN26   : 2;            /*!< [7..6] Interrupt enable for GPIO 26                                       */
8724       __IOM uint32_t OUTCFG26   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 26                              */
8725       __IOM uint32_t DS26       : 2;            /*!< [11..10] Drive strength selection for GPIO 26                             */
8726       __IOM uint32_t SR26       : 1;            /*!< [12..12] Configure the slew rate                                          */
8727       __IOM uint32_t PULLCFG26  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 26                        */
8728       __IOM uint32_t NCESRC26   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 26, DISP control signals
8729                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8730                                                      field                                                                     */
8731       __IOM uint32_t NCEPOL26   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 26                              */
8732             uint32_t            : 3;
8733       __IOM uint32_t FIEN26     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8734                                                      Otherwise the selected function will enable the input only
8735                                                      when needed                                                               */
8736       __IOM uint32_t FOEN26     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8737                                                      Otherwise the selected function will enable the output
8738                                                      only when needed                                                          */
8739             uint32_t            : 4;
8740     } PINCFG26_b;
8741   } ;
8742 
8743   union {
8744     __IOM uint32_t PINCFG27;                    /*!< (@ 0x0000006C) Controls the operation of GPIO pin 27.                     */
8745 
8746     struct {
8747       __IOM uint32_t FNCSEL27   : 4;            /*!< [3..0] Function select for GPIO pin 27                                    */
8748       __IOM uint32_t INPEN27    : 1;            /*!< [4..4] Input enable for GPIO 27                                           */
8749       __IOM uint32_t RDZERO27   : 1;            /*!< [5..5] Return 0 for read data on GPIO 27                                  */
8750       __IOM uint32_t IRPTEN27   : 2;            /*!< [7..6] Interrupt enable for GPIO 27                                       */
8751       __IOM uint32_t OUTCFG27   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 27                              */
8752       __IOM uint32_t DS27       : 2;            /*!< [11..10] Drive strength selection for GPIO 27                             */
8753       __IOM uint32_t SR27       : 1;            /*!< [12..12] Configure the slew rate                                          */
8754       __IOM uint32_t PULLCFG27  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 27                        */
8755       __IOM uint32_t NCESRC27   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 27, DISP control signals
8756                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8757                                                      field                                                                     */
8758       __IOM uint32_t NCEPOL27   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 27                              */
8759             uint32_t            : 3;
8760       __IOM uint32_t FIEN27     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8761                                                      Otherwise the selected function will enable the input only
8762                                                      when needed                                                               */
8763       __IOM uint32_t FOEN27     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8764                                                      Otherwise the selected function will enable the output
8765                                                      only when needed                                                          */
8766             uint32_t            : 4;
8767     } PINCFG27_b;
8768   } ;
8769 
8770   union {
8771     __IOM uint32_t PINCFG28;                    /*!< (@ 0x00000070) Controls the operation of GPIO pin 28.                     */
8772 
8773     struct {
8774       __IOM uint32_t FNCSEL28   : 4;            /*!< [3..0] Function select for GPIO pin 28                                    */
8775       __IOM uint32_t INPEN28    : 1;            /*!< [4..4] Input enable for GPIO 28                                           */
8776       __IOM uint32_t RDZERO28   : 1;            /*!< [5..5] Return 0 for read data on GPIO 28                                  */
8777       __IOM uint32_t IRPTEN28   : 2;            /*!< [7..6] Interrupt enable for GPIO 28                                       */
8778       __IOM uint32_t OUTCFG28   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 28                              */
8779       __IOM uint32_t DS28       : 2;            /*!< [11..10] Drive strength selection for GPIO 28                             */
8780       __IOM uint32_t SR28       : 1;            /*!< [12..12] Configure the slew rate                                          */
8781       __IOM uint32_t PULLCFG28  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 28                        */
8782       __IOM uint32_t NCESRC28   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 28, DISP control signals
8783                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8784                                                      field                                                                     */
8785       __IOM uint32_t NCEPOL28   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 28                              */
8786             uint32_t            : 3;
8787       __IOM uint32_t FIEN28     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8788                                                      Otherwise the selected function will enable the input only
8789                                                      when needed                                                               */
8790       __IOM uint32_t FOEN28     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8791                                                      Otherwise the selected function will enable the output
8792                                                      only when needed                                                          */
8793             uint32_t            : 4;
8794     } PINCFG28_b;
8795   } ;
8796 
8797   union {
8798     __IOM uint32_t PINCFG29;                    /*!< (@ 0x00000074) Controls the operation of GPIO pin 29.                     */
8799 
8800     struct {
8801       __IOM uint32_t FNCSEL29   : 4;            /*!< [3..0] Function select for GPIO pin 29                                    */
8802       __IOM uint32_t INPEN29    : 1;            /*!< [4..4] Input enable for GPIO 29                                           */
8803       __IOM uint32_t RDZERO29   : 1;            /*!< [5..5] Return 0 for read data on GPIO 29                                  */
8804       __IOM uint32_t IRPTEN29   : 2;            /*!< [7..6] Interrupt enable for GPIO 29                                       */
8805       __IOM uint32_t OUTCFG29   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 29                              */
8806       __IOM uint32_t DS29       : 2;            /*!< [11..10] Drive strength selection for GPIO 29                             */
8807       __IOM uint32_t SR29       : 1;            /*!< [12..12] Configure the slew rate                                          */
8808       __IOM uint32_t PULLCFG29  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 29                        */
8809       __IOM uint32_t NCESRC29   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 29, DISP control signals
8810                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8811                                                      field                                                                     */
8812       __IOM uint32_t NCEPOL29   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 29                              */
8813             uint32_t            : 3;
8814       __IOM uint32_t FIEN29     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8815                                                      Otherwise the selected function will enable the input only
8816                                                      when needed                                                               */
8817       __IOM uint32_t FOEN29     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8818                                                      Otherwise the selected function will enable the output
8819                                                      only when needed                                                          */
8820             uint32_t            : 4;
8821     } PINCFG29_b;
8822   } ;
8823 
8824   union {
8825     __IOM uint32_t PINCFG30;                    /*!< (@ 0x00000078) Controls the operation of GPIO pin 30.                     */
8826 
8827     struct {
8828       __IOM uint32_t FNCSEL30   : 4;            /*!< [3..0] Function select for GPIO pin 30                                    */
8829       __IOM uint32_t INPEN30    : 1;            /*!< [4..4] Input enable for GPIO 30                                           */
8830       __IOM uint32_t RDZERO30   : 1;            /*!< [5..5] Return 0 for read data on GPIO 30                                  */
8831       __IOM uint32_t IRPTEN30   : 2;            /*!< [7..6] Interrupt enable for GPIO 30                                       */
8832       __IOM uint32_t OUTCFG30   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 30                              */
8833       __IOM uint32_t DS30       : 2;            /*!< [11..10] Drive strength selection for GPIO 30                             */
8834       __IOM uint32_t SR30       : 1;            /*!< [12..12] Configure the slew rate                                          */
8835       __IOM uint32_t PULLCFG30  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 30                        */
8836       __IOM uint32_t NCESRC30   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 30, DISP control signals
8837                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8838                                                      field                                                                     */
8839       __IOM uint32_t NCEPOL30   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 30                              */
8840             uint32_t            : 3;
8841       __IOM uint32_t FIEN30     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8842                                                      Otherwise the selected function will enable the input only
8843                                                      when needed                                                               */
8844       __IOM uint32_t FOEN30     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8845                                                      Otherwise the selected function will enable the output
8846                                                      only when needed                                                          */
8847             uint32_t            : 4;
8848     } PINCFG30_b;
8849   } ;
8850 
8851   union {
8852     __IOM uint32_t PINCFG31;                    /*!< (@ 0x0000007C) Controls the operation of GPIO pin 31.                     */
8853 
8854     struct {
8855       __IOM uint32_t FNCSEL31   : 4;            /*!< [3..0] Function select for GPIO pin 31                                    */
8856       __IOM uint32_t INPEN31    : 1;            /*!< [4..4] Input enable for GPIO 31                                           */
8857       __IOM uint32_t RDZERO31   : 1;            /*!< [5..5] Return 0 for read data on GPIO 31                                  */
8858       __IOM uint32_t IRPTEN31   : 2;            /*!< [7..6] Interrupt enable for GPIO 31                                       */
8859       __IOM uint32_t OUTCFG31   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 31                              */
8860       __IOM uint32_t DS31       : 2;            /*!< [11..10] Drive strength selection for GPIO 31                             */
8861       __IOM uint32_t SR31       : 1;            /*!< [12..12] Configure the slew rate                                          */
8862       __IOM uint32_t PULLCFG31  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 31                        */
8863       __IOM uint32_t NCESRC31   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 31, DISP control signals
8864                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8865                                                      field                                                                     */
8866       __IOM uint32_t NCEPOL31   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 31                              */
8867             uint32_t            : 3;
8868       __IOM uint32_t FIEN31     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8869                                                      Otherwise the selected function will enable the input only
8870                                                      when needed                                                               */
8871       __IOM uint32_t FOEN31     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8872                                                      Otherwise the selected function will enable the output
8873                                                      only when needed                                                          */
8874             uint32_t            : 4;
8875     } PINCFG31_b;
8876   } ;
8877 
8878   union {
8879     __IOM uint32_t PINCFG32;                    /*!< (@ 0x00000080) Controls the operation of GPIO pin 32.                     */
8880 
8881     struct {
8882       __IOM uint32_t FNCSEL32   : 4;            /*!< [3..0] Function select for GPIO pin 32                                    */
8883       __IOM uint32_t INPEN32    : 1;            /*!< [4..4] Input enable for GPIO 32                                           */
8884       __IOM uint32_t RDZERO32   : 1;            /*!< [5..5] Return 0 for read data on GPIO 32                                  */
8885       __IOM uint32_t IRPTEN32   : 2;            /*!< [7..6] Interrupt enable for GPIO 32                                       */
8886       __IOM uint32_t OUTCFG32   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 32                              */
8887       __IOM uint32_t DS32       : 2;            /*!< [11..10] Drive strength selection for GPIO 32                             */
8888       __IOM uint32_t SR32       : 1;            /*!< [12..12] Configure the slew rate                                          */
8889       __IOM uint32_t PULLCFG32  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 32                        */
8890       __IOM uint32_t NCESRC32   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 32, DISP control signals
8891                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8892                                                      field                                                                     */
8893       __IOM uint32_t NCEPOL32   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 32                              */
8894             uint32_t            : 3;
8895       __IOM uint32_t FIEN32     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8896                                                      Otherwise the selected function will enable the input only
8897                                                      when needed                                                               */
8898       __IOM uint32_t FOEN32     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8899                                                      Otherwise the selected function will enable the output
8900                                                      only when needed                                                          */
8901             uint32_t            : 4;
8902     } PINCFG32_b;
8903   } ;
8904 
8905   union {
8906     __IOM uint32_t PINCFG33;                    /*!< (@ 0x00000084) Controls the operation of GPIO pin 33.                     */
8907 
8908     struct {
8909       __IOM uint32_t FNCSEL33   : 4;            /*!< [3..0] Function select for GPIO pin 33                                    */
8910       __IOM uint32_t INPEN33    : 1;            /*!< [4..4] Input enable for GPIO 33                                           */
8911       __IOM uint32_t RDZERO33   : 1;            /*!< [5..5] Return 0 for read data on GPIO 33                                  */
8912       __IOM uint32_t IRPTEN33   : 2;            /*!< [7..6] Interrupt enable for GPIO 33                                       */
8913       __IOM uint32_t OUTCFG33   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 33                              */
8914       __IOM uint32_t DS33       : 2;            /*!< [11..10] Drive strength selection for GPIO 33                             */
8915       __IOM uint32_t SR33       : 1;            /*!< [12..12] Configure the slew rate                                          */
8916       __IOM uint32_t PULLCFG33  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 33                        */
8917       __IOM uint32_t NCESRC33   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 33, DISP control signals
8918                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8919                                                      field                                                                     */
8920       __IOM uint32_t NCEPOL33   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 33                              */
8921             uint32_t            : 3;
8922       __IOM uint32_t FIEN33     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8923                                                      Otherwise the selected function will enable the input only
8924                                                      when needed                                                               */
8925       __IOM uint32_t FOEN33     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8926                                                      Otherwise the selected function will enable the output
8927                                                      only when needed                                                          */
8928             uint32_t            : 4;
8929     } PINCFG33_b;
8930   } ;
8931 
8932   union {
8933     __IOM uint32_t PINCFG34;                    /*!< (@ 0x00000088) Controls the operation of GPIO pin 34.                     */
8934 
8935     struct {
8936       __IOM uint32_t FNCSEL34   : 4;            /*!< [3..0] Function select for GPIO pin 34                                    */
8937       __IOM uint32_t INPEN34    : 1;            /*!< [4..4] Input enable for GPIO 34                                           */
8938       __IOM uint32_t RDZERO34   : 1;            /*!< [5..5] Return 0 for read data on GPIO 34                                  */
8939       __IOM uint32_t IRPTEN34   : 2;            /*!< [7..6] Interrupt enable for GPIO 34                                       */
8940       __IOM uint32_t OUTCFG34   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 34                              */
8941       __IOM uint32_t DS34       : 2;            /*!< [11..10] Drive strength selection for GPIO 34                             */
8942       __IOM uint32_t SR34       : 1;            /*!< [12..12] Configure the slew rate                                          */
8943       __IOM uint32_t PULLCFG34  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 34                        */
8944       __IOM uint32_t NCESRC34   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 34, DISP control signals
8945                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8946                                                      field                                                                     */
8947       __IOM uint32_t NCEPOL34   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 34                              */
8948             uint32_t            : 3;
8949       __IOM uint32_t FIEN34     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8950                                                      Otherwise the selected function will enable the input only
8951                                                      when needed                                                               */
8952       __IOM uint32_t FOEN34     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8953                                                      Otherwise the selected function will enable the output
8954                                                      only when needed                                                          */
8955             uint32_t            : 4;
8956     } PINCFG34_b;
8957   } ;
8958 
8959   union {
8960     __IOM uint32_t PINCFG35;                    /*!< (@ 0x0000008C) Controls the operation of GPIO pin 35.                     */
8961 
8962     struct {
8963       __IOM uint32_t FNCSEL35   : 4;            /*!< [3..0] Function select for GPIO pin 35                                    */
8964       __IOM uint32_t INPEN35    : 1;            /*!< [4..4] Input enable for GPIO 35                                           */
8965       __IOM uint32_t RDZERO35   : 1;            /*!< [5..5] Return 0 for read data on GPIO 35                                  */
8966       __IOM uint32_t IRPTEN35   : 2;            /*!< [7..6] Interrupt enable for GPIO 35                                       */
8967       __IOM uint32_t OUTCFG35   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 35                              */
8968       __IOM uint32_t DS35       : 2;            /*!< [11..10] Drive strength selection for GPIO 35                             */
8969       __IOM uint32_t SR35       : 1;            /*!< [12..12] Configure the slew rate                                          */
8970       __IOM uint32_t PULLCFG35  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 35                        */
8971       __IOM uint32_t NCESRC35   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 35, DISP control signals
8972                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
8973                                                      field                                                                     */
8974       __IOM uint32_t NCEPOL35   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 35                              */
8975             uint32_t            : 3;
8976       __IOM uint32_t FIEN35     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
8977                                                      Otherwise the selected function will enable the input only
8978                                                      when needed                                                               */
8979       __IOM uint32_t FOEN35     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
8980                                                      Otherwise the selected function will enable the output
8981                                                      only when needed                                                          */
8982             uint32_t            : 4;
8983     } PINCFG35_b;
8984   } ;
8985 
8986   union {
8987     __IOM uint32_t PINCFG36;                    /*!< (@ 0x00000090) Controls the operation of GPIO pin 36.                     */
8988 
8989     struct {
8990       __IOM uint32_t FNCSEL36   : 4;            /*!< [3..0] Function select for GPIO pin 36                                    */
8991       __IOM uint32_t INPEN36    : 1;            /*!< [4..4] Input enable for GPIO 36                                           */
8992       __IOM uint32_t RDZERO36   : 1;            /*!< [5..5] Return 0 for read data on GPIO 36                                  */
8993       __IOM uint32_t IRPTEN36   : 2;            /*!< [7..6] Interrupt enable for GPIO 36                                       */
8994       __IOM uint32_t OUTCFG36   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 36                              */
8995       __IOM uint32_t DS36       : 2;            /*!< [11..10] Drive strength selection for GPIO 36                             */
8996       __IOM uint32_t SR36       : 1;            /*!< [12..12] Configure the slew rate                                          */
8997       __IOM uint32_t PULLCFG36  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 36                        */
8998       __IOM uint32_t NCESRC36   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 36, DISP control signals
8999                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9000                                                      field                                                                     */
9001       __IOM uint32_t NCEPOL36   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 36                              */
9002             uint32_t            : 3;
9003       __IOM uint32_t FIEN36     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9004                                                      Otherwise the selected function will enable the input only
9005                                                      when needed                                                               */
9006       __IOM uint32_t FOEN36     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9007                                                      Otherwise the selected function will enable the output
9008                                                      only when needed                                                          */
9009             uint32_t            : 4;
9010     } PINCFG36_b;
9011   } ;
9012 
9013   union {
9014     __IOM uint32_t PINCFG37;                    /*!< (@ 0x00000094) Controls the operation of GPIO pin 37.                     */
9015 
9016     struct {
9017       __IOM uint32_t FNCSEL37   : 4;            /*!< [3..0] Function select for GPIO pin 37                                    */
9018       __IOM uint32_t INPEN37    : 1;            /*!< [4..4] Input enable for GPIO 37                                           */
9019       __IOM uint32_t RDZERO37   : 1;            /*!< [5..5] Return 0 for read data on GPIO 37                                  */
9020       __IOM uint32_t IRPTEN37   : 2;            /*!< [7..6] Interrupt enable for GPIO 37                                       */
9021       __IOM uint32_t OUTCFG37   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 37                              */
9022       __IOM uint32_t DS37       : 2;            /*!< [11..10] Drive strength selection for GPIO 37                             */
9023       __IOM uint32_t SR37       : 1;            /*!< [12..12] Configure the slew rate                                          */
9024       __IOM uint32_t PULLCFG37  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 37                        */
9025       __IOM uint32_t NCESRC37   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 37, DISP control signals
9026                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9027                                                      field                                                                     */
9028       __IOM uint32_t NCEPOL37   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 37                              */
9029             uint32_t            : 3;
9030       __IOM uint32_t FIEN37     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9031                                                      Otherwise the selected function will enable the input only
9032                                                      when needed                                                               */
9033       __IOM uint32_t FOEN37     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9034                                                      Otherwise the selected function will enable the output
9035                                                      only when needed                                                          */
9036             uint32_t            : 4;
9037     } PINCFG37_b;
9038   } ;
9039 
9040   union {
9041     __IOM uint32_t PINCFG38;                    /*!< (@ 0x00000098) Controls the operation of GPIO pin 38.                     */
9042 
9043     struct {
9044       __IOM uint32_t FNCSEL38   : 4;            /*!< [3..0] Function select for GPIO pin 38                                    */
9045       __IOM uint32_t INPEN38    : 1;            /*!< [4..4] Input enable for GPIO 38                                           */
9046       __IOM uint32_t RDZERO38   : 1;            /*!< [5..5] Return 0 for read data on GPIO 38                                  */
9047       __IOM uint32_t IRPTEN38   : 2;            /*!< [7..6] Interrupt enable for GPIO 38                                       */
9048       __IOM uint32_t OUTCFG38   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 38                              */
9049       __IOM uint32_t DS38       : 2;            /*!< [11..10] Drive strength selection for GPIO 38                             */
9050       __IOM uint32_t SR38       : 1;            /*!< [12..12] Configure the slew rate                                          */
9051       __IOM uint32_t PULLCFG38  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 38                        */
9052       __IOM uint32_t NCESRC38   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 38, DISP control signals
9053                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9054                                                      field                                                                     */
9055       __IOM uint32_t NCEPOL38   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 38                              */
9056             uint32_t            : 3;
9057       __IOM uint32_t FIEN38     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9058                                                      Otherwise the selected function will enable the input only
9059                                                      when needed                                                               */
9060       __IOM uint32_t FOEN38     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9061                                                      Otherwise the selected function will enable the output
9062                                                      only when needed                                                          */
9063             uint32_t            : 4;
9064     } PINCFG38_b;
9065   } ;
9066 
9067   union {
9068     __IOM uint32_t PINCFG39;                    /*!< (@ 0x0000009C) Controls the operation of GPIO pin 39.                     */
9069 
9070     struct {
9071       __IOM uint32_t FNCSEL39   : 4;            /*!< [3..0] Function select for GPIO pin 39                                    */
9072       __IOM uint32_t INPEN39    : 1;            /*!< [4..4] Input enable for GPIO 39                                           */
9073       __IOM uint32_t RDZERO39   : 1;            /*!< [5..5] Return 0 for read data on GPIO 39                                  */
9074       __IOM uint32_t IRPTEN39   : 2;            /*!< [7..6] Interrupt enable for GPIO 39                                       */
9075       __IOM uint32_t OUTCFG39   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 39                              */
9076       __IOM uint32_t DS39       : 2;            /*!< [11..10] Drive strength selection for GPIO 39                             */
9077       __IOM uint32_t SR39       : 1;            /*!< [12..12] Configure the slew rate                                          */
9078       __IOM uint32_t PULLCFG39  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 39                        */
9079       __IOM uint32_t NCESRC39   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 39, DISP control signals
9080                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9081                                                      field                                                                     */
9082       __IOM uint32_t NCEPOL39   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 39                              */
9083             uint32_t            : 3;
9084       __IOM uint32_t FIEN39     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9085                                                      Otherwise the selected function will enable the input only
9086                                                      when needed                                                               */
9087       __IOM uint32_t FOEN39     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9088                                                      Otherwise the selected function will enable the output
9089                                                      only when needed                                                          */
9090             uint32_t            : 4;
9091     } PINCFG39_b;
9092   } ;
9093 
9094   union {
9095     __IOM uint32_t PINCFG40;                    /*!< (@ 0x000000A0) Controls the operation of GPIO pin 40.                     */
9096 
9097     struct {
9098       __IOM uint32_t FNCSEL40   : 4;            /*!< [3..0] Function select for GPIO pin 40                                    */
9099       __IOM uint32_t INPEN40    : 1;            /*!< [4..4] Input enable for GPIO 40                                           */
9100       __IOM uint32_t RDZERO40   : 1;            /*!< [5..5] Return 0 for read data on GPIO 40                                  */
9101       __IOM uint32_t IRPTEN40   : 2;            /*!< [7..6] Interrupt enable for GPIO 40                                       */
9102       __IOM uint32_t OUTCFG40   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 40                              */
9103       __IOM uint32_t DS40       : 2;            /*!< [11..10] Drive strength selection for GPIO 40                             */
9104       __IOM uint32_t SR40       : 1;            /*!< [12..12] Configure the slew rate                                          */
9105       __IOM uint32_t PULLCFG40  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 40                        */
9106       __IOM uint32_t NCESRC40   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 40, DISP control signals
9107                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9108                                                      field                                                                     */
9109       __IOM uint32_t NCEPOL40   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 40                              */
9110             uint32_t            : 3;
9111       __IOM uint32_t FIEN40     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9112                                                      Otherwise the selected function will enable the input only
9113                                                      when needed                                                               */
9114       __IOM uint32_t FOEN40     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9115                                                      Otherwise the selected function will enable the output
9116                                                      only when needed                                                          */
9117             uint32_t            : 4;
9118     } PINCFG40_b;
9119   } ;
9120 
9121   union {
9122     __IOM uint32_t PINCFG41;                    /*!< (@ 0x000000A4) Controls the operation of GPIO pin 41.                     */
9123 
9124     struct {
9125       __IOM uint32_t FNCSEL41   : 4;            /*!< [3..0] Function select for GPIO pin 41                                    */
9126       __IOM uint32_t INPEN41    : 1;            /*!< [4..4] Input enable for GPIO 41                                           */
9127       __IOM uint32_t RDZERO41   : 1;            /*!< [5..5] Return 0 for read data on GPIO 41                                  */
9128       __IOM uint32_t IRPTEN41   : 2;            /*!< [7..6] Interrupt enable for GPIO 41                                       */
9129       __IOM uint32_t OUTCFG41   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 41                              */
9130       __IOM uint32_t DS41       : 2;            /*!< [11..10] Drive strength selection for GPIO 41                             */
9131       __IOM uint32_t SR41       : 1;            /*!< [12..12] Configure the slew rate                                          */
9132       __IOM uint32_t PULLCFG41  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 41                        */
9133       __IOM uint32_t NCESRC41   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 41, DISP control signals
9134                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9135                                                      field                                                                     */
9136       __IOM uint32_t NCEPOL41   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 41                              */
9137             uint32_t            : 3;
9138       __IOM uint32_t FIEN41     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9139                                                      Otherwise the selected function will enable the input only
9140                                                      when needed                                                               */
9141       __IOM uint32_t FOEN41     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9142                                                      Otherwise the selected function will enable the output
9143                                                      only when needed                                                          */
9144             uint32_t            : 4;
9145     } PINCFG41_b;
9146   } ;
9147 
9148   union {
9149     __IOM uint32_t PINCFG42;                    /*!< (@ 0x000000A8) Controls the operation of GPIO pin 42.                     */
9150 
9151     struct {
9152       __IOM uint32_t FNCSEL42   : 4;            /*!< [3..0] Function select for GPIO pin 42                                    */
9153       __IOM uint32_t INPEN42    : 1;            /*!< [4..4] Input enable for GPIO 42                                           */
9154       __IOM uint32_t RDZERO42   : 1;            /*!< [5..5] Return 0 for read data on GPIO 42                                  */
9155       __IOM uint32_t IRPTEN42   : 2;            /*!< [7..6] Interrupt enable for GPIO 42                                       */
9156       __IOM uint32_t OUTCFG42   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 42                              */
9157       __IOM uint32_t DS42       : 2;            /*!< [11..10] Drive strength selection for GPIO 42                             */
9158       __IOM uint32_t SR42       : 1;            /*!< [12..12] Configure the slew rate                                          */
9159       __IOM uint32_t PULLCFG42  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 42                        */
9160       __IOM uint32_t NCESRC42   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 42, DISP control signals
9161                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9162                                                      field                                                                     */
9163       __IOM uint32_t NCEPOL42   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 42                              */
9164             uint32_t            : 3;
9165       __IOM uint32_t FIEN42     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9166                                                      Otherwise the selected function will enable the input only
9167                                                      when needed                                                               */
9168       __IOM uint32_t FOEN42     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9169                                                      Otherwise the selected function will enable the output
9170                                                      only when needed                                                          */
9171             uint32_t            : 4;
9172     } PINCFG42_b;
9173   } ;
9174 
9175   union {
9176     __IOM uint32_t PINCFG43;                    /*!< (@ 0x000000AC) Controls the operation of GPIO pin 43.                     */
9177 
9178     struct {
9179       __IOM uint32_t FNCSEL43   : 4;            /*!< [3..0] Function select for GPIO pin 43                                    */
9180       __IOM uint32_t INPEN43    : 1;            /*!< [4..4] Input enable for GPIO 43                                           */
9181       __IOM uint32_t RDZERO43   : 1;            /*!< [5..5] Return 0 for read data on GPIO 43                                  */
9182       __IOM uint32_t IRPTEN43   : 2;            /*!< [7..6] Interrupt enable for GPIO 43                                       */
9183       __IOM uint32_t OUTCFG43   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 43                              */
9184       __IOM uint32_t DS43       : 2;            /*!< [11..10] Drive strength selection for GPIO 43                             */
9185       __IOM uint32_t SR43       : 1;            /*!< [12..12] Configure the slew rate                                          */
9186       __IOM uint32_t PULLCFG43  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 43                        */
9187       __IOM uint32_t NCESRC43   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 43, DISP control signals
9188                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9189                                                      field                                                                     */
9190       __IOM uint32_t NCEPOL43   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 43                              */
9191             uint32_t            : 3;
9192       __IOM uint32_t FIEN43     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9193                                                      Otherwise the selected function will enable the input only
9194                                                      when needed                                                               */
9195       __IOM uint32_t FOEN43     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9196                                                      Otherwise the selected function will enable the output
9197                                                      only when needed                                                          */
9198             uint32_t            : 4;
9199     } PINCFG43_b;
9200   } ;
9201 
9202   union {
9203     __IOM uint32_t PINCFG44;                    /*!< (@ 0x000000B0) Controls the operation of GPIO pin 44.                     */
9204 
9205     struct {
9206       __IOM uint32_t FNCSEL44   : 4;            /*!< [3..0] Function select for GPIO pin 44                                    */
9207       __IOM uint32_t INPEN44    : 1;            /*!< [4..4] Input enable for GPIO 44                                           */
9208       __IOM uint32_t RDZERO44   : 1;            /*!< [5..5] Return 0 for read data on GPIO 44                                  */
9209       __IOM uint32_t IRPTEN44   : 2;            /*!< [7..6] Interrupt enable for GPIO 44                                       */
9210       __IOM uint32_t OUTCFG44   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 44                              */
9211       __IOM uint32_t DS44       : 2;            /*!< [11..10] Drive strength selection for GPIO 44                             */
9212       __IOM uint32_t SR44       : 1;            /*!< [12..12] Configure the slew rate                                          */
9213       __IOM uint32_t PULLCFG44  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 44                        */
9214       __IOM uint32_t NCESRC44   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 44, DISP control signals
9215                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9216                                                      field                                                                     */
9217       __IOM uint32_t NCEPOL44   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 44                              */
9218             uint32_t            : 3;
9219       __IOM uint32_t FIEN44     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9220                                                      Otherwise the selected function will enable the input only
9221                                                      when needed                                                               */
9222       __IOM uint32_t FOEN44     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9223                                                      Otherwise the selected function will enable the output
9224                                                      only when needed                                                          */
9225             uint32_t            : 4;
9226     } PINCFG44_b;
9227   } ;
9228 
9229   union {
9230     __IOM uint32_t PINCFG45;                    /*!< (@ 0x000000B4) Controls the operation of GPIO pin 45.                     */
9231 
9232     struct {
9233       __IOM uint32_t FNCSEL45   : 4;            /*!< [3..0] Function select for GPIO pin 45                                    */
9234       __IOM uint32_t INPEN45    : 1;            /*!< [4..4] Input enable for GPIO 45                                           */
9235       __IOM uint32_t RDZERO45   : 1;            /*!< [5..5] Return 0 for read data on GPIO 45                                  */
9236       __IOM uint32_t IRPTEN45   : 2;            /*!< [7..6] Interrupt enable for GPIO 45                                       */
9237       __IOM uint32_t OUTCFG45   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 45                              */
9238       __IOM uint32_t DS45       : 2;            /*!< [11..10] Drive strength selection for GPIO 45                             */
9239       __IOM uint32_t SR45       : 1;            /*!< [12..12] Configure the slew rate                                          */
9240       __IOM uint32_t PULLCFG45  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 45                        */
9241       __IOM uint32_t NCESRC45   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 45, DISP control signals
9242                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9243                                                      field                                                                     */
9244       __IOM uint32_t NCEPOL45   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 45                              */
9245             uint32_t            : 3;
9246       __IOM uint32_t FIEN45     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9247                                                      Otherwise the selected function will enable the input only
9248                                                      when needed                                                               */
9249       __IOM uint32_t FOEN45     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9250                                                      Otherwise the selected function will enable the output
9251                                                      only when needed                                                          */
9252             uint32_t            : 4;
9253     } PINCFG45_b;
9254   } ;
9255 
9256   union {
9257     __IOM uint32_t PINCFG46;                    /*!< (@ 0x000000B8) Controls the operation of GPIO pin 46.                     */
9258 
9259     struct {
9260       __IOM uint32_t FNCSEL46   : 4;            /*!< [3..0] Function select for GPIO pin 46                                    */
9261       __IOM uint32_t INPEN46    : 1;            /*!< [4..4] Input enable for GPIO 46                                           */
9262       __IOM uint32_t RDZERO46   : 1;            /*!< [5..5] Return 0 for read data on GPIO 46                                  */
9263       __IOM uint32_t IRPTEN46   : 2;            /*!< [7..6] Interrupt enable for GPIO 46                                       */
9264       __IOM uint32_t OUTCFG46   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 46                              */
9265       __IOM uint32_t DS46       : 2;            /*!< [11..10] Drive strength selection for GPIO 46                             */
9266       __IOM uint32_t SR46       : 1;            /*!< [12..12] Configure the slew rate                                          */
9267       __IOM uint32_t PULLCFG46  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 46                        */
9268       __IOM uint32_t NCESRC46   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 46, DISP control signals
9269                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9270                                                      field                                                                     */
9271       __IOM uint32_t NCEPOL46   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 46                              */
9272             uint32_t            : 3;
9273       __IOM uint32_t FIEN46     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9274                                                      Otherwise the selected function will enable the input only
9275                                                      when needed                                                               */
9276       __IOM uint32_t FOEN46     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9277                                                      Otherwise the selected function will enable the output
9278                                                      only when needed                                                          */
9279             uint32_t            : 4;
9280     } PINCFG46_b;
9281   } ;
9282 
9283   union {
9284     __IOM uint32_t PINCFG47;                    /*!< (@ 0x000000BC) Controls the operation of GPIO pin 47.                     */
9285 
9286     struct {
9287       __IOM uint32_t FNCSEL47   : 4;            /*!< [3..0] Function select for GPIO pin 47                                    */
9288       __IOM uint32_t INPEN47    : 1;            /*!< [4..4] Input enable for GPIO 47                                           */
9289       __IOM uint32_t RDZERO47   : 1;            /*!< [5..5] Return 0 for read data on GPIO 47                                  */
9290       __IOM uint32_t IRPTEN47   : 2;            /*!< [7..6] Interrupt enable for GPIO 47                                       */
9291       __IOM uint32_t OUTCFG47   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 47                              */
9292       __IOM uint32_t DS47       : 2;            /*!< [11..10] Drive strength selection for GPIO 47                             */
9293       __IOM uint32_t SR47       : 1;            /*!< [12..12] Configure the slew rate                                          */
9294       __IOM uint32_t PULLCFG47  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 47                        */
9295       __IOM uint32_t NCESRC47   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 47, DISP control signals
9296                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9297                                                      field                                                                     */
9298       __IOM uint32_t NCEPOL47   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 47                              */
9299             uint32_t            : 3;
9300       __IOM uint32_t FIEN47     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9301                                                      Otherwise the selected function will enable the input only
9302                                                      when needed                                                               */
9303       __IOM uint32_t FOEN47     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9304                                                      Otherwise the selected function will enable the output
9305                                                      only when needed                                                          */
9306             uint32_t            : 4;
9307     } PINCFG47_b;
9308   } ;
9309 
9310   union {
9311     __IOM uint32_t PINCFG48;                    /*!< (@ 0x000000C0) Controls the operation of GPIO pin 48.                     */
9312 
9313     struct {
9314       __IOM uint32_t FNCSEL48   : 4;            /*!< [3..0] Function select for GPIO pin 48                                    */
9315       __IOM uint32_t INPEN48    : 1;            /*!< [4..4] Input enable for GPIO 48                                           */
9316       __IOM uint32_t RDZERO48   : 1;            /*!< [5..5] Return 0 for read data on GPIO 48                                  */
9317       __IOM uint32_t IRPTEN48   : 2;            /*!< [7..6] Interrupt enable for GPIO 48                                       */
9318       __IOM uint32_t OUTCFG48   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 48                              */
9319       __IOM uint32_t DS48       : 2;            /*!< [11..10] Drive strength selection for GPIO 48                             */
9320       __IOM uint32_t SR48       : 1;            /*!< [12..12] Configure the slew rate                                          */
9321       __IOM uint32_t PULLCFG48  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 48                        */
9322       __IOM uint32_t NCESRC48   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 48, DISP control signals
9323                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9324                                                      field                                                                     */
9325       __IOM uint32_t NCEPOL48   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 48                              */
9326             uint32_t            : 3;
9327       __IOM uint32_t FIEN48     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9328                                                      Otherwise the selected function will enable the input only
9329                                                      when needed                                                               */
9330       __IOM uint32_t FOEN48     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9331                                                      Otherwise the selected function will enable the output
9332                                                      only when needed                                                          */
9333             uint32_t            : 4;
9334     } PINCFG48_b;
9335   } ;
9336 
9337   union {
9338     __IOM uint32_t PINCFG49;                    /*!< (@ 0x000000C4) Controls the operation of GPIO pin 49.                     */
9339 
9340     struct {
9341       __IOM uint32_t FNCSEL49   : 4;            /*!< [3..0] Function select for GPIO pin 49                                    */
9342       __IOM uint32_t INPEN49    : 1;            /*!< [4..4] Input enable for GPIO 49                                           */
9343       __IOM uint32_t RDZERO49   : 1;            /*!< [5..5] Return 0 for read data on GPIO 49                                  */
9344       __IOM uint32_t IRPTEN49   : 2;            /*!< [7..6] Interrupt enable for GPIO 49                                       */
9345       __IOM uint32_t OUTCFG49   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 49                              */
9346       __IOM uint32_t DS49       : 2;            /*!< [11..10] Drive strength selection for GPIO 49                             */
9347       __IOM uint32_t SR49       : 1;            /*!< [12..12] Configure the slew rate                                          */
9348       __IOM uint32_t PULLCFG49  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 49                        */
9349       __IOM uint32_t NCESRC49   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 49, DISP control signals
9350                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9351                                                      field                                                                     */
9352       __IOM uint32_t NCEPOL49   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 49                              */
9353             uint32_t            : 3;
9354       __IOM uint32_t FIEN49     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9355                                                      Otherwise the selected function will enable the input only
9356                                                      when needed                                                               */
9357       __IOM uint32_t FOEN49     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9358                                                      Otherwise the selected function will enable the output
9359                                                      only when needed                                                          */
9360             uint32_t            : 4;
9361     } PINCFG49_b;
9362   } ;
9363 
9364   union {
9365     __IOM uint32_t PINCFG50;                    /*!< (@ 0x000000C8) Controls the operation of GPIO pin 50.                     */
9366 
9367     struct {
9368       __IOM uint32_t FNCSEL50   : 4;            /*!< [3..0] Function select for GPIO pin 50                                    */
9369       __IOM uint32_t INPEN50    : 1;            /*!< [4..4] Input enable for GPIO 50                                           */
9370       __IOM uint32_t RDZERO50   : 1;            /*!< [5..5] Return 0 for read data on GPIO 50                                  */
9371       __IOM uint32_t IRPTEN50   : 2;            /*!< [7..6] Interrupt enable for GPIO 50                                       */
9372       __IOM uint32_t OUTCFG50   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 50                              */
9373       __IOM uint32_t DS50       : 2;            /*!< [11..10] Drive strength selection for GPIO 50                             */
9374       __IOM uint32_t SR50       : 1;            /*!< [12..12] Configure the slew rate                                          */
9375       __IOM uint32_t PULLCFG50  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 50                        */
9376       __IOM uint32_t NCESRC50   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 50, DISP control signals
9377                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9378                                                      field                                                                     */
9379       __IOM uint32_t NCEPOL50   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 50                              */
9380             uint32_t            : 3;
9381       __IOM uint32_t FIEN50     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9382                                                      Otherwise the selected function will enable the input only
9383                                                      when needed                                                               */
9384       __IOM uint32_t FOEN50     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9385                                                      Otherwise the selected function will enable the output
9386                                                      only when needed                                                          */
9387             uint32_t            : 4;
9388     } PINCFG50_b;
9389   } ;
9390 
9391   union {
9392     __IOM uint32_t PINCFG51;                    /*!< (@ 0x000000CC) Controls the operation of GPIO pin 51.                     */
9393 
9394     struct {
9395       __IOM uint32_t FNCSEL51   : 4;            /*!< [3..0] Function select for GPIO pin 51                                    */
9396       __IOM uint32_t INPEN51    : 1;            /*!< [4..4] Input enable for GPIO 51                                           */
9397       __IOM uint32_t RDZERO51   : 1;            /*!< [5..5] Return 0 for read data on GPIO 51                                  */
9398       __IOM uint32_t IRPTEN51   : 2;            /*!< [7..6] Interrupt enable for GPIO 51                                       */
9399       __IOM uint32_t OUTCFG51   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 51                              */
9400       __IOM uint32_t DS51       : 2;            /*!< [11..10] Drive strength selection for GPIO 51                             */
9401       __IOM uint32_t SR51       : 1;            /*!< [12..12] Configure the slew rate                                          */
9402       __IOM uint32_t PULLCFG51  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 51                        */
9403       __IOM uint32_t NCESRC51   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 51, DISP control signals
9404                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9405                                                      field                                                                     */
9406       __IOM uint32_t NCEPOL51   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 51                              */
9407             uint32_t            : 3;
9408       __IOM uint32_t FIEN51     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9409                                                      Otherwise the selected function will enable the input only
9410                                                      when needed                                                               */
9411       __IOM uint32_t FOEN51     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9412                                                      Otherwise the selected function will enable the output
9413                                                      only when needed                                                          */
9414             uint32_t            : 4;
9415     } PINCFG51_b;
9416   } ;
9417 
9418   union {
9419     __IOM uint32_t PINCFG52;                    /*!< (@ 0x000000D0) Controls the operation of GPIO pin 52.                     */
9420 
9421     struct {
9422       __IOM uint32_t FNCSEL52   : 4;            /*!< [3..0] Function select for GPIO pin 52                                    */
9423       __IOM uint32_t INPEN52    : 1;            /*!< [4..4] Input enable for GPIO 52                                           */
9424       __IOM uint32_t RDZERO52   : 1;            /*!< [5..5] Return 0 for read data on GPIO 52                                  */
9425       __IOM uint32_t IRPTEN52   : 2;            /*!< [7..6] Interrupt enable for GPIO 52                                       */
9426       __IOM uint32_t OUTCFG52   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 52                              */
9427       __IOM uint32_t DS52       : 2;            /*!< [11..10] Drive strength selection for GPIO 52                             */
9428       __IOM uint32_t SR52       : 1;            /*!< [12..12] Configure the slew rate                                          */
9429       __IOM uint32_t PULLCFG52  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 52                        */
9430       __IOM uint32_t NCESRC52   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 52, DISP control signals
9431                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9432                                                      field                                                                     */
9433       __IOM uint32_t NCEPOL52   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 52                              */
9434             uint32_t            : 3;
9435       __IOM uint32_t FIEN52     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9436                                                      Otherwise the selected function will enable the input only
9437                                                      when needed                                                               */
9438       __IOM uint32_t FOEN52     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9439                                                      Otherwise the selected function will enable the output
9440                                                      only when needed                                                          */
9441             uint32_t            : 4;
9442     } PINCFG52_b;
9443   } ;
9444 
9445   union {
9446     __IOM uint32_t PINCFG53;                    /*!< (@ 0x000000D4) Controls the operation of GPIO pin 53.                     */
9447 
9448     struct {
9449       __IOM uint32_t FNCSEL53   : 4;            /*!< [3..0] Function select for GPIO pin 53                                    */
9450       __IOM uint32_t INPEN53    : 1;            /*!< [4..4] Input enable for GPIO 53                                           */
9451       __IOM uint32_t RDZERO53   : 1;            /*!< [5..5] Return 0 for read data on GPIO 53                                  */
9452       __IOM uint32_t IRPTEN53   : 2;            /*!< [7..6] Interrupt enable for GPIO 53                                       */
9453       __IOM uint32_t OUTCFG53   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 53                              */
9454       __IOM uint32_t DS53       : 2;            /*!< [11..10] Drive strength selection for GPIO 53                             */
9455       __IOM uint32_t SR53       : 1;            /*!< [12..12] Configure the slew rate                                          */
9456       __IOM uint32_t PULLCFG53  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 53                        */
9457       __IOM uint32_t NCESRC53   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 53, DISP control signals
9458                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9459                                                      field                                                                     */
9460       __IOM uint32_t NCEPOL53   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 53                              */
9461             uint32_t            : 3;
9462       __IOM uint32_t FIEN53     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9463                                                      Otherwise the selected function will enable the input only
9464                                                      when needed                                                               */
9465       __IOM uint32_t FOEN53     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9466                                                      Otherwise the selected function will enable the output
9467                                                      only when needed                                                          */
9468             uint32_t            : 4;
9469     } PINCFG53_b;
9470   } ;
9471 
9472   union {
9473     __IOM uint32_t PINCFG54;                    /*!< (@ 0x000000D8) Controls the operation of GPIO pin 54.                     */
9474 
9475     struct {
9476       __IOM uint32_t FNCSEL54   : 4;            /*!< [3..0] Function select for GPIO pin 54                                    */
9477       __IOM uint32_t INPEN54    : 1;            /*!< [4..4] Input enable for GPIO 54                                           */
9478       __IOM uint32_t RDZERO54   : 1;            /*!< [5..5] Return 0 for read data on GPIO 54                                  */
9479       __IOM uint32_t IRPTEN54   : 2;            /*!< [7..6] Interrupt enable for GPIO 54                                       */
9480       __IOM uint32_t OUTCFG54   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 54                              */
9481       __IOM uint32_t DS54       : 2;            /*!< [11..10] Drive strength selection for GPIO 54                             */
9482       __IOM uint32_t SR54       : 1;            /*!< [12..12] Configure the slew rate                                          */
9483       __IOM uint32_t PULLCFG54  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 54                        */
9484       __IOM uint32_t NCESRC54   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 54, DISP control signals
9485                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9486                                                      field                                                                     */
9487       __IOM uint32_t NCEPOL54   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 54                              */
9488             uint32_t            : 3;
9489       __IOM uint32_t FIEN54     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9490                                                      Otherwise the selected function will enable the input only
9491                                                      when needed                                                               */
9492       __IOM uint32_t FOEN54     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9493                                                      Otherwise the selected function will enable the output
9494                                                      only when needed                                                          */
9495             uint32_t            : 4;
9496     } PINCFG54_b;
9497   } ;
9498 
9499   union {
9500     __IOM uint32_t PINCFG55;                    /*!< (@ 0x000000DC) Controls the operation of GPIO pin 55.                     */
9501 
9502     struct {
9503       __IOM uint32_t FNCSEL55   : 4;            /*!< [3..0] Function select for GPIO pin 55                                    */
9504       __IOM uint32_t INPEN55    : 1;            /*!< [4..4] Input enable for GPIO 55                                           */
9505       __IOM uint32_t RDZERO55   : 1;            /*!< [5..5] Return 0 for read data on GPIO 55                                  */
9506       __IOM uint32_t IRPTEN55   : 2;            /*!< [7..6] Interrupt enable for GPIO 55                                       */
9507       __IOM uint32_t OUTCFG55   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 55                              */
9508       __IOM uint32_t DS55       : 2;            /*!< [11..10] Drive strength selection for GPIO 55                             */
9509       __IOM uint32_t SR55       : 1;            /*!< [12..12] Configure the slew rate                                          */
9510       __IOM uint32_t PULLCFG55  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 55                        */
9511       __IOM uint32_t NCESRC55   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 55, DISP control signals
9512                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9513                                                      field                                                                     */
9514       __IOM uint32_t NCEPOL55   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 55                              */
9515             uint32_t            : 3;
9516       __IOM uint32_t FIEN55     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9517                                                      Otherwise the selected function will enable the input only
9518                                                      when needed                                                               */
9519       __IOM uint32_t FOEN55     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9520                                                      Otherwise the selected function will enable the output
9521                                                      only when needed                                                          */
9522             uint32_t            : 4;
9523     } PINCFG55_b;
9524   } ;
9525 
9526   union {
9527     __IOM uint32_t PINCFG56;                    /*!< (@ 0x000000E0) Controls the operation of GPIO pin 56.                     */
9528 
9529     struct {
9530       __IOM uint32_t FNCSEL56   : 4;            /*!< [3..0] Function select for GPIO pin 56                                    */
9531       __IOM uint32_t INPEN56    : 1;            /*!< [4..4] Input enable for GPIO 56                                           */
9532       __IOM uint32_t RDZERO56   : 1;            /*!< [5..5] Return 0 for read data on GPIO 56                                  */
9533       __IOM uint32_t IRPTEN56   : 2;            /*!< [7..6] Interrupt enable for GPIO 56                                       */
9534       __IOM uint32_t OUTCFG56   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 56                              */
9535       __IOM uint32_t DS56       : 2;            /*!< [11..10] Drive strength selection for GPIO 56                             */
9536       __IOM uint32_t SR56       : 1;            /*!< [12..12] Configure the slew rate                                          */
9537       __IOM uint32_t PULLCFG56  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 56                        */
9538       __IOM uint32_t NCESRC56   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 56, DISP control signals
9539                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9540                                                      field                                                                     */
9541       __IOM uint32_t NCEPOL56   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 56                              */
9542             uint32_t            : 3;
9543       __IOM uint32_t FIEN56     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9544                                                      Otherwise the selected function will enable the input only
9545                                                      when needed                                                               */
9546       __IOM uint32_t FOEN56     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9547                                                      Otherwise the selected function will enable the output
9548                                                      only when needed                                                          */
9549             uint32_t            : 4;
9550     } PINCFG56_b;
9551   } ;
9552 
9553   union {
9554     __IOM uint32_t PINCFG57;                    /*!< (@ 0x000000E4) Controls the operation of GPIO pin 57.                     */
9555 
9556     struct {
9557       __IOM uint32_t FNCSEL57   : 4;            /*!< [3..0] Function select for GPIO pin 57                                    */
9558       __IOM uint32_t INPEN57    : 1;            /*!< [4..4] Input enable for GPIO 57                                           */
9559       __IOM uint32_t RDZERO57   : 1;            /*!< [5..5] Return 0 for read data on GPIO 57                                  */
9560       __IOM uint32_t IRPTEN57   : 2;            /*!< [7..6] Interrupt enable for GPIO 57                                       */
9561       __IOM uint32_t OUTCFG57   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 57                              */
9562       __IOM uint32_t DS57       : 2;            /*!< [11..10] Drive strength selection for GPIO 57                             */
9563       __IOM uint32_t SR57       : 1;            /*!< [12..12] Configure the slew rate                                          */
9564       __IOM uint32_t PULLCFG57  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 57                        */
9565       __IOM uint32_t NCESRC57   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 57, DISP control signals
9566                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9567                                                      field                                                                     */
9568       __IOM uint32_t NCEPOL57   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 57                              */
9569             uint32_t            : 3;
9570       __IOM uint32_t FIEN57     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9571                                                      Otherwise the selected function will enable the input only
9572                                                      when needed                                                               */
9573       __IOM uint32_t FOEN57     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9574                                                      Otherwise the selected function will enable the output
9575                                                      only when needed                                                          */
9576             uint32_t            : 4;
9577     } PINCFG57_b;
9578   } ;
9579 
9580   union {
9581     __IOM uint32_t PINCFG58;                    /*!< (@ 0x000000E8) Controls the operation of GPIO pin 58.                     */
9582 
9583     struct {
9584       __IOM uint32_t FNCSEL58   : 4;            /*!< [3..0] Function select for GPIO pin 58                                    */
9585       __IOM uint32_t INPEN58    : 1;            /*!< [4..4] Input enable for GPIO 58                                           */
9586       __IOM uint32_t RDZERO58   : 1;            /*!< [5..5] Return 0 for read data on GPIO 58                                  */
9587       __IOM uint32_t IRPTEN58   : 2;            /*!< [7..6] Interrupt enable for GPIO 58                                       */
9588       __IOM uint32_t OUTCFG58   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 58                              */
9589       __IOM uint32_t DS58       : 2;            /*!< [11..10] Drive strength selection for GPIO 58                             */
9590       __IOM uint32_t SR58       : 1;            /*!< [12..12] Configure the slew rate                                          */
9591       __IOM uint32_t PULLCFG58  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 58                        */
9592       __IOM uint32_t NCESRC58   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 58, DISP control signals
9593                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9594                                                      field                                                                     */
9595       __IOM uint32_t NCEPOL58   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 58                              */
9596             uint32_t            : 3;
9597       __IOM uint32_t FIEN58     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9598                                                      Otherwise the selected function will enable the input only
9599                                                      when needed                                                               */
9600       __IOM uint32_t FOEN58     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9601                                                      Otherwise the selected function will enable the output
9602                                                      only when needed                                                          */
9603             uint32_t            : 4;
9604     } PINCFG58_b;
9605   } ;
9606 
9607   union {
9608     __IOM uint32_t PINCFG59;                    /*!< (@ 0x000000EC) Controls the operation of GPIO pin 59.                     */
9609 
9610     struct {
9611       __IOM uint32_t FNCSEL59   : 4;            /*!< [3..0] Function select for GPIO pin 59                                    */
9612       __IOM uint32_t INPEN59    : 1;            /*!< [4..4] Input enable for GPIO 59                                           */
9613       __IOM uint32_t RDZERO59   : 1;            /*!< [5..5] Return 0 for read data on GPIO 59                                  */
9614       __IOM uint32_t IRPTEN59   : 2;            /*!< [7..6] Interrupt enable for GPIO 59                                       */
9615       __IOM uint32_t OUTCFG59   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 59                              */
9616       __IOM uint32_t DS59       : 2;            /*!< [11..10] Drive strength selection for GPIO 59                             */
9617       __IOM uint32_t SR59       : 1;            /*!< [12..12] Configure the slew rate                                          */
9618       __IOM uint32_t PULLCFG59  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 59                        */
9619       __IOM uint32_t NCESRC59   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 59, DISP control signals
9620                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9621                                                      field                                                                     */
9622       __IOM uint32_t NCEPOL59   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 59                              */
9623             uint32_t            : 3;
9624       __IOM uint32_t FIEN59     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9625                                                      Otherwise the selected function will enable the input only
9626                                                      when needed                                                               */
9627       __IOM uint32_t FOEN59     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9628                                                      Otherwise the selected function will enable the output
9629                                                      only when needed                                                          */
9630             uint32_t            : 4;
9631     } PINCFG59_b;
9632   } ;
9633 
9634   union {
9635     __IOM uint32_t PINCFG60;                    /*!< (@ 0x000000F0) Controls the operation of GPIO pin 60.                     */
9636 
9637     struct {
9638       __IOM uint32_t FNCSEL60   : 4;            /*!< [3..0] Function select for GPIO pin 60                                    */
9639       __IOM uint32_t INPEN60    : 1;            /*!< [4..4] Input enable for GPIO 60                                           */
9640       __IOM uint32_t RDZERO60   : 1;            /*!< [5..5] Return 0 for read data on GPIO 60                                  */
9641       __IOM uint32_t IRPTEN60   : 2;            /*!< [7..6] Interrupt enable for GPIO 60                                       */
9642       __IOM uint32_t OUTCFG60   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 60                              */
9643       __IOM uint32_t DS60       : 2;            /*!< [11..10] Drive strength selection for GPIO 60                             */
9644       __IOM uint32_t SR60       : 1;            /*!< [12..12] Configure the slew rate                                          */
9645       __IOM uint32_t PULLCFG60  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 60                        */
9646       __IOM uint32_t NCESRC60   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 60, DISP control signals
9647                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9648                                                      field                                                                     */
9649       __IOM uint32_t NCEPOL60   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 60                              */
9650             uint32_t            : 3;
9651       __IOM uint32_t FIEN60     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9652                                                      Otherwise the selected function will enable the input only
9653                                                      when needed                                                               */
9654       __IOM uint32_t FOEN60     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9655                                                      Otherwise the selected function will enable the output
9656                                                      only when needed                                                          */
9657             uint32_t            : 4;
9658     } PINCFG60_b;
9659   } ;
9660 
9661   union {
9662     __IOM uint32_t PINCFG61;                    /*!< (@ 0x000000F4) Controls the operation of GPIO pin 61.                     */
9663 
9664     struct {
9665       __IOM uint32_t FNCSEL61   : 4;            /*!< [3..0] Function select for GPIO pin 61                                    */
9666       __IOM uint32_t INPEN61    : 1;            /*!< [4..4] Input enable for GPIO 61                                           */
9667       __IOM uint32_t RDZERO61   : 1;            /*!< [5..5] Return 0 for read data on GPIO 61                                  */
9668       __IOM uint32_t IRPTEN61   : 2;            /*!< [7..6] Interrupt enable for GPIO 61                                       */
9669       __IOM uint32_t OUTCFG61   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 61                              */
9670       __IOM uint32_t DS61       : 2;            /*!< [11..10] Drive strength selection for GPIO 61                             */
9671       __IOM uint32_t SR61       : 1;            /*!< [12..12] Configure the slew rate                                          */
9672       __IOM uint32_t PULLCFG61  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 61                        */
9673       __IOM uint32_t NCESRC61   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 61, DISP control signals
9674                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9675                                                      field                                                                     */
9676       __IOM uint32_t NCEPOL61   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 61                              */
9677             uint32_t            : 3;
9678       __IOM uint32_t FIEN61     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9679                                                      Otherwise the selected function will enable the input only
9680                                                      when needed                                                               */
9681       __IOM uint32_t FOEN61     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9682                                                      Otherwise the selected function will enable the output
9683                                                      only when needed                                                          */
9684             uint32_t            : 4;
9685     } PINCFG61_b;
9686   } ;
9687 
9688   union {
9689     __IOM uint32_t PINCFG62;                    /*!< (@ 0x000000F8) Controls the operation of GPIO pin 62.                     */
9690 
9691     struct {
9692       __IOM uint32_t FNCSEL62   : 4;            /*!< [3..0] Function select for GPIO pin 62                                    */
9693       __IOM uint32_t INPEN62    : 1;            /*!< [4..4] Input enable for GPIO 62                                           */
9694       __IOM uint32_t RDZERO62   : 1;            /*!< [5..5] Return 0 for read data on GPIO 62                                  */
9695       __IOM uint32_t IRPTEN62   : 2;            /*!< [7..6] Interrupt enable for GPIO 62                                       */
9696       __IOM uint32_t OUTCFG62   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 62                              */
9697       __IOM uint32_t DS62       : 2;            /*!< [11..10] Drive strength selection for GPIO 62                             */
9698       __IOM uint32_t SR62       : 1;            /*!< [12..12] Configure the slew rate                                          */
9699       __IOM uint32_t PULLCFG62  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 62                        */
9700       __IOM uint32_t NCESRC62   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 62, DISP control signals
9701                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9702                                                      field                                                                     */
9703       __IOM uint32_t NCEPOL62   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 62                              */
9704             uint32_t            : 3;
9705       __IOM uint32_t FIEN62     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9706                                                      Otherwise the selected function will enable the input only
9707                                                      when needed                                                               */
9708       __IOM uint32_t FOEN62     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9709                                                      Otherwise the selected function will enable the output
9710                                                      only when needed                                                          */
9711             uint32_t            : 4;
9712     } PINCFG62_b;
9713   } ;
9714 
9715   union {
9716     __IOM uint32_t PINCFG63;                    /*!< (@ 0x000000FC) Controls the operation of GPIO pin 63.                     */
9717 
9718     struct {
9719       __IOM uint32_t FNCSEL63   : 4;            /*!< [3..0] Function select for GPIO pin 63                                    */
9720       __IOM uint32_t INPEN63    : 1;            /*!< [4..4] Input enable for GPIO 63                                           */
9721       __IOM uint32_t RDZERO63   : 1;            /*!< [5..5] Return 0 for read data on GPIO 63                                  */
9722       __IOM uint32_t IRPTEN63   : 2;            /*!< [7..6] Interrupt enable for GPIO 63                                       */
9723       __IOM uint32_t OUTCFG63   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 63                              */
9724       __IOM uint32_t DS63       : 2;            /*!< [11..10] Drive strength selection for GPIO 63                             */
9725       __IOM uint32_t SR63       : 1;            /*!< [12..12] Configure the slew rate                                          */
9726       __IOM uint32_t PULLCFG63  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 63                        */
9727       __IOM uint32_t NCESRC63   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 63, DISP control signals
9728                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9729                                                      field                                                                     */
9730       __IOM uint32_t NCEPOL63   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 63                              */
9731             uint32_t            : 3;
9732       __IOM uint32_t FIEN63     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9733                                                      Otherwise the selected function will enable the input only
9734                                                      when needed                                                               */
9735       __IOM uint32_t FOEN63     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9736                                                      Otherwise the selected function will enable the output
9737                                                      only when needed                                                          */
9738             uint32_t            : 4;
9739     } PINCFG63_b;
9740   } ;
9741 
9742   union {
9743     __IOM uint32_t PINCFG64;                    /*!< (@ 0x00000100) Controls the operation of GPIO pin 64.                     */
9744 
9745     struct {
9746       __IOM uint32_t FNCSEL64   : 4;            /*!< [3..0] Function select for GPIO pin 64                                    */
9747       __IOM uint32_t INPEN64    : 1;            /*!< [4..4] Input enable for GPIO 64                                           */
9748       __IOM uint32_t RDZERO64   : 1;            /*!< [5..5] Return 0 for read data on GPIO 64                                  */
9749       __IOM uint32_t IRPTEN64   : 2;            /*!< [7..6] Interrupt enable for GPIO 64                                       */
9750       __IOM uint32_t OUTCFG64   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 64                              */
9751       __IOM uint32_t DS64       : 2;            /*!< [11..10] Drive strength selection for GPIO 64                             */
9752       __IOM uint32_t SR64       : 1;            /*!< [12..12] Configure the slew rate                                          */
9753       __IOM uint32_t PULLCFG64  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 64                        */
9754       __IOM uint32_t NCESRC64   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 64, DISP control signals
9755                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9756                                                      field                                                                     */
9757       __IOM uint32_t NCEPOL64   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 64                              */
9758             uint32_t            : 3;
9759       __IOM uint32_t FIEN64     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9760                                                      Otherwise the selected function will enable the input only
9761                                                      when needed                                                               */
9762       __IOM uint32_t FOEN64     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9763                                                      Otherwise the selected function will enable the output
9764                                                      only when needed                                                          */
9765             uint32_t            : 4;
9766     } PINCFG64_b;
9767   } ;
9768 
9769   union {
9770     __IOM uint32_t PINCFG65;                    /*!< (@ 0x00000104) Controls the operation of GPIO pin 65.                     */
9771 
9772     struct {
9773       __IOM uint32_t FNCSEL65   : 4;            /*!< [3..0] Function select for GPIO pin 65                                    */
9774       __IOM uint32_t INPEN65    : 1;            /*!< [4..4] Input enable for GPIO 65                                           */
9775       __IOM uint32_t RDZERO65   : 1;            /*!< [5..5] Return 0 for read data on GPIO 65                                  */
9776       __IOM uint32_t IRPTEN65   : 2;            /*!< [7..6] Interrupt enable for GPIO 65                                       */
9777       __IOM uint32_t OUTCFG65   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 65                              */
9778       __IOM uint32_t DS65       : 2;            /*!< [11..10] Drive strength selection for GPIO 65                             */
9779       __IOM uint32_t SR65       : 1;            /*!< [12..12] Configure the slew rate                                          */
9780       __IOM uint32_t PULLCFG65  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 65                        */
9781       __IOM uint32_t NCESRC65   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 65, DISP control signals
9782                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9783                                                      field                                                                     */
9784       __IOM uint32_t NCEPOL65   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 65                              */
9785             uint32_t            : 3;
9786       __IOM uint32_t FIEN65     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9787                                                      Otherwise the selected function will enable the input only
9788                                                      when needed                                                               */
9789       __IOM uint32_t FOEN65     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9790                                                      Otherwise the selected function will enable the output
9791                                                      only when needed                                                          */
9792             uint32_t            : 4;
9793     } PINCFG65_b;
9794   } ;
9795 
9796   union {
9797     __IOM uint32_t PINCFG66;                    /*!< (@ 0x00000108) Controls the operation of GPIO pin 66.                     */
9798 
9799     struct {
9800       __IOM uint32_t FNCSEL66   : 4;            /*!< [3..0] Function select for GPIO pin 66                                    */
9801       __IOM uint32_t INPEN66    : 1;            /*!< [4..4] Input enable for GPIO 66                                           */
9802       __IOM uint32_t RDZERO66   : 1;            /*!< [5..5] Return 0 for read data on GPIO 66                                  */
9803       __IOM uint32_t IRPTEN66   : 2;            /*!< [7..6] Interrupt enable for GPIO 66                                       */
9804       __IOM uint32_t OUTCFG66   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 66                              */
9805       __IOM uint32_t DS66       : 2;            /*!< [11..10] Drive strength selection for GPIO 66                             */
9806       __IOM uint32_t SR66       : 1;            /*!< [12..12] Configure the slew rate                                          */
9807       __IOM uint32_t PULLCFG66  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 66                        */
9808       __IOM uint32_t NCESRC66   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 66, DISP control signals
9809                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9810                                                      field                                                                     */
9811       __IOM uint32_t NCEPOL66   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 66                              */
9812             uint32_t            : 3;
9813       __IOM uint32_t FIEN66     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9814                                                      Otherwise the selected function will enable the input only
9815                                                      when needed                                                               */
9816       __IOM uint32_t FOEN66     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9817                                                      Otherwise the selected function will enable the output
9818                                                      only when needed                                                          */
9819             uint32_t            : 4;
9820     } PINCFG66_b;
9821   } ;
9822 
9823   union {
9824     __IOM uint32_t PINCFG67;                    /*!< (@ 0x0000010C) Controls the operation of GPIO pin 67.                     */
9825 
9826     struct {
9827       __IOM uint32_t FNCSEL67   : 4;            /*!< [3..0] Function select for GPIO pin 67                                    */
9828       __IOM uint32_t INPEN67    : 1;            /*!< [4..4] Input enable for GPIO 67                                           */
9829       __IOM uint32_t RDZERO67   : 1;            /*!< [5..5] Return 0 for read data on GPIO 67                                  */
9830       __IOM uint32_t IRPTEN67   : 2;            /*!< [7..6] Interrupt enable for GPIO 67                                       */
9831       __IOM uint32_t OUTCFG67   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 67                              */
9832       __IOM uint32_t DS67       : 2;            /*!< [11..10] Drive strength selection for GPIO 67                             */
9833       __IOM uint32_t SR67       : 1;            /*!< [12..12] Configure the slew rate                                          */
9834       __IOM uint32_t PULLCFG67  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 67                        */
9835       __IOM uint32_t NCESRC67   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 67, DISP control signals
9836                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9837                                                      field                                                                     */
9838       __IOM uint32_t NCEPOL67   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 67                              */
9839             uint32_t            : 3;
9840       __IOM uint32_t FIEN67     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9841                                                      Otherwise the selected function will enable the input only
9842                                                      when needed                                                               */
9843       __IOM uint32_t FOEN67     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9844                                                      Otherwise the selected function will enable the output
9845                                                      only when needed                                                          */
9846             uint32_t            : 4;
9847     } PINCFG67_b;
9848   } ;
9849 
9850   union {
9851     __IOM uint32_t PINCFG68;                    /*!< (@ 0x00000110) Controls the operation of GPIO pin 68.                     */
9852 
9853     struct {
9854       __IOM uint32_t FNCSEL68   : 4;            /*!< [3..0] Function select for GPIO pin 68                                    */
9855       __IOM uint32_t INPEN68    : 1;            /*!< [4..4] Input enable for GPIO 68                                           */
9856       __IOM uint32_t RDZERO68   : 1;            /*!< [5..5] Return 0 for read data on GPIO 68                                  */
9857       __IOM uint32_t IRPTEN68   : 2;            /*!< [7..6] Interrupt enable for GPIO 68                                       */
9858       __IOM uint32_t OUTCFG68   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 68                              */
9859       __IOM uint32_t DS68       : 2;            /*!< [11..10] Drive strength selection for GPIO 68                             */
9860       __IOM uint32_t SR68       : 1;            /*!< [12..12] Configure the slew rate                                          */
9861       __IOM uint32_t PULLCFG68  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 68                        */
9862       __IOM uint32_t NCESRC68   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 68, DISP control signals
9863                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9864                                                      field                                                                     */
9865       __IOM uint32_t NCEPOL68   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 68                              */
9866             uint32_t            : 3;
9867       __IOM uint32_t FIEN68     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9868                                                      Otherwise the selected function will enable the input only
9869                                                      when needed                                                               */
9870       __IOM uint32_t FOEN68     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9871                                                      Otherwise the selected function will enable the output
9872                                                      only when needed                                                          */
9873             uint32_t            : 4;
9874     } PINCFG68_b;
9875   } ;
9876 
9877   union {
9878     __IOM uint32_t PINCFG69;                    /*!< (@ 0x00000114) Controls the operation of GPIO pin 69.                     */
9879 
9880     struct {
9881       __IOM uint32_t FNCSEL69   : 4;            /*!< [3..0] Function select for GPIO pin 69                                    */
9882       __IOM uint32_t INPEN69    : 1;            /*!< [4..4] Input enable for GPIO 69                                           */
9883       __IOM uint32_t RDZERO69   : 1;            /*!< [5..5] Return 0 for read data on GPIO 69                                  */
9884       __IOM uint32_t IRPTEN69   : 2;            /*!< [7..6] Interrupt enable for GPIO 69                                       */
9885       __IOM uint32_t OUTCFG69   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 69                              */
9886       __IOM uint32_t DS69       : 2;            /*!< [11..10] Drive strength selection for GPIO 69                             */
9887       __IOM uint32_t SR69       : 1;            /*!< [12..12] Configure the slew rate                                          */
9888       __IOM uint32_t PULLCFG69  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 69                        */
9889       __IOM uint32_t NCESRC69   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 69, DISP control signals
9890                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9891                                                      field                                                                     */
9892       __IOM uint32_t NCEPOL69   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 69                              */
9893             uint32_t            : 3;
9894       __IOM uint32_t FIEN69     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9895                                                      Otherwise the selected function will enable the input only
9896                                                      when needed                                                               */
9897       __IOM uint32_t FOEN69     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9898                                                      Otherwise the selected function will enable the output
9899                                                      only when needed                                                          */
9900             uint32_t            : 4;
9901     } PINCFG69_b;
9902   } ;
9903 
9904   union {
9905     __IOM uint32_t PINCFG70;                    /*!< (@ 0x00000118) Controls the operation of GPIO pin 70.                     */
9906 
9907     struct {
9908       __IOM uint32_t FNCSEL70   : 4;            /*!< [3..0] Function select for GPIO pin 70                                    */
9909       __IOM uint32_t INPEN70    : 1;            /*!< [4..4] Input enable for GPIO 70                                           */
9910       __IOM uint32_t RDZERO70   : 1;            /*!< [5..5] Return 0 for read data on GPIO 70                                  */
9911       __IOM uint32_t IRPTEN70   : 2;            /*!< [7..6] Interrupt enable for GPIO 70                                       */
9912       __IOM uint32_t OUTCFG70   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 70                              */
9913       __IOM uint32_t DS70       : 2;            /*!< [11..10] Drive strength selection for GPIO 70                             */
9914       __IOM uint32_t SR70       : 1;            /*!< [12..12] Configure the slew rate                                          */
9915       __IOM uint32_t PULLCFG70  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 70                        */
9916       __IOM uint32_t NCESRC70   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 70, DISP control signals
9917                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9918                                                      field                                                                     */
9919       __IOM uint32_t NCEPOL70   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 70                              */
9920             uint32_t            : 3;
9921       __IOM uint32_t FIEN70     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9922                                                      Otherwise the selected function will enable the input only
9923                                                      when needed                                                               */
9924       __IOM uint32_t FOEN70     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9925                                                      Otherwise the selected function will enable the output
9926                                                      only when needed                                                          */
9927             uint32_t            : 4;
9928     } PINCFG70_b;
9929   } ;
9930 
9931   union {
9932     __IOM uint32_t PINCFG71;                    /*!< (@ 0x0000011C) Controls the operation of GPIO pin 71.                     */
9933 
9934     struct {
9935       __IOM uint32_t FNCSEL71   : 4;            /*!< [3..0] Function select for GPIO pin 71                                    */
9936       __IOM uint32_t INPEN71    : 1;            /*!< [4..4] Input enable for GPIO 71                                           */
9937       __IOM uint32_t RDZERO71   : 1;            /*!< [5..5] Return 0 for read data on GPIO 71                                  */
9938       __IOM uint32_t IRPTEN71   : 2;            /*!< [7..6] Interrupt enable for GPIO 71                                       */
9939       __IOM uint32_t OUTCFG71   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 71                              */
9940       __IOM uint32_t DS71       : 2;            /*!< [11..10] Drive strength selection for GPIO 71                             */
9941       __IOM uint32_t SR71       : 1;            /*!< [12..12] Configure the slew rate                                          */
9942       __IOM uint32_t PULLCFG71  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 71                        */
9943       __IOM uint32_t NCESRC71   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 71, DISP control signals
9944                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9945                                                      field                                                                     */
9946       __IOM uint32_t NCEPOL71   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 71                              */
9947             uint32_t            : 3;
9948       __IOM uint32_t FIEN71     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9949                                                      Otherwise the selected function will enable the input only
9950                                                      when needed                                                               */
9951       __IOM uint32_t FOEN71     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9952                                                      Otherwise the selected function will enable the output
9953                                                      only when needed                                                          */
9954             uint32_t            : 4;
9955     } PINCFG71_b;
9956   } ;
9957 
9958   union {
9959     __IOM uint32_t PINCFG72;                    /*!< (@ 0x00000120) Controls the operation of GPIO pin 72.                     */
9960 
9961     struct {
9962       __IOM uint32_t FNCSEL72   : 4;            /*!< [3..0] Function select for GPIO pin 72                                    */
9963       __IOM uint32_t INPEN72    : 1;            /*!< [4..4] Input enable for GPIO 72                                           */
9964       __IOM uint32_t RDZERO72   : 1;            /*!< [5..5] Return 0 for read data on GPIO 72                                  */
9965       __IOM uint32_t IRPTEN72   : 2;            /*!< [7..6] Interrupt enable for GPIO 72                                       */
9966       __IOM uint32_t OUTCFG72   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 72                              */
9967       __IOM uint32_t DS72       : 2;            /*!< [11..10] Drive strength selection for GPIO 72                             */
9968       __IOM uint32_t SR72       : 1;            /*!< [12..12] Configure the slew rate                                          */
9969       __IOM uint32_t PULLCFG72  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 72                        */
9970       __IOM uint32_t NCESRC72   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 72, DISP control signals
9971                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9972                                                      field                                                                     */
9973       __IOM uint32_t NCEPOL72   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 72                              */
9974             uint32_t            : 3;
9975       __IOM uint32_t FIEN72     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
9976                                                      Otherwise the selected function will enable the input only
9977                                                      when needed                                                               */
9978       __IOM uint32_t FOEN72     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
9979                                                      Otherwise the selected function will enable the output
9980                                                      only when needed                                                          */
9981             uint32_t            : 4;
9982     } PINCFG72_b;
9983   } ;
9984 
9985   union {
9986     __IOM uint32_t PINCFG73;                    /*!< (@ 0x00000124) Controls the operation of GPIO pin 73.                     */
9987 
9988     struct {
9989       __IOM uint32_t FNCSEL73   : 4;            /*!< [3..0] Function select for GPIO pin 73                                    */
9990       __IOM uint32_t INPEN73    : 1;            /*!< [4..4] Input enable for GPIO 73                                           */
9991       __IOM uint32_t RDZERO73   : 1;            /*!< [5..5] Return 0 for read data on GPIO 73                                  */
9992       __IOM uint32_t IRPTEN73   : 2;            /*!< [7..6] Interrupt enable for GPIO 73                                       */
9993       __IOM uint32_t OUTCFG73   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 73                              */
9994       __IOM uint32_t DS73       : 2;            /*!< [11..10] Drive strength selection for GPIO 73                             */
9995       __IOM uint32_t SR73       : 1;            /*!< [12..12] Configure the slew rate                                          */
9996       __IOM uint32_t PULLCFG73  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 73                        */
9997       __IOM uint32_t NCESRC73   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 73, DISP control signals
9998                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
9999                                                      field                                                                     */
10000       __IOM uint32_t NCEPOL73   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 73                              */
10001             uint32_t            : 3;
10002       __IOM uint32_t FIEN73     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10003                                                      Otherwise the selected function will enable the input only
10004                                                      when needed                                                               */
10005       __IOM uint32_t FOEN73     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10006                                                      Otherwise the selected function will enable the output
10007                                                      only when needed                                                          */
10008             uint32_t            : 4;
10009     } PINCFG73_b;
10010   } ;
10011 
10012   union {
10013     __IOM uint32_t PINCFG74;                    /*!< (@ 0x00000128) Controls the operation of GPIO pin 74.                     */
10014 
10015     struct {
10016       __IOM uint32_t FNCSEL74   : 4;            /*!< [3..0] Function select for GPIO pin 74                                    */
10017       __IOM uint32_t INPEN74    : 1;            /*!< [4..4] Input enable for GPIO 74                                           */
10018       __IOM uint32_t RDZERO74   : 1;            /*!< [5..5] Return 0 for read data on GPIO 74                                  */
10019       __IOM uint32_t IRPTEN74   : 2;            /*!< [7..6] Interrupt enable for GPIO 74                                       */
10020       __IOM uint32_t OUTCFG74   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 74                              */
10021       __IOM uint32_t DS74       : 2;            /*!< [11..10] Drive strength selection for GPIO 74                             */
10022       __IOM uint32_t SR74       : 1;            /*!< [12..12] Configure the slew rate                                          */
10023       __IOM uint32_t PULLCFG74  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 74                        */
10024       __IOM uint32_t NCESRC74   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 74, DISP control signals
10025                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10026                                                      field                                                                     */
10027       __IOM uint32_t NCEPOL74   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 74                              */
10028             uint32_t            : 3;
10029       __IOM uint32_t FIEN74     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10030                                                      Otherwise the selected function will enable the input only
10031                                                      when needed                                                               */
10032       __IOM uint32_t FOEN74     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10033                                                      Otherwise the selected function will enable the output
10034                                                      only when needed                                                          */
10035             uint32_t            : 4;
10036     } PINCFG74_b;
10037   } ;
10038 
10039   union {
10040     __IOM uint32_t PINCFG75;                    /*!< (@ 0x0000012C) Controls the operation of GPIO pin 75.                     */
10041 
10042     struct {
10043       __IOM uint32_t FNCSEL75   : 4;            /*!< [3..0] Function select for GPIO pin 75                                    */
10044       __IOM uint32_t INPEN75    : 1;            /*!< [4..4] Input enable for GPIO 75                                           */
10045       __IOM uint32_t RDZERO75   : 1;            /*!< [5..5] Return 0 for read data on GPIO 75                                  */
10046       __IOM uint32_t IRPTEN75   : 2;            /*!< [7..6] Interrupt enable for GPIO 75                                       */
10047       __IOM uint32_t OUTCFG75   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 75                              */
10048       __IOM uint32_t DS75       : 2;            /*!< [11..10] Drive strength selection for GPIO 75                             */
10049       __IOM uint32_t SR75       : 1;            /*!< [12..12] Configure the slew rate                                          */
10050       __IOM uint32_t PULLCFG75  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 75                        */
10051       __IOM uint32_t NCESRC75   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 75, DISP control signals
10052                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10053                                                      field                                                                     */
10054       __IOM uint32_t NCEPOL75   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 75                              */
10055             uint32_t            : 3;
10056       __IOM uint32_t FIEN75     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10057                                                      Otherwise the selected function will enable the input only
10058                                                      when needed                                                               */
10059       __IOM uint32_t FOEN75     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10060                                                      Otherwise the selected function will enable the output
10061                                                      only when needed                                                          */
10062             uint32_t            : 4;
10063     } PINCFG75_b;
10064   } ;
10065 
10066   union {
10067     __IOM uint32_t PINCFG76;                    /*!< (@ 0x00000130) Controls the operation of GPIO pin 76.                     */
10068 
10069     struct {
10070       __IOM uint32_t FNCSEL76   : 4;            /*!< [3..0] Function select for GPIO pin 76                                    */
10071       __IOM uint32_t INPEN76    : 1;            /*!< [4..4] Input enable for GPIO 76                                           */
10072       __IOM uint32_t RDZERO76   : 1;            /*!< [5..5] Return 0 for read data on GPIO 76                                  */
10073       __IOM uint32_t IRPTEN76   : 2;            /*!< [7..6] Interrupt enable for GPIO 76                                       */
10074       __IOM uint32_t OUTCFG76   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 76                              */
10075       __IOM uint32_t DS76       : 2;            /*!< [11..10] Drive strength selection for GPIO 76                             */
10076       __IOM uint32_t SR76       : 1;            /*!< [12..12] Configure the slew rate                                          */
10077       __IOM uint32_t PULLCFG76  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 76                        */
10078       __IOM uint32_t NCESRC76   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 76, DISP control signals
10079                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10080                                                      field                                                                     */
10081       __IOM uint32_t NCEPOL76   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 76                              */
10082             uint32_t            : 3;
10083       __IOM uint32_t FIEN76     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10084                                                      Otherwise the selected function will enable the input only
10085                                                      when needed                                                               */
10086       __IOM uint32_t FOEN76     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10087                                                      Otherwise the selected function will enable the output
10088                                                      only when needed                                                          */
10089             uint32_t            : 4;
10090     } PINCFG76_b;
10091   } ;
10092 
10093   union {
10094     __IOM uint32_t PINCFG77;                    /*!< (@ 0x00000134) Controls the operation of GPIO pin 77.                     */
10095 
10096     struct {
10097       __IOM uint32_t FNCSEL77   : 4;            /*!< [3..0] Function select for GPIO pin 77                                    */
10098       __IOM uint32_t INPEN77    : 1;            /*!< [4..4] Input enable for GPIO 77                                           */
10099       __IOM uint32_t RDZERO77   : 1;            /*!< [5..5] Return 0 for read data on GPIO 77                                  */
10100       __IOM uint32_t IRPTEN77   : 2;            /*!< [7..6] Interrupt enable for GPIO 77                                       */
10101       __IOM uint32_t OUTCFG77   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 77                              */
10102       __IOM uint32_t DS77       : 2;            /*!< [11..10] Drive strength selection for GPIO 77                             */
10103       __IOM uint32_t SR77       : 1;            /*!< [12..12] Configure the slew rate                                          */
10104       __IOM uint32_t PULLCFG77  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 77                        */
10105       __IOM uint32_t NCESRC77   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 77, DISP control signals
10106                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10107                                                      field                                                                     */
10108       __IOM uint32_t NCEPOL77   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 77                              */
10109             uint32_t            : 3;
10110       __IOM uint32_t FIEN77     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10111                                                      Otherwise the selected function will enable the input only
10112                                                      when needed                                                               */
10113       __IOM uint32_t FOEN77     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10114                                                      Otherwise the selected function will enable the output
10115                                                      only when needed                                                          */
10116             uint32_t            : 4;
10117     } PINCFG77_b;
10118   } ;
10119 
10120   union {
10121     __IOM uint32_t PINCFG78;                    /*!< (@ 0x00000138) Controls the operation of GPIO pin 78.                     */
10122 
10123     struct {
10124       __IOM uint32_t FNCSEL78   : 4;            /*!< [3..0] Function select for GPIO pin 78                                    */
10125       __IOM uint32_t INPEN78    : 1;            /*!< [4..4] Input enable for GPIO 78                                           */
10126       __IOM uint32_t RDZERO78   : 1;            /*!< [5..5] Return 0 for read data on GPIO 78                                  */
10127       __IOM uint32_t IRPTEN78   : 2;            /*!< [7..6] Interrupt enable for GPIO 78                                       */
10128       __IOM uint32_t OUTCFG78   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 78                              */
10129       __IOM uint32_t DS78       : 2;            /*!< [11..10] Drive strength selection for GPIO 78                             */
10130       __IOM uint32_t SR78       : 1;            /*!< [12..12] Configure the slew rate                                          */
10131       __IOM uint32_t PULLCFG78  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 78                        */
10132       __IOM uint32_t NCESRC78   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 78, DISP control signals
10133                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10134                                                      field                                                                     */
10135       __IOM uint32_t NCEPOL78   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 78                              */
10136             uint32_t            : 3;
10137       __IOM uint32_t FIEN78     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10138                                                      Otherwise the selected function will enable the input only
10139                                                      when needed                                                               */
10140       __IOM uint32_t FOEN78     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10141                                                      Otherwise the selected function will enable the output
10142                                                      only when needed                                                          */
10143             uint32_t            : 4;
10144     } PINCFG78_b;
10145   } ;
10146 
10147   union {
10148     __IOM uint32_t PINCFG79;                    /*!< (@ 0x0000013C) Controls the operation of GPIO pin 79.                     */
10149 
10150     struct {
10151       __IOM uint32_t FNCSEL79   : 4;            /*!< [3..0] Function select for GPIO pin 79                                    */
10152       __IOM uint32_t INPEN79    : 1;            /*!< [4..4] Input enable for GPIO 79                                           */
10153       __IOM uint32_t RDZERO79   : 1;            /*!< [5..5] Return 0 for read data on GPIO 79                                  */
10154       __IOM uint32_t IRPTEN79   : 2;            /*!< [7..6] Interrupt enable for GPIO 79                                       */
10155       __IOM uint32_t OUTCFG79   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 79                              */
10156       __IOM uint32_t DS79       : 2;            /*!< [11..10] Drive strength selection for GPIO 79                             */
10157       __IOM uint32_t SR79       : 1;            /*!< [12..12] Configure the slew rate                                          */
10158       __IOM uint32_t PULLCFG79  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 79                        */
10159       __IOM uint32_t NCESRC79   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 79, DISP control signals
10160                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10161                                                      field                                                                     */
10162       __IOM uint32_t NCEPOL79   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 79                              */
10163             uint32_t            : 3;
10164       __IOM uint32_t FIEN79     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10165                                                      Otherwise the selected function will enable the input only
10166                                                      when needed                                                               */
10167       __IOM uint32_t FOEN79     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10168                                                      Otherwise the selected function will enable the output
10169                                                      only when needed                                                          */
10170             uint32_t            : 4;
10171     } PINCFG79_b;
10172   } ;
10173 
10174   union {
10175     __IOM uint32_t PINCFG80;                    /*!< (@ 0x00000140) Controls the operation of GPIO pin 80.                     */
10176 
10177     struct {
10178       __IOM uint32_t FNCSEL80   : 4;            /*!< [3..0] Function select for GPIO pin 80                                    */
10179       __IOM uint32_t INPEN80    : 1;            /*!< [4..4] Input enable for GPIO 80                                           */
10180       __IOM uint32_t RDZERO80   : 1;            /*!< [5..5] Return 0 for read data on GPIO 80                                  */
10181       __IOM uint32_t IRPTEN80   : 2;            /*!< [7..6] Interrupt enable for GPIO 80                                       */
10182       __IOM uint32_t OUTCFG80   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 80                              */
10183       __IOM uint32_t DS80       : 2;            /*!< [11..10] Drive strength selection for GPIO 80                             */
10184       __IOM uint32_t SR80       : 1;            /*!< [12..12] Configure the slew rate                                          */
10185       __IOM uint32_t PULLCFG80  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 80                        */
10186       __IOM uint32_t NCESRC80   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 80, DISP control signals
10187                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10188                                                      field                                                                     */
10189       __IOM uint32_t NCEPOL80   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 80                              */
10190             uint32_t            : 3;
10191       __IOM uint32_t FIEN80     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10192                                                      Otherwise the selected function will enable the input only
10193                                                      when needed                                                               */
10194       __IOM uint32_t FOEN80     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10195                                                      Otherwise the selected function will enable the output
10196                                                      only when needed                                                          */
10197             uint32_t            : 4;
10198     } PINCFG80_b;
10199   } ;
10200 
10201   union {
10202     __IOM uint32_t PINCFG81;                    /*!< (@ 0x00000144) Controls the operation of GPIO pin 81.                     */
10203 
10204     struct {
10205       __IOM uint32_t FNCSEL81   : 4;            /*!< [3..0] Function select for GPIO pin 81                                    */
10206       __IOM uint32_t INPEN81    : 1;            /*!< [4..4] Input enable for GPIO 81                                           */
10207       __IOM uint32_t RDZERO81   : 1;            /*!< [5..5] Return 0 for read data on GPIO 81                                  */
10208       __IOM uint32_t IRPTEN81   : 2;            /*!< [7..6] Interrupt enable for GPIO 81                                       */
10209       __IOM uint32_t OUTCFG81   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 81                              */
10210       __IOM uint32_t DS81       : 2;            /*!< [11..10] Drive strength selection for GPIO 81                             */
10211       __IOM uint32_t SR81       : 1;            /*!< [12..12] Configure the slew rate                                          */
10212       __IOM uint32_t PULLCFG81  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 81                        */
10213       __IOM uint32_t NCESRC81   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 81, DISP control signals
10214                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10215                                                      field                                                                     */
10216       __IOM uint32_t NCEPOL81   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 81                              */
10217             uint32_t            : 3;
10218       __IOM uint32_t FIEN81     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10219                                                      Otherwise the selected function will enable the input only
10220                                                      when needed                                                               */
10221       __IOM uint32_t FOEN81     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10222                                                      Otherwise the selected function will enable the output
10223                                                      only when needed                                                          */
10224             uint32_t            : 4;
10225     } PINCFG81_b;
10226   } ;
10227 
10228   union {
10229     __IOM uint32_t PINCFG82;                    /*!< (@ 0x00000148) Controls the operation of GPIO pin 82.                     */
10230 
10231     struct {
10232       __IOM uint32_t FNCSEL82   : 4;            /*!< [3..0] Function select for GPIO pin 82                                    */
10233       __IOM uint32_t INPEN82    : 1;            /*!< [4..4] Input enable for GPIO 82                                           */
10234       __IOM uint32_t RDZERO82   : 1;            /*!< [5..5] Return 0 for read data on GPIO 82                                  */
10235       __IOM uint32_t IRPTEN82   : 2;            /*!< [7..6] Interrupt enable for GPIO 82                                       */
10236       __IOM uint32_t OUTCFG82   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 82                              */
10237       __IOM uint32_t DS82       : 2;            /*!< [11..10] Drive strength selection for GPIO 82                             */
10238       __IOM uint32_t SR82       : 1;            /*!< [12..12] Configure the slew rate                                          */
10239       __IOM uint32_t PULLCFG82  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 82                        */
10240       __IOM uint32_t NCESRC82   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 82, DISP control signals
10241                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10242                                                      field                                                                     */
10243       __IOM uint32_t NCEPOL82   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 82                              */
10244             uint32_t            : 3;
10245       __IOM uint32_t FIEN82     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10246                                                      Otherwise the selected function will enable the input only
10247                                                      when needed                                                               */
10248       __IOM uint32_t FOEN82     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10249                                                      Otherwise the selected function will enable the output
10250                                                      only when needed                                                          */
10251             uint32_t            : 4;
10252     } PINCFG82_b;
10253   } ;
10254 
10255   union {
10256     __IOM uint32_t PINCFG83;                    /*!< (@ 0x0000014C) Controls the operation of GPIO pin 83.                     */
10257 
10258     struct {
10259       __IOM uint32_t FNCSEL83   : 4;            /*!< [3..0] Function select for GPIO pin 83                                    */
10260       __IOM uint32_t INPEN83    : 1;            /*!< [4..4] Input enable for GPIO 83                                           */
10261       __IOM uint32_t RDZERO83   : 1;            /*!< [5..5] Return 0 for read data on GPIO 83                                  */
10262       __IOM uint32_t IRPTEN83   : 2;            /*!< [7..6] Interrupt enable for GPIO 83                                       */
10263       __IOM uint32_t OUTCFG83   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 83                              */
10264       __IOM uint32_t DS83       : 2;            /*!< [11..10] Drive strength selection for GPIO 83                             */
10265       __IOM uint32_t SR83       : 1;            /*!< [12..12] Configure the slew rate                                          */
10266       __IOM uint32_t PULLCFG83  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 83                        */
10267       __IOM uint32_t NCESRC83   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 83, DISP control signals
10268                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10269                                                      field                                                                     */
10270       __IOM uint32_t NCEPOL83   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 83                              */
10271             uint32_t            : 3;
10272       __IOM uint32_t FIEN83     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10273                                                      Otherwise the selected function will enable the input only
10274                                                      when needed                                                               */
10275       __IOM uint32_t FOEN83     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10276                                                      Otherwise the selected function will enable the output
10277                                                      only when needed                                                          */
10278             uint32_t            : 4;
10279     } PINCFG83_b;
10280   } ;
10281 
10282   union {
10283     __IOM uint32_t PINCFG84;                    /*!< (@ 0x00000150) Controls the operation of GPIO pin 84.                     */
10284 
10285     struct {
10286       __IOM uint32_t FNCSEL84   : 4;            /*!< [3..0] Function select for GPIO pin 84                                    */
10287       __IOM uint32_t INPEN84    : 1;            /*!< [4..4] Input enable for GPIO 84                                           */
10288       __IOM uint32_t RDZERO84   : 1;            /*!< [5..5] Return 0 for read data on GPIO 84                                  */
10289       __IOM uint32_t IRPTEN84   : 2;            /*!< [7..6] Interrupt enable for GPIO 84                                       */
10290       __IOM uint32_t OUTCFG84   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 84                              */
10291       __IOM uint32_t DS84       : 2;            /*!< [11..10] Drive strength selection for GPIO 84                             */
10292       __IOM uint32_t SR84       : 1;            /*!< [12..12] Configure the slew rate                                          */
10293       __IOM uint32_t PULLCFG84  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 84                        */
10294       __IOM uint32_t NCESRC84   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 84, DISP control signals
10295                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10296                                                      field                                                                     */
10297       __IOM uint32_t NCEPOL84   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 84                              */
10298             uint32_t            : 3;
10299       __IOM uint32_t FIEN84     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10300                                                      Otherwise the selected function will enable the input only
10301                                                      when needed                                                               */
10302       __IOM uint32_t FOEN84     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10303                                                      Otherwise the selected function will enable the output
10304                                                      only when needed                                                          */
10305             uint32_t            : 4;
10306     } PINCFG84_b;
10307   } ;
10308 
10309   union {
10310     __IOM uint32_t PINCFG85;                    /*!< (@ 0x00000154) Controls the operation of GPIO pin 85.                     */
10311 
10312     struct {
10313       __IOM uint32_t FNCSEL85   : 4;            /*!< [3..0] Function select for GPIO pin 85                                    */
10314       __IOM uint32_t INPEN85    : 1;            /*!< [4..4] Input enable for GPIO 85                                           */
10315       __IOM uint32_t RDZERO85   : 1;            /*!< [5..5] Return 0 for read data on GPIO 85                                  */
10316       __IOM uint32_t IRPTEN85   : 2;            /*!< [7..6] Interrupt enable for GPIO 85                                       */
10317       __IOM uint32_t OUTCFG85   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 85                              */
10318       __IOM uint32_t DS85       : 2;            /*!< [11..10] Drive strength selection for GPIO 85                             */
10319       __IOM uint32_t SR85       : 1;            /*!< [12..12] Configure the slew rate                                          */
10320       __IOM uint32_t PULLCFG85  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 85                        */
10321       __IOM uint32_t NCESRC85   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 85, DISP control signals
10322                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10323                                                      field                                                                     */
10324       __IOM uint32_t NCEPOL85   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 85                              */
10325             uint32_t            : 3;
10326       __IOM uint32_t FIEN85     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10327                                                      Otherwise the selected function will enable the input only
10328                                                      when needed                                                               */
10329       __IOM uint32_t FOEN85     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10330                                                      Otherwise the selected function will enable the output
10331                                                      only when needed                                                          */
10332             uint32_t            : 4;
10333     } PINCFG85_b;
10334   } ;
10335 
10336   union {
10337     __IOM uint32_t PINCFG86;                    /*!< (@ 0x00000158) Controls the operation of GPIO pin 86.                     */
10338 
10339     struct {
10340       __IOM uint32_t FNCSEL86   : 4;            /*!< [3..0] Function select for GPIO pin 86                                    */
10341       __IOM uint32_t INPEN86    : 1;            /*!< [4..4] Input enable for GPIO 86                                           */
10342       __IOM uint32_t RDZERO86   : 1;            /*!< [5..5] Return 0 for read data on GPIO 86                                  */
10343       __IOM uint32_t IRPTEN86   : 2;            /*!< [7..6] Interrupt enable for GPIO 86                                       */
10344       __IOM uint32_t OUTCFG86   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 86                              */
10345       __IOM uint32_t DS86       : 2;            /*!< [11..10] Drive strength selection for GPIO 86                             */
10346       __IOM uint32_t SR86       : 1;            /*!< [12..12] Configure the slew rate                                          */
10347       __IOM uint32_t PULLCFG86  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 86                        */
10348       __IOM uint32_t NCESRC86   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 86, DISP control signals
10349                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10350                                                      field                                                                     */
10351       __IOM uint32_t NCEPOL86   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 86                              */
10352             uint32_t            : 3;
10353       __IOM uint32_t FIEN86     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10354                                                      Otherwise the selected function will enable the input only
10355                                                      when needed                                                               */
10356       __IOM uint32_t FOEN86     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10357                                                      Otherwise the selected function will enable the output
10358                                                      only when needed                                                          */
10359             uint32_t            : 4;
10360     } PINCFG86_b;
10361   } ;
10362 
10363   union {
10364     __IOM uint32_t PINCFG87;                    /*!< (@ 0x0000015C) Controls the operation of GPIO pin 87.                     */
10365 
10366     struct {
10367       __IOM uint32_t FNCSEL87   : 4;            /*!< [3..0] Function select for GPIO pin 87                                    */
10368       __IOM uint32_t INPEN87    : 1;            /*!< [4..4] Input enable for GPIO 87                                           */
10369       __IOM uint32_t RDZERO87   : 1;            /*!< [5..5] Return 0 for read data on GPIO 87                                  */
10370       __IOM uint32_t IRPTEN87   : 2;            /*!< [7..6] Interrupt enable for GPIO 87                                       */
10371       __IOM uint32_t OUTCFG87   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 87                              */
10372       __IOM uint32_t DS87       : 2;            /*!< [11..10] Drive strength selection for GPIO 87                             */
10373       __IOM uint32_t SR87       : 1;            /*!< [12..12] Configure the slew rate                                          */
10374       __IOM uint32_t PULLCFG87  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 87                        */
10375       __IOM uint32_t NCESRC87   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 87, DISP control signals
10376                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10377                                                      field                                                                     */
10378       __IOM uint32_t NCEPOL87   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 87                              */
10379             uint32_t            : 3;
10380       __IOM uint32_t FIEN87     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10381                                                      Otherwise the selected function will enable the input only
10382                                                      when needed                                                               */
10383       __IOM uint32_t FOEN87     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10384                                                      Otherwise the selected function will enable the output
10385                                                      only when needed                                                          */
10386             uint32_t            : 4;
10387     } PINCFG87_b;
10388   } ;
10389 
10390   union {
10391     __IOM uint32_t PINCFG88;                    /*!< (@ 0x00000160) Controls the operation of GPIO pin 88.                     */
10392 
10393     struct {
10394       __IOM uint32_t FNCSEL88   : 4;            /*!< [3..0] Function select for GPIO pin 88                                    */
10395       __IOM uint32_t INPEN88    : 1;            /*!< [4..4] Input enable for GPIO 88                                           */
10396       __IOM uint32_t RDZERO88   : 1;            /*!< [5..5] Return 0 for read data on GPIO 88                                  */
10397       __IOM uint32_t IRPTEN88   : 2;            /*!< [7..6] Interrupt enable for GPIO 88                                       */
10398       __IOM uint32_t OUTCFG88   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 88                              */
10399       __IOM uint32_t DS88       : 2;            /*!< [11..10] Drive strength selection for GPIO 88                             */
10400       __IOM uint32_t SR88       : 1;            /*!< [12..12] Configure the slew rate                                          */
10401       __IOM uint32_t PULLCFG88  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 88                        */
10402       __IOM uint32_t NCESRC88   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 88, DISP control signals
10403                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10404                                                      field                                                                     */
10405       __IOM uint32_t NCEPOL88   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 88                              */
10406             uint32_t            : 3;
10407       __IOM uint32_t FIEN88     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10408                                                      Otherwise the selected function will enable the input only
10409                                                      when needed                                                               */
10410       __IOM uint32_t FOEN88     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10411                                                      Otherwise the selected function will enable the output
10412                                                      only when needed                                                          */
10413             uint32_t            : 4;
10414     } PINCFG88_b;
10415   } ;
10416 
10417   union {
10418     __IOM uint32_t PINCFG89;                    /*!< (@ 0x00000164) Controls the operation of GPIO pin 89.                     */
10419 
10420     struct {
10421       __IOM uint32_t FNCSEL89   : 4;            /*!< [3..0] Function select for GPIO pin 89                                    */
10422       __IOM uint32_t INPEN89    : 1;            /*!< [4..4] Input enable for GPIO 89                                           */
10423       __IOM uint32_t RDZERO89   : 1;            /*!< [5..5] Return 0 for read data on GPIO 89                                  */
10424       __IOM uint32_t IRPTEN89   : 2;            /*!< [7..6] Interrupt enable for GPIO 89                                       */
10425       __IOM uint32_t OUTCFG89   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 89                              */
10426       __IOM uint32_t DS89       : 2;            /*!< [11..10] Drive strength selection for GPIO 89                             */
10427       __IOM uint32_t SR89       : 1;            /*!< [12..12] Configure the slew rate                                          */
10428       __IOM uint32_t PULLCFG89  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 89                        */
10429       __IOM uint32_t NCESRC89   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 89, DISP control signals
10430                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10431                                                      field                                                                     */
10432       __IOM uint32_t NCEPOL89   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 89                              */
10433             uint32_t            : 3;
10434       __IOM uint32_t FIEN89     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10435                                                      Otherwise the selected function will enable the input only
10436                                                      when needed                                                               */
10437       __IOM uint32_t FOEN89     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10438                                                      Otherwise the selected function will enable the output
10439                                                      only when needed                                                          */
10440             uint32_t            : 4;
10441     } PINCFG89_b;
10442   } ;
10443 
10444   union {
10445     __IOM uint32_t PINCFG90;                    /*!< (@ 0x00000168) Controls the operation of GPIO pin 90.                     */
10446 
10447     struct {
10448       __IOM uint32_t FNCSEL90   : 4;            /*!< [3..0] Function select for GPIO pin 90                                    */
10449       __IOM uint32_t INPEN90    : 1;            /*!< [4..4] Input enable for GPIO 90                                           */
10450       __IOM uint32_t RDZERO90   : 1;            /*!< [5..5] Return 0 for read data on GPIO 90                                  */
10451       __IOM uint32_t IRPTEN90   : 2;            /*!< [7..6] Interrupt enable for GPIO 90                                       */
10452       __IOM uint32_t OUTCFG90   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 90                              */
10453       __IOM uint32_t DS90       : 2;            /*!< [11..10] Drive strength selection for GPIO 90                             */
10454       __IOM uint32_t SR90       : 1;            /*!< [12..12] Configure the slew rate                                          */
10455       __IOM uint32_t PULLCFG90  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 90                        */
10456       __IOM uint32_t NCESRC90   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 90, DISP control signals
10457                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10458                                                      field                                                                     */
10459       __IOM uint32_t NCEPOL90   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 90                              */
10460             uint32_t            : 3;
10461       __IOM uint32_t FIEN90     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10462                                                      Otherwise the selected function will enable the input only
10463                                                      when needed                                                               */
10464       __IOM uint32_t FOEN90     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10465                                                      Otherwise the selected function will enable the output
10466                                                      only when needed                                                          */
10467             uint32_t            : 4;
10468     } PINCFG90_b;
10469   } ;
10470 
10471   union {
10472     __IOM uint32_t PINCFG91;                    /*!< (@ 0x0000016C) Controls the operation of GPIO pin 91.                     */
10473 
10474     struct {
10475       __IOM uint32_t FNCSEL91   : 4;            /*!< [3..0] Function select for GPIO pin 91                                    */
10476       __IOM uint32_t INPEN91    : 1;            /*!< [4..4] Input enable for GPIO 91                                           */
10477       __IOM uint32_t RDZERO91   : 1;            /*!< [5..5] Return 0 for read data on GPIO 91                                  */
10478       __IOM uint32_t IRPTEN91   : 2;            /*!< [7..6] Interrupt enable for GPIO 91                                       */
10479       __IOM uint32_t OUTCFG91   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 91                              */
10480       __IOM uint32_t DS91       : 2;            /*!< [11..10] Drive strength selection for GPIO 91                             */
10481       __IOM uint32_t SR91       : 1;            /*!< [12..12] Configure the slew rate                                          */
10482       __IOM uint32_t PULLCFG91  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 91                        */
10483       __IOM uint32_t NCESRC91   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 91, DISP control signals
10484                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10485                                                      field                                                                     */
10486       __IOM uint32_t NCEPOL91   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 91                              */
10487             uint32_t            : 3;
10488       __IOM uint32_t FIEN91     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10489                                                      Otherwise the selected function will enable the input only
10490                                                      when needed                                                               */
10491       __IOM uint32_t FOEN91     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10492                                                      Otherwise the selected function will enable the output
10493                                                      only when needed                                                          */
10494             uint32_t            : 4;
10495     } PINCFG91_b;
10496   } ;
10497 
10498   union {
10499     __IOM uint32_t PINCFG92;                    /*!< (@ 0x00000170) Controls the operation of GPIO pin 92.                     */
10500 
10501     struct {
10502       __IOM uint32_t FNCSEL92   : 4;            /*!< [3..0] Function select for GPIO pin 92                                    */
10503       __IOM uint32_t INPEN92    : 1;            /*!< [4..4] Input enable for GPIO 92                                           */
10504       __IOM uint32_t RDZERO92   : 1;            /*!< [5..5] Return 0 for read data on GPIO 92                                  */
10505       __IOM uint32_t IRPTEN92   : 2;            /*!< [7..6] Interrupt enable for GPIO 92                                       */
10506       __IOM uint32_t OUTCFG92   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 92                              */
10507       __IOM uint32_t DS92       : 2;            /*!< [11..10] Drive strength selection for GPIO 92                             */
10508       __IOM uint32_t SR92       : 1;            /*!< [12..12] Configure the slew rate                                          */
10509       __IOM uint32_t PULLCFG92  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 92                        */
10510       __IOM uint32_t NCESRC92   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 92, DISP control signals
10511                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10512                                                      field                                                                     */
10513       __IOM uint32_t NCEPOL92   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 92                              */
10514             uint32_t            : 3;
10515       __IOM uint32_t FIEN92     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10516                                                      Otherwise the selected function will enable the input only
10517                                                      when needed                                                               */
10518       __IOM uint32_t FOEN92     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10519                                                      Otherwise the selected function will enable the output
10520                                                      only when needed                                                          */
10521             uint32_t            : 4;
10522     } PINCFG92_b;
10523   } ;
10524 
10525   union {
10526     __IOM uint32_t PINCFG93;                    /*!< (@ 0x00000174) Controls the operation of GPIO pin 93.                     */
10527 
10528     struct {
10529       __IOM uint32_t FNCSEL93   : 4;            /*!< [3..0] Function select for GPIO pin 93                                    */
10530       __IOM uint32_t INPEN93    : 1;            /*!< [4..4] Input enable for GPIO 93                                           */
10531       __IOM uint32_t RDZERO93   : 1;            /*!< [5..5] Return 0 for read data on GPIO 93                                  */
10532       __IOM uint32_t IRPTEN93   : 2;            /*!< [7..6] Interrupt enable for GPIO 93                                       */
10533       __IOM uint32_t OUTCFG93   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 93                              */
10534       __IOM uint32_t DS93       : 2;            /*!< [11..10] Drive strength selection for GPIO 93                             */
10535       __IOM uint32_t SR93       : 1;            /*!< [12..12] Configure the slew rate                                          */
10536       __IOM uint32_t PULLCFG93  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 93                        */
10537       __IOM uint32_t NCESRC93   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 93, DISP control signals
10538                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10539                                                      field                                                                     */
10540       __IOM uint32_t NCEPOL93   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 93                              */
10541             uint32_t            : 3;
10542       __IOM uint32_t FIEN93     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10543                                                      Otherwise the selected function will enable the input only
10544                                                      when needed                                                               */
10545       __IOM uint32_t FOEN93     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10546                                                      Otherwise the selected function will enable the output
10547                                                      only when needed                                                          */
10548             uint32_t            : 4;
10549     } PINCFG93_b;
10550   } ;
10551 
10552   union {
10553     __IOM uint32_t PINCFG94;                    /*!< (@ 0x00000178) Controls the operation of GPIO pin 94.                     */
10554 
10555     struct {
10556       __IOM uint32_t FNCSEL94   : 4;            /*!< [3..0] Function select for GPIO pin 94                                    */
10557       __IOM uint32_t INPEN94    : 1;            /*!< [4..4] Input enable for GPIO 94                                           */
10558       __IOM uint32_t RDZERO94   : 1;            /*!< [5..5] Return 0 for read data on GPIO 94                                  */
10559       __IOM uint32_t IRPTEN94   : 2;            /*!< [7..6] Interrupt enable for GPIO 94                                       */
10560       __IOM uint32_t OUTCFG94   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 94                              */
10561       __IOM uint32_t DS94       : 2;            /*!< [11..10] Drive strength selection for GPIO 94                             */
10562       __IOM uint32_t SR94       : 1;            /*!< [12..12] Configure the slew rate                                          */
10563       __IOM uint32_t PULLCFG94  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 94                        */
10564       __IOM uint32_t NCESRC94   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 94, DISP control signals
10565                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10566                                                      field                                                                     */
10567       __IOM uint32_t NCEPOL94   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 94                              */
10568             uint32_t            : 3;
10569       __IOM uint32_t FIEN94     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10570                                                      Otherwise the selected function will enable the input only
10571                                                      when needed                                                               */
10572       __IOM uint32_t FOEN94     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10573                                                      Otherwise the selected function will enable the output
10574                                                      only when needed                                                          */
10575             uint32_t            : 4;
10576     } PINCFG94_b;
10577   } ;
10578 
10579   union {
10580     __IOM uint32_t PINCFG95;                    /*!< (@ 0x0000017C) Controls the operation of GPIO pin 95.                     */
10581 
10582     struct {
10583       __IOM uint32_t FNCSEL95   : 4;            /*!< [3..0] Function select for GPIO pin 95                                    */
10584       __IOM uint32_t INPEN95    : 1;            /*!< [4..4] Input enable for GPIO 95                                           */
10585       __IOM uint32_t RDZERO95   : 1;            /*!< [5..5] Return 0 for read data on GPIO 95                                  */
10586       __IOM uint32_t IRPTEN95   : 2;            /*!< [7..6] Interrupt enable for GPIO 95                                       */
10587       __IOM uint32_t OUTCFG95   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 95                              */
10588       __IOM uint32_t DS95       : 2;            /*!< [11..10] Drive strength selection for GPIO 95                             */
10589       __IOM uint32_t SR95       : 1;            /*!< [12..12] Configure the slew rate                                          */
10590       __IOM uint32_t PULLCFG95  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 95                        */
10591       __IOM uint32_t NCESRC95   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 95, DISP control signals
10592                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10593                                                      field                                                                     */
10594       __IOM uint32_t NCEPOL95   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 95                              */
10595             uint32_t            : 3;
10596       __IOM uint32_t FIEN95     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10597                                                      Otherwise the selected function will enable the input only
10598                                                      when needed                                                               */
10599       __IOM uint32_t FOEN95     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10600                                                      Otherwise the selected function will enable the output
10601                                                      only when needed                                                          */
10602             uint32_t            : 4;
10603     } PINCFG95_b;
10604   } ;
10605 
10606   union {
10607     __IOM uint32_t PINCFG96;                    /*!< (@ 0x00000180) Controls the operation of GPIO pin 96.                     */
10608 
10609     struct {
10610       __IOM uint32_t FNCSEL96   : 4;            /*!< [3..0] Function select for GPIO pin 96                                    */
10611       __IOM uint32_t INPEN96    : 1;            /*!< [4..4] Input enable for GPIO 96                                           */
10612       __IOM uint32_t RDZERO96   : 1;            /*!< [5..5] Return 0 for read data on GPIO 96                                  */
10613       __IOM uint32_t IRPTEN96   : 2;            /*!< [7..6] Interrupt enable for GPIO 96                                       */
10614       __IOM uint32_t OUTCFG96   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 96                              */
10615       __IOM uint32_t DS96       : 2;            /*!< [11..10] Drive strength selection for GPIO 96                             */
10616       __IOM uint32_t SR96       : 1;            /*!< [12..12] Configure the slew rate                                          */
10617       __IOM uint32_t PULLCFG96  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 96                        */
10618       __IOM uint32_t NCESRC96   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 96, DISP control signals
10619                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10620                                                      field                                                                     */
10621       __IOM uint32_t NCEPOL96   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 96                              */
10622             uint32_t            : 3;
10623       __IOM uint32_t FIEN96     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10624                                                      Otherwise the selected function will enable the input only
10625                                                      when needed                                                               */
10626       __IOM uint32_t FOEN96     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10627                                                      Otherwise the selected function will enable the output
10628                                                      only when needed                                                          */
10629             uint32_t            : 4;
10630     } PINCFG96_b;
10631   } ;
10632 
10633   union {
10634     __IOM uint32_t PINCFG97;                    /*!< (@ 0x00000184) Controls the operation of GPIO pin 97.                     */
10635 
10636     struct {
10637       __IOM uint32_t FNCSEL97   : 4;            /*!< [3..0] Function select for GPIO pin 97                                    */
10638       __IOM uint32_t INPEN97    : 1;            /*!< [4..4] Input enable for GPIO 97                                           */
10639       __IOM uint32_t RDZERO97   : 1;            /*!< [5..5] Return 0 for read data on GPIO 97                                  */
10640       __IOM uint32_t IRPTEN97   : 2;            /*!< [7..6] Interrupt enable for GPIO 97                                       */
10641       __IOM uint32_t OUTCFG97   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 97                              */
10642       __IOM uint32_t DS97       : 2;            /*!< [11..10] Drive strength selection for GPIO 97                             */
10643       __IOM uint32_t SR97       : 1;            /*!< [12..12] Configure the slew rate                                          */
10644       __IOM uint32_t PULLCFG97  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 97                        */
10645       __IOM uint32_t NCESRC97   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 97, DISP control signals
10646                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10647                                                      field                                                                     */
10648       __IOM uint32_t NCEPOL97   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 97                              */
10649             uint32_t            : 3;
10650       __IOM uint32_t FIEN97     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10651                                                      Otherwise the selected function will enable the input only
10652                                                      when needed                                                               */
10653       __IOM uint32_t FOEN97     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10654                                                      Otherwise the selected function will enable the output
10655                                                      only when needed                                                          */
10656             uint32_t            : 4;
10657     } PINCFG97_b;
10658   } ;
10659 
10660   union {
10661     __IOM uint32_t PINCFG98;                    /*!< (@ 0x00000188) Controls the operation of GPIO pin 98.                     */
10662 
10663     struct {
10664       __IOM uint32_t FNCSEL98   : 4;            /*!< [3..0] Function select for GPIO pin 98                                    */
10665       __IOM uint32_t INPEN98    : 1;            /*!< [4..4] Input enable for GPIO 98                                           */
10666       __IOM uint32_t RDZERO98   : 1;            /*!< [5..5] Return 0 for read data on GPIO 98                                  */
10667       __IOM uint32_t IRPTEN98   : 2;            /*!< [7..6] Interrupt enable for GPIO 98                                       */
10668       __IOM uint32_t OUTCFG98   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 98                              */
10669       __IOM uint32_t DS98       : 2;            /*!< [11..10] Drive strength selection for GPIO 98                             */
10670       __IOM uint32_t SR98       : 1;            /*!< [12..12] Configure the slew rate                                          */
10671       __IOM uint32_t PULLCFG98  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 98                        */
10672       __IOM uint32_t NCESRC98   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 98, DISP control signals
10673                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10674                                                      field                                                                     */
10675       __IOM uint32_t NCEPOL98   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 98                              */
10676             uint32_t            : 3;
10677       __IOM uint32_t FIEN98     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10678                                                      Otherwise the selected function will enable the input only
10679                                                      when needed                                                               */
10680       __IOM uint32_t FOEN98     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10681                                                      Otherwise the selected function will enable the output
10682                                                      only when needed                                                          */
10683             uint32_t            : 4;
10684     } PINCFG98_b;
10685   } ;
10686 
10687   union {
10688     __IOM uint32_t PINCFG99;                    /*!< (@ 0x0000018C) Controls the operation of GPIO pin 99.                     */
10689 
10690     struct {
10691       __IOM uint32_t FNCSEL99   : 4;            /*!< [3..0] Function select for GPIO pin 99                                    */
10692       __IOM uint32_t INPEN99    : 1;            /*!< [4..4] Input enable for GPIO 99                                           */
10693       __IOM uint32_t RDZERO99   : 1;            /*!< [5..5] Return 0 for read data on GPIO 99                                  */
10694       __IOM uint32_t IRPTEN99   : 2;            /*!< [7..6] Interrupt enable for GPIO 99                                       */
10695       __IOM uint32_t OUTCFG99   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 99                              */
10696       __IOM uint32_t DS99       : 2;            /*!< [11..10] Drive strength selection for GPIO 99                             */
10697       __IOM uint32_t SR99       : 1;            /*!< [12..12] Configure the slew rate                                          */
10698       __IOM uint32_t PULLCFG99  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 99                        */
10699       __IOM uint32_t NCESRC99   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 99, DISP control signals
10700                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10701                                                      field                                                                     */
10702       __IOM uint32_t NCEPOL99   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 99                              */
10703             uint32_t            : 3;
10704       __IOM uint32_t FIEN99     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10705                                                      Otherwise the selected function will enable the input only
10706                                                      when needed                                                               */
10707       __IOM uint32_t FOEN99     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10708                                                      Otherwise the selected function will enable the output
10709                                                      only when needed                                                          */
10710             uint32_t            : 4;
10711     } PINCFG99_b;
10712   } ;
10713 
10714   union {
10715     __IOM uint32_t PINCFG100;                   /*!< (@ 0x00000190) Controls the operation of GPIO pin 100.                    */
10716 
10717     struct {
10718       __IOM uint32_t FNCSEL100  : 4;            /*!< [3..0] Function select for GPIO pin 100                                   */
10719       __IOM uint32_t INPEN100   : 1;            /*!< [4..4] Input enable for GPIO 100                                          */
10720       __IOM uint32_t RDZERO100  : 1;            /*!< [5..5] Return 0 for read data on GPIO 100                                 */
10721       __IOM uint32_t IRPTEN100  : 2;            /*!< [7..6] Interrupt enable for GPIO 100                                      */
10722       __IOM uint32_t OUTCFG100  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 100                             */
10723       __IOM uint32_t DS100      : 2;            /*!< [11..10] Drive strength selection for GPIO 100                            */
10724       __IOM uint32_t SR100      : 1;            /*!< [12..12] Configure the slew rate                                          */
10725       __IOM uint32_t PULLCFG100 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 100                       */
10726       __IOM uint32_t NCESRC100  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 100, DISP control signals
10727                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10728                                                      field                                                                     */
10729       __IOM uint32_t NCEPOL100  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 100                             */
10730             uint32_t            : 3;
10731       __IOM uint32_t FIEN100    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10732                                                      Otherwise the selected function will enable the input only
10733                                                      when needed                                                               */
10734       __IOM uint32_t FOEN100    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10735                                                      Otherwise the selected function will enable the output
10736                                                      only when needed                                                          */
10737             uint32_t            : 4;
10738     } PINCFG100_b;
10739   } ;
10740 
10741   union {
10742     __IOM uint32_t PINCFG101;                   /*!< (@ 0x00000194) Controls the operation of GPIO pin 101.                    */
10743 
10744     struct {
10745       __IOM uint32_t FNCSEL101  : 4;            /*!< [3..0] Function select for GPIO pin 101                                   */
10746       __IOM uint32_t INPEN101   : 1;            /*!< [4..4] Input enable for GPIO 101                                          */
10747       __IOM uint32_t RDZERO101  : 1;            /*!< [5..5] Return 0 for read data on GPIO 101                                 */
10748       __IOM uint32_t IRPTEN101  : 2;            /*!< [7..6] Interrupt enable for GPIO 101                                      */
10749       __IOM uint32_t OUTCFG101  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 101                             */
10750       __IOM uint32_t DS101      : 2;            /*!< [11..10] Drive strength selection for GPIO 101                            */
10751       __IOM uint32_t SR101      : 1;            /*!< [12..12] Configure the slew rate                                          */
10752       __IOM uint32_t PULLCFG101 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 101                       */
10753       __IOM uint32_t NCESRC101  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 101, DISP control signals
10754                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10755                                                      field                                                                     */
10756       __IOM uint32_t NCEPOL101  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 101                             */
10757             uint32_t            : 3;
10758       __IOM uint32_t FIEN101    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10759                                                      Otherwise the selected function will enable the input only
10760                                                      when needed                                                               */
10761       __IOM uint32_t FOEN101    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10762                                                      Otherwise the selected function will enable the output
10763                                                      only when needed                                                          */
10764             uint32_t            : 4;
10765     } PINCFG101_b;
10766   } ;
10767 
10768   union {
10769     __IOM uint32_t PINCFG102;                   /*!< (@ 0x00000198) Controls the operation of GPIO pin 102.                    */
10770 
10771     struct {
10772       __IOM uint32_t FNCSEL102  : 4;            /*!< [3..0] Function select for GPIO pin 102                                   */
10773       __IOM uint32_t INPEN102   : 1;            /*!< [4..4] Input enable for GPIO 102                                          */
10774       __IOM uint32_t RDZERO102  : 1;            /*!< [5..5] Return 0 for read data on GPIO 102                                 */
10775       __IOM uint32_t IRPTEN102  : 2;            /*!< [7..6] Interrupt enable for GPIO 102                                      */
10776       __IOM uint32_t OUTCFG102  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 102                             */
10777       __IOM uint32_t DS102      : 2;            /*!< [11..10] Drive strength selection for GPIO 102                            */
10778       __IOM uint32_t SR102      : 1;            /*!< [12..12] Configure the slew rate                                          */
10779       __IOM uint32_t PULLCFG102 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 102                       */
10780       __IOM uint32_t NCESRC102  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 102, DISP control signals
10781                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10782                                                      field                                                                     */
10783       __IOM uint32_t NCEPOL102  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 102                             */
10784             uint32_t            : 3;
10785       __IOM uint32_t FIEN102    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10786                                                      Otherwise the selected function will enable the input only
10787                                                      when needed                                                               */
10788       __IOM uint32_t FOEN102    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10789                                                      Otherwise the selected function will enable the output
10790                                                      only when needed                                                          */
10791             uint32_t            : 4;
10792     } PINCFG102_b;
10793   } ;
10794 
10795   union {
10796     __IOM uint32_t PINCFG103;                   /*!< (@ 0x0000019C) Controls the operation of GPIO pin 103.                    */
10797 
10798     struct {
10799       __IOM uint32_t FNCSEL103  : 4;            /*!< [3..0] Function select for GPIO pin 103                                   */
10800       __IOM uint32_t INPEN103   : 1;            /*!< [4..4] Input enable for GPIO 103                                          */
10801       __IOM uint32_t RDZERO103  : 1;            /*!< [5..5] Return 0 for read data on GPIO 103                                 */
10802       __IOM uint32_t IRPTEN103  : 2;            /*!< [7..6] Interrupt enable for GPIO 103                                      */
10803       __IOM uint32_t OUTCFG103  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 103                             */
10804       __IOM uint32_t DS103      : 2;            /*!< [11..10] Drive strength selection for GPIO 103                            */
10805       __IOM uint32_t SR103      : 1;            /*!< [12..12] Configure the slew rate                                          */
10806       __IOM uint32_t PULLCFG103 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 103                       */
10807       __IOM uint32_t NCESRC103  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 103, DISP control signals
10808                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10809                                                      field                                                                     */
10810       __IOM uint32_t NCEPOL103  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 103                             */
10811             uint32_t            : 3;
10812       __IOM uint32_t FIEN103    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10813                                                      Otherwise the selected function will enable the input only
10814                                                      when needed                                                               */
10815       __IOM uint32_t FOEN103    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10816                                                      Otherwise the selected function will enable the output
10817                                                      only when needed                                                          */
10818             uint32_t            : 4;
10819     } PINCFG103_b;
10820   } ;
10821 
10822   union {
10823     __IOM uint32_t PINCFG104;                   /*!< (@ 0x000001A0) Controls the operation of GPIO pin 104.                    */
10824 
10825     struct {
10826       __IOM uint32_t FNCSEL104  : 4;            /*!< [3..0] Function select for GPIO pin 104                                   */
10827       __IOM uint32_t INPEN104   : 1;            /*!< [4..4] Input enable for GPIO 104                                          */
10828       __IOM uint32_t RDZERO104  : 1;            /*!< [5..5] Return 0 for read data on GPIO 104                                 */
10829       __IOM uint32_t IRPTEN104  : 2;            /*!< [7..6] Interrupt enable for GPIO 104                                      */
10830       __IOM uint32_t OUTCFG104  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 104                             */
10831       __IOM uint32_t DS104      : 2;            /*!< [11..10] Drive strength selection for GPIO 104                            */
10832       __IOM uint32_t SR104      : 1;            /*!< [12..12] Configure the slew rate                                          */
10833       __IOM uint32_t PULLCFG104 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 104                       */
10834       __IOM uint32_t NCESRC104  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 104, DISP control signals
10835                                                      DE, CSX, and CS. Polarity is determined by CE_POLARITY
10836                                                      field                                                                     */
10837       __IOM uint32_t NCEPOL104  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 104                             */
10838             uint32_t            : 3;
10839       __IOM uint32_t FIEN104    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
10840                                                      Otherwise the selected function will enable the input only
10841                                                      when needed                                                               */
10842       __IOM uint32_t FOEN104    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
10843                                                      Otherwise the selected function will enable the output
10844                                                      only when needed                                                          */
10845             uint32_t            : 4;
10846     } PINCFG104_b;
10847   } ;
10848 
10849   union {
10850     __IOM uint32_t PINCFG105;                   /*!< (@ 0x000001A4) Controls the operation of virtual GPIO pin 105.            */
10851 
10852     struct {
10853       __IOM uint32_t FNCSEL105  : 4;            /*!< [3..0] Function select for GPIO pin 105                                   */
10854       __IOM uint32_t INPEN105   : 1;            /*!< [4..4] Input enable for GPIO 105                                          */
10855       __IOM uint32_t RDZERO105  : 1;            /*!< [5..5] Return 0 for read data on GPIO 105                                 */
10856       __IOM uint32_t IRPTEN105  : 2;            /*!< [7..6] Interrupt enable for GPIO 105                                      */
10857       __IOM uint32_t OUTCFG105  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 105                             */
10858             uint32_t            : 22;
10859     } PINCFG105_b;
10860   } ;
10861 
10862   union {
10863     __IOM uint32_t PINCFG106;                   /*!< (@ 0x000001A8) Controls the operation of virtual GPIO pin 106.            */
10864 
10865     struct {
10866       __IOM uint32_t FNCSEL106  : 4;            /*!< [3..0] Function select for GPIO pin 106                                   */
10867       __IOM uint32_t INPEN106   : 1;            /*!< [4..4] Input enable for GPIO 106                                          */
10868       __IOM uint32_t RDZERO106  : 1;            /*!< [5..5] Return 0 for read data on GPIO 106                                 */
10869       __IOM uint32_t IRPTEN106  : 2;            /*!< [7..6] Interrupt enable for GPIO 106                                      */
10870       __IOM uint32_t OUTCFG106  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 106                             */
10871             uint32_t            : 22;
10872     } PINCFG106_b;
10873   } ;
10874 
10875   union {
10876     __IOM uint32_t PINCFG107;                   /*!< (@ 0x000001AC) Controls the operation of virtual GPIO pin 107.            */
10877 
10878     struct {
10879       __IOM uint32_t FNCSEL107  : 4;            /*!< [3..0] Function select for GPIO pin 107                                   */
10880       __IOM uint32_t INPEN107   : 1;            /*!< [4..4] Input enable for GPIO 107                                          */
10881       __IOM uint32_t RDZERO107  : 1;            /*!< [5..5] Return 0 for read data on GPIO 107                                 */
10882       __IOM uint32_t IRPTEN107  : 2;            /*!< [7..6] Interrupt enable for GPIO 107                                      */
10883       __IOM uint32_t OUTCFG107  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 107                             */
10884             uint32_t            : 22;
10885     } PINCFG107_b;
10886   } ;
10887 
10888   union {
10889     __IOM uint32_t PINCFG108;                   /*!< (@ 0x000001B0) Controls the operation of virtual GPIO pin 108.            */
10890 
10891     struct {
10892       __IOM uint32_t FNCSEL108  : 4;            /*!< [3..0] Function select for GPIO pin 108                                   */
10893       __IOM uint32_t INPEN108   : 1;            /*!< [4..4] Input enable for GPIO 108                                          */
10894       __IOM uint32_t RDZERO108  : 1;            /*!< [5..5] Return 0 for read data on GPIO 108                                 */
10895       __IOM uint32_t IRPTEN108  : 2;            /*!< [7..6] Interrupt enable for GPIO 108                                      */
10896       __IOM uint32_t OUTCFG108  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 108                             */
10897             uint32_t            : 22;
10898     } PINCFG108_b;
10899   } ;
10900 
10901   union {
10902     __IOM uint32_t PINCFG109;                   /*!< (@ 0x000001B4) Controls the operation of virtual GPIO pin 109.            */
10903 
10904     struct {
10905       __IOM uint32_t FNCSEL109  : 4;            /*!< [3..0] Function select for GPIO pin 109                                   */
10906       __IOM uint32_t INPEN109   : 1;            /*!< [4..4] Input enable for GPIO 109                                          */
10907       __IOM uint32_t RDZERO109  : 1;            /*!< [5..5] Return 0 for read data on GPIO 109                                 */
10908       __IOM uint32_t IRPTEN109  : 2;            /*!< [7..6] Interrupt enable for GPIO 109                                      */
10909       __IOM uint32_t OUTCFG109  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 109                             */
10910             uint32_t            : 22;
10911     } PINCFG109_b;
10912   } ;
10913 
10914   union {
10915     __IOM uint32_t PINCFG110;                   /*!< (@ 0x000001B8) Controls the operation of virtual GPIO pin 110.            */
10916 
10917     struct {
10918       __IOM uint32_t FNCSEL110  : 4;            /*!< [3..0] Function select for GPIO pin 110                                   */
10919       __IOM uint32_t INPEN110   : 1;            /*!< [4..4] Input enable for GPIO 110                                          */
10920       __IOM uint32_t RDZERO110  : 1;            /*!< [5..5] Return 0 for read data on GPIO 110                                 */
10921       __IOM uint32_t IRPTEN110  : 2;            /*!< [7..6] Interrupt enable for GPIO 110                                      */
10922       __IOM uint32_t OUTCFG110  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 110                             */
10923             uint32_t            : 22;
10924     } PINCFG110_b;
10925   } ;
10926 
10927   union {
10928     __IOM uint32_t PINCFG111;                   /*!< (@ 0x000001BC) Controls the operation of virtual GPIO pin 111.            */
10929 
10930     struct {
10931       __IOM uint32_t FNCSEL111  : 4;            /*!< [3..0] Function select for GPIO pin 111                                   */
10932       __IOM uint32_t INPEN111   : 1;            /*!< [4..4] Input enable for GPIO 111                                          */
10933       __IOM uint32_t RDZERO111  : 1;            /*!< [5..5] Return 0 for read data on GPIO 111                                 */
10934       __IOM uint32_t IRPTEN111  : 2;            /*!< [7..6] Interrupt enable for GPIO 111                                      */
10935       __IOM uint32_t OUTCFG111  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 111                             */
10936             uint32_t            : 22;
10937     } PINCFG111_b;
10938   } ;
10939 
10940   union {
10941     __IOM uint32_t PINCFG112;                   /*!< (@ 0x000001C0) Controls the operation of virtual GPIO pin 112.            */
10942 
10943     struct {
10944       __IOM uint32_t FNCSEL112  : 4;            /*!< [3..0] Function select for GPIO pin 112                                   */
10945       __IOM uint32_t INPEN112   : 1;            /*!< [4..4] Input enable for GPIO 112                                          */
10946       __IOM uint32_t RDZERO112  : 1;            /*!< [5..5] Return 0 for read data on GPIO 112                                 */
10947       __IOM uint32_t IRPTEN112  : 2;            /*!< [7..6] Interrupt enable for GPIO 112                                      */
10948       __IOM uint32_t OUTCFG112  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 112                             */
10949             uint32_t            : 22;
10950     } PINCFG112_b;
10951   } ;
10952 
10953   union {
10954     __IOM uint32_t PINCFG113;                   /*!< (@ 0x000001C4) Controls the operation of virtual GPIO pin 113.            */
10955 
10956     struct {
10957       __IOM uint32_t FNCSEL113  : 4;            /*!< [3..0] Function select for GPIO pin 113                                   */
10958       __IOM uint32_t INPEN113   : 1;            /*!< [4..4] Input enable for GPIO 113                                          */
10959       __IOM uint32_t RDZERO113  : 1;            /*!< [5..5] Return 0 for read data on GPIO 113                                 */
10960       __IOM uint32_t IRPTEN113  : 2;            /*!< [7..6] Interrupt enable for GPIO 113                                      */
10961       __IOM uint32_t OUTCFG113  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 113                             */
10962             uint32_t            : 22;
10963     } PINCFG113_b;
10964   } ;
10965 
10966   union {
10967     __IOM uint32_t PINCFG114;                   /*!< (@ 0x000001C8) Controls the operation of virtual GPIO pin 114.            */
10968 
10969     struct {
10970       __IOM uint32_t FNCSEL114  : 4;            /*!< [3..0] Function select for GPIO pin 114                                   */
10971       __IOM uint32_t INPEN114   : 1;            /*!< [4..4] Input enable for GPIO 114                                          */
10972       __IOM uint32_t RDZERO114  : 1;            /*!< [5..5] Return 0 for read data on GPIO 114                                 */
10973       __IOM uint32_t IRPTEN114  : 2;            /*!< [7..6] Interrupt enable for GPIO 114                                      */
10974       __IOM uint32_t OUTCFG114  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 114                             */
10975             uint32_t            : 22;
10976     } PINCFG114_b;
10977   } ;
10978 
10979   union {
10980     __IOM uint32_t PINCFG115;                   /*!< (@ 0x000001CC) Controls the operation of virtual GPIO pin 115.            */
10981 
10982     struct {
10983       __IOM uint32_t FNCSEL115  : 4;            /*!< [3..0] Function select for GPIO pin 115                                   */
10984       __IOM uint32_t INPEN115   : 1;            /*!< [4..4] Input enable for GPIO 115                                          */
10985       __IOM uint32_t RDZERO115  : 1;            /*!< [5..5] Return 0 for read data on GPIO 115                                 */
10986       __IOM uint32_t IRPTEN115  : 2;            /*!< [7..6] Interrupt enable for GPIO 115                                      */
10987       __IOM uint32_t OUTCFG115  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 115                             */
10988             uint32_t            : 22;
10989     } PINCFG115_b;
10990   } ;
10991 
10992   union {
10993     __IOM uint32_t PINCFG116;                   /*!< (@ 0x000001D0) Controls the operation of virtual GPIO pin 116.            */
10994 
10995     struct {
10996       __IOM uint32_t FNCSEL116  : 4;            /*!< [3..0] Function select for GPIO pin 116                                   */
10997       __IOM uint32_t INPEN116   : 1;            /*!< [4..4] Input enable for GPIO 116                                          */
10998       __IOM uint32_t RDZERO116  : 1;            /*!< [5..5] Return 0 for read data on GPIO 116                                 */
10999       __IOM uint32_t IRPTEN116  : 2;            /*!< [7..6] Interrupt enable for GPIO 116                                      */
11000       __IOM uint32_t OUTCFG116  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 116                             */
11001             uint32_t            : 22;
11002     } PINCFG116_b;
11003   } ;
11004 
11005   union {
11006     __IOM uint32_t PINCFG117;                   /*!< (@ 0x000001D4) Controls the operation of virtual GPIO pin 117.            */
11007 
11008     struct {
11009       __IOM uint32_t FNCSEL117  : 4;            /*!< [3..0] Function select for GPIO pin 117                                   */
11010       __IOM uint32_t INPEN117   : 1;            /*!< [4..4] Input enable for GPIO 117                                          */
11011       __IOM uint32_t RDZERO117  : 1;            /*!< [5..5] Return 0 for read data on GPIO 117                                 */
11012       __IOM uint32_t IRPTEN117  : 2;            /*!< [7..6] Interrupt enable for GPIO 117                                      */
11013       __IOM uint32_t OUTCFG117  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 117                             */
11014             uint32_t            : 22;
11015     } PINCFG117_b;
11016   } ;
11017 
11018   union {
11019     __IOM uint32_t PINCFG118;                   /*!< (@ 0x000001D8) Controls the operation of virtual GPIO pin 118.            */
11020 
11021     struct {
11022       __IOM uint32_t FNCSEL118  : 4;            /*!< [3..0] Function select for GPIO pin 118                                   */
11023       __IOM uint32_t INPEN118   : 1;            /*!< [4..4] Input enable for GPIO 118                                          */
11024       __IOM uint32_t RDZERO118  : 1;            /*!< [5..5] Return 0 for read data on GPIO 118                                 */
11025       __IOM uint32_t IRPTEN118  : 2;            /*!< [7..6] Interrupt enable for GPIO 118                                      */
11026       __IOM uint32_t OUTCFG118  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 118                             */
11027             uint32_t            : 22;
11028     } PINCFG118_b;
11029   } ;
11030 
11031   union {
11032     __IOM uint32_t PINCFG119;                   /*!< (@ 0x000001DC) Controls the operation of virtual GPIO pin 119.            */
11033 
11034     struct {
11035       __IOM uint32_t FNCSEL119  : 4;            /*!< [3..0] Function select for GPIO pin 119                                   */
11036       __IOM uint32_t INPEN119   : 1;            /*!< [4..4] Input enable for GPIO 119                                          */
11037       __IOM uint32_t RDZERO119  : 1;            /*!< [5..5] Return 0 for read data on GPIO 119                                 */
11038       __IOM uint32_t IRPTEN119  : 2;            /*!< [7..6] Interrupt enable for GPIO 119                                      */
11039       __IOM uint32_t OUTCFG119  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 119                             */
11040             uint32_t            : 22;
11041     } PINCFG119_b;
11042   } ;
11043 
11044   union {
11045     __IOM uint32_t PINCFG120;                   /*!< (@ 0x000001E0) Controls the operation of virtual GPIO pin 120.            */
11046 
11047     struct {
11048       __IOM uint32_t FNCSEL120  : 4;            /*!< [3..0] Function select for GPIO pin 120                                   */
11049       __IOM uint32_t INPEN120   : 1;            /*!< [4..4] Input enable for GPIO 120                                          */
11050       __IOM uint32_t RDZERO120  : 1;            /*!< [5..5] Return 0 for read data on GPIO 120                                 */
11051       __IOM uint32_t IRPTEN120  : 2;            /*!< [7..6] Interrupt enable for GPIO 120                                      */
11052       __IOM uint32_t OUTCFG120  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 120                             */
11053             uint32_t            : 22;
11054     } PINCFG120_b;
11055   } ;
11056 
11057   union {
11058     __IOM uint32_t PINCFG121;                   /*!< (@ 0x000001E4) Controls the operation of virtual GPIO pin 121.            */
11059 
11060     struct {
11061       __IOM uint32_t FNCSEL121  : 4;            /*!< [3..0] Function select for GPIO pin 121                                   */
11062       __IOM uint32_t INPEN121   : 1;            /*!< [4..4] Input enable for GPIO 121                                          */
11063       __IOM uint32_t RDZERO121  : 1;            /*!< [5..5] Return 0 for read data on GPIO 121                                 */
11064       __IOM uint32_t IRPTEN121  : 2;            /*!< [7..6] Interrupt enable for GPIO 121                                      */
11065       __IOM uint32_t OUTCFG121  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 121                             */
11066             uint32_t            : 22;
11067     } PINCFG121_b;
11068   } ;
11069 
11070   union {
11071     __IOM uint32_t PINCFG122;                   /*!< (@ 0x000001E8) Controls the operation of virtual GPIO pin 122.            */
11072 
11073     struct {
11074       __IOM uint32_t FNCSEL122  : 4;            /*!< [3..0] Function select for GPIO pin 122                                   */
11075       __IOM uint32_t INPEN122   : 1;            /*!< [4..4] Input enable for GPIO 122                                          */
11076       __IOM uint32_t RDZERO122  : 1;            /*!< [5..5] Return 0 for read data on GPIO 122                                 */
11077       __IOM uint32_t IRPTEN122  : 2;            /*!< [7..6] Interrupt enable for GPIO 122                                      */
11078       __IOM uint32_t OUTCFG122  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 122                             */
11079             uint32_t            : 22;
11080     } PINCFG122_b;
11081   } ;
11082 
11083   union {
11084     __IOM uint32_t PINCFG123;                   /*!< (@ 0x000001EC) Controls the operation of virtual GPIO pin 123.            */
11085 
11086     struct {
11087       __IOM uint32_t FNCSEL123  : 4;            /*!< [3..0] Function select for GPIO pin 123                                   */
11088       __IOM uint32_t INPEN123   : 1;            /*!< [4..4] Input enable for GPIO 123                                          */
11089       __IOM uint32_t RDZERO123  : 1;            /*!< [5..5] Return 0 for read data on GPIO 123                                 */
11090       __IOM uint32_t IRPTEN123  : 2;            /*!< [7..6] Interrupt enable for GPIO 123                                      */
11091       __IOM uint32_t OUTCFG123  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 123                             */
11092             uint32_t            : 22;
11093     } PINCFG123_b;
11094   } ;
11095 
11096   union {
11097     __IOM uint32_t PINCFG124;                   /*!< (@ 0x000001F0) Controls the operation of virtual GPIO pin 124.            */
11098 
11099     struct {
11100       __IOM uint32_t FNCSEL124  : 4;            /*!< [3..0] Function select for GPIO pin 124                                   */
11101       __IOM uint32_t INPEN124   : 1;            /*!< [4..4] Input enable for GPIO 124                                          */
11102       __IOM uint32_t RDZERO124  : 1;            /*!< [5..5] Return 0 for read data on GPIO 124                                 */
11103       __IOM uint32_t IRPTEN124  : 2;            /*!< [7..6] Interrupt enable for GPIO 124                                      */
11104       __IOM uint32_t OUTCFG124  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 124                             */
11105             uint32_t            : 22;
11106     } PINCFG124_b;
11107   } ;
11108 
11109   union {
11110     __IOM uint32_t PINCFG125;                   /*!< (@ 0x000001F4) Controls the operation of virtual GPIO pin 125.            */
11111 
11112     struct {
11113       __IOM uint32_t FNCSEL125  : 4;            /*!< [3..0] Function select for GPIO pin 125                                   */
11114       __IOM uint32_t INPEN125   : 1;            /*!< [4..4] Input enable for GPIO 125                                          */
11115       __IOM uint32_t RDZERO125  : 1;            /*!< [5..5] Return 0 for read data on GPIO 125                                 */
11116       __IOM uint32_t IRPTEN125  : 2;            /*!< [7..6] Interrupt enable for GPIO 125                                      */
11117       __IOM uint32_t OUTCFG125  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 125                             */
11118             uint32_t            : 22;
11119     } PINCFG125_b;
11120   } ;
11121 
11122   union {
11123     __IOM uint32_t PINCFG126;                   /*!< (@ 0x000001F8) Controls the operation of virtual GPIO pin 126.            */
11124 
11125     struct {
11126       __IOM uint32_t FNCSEL126  : 4;            /*!< [3..0] Function select for GPIO pin 126                                   */
11127       __IOM uint32_t INPEN126   : 1;            /*!< [4..4] Input enable for GPIO 126                                          */
11128       __IOM uint32_t RDZERO126  : 1;            /*!< [5..5] Return 0 for read data on GPIO 126                                 */
11129       __IOM uint32_t IRPTEN126  : 2;            /*!< [7..6] Interrupt enable for GPIO 126                                      */
11130       __IOM uint32_t OUTCFG126  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 126                             */
11131             uint32_t            : 22;
11132     } PINCFG126_b;
11133   } ;
11134 
11135   union {
11136     __IOM uint32_t PINCFG127;                   /*!< (@ 0x000001FC) Controls the operation of virtual GPIO pin 127.            */
11137 
11138     struct {
11139       __IOM uint32_t FNCSEL127  : 4;            /*!< [3..0] Function select for GPIO pin 127                                   */
11140       __IOM uint32_t INPEN127   : 1;            /*!< [4..4] Input enable for GPIO 127                                          */
11141       __IOM uint32_t RDZERO127  : 1;            /*!< [5..5] Return 0 for read data on GPIO 127                                 */
11142       __IOM uint32_t IRPTEN127  : 2;            /*!< [7..6] Interrupt enable for GPIO 127                                      */
11143       __IOM uint32_t OUTCFG127  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 127                             */
11144             uint32_t            : 22;
11145     } PINCFG127_b;
11146   } ;
11147 
11148   union {
11149     __IOM uint32_t PADKEY;                      /*!< (@ 0x00000200) Lock state of the PINCFG and GPIO configuration
11150                                                                     registers. Write a value of 0x73 to unlock
11151                                                                     write access to the PAD and GPIO.                          */
11152 
11153     struct {
11154       __IOM uint32_t PADKEY     : 32;           /*!< [31..0] Key register value.                                               */
11155     } PADKEY_b;
11156   } ;
11157 
11158   union {
11159     __IOM uint32_t RD0;                         /*!< (@ 0x00000204) GPIO Input 0 (31-0)                                        */
11160 
11161     struct {
11162       __IOM uint32_t RD0        : 32;           /*!< [31..0] GPIO31-0 Reads pin state - read only. Returns the pad
11163                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
11164                                                      is active and RDZERO is inactive.                                         */
11165     } RD0_b;
11166   } ;
11167 
11168   union {
11169     __IOM uint32_t RD1;                         /*!< (@ 0x00000208) GPIO Input 1 (63-32)                                       */
11170 
11171     struct {
11172       __IOM uint32_t RD1        : 32;           /*!< [31..0] GPIO63-32 Reads pin state - read only. Returns the pad
11173                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
11174                                                      is active and RDZERO is inactive.                                         */
11175     } RD1_b;
11176   } ;
11177 
11178   union {
11179     __IOM uint32_t RD2;                         /*!< (@ 0x0000020C) GPIO Input 2 (95-64)                                       */
11180 
11181     struct {
11182       __IOM uint32_t RD2        : 32;           /*!< [31..0] GPIO95-64 Reads pin state - read only. Returns the pad
11183                                                      pin state for pins 0-31 if the PINCFG's input enable (INPEN)
11184                                                      is active and RDZERO is inactive.                                         */
11185     } RD2_b;
11186   } ;
11187 
11188   union {
11189     __IOM uint32_t RD3;                         /*!< (@ 0x00000210) GPIO Input 3 (127-96)                                      */
11190 
11191     struct {
11192       __IOM uint32_t RD3        : 32;           /*!< [31..0] GPIO127-96 Reads pin state - read only. Returns the
11193                                                      pad pin state for pins 0-31 if the PINCFG's input enable
11194                                                      (INPEN) is active and RDZERO is inactive.                                 */
11195     } RD3_b;
11196   } ;
11197 
11198   union {
11199     __IOM uint32_t WT0;                         /*!< (@ 0x00000214) GPIO Output 0 (31-0)                                       */
11200 
11201     struct {
11202       __IOM uint32_t WT0        : 32;           /*!< [31..0] GPIO31-0 Reads or writes pin state. Writes of 1 bits
11203                                                      set output pad signal if the GPIO is enabled for output.
11204                                                      Reads return status, including sets/clears through the
11205                                                      WTS and WTC registers.                                                    */
11206     } WT0_b;
11207   } ;
11208 
11209   union {
11210     __IOM uint32_t WT1;                         /*!< (@ 0x00000218) GPIO Output 1 (63-32)                                      */
11211 
11212     struct {
11213       __IOM uint32_t WT1        : 32;           /*!< [31..0] GPIO63-32 Reads or writes pin state. Writes of 1 bits
11214                                                      set output pad signal if the GPIO is enabled for output.
11215                                                      Reads return status, including sets/clears through the
11216                                                      WTS and WTC registers.                                                    */
11217     } WT1_b;
11218   } ;
11219 
11220   union {
11221     __IOM uint32_t WT2;                         /*!< (@ 0x0000021C) GPIO Output 2 (95-64)                                      */
11222 
11223     struct {
11224       __IOM uint32_t WT2        : 32;           /*!< [31..0] GPIO95-64 Reads or writes pin state. Writes of 1 bits
11225                                                      set output pad signal if the GPIO is enabled for output.
11226                                                      Reads return status, including sets/clears through the
11227                                                      WTS and WTC registers.                                                    */
11228     } WT2_b;
11229   } ;
11230 
11231   union {
11232     __IOM uint32_t WT3;                         /*!< (@ 0x00000220) GPIO Output 3 (127-96)                                     */
11233 
11234     struct {
11235       __IOM uint32_t WT3        : 32;           /*!< [31..0] GPIO127-96 Reads or writes pin state. Writes of 1 bits
11236                                                      set output pad signal if the GPIO is enabled for output.
11237                                                      Reads return status, including sets/clears through the
11238                                                      WTS and WTC registers.                                                    */
11239     } WT3_b;
11240   } ;
11241 
11242   union {
11243     __IOM uint32_t WTS0;                        /*!< (@ 0x00000224) GPIO Output Set 0 (31-0)                                   */
11244 
11245     struct {
11246       __IOM uint32_t WTS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin state. Writing a 1 to any bit sets
11247                                                      the corresponding bit in the WT register if the GPIO is
11248                                                      enabled for output. Writing a value of 0 has no effect
11249                                                      on the corresponding bit in the WT register. Status reads
11250                                                      should be made via the WT Register.                                       */
11251     } WTS0_b;
11252   } ;
11253 
11254   union {
11255     __IOM uint32_t WTS1;                        /*!< (@ 0x00000228) GPIO Output Set 1 (63-32)                                  */
11256 
11257     struct {
11258       __IOM uint32_t WTS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin state. Writing a 1 to any bit sets
11259                                                      the corresponding bit in the WT register if the GPIO is
11260                                                      enabled for output. Writing a value of 0 has no effect
11261                                                      on the corresponding bit in the WT register. Status reads
11262                                                      should be made via the WT Register.                                       */
11263     } WTS1_b;
11264   } ;
11265 
11266   union {
11267     __IOM uint32_t WTS2;                        /*!< (@ 0x0000022C) GPIO Output Set 2 (95-64)                                  */
11268 
11269     struct {
11270       __IOM uint32_t WTS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin state. Writing a 1 to any bit sets
11271                                                      the corresponding bit in the WT register if the GPIO is
11272                                                      enabled for output. Writing a value of 0 has no effect
11273                                                      on the corresponding bit in the WT register. Status reads
11274                                                      should be made via the WT Register.                                       */
11275     } WTS2_b;
11276   } ;
11277 
11278   union {
11279     __IOM uint32_t WTS3;                        /*!< (@ 0x00000230) GPIO Output Set 3 (127-96)                                 */
11280 
11281     struct {
11282       __IOM uint32_t WTS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin state. Writing a 1 to any bit sets
11283                                                      the corresponding bit in the WT register if the GPIO is
11284                                                      enabled for output. Writing a value of 0 has no effect
11285                                                      on the corresponding bit in the WT register. Status reads
11286                                                      should be made via the WT Register.                                       */
11287     } WTS3_b;
11288   } ;
11289 
11290   union {
11291     __IOM uint32_t WTC0;                        /*!< (@ 0x00000234) GPIO Output Clear 0 (31-0)                                 */
11292 
11293     struct {
11294       __IOM uint32_t WTC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin state. Writing a 1 to any bit clears
11295                                                      the corresponding bit in the WT register if the GPIO is
11296                                                      enabled for output. Writing a value of 0 has no effect
11297                                                      on the corresponding bit in the WT register. Status reads
11298                                                      should be made via the WT register.                                       */
11299     } WTC0_b;
11300   } ;
11301 
11302   union {
11303     __IOM uint32_t WTC1;                        /*!< (@ 0x00000238) GPIO Output Clear 1 (63-32)                                */
11304 
11305     struct {
11306       __IOM uint32_t WTC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin state. Writing a 1 to any bit clears
11307                                                      the corresponding bit in the WT register if the GPIO is
11308                                                      enabled for output. Writing a value of 0 has no effect
11309                                                      on the corresponding bit in the WT register. Status reads
11310                                                      should be made via the WT register.                                       */
11311     } WTC1_b;
11312   } ;
11313 
11314   union {
11315     __IOM uint32_t WTC2;                        /*!< (@ 0x0000023C) GPIO Output Clear 2 (95-64)                                */
11316 
11317     struct {
11318       __IOM uint32_t WTC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin state. Writing a 1 to any bit clears
11319                                                      the corresponding bit in the WT register if the GPIO is
11320                                                      enabled for output. Writing a value of 0 has no effect
11321                                                      on the corresponding bit in the WT register. Status reads
11322                                                      should be made via the WT register.                                       */
11323     } WTC2_b;
11324   } ;
11325 
11326   union {
11327     __IOM uint32_t WTC3;                        /*!< (@ 0x00000240) GPIO Output Clear 3 (127-96)                               */
11328 
11329     struct {
11330       __IOM uint32_t WTC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin state. Writing a 1 to any bit
11331                                                      clears the corresponding bit in the WT register if the
11332                                                      GPIO is enabled for output. Writing a value of 0 has no
11333                                                      effect on the corresponding bit in the WT register. Status
11334                                                      reads should be made via the WT register.                                 */
11335     } WTC3_b;
11336   } ;
11337 
11338   union {
11339     __IOM uint32_t EN0;                         /*!< (@ 0x00000244) GPIO Enable 0 (31-0)                                       */
11340 
11341     struct {
11342       __IOM uint32_t EN0        : 32;           /*!< [31..0] GPIO31-0 Enables tri-state pin output. Writing a 1 to
11343                                                      any bit enables, and writing a 0 to any bit disables, the
11344                                                      output for the corresponding GPIO. Reads return output
11345                                                      enable/disable status of GPIO.                                            */
11346     } EN0_b;
11347   } ;
11348 
11349   union {
11350     __IOM uint32_t EN1;                         /*!< (@ 0x00000248) GPIO Enable 1 (63-32)                                      */
11351 
11352     struct {
11353       __IOM uint32_t EN1        : 32;           /*!< [31..0] GPIO63-32 Enables tri-state pin output. Writing a 1
11354                                                      to any bit enables, and writing a 0 to any bit disables,
11355                                                      the output for the corresponding GPIO. Reads return output
11356                                                      enable/disable status of GPIO.                                            */
11357     } EN1_b;
11358   } ;
11359 
11360   union {
11361     __IOM uint32_t EN2;                         /*!< (@ 0x0000024C) GPIO Enable 2 (95-64)                                      */
11362 
11363     struct {
11364       __IOM uint32_t EN2        : 32;           /*!< [31..0] GPIO95-64 Enables tri-state pin output. Writing a 1
11365                                                      to any bit enables, and writing a 0 to any bit disables,
11366                                                      the output for the corresponding GPIO. Reads return output
11367                                                      enable/disable status of GPIO.                                            */
11368     } EN2_b;
11369   } ;
11370 
11371   union {
11372     __IOM uint32_t EN3;                         /*!< (@ 0x00000250) GPIO Enable 3 (127-96)                                     */
11373 
11374     struct {
11375       __IOM uint32_t EN3        : 32;           /*!< [31..0] GPIO127-96 Enables tri-state pin output. Writing a 1
11376                                                      to any bit enables, and writing a 0 to any bit disables,
11377                                                      the output for the corresponding GPIO. Reads return output
11378                                                      enable/disable status of GPIO.                                            */
11379     } EN3_b;
11380   } ;
11381 
11382   union {
11383     __IOM uint32_t ENS0;                        /*!< (@ 0x00000254) GPIO Enable Set 0 (31-0)                                   */
11384 
11385     struct {
11386       __IOM uint32_t ENS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin tri-state output enables. Writing
11387                                                      a 1 to any bit sets the corresponding bit in the EN register.
11388                                                      Writing a value of 0 has no effect on the corresponding
11389                                                      bit in the EN register. Status reads should be made to
11390                                                      the EN Register.                                                          */
11391     } ENS0_b;
11392   } ;
11393 
11394   union {
11395     __IOM uint32_t ENS1;                        /*!< (@ 0x00000258) GPIO Enable Set 1 (63-32)                                  */
11396 
11397     struct {
11398       __IOM uint32_t ENS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin tri-state output enables. Writing
11399                                                      a 1 to any bit sets the corresponding bit in the EN register.
11400                                                      Writing a value of 0 has no effect on the corresponding
11401                                                      bit in the EN register. Status reads should be made to
11402                                                      the EN Register.                                                          */
11403     } ENS1_b;
11404   } ;
11405 
11406   union {
11407     __IOM uint32_t ENS2;                        /*!< (@ 0x0000025C) GPIO Enable Set 2 (95-64)                                  */
11408 
11409     struct {
11410       __IOM uint32_t ENS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin tri-state output enables. Writing
11411                                                      a 1 to any bit sets the corresponding bit in the EN register.
11412                                                      Writing a value of 0 has no effect on the corresponding
11413                                                      bit in the EN register. Status reads should be made to
11414                                                      the EN Register.                                                          */
11415     } ENS2_b;
11416   } ;
11417 
11418   union {
11419     __IOM uint32_t ENS3;                        /*!< (@ 0x00000260) GPIO Enable Set 3 (127-96)                                 */
11420 
11421     struct {
11422       __IOM uint32_t ENS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin tri-state output enables. Writing
11423                                                      a 1 to any bit sets the corresponding bit in the EN register.
11424                                                      Writing a value of 0 has no effect on the corresponding
11425                                                      bit in the EN register. Status reads should be made to
11426                                                      the EN Register.                                                          */
11427     } ENS3_b;
11428   } ;
11429 
11430   union {
11431     __IOM uint32_t ENC0;                        /*!< (@ 0x00000264) GPIO Enable Clear 0 (31-0)                                 */
11432 
11433     struct {
11434       __IOM uint32_t ENC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin tri-state output enables. Writing
11435                                                      a 1 to any bit clears the corresponding bit in the EN register.
11436                                                      Writing a value of 0 has no effect on the corresponding
11437                                                      bit in the EN register. Status reads should be made to
11438                                                      the EN Register.                                                          */
11439     } ENC0_b;
11440   } ;
11441 
11442   union {
11443     __IOM uint32_t ENC1;                        /*!< (@ 0x00000268) GPIO Enable Clear 1 (63-32)                                */
11444 
11445     struct {
11446       __IOM uint32_t ENC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin tri-state output enables. Writing
11447                                                      a 1 to any bit clears the corresponding bit in the EN register.
11448                                                      Writing a value of 0 has no effect on the corresponding
11449                                                      bit in the EN register. Status reads should be made to
11450                                                      the EN Register.                                                          */
11451     } ENC1_b;
11452   } ;
11453 
11454   union {
11455     __IOM uint32_t ENC2;                        /*!< (@ 0x0000026C) GPIO Enable Clear 2 (95-64)                                */
11456 
11457     struct {
11458       __IOM uint32_t ENC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin tri-state output enables. Writing
11459                                                      a 1 to any bit clears the corresponding bit in the EN register.
11460                                                      Writing a value of 0 has no effect on the corresponding
11461                                                      bit in the EN register. Status reads should be made to
11462                                                      the EN Register.                                                          */
11463     } ENC2_b;
11464   } ;
11465 
11466   union {
11467     __IOM uint32_t ENC3;                        /*!< (@ 0x00000270) GPIO Enable Clear 3 (127-96)                               */
11468 
11469     struct {
11470       __IOM uint32_t ENC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin tri-state output enables. Writing
11471                                                      a 1 to any bit clears the corresponding bit in the EN register.
11472                                                      Writing a value of 0 has no effect on the corresponding
11473                                                      bit in the EN register. Status reads should be made to
11474                                                      the EN Register.                                                          */
11475     } ENC3_b;
11476   } ;
11477 
11478   union {
11479     __IOM uint32_t IOM0IRQ;                     /*!< (@ 0x00000274) IOM0 IRQ select for flow control.                          */
11480 
11481     struct {
11482       __IOM uint32_t IOM0IRQ    : 7;            /*!< [6..0] IOM0 IRQ pad select.                                               */
11483             uint32_t            : 25;
11484     } IOM0IRQ_b;
11485   } ;
11486 
11487   union {
11488     __IOM uint32_t IOM1IRQ;                     /*!< (@ 0x00000278) IOM1 IRQ select for flow control.                          */
11489 
11490     struct {
11491       __IOM uint32_t IOM1IRQ    : 7;            /*!< [6..0] IOM1 IRQ pad select.                                               */
11492             uint32_t            : 25;
11493     } IOM1IRQ_b;
11494   } ;
11495 
11496   union {
11497     __IOM uint32_t IOM2IRQ;                     /*!< (@ 0x0000027C) IOM2 IRQ select for flow control.                          */
11498 
11499     struct {
11500       __IOM uint32_t IOM2IRQ    : 7;            /*!< [6..0] IOM2 IRQ pad select.                                               */
11501             uint32_t            : 25;
11502     } IOM2IRQ_b;
11503   } ;
11504 
11505   union {
11506     __IOM uint32_t IOM3IRQ;                     /*!< (@ 0x00000280) IOM3 IRQ select for flow control.                          */
11507 
11508     struct {
11509       __IOM uint32_t IOM3IRQ    : 7;            /*!< [6..0] IOM3 IRQ pad select.                                               */
11510             uint32_t            : 25;
11511     } IOM3IRQ_b;
11512   } ;
11513 
11514   union {
11515     __IOM uint32_t IOM4IRQ;                     /*!< (@ 0x00000284) IOM4 IRQ select for flow control.                          */
11516 
11517     struct {
11518       __IOM uint32_t IOM4IRQ    : 7;            /*!< [6..0] IOM4 IRQ pad select.                                               */
11519             uint32_t            : 25;
11520     } IOM4IRQ_b;
11521   } ;
11522 
11523   union {
11524     __IOM uint32_t IOM5IRQ;                     /*!< (@ 0x00000288) IOM5 IRQ select for flow control.                          */
11525 
11526     struct {
11527       __IOM uint32_t IOM5IRQ    : 7;            /*!< [6..0] IOM5 IRQ pad select.                                               */
11528             uint32_t            : 25;
11529     } IOM5IRQ_b;
11530   } ;
11531 
11532   union {
11533     __IOM uint32_t IOM6IRQ;                     /*!< (@ 0x0000028C) IOM6 IRQ select for flow control.                          */
11534 
11535     struct {
11536       __IOM uint32_t IOM6IRQ    : 7;            /*!< [6..0] IOM6 IRQ pad select.                                               */
11537             uint32_t            : 25;
11538     } IOM6IRQ_b;
11539   } ;
11540 
11541   union {
11542     __IOM uint32_t IOM7IRQ;                     /*!< (@ 0x00000290) IOM7 IRQ select for flow control.                          */
11543 
11544     struct {
11545       __IOM uint32_t IOM7IRQ    : 7;            /*!< [6..0] IOM7 IRQ pad select.                                               */
11546             uint32_t            : 25;
11547     } IOM7IRQ_b;
11548   } ;
11549 
11550   union {
11551     __IOM uint32_t SDIFCDWP;                    /*!< (@ 0x00000294) SDIF CD and WP Select.                                     */
11552 
11553     struct {
11554       __IOM uint32_t SDIFCD     : 7;            /*!< [6..0] SDIF CD pad select.                                                */
11555             uint32_t            : 1;
11556       __IOM uint32_t SDIFWP     : 7;            /*!< [14..8] SDIF WP pad select.                                               */
11557             uint32_t            : 17;
11558     } SDIFCDWP_b;
11559   } ;
11560 
11561   union {
11562     __IOM uint32_t OBSDATA;                     /*!< (@ 0x00000298) GPIO Observation mode sample                               */
11563 
11564     struct {
11565       __IOM uint32_t OBSDATA    : 16;           /*!< [15..0] Sample of the data output on the GPIO observation port.
11566                                                      May have async sampling issues, as the data is not synronized
11567                                                      to the read operation. Intended for debug purposes only.                  */
11568             uint32_t            : 16;
11569     } OBSDATA_b;
11570   } ;
11571 
11572   union {
11573     __IOM uint32_t IEOBS0;                      /*!< (@ 0x0000029C) Read only. Reflects the value of the input enable
11574                                                                     signals for pads 31-0 sent to the pad.                     */
11575 
11576     struct {
11577       __IOM uint32_t IEDATA0    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
11578                                                      the pad will be trasmitted to the internal logic within
11579                                                      the device.                                                               */
11580     } IEOBS0_b;
11581   } ;
11582 
11583   union {
11584     __IOM uint32_t IEOBS1;                      /*!< (@ 0x000002A0) Read only. Reflects the value of the input enable
11585                                                                     signals for pads 63-32 sent to the pad.                    */
11586 
11587     struct {
11588       __IOM uint32_t IEDATA1    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
11589                                                      the pad will be trasmitted to the internal logic within
11590                                                      the device.                                                               */
11591     } IEOBS1_b;
11592   } ;
11593 
11594   union {
11595     __IOM uint32_t IEOBS2;                      /*!< (@ 0x000002A4) Read only. Reflects the value of the input enable
11596                                                                     signals for pads 95-64 sent to the pad.                    */
11597 
11598     struct {
11599       __IOM uint32_t IEDATA2    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
11600                                                      the pad will be trasmitted to the internal logic within
11601                                                      the device.                                                               */
11602     } IEOBS2_b;
11603   } ;
11604 
11605   union {
11606     __IOM uint32_t IEOBS3;                      /*!< (@ 0x000002A8) Read only. Reflects the value of the input enable
11607                                                                     signals for pads 127-96 sent to the pad.                   */
11608 
11609     struct {
11610       __IOM uint32_t IEDATA3    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
11611                                                      the pad will be trasmitted to the internal logic within
11612                                                      the device.                                                               */
11613     } IEOBS3_b;
11614   } ;
11615 
11616   union {
11617     __IOM uint32_t OEOBS0;                      /*!< (@ 0x000002AC) Read only. Reflects the value of the output enable
11618                                                                     signals for pads 31-0 sent to the pad.                     */
11619 
11620     struct {
11621       __IOM uint32_t OEDATA0    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
11622                                                      the output_en_ is active and the MCU will be driving the
11623                                                      pad.                                                                      */
11624     } OEOBS0_b;
11625   } ;
11626 
11627   union {
11628     __IOM uint32_t OEOBS1;                      /*!< (@ 0x000002B0) Read only. Reflects the value of the output enable
11629                                                                     signals for pads 63-32 sent to the pad.                    */
11630 
11631     struct {
11632       __IOM uint32_t OEDATA1    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
11633                                                      the output_en_ is active and the MCU will be driving the
11634                                                      pad.                                                                      */
11635     } OEOBS1_b;
11636   } ;
11637 
11638   union {
11639     __IOM uint32_t OEOBS2;                      /*!< (@ 0x000002B4) Read only. Reflects the value of the output enable
11640                                                                     signals for pads 95-64 sent to the pad.                    */
11641 
11642     struct {
11643       __IOM uint32_t OEDATA2    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
11644                                                      the output_en_ is active and the MCU will be driving the
11645                                                      pad.                                                                      */
11646     } OEOBS2_b;
11647   } ;
11648 
11649   union {
11650     __IOM uint32_t OEOBS3;                      /*!< (@ 0x000002B8) Read only. Reflects the value of the output enable
11651                                                                     signals for pads 127-96 sent to the pad.                   */
11652 
11653     struct {
11654       __IOM uint32_t OEDATA3    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
11655                                                      the output_en_ is active and the MCU will be driving the
11656                                                      pad.                                                                      */
11657     } OEOBS3_b;
11658   } ;
11659   __IM  uint32_t  RESERVED;
11660 
11661   union {
11662     __IOM uint32_t MCUN0INT0EN;                 /*!< (@ 0x000002C0) Set bits in this register to allow this module
11663                                                                     to generate the corresponding interrupt.                   */
11664 
11665     struct {
11666       __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
11667       __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
11668       __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
11669       __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
11670       __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
11671       __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
11672       __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
11673       __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
11674       __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
11675       __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
11676       __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
11677       __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
11678       __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
11679       __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
11680       __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
11681       __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
11682       __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
11683       __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
11684       __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
11685       __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
11686       __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
11687       __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
11688       __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
11689       __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
11690       __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
11691       __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
11692       __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
11693       __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
11694       __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
11695       __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
11696       __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
11697       __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
11698     } MCUN0INT0EN_b;
11699   } ;
11700 
11701   union {
11702     __IOM uint32_t MCUN0INT0STAT;               /*!< (@ 0x000002C4) Read bits from this register to discover the
11703                                                                     cause of a recent interrupt.                               */
11704 
11705     struct {
11706       __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
11707       __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
11708       __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
11709       __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
11710       __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
11711       __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
11712       __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
11713       __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
11714       __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
11715       __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
11716       __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
11717       __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
11718       __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
11719       __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
11720       __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
11721       __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
11722       __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
11723       __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
11724       __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
11725       __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
11726       __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
11727       __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
11728       __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
11729       __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
11730       __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
11731       __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
11732       __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
11733       __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
11734       __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
11735       __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
11736       __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
11737       __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
11738     } MCUN0INT0STAT_b;
11739   } ;
11740 
11741   union {
11742     __IOM uint32_t MCUN0INT0CLR;                /*!< (@ 0x000002C8) Write a 1 to a bit in this register to clear
11743                                                                     the interrupt status associated with that
11744                                                                     bit.                                                       */
11745 
11746     struct {
11747       __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
11748       __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
11749       __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
11750       __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
11751       __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
11752       __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
11753       __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
11754       __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
11755       __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
11756       __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
11757       __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
11758       __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
11759       __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
11760       __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
11761       __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
11762       __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
11763       __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
11764       __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
11765       __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
11766       __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
11767       __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
11768       __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
11769       __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
11770       __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
11771       __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
11772       __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
11773       __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
11774       __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
11775       __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
11776       __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
11777       __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
11778       __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
11779     } MCUN0INT0CLR_b;
11780   } ;
11781 
11782   union {
11783     __IOM uint32_t MCUN0INT0SET;                /*!< (@ 0x000002CC) Write a 1 to a bit in this register to instantly
11784                                                                     generate an interrupt from this module.
11785                                                                     (Generally used for testing purposes).                     */
11786 
11787     struct {
11788       __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
11789       __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
11790       __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
11791       __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
11792       __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
11793       __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
11794       __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
11795       __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
11796       __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
11797       __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
11798       __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
11799       __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
11800       __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
11801       __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
11802       __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
11803       __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
11804       __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
11805       __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
11806       __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
11807       __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
11808       __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
11809       __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
11810       __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
11811       __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
11812       __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
11813       __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
11814       __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
11815       __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
11816       __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
11817       __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
11818       __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
11819       __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
11820     } MCUN0INT0SET_b;
11821   } ;
11822 
11823   union {
11824     __IOM uint32_t MCUN0INT1EN;                 /*!< (@ 0x000002D0) Set bits in this register to allow this module
11825                                                                     to generate the corresponding interrupt.                   */
11826 
11827     struct {
11828       __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
11829       __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
11830       __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
11831       __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
11832       __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
11833       __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
11834       __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
11835       __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
11836       __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
11837       __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
11838       __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
11839       __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
11840       __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
11841       __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
11842       __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
11843       __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
11844       __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
11845       __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
11846       __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
11847       __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
11848       __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
11849       __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
11850       __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
11851       __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
11852       __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
11853       __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
11854       __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
11855       __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
11856       __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
11857       __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
11858       __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
11859       __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
11860     } MCUN0INT1EN_b;
11861   } ;
11862 
11863   union {
11864     __IOM uint32_t MCUN0INT1STAT;               /*!< (@ 0x000002D4) Read bits from this register to discover the
11865                                                                     cause of a recent interrupt.                               */
11866 
11867     struct {
11868       __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
11869       __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
11870       __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
11871       __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
11872       __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
11873       __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
11874       __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
11875       __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
11876       __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
11877       __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
11878       __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
11879       __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
11880       __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
11881       __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
11882       __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
11883       __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
11884       __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
11885       __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
11886       __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
11887       __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
11888       __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
11889       __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
11890       __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
11891       __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
11892       __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
11893       __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
11894       __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
11895       __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
11896       __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
11897       __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
11898       __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
11899       __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
11900     } MCUN0INT1STAT_b;
11901   } ;
11902 
11903   union {
11904     __IOM uint32_t MCUN0INT1CLR;                /*!< (@ 0x000002D8) Write a 1 to a bit in this register to clear
11905                                                                     the interrupt status associated with that
11906                                                                     bit.                                                       */
11907 
11908     struct {
11909       __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
11910       __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
11911       __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
11912       __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
11913       __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
11914       __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
11915       __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
11916       __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
11917       __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
11918       __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
11919       __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
11920       __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
11921       __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
11922       __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
11923       __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
11924       __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
11925       __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
11926       __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
11927       __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
11928       __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
11929       __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
11930       __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
11931       __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
11932       __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
11933       __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
11934       __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
11935       __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
11936       __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
11937       __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
11938       __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
11939       __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
11940       __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
11941     } MCUN0INT1CLR_b;
11942   } ;
11943 
11944   union {
11945     __IOM uint32_t MCUN0INT1SET;                /*!< (@ 0x000002DC) Write a 1 to a bit in this register to instantly
11946                                                                     generate an interrupt from this module.
11947                                                                     (Generally used for testing purposes).                     */
11948 
11949     struct {
11950       __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
11951       __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
11952       __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
11953       __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
11954       __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
11955       __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
11956       __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
11957       __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
11958       __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
11959       __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
11960       __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
11961       __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
11962       __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
11963       __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
11964       __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
11965       __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
11966       __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
11967       __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
11968       __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
11969       __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
11970       __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
11971       __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
11972       __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
11973       __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
11974       __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
11975       __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
11976       __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
11977       __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
11978       __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
11979       __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
11980       __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
11981       __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
11982     } MCUN0INT1SET_b;
11983   } ;
11984 
11985   union {
11986     __IOM uint32_t MCUN0INT2EN;                 /*!< (@ 0x000002E0) Set bits in this register to allow this module
11987                                                                     to generate the corresponding interrupt.                   */
11988 
11989     struct {
11990       __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
11991       __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
11992       __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
11993       __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
11994       __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
11995       __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
11996       __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
11997       __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
11998       __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
11999       __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
12000       __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
12001       __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
12002       __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
12003       __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
12004       __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
12005       __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
12006       __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
12007       __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
12008       __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
12009       __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
12010       __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
12011       __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
12012       __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
12013       __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
12014       __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
12015       __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
12016       __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
12017       __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
12018       __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
12019       __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
12020       __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
12021       __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
12022     } MCUN0INT2EN_b;
12023   } ;
12024 
12025   union {
12026     __IOM uint32_t MCUN0INT2STAT;               /*!< (@ 0x000002E4) Read bits from this register to discover the
12027                                                                     cause of a recent interrupt.                               */
12028 
12029     struct {
12030       __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
12031       __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
12032       __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
12033       __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
12034       __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
12035       __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
12036       __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
12037       __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
12038       __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
12039       __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
12040       __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
12041       __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
12042       __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
12043       __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
12044       __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
12045       __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
12046       __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
12047       __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
12048       __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
12049       __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
12050       __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
12051       __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
12052       __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
12053       __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
12054       __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
12055       __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
12056       __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
12057       __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
12058       __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
12059       __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
12060       __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
12061       __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
12062     } MCUN0INT2STAT_b;
12063   } ;
12064 
12065   union {
12066     __IOM uint32_t MCUN0INT2CLR;                /*!< (@ 0x000002E8) Write a 1 to a bit in this register to clear
12067                                                                     the interrupt status associated with that
12068                                                                     bit.                                                       */
12069 
12070     struct {
12071       __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
12072       __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
12073       __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
12074       __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
12075       __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
12076       __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
12077       __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
12078       __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
12079       __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
12080       __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
12081       __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
12082       __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
12083       __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
12084       __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
12085       __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
12086       __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
12087       __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
12088       __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
12089       __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
12090       __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
12091       __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
12092       __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
12093       __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
12094       __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
12095       __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
12096       __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
12097       __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
12098       __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
12099       __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
12100       __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
12101       __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
12102       __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
12103     } MCUN0INT2CLR_b;
12104   } ;
12105 
12106   union {
12107     __IOM uint32_t MCUN0INT2SET;                /*!< (@ 0x000002EC) Write a 1 to a bit in this register to instantly
12108                                                                     generate an interrupt from this module.
12109                                                                     (Generally used for testing purposes).                     */
12110 
12111     struct {
12112       __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
12113       __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
12114       __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
12115       __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
12116       __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
12117       __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
12118       __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
12119       __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
12120       __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
12121       __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
12122       __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
12123       __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
12124       __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
12125       __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
12126       __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
12127       __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
12128       __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
12129       __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
12130       __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
12131       __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
12132       __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
12133       __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
12134       __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
12135       __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
12136       __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
12137       __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
12138       __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
12139       __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
12140       __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
12141       __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
12142       __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
12143       __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
12144     } MCUN0INT2SET_b;
12145   } ;
12146 
12147   union {
12148     __IOM uint32_t MCUN0INT3EN;                 /*!< (@ 0x000002F0) Set bits in this register to allow this module
12149                                                                     to generate the corresponding interrupt.                   */
12150 
12151     struct {
12152       __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
12153       __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
12154       __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
12155       __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
12156       __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
12157       __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
12158       __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
12159       __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
12160       __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
12161       __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
12162       __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
12163       __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
12164       __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
12165       __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
12166       __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
12167       __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
12168       __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
12169       __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
12170       __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
12171       __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
12172       __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
12173       __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
12174       __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
12175       __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
12176       __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
12177       __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
12178       __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
12179       __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
12180       __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
12181       __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
12182       __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
12183       __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
12184     } MCUN0INT3EN_b;
12185   } ;
12186 
12187   union {
12188     __IOM uint32_t MCUN0INT3STAT;               /*!< (@ 0x000002F4) Read bits from this register to discover the
12189                                                                     cause of a recent interrupt.                               */
12190 
12191     struct {
12192       __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
12193       __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
12194       __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
12195       __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
12196       __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
12197       __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
12198       __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
12199       __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
12200       __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
12201       __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
12202       __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
12203       __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
12204       __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
12205       __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
12206       __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
12207       __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
12208       __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
12209       __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
12210       __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
12211       __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
12212       __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
12213       __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
12214       __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
12215       __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
12216       __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
12217       __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
12218       __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
12219       __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
12220       __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
12221       __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
12222       __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
12223       __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
12224     } MCUN0INT3STAT_b;
12225   } ;
12226 
12227   union {
12228     __IOM uint32_t MCUN0INT3CLR;                /*!< (@ 0x000002F8) Write a 1 to a bit in this register to clear
12229                                                                     the interrupt status associated with that
12230                                                                     bit.                                                       */
12231 
12232     struct {
12233       __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
12234       __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
12235       __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
12236       __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
12237       __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
12238       __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
12239       __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
12240       __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
12241       __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
12242       __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
12243       __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
12244       __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
12245       __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
12246       __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
12247       __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
12248       __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
12249       __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
12250       __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
12251       __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
12252       __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
12253       __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
12254       __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
12255       __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
12256       __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
12257       __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
12258       __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
12259       __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
12260       __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
12261       __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
12262       __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
12263       __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
12264       __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
12265     } MCUN0INT3CLR_b;
12266   } ;
12267 
12268   union {
12269     __IOM uint32_t MCUN0INT3SET;                /*!< (@ 0x000002FC) Write a 1 to a bit in this register to instantly
12270                                                                     generate an interrupt from this module.
12271                                                                     (Generally used for testing purposes).                     */
12272 
12273     struct {
12274       __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
12275       __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
12276       __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
12277       __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
12278       __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
12279       __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
12280       __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
12281       __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
12282       __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
12283       __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
12284       __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
12285       __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
12286       __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
12287       __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
12288       __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
12289       __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
12290       __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
12291       __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
12292       __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
12293       __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
12294       __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
12295       __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
12296       __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
12297       __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
12298       __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
12299       __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
12300       __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
12301       __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
12302       __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
12303       __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
12304       __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
12305       __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
12306     } MCUN0INT3SET_b;
12307   } ;
12308 
12309   union {
12310     __IOM uint32_t MCUN1INT0EN;                 /*!< (@ 0x00000300) Set bits in this register to allow this module
12311                                                                     to generate the corresponding interrupt.                   */
12312 
12313     struct {
12314       __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
12315       __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
12316       __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
12317       __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
12318       __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
12319       __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
12320       __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
12321       __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
12322       __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
12323       __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
12324       __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
12325       __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
12326       __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
12327       __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
12328       __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
12329       __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
12330       __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
12331       __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
12332       __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
12333       __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
12334       __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
12335       __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
12336       __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
12337       __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
12338       __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
12339       __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
12340       __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
12341       __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
12342       __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
12343       __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
12344       __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
12345       __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
12346     } MCUN1INT0EN_b;
12347   } ;
12348 
12349   union {
12350     __IOM uint32_t MCUN1INT0STAT;               /*!< (@ 0x00000304) Read bits from this register to discover the
12351                                                                     cause of a recent interrupt.                               */
12352 
12353     struct {
12354       __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
12355       __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
12356       __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
12357       __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
12358       __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
12359       __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
12360       __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
12361       __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
12362       __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
12363       __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
12364       __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
12365       __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
12366       __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
12367       __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
12368       __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
12369       __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
12370       __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
12371       __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
12372       __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
12373       __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
12374       __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
12375       __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
12376       __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
12377       __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
12378       __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
12379       __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
12380       __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
12381       __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
12382       __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
12383       __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
12384       __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
12385       __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
12386     } MCUN1INT0STAT_b;
12387   } ;
12388 
12389   union {
12390     __IOM uint32_t MCUN1INT0CLR;                /*!< (@ 0x00000308) Write a 1 to a bit in this register to clear
12391                                                                     the interrupt status associated with that
12392                                                                     bit.                                                       */
12393 
12394     struct {
12395       __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
12396       __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
12397       __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
12398       __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
12399       __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
12400       __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
12401       __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
12402       __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
12403       __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
12404       __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
12405       __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
12406       __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
12407       __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
12408       __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
12409       __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
12410       __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
12411       __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
12412       __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
12413       __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
12414       __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
12415       __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
12416       __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
12417       __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
12418       __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
12419       __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
12420       __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
12421       __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
12422       __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
12423       __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
12424       __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
12425       __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
12426       __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
12427     } MCUN1INT0CLR_b;
12428   } ;
12429 
12430   union {
12431     __IOM uint32_t MCUN1INT0SET;                /*!< (@ 0x0000030C) Write a 1 to a bit in this register to instantly
12432                                                                     generate an interrupt from this module.
12433                                                                     (Generally used for testing purposes).                     */
12434 
12435     struct {
12436       __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
12437       __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
12438       __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
12439       __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
12440       __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
12441       __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
12442       __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
12443       __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
12444       __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
12445       __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
12446       __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
12447       __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
12448       __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
12449       __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
12450       __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
12451       __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
12452       __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
12453       __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
12454       __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
12455       __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
12456       __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
12457       __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
12458       __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
12459       __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
12460       __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
12461       __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
12462       __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
12463       __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
12464       __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
12465       __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
12466       __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
12467       __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
12468     } MCUN1INT0SET_b;
12469   } ;
12470 
12471   union {
12472     __IOM uint32_t MCUN1INT1EN;                 /*!< (@ 0x00000310) Set bits in this register to allow this module
12473                                                                     to generate the corresponding interrupt.                   */
12474 
12475     struct {
12476       __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
12477       __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
12478       __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
12479       __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
12480       __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
12481       __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
12482       __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
12483       __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
12484       __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
12485       __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
12486       __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
12487       __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
12488       __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
12489       __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
12490       __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
12491       __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
12492       __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
12493       __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
12494       __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
12495       __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
12496       __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
12497       __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
12498       __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
12499       __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
12500       __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
12501       __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
12502       __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
12503       __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
12504       __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
12505       __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
12506       __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
12507       __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
12508     } MCUN1INT1EN_b;
12509   } ;
12510 
12511   union {
12512     __IOM uint32_t MCUN1INT1STAT;               /*!< (@ 0x00000314) Read bits from this register to discover the
12513                                                                     cause of a recent interrupt.                               */
12514 
12515     struct {
12516       __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
12517       __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
12518       __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
12519       __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
12520       __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
12521       __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
12522       __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
12523       __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
12524       __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
12525       __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
12526       __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
12527       __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
12528       __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
12529       __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
12530       __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
12531       __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
12532       __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
12533       __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
12534       __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
12535       __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
12536       __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
12537       __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
12538       __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
12539       __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
12540       __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
12541       __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
12542       __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
12543       __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
12544       __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
12545       __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
12546       __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
12547       __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
12548     } MCUN1INT1STAT_b;
12549   } ;
12550 
12551   union {
12552     __IOM uint32_t MCUN1INT1CLR;                /*!< (@ 0x00000318) Write a 1 to a bit in this register to clear
12553                                                                     the interrupt status associated with that
12554                                                                     bit.                                                       */
12555 
12556     struct {
12557       __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
12558       __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
12559       __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
12560       __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
12561       __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
12562       __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
12563       __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
12564       __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
12565       __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
12566       __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
12567       __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
12568       __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
12569       __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
12570       __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
12571       __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
12572       __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
12573       __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
12574       __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
12575       __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
12576       __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
12577       __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
12578       __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
12579       __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
12580       __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
12581       __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
12582       __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
12583       __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
12584       __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
12585       __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
12586       __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
12587       __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
12588       __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
12589     } MCUN1INT1CLR_b;
12590   } ;
12591 
12592   union {
12593     __IOM uint32_t MCUN1INT1SET;                /*!< (@ 0x0000031C) Write a 1 to a bit in this register to instantly
12594                                                                     generate an interrupt from this module.
12595                                                                     (Generally used for testing purposes).                     */
12596 
12597     struct {
12598       __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
12599       __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
12600       __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
12601       __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
12602       __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
12603       __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
12604       __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
12605       __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
12606       __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
12607       __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
12608       __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
12609       __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
12610       __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
12611       __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
12612       __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
12613       __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
12614       __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
12615       __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
12616       __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
12617       __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
12618       __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
12619       __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
12620       __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
12621       __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
12622       __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
12623       __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
12624       __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
12625       __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
12626       __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
12627       __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
12628       __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
12629       __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
12630     } MCUN1INT1SET_b;
12631   } ;
12632 
12633   union {
12634     __IOM uint32_t MCUN1INT2EN;                 /*!< (@ 0x00000320) Set bits in this register to allow this module
12635                                                                     to generate the corresponding interrupt.                   */
12636 
12637     struct {
12638       __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
12639       __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
12640       __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
12641       __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
12642       __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
12643       __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
12644       __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
12645       __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
12646       __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
12647       __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
12648       __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
12649       __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
12650       __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
12651       __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
12652       __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
12653       __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
12654       __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
12655       __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
12656       __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
12657       __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
12658       __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
12659       __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
12660       __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
12661       __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
12662       __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
12663       __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
12664       __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
12665       __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
12666       __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
12667       __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
12668       __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
12669       __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
12670     } MCUN1INT2EN_b;
12671   } ;
12672 
12673   union {
12674     __IOM uint32_t MCUN1INT2STAT;               /*!< (@ 0x00000324) Read bits from this register to discover the
12675                                                                     cause of a recent interrupt.                               */
12676 
12677     struct {
12678       __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
12679       __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
12680       __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
12681       __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
12682       __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
12683       __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
12684       __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
12685       __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
12686       __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
12687       __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
12688       __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
12689       __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
12690       __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
12691       __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
12692       __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
12693       __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
12694       __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
12695       __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
12696       __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
12697       __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
12698       __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
12699       __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
12700       __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
12701       __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
12702       __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
12703       __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
12704       __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
12705       __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
12706       __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
12707       __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
12708       __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
12709       __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
12710     } MCUN1INT2STAT_b;
12711   } ;
12712 
12713   union {
12714     __IOM uint32_t MCUN1INT2CLR;                /*!< (@ 0x00000328) Write a 1 to a bit in this register to clear
12715                                                                     the interrupt status associated with that
12716                                                                     bit.                                                       */
12717 
12718     struct {
12719       __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
12720       __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
12721       __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
12722       __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
12723       __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
12724       __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
12725       __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
12726       __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
12727       __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
12728       __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
12729       __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
12730       __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
12731       __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
12732       __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
12733       __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
12734       __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
12735       __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
12736       __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
12737       __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
12738       __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
12739       __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
12740       __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
12741       __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
12742       __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
12743       __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
12744       __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
12745       __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
12746       __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
12747       __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
12748       __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
12749       __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
12750       __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
12751     } MCUN1INT2CLR_b;
12752   } ;
12753 
12754   union {
12755     __IOM uint32_t MCUN1INT2SET;                /*!< (@ 0x0000032C) Write a 1 to a bit in this register to instantly
12756                                                                     generate an interrupt from this module.
12757                                                                     (Generally used for testing purposes).                     */
12758 
12759     struct {
12760       __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
12761       __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
12762       __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
12763       __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
12764       __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
12765       __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
12766       __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
12767       __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
12768       __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
12769       __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
12770       __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
12771       __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
12772       __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
12773       __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
12774       __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
12775       __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
12776       __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
12777       __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
12778       __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
12779       __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
12780       __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
12781       __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
12782       __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
12783       __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
12784       __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
12785       __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
12786       __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
12787       __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
12788       __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
12789       __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
12790       __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
12791       __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
12792     } MCUN1INT2SET_b;
12793   } ;
12794 
12795   union {
12796     __IOM uint32_t MCUN1INT3EN;                 /*!< (@ 0x00000330) Set bits in this register to allow this module
12797                                                                     to generate the corresponding interrupt.                   */
12798 
12799     struct {
12800       __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
12801       __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
12802       __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
12803       __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
12804       __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
12805       __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
12806       __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
12807       __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
12808       __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
12809       __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
12810       __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
12811       __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
12812       __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
12813       __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
12814       __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
12815       __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
12816       __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
12817       __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
12818       __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
12819       __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
12820       __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
12821       __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
12822       __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
12823       __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
12824       __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
12825       __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
12826       __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
12827       __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
12828       __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
12829       __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
12830       __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
12831       __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
12832     } MCUN1INT3EN_b;
12833   } ;
12834 
12835   union {
12836     __IOM uint32_t MCUN1INT3STAT;               /*!< (@ 0x00000334) Read bits from this register to discover the
12837                                                                     cause of a recent interrupt.                               */
12838 
12839     struct {
12840       __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
12841       __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
12842       __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
12843       __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
12844       __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
12845       __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
12846       __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
12847       __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
12848       __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
12849       __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
12850       __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
12851       __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
12852       __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
12853       __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
12854       __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
12855       __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
12856       __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
12857       __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
12858       __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
12859       __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
12860       __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
12861       __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
12862       __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
12863       __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
12864       __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
12865       __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
12866       __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
12867       __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
12868       __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
12869       __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
12870       __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
12871       __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
12872     } MCUN1INT3STAT_b;
12873   } ;
12874 
12875   union {
12876     __IOM uint32_t MCUN1INT3CLR;                /*!< (@ 0x00000338) Write a 1 to a bit in this register to clear
12877                                                                     the interrupt status associated with that
12878                                                                     bit.                                                       */
12879 
12880     struct {
12881       __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
12882       __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
12883       __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
12884       __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
12885       __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
12886       __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
12887       __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
12888       __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
12889       __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
12890       __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
12891       __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
12892       __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
12893       __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
12894       __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
12895       __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
12896       __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
12897       __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
12898       __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
12899       __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
12900       __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
12901       __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
12902       __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
12903       __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
12904       __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
12905       __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
12906       __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
12907       __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
12908       __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
12909       __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
12910       __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
12911       __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
12912       __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
12913     } MCUN1INT3CLR_b;
12914   } ;
12915 
12916   union {
12917     __IOM uint32_t MCUN1INT3SET;                /*!< (@ 0x0000033C) Write a 1 to a bit in this register to instantly
12918                                                                     generate an interrupt from this module.
12919                                                                     (Generally used for testing purposes).                     */
12920 
12921     struct {
12922       __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
12923       __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
12924       __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
12925       __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
12926       __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
12927       __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
12928       __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
12929       __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
12930       __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
12931       __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
12932       __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
12933       __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
12934       __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
12935       __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
12936       __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
12937       __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
12938       __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
12939       __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
12940       __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
12941       __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
12942       __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
12943       __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
12944       __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
12945       __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
12946       __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
12947       __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
12948       __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
12949       __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
12950       __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
12951       __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
12952       __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
12953       __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
12954     } MCUN1INT3SET_b;
12955   } ;
12956 
12957   union {
12958     __IOM uint32_t DSP0N0INT0EN;                /*!< (@ 0x00000340) Set bits in this register to allow this module
12959                                                                     to generate the corresponding interrupt.                   */
12960 
12961     struct {
12962       __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
12963       __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
12964       __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
12965       __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
12966       __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
12967       __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
12968       __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
12969       __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
12970       __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
12971       __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
12972       __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
12973       __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
12974       __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
12975       __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
12976       __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
12977       __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
12978       __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
12979       __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
12980       __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
12981       __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
12982       __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
12983       __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
12984       __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
12985       __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
12986       __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
12987       __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
12988       __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
12989       __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
12990       __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
12991       __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
12992       __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
12993       __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
12994     } DSP0N0INT0EN_b;
12995   } ;
12996 
12997   union {
12998     __IOM uint32_t DSP0N0INT0STAT;              /*!< (@ 0x00000344) Read bits from this register to discover the
12999                                                                     cause of a recent interrupt.                               */
13000 
13001     struct {
13002       __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
13003       __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
13004       __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
13005       __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
13006       __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
13007       __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
13008       __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
13009       __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
13010       __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
13011       __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
13012       __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
13013       __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
13014       __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
13015       __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
13016       __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
13017       __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
13018       __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
13019       __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
13020       __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
13021       __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
13022       __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
13023       __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
13024       __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
13025       __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
13026       __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
13027       __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
13028       __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
13029       __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
13030       __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
13031       __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
13032       __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
13033       __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
13034     } DSP0N0INT0STAT_b;
13035   } ;
13036 
13037   union {
13038     __IOM uint32_t DSP0N0INT0CLR;               /*!< (@ 0x00000348) Write a 1 to a bit in this register to clear
13039                                                                     the interrupt status associated with that
13040                                                                     bit.                                                       */
13041 
13042     struct {
13043       __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
13044       __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
13045       __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
13046       __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
13047       __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
13048       __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
13049       __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
13050       __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
13051       __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
13052       __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
13053       __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
13054       __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
13055       __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
13056       __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
13057       __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
13058       __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
13059       __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
13060       __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
13061       __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
13062       __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
13063       __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
13064       __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
13065       __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
13066       __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
13067       __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
13068       __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
13069       __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
13070       __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
13071       __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
13072       __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
13073       __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
13074       __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
13075     } DSP0N0INT0CLR_b;
13076   } ;
13077 
13078   union {
13079     __IOM uint32_t DSP0N0INT0SET;               /*!< (@ 0x0000034C) Write a 1 to a bit in this register to instantly
13080                                                                     generate an interrupt from this module.
13081                                                                     (Generally used for testing purposes).                     */
13082 
13083     struct {
13084       __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
13085       __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
13086       __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
13087       __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
13088       __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
13089       __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
13090       __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
13091       __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
13092       __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
13093       __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
13094       __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
13095       __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
13096       __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
13097       __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
13098       __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
13099       __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
13100       __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
13101       __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
13102       __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
13103       __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
13104       __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
13105       __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
13106       __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
13107       __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
13108       __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
13109       __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
13110       __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
13111       __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
13112       __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
13113       __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
13114       __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
13115       __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
13116     } DSP0N0INT0SET_b;
13117   } ;
13118 
13119   union {
13120     __IOM uint32_t DSP0N0INT1EN;                /*!< (@ 0x00000350) Set bits in this register to allow this module
13121                                                                     to generate the corresponding interrupt.                   */
13122 
13123     struct {
13124       __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
13125       __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
13126       __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
13127       __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
13128       __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
13129       __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
13130       __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
13131       __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
13132       __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
13133       __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
13134       __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
13135       __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
13136       __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
13137       __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
13138       __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
13139       __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
13140       __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
13141       __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
13142       __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
13143       __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
13144       __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
13145       __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
13146       __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
13147       __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
13148       __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
13149       __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
13150       __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
13151       __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
13152       __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
13153       __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
13154       __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
13155       __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
13156     } DSP0N0INT1EN_b;
13157   } ;
13158 
13159   union {
13160     __IOM uint32_t DSP0N0INT1STAT;              /*!< (@ 0x00000354) Read bits from this register to discover the
13161                                                                     cause of a recent interrupt.                               */
13162 
13163     struct {
13164       __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
13165       __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
13166       __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
13167       __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
13168       __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
13169       __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
13170       __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
13171       __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
13172       __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
13173       __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
13174       __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
13175       __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
13176       __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
13177       __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
13178       __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
13179       __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
13180       __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
13181       __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
13182       __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
13183       __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
13184       __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
13185       __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
13186       __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
13187       __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
13188       __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
13189       __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
13190       __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
13191       __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
13192       __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
13193       __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
13194       __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
13195       __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
13196     } DSP0N0INT1STAT_b;
13197   } ;
13198 
13199   union {
13200     __IOM uint32_t DSP0N0INT1CLR;               /*!< (@ 0x00000358) Write a 1 to a bit in this register to clear
13201                                                                     the interrupt status associated with that
13202                                                                     bit.                                                       */
13203 
13204     struct {
13205       __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
13206       __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
13207       __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
13208       __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
13209       __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
13210       __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
13211       __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
13212       __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
13213       __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
13214       __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
13215       __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
13216       __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
13217       __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
13218       __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
13219       __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
13220       __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
13221       __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
13222       __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
13223       __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
13224       __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
13225       __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
13226       __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
13227       __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
13228       __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
13229       __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
13230       __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
13231       __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
13232       __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
13233       __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
13234       __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
13235       __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
13236       __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
13237     } DSP0N0INT1CLR_b;
13238   } ;
13239 
13240   union {
13241     __IOM uint32_t DSP0N0INT1SET;               /*!< (@ 0x0000035C) Write a 1 to a bit in this register to instantly
13242                                                                     generate an interrupt from this module.
13243                                                                     (Generally used for testing purposes).                     */
13244 
13245     struct {
13246       __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
13247       __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
13248       __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
13249       __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
13250       __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
13251       __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
13252       __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
13253       __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
13254       __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
13255       __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
13256       __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
13257       __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
13258       __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
13259       __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
13260       __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
13261       __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
13262       __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
13263       __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
13264       __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
13265       __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
13266       __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
13267       __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
13268       __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
13269       __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
13270       __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
13271       __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
13272       __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
13273       __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
13274       __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
13275       __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
13276       __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
13277       __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
13278     } DSP0N0INT1SET_b;
13279   } ;
13280 
13281   union {
13282     __IOM uint32_t DSP0N0INT2EN;                /*!< (@ 0x00000360) Set bits in this register to allow this module
13283                                                                     to generate the corresponding interrupt.                   */
13284 
13285     struct {
13286       __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
13287       __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
13288       __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
13289       __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
13290       __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
13291       __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
13292       __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
13293       __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
13294       __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
13295       __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
13296       __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
13297       __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
13298       __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
13299       __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
13300       __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
13301       __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
13302       __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
13303       __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
13304       __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
13305       __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
13306       __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
13307       __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
13308       __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
13309       __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
13310       __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
13311       __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
13312       __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
13313       __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
13314       __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
13315       __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
13316       __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
13317       __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
13318     } DSP0N0INT2EN_b;
13319   } ;
13320 
13321   union {
13322     __IOM uint32_t DSP0N0INT2STAT;              /*!< (@ 0x00000364) Read bits from this register to discover the
13323                                                                     cause of a recent interrupt.                               */
13324 
13325     struct {
13326       __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
13327       __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
13328       __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
13329       __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
13330       __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
13331       __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
13332       __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
13333       __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
13334       __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
13335       __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
13336       __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
13337       __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
13338       __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
13339       __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
13340       __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
13341       __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
13342       __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
13343       __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
13344       __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
13345       __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
13346       __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
13347       __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
13348       __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
13349       __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
13350       __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
13351       __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
13352       __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
13353       __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
13354       __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
13355       __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
13356       __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
13357       __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
13358     } DSP0N0INT2STAT_b;
13359   } ;
13360 
13361   union {
13362     __IOM uint32_t DSP0N0INT2CLR;               /*!< (@ 0x00000368) Write a 1 to a bit in this register to clear
13363                                                                     the interrupt status associated with that
13364                                                                     bit.                                                       */
13365 
13366     struct {
13367       __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
13368       __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
13369       __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
13370       __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
13371       __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
13372       __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
13373       __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
13374       __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
13375       __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
13376       __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
13377       __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
13378       __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
13379       __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
13380       __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
13381       __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
13382       __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
13383       __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
13384       __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
13385       __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
13386       __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
13387       __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
13388       __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
13389       __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
13390       __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
13391       __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
13392       __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
13393       __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
13394       __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
13395       __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
13396       __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
13397       __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
13398       __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
13399     } DSP0N0INT2CLR_b;
13400   } ;
13401 
13402   union {
13403     __IOM uint32_t DSP0N0INT2SET;               /*!< (@ 0x0000036C) Write a 1 to a bit in this register to instantly
13404                                                                     generate an interrupt from this module.
13405                                                                     (Generally used for testing purposes).                     */
13406 
13407     struct {
13408       __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
13409       __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
13410       __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
13411       __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
13412       __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
13413       __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
13414       __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
13415       __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
13416       __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
13417       __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
13418       __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
13419       __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
13420       __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
13421       __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
13422       __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
13423       __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
13424       __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
13425       __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
13426       __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
13427       __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
13428       __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
13429       __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
13430       __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
13431       __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
13432       __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
13433       __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
13434       __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
13435       __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
13436       __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
13437       __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
13438       __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
13439       __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
13440     } DSP0N0INT2SET_b;
13441   } ;
13442 
13443   union {
13444     __IOM uint32_t DSP0N0INT3EN;                /*!< (@ 0x00000370) Set bits in this register to allow this module
13445                                                                     to generate the corresponding interrupt.                   */
13446 
13447     struct {
13448       __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
13449       __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
13450       __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
13451       __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
13452       __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
13453       __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
13454       __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
13455       __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
13456       __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
13457       __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
13458       __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
13459       __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
13460       __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
13461       __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
13462       __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
13463       __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
13464       __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
13465       __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
13466       __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
13467       __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
13468       __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
13469       __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
13470       __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
13471       __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
13472       __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
13473       __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
13474       __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
13475       __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
13476       __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
13477       __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
13478       __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
13479       __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
13480     } DSP0N0INT3EN_b;
13481   } ;
13482 
13483   union {
13484     __IOM uint32_t DSP0N0INT3STAT;              /*!< (@ 0x00000374) Read bits from this register to discover the
13485                                                                     cause of a recent interrupt.                               */
13486 
13487     struct {
13488       __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
13489       __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
13490       __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
13491       __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
13492       __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
13493       __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
13494       __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
13495       __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
13496       __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
13497       __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
13498       __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
13499       __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
13500       __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
13501       __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
13502       __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
13503       __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
13504       __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
13505       __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
13506       __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
13507       __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
13508       __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
13509       __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
13510       __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
13511       __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
13512       __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
13513       __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
13514       __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
13515       __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
13516       __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
13517       __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
13518       __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
13519       __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
13520     } DSP0N0INT3STAT_b;
13521   } ;
13522 
13523   union {
13524     __IOM uint32_t DSP0N0INT3CLR;               /*!< (@ 0x00000378) Write a 1 to a bit in this register to clear
13525                                                                     the interrupt status associated with that
13526                                                                     bit.                                                       */
13527 
13528     struct {
13529       __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
13530       __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
13531       __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
13532       __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
13533       __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
13534       __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
13535       __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
13536       __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
13537       __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
13538       __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
13539       __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
13540       __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
13541       __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
13542       __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
13543       __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
13544       __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
13545       __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
13546       __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
13547       __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
13548       __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
13549       __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
13550       __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
13551       __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
13552       __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
13553       __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
13554       __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
13555       __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
13556       __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
13557       __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
13558       __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
13559       __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
13560       __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
13561     } DSP0N0INT3CLR_b;
13562   } ;
13563 
13564   union {
13565     __IOM uint32_t DSP0N0INT3SET;               /*!< (@ 0x0000037C) Write a 1 to a bit in this register to instantly
13566                                                                     generate an interrupt from this module.
13567                                                                     (Generally used for testing purposes).                     */
13568 
13569     struct {
13570       __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
13571       __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
13572       __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
13573       __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
13574       __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
13575       __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
13576       __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
13577       __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
13578       __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
13579       __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
13580       __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
13581       __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
13582       __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
13583       __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
13584       __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
13585       __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
13586       __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
13587       __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
13588       __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
13589       __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
13590       __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
13591       __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
13592       __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
13593       __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
13594       __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
13595       __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
13596       __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
13597       __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
13598       __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
13599       __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
13600       __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
13601       __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
13602     } DSP0N0INT3SET_b;
13603   } ;
13604 
13605   union {
13606     __IOM uint32_t DSP0N1INT0EN;                /*!< (@ 0x00000380) Set bits in this register to allow this module
13607                                                                     to generate the corresponding interrupt.                   */
13608 
13609     struct {
13610       __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
13611       __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
13612       __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
13613       __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
13614       __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
13615       __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
13616       __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
13617       __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
13618       __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
13619       __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
13620       __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
13621       __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
13622       __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
13623       __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
13624       __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
13625       __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
13626       __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
13627       __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
13628       __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
13629       __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
13630       __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
13631       __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
13632       __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
13633       __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
13634       __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
13635       __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
13636       __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
13637       __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
13638       __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
13639       __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
13640       __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
13641       __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
13642     } DSP0N1INT0EN_b;
13643   } ;
13644 
13645   union {
13646     __IOM uint32_t DSP0N1INT0STAT;              /*!< (@ 0x00000384) Read bits from this register to discover the
13647                                                                     cause of a recent interrupt.                               */
13648 
13649     struct {
13650       __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
13651       __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
13652       __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
13653       __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
13654       __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
13655       __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
13656       __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
13657       __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
13658       __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
13659       __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
13660       __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
13661       __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
13662       __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
13663       __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
13664       __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
13665       __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
13666       __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
13667       __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
13668       __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
13669       __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
13670       __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
13671       __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
13672       __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
13673       __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
13674       __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
13675       __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
13676       __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
13677       __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
13678       __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
13679       __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
13680       __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
13681       __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
13682     } DSP0N1INT0STAT_b;
13683   } ;
13684 
13685   union {
13686     __IOM uint32_t DSP0N1INT0CLR;               /*!< (@ 0x00000388) Write a 1 to a bit in this register to clear
13687                                                                     the interrupt status associated with that
13688                                                                     bit.                                                       */
13689 
13690     struct {
13691       __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
13692       __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
13693       __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
13694       __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
13695       __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
13696       __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
13697       __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
13698       __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
13699       __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
13700       __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
13701       __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
13702       __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
13703       __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
13704       __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
13705       __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
13706       __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
13707       __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
13708       __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
13709       __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
13710       __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
13711       __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
13712       __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
13713       __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
13714       __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
13715       __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
13716       __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
13717       __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
13718       __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
13719       __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
13720       __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
13721       __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
13722       __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
13723     } DSP0N1INT0CLR_b;
13724   } ;
13725 
13726   union {
13727     __IOM uint32_t DSP0N1INT0SET;               /*!< (@ 0x0000038C) Write a 1 to a bit in this register to instantly
13728                                                                     generate an interrupt from this module.
13729                                                                     (Generally used for testing purposes).                     */
13730 
13731     struct {
13732       __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
13733       __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
13734       __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
13735       __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
13736       __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
13737       __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
13738       __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
13739       __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
13740       __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
13741       __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
13742       __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
13743       __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
13744       __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
13745       __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
13746       __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
13747       __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
13748       __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
13749       __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
13750       __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
13751       __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
13752       __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
13753       __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
13754       __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
13755       __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
13756       __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
13757       __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
13758       __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
13759       __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
13760       __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
13761       __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
13762       __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
13763       __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
13764     } DSP0N1INT0SET_b;
13765   } ;
13766 
13767   union {
13768     __IOM uint32_t DSP0N1INT1EN;                /*!< (@ 0x00000390) Set bits in this register to allow this module
13769                                                                     to generate the corresponding interrupt.                   */
13770 
13771     struct {
13772       __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
13773       __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
13774       __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
13775       __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
13776       __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
13777       __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
13778       __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
13779       __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
13780       __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
13781       __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
13782       __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
13783       __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
13784       __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
13785       __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
13786       __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
13787       __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
13788       __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
13789       __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
13790       __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
13791       __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
13792       __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
13793       __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
13794       __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
13795       __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
13796       __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
13797       __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
13798       __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
13799       __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
13800       __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
13801       __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
13802       __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
13803       __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
13804     } DSP0N1INT1EN_b;
13805   } ;
13806 
13807   union {
13808     __IOM uint32_t DSP0N1INT1STAT;              /*!< (@ 0x00000394) Read bits from this register to discover the
13809                                                                     cause of a recent interrupt.                               */
13810 
13811     struct {
13812       __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
13813       __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
13814       __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
13815       __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
13816       __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
13817       __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
13818       __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
13819       __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
13820       __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
13821       __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
13822       __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
13823       __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
13824       __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
13825       __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
13826       __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
13827       __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
13828       __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
13829       __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
13830       __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
13831       __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
13832       __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
13833       __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
13834       __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
13835       __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
13836       __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
13837       __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
13838       __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
13839       __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
13840       __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
13841       __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
13842       __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
13843       __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
13844     } DSP0N1INT1STAT_b;
13845   } ;
13846 
13847   union {
13848     __IOM uint32_t DSP0N1INT1CLR;               /*!< (@ 0x00000398) Write a 1 to a bit in this register to clear
13849                                                                     the interrupt status associated with that
13850                                                                     bit.                                                       */
13851 
13852     struct {
13853       __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
13854       __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
13855       __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
13856       __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
13857       __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
13858       __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
13859       __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
13860       __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
13861       __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
13862       __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
13863       __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
13864       __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
13865       __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
13866       __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
13867       __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
13868       __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
13869       __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
13870       __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
13871       __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
13872       __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
13873       __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
13874       __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
13875       __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
13876       __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
13877       __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
13878       __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
13879       __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
13880       __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
13881       __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
13882       __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
13883       __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
13884       __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
13885     } DSP0N1INT1CLR_b;
13886   } ;
13887 
13888   union {
13889     __IOM uint32_t DSP0N1INT1SET;               /*!< (@ 0x0000039C) Write a 1 to a bit in this register to instantly
13890                                                                     generate an interrupt from this module.
13891                                                                     (Generally used for testing purposes).                     */
13892 
13893     struct {
13894       __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
13895       __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
13896       __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
13897       __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
13898       __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
13899       __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
13900       __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
13901       __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
13902       __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
13903       __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
13904       __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
13905       __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
13906       __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
13907       __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
13908       __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
13909       __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
13910       __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
13911       __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
13912       __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
13913       __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
13914       __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
13915       __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
13916       __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
13917       __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
13918       __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
13919       __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
13920       __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
13921       __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
13922       __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
13923       __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
13924       __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
13925       __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
13926     } DSP0N1INT1SET_b;
13927   } ;
13928 
13929   union {
13930     __IOM uint32_t DSP0N1INT2EN;                /*!< (@ 0x000003A0) Set bits in this register to allow this module
13931                                                                     to generate the corresponding interrupt.                   */
13932 
13933     struct {
13934       __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
13935       __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
13936       __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
13937       __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
13938       __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
13939       __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
13940       __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
13941       __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
13942       __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
13943       __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
13944       __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
13945       __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
13946       __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
13947       __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
13948       __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
13949       __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
13950       __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
13951       __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
13952       __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
13953       __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
13954       __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
13955       __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
13956       __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
13957       __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
13958       __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
13959       __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
13960       __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
13961       __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
13962       __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
13963       __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
13964       __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
13965       __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
13966     } DSP0N1INT2EN_b;
13967   } ;
13968 
13969   union {
13970     __IOM uint32_t DSP0N1INT2STAT;              /*!< (@ 0x000003A4) Read bits from this register to discover the
13971                                                                     cause of a recent interrupt.                               */
13972 
13973     struct {
13974       __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
13975       __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
13976       __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
13977       __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
13978       __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
13979       __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
13980       __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
13981       __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
13982       __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
13983       __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
13984       __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
13985       __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
13986       __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
13987       __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
13988       __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
13989       __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
13990       __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
13991       __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
13992       __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
13993       __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
13994       __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
13995       __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
13996       __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
13997       __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
13998       __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
13999       __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
14000       __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
14001       __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
14002       __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
14003       __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
14004       __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
14005       __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
14006     } DSP0N1INT2STAT_b;
14007   } ;
14008 
14009   union {
14010     __IOM uint32_t DSP0N1INT2CLR;               /*!< (@ 0x000003A8) Write a 1 to a bit in this register to clear
14011                                                                     the interrupt status associated with that
14012                                                                     bit.                                                       */
14013 
14014     struct {
14015       __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
14016       __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
14017       __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
14018       __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
14019       __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
14020       __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
14021       __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
14022       __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
14023       __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
14024       __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
14025       __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
14026       __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
14027       __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
14028       __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
14029       __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
14030       __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
14031       __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
14032       __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
14033       __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
14034       __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
14035       __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
14036       __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
14037       __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
14038       __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
14039       __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
14040       __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
14041       __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
14042       __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
14043       __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
14044       __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
14045       __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
14046       __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
14047     } DSP0N1INT2CLR_b;
14048   } ;
14049 
14050   union {
14051     __IOM uint32_t DSP0N1INT2SET;               /*!< (@ 0x000003AC) Write a 1 to a bit in this register to instantly
14052                                                                     generate an interrupt from this module.
14053                                                                     (Generally used for testing purposes).                     */
14054 
14055     struct {
14056       __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
14057       __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
14058       __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
14059       __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
14060       __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
14061       __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
14062       __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
14063       __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
14064       __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
14065       __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
14066       __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
14067       __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
14068       __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
14069       __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
14070       __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
14071       __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
14072       __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
14073       __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
14074       __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
14075       __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
14076       __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
14077       __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
14078       __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
14079       __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
14080       __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
14081       __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
14082       __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
14083       __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
14084       __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
14085       __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
14086       __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
14087       __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
14088     } DSP0N1INT2SET_b;
14089   } ;
14090 
14091   union {
14092     __IOM uint32_t DSP0N1INT3EN;                /*!< (@ 0x000003B0) Set bits in this register to allow this module
14093                                                                     to generate the corresponding interrupt.                   */
14094 
14095     struct {
14096       __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
14097       __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
14098       __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
14099       __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
14100       __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
14101       __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
14102       __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
14103       __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
14104       __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
14105       __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
14106       __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
14107       __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
14108       __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
14109       __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
14110       __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
14111       __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
14112       __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
14113       __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
14114       __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
14115       __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
14116       __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
14117       __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
14118       __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
14119       __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
14120       __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
14121       __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
14122       __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
14123       __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
14124       __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
14125       __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
14126       __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
14127       __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
14128     } DSP0N1INT3EN_b;
14129   } ;
14130 
14131   union {
14132     __IOM uint32_t DSP0N1INT3STAT;              /*!< (@ 0x000003B4) Read bits from this register to discover the
14133                                                                     cause of a recent interrupt.                               */
14134 
14135     struct {
14136       __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
14137       __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
14138       __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
14139       __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
14140       __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
14141       __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
14142       __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
14143       __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
14144       __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
14145       __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
14146       __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
14147       __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
14148       __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
14149       __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
14150       __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
14151       __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
14152       __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
14153       __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
14154       __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
14155       __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
14156       __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
14157       __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
14158       __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
14159       __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
14160       __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
14161       __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
14162       __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
14163       __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
14164       __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
14165       __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
14166       __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
14167       __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
14168     } DSP0N1INT3STAT_b;
14169   } ;
14170 
14171   union {
14172     __IOM uint32_t DSP0N1INT3CLR;               /*!< (@ 0x000003B8) Write a 1 to a bit in this register to clear
14173                                                                     the interrupt status associated with that
14174                                                                     bit.                                                       */
14175 
14176     struct {
14177       __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
14178       __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
14179       __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
14180       __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
14181       __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
14182       __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
14183       __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
14184       __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
14185       __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
14186       __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
14187       __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
14188       __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
14189       __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
14190       __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
14191       __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
14192       __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
14193       __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
14194       __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
14195       __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
14196       __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
14197       __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
14198       __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
14199       __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
14200       __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
14201       __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
14202       __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
14203       __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
14204       __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
14205       __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
14206       __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
14207       __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
14208       __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
14209     } DSP0N1INT3CLR_b;
14210   } ;
14211 
14212   union {
14213     __IOM uint32_t DSP0N1INT3SET;               /*!< (@ 0x000003BC) Write a 1 to a bit in this register to instantly
14214                                                                     generate an interrupt from this module.
14215                                                                     (Generally used for testing purposes).                     */
14216 
14217     struct {
14218       __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
14219       __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
14220       __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
14221       __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
14222       __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
14223       __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
14224       __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
14225       __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
14226       __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
14227       __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
14228       __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
14229       __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
14230       __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
14231       __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
14232       __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
14233       __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
14234       __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
14235       __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
14236       __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
14237       __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
14238       __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
14239       __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
14240       __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
14241       __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
14242       __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
14243       __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
14244       __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
14245       __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
14246       __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
14247       __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
14248       __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
14249       __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
14250     } DSP0N1INT3SET_b;
14251   } ;
14252 
14253   union {
14254     __IOM uint32_t DSP1N0INT0EN;                /*!< (@ 0x000003C0) Set bits in this register to allow this module
14255                                                                     to generate the corresponding interrupt.                   */
14256 
14257     struct {
14258       __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
14259       __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
14260       __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
14261       __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
14262       __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
14263       __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
14264       __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
14265       __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
14266       __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
14267       __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
14268       __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
14269       __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
14270       __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
14271       __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
14272       __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
14273       __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
14274       __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
14275       __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
14276       __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
14277       __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
14278       __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
14279       __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
14280       __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
14281       __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
14282       __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
14283       __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
14284       __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
14285       __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
14286       __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
14287       __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
14288       __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
14289       __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
14290     } DSP1N0INT0EN_b;
14291   } ;
14292 
14293   union {
14294     __IOM uint32_t DSP1N0INT0STAT;              /*!< (@ 0x000003C4) Read bits from this register to discover the
14295                                                                     cause of a recent interrupt.                               */
14296 
14297     struct {
14298       __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
14299       __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
14300       __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
14301       __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
14302       __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
14303       __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
14304       __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
14305       __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
14306       __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
14307       __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
14308       __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
14309       __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
14310       __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
14311       __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
14312       __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
14313       __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
14314       __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
14315       __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
14316       __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
14317       __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
14318       __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
14319       __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
14320       __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
14321       __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
14322       __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
14323       __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
14324       __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
14325       __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
14326       __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
14327       __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
14328       __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
14329       __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
14330     } DSP1N0INT0STAT_b;
14331   } ;
14332 
14333   union {
14334     __IOM uint32_t DSP1N0INT0CLR;               /*!< (@ 0x000003C8) Write a 1 to a bit in this register to clear
14335                                                                     the interrupt status associated with that
14336                                                                     bit.                                                       */
14337 
14338     struct {
14339       __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
14340       __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
14341       __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
14342       __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
14343       __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
14344       __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
14345       __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
14346       __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
14347       __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
14348       __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
14349       __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
14350       __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
14351       __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
14352       __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
14353       __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
14354       __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
14355       __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
14356       __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
14357       __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
14358       __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
14359       __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
14360       __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
14361       __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
14362       __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
14363       __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
14364       __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
14365       __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
14366       __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
14367       __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
14368       __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
14369       __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
14370       __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
14371     } DSP1N0INT0CLR_b;
14372   } ;
14373 
14374   union {
14375     __IOM uint32_t DSP1N0INT0SET;               /*!< (@ 0x000003CC) Write a 1 to a bit in this register to instantly
14376                                                                     generate an interrupt from this module.
14377                                                                     (Generally used for testing purposes).                     */
14378 
14379     struct {
14380       __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
14381       __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
14382       __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
14383       __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
14384       __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
14385       __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
14386       __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
14387       __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
14388       __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
14389       __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
14390       __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
14391       __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
14392       __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
14393       __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
14394       __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
14395       __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
14396       __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
14397       __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
14398       __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
14399       __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
14400       __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
14401       __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
14402       __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
14403       __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
14404       __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
14405       __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
14406       __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
14407       __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
14408       __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
14409       __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
14410       __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
14411       __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
14412     } DSP1N0INT0SET_b;
14413   } ;
14414 
14415   union {
14416     __IOM uint32_t DSP1N0INT1EN;                /*!< (@ 0x000003D0) Set bits in this register to allow this module
14417                                                                     to generate the corresponding interrupt.                   */
14418 
14419     struct {
14420       __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
14421       __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
14422       __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
14423       __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
14424       __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
14425       __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
14426       __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
14427       __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
14428       __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
14429       __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
14430       __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
14431       __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
14432       __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
14433       __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
14434       __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
14435       __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
14436       __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
14437       __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
14438       __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
14439       __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
14440       __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
14441       __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
14442       __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
14443       __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
14444       __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
14445       __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
14446       __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
14447       __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
14448       __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
14449       __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
14450       __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
14451       __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
14452     } DSP1N0INT1EN_b;
14453   } ;
14454 
14455   union {
14456     __IOM uint32_t DSP1N0INT1STAT;              /*!< (@ 0x000003D4) Read bits from this register to discover the
14457                                                                     cause of a recent interrupt.                               */
14458 
14459     struct {
14460       __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
14461       __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
14462       __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
14463       __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
14464       __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
14465       __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
14466       __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
14467       __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
14468       __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
14469       __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
14470       __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
14471       __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
14472       __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
14473       __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
14474       __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
14475       __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
14476       __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
14477       __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
14478       __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
14479       __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
14480       __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
14481       __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
14482       __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
14483       __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
14484       __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
14485       __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
14486       __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
14487       __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
14488       __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
14489       __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
14490       __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
14491       __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
14492     } DSP1N0INT1STAT_b;
14493   } ;
14494 
14495   union {
14496     __IOM uint32_t DSP1N0INT1CLR;               /*!< (@ 0x000003D8) Write a 1 to a bit in this register to clear
14497                                                                     the interrupt status associated with that
14498                                                                     bit.                                                       */
14499 
14500     struct {
14501       __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
14502       __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
14503       __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
14504       __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
14505       __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
14506       __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
14507       __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
14508       __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
14509       __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
14510       __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
14511       __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
14512       __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
14513       __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
14514       __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
14515       __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
14516       __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
14517       __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
14518       __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
14519       __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
14520       __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
14521       __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
14522       __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
14523       __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
14524       __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
14525       __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
14526       __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
14527       __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
14528       __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
14529       __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
14530       __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
14531       __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
14532       __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
14533     } DSP1N0INT1CLR_b;
14534   } ;
14535 
14536   union {
14537     __IOM uint32_t DSP1N0INT1SET;               /*!< (@ 0x000003DC) Write a 1 to a bit in this register to instantly
14538                                                                     generate an interrupt from this module.
14539                                                                     (Generally used for testing purposes).                     */
14540 
14541     struct {
14542       __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
14543       __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
14544       __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
14545       __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
14546       __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
14547       __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
14548       __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
14549       __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
14550       __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
14551       __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
14552       __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
14553       __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
14554       __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
14555       __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
14556       __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
14557       __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
14558       __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
14559       __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
14560       __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
14561       __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
14562       __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
14563       __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
14564       __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
14565       __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
14566       __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
14567       __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
14568       __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
14569       __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
14570       __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
14571       __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
14572       __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
14573       __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
14574     } DSP1N0INT1SET_b;
14575   } ;
14576 
14577   union {
14578     __IOM uint32_t DSP1N0INT2EN;                /*!< (@ 0x000003E0) Set bits in this register to allow this module
14579                                                                     to generate the corresponding interrupt.                   */
14580 
14581     struct {
14582       __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
14583       __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
14584       __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
14585       __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
14586       __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
14587       __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
14588       __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
14589       __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
14590       __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
14591       __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
14592       __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
14593       __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
14594       __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
14595       __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
14596       __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
14597       __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
14598       __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
14599       __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
14600       __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
14601       __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
14602       __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
14603       __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
14604       __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
14605       __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
14606       __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
14607       __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
14608       __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
14609       __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
14610       __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
14611       __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
14612       __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
14613       __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
14614     } DSP1N0INT2EN_b;
14615   } ;
14616 
14617   union {
14618     __IOM uint32_t DSP1N0INT2STAT;              /*!< (@ 0x000003E4) Read bits from this register to discover the
14619                                                                     cause of a recent interrupt.                               */
14620 
14621     struct {
14622       __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
14623       __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
14624       __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
14625       __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
14626       __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
14627       __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
14628       __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
14629       __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
14630       __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
14631       __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
14632       __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
14633       __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
14634       __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
14635       __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
14636       __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
14637       __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
14638       __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
14639       __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
14640       __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
14641       __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
14642       __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
14643       __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
14644       __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
14645       __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
14646       __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
14647       __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
14648       __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
14649       __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
14650       __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
14651       __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
14652       __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
14653       __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
14654     } DSP1N0INT2STAT_b;
14655   } ;
14656 
14657   union {
14658     __IOM uint32_t DSP1N0INT2CLR;               /*!< (@ 0x000003E8) Write a 1 to a bit in this register to clear
14659                                                                     the interrupt status associated with that
14660                                                                     bit.                                                       */
14661 
14662     struct {
14663       __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
14664       __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
14665       __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
14666       __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
14667       __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
14668       __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
14669       __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
14670       __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
14671       __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
14672       __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
14673       __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
14674       __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
14675       __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
14676       __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
14677       __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
14678       __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
14679       __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
14680       __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
14681       __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
14682       __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
14683       __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
14684       __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
14685       __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
14686       __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
14687       __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
14688       __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
14689       __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
14690       __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
14691       __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
14692       __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
14693       __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
14694       __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
14695     } DSP1N0INT2CLR_b;
14696   } ;
14697 
14698   union {
14699     __IOM uint32_t DSP1N0INT2SET;               /*!< (@ 0x000003EC) Write a 1 to a bit in this register to instantly
14700                                                                     generate an interrupt from this module.
14701                                                                     (Generally used for testing purposes).                     */
14702 
14703     struct {
14704       __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
14705       __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
14706       __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
14707       __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
14708       __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
14709       __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
14710       __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
14711       __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
14712       __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
14713       __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
14714       __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
14715       __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
14716       __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
14717       __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
14718       __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
14719       __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
14720       __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
14721       __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
14722       __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
14723       __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
14724       __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
14725       __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
14726       __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
14727       __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
14728       __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
14729       __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
14730       __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
14731       __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
14732       __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
14733       __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
14734       __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
14735       __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
14736     } DSP1N0INT2SET_b;
14737   } ;
14738 
14739   union {
14740     __IOM uint32_t DSP1N0INT3EN;                /*!< (@ 0x000003F0) Set bits in this register to allow this module
14741                                                                     to generate the corresponding interrupt.                   */
14742 
14743     struct {
14744       __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
14745       __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
14746       __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
14747       __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
14748       __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
14749       __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
14750       __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
14751       __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
14752       __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
14753       __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
14754       __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
14755       __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
14756       __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
14757       __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
14758       __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
14759       __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
14760       __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
14761       __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
14762       __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
14763       __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
14764       __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
14765       __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
14766       __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
14767       __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
14768       __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
14769       __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
14770       __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
14771       __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
14772       __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
14773       __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
14774       __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
14775       __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
14776     } DSP1N0INT3EN_b;
14777   } ;
14778 
14779   union {
14780     __IOM uint32_t DSP1N0INT3STAT;              /*!< (@ 0x000003F4) Read bits from this register to discover the
14781                                                                     cause of a recent interrupt.                               */
14782 
14783     struct {
14784       __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
14785       __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
14786       __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
14787       __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
14788       __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
14789       __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
14790       __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
14791       __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
14792       __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
14793       __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
14794       __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
14795       __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
14796       __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
14797       __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
14798       __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
14799       __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
14800       __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
14801       __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
14802       __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
14803       __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
14804       __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
14805       __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
14806       __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
14807       __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
14808       __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
14809       __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
14810       __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
14811       __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
14812       __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
14813       __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
14814       __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
14815       __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
14816     } DSP1N0INT3STAT_b;
14817   } ;
14818 
14819   union {
14820     __IOM uint32_t DSP1N0INT3CLR;               /*!< (@ 0x000003F8) Write a 1 to a bit in this register to clear
14821                                                                     the interrupt status associated with that
14822                                                                     bit.                                                       */
14823 
14824     struct {
14825       __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
14826       __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
14827       __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
14828       __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
14829       __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
14830       __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
14831       __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
14832       __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
14833       __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
14834       __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
14835       __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
14836       __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
14837       __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
14838       __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
14839       __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
14840       __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
14841       __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
14842       __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
14843       __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
14844       __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
14845       __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
14846       __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
14847       __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
14848       __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
14849       __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
14850       __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
14851       __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
14852       __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
14853       __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
14854       __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
14855       __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
14856       __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
14857     } DSP1N0INT3CLR_b;
14858   } ;
14859 
14860   union {
14861     __IOM uint32_t DSP1N0INT3SET;               /*!< (@ 0x000003FC) Write a 1 to a bit in this register to instantly
14862                                                                     generate an interrupt from this module.
14863                                                                     (Generally used for testing purposes).                     */
14864 
14865     struct {
14866       __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
14867       __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
14868       __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
14869       __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
14870       __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
14871       __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
14872       __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
14873       __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
14874       __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
14875       __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
14876       __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
14877       __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
14878       __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
14879       __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
14880       __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
14881       __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
14882       __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
14883       __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
14884       __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
14885       __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
14886       __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
14887       __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
14888       __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
14889       __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
14890       __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
14891       __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
14892       __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
14893       __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
14894       __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
14895       __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
14896       __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
14897       __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
14898     } DSP1N0INT3SET_b;
14899   } ;
14900 
14901   union {
14902     __IOM uint32_t DSP1N1INT0EN;                /*!< (@ 0x00000400) Set bits in this register to allow this module
14903                                                                     to generate the corresponding interrupt.                   */
14904 
14905     struct {
14906       __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
14907       __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
14908       __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
14909       __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
14910       __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
14911       __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
14912       __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
14913       __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
14914       __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
14915       __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
14916       __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
14917       __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
14918       __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
14919       __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
14920       __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
14921       __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
14922       __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
14923       __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
14924       __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
14925       __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
14926       __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
14927       __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
14928       __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
14929       __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
14930       __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
14931       __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
14932       __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
14933       __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
14934       __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
14935       __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
14936       __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
14937       __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
14938     } DSP1N1INT0EN_b;
14939   } ;
14940 
14941   union {
14942     __IOM uint32_t DSP1N1INT0STAT;              /*!< (@ 0x00000404) Read bits from this register to discover the
14943                                                                     cause of a recent interrupt.                               */
14944 
14945     struct {
14946       __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
14947       __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
14948       __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
14949       __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
14950       __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
14951       __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
14952       __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
14953       __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
14954       __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
14955       __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
14956       __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
14957       __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
14958       __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
14959       __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
14960       __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
14961       __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
14962       __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
14963       __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
14964       __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
14965       __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
14966       __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
14967       __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
14968       __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
14969       __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
14970       __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
14971       __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
14972       __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
14973       __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
14974       __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
14975       __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
14976       __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
14977       __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
14978     } DSP1N1INT0STAT_b;
14979   } ;
14980 
14981   union {
14982     __IOM uint32_t DSP1N1INT0CLR;               /*!< (@ 0x00000408) Write a 1 to a bit in this register to clear
14983                                                                     the interrupt status associated with that
14984                                                                     bit.                                                       */
14985 
14986     struct {
14987       __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
14988       __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
14989       __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
14990       __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
14991       __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
14992       __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
14993       __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
14994       __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
14995       __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
14996       __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
14997       __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
14998       __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
14999       __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
15000       __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
15001       __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
15002       __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
15003       __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
15004       __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
15005       __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
15006       __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
15007       __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
15008       __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
15009       __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
15010       __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
15011       __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
15012       __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
15013       __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
15014       __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
15015       __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
15016       __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
15017       __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
15018       __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
15019     } DSP1N1INT0CLR_b;
15020   } ;
15021 
15022   union {
15023     __IOM uint32_t DSP1N1INT0SET;               /*!< (@ 0x0000040C) Write a 1 to a bit in this register to instantly
15024                                                                     generate an interrupt from this module.
15025                                                                     (Generally used for testing purposes).                     */
15026 
15027     struct {
15028       __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
15029       __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
15030       __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
15031       __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
15032       __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
15033       __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
15034       __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
15035       __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
15036       __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
15037       __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
15038       __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
15039       __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
15040       __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
15041       __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
15042       __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
15043       __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
15044       __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
15045       __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
15046       __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
15047       __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
15048       __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
15049       __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
15050       __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
15051       __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
15052       __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
15053       __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
15054       __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
15055       __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
15056       __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
15057       __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
15058       __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
15059       __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
15060     } DSP1N1INT0SET_b;
15061   } ;
15062 
15063   union {
15064     __IOM uint32_t DSP1N1INT1EN;                /*!< (@ 0x00000410) Set bits in this register to allow this module
15065                                                                     to generate the corresponding interrupt.                   */
15066 
15067     struct {
15068       __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
15069       __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
15070       __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
15071       __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
15072       __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
15073       __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
15074       __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
15075       __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
15076       __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
15077       __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
15078       __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
15079       __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
15080       __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
15081       __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
15082       __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
15083       __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
15084       __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
15085       __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
15086       __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
15087       __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
15088       __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
15089       __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
15090       __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
15091       __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
15092       __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
15093       __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
15094       __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
15095       __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
15096       __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
15097       __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
15098       __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
15099       __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
15100     } DSP1N1INT1EN_b;
15101   } ;
15102 
15103   union {
15104     __IOM uint32_t DSP1N1INT1STAT;              /*!< (@ 0x00000414) Read bits from this register to discover the
15105                                                                     cause of a recent interrupt.                               */
15106 
15107     struct {
15108       __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
15109       __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
15110       __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
15111       __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
15112       __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
15113       __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
15114       __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
15115       __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
15116       __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
15117       __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
15118       __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
15119       __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
15120       __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
15121       __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
15122       __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
15123       __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
15124       __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
15125       __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
15126       __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
15127       __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
15128       __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
15129       __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
15130       __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
15131       __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
15132       __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
15133       __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
15134       __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
15135       __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
15136       __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
15137       __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
15138       __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
15139       __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
15140     } DSP1N1INT1STAT_b;
15141   } ;
15142 
15143   union {
15144     __IOM uint32_t DSP1N1INT1CLR;               /*!< (@ 0x00000418) Write a 1 to a bit in this register to clear
15145                                                                     the interrupt status associated with that
15146                                                                     bit.                                                       */
15147 
15148     struct {
15149       __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
15150       __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
15151       __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
15152       __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
15153       __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
15154       __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
15155       __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
15156       __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
15157       __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
15158       __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
15159       __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
15160       __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
15161       __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
15162       __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
15163       __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
15164       __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
15165       __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
15166       __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
15167       __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
15168       __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
15169       __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
15170       __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
15171       __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
15172       __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
15173       __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
15174       __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
15175       __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
15176       __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
15177       __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
15178       __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
15179       __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
15180       __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
15181     } DSP1N1INT1CLR_b;
15182   } ;
15183 
15184   union {
15185     __IOM uint32_t DSP1N1INT1SET;               /*!< (@ 0x0000041C) Write a 1 to a bit in this register to instantly
15186                                                                     generate an interrupt from this module.
15187                                                                     (Generally used for testing purposes).                     */
15188 
15189     struct {
15190       __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
15191       __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
15192       __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
15193       __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
15194       __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
15195       __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
15196       __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
15197       __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
15198       __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
15199       __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
15200       __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
15201       __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
15202       __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
15203       __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
15204       __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
15205       __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
15206       __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
15207       __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
15208       __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
15209       __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
15210       __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
15211       __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
15212       __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
15213       __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
15214       __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
15215       __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
15216       __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
15217       __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
15218       __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
15219       __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
15220       __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
15221       __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
15222     } DSP1N1INT1SET_b;
15223   } ;
15224 
15225   union {
15226     __IOM uint32_t DSP1N1INT2EN;                /*!< (@ 0x00000420) Set bits in this register to allow this module
15227                                                                     to generate the corresponding interrupt.                   */
15228 
15229     struct {
15230       __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
15231       __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
15232       __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
15233       __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
15234       __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
15235       __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
15236       __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
15237       __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
15238       __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
15239       __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
15240       __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
15241       __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
15242       __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
15243       __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
15244       __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
15245       __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
15246       __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
15247       __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
15248       __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
15249       __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
15250       __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
15251       __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
15252       __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
15253       __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
15254       __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
15255       __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
15256       __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
15257       __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
15258       __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
15259       __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
15260       __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
15261       __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
15262     } DSP1N1INT2EN_b;
15263   } ;
15264 
15265   union {
15266     __IOM uint32_t DSP1N1INT2STAT;              /*!< (@ 0x00000424) Read bits from this register to discover the
15267                                                                     cause of a recent interrupt.                               */
15268 
15269     struct {
15270       __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
15271       __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
15272       __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
15273       __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
15274       __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
15275       __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
15276       __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
15277       __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
15278       __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
15279       __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
15280       __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
15281       __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
15282       __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
15283       __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
15284       __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
15285       __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
15286       __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
15287       __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
15288       __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
15289       __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
15290       __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
15291       __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
15292       __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
15293       __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
15294       __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
15295       __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
15296       __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
15297       __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
15298       __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
15299       __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
15300       __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
15301       __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
15302     } DSP1N1INT2STAT_b;
15303   } ;
15304 
15305   union {
15306     __IOM uint32_t DSP1N1INT2CLR;               /*!< (@ 0x00000428) Write a 1 to a bit in this register to clear
15307                                                                     the interrupt status associated with that
15308                                                                     bit.                                                       */
15309 
15310     struct {
15311       __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
15312       __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
15313       __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
15314       __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
15315       __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
15316       __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
15317       __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
15318       __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
15319       __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
15320       __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
15321       __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
15322       __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
15323       __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
15324       __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
15325       __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
15326       __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
15327       __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
15328       __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
15329       __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
15330       __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
15331       __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
15332       __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
15333       __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
15334       __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
15335       __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
15336       __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
15337       __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
15338       __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
15339       __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
15340       __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
15341       __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
15342       __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
15343     } DSP1N1INT2CLR_b;
15344   } ;
15345 
15346   union {
15347     __IOM uint32_t DSP1N1INT2SET;               /*!< (@ 0x0000042C) Write a 1 to a bit in this register to instantly
15348                                                                     generate an interrupt from this module.
15349                                                                     (Generally used for testing purposes).                     */
15350 
15351     struct {
15352       __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
15353       __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
15354       __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
15355       __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
15356       __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
15357       __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
15358       __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
15359       __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
15360       __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
15361       __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
15362       __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
15363       __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
15364       __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
15365       __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
15366       __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
15367       __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
15368       __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
15369       __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
15370       __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
15371       __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
15372       __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
15373       __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
15374       __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
15375       __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
15376       __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
15377       __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
15378       __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
15379       __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
15380       __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
15381       __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
15382       __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
15383       __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
15384     } DSP1N1INT2SET_b;
15385   } ;
15386 
15387   union {
15388     __IOM uint32_t DSP1N1INT3EN;                /*!< (@ 0x00000430) Set bits in this register to allow this module
15389                                                                     to generate the corresponding interrupt.                   */
15390 
15391     struct {
15392       __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
15393       __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
15394       __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
15395       __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
15396       __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
15397       __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
15398       __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
15399       __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
15400       __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
15401       __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
15402       __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
15403       __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
15404       __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
15405       __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
15406       __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
15407       __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
15408       __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
15409       __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
15410       __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
15411       __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
15412       __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
15413       __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
15414       __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
15415       __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
15416       __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
15417       __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
15418       __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
15419       __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
15420       __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
15421       __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
15422       __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
15423       __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
15424     } DSP1N1INT3EN_b;
15425   } ;
15426 
15427   union {
15428     __IOM uint32_t DSP1N1INT3STAT;              /*!< (@ 0x00000434) Read bits from this register to discover the
15429                                                                     cause of a recent interrupt.                               */
15430 
15431     struct {
15432       __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
15433       __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
15434       __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
15435       __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
15436       __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
15437       __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
15438       __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
15439       __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
15440       __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
15441       __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
15442       __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
15443       __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
15444       __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
15445       __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
15446       __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
15447       __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
15448       __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
15449       __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
15450       __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
15451       __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
15452       __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
15453       __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
15454       __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
15455       __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
15456       __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
15457       __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
15458       __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
15459       __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
15460       __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
15461       __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
15462       __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
15463       __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
15464     } DSP1N1INT3STAT_b;
15465   } ;
15466 
15467   union {
15468     __IOM uint32_t DSP1N1INT3CLR;               /*!< (@ 0x00000438) Write a 1 to a bit in this register to clear
15469                                                                     the interrupt status associated with that
15470                                                                     bit.                                                       */
15471 
15472     struct {
15473       __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
15474       __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
15475       __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
15476       __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
15477       __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
15478       __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
15479       __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
15480       __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
15481       __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
15482       __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
15483       __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
15484       __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
15485       __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
15486       __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
15487       __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
15488       __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
15489       __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
15490       __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
15491       __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
15492       __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
15493       __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
15494       __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
15495       __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
15496       __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
15497       __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
15498       __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
15499       __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
15500       __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
15501       __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
15502       __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
15503       __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
15504       __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
15505     } DSP1N1INT3CLR_b;
15506   } ;
15507 
15508   union {
15509     __IOM uint32_t DSP1N1INT3SET;               /*!< (@ 0x0000043C) Write a 1 to a bit in this register to instantly
15510                                                                     generate an interrupt from this module.
15511                                                                     (Generally used for testing purposes).                     */
15512 
15513     struct {
15514       __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
15515       __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
15516       __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
15517       __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
15518       __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
15519       __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
15520       __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
15521       __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
15522       __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
15523       __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
15524       __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
15525       __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
15526       __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
15527       __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
15528       __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
15529       __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
15530       __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
15531       __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
15532       __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
15533       __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
15534       __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
15535       __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
15536       __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
15537       __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
15538       __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
15539       __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
15540       __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
15541       __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
15542       __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
15543       __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
15544       __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
15545       __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
15546     } DSP1N1INT3SET_b;
15547   } ;
15548 } GPIO_Type;                                    /*!< Size = 1088 (0x440)                                                       */
15549 
15550 
15551 
15552 /* =========================================================================================================================== */
15553 /* ================                                            GPU                                            ================ */
15554 /* =========================================================================================================================== */
15555 
15556 
15557 /**
15558   * @brief Graphics Processing Unit (GPU)
15559   */
15560 
15561 typedef struct {                                /*!< (@ 0x40090000) GPU Structure                                              */
15562 
15563   union {
15564     __IOM uint32_t TEX0BASE;                    /*!< (@ 0x00000000) Base address of the drawing surface 0 (must be
15565                                                                     word aligned).                                             */
15566 
15567     struct {
15568       __IOM uint32_t Base       : 32;           /*!< [31..0] Address 0: base address of the drawing surface 0 (must
15569                                                      be word aligned).                                                         */
15570     } TEX0BASE_b;
15571   } ;
15572 
15573   union {
15574     __IOM uint32_t TEX0STRIDE;                  /*!< (@ 0x00000004) Image 0 mode and stride.                                   */
15575 
15576     struct {
15577       __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
15578                                                      to another                                                                */
15579       __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] Image Mode                                                       */
15580       __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] Image Format                                                     */
15581     } TEX0STRIDE_b;
15582   } ;
15583 
15584   union {
15585     __IOM uint32_t TEX0RES;                     /*!< (@ 0x00000008) Image 0 resolution.                                        */
15586 
15587     struct {
15588       __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
15589       __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
15590     } TEX0RES_b;
15591   } ;
15592   __IM  uint32_t  RESERVED;
15593 
15594   union {
15595     __IOM uint32_t TEX1BASE;                    /*!< (@ 0x00000010) Base address of the drawing surface 1 (must be
15596                                                                     word aligned).                                             */
15597 
15598     struct {
15599       __IOM uint32_t Base       : 32;           /*!< [31..0] address 1: base address of the drawing surface 1 (must
15600                                                      be word aligned).                                                         */
15601     } TEX1BASE_b;
15602   } ;
15603 
15604   union {
15605     __IOM uint32_t TEX1STRIDE;                  /*!< (@ 0x00000014) Image 1 mode and stride.                                   */
15606 
15607     struct {
15608       __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
15609                                                      to another                                                                */
15610       __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] Image Mode                                                       */
15611       __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] Image Format                                                     */
15612     } TEX1STRIDE_b;
15613   } ;
15614 
15615   union {
15616     __IOM uint32_t TEX1RES;                     /*!< (@ 0x00000018) Image 1 resolution.                                        */
15617 
15618     struct {
15619       __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
15620       __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
15621     } TEX1RES_b;
15622   } ;
15623 
15624   union {
15625     __IOM uint32_t TEX1COLOR;                   /*!< (@ 0x0000001C) Texture maps default color.Used with luminance
15626                                                                     and alpha-only color formats.                              */
15627 
15628     struct {
15629       __IOM uint32_t RED        : 8;            /*!< [7..0] red value                                                          */
15630       __IOM uint32_t GREEN      : 8;            /*!< [15..8] green value                                                       */
15631       __IOM uint32_t BLUE       : 8;            /*!< [23..16] blue value                                                       */
15632       __IOM uint32_t ALPHA      : 8;            /*!< [31..24] alpha value                                                      */
15633     } TEX1COLOR_b;
15634   } ;
15635 
15636   union {
15637     __IOM uint32_t TEX2BASE;                    /*!< (@ 0x00000020) Base address of the drawing surface 2 (must be
15638                                                                     word aligned).                                             */
15639 
15640     struct {
15641       __IOM uint32_t Drawing    : 32;           /*!< [31..0] surface 2 Base address of the drawing surface 2                   */
15642     } TEX2BASE_b;
15643   } ;
15644 
15645   union {
15646     __IOM uint32_t TEX2STRIDE;                  /*!< (@ 0x00000024) Image 2 mode and stride.                                   */
15647 
15648     struct {
15649       __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
15650                                                      to another                                                                */
15651       __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] image mode                                                       */
15652       __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] image format                                                     */
15653     } TEX2STRIDE_b;
15654   } ;
15655 
15656   union {
15657     __IOM uint32_t TEX2RES;                     /*!< (@ 0x00000028) Image 2 resolution.                                        */
15658 
15659     struct {
15660       __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
15661       __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
15662     } TEX2RES_b;
15663   } ;
15664   __IM  uint32_t  RESERVED1;
15665 
15666   union {
15667     __IOM uint32_t TEX3BASE;                    /*!< (@ 0x00000030) Base address of the drawing surface 3 (must be
15668                                                                     word aligned).                                             */
15669 
15670     struct {
15671       __IOM uint32_t Image      : 32;           /*!< [31..0] 3 Base address of the drawing surface                             */
15672     } TEX3BASE_b;
15673   } ;
15674 
15675   union {
15676     __IOM uint32_t TEX3STRIDE;                  /*!< (@ 0x00000034) mode and stride.                                           */
15677 
15678     struct {
15679       __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
15680                                                      to another                                                                */
15681       __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] image mode                                                       */
15682       __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] image format                                                     */
15683     } TEX3STRIDE_b;
15684   } ;
15685 
15686   union {
15687     __IOM uint32_t TEX3RES;                     /*!< (@ 0x00000038) Image 3 resolution.                                        */
15688 
15689     struct {
15690       __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
15691       __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
15692     } TEX3RES_b;
15693   } ;
15694   __IM  uint32_t  RESERVED2[21];
15695 
15696   union {
15697     __IOM uint32_t CGCMD;                       /*!< (@ 0x00000090) Clock gating enable                                        */
15698 
15699     struct {
15700       __IOM uint32_t STOP       : 1;            /*!< [0..0] stop clock                                                         */
15701       __IOM uint32_t START      : 1;            /*!< [1..1] start clock                                                        */
15702             uint32_t            : 30;
15703     } CGCMD_b;
15704   } ;
15705 
15706   union {
15707     __IOM uint32_t CGCTRL;                      /*!< (@ 0x00000094) CGCTRL register description needed here.                   */
15708 
15709     struct {
15710       __IOM uint32_t DISCLKPROC : 1;            /*!< [0..0] disable clock gating for command list processor                    */
15711       __IOM uint32_t DISCLKCFG  : 1;            /*!< [1..1] disable clock gating for configuration file                        */
15712       __IOM uint32_t DISCLKFRAME : 2;           /*!< [3..2] disable clock gating for framebuffer 0 (MISTAKE ?)                 */
15713       __IOM uint32_t RSVD0      : 19;           /*!< [22..4] This bitfield is reserved.                                        */
15714       __IOM uint32_t DISCLKCORE : 1;            /*!< [23..23] disable clock gating for core 0                                  */
15715       __IOM uint32_t RSVD1      : 6;            /*!< [29..24] This bitfield is reserved.                                       */
15716       __IOM uint32_t DISCLKMOD  : 2;            /*!< [31..30] disable clock gating for all modules (MISTAKE ?)                 */
15717     } CGCTRL_b;
15718   } ;
15719 
15720   union {
15721     __IOM uint32_t DIRTYTRIGMIN;                /*!< (@ 0x00000098) Resets dirty region to resolution size when written.       */
15722 
15723     struct {
15724       __IOM uint32_t DRTYREG    : 32;           /*!< [31..0] Resets dirty region to resolution size when written.              */
15725     } DIRTYTRIGMIN_b;
15726   } ;
15727 
15728   union {
15729     __IOM uint32_t DIRTYTRIGMAX;                /*!< (@ 0x0000009C) Resets dirty region to resolution size when written.       */
15730 
15731     struct {
15732       __IOM uint32_t DRTYREG    : 32;           /*!< [31..0] Resets dirty region to resolution size when written.              */
15733     } DIRTYTRIGMAX_b;
15734   } ;
15735   __IM  uint32_t  RESERVED3[4];
15736 
15737   union {
15738     __IOM uint32_t STATUS;                      /*!< (@ 0x000000B0) On read, returns GPU status (CHECK address!!).             */
15739 
15740     struct {
15741       __IOM uint32_t COREBSY    : 4;            /*!< [3..0] processing core busy (Cores 3-0)                                   */
15742       __IOM uint32_t PIPEBSY    : 4;            /*!< [7..4] pipeline busy (Cores 3-0)                                          */
15743       __IOM uint32_t TEXTMAPBSY : 4;            /*!< [11..8] texture map busy (Cores 3-0)                                      */
15744       __IOM uint32_t RENDERBSY  : 4;            /*!< [15..12] render output unit busy (Cores 3-0)                              */
15745       __IOM uint32_t DEPTHFIFOBSY : 4;          /*!< [19..16] depth buffer busy (Cores 3-0)                                    */
15746             uint32_t            : 4;
15747       __IOM uint32_t RASTBSY    : 4;            /*!< [27..24] rasterizer busy                                                  */
15748       __IOM uint32_t CLPBSY     : 1;            /*!< [28..28] command list processor busy                                      */
15749       __IOM uint32_t CLBSY      : 1;            /*!< [29..29] command list bus busy                                            */
15750       __IOM uint32_t MEMBSY     : 1;            /*!< [30..30] memory system busy                                               */
15751       __IOM uint32_t SYSBSY     : 1;            /*!< [31..31] system busy                                                      */
15752     } STATUS_b;
15753   } ;
15754   __IM  uint32_t  RESERVED4[3];
15755 
15756   union {
15757     __IOM uint32_t BUSCTRL;                     /*!< (@ 0x000000C0) Bus Control                                                */
15758 
15759     struct {
15760       __IOM uint32_t BUSCTRL    : 32;           /*!< [31..0] Bus Control                                                       */
15761     } BUSCTRL_b;
15762   } ;
15763 
15764   union {
15765     __IOM uint32_t IMEMLDIADDR;                 /*!< (@ 0x000000C4) Load shader instruction memory address.                    */
15766 
15767     struct {
15768       __IOM uint32_t IMEM       : 32;           /*!< [31..0] ADDR Load shader. Load shader instruction memory address.         */
15769     } IMEMLDIADDR_b;
15770   } ;
15771 
15772   union {
15773     __IOM uint32_t IMEMLDIDATAHL;               /*!< (@ 0x000000C8) Load shader instruction Memory data (31:0).                */
15774 
15775     struct {
15776       __IOM uint32_t IMEM       : 32;           /*!< [31..0] DATA Load shader. Load shader instruction Memory data
15777                                                      (31:0).                                                                   */
15778     } IMEMLDIDATAHL_b;
15779   } ;
15780 
15781   union {
15782     __IOM uint32_t IMEMLDIDATAHH;               /*!< (@ 0x000000CC) Load shader instruction Memory data (63:32).               */
15783 
15784     struct {
15785       __IOM uint32_t IMEM       : 32;           /*!< [31..0] DATA Load shader. Load shader instruction Memory data
15786                                                      (63:32).                                                                  */
15787     } IMEMLDIDATAHH_b;
15788   } ;
15789   __IM  uint32_t  RESERVED5[6];
15790 
15791   union {
15792     __IOM uint32_t CMDLISTSTATUS;               /*!< (@ 0x000000E8) On read, returns command list processor status;
15793                                                                     On write, resets command list processor.                   */
15794 
15795     struct {
15796       __IOM uint32_t LIST       : 1;            /*!< [0..0] processor status                                                   */
15797             uint32_t            : 31;
15798     } CMDLISTSTATUS_b;
15799   } ;
15800 
15801   union {
15802     __IOM uint32_t CMDLISTRINGSTOP;             /*!< (@ 0x000000EC) Updates GPU command list pointer to stop executing.        */
15803 
15804     struct {
15805       __IOM uint32_t UPDATEPRT  : 32;           /*!< [31..0] Updates GPU command list pointer to stop executing.               */
15806     } CMDLISTRINGSTOP_b;
15807   } ;
15808 
15809   union {
15810     __IOM uint32_t CMDLISTADDR;                 /*!< (@ 0x000000F0) Command list base pointer.                                 */
15811 
15812     struct {
15813       __IOM uint32_t BASEPTR    : 32;           /*!< [31..0] Command list base pointer.                                        */
15814     } CMDLISTADDR_b;
15815   } ;
15816 
15817   union {
15818     __IOM uint32_t CMDLISTSIZE;                 /*!< (@ 0x000000F4) Command list length in words.                              */
15819 
15820     struct {
15821       __IOM uint32_t LISTWORDS  : 32;           /*!< [31..0] Command list length in words.                                     */
15822     } CMDLISTSIZE_b;
15823   } ;
15824 
15825   union {
15826     __IOM uint32_t INTERRUPTCTRL;               /*!< (@ 0x000000F8) On write, clears the IRQ (CHECK address!).                 */
15827 
15828     struct {
15829       __IOM uint32_t IRQACTIVE  : 1;            /*!< [0..0] if set to zero IRQ is active high, if set to one IRQ
15830                                                      is active low                                                             */
15831       __IOM uint32_t INTCMDEND  : 1;            /*!< [1..1] if set, signals interrupt at the end of command list               */
15832       __IOM uint32_t INTDRAWEND : 1;            /*!< [2..2] if set, signals interrupt at the end of drawing command            */
15833       __IOM uint32_t AUTOCLR    : 1;            /*!< [3..3] if set, auto clears interrupt                                      */
15834       __IOM uint32_t RSVD       : 26;           /*!< [29..4] This bitfield is reserved.                                        */
15835       __IOM uint32_t CHANGEFREQ : 2;            /*!< [31..30] change frequency of asynchronous clock                           */
15836     } INTERRUPTCTRL_b;
15837   } ;
15838 
15839   union {
15840     __IOM uint32_t SYSCLEAR;                    /*!< (@ 0x000000FC) On write, resets the GPU (CHECK address!).                 */
15841 
15842     struct {
15843       __IOM uint32_t RESETGPU   : 32;           /*!< [31..0] On write, resets the GPU (CHECK address!).                        */
15844     } SYSCLEAR_b;
15845   } ;
15846 
15847   union {
15848     __IOM uint32_t DRAWCMD;                     /*!< (@ 0x00000100) Rasterizer drawing command.                                */
15849 
15850     struct {
15851       __IOM uint32_t START      : 3;            /*!< [2..0] Start the draw command                                             */
15852       __IOM uint32_t RSVD       : 29;           /*!< [31..3] This bitfield is reserved.                                        */
15853     } DRAWCMD_b;
15854   } ;
15855 
15856   union {
15857     __IOM uint32_t DRAWPT0;                     /*!< (@ 0x00000104) Stores only integer values. For greater accurancy
15858                                                                     DRAWPT0X and DRAWPT0Y registers are used
15859                                                                     which are 16, 16 fixed point.                              */
15860 
15861     struct {
15862       __IOM uint32_t COORDX     : 16;           /*!< [15..0] vertex 0 X coordinate (integer value)                             */
15863       __IOM uint32_t COORDY     : 16;           /*!< [31..16] vertex 0 Y coordinate (integer value)                            */
15864     } DRAWPT0_b;
15865   } ;
15866 
15867   union {
15868     __IOM uint32_t DRAWPT1;                     /*!< (@ 0x00000108) Stores only integer values. Vertex 1 drawing
15869                                                                     primitive. Stores only integer values. For
15870                                                                     greater accurancy DRAWPT1X and DRAWPT1Y
15871                                                                     registers are used which are 16, 16 fixed
15872                                                                     point.                                                     */
15873 
15874     struct {
15875       __IOM uint32_t COORDX     : 16;           /*!< [15..0] vertex 0 X coordinate (integer value)                             */
15876       __IOM uint32_t COORDY     : 16;           /*!< [31..16] vertex 0 Y coordinate (integer value)                            */
15877     } DRAWPT1_b;
15878   } ;
15879   __IM  uint32_t  RESERVED6;
15880 
15881   union {
15882     __IOM uint32_t CLIPMIN;                     /*!< (@ 0x00000110) Clipping rectangle upper left vertex.                      */
15883 
15884     struct {
15885       __IOM uint32_t COORDX     : 16;           /*!< [15..0] upper left X coordinate                                           */
15886       __IOM uint32_t COORDY     : 16;           /*!< [31..16] upper left Y coordinate                                          */
15887     } CLIPMIN_b;
15888   } ;
15889 
15890   union {
15891     __IOM uint32_t CLIPMAX;                     /*!< (@ 0x00000114) Clipping rectangle bottom right vertex.                    */
15892 
15893     struct {
15894       __IOM uint32_t COORDX     : 16;           /*!< [15..0] bottom right X coordinate                                         */
15895       __IOM uint32_t COORDY     : 16;           /*!< [31..16] bottom right Y coordinate                                        */
15896     } CLIPMAX_b;
15897   } ;
15898 
15899   union {
15900     __IOM uint32_t RASTCTRL;                    /*!< (@ 0x00000118) Rasterizer matrix multiplication control                   */
15901 
15902     struct {
15903       __IOM uint32_t RSVD       : 28;           /*!< [27..0] This bitfield is reserved.                                        */
15904       __IOM uint32_t BYPASS     : 1;            /*!< [28..28] tells module to bypass calculations                              */
15905       __IOM uint32_t ADD        : 1;            /*!< [29..29] adds 0.5 to X and Y                                              */
15906       __IOM uint32_t PERSP      : 2;            /*!< [31..30] when set to 0 is in perspective mode (MISTAKE IN DOC?)           */
15907     } RASTCTRL_b;
15908   } ;
15909 
15910   union {
15911     __IOM uint32_t DRAWCODEPTR;                 /*!< (@ 0x0000011C) DRAWCODEPTR register description needed here.              */
15912 
15913     struct {
15914       __IOM uint32_t FRGND      : 16;           /*!< [15..0] the pointer for the instruction that will be executed
15915                                                      for foreground pixel                                                      */
15916       __IOM uint32_t BKGND      : 16;           /*!< [31..16] the pointer for the instruction that will be executed
15917                                                      for background pixel                                                      */
15918     } DRAWCODEPTR_b;
15919   } ;
15920 
15921   union {
15922     __IOM uint32_t DRAWPT0X;                    /*!< (@ 0x00000120) X coordinate of Vertex 0 drawing primitive 16,
15923                                                                     16 fixed point.                                            */
15924 
15925     struct {
15926       __IOM uint32_t DRAW0X     : 32;           /*!< [31..0] X coordinate                                                      */
15927     } DRAWPT0X_b;
15928   } ;
15929 
15930   union {
15931     __IOM uint32_t DRAWPT0Y;                    /*!< (@ 0x00000124) Y coordinate of Vertex 0 drawing primitive 16,
15932                                                                     16 fixed point.                                            */
15933 
15934     struct {
15935       __IOM uint32_t DRAW0Y     : 32;           /*!< [31..0] Y coordinate                                                      */
15936     } DRAWPT0Y_b;
15937   } ;
15938 
15939   union {
15940     __IOM uint32_t DRAWPT0Z;                    /*!< (@ 0x00000128) DRAWPTOX register description needed here.                 */
15941 
15942     struct {
15943       __IOM uint32_t DRAW0Z     : 32;           /*!< [31..0] This bitfield is reserved.                                        */
15944     } DRAWPT0Z_b;
15945   } ;
15946 
15947   union {
15948     __IOM uint32_t DRAWCOLOR;                   /*!< (@ 0x0000012C) DRAWCOLOR register description needed here.                */
15949 
15950     struct {
15951       __IOM uint32_t RASTPRIM   : 32;           /*!< [31..0] Rasterizer drawing                                                */
15952     } DRAWCOLOR_b;
15953   } ;
15954 
15955   union {
15956     __IOM uint32_t DRAWPT1X;                    /*!< (@ 0x00000130) X coordinate of Vertex 1 drawing primitive 16,
15957                                                                     16 fixed point.                                            */
15958 
15959     struct {
15960       __IOM uint32_t DRAW1X     : 32;           /*!< [31..0] X coordinate                                                      */
15961     } DRAWPT1X_b;
15962   } ;
15963 
15964   union {
15965     __IOM uint32_t DRAWPT1Y;                    /*!< (@ 0x00000134) Y coordinate of Vertex 1 drawing primitive 16,
15966                                                                     16 fixed point.                                            */
15967 
15968     struct {
15969       __IOM uint32_t DRAW1Y     : 32;           /*!< [31..0] Y coordinate                                                      */
15970     } DRAWPT1Y_b;
15971   } ;
15972 
15973   union {
15974     __IOM uint32_t DRAWPT1Z;                    /*!< (@ 0x00000138) DRAWPT1Z register description needed here.                 */
15975 
15976     struct {
15977       __IOM uint32_t DRAW1Z     : 32;           /*!< [31..0] This bitfield is reserved.                                        */
15978     } DRAWPT1Z_b;
15979   } ;
15980   __IM  uint32_t  RESERVED7;
15981 
15982   union {
15983     __IOM uint32_t DRAWPT2X;                    /*!< (@ 0x00000140) X coordinate of Vertex 2 drawing primitive 16,
15984                                                                     16 fixed point.                                            */
15985 
15986     struct {
15987       __IOM uint32_t DRAW2X     : 32;           /*!< [31..0] X coordinate                                                      */
15988     } DRAWPT2X_b;
15989   } ;
15990 
15991   union {
15992     __IOM uint32_t DRAWPT2Y;                    /*!< (@ 0x00000144) Y coordinate of Vertex 2 drawing primitive 16,
15993                                                                     16 fixed point.                                            */
15994 
15995     struct {
15996       __IOM uint32_t DRAW2Y     : 32;           /*!< [31..0] Y coordinate                                                      */
15997     } DRAWPT2Y_b;
15998   } ;
15999 
16000   union {
16001     __IOM uint32_t DRAWPT2Z;                    /*!< (@ 0x00000148) DRAWPT2Z register description needed here.                 */
16002 
16003     struct {
16004       __IOM uint32_t RSVD       : 32;           /*!< [31..0] This bitfield is reserved.                                        */
16005     } DRAWPT2Z_b;
16006   } ;
16007   __IM  uint32_t  RESERVED8;
16008 
16009   union {
16010     __IOM uint32_t DRAWPT3X;                    /*!< (@ 0x00000150) X coordinate of Vertex 3 drawing primitive 16,
16011                                                                     16 fixed point.                                            */
16012 
16013     struct {
16014       __IOM uint32_t DRAW3X     : 32;           /*!< [31..0] X coordinate                                                      */
16015     } DRAWPT3X_b;
16016   } ;
16017 
16018   union {
16019     __IOM uint32_t DRAWPT3Y;                    /*!< (@ 0x00000154) Y coordinate of Vertex 3 drawing primitive 16,
16020                                                                     16 fixed point.                                            */
16021 
16022     struct {
16023       __IOM uint32_t DRAW3Y     : 32;           /*!< [31..0] Y coordinate.                                                     */
16024     } DRAWPT3Y_b;
16025   } ;
16026 
16027   union {
16028     __IOM uint32_t DRAWPT3Z;                    /*!< (@ 0x00000158) Fixed value (not accessible). Registers 0x160-0x180
16029                                                                     are the elements of the 3x3 transformation
16030                                                                     matrix used for homogeneous conversion from
16031                                                                     screen coordinates to texture coordinates;
16032                                                                     the elements are floating points                           */
16033 
16034     struct {
16035       __IOM uint32_t DRAW3Z     : 32;           /*!< [31..0] Fixed value (not accessible)                                      */
16036     } DRAWPT3Z_b;
16037   } ;
16038   __IM  uint32_t  RESERVED9;
16039 
16040   union {
16041     __IOM uint32_t MM00;                        /*!< (@ 0x00000160) matrix floating point element.                             */
16042 
16043     struct {
16044       __IOM uint32_t MTX        : 32;           /*!< [31..0] (0,0). matrix floating point element.                             */
16045     } MM00_b;
16046   } ;
16047 
16048   union {
16049     __IOM uint32_t MM01;                        /*!< (@ 0x00000164) matrix floating point element.                             */
16050 
16051     struct {
16052       __IOM uint32_t MTX        : 32;           /*!< [31..0] (0,1). matrix floating point element.                             */
16053     } MM01_b;
16054   } ;
16055 
16056   union {
16057     __IOM uint32_t MM02;                        /*!< (@ 0x00000168) matrix floating point element; sets to unit matrix
16058                                                                     if previously written element is MM12.                     */
16059 
16060     struct {
16061       __IOM uint32_t MTX        : 32;           /*!< [31..0] (0,2). matrix floating point element.                             */
16062     } MM02_b;
16063   } ;
16064 
16065   union {
16066     __IOM uint32_t MM10;                        /*!< (@ 0x0000016C) matrix floating point element.                             */
16067 
16068     struct {
16069       __IOM uint32_t MTX        : 32;           /*!< [31..0] (1,0). matrix floating point element.                             */
16070     } MM10_b;
16071   } ;
16072 
16073   union {
16074     __IOM uint32_t MM11;                        /*!< (@ 0x00000170) matrix floating point element.                             */
16075 
16076     struct {
16077       __IOM uint32_t MTX        : 32;           /*!< [31..0] (1,1). matrix floating point element                              */
16078     } MM11_b;
16079   } ;
16080 
16081   union {
16082     __IOM uint32_t MM12;                        /*!< (@ 0x00000174) matrix floating point element.                             */
16083 
16084     struct {
16085       __IOM uint32_t MTX        : 32;           /*!< [31..0] (1,2). matrix floating point element.                             */
16086     } MM12_b;
16087   } ;
16088 
16089   union {
16090     __IOM uint32_t MM20;                        /*!< (@ 0x00000178) matrix floating point element.                             */
16091 
16092     struct {
16093       __IOM uint32_t MTX        : 32;           /*!< [31..0] (2,0). matrix floating point element.                             */
16094     } MM20_b;
16095   } ;
16096 
16097   union {
16098     __IOM uint32_t MM21;                        /*!< (@ 0x0000017C) matrix floating point element.                             */
16099 
16100     struct {
16101       __IOM uint32_t MTX        : 32;           /*!< [31..0] (2,1). matrix floating point element.                             */
16102     } MM21_b;
16103   } ;
16104 
16105   union {
16106     __IOM uint32_t MM22;                        /*!< (@ 0x00000180) matrix floating point element.                             */
16107 
16108     struct {
16109       __IOM uint32_t MTX        : 32;           /*!< [31..0] (2,2). matrix floating point element                              */
16110     } MM22_b;
16111   } ;
16112 
16113   union {
16114     __IOM uint32_t DEPTHSTARTL;                 /*!< (@ 0x00000184) Depth value of START pixel, (32 low bits fractional.)      */
16115 
16116     struct {
16117       __IOM uint32_t DEPTH32LO  : 32;           /*!< [31..0] Depth value of START pixel                                        */
16118     } DEPTHSTARTL_b;
16119   } ;
16120 
16121   union {
16122     __IOM uint32_t DEPTHSTARTH;                 /*!< (@ 0x00000188) Depth value of START pixel, (32 high bits integral.)       */
16123 
16124     struct {
16125       __IOM uint32_t DEPTH32HI  : 32;           /*!< [31..0] Depth value of START pixel                                        */
16126     } DEPTHSTARTH_b;
16127   } ;
16128 
16129   union {
16130     __IOM uint32_t DEPTHDXL;                    /*!< (@ 0x0000018C) Added depth value for each step at x-axis (32
16131                                                                     low bits fractional.)                                      */
16132 
16133     struct {
16134       __IOM uint32_t XAXISLO    : 32;           /*!< [31..0] Added depth value for each step at x-axis                         */
16135     } DEPTHDXL_b;
16136   } ;
16137 
16138   union {
16139     __IOM uint32_t DEPTHDXH;                    /*!< (@ 0x00000190) Added depth value for each step at x-axis (32
16140                                                                     high bits integral.)                                       */
16141 
16142     struct {
16143       __IOM uint32_t XAXISHI    : 32;           /*!< [31..0] Added depth value for each step at x-axis                         */
16144     } DEPTHDXH_b;
16145   } ;
16146 
16147   union {
16148     __IOM uint32_t DEPTHDYL;                    /*!< (@ 0x00000194) Added depth value for each step at y-axis (32
16149                                                                     low bits fractional.)                                      */
16150 
16151     struct {
16152       __IOM uint32_t YAXISLO    : 32;           /*!< [31..0] Added depth value for each step at y-axis                         */
16153     } DEPTHDYL_b;
16154   } ;
16155 
16156   union {
16157     __IOM uint32_t DEPTHDYH;                    /*!< (@ 0x00000198) Added depth value for each step at y-axis (32
16158                                                                     high bits integral.)                                       */
16159 
16160     struct {
16161       __IOM uint32_t YAXISHI    : 32;           /*!< [31..0] Added depth value for each step at y-axis                         */
16162     } DEPTHDYH_b;
16163   } ;
16164   __IM  uint32_t  RESERVED10;
16165 
16166   union {
16167     __IOM uint32_t REDX;                        /*!< (@ 0x000001A0) Added red value for each step at x-axis, (16,
16168                                                                     16 fixed point)                                            */
16169 
16170     struct {
16171       __IOM uint32_t REDX       : 32;           /*!< [31..0] Added red value for each step at x-axis                           */
16172     } REDX_b;
16173   } ;
16174 
16175   union {
16176     __IOM uint32_t REDY;                        /*!< (@ 0x000001A4) Added red value for each step at y-axis, (16,
16177                                                                     16 fixed point)                                            */
16178 
16179     struct {
16180       __IOM uint32_t REDY       : 32;           /*!< [31..0] red value for each step at y-axis                                 */
16181     } REDY_b;
16182   } ;
16183 
16184   union {
16185     __IOM uint32_t GREENX;                      /*!< (@ 0x000001A8) Added green value for each step at x-axis, (16,
16186                                                                     16 fixed point)                                            */
16187 
16188     struct {
16189       __IOM uint32_t GREENX     : 32;           /*!< [31..0] Added green value for each step at x-axis                         */
16190     } GREENX_b;
16191   } ;
16192 
16193   union {
16194     __IOM uint32_t GREENY;                      /*!< (@ 0x000001AC) Added green value for each step at y-axis, (16,
16195                                                                     16 fixed point)                                            */
16196 
16197     struct {
16198       __IOM uint32_t GREENY     : 32;           /*!< [31..0] Added green value for each step at y-axis                         */
16199     } GREENY_b;
16200   } ;
16201 
16202   union {
16203     __IOM uint32_t BLUEX;                       /*!< (@ 0x000001B0) Added blue value for each step at x-axis, (16,
16204                                                                     16 fixed point)                                            */
16205 
16206     struct {
16207       __IOM uint32_t BLUEX      : 32;           /*!< [31..0] Added blue value for each step at x-axis                          */
16208     } BLUEX_b;
16209   } ;
16210 
16211   union {
16212     __IOM uint32_t BLUEY;                       /*!< (@ 0x000001B4) Added blue value for each step at y-axis, (16,
16213                                                                     16 fixed point)                                            */
16214 
16215     struct {
16216       __IOM uint32_t BLUEY      : 32;           /*!< [31..0] Added blue value for each step at y-axis                          */
16217     } BLUEY_b;
16218   } ;
16219 
16220   union {
16221     __IOM uint32_t ALFX;                        /*!< (@ 0x000001B8) Added alfa value for each step at x-axis, (16,
16222                                                                     16 fixed point)                                            */
16223 
16224     struct {
16225       __IOM uint32_t ALFX       : 32;           /*!< [31..0] Added alfa value for each step at x-axis                          */
16226     } ALFX_b;
16227   } ;
16228 
16229   union {
16230     __IOM uint32_t ALFY;                        /*!< (@ 0x000001BC) Added alfa value for each step at y-axis, (16,
16231                                                                     16 fixed point)                                            */
16232 
16233     struct {
16234       __IOM uint32_t ALFY       : 32;           /*!< [31..0] Added alfa value for each step at y-axis                          */
16235     } ALFY_b;
16236   } ;
16237 
16238   union {
16239     __IOM uint32_t REDINIT;                     /*!< (@ 0x000001C0) Red value of STARTXY pixel, (16, 16 fixed point)           */
16240 
16241     struct {
16242       __IOM uint32_t REDXY      : 32;           /*!< [31..0] Red value of STARTXY pixel                                        */
16243     } REDINIT_b;
16244   } ;
16245 
16246   union {
16247     __IOM uint32_t GREINIT;                     /*!< (@ 0x000001C4) Green value of STARTXY pixel, (16, 16 fixed point)         */
16248 
16249     struct {
16250       __IOM uint32_t GREENXY    : 32;           /*!< [31..0] Green value of STARTXY pixel                                      */
16251     } GREINIT_b;
16252   } ;
16253 
16254   union {
16255     __IOM uint32_t BLUINIT;                     /*!< (@ 0x000001C8) Blue value of STARTXY pixel, (16, 16 fixed point)          */
16256 
16257     struct {
16258       __IOM uint32_t BLUEXY     : 32;           /*!< [31..0] Blue value of STARTXY pixel                                       */
16259     } BLUINIT_b;
16260   } ;
16261 
16262   union {
16263     __IOM uint32_t ALFINIT;                     /*!< (@ 0x000001CC) Alfa value of STARTXY pixel, (16, 16 fixed point)
16264                                                                     Shader Registers                                           */
16265 
16266     struct {
16267       __IOM uint32_t ALFXY      : 32;           /*!< [31..0] Alfa value of STARTXY pixel                                       */
16268     } ALFINIT_b;
16269   } ;
16270   __IM  uint32_t  RESERVED11[7];
16271 
16272   union {
16273     __IOM uint32_t IDREG;                       /*!< (@ 0x000001EC) Fixed value                                                */
16274 
16275     struct {
16276       __IOM uint32_t GPUID      : 32;           /*!< [31..0] Fixed value for GPU ID                                            */
16277     } IDREG_b;
16278   } ;
16279 
16280   union {
16281     __IOM uint32_t LOADCTRL;                    /*!< (@ 0x000001F0) Load Control                                               */
16282 
16283     struct {
16284       __IOM uint32_t LOADCTRL   : 32;           /*!< [31..0] Load Control                                                      */
16285     } LOADCTRL_b;
16286   } ;
16287   __IM  uint32_t  RESERVED12[3];
16288 
16289   union {
16290     __IOM uint32_t C0REG;                       /*!< (@ 0x00000200) Shader constant register 0.                                */
16291 
16292     struct {
16293       __IOM uint32_t C0SHADER   : 32;           /*!< [31..0] Shader constant register 0.                                       */
16294     } C0REG_b;
16295   } ;
16296 
16297   union {
16298     __IOM uint32_t C1REG;                       /*!< (@ 0x00000204) Shader constant register 1.                                */
16299 
16300     struct {
16301       __IOM uint32_t C1SHADER   : 32;           /*!< [31..0] Shader constant register 1.                                       */
16302     } C1REG_b;
16303   } ;
16304 
16305   union {
16306     __IOM uint32_t C2REG;                       /*!< (@ 0x00000208) Shader constant register 2.                                */
16307 
16308     struct {
16309       __IOM uint32_t C2SHADER   : 32;           /*!< [31..0] Shader constant register 2                                        */
16310     } C2REG_b;
16311   } ;
16312 
16313   union {
16314     __IOM uint32_t C3REG;                       /*!< (@ 0x0000020C) Shader constant register 3, the dirty Region
16315                                                                     Register                                                   */
16316 
16317     struct {
16318       __IOM uint32_t C3SHADER   : 32;           /*!< [31..0] Shader constant register 3                                        */
16319     } C3REG_b;
16320   } ;
16321   __IM  uint32_t  RESERVED13[888];
16322 
16323   union {
16324     __IOM uint32_t IRQID;                       /*!< (@ 0x00000FF0) Signals interrupt when set (CHECK address!).               */
16325 
16326     struct {
16327       __IOM uint32_t IRQID      : 32;           /*!< [31..0] Signals interrupt when set (CHECK address!                        */
16328     } IRQID_b;
16329   } ;
16330 } GPU_Type;                                     /*!< Size = 4084 (0xff4)                                                       */
16331 
16332 
16333 
16334 /* =========================================================================================================================== */
16335 /* ================                                           I2S0                                            ================ */
16336 /* =========================================================================================================================== */
16337 
16338 
16339 /**
16340   * @brief I2S ASRC Master/Slave Module (I2S0)
16341   */
16342 
16343 typedef struct {                                /*!< (@ 0x40208000) I2S0 Structure                                             */
16344 
16345   union {
16346     __IOM uint32_t RXDATA;                      /*!< (@ 0x00000000) Read only access to the i2S receive data                   */
16347 
16348     struct {
16349       __IOM uint32_t RXSAMPLE   : 32;           /*!< [31..0] 32b audio sample from the internal receive FIFO. MSB
16350                                                      is always in bit 31                                                       */
16351     } RXDATA_b;
16352   } ;
16353 
16354   union {
16355     __IOM uint32_t RXCHANID;                    /*!< (@ 0x00000004) Read only received channel identification register         */
16356 
16357     struct {
16358       __IOM uint32_t RXCHANID   : 8;            /*!< [7..0] Channel ID value 0-255.                                            */
16359             uint32_t            : 24;
16360     } RXCHANID_b;
16361   } ;
16362 
16363   union {
16364     __IOM uint32_t RXFIFOSTATUS;                /*!< (@ 0x00000008) Holds the number of samples currently in the
16365                                                                     receive FIFO, and the empty condition flag                 */
16366 
16367     struct {
16368       __IOM uint32_t RXSAMPLECNT : 28;          /*!< [27..0] The count of the number of samples currently in the
16369                                                      receive FIFO.                                                             */
16370       __IOM uint32_t RXEMPTY    : 1;            /*!< [28..28] Receive FIFO empty bit. a 1 indicates the receive FIFO
16371                                                      is empty.                                                                 */
16372             uint32_t            : 3;
16373     } RXFIFOSTATUS_b;
16374   } ;
16375 
16376   union {
16377     __IOM uint32_t RXFIFOSIZE;                  /*!< (@ 0x0000000C) Holds the size of the receive FIFO in samples              */
16378 
16379     struct {
16380       __IOM uint32_t SIZE       : 32;           /*!< [31..0] Size of the receive FIFO in units of i2S samples. Read
16381                                                      only value.                                                               */
16382     } RXFIFOSIZE_b;
16383   } ;
16384 
16385   union {
16386     __IOM uint32_t RXUPPERLIMIT;                /*!< (@ 0x00000010) The number of samples required to be in the RX
16387                                                                     FIFO before asserting the RX_FFi interrupt
16388                                                                     bit                                                        */
16389 
16390     struct {
16391       __IOM uint32_t SIZE       : 32;           /*!< [31..0] When the I2S sample count stored within the receive
16392                                                      FIFO reaches this value or is larger, the interrupt RX_FFi
16393                                                      bit is asserted.                                                          */
16394     } RXUPPERLIMIT_b;
16395   } ;
16396   __IM  uint32_t  RESERVED[3];
16397 
16398   union {
16399     __IOM uint32_t TXDATA;                      /*!< (@ 0x00000020) Write only register to hold the i2S sample to
16400                                                                     transmit via the write FIFO                                */
16401 
16402     struct {
16403       __IOM uint32_t TXSAMPLE   : 32;           /*!< [31..0] 32b I2S sample to send out of the I2S module via the
16404                                                      external pins. All sample have the MSB in bit 31 regardless
16405                                                      of number of bits per sample and data justification                       */
16406     } TXDATA_b;
16407   } ;
16408 
16409   union {
16410     __IOM uint32_t TXCHANID;                    /*!< (@ 0x00000024) Channel ID used for the next audio sample to
16411                                                                     be written to the data transmission register               */
16412 
16413     struct {
16414       __IOM uint32_t TXCHANID   : 8;            /*!< [7..0] Channel ID value 0-255.                                            */
16415             uint32_t            : 24;
16416     } TXCHANID_b;
16417   } ;
16418 
16419   union {
16420     __IOM uint32_t TXFIFOSTATUS;                /*!< (@ 0x00000028) Holds the number of samples currently in the
16421                                                                     transmit FIFO, and the full condition flag                 */
16422 
16423     struct {
16424       __IOM uint32_t TXFIFOCNT  : 28;           /*!< [27..0] The count of the number of samples currently in the
16425                                                      transmit FIFO.                                                            */
16426       __IOM uint32_t TXFIFOFULL : 1;            /*!< [28..28] Transmit FIFO full bit. a 1 indicates the transmit
16427                                                      FIFO is full.                                                             */
16428             uint32_t            : 3;
16429     } TXFIFOSTATUS_b;
16430   } ;
16431 
16432   union {
16433     __IOM uint32_t TXFIFOSIZE;                  /*!< (@ 0x0000002C) Holds the size of the transmit FIFO in samples             */
16434 
16435     struct {
16436       __IOM uint32_t SIZE       : 32;           /*!< [31..0] Size of the transmit FIFO in units of I2S samples. Read
16437                                                      only value.                                                               */
16438     } TXFIFOSIZE_b;
16439   } ;
16440 
16441   union {
16442     __IOM uint32_t TXLOWERLIMIT;                /*!< (@ 0x00000030) Minimum number of samples have been reached in
16443                                                                     the transmit FIFO.                                         */
16444 
16445     struct {
16446       __IOM uint32_t SIZE       : 32;           /*!< [31..0] When the number of sample in the TX FIFO goes below
16447                                                      this value, the interrupt TX_FFi bit is asserted.                         */
16448     } TXLOWERLIMIT_b;
16449   } ;
16450   __IM  uint32_t  RESERVED1[3];
16451 
16452   union {
16453     __IOM uint32_t I2SDATACFG;                  /*!< (@ 0x00000040) Specifies the data format of I2S sub frames                */
16454 
16455     struct {
16456       __IOM uint32_t SSZ1       : 3;            /*!< [2..0] Receive audio sample length for phase 1. 0: 8b, 2: 16b,
16457                                                      4: 24b, 5: 32b, 1,3,6,7: Reserved                                         */
16458       __IOM uint32_t JUST       : 1;            /*!< [3..3] Audio sample justification. 0: Left-justified, 1: Right-justified  */
16459             uint32_t            : 1;
16460       __IOM uint32_t WDLEN1     : 3;            /*!< [7..5] Receive channel length in bits for phase 1. 0: 8b, 2:
16461                                                      16b, 4: 24b, 5: 32b, 1,3,6,7: Reserved                                    */
16462       __IOM uint32_t FRLEN1     : 7;            /*!< [14..8] Number of channels in phase 1; 0: 1 Channel in phase
16463                                                      2, .. 0x7: 8 channels in phase 1                                          */
16464             uint32_t            : 1;
16465       __IOM uint32_t SSZ2       : 3;            /*!< [18..16] Receive audio sample length for phase 2. 0: 8b, 2:
16466                                                      16b, 4: 24b, 5: 32b, 1,3,6,7: Reserved                                    */
16467       __IOM uint32_t DATADLY    : 2;            /*!< [20..19] Receive data delay bit count. Valid values are 0-2,
16468                                                      3 is reserved.                                                            */
16469       __IOM uint32_t WDLEN2     : 3;            /*!< [23..21] Receive channel length in bits for phase 2. 0: 8b,
16470                                                      2: 16b, 4: 24b, 5: 32b, 1,3,6,7: Reserved                                 */
16471       __IOM uint32_t FRLEN2     : 7;            /*!< [30..24] Number of channels in phase 2; 0: 1 Channel in phase
16472                                                      2, .. 0x7: 8 channels in phase 2                                          */
16473       __IOM uint32_t PH         : 1;            /*!< [31..31] Read Phase Bit. 0: Single Phase frame; 1: Dual-Phase
16474                                                      frame.                                                                    */
16475     } I2SDATACFG_b;
16476   } ;
16477 
16478   union {
16479     __IOM uint32_t I2SIOCFG;                    /*!< (@ 0x00000044) Specified polarity and clock configuration of
16480                                                                     the I2S IPB clocks and IO signals                          */
16481 
16482     struct {
16483       __IOM uint32_t OEN        : 1;            /*!< [0..0] Output enable for SDATA output                                     */
16484             uint32_t            : 3;
16485       __IOM uint32_t FPER       : 12;           /*!< [15..4] Frame period in units of sclk. Period is FPER + 1 sclks
16486                                                      in length. 0: 1 sclk, 0x3F: 64 sclks                                      */
16487       __IOM uint32_t FSP        : 1;            /*!< [16..16] Polarity of fsync/lr_clk signal. 0: Active high. 1:
16488                                                      Active low                                                                */
16489       __IOM uint32_t PRTX       : 1;            /*!< [17..17] Transmit clock edge polarity bit. 0: sdata is transmitted
16490                                                      starting from the falling edge of sclk. 1: sdata is transmitted
16491                                                      starting from the rising edge of sclk.                                    */
16492       __IOM uint32_t MSL        : 1;            /*!< [18..18] Master/Slave clock configuration. 0: External clock(sclk
16493                                                      and lr_clk provided externally). 1: Internal clock (sclk
16494                                                      and lr_clk sourced internally).                                           */
16495       __IOM uint32_t PRx        : 1;            /*!< [19..19] Receive clock edge polarity bit. 0: sdata is sampled
16496                                                      on the rising edge of sclk. 1: sdata is sampled on the
16497                                                      falling edge of sclk.                                                     */
16498       __IOM uint32_t FWID       : 8;            /*!< [27..20] period of fsync/lr_clk in units of sclks                         */
16499             uint32_t            : 4;
16500     } I2SIOCFG_b;
16501   } ;
16502 
16503   union {
16504     __IOM uint32_t I2SCTL;                      /*!< (@ 0x00000048) Specified polarity and clock configuration of
16505                                                                     the I2S IPB clocks and IO signals                          */
16506 
16507     struct {
16508       __IOM uint32_t TXEN       : 1;            /*!< [0..0] Transmit enable signal. 1 will enable the transmission
16509                                                      of serial audio. For Full duplex operation, RXEN and TXEN
16510                                                      MUST be set in a single register write access, or the Slave
16511                                                      FSM may ignore one of the bit-field read-modify-write accesses.
16512                                                      TXRST and RXRST must be cleared in advance.                               */
16513       __IOM uint32_t TXRST      : 1;            /*!< [1..1] Transmit reset signal. 1 will reset the TX side registers
16514                                                      and flush the TX FIFO.                                                    */
16515             uint32_t            : 2;
16516       __IOM uint32_t RXEN       : 1;            /*!< [4..4] Receive enable control. 1: Enables capture of serial
16517                                                      audio, starting with first channel. 0: No receive data
16518                                                      captured. For Full duplex operation, RXEN and TXEN MUST
16519                                                      be set in a single register write access, or the Slave
16520                                                      FSM may ignore one of the bit-field read-modify-write accesses.
16521                                                      TXRST and RXRST must be cleared in advance.                               */
16522       __IOM uint32_t RXRST      : 1;            /*!< [5..5] Active high receiver reset signal. 1: Flush the RX FIFO            */
16523             uint32_t            : 25;
16524       __IOM uint32_t I2SVAL     : 1;            /*!< [31..31] I2S validity bit mode. 1: RX data stored only when
16525                                                      validity mask condition is asserted. 0: No validity mask
16526                                                      conditions checking is done.                                              */
16527     } I2SCTL_b;
16528   } ;
16529 
16530   union {
16531     __IOM uint32_t IPBIRPT;                     /*!< (@ 0x0000004C) Additional mask and status registers for the
16532                                                                     IPB core.                                                  */
16533 
16534     struct {
16535       __IOM uint32_t RXFFM      : 1;            /*!< [0..0] Receive FIFO interrupt mask. Will assert interrupt when
16536                                                      = 1 and RXFFI is asserted                                                 */
16537       __IOM uint32_t TXFFM      : 1;            /*!< [1..1] Transmit FIFO interrupt mask. Will assert interrupt when
16538                                                      = 1 and TXFFI is asserted                                                 */
16539       __IOM uint32_t RXFM       : 1;            /*!< [2..2] Receive FIFO interrupt mask. Will assert interrupt when
16540                                                      = 1 and RXFI is asserted                                                  */
16541       __IOM uint32_t TXEM       : 1;            /*!< [3..3] Transmit FIFO interrupt mask. Will assert interrupt when
16542                                                      = 1 and TXEI is asserted                                                  */
16543       __IOM uint32_t RXDMAM     : 1;            /*!< [4..4] Receive FIFO interrupt mask. Will assert interrupt when
16544                                                      = 1 and cimdmareq_rx is asserted                                          */
16545       __IOM uint32_t TXDMAM     : 1;            /*!< [5..5] Transmit FIFO interrupt mask. Will assert interrupt when
16546                                                      = 1 and cimdmareq_tx is asserted                                          */
16547             uint32_t            : 10;
16548       __IOM uint32_t RXFFI      : 1;            /*!< [16..16] Receive fifo high limit interrupt                                */
16549       __IOM uint32_t TXFFI      : 1;            /*!< [17..17] Transmit fifo low limit interrupt                                */
16550       __IOM uint32_t RXFI       : 1;            /*!< [18..18] RX Full interrupt. RX unit attempted to write to a
16551                                                      full FIFO                                                                 */
16552       __IOM uint32_t TXEI       : 1;            /*!< [19..19] TX Empty interrupt. TX unit attempted to read an empty
16553                                                      FIFO                                                                      */
16554       __IOM uint32_t RXDMAI     : 1;            /*!< [20..20] RX dma interrupt                                                 */
16555       __IOM uint32_t TXDMAI     : 1;            /*!< [21..21] TX dma interrupt                                                 */
16556             uint32_t            : 10;
16557     } IPBIRPT_b;
16558   } ;
16559 
16560   union {
16561     __IOM uint32_t IPCOREID;                    /*!< (@ 0x00000050) Returns the core ID of the IPB core, and used
16562                                                                     to write the I2S validity mask.                            */
16563 
16564     struct {
16565             uint32_t            : 16;
16566       __IOM uint32_t COREID     : 8;            /*!< [23..16] Core ID of the IPB core                                          */
16567       __IOM uint32_t COREFAM    : 8;            /*!< [31..24] Core Family. Also bit 31 is used to set the I2S validity
16568                                                      bit when a write is done.                                                 */
16569     } IPCOREID_b;
16570   } ;
16571 
16572   union {
16573     __IOM uint32_t AMQCFG;                      /*!< (@ 0x00000054) Control the enablement of the ASRC module and
16574                                                                     the source of the MCLK used in the IPB core.               */
16575 
16576     struct {
16577       __IOM uint32_t MCLKSRC    : 1;            /*!< [0..0] MCLK source. 1: Output of nco_clk divider. 0: MCLK from
16578                                                      ambiq clock configuration directly                                        */
16579       __IOM uint32_t ASRCEN     : 1;            /*!< [1..1] ASRC sub module enable. 0: Enabled. 1: Disabled/Bypassed           */
16580             uint32_t            : 30;
16581     } AMQCFG_b;
16582   } ;
16583   __IM  uint32_t  RESERVED2[2];
16584 
16585   union {
16586     __IOM uint32_t INTDIV;                      /*!< (@ 0x00000060) Integer divide value for the nco_clk divider               */
16587 
16588     struct {
16589       __IOM uint32_t INTDIV     : 32;           /*!< [31..0] Integer divide value for internal clock divider                   */
16590     } INTDIV_b;
16591   } ;
16592 
16593   union {
16594     __IOM uint32_t FRACDIV;                     /*!< (@ 0x00000064) Fractional divide value for the nco_clk divider            */
16595 
16596     struct {
16597       __IOM uint32_t FRACDIV    : 32;           /*!< [31..0] Fractional divide value for internal clock divider                */
16598     } FRACDIV_b;
16599   } ;
16600   __IM  uint32_t  RESERVED3[38];
16601 
16602   union {
16603     __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000100) Provides clock selection and control for I2S
16604                                                                     clocks                                                     */
16605 
16606     struct {
16607       __IOM uint32_t MCLKEN     : 1;            /*!< [0..0] Enable for the master audio clock.                                 */
16608             uint32_t            : 3;
16609       __IOM uint32_t FSEL       : 5;            /*!< [8..4] Select the input clock frequency for the MCLK.Whenever
16610                                                      changing the clock source here, the MISC_HFRC2FRC bit in
16611                                                      the CLKGEN module must first be set. The sequence for changing
16612                                                      the clock source regardless of clock selection is to first
16613                                                      force HFRC2 on by setting the CLKGEN_MISC_HFRC2FRC bit,
16614                                                      select the clock source in this field, clear the CLKGEN_MISC_HFRC2FRC
16615                                                      bit only if HFRC2 is NOT selected, and then engage the
16616                                                      peripheral.If HFRC2 is the clock source, then shutting
16617                                                      the module down cleanly requires switchin                                 */
16618             uint32_t            : 3;
16619       __IOM uint32_t REFCLKEN   : 1;            /*!< [12..12] FUTURE USE Enable for the reference clock                        */
16620             uint32_t            : 3;
16621       __IOM uint32_t REFFSEL    : 2;            /*!< [17..16] FUTURE USE Select the input clock frequency for the
16622                                                      ref_clk. 0: HFRC_48MHz 1: HFRC_48MHz_GATED 2: XT_24MHz
16623                                                      3: HFRC2_48MHz                                                            */
16624             uint32_t            : 2;
16625       __IOM uint32_t DIV3       : 1;            /*!< [20..20] 0: no change to the clock selected by FSEL 1: frequency
16626                                                      divide-by-3 of the clock selected by FSEL                                 */
16627             uint32_t            : 11;
16628     } CLKCFG_b;
16629   } ;
16630   __IM  uint32_t  RESERVED4[63];
16631 
16632   union {
16633     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000200) Configuration control of the DMA process, including
16634                                                                     the direction of DMA, and enablement of
16635                                                                     DMA                                                        */
16636 
16637     struct {
16638       __IOM uint32_t RXDMAEN    : 1;            /*!< [0..0] DMA Enable for RX channel. Setting this bit to EN will
16639                                                      start the DMA operation. This should be the last DMA related
16640                                                      register set prior to issuing the command                                 */
16641       __IOM uint32_t RXDMAPRI   : 1;            /*!< [1..1] Sets the Priority of the RXDMA request                             */
16642             uint32_t            : 2;
16643       __IOM uint32_t TXDMAEN    : 1;            /*!< [4..4] DMA Enable for TX channel. Setting this bit to EN will
16644                                                      start the DMA operation. This should be the last DMA related
16645                                                      register set prior to issuing the command                                 */
16646       __IOM uint32_t TXDMAPRI   : 1;            /*!< [5..5] Sets the Priority of the TXDMA request                             */
16647             uint32_t            : 2;
16648       __IOM uint32_t TXREQCNT   : 8;            /*!< [15..8] Number of blocks of samples transferred before asserting
16649                                                      the TXREQCNT interrupt signal. A block is 8 samples. The
16650                                                      interrupt will assert if enabled and after TXREQCNT blocks
16651                                                      of data has been transferred to the I2S module from the
16652                                                      device. A value of 0 will cause the assertion of the interrupt
16653                                                      for every block of transfer done.                                         */
16654       __IOM uint32_t RXREQCNT   : 8;            /*!< [23..16] Number of blocks of samples transferred before asserting
16655                                                      the RXREQCNT interrupt signal. A block is 8 samples. The
16656                                                      interrupt will assert if enabled and after RXREQCNT blocks
16657                                                      of data has been transferred from the I2S into the device.
16658                                                      A value of 0 will cause the assertion of the interrupt
16659                                                      for every block of transfer done.                                         */
16660             uint32_t            : 8;
16661     } DMACFG_b;
16662   } ;
16663 
16664   union {
16665     __IOM uint32_t RXDMATOTCNT;                 /*!< (@ 0x00000204) Contains the total count of samples to be stored
16666                                                                     for the current RX DMA operation. This register
16667                                                                     is updated as DMA beats complete.                          */
16668 
16669     struct {
16670       __IOM uint32_t RXTOTCNT   : 12;           /*!< [11..0] Number of 32b audio samples to transfer for RX DMA.               */
16671             uint32_t            : 20;
16672     } RXDMATOTCNT_b;
16673   } ;
16674 
16675   union {
16676     __IOM uint32_t RXDMAADDR;                   /*!< (@ 0x00000208) The address which the DMA operation will store
16677                                                                     the incoming audio samples. This address
16678                                                                     is updated as the samples are stored.                      */
16679 
16680     struct {
16681       __IOM uint32_t RXTARGADDR : 32;           /*!< [31..0] Address bits of the target byte address for source of
16682                                                      RX write DMA.                                                             */
16683     } RXDMAADDR_b;
16684   } ;
16685 
16686   union {
16687     __IOM uint32_t RXDMASTAT;                   /*!< (@ 0x0000020C) Status of the RX DMA operation currently in progress.      */
16688 
16689     struct {
16690       __IOM uint32_t RXDMATIP   : 1;            /*!< [0..0] RX DMA Transfer In Progress indicator. 1 will indicate
16691                                                      that a DMA transfer is active. The DMA transfer may be
16692                                                      waiting on data, transferring data, or waiting for priority.All
16693                                                      of these will be indicated with a 1. A 0 will indicate
16694                                                      that the DMA is fully complete and no further transactions
16695                                                      will be done. This bit is read only.                                      */
16696       __IOM uint32_t RXDMACPL   : 1;            /*!< [1..1] RX DMA Transfer Complete. This signals the end of the
16697                                                      DMA operation. This bit can be cleared by writing to 0,
16698                                                      and will also be cleared when a new DMA is started.                       */
16699       __IOM uint32_t RXDMAERR   : 1;            /*!< [2..2] RX DMA Error. This active high bit signals an error was
16700                                                      encountered during the DMA operation. The bit can be cleared
16701                                                      by writing to 0. Once set, this bit will remain set until
16702                                                      cleared by software.                                                      */
16703             uint32_t            : 29;
16704     } RXDMASTAT_b;
16705   } ;
16706 
16707   union {
16708     __IOM uint32_t TXDMATOTCNT;                 /*!< (@ 0x00000210) Contains the total count of samples to be read
16709                                                                     and transmitted for the current TX DMA operation.
16710                                                                     This register is updated as DMA beats complete.            */
16711 
16712     struct {
16713       __IOM uint32_t TXTOTCNT   : 12;           /*!< [11..0] Number of 32b audio samples to transmit                           */
16714             uint32_t            : 20;
16715     } TXDMATOTCNT_b;
16716   } ;
16717 
16718   union {
16719     __IOM uint32_t TXDMAADDR;                   /*!< (@ 0x00000214) The address which the DMA operation will fetch
16720                                                                     the audio samples. This address is updated
16721                                                                     as the samples are stored.                                 */
16722 
16723     struct {
16724       __IOM uint32_t TXTARGADDR : 32;           /*!< [31..0] Address bits of the target byte address for source of
16725                                                      TX write DMA.                                                             */
16726     } TXDMAADDR_b;
16727   } ;
16728 
16729   union {
16730     __IOM uint32_t TXDMASTAT;                   /*!< (@ 0x00000218) Status of the TX DMA operation currently in progress.      */
16731 
16732     struct {
16733       __IOM uint32_t TXDMATIP   : 1;            /*!< [0..0] TX DMA Transfer In Progress indicator. 1 will indicate
16734                                                      that a DMA transfer is active. The DMA transfer may be
16735                                                      waiting on data, transferring data, or waiting for priority.All
16736                                                      of these will be indicated with a 1. A 0 will indicate
16737                                                      that the DMA is fully complete and no further transactions
16738                                                      will be done. This bit is read only.                                      */
16739       __IOM uint32_t TXDMACPL   : 1;            /*!< [1..1] TX DMA Transfer Complete. This signals the end of the
16740                                                      DMA operation. This bit can be cleared by writing to 0,
16741                                                      and will also be cleared when a new DMA is started.                       */
16742       __IOM uint32_t TXDMAERR   : 1;            /*!< [2..2] TX DMA Error. This active high bit signals an error was
16743                                                      encountered during the DMA operation. The bit can be cleared
16744                                                      by writing to 0. Once set, this bit will remain set until
16745                                                      cleared by software.                                                      */
16746             uint32_t            : 29;
16747     } TXDMASTAT_b;
16748   } ;
16749   __IM  uint32_t  RESERVED5[5];
16750 
16751   union {
16752     __IOM uint32_t STATUS;                      /*!< (@ 0x00000230) I2S Module Status                                          */
16753 
16754     struct {
16755       __IOM uint32_t TBD        : 1;            /*!< [0..0] To Be determined.                                                  */
16756             uint32_t            : 31;
16757     } STATUS_b;
16758   } ;
16759   __IM  uint32_t  RESERVED6[51];
16760 
16761   union {
16762     __IOM uint32_t INTEN;                       /*!< (@ 0x00000300) Set bits in this register to allow this module
16763                                                                     to generate the corresponding interrupt.                   */
16764 
16765     struct {
16766       __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
16767       __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
16768                                                      of size 8 samples. This interrupt allows servicing of buffers
16769                                                      at a programmable location within the overall DMA transfer.               */
16770       __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
16771                                                      on TX fifo level.                                                         */
16772       __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
16773       __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
16774             uint32_t            : 27;
16775     } INTEN_b;
16776   } ;
16777 
16778   union {
16779     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000304) Read bits from this register to discover the
16780                                                                     cause of a recent interrupt.                               */
16781 
16782     struct {
16783       __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
16784       __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
16785                                                      of size 8 samples. This interrupt allows servicing of buffers
16786                                                      at a programmable location within the overall DMA transfer.               */
16787       __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
16788                                                      on TX fifo level.                                                         */
16789       __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
16790       __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
16791             uint32_t            : 27;
16792     } INTSTAT_b;
16793   } ;
16794 
16795   union {
16796     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000308) Write a 1 to a bit in this register to clear
16797                                                                     the interrupt status associated with that
16798                                                                     bit.                                                       */
16799 
16800     struct {
16801       __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
16802       __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
16803                                                      of size 8 samples. This interrupt allows servicing of buffers
16804                                                      at a programmable location within the overall DMA transfer.               */
16805       __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
16806                                                      on TX fifo level.                                                         */
16807       __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
16808       __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
16809             uint32_t            : 27;
16810     } INTCLR_b;
16811   } ;
16812 
16813   union {
16814     __IOM uint32_t INTSET;                      /*!< (@ 0x0000030C) Write a 1 to a bit in this register to instantly
16815                                                                     generate an interrupt from this module.
16816                                                                     (Generally used for testing purposes).                     */
16817 
16818     struct {
16819       __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
16820       __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
16821                                                      of size 8 samples. This interrupt allows servicing of buffers
16822                                                      at a programmable location within the overall DMA transfer.               */
16823       __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
16824                                                      on TX fifo level.                                                         */
16825       __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
16826       __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
16827             uint32_t            : 27;
16828     } INTSET_b;
16829   } ;
16830   __IM  uint32_t  RESERVED7[60];
16831 
16832   union {
16833     __IOM uint32_t I2SDBG;                      /*!< (@ 0x00000400) Debug control                                              */
16834 
16835     struct {
16836       __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting bit will enable the update of data
16837                                                      within this register, otherwise it is clock gated for power
16838                                                      savings                                                                   */
16839       __IOM uint32_t MCLKON     : 1;            /*!< [1..1] MCLK debug clock control. Enable MCLK to be active when
16840                                                      this bit is '1'. Otherwise, the clock is controlled with
16841                                                      gating from the logic as needed.                                          */
16842       __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
16843                                                      when this bit is '1'. Otherwise, the clock is controlled
16844                                                      with gating from the logic as needed.                                     */
16845       __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used
16846                                                      to select between different debug data available in the
16847                                                      DBG0 and DBG1 registers.                                                  */
16848     } I2SDBG_b;
16849   } ;
16850 } I2S0_Type;                                    /*!< Size = 1028 (0x404)                                                       */
16851 
16852 
16853 
16854 /* =========================================================================================================================== */
16855 /* ================                                           IOM0                                            ================ */
16856 /* =========================================================================================================================== */
16857 
16858 
16859 /**
16860   * @brief IO Peripheral Master (IOM0)
16861   */
16862 
16863 typedef struct {                                /*!< (@ 0x40050000) IOM0 Structure                                             */
16864 
16865   union {
16866     __IOM uint32_t FIFO;                        /*!< (@ 0x00000000) Provides direct random access to both input and
16867                                                                     output fifos. The state of the FIFO is not
16868                                                                     distured by reading these locations (ie
16869                                                                     no POP will be done). FIFO0 is accessible
16870                                                                     from addresses 0x0 - 0x1C, and is used for
16871                                                                     data outuput from the IOM to external devices.
16872                                                                     These FIFO locations can be read and written
16873                                                                     directly.FIFO locations 0x20 - 0x3C provide
16874                                                                     read only access to the input fifo. These
16875                                                                     FIFO locations cannot be directly written
16876                                                                     by the MCU, and are updated only by the
16877                                                                     internal hardware.                                         */
16878 
16879     struct {
16880       __IOM uint32_t FIFO       : 32;           /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return
16881                                                      valid information.                                                        */
16882     } FIFO_b;
16883   } ;
16884   __IM  uint32_t  RESERVED[63];
16885 
16886   union {
16887     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Provides the current valid byte count of data
16888                                                                     within the FIFO as seen from the internal
16889                                                                     state machines. FIFO0 is dedicated to outgoing
16890                                                                     transactions and FIFO1 is dedicated to incoming
16891                                                                     transactions. All counts are specified in
16892                                                                     units of bytes.                                            */
16893 
16894     struct {
16895       __IOM uint32_t FIFO0SIZ   : 8;            /*!< [7..0] The number of valid data bytes currently in the FIFO
16896                                                      0 (written by MCU, read by interface)                                     */
16897       __IOM uint32_t FIFO0REM   : 8;            /*!< [15..8] The number of remaining data bytes slots currently in
16898                                                      FIFO 0 (written by MCU, read by interface)                                */
16899       __IOM uint32_t FIFO1SIZ   : 8;            /*!< [23..16] The number of valid data bytes currently in FIFO 1
16900                                                      (written by interface, read by MCU)                                       */
16901       __IOM uint32_t FIFO1REM   : 8;            /*!< [31..24] The number of remaining data bytes slots currently
16902                                                      in FIFO 1 (written by interface, read by MCU)                             */
16903     } FIFOPTR_b;
16904   } ;
16905 
16906   union {
16907     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000104) Sets the threshold values for incoming and outgoing
16908                                                                     transactions. The threshold values are used
16909                                                                     to assert the interrupt if enabled, and
16910                                                                     also used during DMA to set the transfer
16911                                                                     size as a result of DMATHR trigger.The WTHR
16912                                                                     is used to indicate when there are more
16913                                                                     than WTHR bytes of open fifo locations available
16914                                                                     in the outgoing FIFO (FIFO0). The intended
16915                                                                     use to invoke an interrupt or DMA transfer
16916                                                                     that will refill the FIFO with a byte count
16917                                                                     up to this value.The RTHR is used to indicate
16918                                                                     when t                                                     */
16919 
16920     struct {
16921       __IOM uint32_t FIFORTHR   : 6;            /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable
16922                                                      the read FIFO level from activating the threshold interrupt.
16923                                                      If this field is non-zero, it will trigger a threshold
16924                                                      interrupt when the read fifo contains FIFORTHR valid bytes
16925                                                      of data, as indicated by the FIFO1SIZ field. This is intended
16926                                                      to signal when a data transfer of FIFORTHR bytes can be
16927                                                      done from the IOM module to the host via the read fifo
16928                                                      to support large IOM read operations.                                     */
16929             uint32_t            : 2;
16930       __IOM uint32_t FIFOWTHR   : 6;            /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable
16931                                                      the write FIFO level from activating the threshold interrupt.
16932                                                      If this field is non-zero, it will trigger a threshold
16933                                                      interrupt when the write fifo contains FIFOWTHR free bytes,
16934                                                      as indicated by the FIFO0REM field. This is intended to
16935                                                      signal when a transfer of FIFOWTHR bytes can be done from
16936                                                      the host to the IOM write fifo to support large IOM write
16937                                                      operations.                                                               */
16938             uint32_t            : 18;
16939     } FIFOTHR_b;
16940   } ;
16941 
16942   union {
16943     __IOM uint32_t FIFOPOP;                     /*!< (@ 0x00000108) Will advance the internal read pointer of the
16944                                                                     incoming FIFO (FIFO1) when read, if POPWR
16945                                                                     is not active. If POPWR is active, a write
16946                                                                     to this register is needed to advance the
16947                                                                     internal FIFO pointer.                                     */
16948 
16949     struct {
16950       __IOM uint32_t FIFODOUT   : 32;           /*!< [31..0] This register will return the read data indicated by
16951                                                      the current read pointer on reads. If the POPWR control
16952                                                      bit in the FIFOCTRL register is reset (0), the fifo read
16953                                                      pointer will be advanced by one word as a result of the
16954                                                      read.If the POPWR bit is set (1), the fifo read pointer
16955                                                      will only be advanced after a write operation to this register.
16956                                                      The write data is ignored for this register.If less than
16957                                                      a even word multiple is available, and the command is completed,
16958                                                      the module will return the word containing                                */
16959     } FIFOPOP_b;
16960   } ;
16961 
16962   union {
16963     __IOM uint32_t FIFOPUSH;                    /*!< (@ 0x0000010C) Will write new data into the outgoing FIFO and
16964                                                                     advance the internal write pointer.                        */
16965 
16966     struct {
16967       __IOM uint32_t FIFODIN    : 32;           /*!< [31..0] This register is used to write the FIFORAM in FIFO mode
16968                                                      and will cause a push event to occur to the next open slot
16969                                                      within the FIFORAM. Writing to this register will cause
16970                                                      the write point to increment by 1 word(4 bytes).                          */
16971     } FIFOPUSH_b;
16972   } ;
16973 
16974   union {
16975     __IOM uint32_t FIFOCTRL;                    /*!< (@ 0x00000110) Provides controls for the operation of the internal
16976                                                                     FIFOs. Contains fields used to control the
16977                                                                     operation of the POP register, and also
16978                                                                     controls to reset the internal pointers
16979                                                                     of the FIFOs.                                              */
16980 
16981     struct {
16982       __IOM uint32_t POPWR      : 1;            /*!< [0..0] Selects the mode in which 'pop' events are done for the
16983                                                      fifo read operations. A value of '1' will prevent a pop
16984                                                      event on a read operation, and will require a write to
16985                                                      the FIFOPOP register to create a pop event.A value of '0'
16986                                                      in this register will allow a pop event to occur on the
16987                                                      read of the FIFOPOP register, and may cause inadvertant
16988                                                      fifo pops when used in a debugging mode.                                  */
16989       __IOM uint32_t FIFORSTN   : 1;            /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset
16990                                                      fifo, and then write to 1 to remove the reset.                            */
16991             uint32_t            : 30;
16992     } FIFOCTRL_b;
16993   } ;
16994 
16995   union {
16996     __IOM uint32_t FIFOLOC;                     /*!< (@ 0x00000114) Provides a read only value of the current read
16997                                                                     and write pointers. This register is read
16998                                                                     only and can be used alogn with the FIFO
16999                                                                     direct access method to determine the next
17000                                                                     data to be used for input and output functions.            */
17001 
17002     struct {
17003       __IOM uint32_t FIFOWPTR   : 4;            /*!< [3..0] Current FIFO write pointer. Value is the index into the
17004                                                      outgoing FIFO (FIFO0), which is used during write operations
17005                                                      to external devices.                                                      */
17006             uint32_t            : 4;
17007       __IOM uint32_t FIFORPTR   : 4;            /*!< [11..8] Current FIFO read pointer. Used to index into the incoming
17008                                                      FIFO (FIFO1), which is used to store read data returned
17009                                                      from external devices during a read operation.                            */
17010             uint32_t            : 20;
17011     } FIFOLOC_b;
17012   } ;
17013 
17014   union {
17015     __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000118) Provides clock related controls used internal
17016                                                                     to the BLEIF module, and enablement of 32KHz
17017                                                                     clock to the BLE Core module. The internal
17018                                                                     clock sourced is selected via the FSEL and
17019                                                                     can be further divided by 3 using the DIV3
17020                                                                     control.This register is also used to enable
17021                                                                     the clock, which must be done prior to performing
17022                                                                     any IO transactions.                                       */
17023 
17024     struct {
17025       __IOM uint32_t IOCLKEN    : 1;            /*!< [0..0] Enable for the interface clock. Must be enabled prior
17026                                                      to executing any IO operations.                                           */
17027             uint32_t            : 7;
17028       __IOM uint32_t FSEL       : 3;            /*!< [10..8] Select the input clock frequency.                                 */
17029       __IOM uint32_t DIV3       : 1;            /*!< [11..11] Enable divide by 3 of the source IOCLK. Division by
17030                                                      3 is done before the DIVEN programmable divider, and if
17031                                                      enabledwill provide the divided by 3 clock as the source
17032                                                      to the programmable divider.                                              */
17033       __IOM uint32_t DIVEN      : 1;            /*!< [12..12] Enable clock division by TOTPER and LOWPER                       */
17034             uint32_t            : 3;
17035       __IOM uint32_t LOWPER     : 8;            /*!< [23..16] Clock low clock count minus 1. This provides the number
17036                                                      of clocks the divided clock will be low when the DIVEN
17037                                                      = 1.Only applicable when DIVEN = 1.                                       */
17038       __IOM uint32_t TOTPER     : 8;            /*!< [31..24] Clock total clock count minus 1. This provides the
17039                                                      total period of the divided clock -1 when the DIVEN is
17040                                                      active. Thesource clock is selected by FSEL. Only applicable
17041                                                      when DIVEN = 1.                                                           */
17042     } CLKCFG_b;
17043   } ;
17044 
17045   union {
17046     __IOM uint32_t SUBMODCTRL;                  /*!< (@ 0x0000011C) Provides enable for each submodule. Only a sigle
17047                                                                     submodule can be enabled at one time.                      */
17048 
17049     struct {
17050       __IOM uint32_t SMOD0EN    : 1;            /*!< [0..0] Submodule 0 enable (1) or disable (0)                              */
17051       __IOM uint32_t SMOD0TYPE  : 3;            /*!< [3..1] Submodule 0 module type. This is the SPI Master interface.         */
17052       __IOM uint32_t SMOD1EN    : 1;            /*!< [4..4] Submodule 1 enable (1) or disable (0)                              */
17053       __IOM uint32_t SMOD1TYPE  : 3;            /*!< [7..5] Submodule 1 module type. This is the I2C Master interface          */
17054       __IOM uint32_t SMOD2EN    : 1;            /*!< [8..8] Submodule 2 enable (1) or disable (0)                              */
17055       __IOM uint32_t SMOD2TYPE  : 3;            /*!< [11..9] Submodule 2 module type. This is the I2S Master/Slave
17056                                                      interface                                                                 */
17057             uint32_t            : 20;
17058     } SUBMODCTRL_b;
17059   } ;
17060 
17061   union {
17062     __IOM uint32_t CMD;                         /*!< (@ 0x00000120) Writes to this register will start an IO transaction,
17063                                                                     as well as set various parameters for the
17064                                                                     command itself. Reads will return the command
17065                                                                     value written to the CMD register.To read
17066                                                                     the number of bytes that have yet to be
17067                                                                     transferred, refer to the CTSIZE field within
17068                                                                     the CMDSTAT register.                                      */
17069 
17070     struct {
17071       __IOM uint32_t CMD        : 4;            /*!< [3..0] Command for submodule.                                             */
17072       __IOM uint32_t OFFSETCNT  : 3;            /*!< [6..4] Number of offset bytes to use for the command - 0, 1,
17073                                                      2, 3, 4, 5 are valid selections. The second (byte 1),third
17074                                                      (byte 2), and forth (byte 3) are read from the OFFSETHI
17075                                                      register, and the low order byte is pulled from this register
17076                                                      in the OFFSETLO field.Offset bytes are transmitted highest
17077                                                      byte first. EG if offsetcnt == 4, OFFSETHI[23:16] will
17078                                                      be transmitted first, then OFFSETHI[15:8], then OFFSETHI[7:0]
17079                                                      then OFFSETLO.If offsetcnt == 5, OFFSETHI[31:24] will be
17080                                                      transmitted, then OFFSETHI[23:0], then O                                  */
17081       __IOM uint32_t CONT       : 1;            /*!< [7..7] Contine to hold the bus after the current transaction
17082                                                      if set to a 1 with a new command issued.                                  */
17083       __IOM uint32_t TSIZE      : 12;           /*!< [19..8] Defines the transaction size in bytes. The offset transfer
17084                                                      is not included in this size.                                             */
17085       __IOM uint32_t CMDSEL     : 2;            /*!< [21..20] Command Specific selection information. Not used in
17086                                                      Master I2C. Used as CEn select for Master SPI transactions                */
17087             uint32_t            : 2;
17088       __IOM uint32_t OFFSETLO   : 8;            /*!< [31..24] This register holds the low order byte of offset to
17089                                                      be used in the transaction. The number of offset bytes
17090                                                      to use is set with bits 1:0 of the command.                               */
17091     } CMD_b;
17092   } ;
17093 
17094   union {
17095     __IOM uint32_t DCXCTRL;                     /*!< (@ 0x00000124) Enables transmission of DCX signal with SPI transactions
17096                                                                     and selects which CE signals will be used
17097                                                                     to transmit the DCX signal.                                */
17098 
17099     struct {
17100       __IOM uint32_t DCXSEL     : 4;            /*!< [3..0] Selects the CE channel used to convey the DCX function.
17101                                                      The select is bitwise encoded, with bit 0 = 1 enabling
17102                                                      CE0 for DCX transmission, bit 1 = 1 enableing CE1 for DCX
17103                                                      transmission, etc. If the CE used for the SPI transaction
17104                                                      is set, it will be ignored and used as the transaction
17105                                                      CE instead. Multiple CE channels can be selected at once.
17106                                                      To enable the DCX signal to be transmitted out of the chip,
17107                                                      the corresponding pin mux function must be enabled in the
17108                                                      GPIO logic as well.                                                       */
17109       __IOM uint32_t DCXEN      : 1;            /*!< [4..4] Global enable of the DCX function. Setting to 1 will
17110                                                      enable the generation of the DCX signal, which will assert
17111                                                      when sending the offset bytes of the SPI transaction.                     */
17112             uint32_t            : 27;
17113     } DCXCTRL_b;
17114   } ;
17115 
17116   union {
17117     __IOM uint32_t OFFSETHI;                    /*!< (@ 0x00000128) High order bytes of offset for IO transaction              */
17118 
17119     struct {
17120       __IOM uint32_t OFFSETHI   : 32;           /*!< [31..0] Holds the high order bytes of the byte addressing/offset
17121                                                      field to use with IO commands. The number of offset bytes
17122                                                      to use is specified in the command register                               */
17123     } OFFSETHI_b;
17124   } ;
17125 
17126   union {
17127     __IOM uint32_t CMDSTAT;                     /*!< (@ 0x0000012C) Provides staus on the execution of the command
17128                                                                     currently in progress. The fields in this
17129                                                                     register will reflect the real time status
17130                                                                     of the internal state machines and data
17131                                                                     transfers within the IOM.These are read
17132                                                                     only fields and writes to the registers
17133                                                                     are ignored.                                               */
17134 
17135     struct {
17136       __IOM uint32_t CCMD       : 5;            /*!< [4..0] current command that is being executed                             */
17137       __IOM uint32_t CMDSTAT    : 3;            /*!< [7..5] The current status of the command execution.                       */
17138       __IOM uint32_t CTSIZE     : 12;           /*!< [19..8] The current number of bytes still to be transferred
17139                                                      with this command. This field will count down to zero.                    */
17140             uint32_t            : 12;
17141     } CMDSTAT_b;
17142   } ;
17143   __IM  uint32_t  RESERVED1[52];
17144 
17145   union {
17146     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
17147                                                                     to generate the corresponding interrupt.                   */
17148 
17149     struct {
17150       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
17151                                                      operation has completed. For repeated commands, this will
17152                                                      only be asserted when the final repeated command is completed.            */
17153       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
17154                                                      when the number of free bytes in the write FIFO equals
17155                                                      or exceeds the WTHR field.For read operations, asserted
17156                                                      when the number of valid bytes in the read FIFO equals
17157                                                      of exceeds the value set in the RTHR field.                               */
17158       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
17159                                                      tries to pop from an empty fifo.                                          */
17160       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
17161                                                      tries to write to a full fifo. The current operation does
17162                                                      not stop.                                                                 */
17163       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
17164                                                      been received on the I2C bus.                                             */
17165       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
17166                                                      a overflow or underflow event                                             */
17167       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
17168                                                      written when an active command is in progress.                            */
17169       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
17170                                                      on the bus has signaled a START command.                                  */
17171       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
17172                                                      on the bus has signaled a STOP command.                                   */
17173       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
17174                                                      is enabled and has been lost to another master on the bus.                */
17175       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
17176                                                      and the DMA submodule is returned into the idle state                     */
17177       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
17178                                                      DMA command. The DMA error could occur when the memory
17179                                                      access specified in the DMA operation is not available
17180                                                      or incorrectly specified.                                                 */
17181       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
17182                                                      in the PAUSEEN register. The interrupt is posted when the
17183                                                      event is enabled within the PAUSEEN register, the mask
17184                                                      is active in the CQIRQMASK field and the event occurs.                    */
17185       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
17186                                                      the register address bit 0 set to 1. The low address bits
17187                                                      in the CQ address fields are unused and bit 0 can be used
17188                                                      to trigger an interrupt to indicate when this register
17189                                                      write is performed by the CQ operation.                                   */
17190       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
17191             uint32_t            : 17;
17192     } INTEN_b;
17193   } ;
17194 
17195   union {
17196     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
17197                                                                     cause of a recent interrupt.                               */
17198 
17199     struct {
17200       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
17201                                                      operation has completed. For repeated commands, this will
17202                                                      only be asserted when the final repeated command is completed.            */
17203       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
17204                                                      when the number of free bytes in the write FIFO equals
17205                                                      or exceeds the WTHR field.For read operations, asserted
17206                                                      when the number of valid bytes in the read FIFO equals
17207                                                      of exceeds the value set in the RTHR field.                               */
17208       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
17209                                                      tries to pop from an empty fifo.                                          */
17210       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
17211                                                      tries to write to a full fifo. The current operation does
17212                                                      not stop.                                                                 */
17213       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
17214                                                      been received on the I2C bus.                                             */
17215       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
17216                                                      a overflow or underflow event                                             */
17217       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
17218                                                      written when an active command is in progress.                            */
17219       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
17220                                                      on the bus has signaled a START command.                                  */
17221       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
17222                                                      on the bus has signaled a STOP command.                                   */
17223       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
17224                                                      is enabled and has been lost to another master on the bus.                */
17225       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
17226                                                      and the DMA submodule is returned into the idle state                     */
17227       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
17228                                                      DMA command. The DMA error could occur when the memory
17229                                                      access specified in the DMA operation is not available
17230                                                      or incorrectly specified.                                                 */
17231       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
17232                                                      in the PAUSEEN register. The interrupt is posted when the
17233                                                      event is enabled within the PAUSEEN register, the mask
17234                                                      is active in the CQIRQMASK field and the event occurs.                    */
17235       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
17236                                                      the register address bit 0 set to 1. The low address bits
17237                                                      in the CQ address fields are unused and bit 0 can be used
17238                                                      to trigger an interrupt to indicate when this register
17239                                                      write is performed by the CQ operation.                                   */
17240       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
17241             uint32_t            : 17;
17242     } INTSTAT_b;
17243   } ;
17244 
17245   union {
17246     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
17247                                                                     the interrupt status associated with that
17248                                                                     bit.                                                       */
17249 
17250     struct {
17251       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
17252                                                      operation has completed. For repeated commands, this will
17253                                                      only be asserted when the final repeated command is completed.            */
17254       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
17255                                                      when the number of free bytes in the write FIFO equals
17256                                                      or exceeds the WTHR field.For read operations, asserted
17257                                                      when the number of valid bytes in the read FIFO equals
17258                                                      of exceeds the value set in the RTHR field.                               */
17259       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
17260                                                      tries to pop from an empty fifo.                                          */
17261       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
17262                                                      tries to write to a full fifo. The current operation does
17263                                                      not stop.                                                                 */
17264       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
17265                                                      been received on the I2C bus.                                             */
17266       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
17267                                                      a overflow or underflow event                                             */
17268       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
17269                                                      written when an active command is in progress.                            */
17270       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
17271                                                      on the bus has signaled a START command.                                  */
17272       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
17273                                                      on the bus has signaled a STOP command.                                   */
17274       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
17275                                                      is enabled and has been lost to another master on the bus.                */
17276       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
17277                                                      and the DMA submodule is returned into the idle state                     */
17278       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
17279                                                      DMA command. The DMA error could occur when the memory
17280                                                      access specified in the DMA operation is not available
17281                                                      or incorrectly specified.                                                 */
17282       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
17283                                                      in the PAUSEEN register. The interrupt is posted when the
17284                                                      event is enabled within the PAUSEEN register, the mask
17285                                                      is active in the CQIRQMASK field and the event occurs.                    */
17286       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
17287                                                      the register address bit 0 set to 1. The low address bits
17288                                                      in the CQ address fields are unused and bit 0 can be used
17289                                                      to trigger an interrupt to indicate when this register
17290                                                      write is performed by the CQ operation.                                   */
17291       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
17292             uint32_t            : 17;
17293     } INTCLR_b;
17294   } ;
17295 
17296   union {
17297     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
17298                                                                     generate an interrupt from this module.
17299                                                                     (Generally used for testing purposes).                     */
17300 
17301     struct {
17302       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
17303                                                      operation has completed. For repeated commands, this will
17304                                                      only be asserted when the final repeated command is completed.            */
17305       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
17306                                                      when the number of free bytes in the write FIFO equals
17307                                                      or exceeds the WTHR field.For read operations, asserted
17308                                                      when the number of valid bytes in the read FIFO equals
17309                                                      of exceeds the value set in the RTHR field.                               */
17310       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
17311                                                      tries to pop from an empty fifo.                                          */
17312       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
17313                                                      tries to write to a full fifo. The current operation does
17314                                                      not stop.                                                                 */
17315       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
17316                                                      been received on the I2C bus.                                             */
17317       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
17318                                                      a overflow or underflow event                                             */
17319       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
17320                                                      written when an active command is in progress.                            */
17321       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
17322                                                      on the bus has signaled a START command.                                  */
17323       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
17324                                                      on the bus has signaled a STOP command.                                   */
17325       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
17326                                                      is enabled and has been lost to another master on the bus.                */
17327       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
17328                                                      and the DMA submodule is returned into the idle state                     */
17329       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
17330                                                      DMA command. The DMA error could occur when the memory
17331                                                      access specified in the DMA operation is not available
17332                                                      or incorrectly specified.                                                 */
17333       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
17334                                                      in the PAUSEEN register. The interrupt is posted when the
17335                                                      event is enabled within the PAUSEEN register, the mask
17336                                                      is active in the CQIRQMASK field and the event occurs.                    */
17337       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
17338                                                      the register address bit 0 set to 1. The low address bits
17339                                                      in the CQ address fields are unused and bit 0 can be used
17340                                                      to trigger an interrupt to indicate when this register
17341                                                      write is performed by the CQ operation.                                   */
17342       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
17343             uint32_t            : 17;
17344     } INTSET_b;
17345   } ;
17346 
17347   union {
17348     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000210) Provides control on which event will trigger
17349                                                                     the DMA transfer after the DMA operation
17350                                                                     is setup and enabled. The trigger event
17351                                                                     will cause a number of bytes (depending
17352                                                                     on trigger event) to betransferred via the
17353                                                                     DMA operation, and can be used to adjust
17354                                                                     the latency of data to/from the IOM module
17355                                                                     to/from the dma target. DMA transfers are
17356                                                                     broken into smaller transfers internally
17357                                                                     of up to16 bytes each, and multiple trigger
17358                                                                     events can be used to complete the entire
17359                                                                     programmed DMA transfer.                                   */
17360 
17361     struct {
17362       __IOM uint32_t DCMDCMPEN  : 1;            /*!< [0..0] Trigger DMA upon command complete. Enables the trigger
17363                                                      of the DMA when a command is completed. When this event
17364                                                      is triggered, the number of words transferred will be the
17365                                                      lesser of the remaining TOTCOUNT bytes, or                                */
17366       __IOM uint32_t DTHREN     : 1;            /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations
17367                                                      (IOM writes), the trigger will assert when the write FIFO
17368                                                      has (WTHR/4) number of words free in the write FIFO, and
17369                                                      will transfer (WTHR/4) number of wordsor, if the number
17370                                                      of words left to transfer is less than the WTHR value,
17371                                                      will transfer the remaining byte count.For P2M DMA operations,
17372                                                      the trigger will assert when the read FIFO has (RTHR/4)
17373                                                      words available in the read FIFO, and will transfer (RTHR/4)
17374                                                      words to SRAM. This trigger will NOT asser                                */
17375             uint32_t            : 30;
17376     } DMATRIGEN_b;
17377   } ;
17378 
17379   union {
17380     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000214) Provides the status of trigger events that have
17381                                                                     occurred for the transaction. Some of the
17382                                                                     bits are read only and some can be reset
17383                                                                     via a write of 0.                                          */
17384 
17385     struct {
17386       __IOM uint32_t DCMDCMP    : 1;            /*!< [0..0] Triggered DMA from Command complete event. Bit is read
17387                                                      only and can be cleared by disabling the DCMDCMP trigger
17388                                                      enable or by disabling DMA.                                               */
17389       __IOM uint32_t DTHR       : 1;            /*!< [1..1] Triggered DMA from THR event. Bit is read only and can
17390                                                      be cleared by disabling the DTHR trigger enable or by disabling
17391                                                      DMA.                                                                      */
17392       __IOM uint32_t DTOTCMP    : 1;            /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data
17393                                                      in the FIFO was enough to complete the DMA operation (greater
17394                                                      than or equal to current TOTCOUNT) when the command completed.
17395                                                      This trigger is default active when the DCMDCMP trigger
17396                                                      isdisabled and there is enough data in the FIFO to complete
17397                                                      the DMA operation.                                                        */
17398             uint32_t            : 29;
17399     } DMATRIGSTAT_b;
17400   } ;
17401 
17402   union {
17403     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000218) Configuration control of the DMA process, including
17404                                                                     the direction of DMA, and enablement of
17405                                                                     DMA                                                        */
17406 
17407     struct {
17408       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA
17409                                                      operation. This should be the last DMA related register
17410                                                      set prior to issuing the command                                          */
17411       __IOM uint32_t DMADIR     : 1;            /*!< [1..1] Direction                                                          */
17412             uint32_t            : 6;
17413       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
17414       __IOM uint32_t DPWROFF    : 1;            /*!< [9..9] Power off module after DMA is complete. If this bit is
17415                                                      active, the module will request to power off the supply
17416                                                      it is attached to. If there are other units still requiring
17417                                                      power from the same domain, power down will not be performed.             */
17418             uint32_t            : 22;
17419     } DMACFG_b;
17420   } ;
17421 
17422   union {
17423     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x0000021C) Contains the number of bytes to be transferred
17424                                                                     for this DMA transaction. This register
17425                                                                     is decremented as the data is transferred,
17426                                                                     and will be 0 at the completion of the DMA
17427                                                                     operation.                                                 */
17428 
17429     struct {
17430       __IOM uint32_t TOTCOUNT   : 12;           /*!< [11..0] Triggered DMA from Command complete event occured. Bit
17431                                                      is read only and can be cleared by disabling the DTHR trigger
17432                                                      enable or by disabling DMA.                                               */
17433             uint32_t            : 20;
17434     } DMATOTCOUNT_b;
17435   } ;
17436 
17437   union {
17438     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000220) The source or destination address internal the
17439                                                                     SRAM for the DMA data. For write operations,
17440                                                                     this can only be SRAM data (ADDR bit 28
17441                                                                     = 1); For read operations, this can ve either
17442                                                                     SRAM or FLASH (ADDR bit 28 = 0)                            */
17443 
17444     struct {
17445       __IOM uint32_t TARGADDR   : 29;           /*!< [28..0] Bits [28:0] of the target byte address for source of
17446                                                      DMA (either read or write). The address can be any byte
17447                                                      alignment, and does not have to be word aligned. In cases
17448                                                      of non-word aligned addresses, the DMA logic will take
17449                                                      care for ensuring only the target bytes are read/written.                 */
17450             uint32_t            : 3;
17451     } DMATARGADDR_b;
17452   } ;
17453 
17454   union {
17455     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000224) Status of the DMA operation currently in progress.         */
17456 
17457     struct {
17458       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
17459                                                      a DMA transfer is active. The DMA transfer may be waiting
17460                                                      on data, transferring data, or waiting for priority.All
17461                                                      of these will be indicated with a 1. A 0 will indicate
17462                                                      that the DMA is fully complete and no further transactions
17463                                                      will be done. This bit is read only.                                      */
17464       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
17465                                                      operation. This bit can be cleared by writing to 0, and
17466                                                      will also be cleared when a new DMA is started.                           */
17467       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals an error was
17468                                                      encountered during the DMA operation. The bit can be cleared
17469                                                      by writing to 0. Once set, this bit will remain set until
17470                                                      cleared by software.                                                      */
17471             uint32_t            : 29;
17472     } DMASTAT_b;
17473   } ;
17474 
17475   union {
17476     __IOM uint32_t CQCFG;                       /*!< (@ 0x00000228) Controls parameters and options for execution
17477                                                                     of the command queue operation. To enable
17478                                                                     command queue, create this in memory, set
17479                                                                     the address, and enable it with a write
17480                                                                     to CQEN                                                    */
17481 
17482     struct {
17483       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
17484                                                      of the command queue and fetches of address/data pairs
17485                                                      will proceed from the word address within the CQADDR register.
17486                                                      Can be disabledusing a CQ executed write to this bit as
17487                                                      well.                                                                     */
17488       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue dma request                 */
17489       __IOM uint32_t MSPIFLGSEL : 2;            /*!< [3..2] Selects the MPSI modules used for sourcing the CQFLAG
17490                                                      [11:8].                                                                   */
17491             uint32_t            : 28;
17492     } CQCFG_b;
17493   } ;
17494 
17495   union {
17496     __IOM uint32_t CQADDR;                      /*!< (@ 0x0000022C) The SRAM address which will be fetched next execution
17497                                                                     of the CQ operation. This register is updated
17498                                                                     as the CQ operation progresses, and is the
17499                                                                     live version of the register. The register
17500                                                                     can also bewritten by the Command Queue
17501                                                                     operation itself, allowing the relocation
17502                                                                     of successive CQ fetches. In this case,
17503                                                                     the new CQ address will be used for the
17504                                                                     next CQ address/data fetch                                 */
17505 
17506     struct {
17507             uint32_t            : 2;
17508       __IOM uint32_t CQADDR     : 27;           /*!< [28..2] Bits 28:2 of target byte address for source of CQ .
17509                                                      The buffer must be aligned on a word boundary                             */
17510             uint32_t            : 3;
17511     } CQADDR_b;
17512   } ;
17513 
17514   union {
17515     __IOM uint32_t CQSTAT;                      /*!< (@ 0x00000230) Provides the status of the command queue operation.
17516                                                                     If the command queue is disabled, these
17517                                                                     bits will be cleared. The bits are read
17518                                                                     only                                                       */
17519 
17520     struct {
17521       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
17522                                                      indicate that a CQ transfer is active and this will remain
17523                                                      active even when paused waiting for external event.                       */
17524       __IOM uint32_t CQPAUSED   : 1;            /*!< [1..1] Command queue operation is currently paused.                       */
17525       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
17526                                                      signals that an error was encountered during the CQ operation.            */
17527             uint32_t            : 29;
17528     } CQSTAT_b;
17529   } ;
17530 
17531   union {
17532     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x00000234) Command Queue Flag                                         */
17533 
17534     struct {
17535       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
17536                                                      controllable and bits [15:8] are hardware status.                         */
17537       __IOM uint32_t CQIRQMASK  : 16;           /*!< [31..16] Mask the bits used to generate the command queue interrupt.
17538                                                      A '1' in the bit position will enable the pause event to
17539                                                      trigger the interrupt, if the CQWT_int interrupt is enabled.
17540                                                      Bits definitions are the same as CQPAUSE                                  */
17541     } CQFLAGS_b;
17542   } ;
17543 
17544   union {
17545     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x00000238) Set/Clear the command queue software pause flags
17546                                                                     on a per-bit basis. Contains 3 fields, allowing
17547                                                                     for setting, clearing or toggling the value
17548                                                                     in the software flags. Priority when the
17549                                                                     same bitis enabled in each field is toggle,
17550                                                                     then set, then clear.                                      */
17551 
17552     struct {
17553       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any
17554                                                      SWFLAG with a '1' in the corresponding bit position of
17555                                                      this field                                                                */
17556       __IOM uint32_t CQFTGL     : 8;            /*!< [15..8] Toggle the indicated bit. Will toggle the value of any
17557                                                      SWFLAG with a '1' in the corresponding bit position of
17558                                                      this field                                                                */
17559       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG
17560                                                      with a '1' in the corresponding bit position of this field                */
17561             uint32_t            : 8;
17562     } CQSETCLEAR_b;
17563   } ;
17564 
17565   union {
17566     __IOM uint32_t CQPAUSEEN;                   /*!< (@ 0x0000023C) Enables a flag to pause an active command queue
17567                                                                     operation. If a bit is '1' and the corresponding
17568                                                                     bit in the CQFLAG register is '1', CQ processing
17569                                                                     will halt until either value is changed
17570                                                                     to '0'.                                                    */
17571 
17572     struct {
17573       __IOM uint32_t CQPEN      : 16;           /*!< [15..0] Enables the specified event to pause command processing
17574                                                      when active                                                               */
17575             uint32_t            : 16;
17576     } CQPAUSEEN_b;
17577   } ;
17578 
17579   union {
17580     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x00000240) Current index value, targeted to be written by
17581                                                                     register write operations within the command
17582                                                                     queue. This is compared to the CQENDIDX
17583                                                                     and will stop the CQ operation if bit 15
17584                                                                     of the CQPAUSEEN is '1' andthis current
17585                                                                     index equals the CQENDIDX register value.
17586                                                                     This will only pause when the values are
17587                                                                     equal.                                                     */
17588 
17589     struct {
17590       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX
17591                                                      register field. If the values match, the IDXEQ pause event
17592                                                      will be activated, which will cause the pausing of command
17593                                                      quue operation if the IDXEQ bit is enabled in CQPAUSEEN.                  */
17594             uint32_t            : 24;
17595     } CQCURIDX_b;
17596   } ;
17597 
17598   union {
17599     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x00000244) End index value, targeted to be written by software
17600                                                                     to indicate the last valid register pair
17601                                                                     contained within the command queue. rgister
17602                                                                     write operations within the command queue.This
17603                                                                     is compared to the CQCURIDX and will stop
17604                                                                     the CQ operation if bit 15 of the CQPAUSEEN
17605                                                                     is '1' andthis current index equals the
17606                                                                     CQCURIDX register value. This will only
17607                                                                     pause when the values are equal.                           */
17608 
17609     struct {
17610       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX
17611                                                      register field. If the values match, the IDXEQ pause event
17612                                                      will be activated, which will cause the pausing of command
17613                                                      quue operation if the IDXEQ bit is enabled in CQPAUSEEN.                  */
17614             uint32_t            : 24;
17615     } CQENDIDX_b;
17616   } ;
17617 
17618   union {
17619     __IOM uint32_t STATUS;                      /*!< (@ 0x00000248) IOM Module Status                                          */
17620 
17621     struct {
17622       __IOM uint32_t ERR        : 1;            /*!< [0..0] Bit has been deprecated. Please refer to the other error
17623                                                      indicators. This will always return 0.                                    */
17624       __IOM uint32_t CMDACT     : 1;            /*!< [1..1] Indicates if the active I/O Command is currently processing
17625                                                      a transaction, or command is complete, but the FIFO pointers
17626                                                      are still syncronizing internally. This bit will go high
17627                                                      atthe start of the transaction, and will go low when the
17628                                                      command is complete, and the data and pointers within the
17629                                                      FIFO have been syncronized.                                               */
17630       __IOM uint32_t IDLEST     : 1;            /*!< [2..2] indicates if the active I/O state machine is IDLE. Note
17631                                                      - The state machine could be in idle state due to holdoffs
17632                                                      from data availability, or as the command gets propagated
17633                                                      into the logic from the registers.                                        */
17634             uint32_t            : 29;
17635     } STATUS_b;
17636   } ;
17637   __IM  uint32_t  RESERVED2[13];
17638 
17639   union {
17640     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000280) Controls the configuration of the SPI master
17641                                                                     module, including POL/PHA, LSB, flow control,
17642                                                                     and delays for MISO and MOSI                               */
17643 
17644     struct {
17645       __IOM uint32_t SPOL       : 1;            /*!< [0..0] Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility
17646                                                      of creating a clock glitch which could cause register corruption,
17647                                                      changing SPHA and SPOL bits should be done in separate
17648                                                      writes to this register.                                                  */
17649       __IOM uint32_t SPHA       : 1;            /*!< [1..1] Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility
17650                                                      of creating a clock glitch which could cause register corruption,
17651                                                      changing SPHA and SPOL bits should be done in separate
17652                                                      writes to this register.                                                  */
17653       __IOM uint32_t FULLDUP    : 1;            /*!< [2..2] Enables full duplex mode for Master SPI write operations.
17654                                                      Data will be captured simultaneously into the read fifo                   */
17655             uint32_t            : 13;
17656       __IOM uint32_t WTFC       : 1;            /*!< [16..16] enables write mode flow control.                                 */
17657       __IOM uint32_t RDFC       : 1;            /*!< [17..17] Enables read mode flow control.                                  */
17658       __IOM uint32_t MOSIINV    : 1;            /*!< [18..18] Inverts MOSI when flow control is enabled.                       */
17659             uint32_t            : 1;
17660       __IOM uint32_t WTFCIRQ    : 1;            /*!< [20..20] Selects the write mode flow control signal.                      */
17661       __IOM uint32_t WTFCPOL    : 1;            /*!< [21..21] selects the write flow control signal polarity. The
17662                                                      transfers are halted when the selected flow control signal
17663                                                      is OPPOSITE polarity of bit. (For example: WTFCPOL = 0
17664                                                      will allow a IRQ=1 to pause transfers).                                   */
17665       __IOM uint32_t RDFCPOL    : 1;            /*!< [22..22] Selects the read flow control signal polarity.                   */
17666       __IOM uint32_t SPILSB     : 1;            /*!< [23..23] Selects data transfer as MSB first (0) or LSB first
17667                                                      (1) for the data portion of the SPI transaction. The offset
17668                                                      bytes are always transmitted MSB first.                                   */
17669       __IOM uint32_t DINDLY     : 3;            /*!< [26..24] Delay tap to use for the input signal (MISO). This
17670                                                      gives more hold time on the input data.                                   */
17671       __IOM uint32_t DOUTDLY    : 3;            /*!< [29..27] Delay tap to use for the output signal (MOSI). This
17672                                                      give more hold time on the output data                                    */
17673       __IOM uint32_t MSPIRST    : 1;            /*!< [30..30] Not used. To reset the module, toggle the SMOD_EN for
17674                                                      the module                                                                */
17675             uint32_t            : 1;
17676     } MSPICFG_b;
17677   } ;
17678   __IM  uint32_t  RESERVED3[15];
17679 
17680   union {
17681     __IOM uint32_t MI2CCFG;                     /*!< (@ 0x000002C0) Controls the configuration of the I2C bus master.          */
17682 
17683     struct {
17684       __IOM uint32_t ADDRSZ     : 1;            /*!< [0..0] Sets the I2C master device address size to either 7b
17685                                                      (0) or 10b (1).                                                           */
17686       __IOM uint32_t I2CLSB     : 1;            /*!< [1..1] Direction of data transmit and receive, MSB(0) or LSB(1)
17687                                                      first. Default per I2C specification is MSB first. This
17688                                                      applies to both read and write data, and read data will
17689                                                      be bit                                                                    */
17690       __IOM uint32_t ARBEN      : 1;            /*!< [2..2] Enables multi-master arbitration for the I2C master.
17691                                                      If the bus is known to have only a single master, this
17692                                                      function can be disabled to save clock cycles on I2C transactions         */
17693             uint32_t            : 1;
17694       __IOM uint32_t SDADLY     : 2;            /*!< [5..4] Delay to enable on the SDA output. Values are 0x0-0x3.             */
17695       __IOM uint32_t MI2CRST    : 1;            /*!< [6..6] Not used. To reset the module, toggle the SMOD_EN for
17696                                                      the module                                                                */
17697             uint32_t            : 1;
17698       __IOM uint32_t SCLENDLY   : 4;            /*!< [11..8] Number of IOCLK cycles to delay the rising edge of the
17699                                                      SCL output en (clock will go low on this edge). Used to
17700                                                      allow clock shaping.                                                      */
17701       __IOM uint32_t SDAENDLY   : 4;            /*!< [15..12] Number of IOCLK cycles to delay the SDA output en (all
17702                                                      transitions affected). Used to delay data relative to clock               */
17703       __IOM uint32_t SMPCNT     : 8;            /*!< [23..16] Number of Base clk cycles to wait before sampling the
17704                                                      SCL clock to determine if a clock stretch event has occured               */
17705       __IOM uint32_t STRDIS     : 1;            /*!< [24..24] Disable detection of clock stretch events smaller than
17706                                                      1 cycle                                                                   */
17707             uint32_t            : 7;
17708     } MI2CCFG_b;
17709   } ;
17710 
17711   union {
17712     __IOM uint32_t DEVCFG;                      /*!< (@ 0x000002C4) Contains the I2C device address.                           */
17713 
17714     struct {
17715       __IOM uint32_t DEVADDR    : 10;           /*!< [9..0] I2C address of the device that the Master will use to
17716                                                      target for read/write operations. This can be either a
17717                                                      7b or 10b address.                                                        */
17718             uint32_t            : 22;
17719     } DEVCFG_b;
17720   } ;
17721   __IM  uint32_t  RESERVED4[48];
17722 
17723   union {
17724     __IOM uint32_t IOMDBG;                      /*!< (@ 0x00000388) Debug control                                              */
17725 
17726     struct {
17727       __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting bit will enable the update of data
17728                                                      within this register, otherwise it is clock gated for power
17729                                                      savings                                                                   */
17730       __IOM uint32_t IOCLKON    : 1;            /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active
17731                                                      when this bit is '1'. Otherwise, the clock is controlled
17732                                                      with gating from the logic as needed.                                     */
17733       __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
17734                                                      when this bit is '1'. Otherwise, the clock is controlled
17735                                                      with gating from the logic as needed.                                     */
17736       __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used
17737                                                      to select between different debug data available in the
17738                                                      DBG0 and DBG1 registers.                                                  */
17739     } IOMDBG_b;
17740   } ;
17741 } IOM0_Type;                                    /*!< Size = 908 (0x38c)                                                        */
17742 
17743 
17744 
17745 /* =========================================================================================================================== */
17746 /* ================                                          IOSLAVE                                          ================ */
17747 /* =========================================================================================================================== */
17748 
17749 
17750 /**
17751   * @brief I2C/SPI Slave (IOSLAVE)
17752   */
17753 
17754 typedef struct {                                /*!< (@ 0x40034000) IOSLAVE Structure                                          */
17755   __IM  uint32_t  RESERVED[64];
17756 
17757   union {
17758     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Current FIFO Pointer                                       */
17759 
17760     struct {
17761       __IOM uint32_t FIFOPTR    : 8;            /*!< [7..0] Current FIFO pointer.                                              */
17762       __IOM uint32_t FIFOSIZ    : 8;            /*!< [15..8] The number of bytes currently in the hardware FIFO.               */
17763             uint32_t            : 16;
17764     } FIFOPTR_b;
17765   } ;
17766 
17767   union {
17768     __IOM uint32_t FIFOCFG;                     /*!< (@ 0x00000104) FIFO Configuration                                         */
17769 
17770     struct {
17771       __IOM uint32_t FIFOBASE   : 5;            /*!< [4..0] These bits hold the base address of the I/O FIFO in 8
17772                                                      byte segments. The IO Slave FIFO is situated in LRAM at
17773                                                      (FIFOBASE*8) to (FIFOMAX*8-1).                                            */
17774             uint32_t            : 3;
17775       __IOM uint32_t FIFOMAX    : 6;            /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments.
17776                                                      It is also the beginning of the RAM area of the LRAM. Note
17777                                                      that no RAM area is configured if FIFOMAX is set to 0x1F.                 */
17778             uint32_t            : 10;
17779       __IOM uint32_t ROBASE     : 6;            /*!< [29..24] Defines the read-only area. The IO Slave read-only
17780                                                      area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1)                  */
17781             uint32_t            : 2;
17782     } FIFOCFG_b;
17783   } ;
17784 
17785   union {
17786     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000108) FIFO Threshold Configuration                               */
17787 
17788     struct {
17789       __IOM uint32_t FIFOTHR    : 8;            /*!< [7..0] FIFO size interrupt threshold.                                     */
17790             uint32_t            : 24;
17791     } FIFOTHR_b;
17792   } ;
17793 
17794   union {
17795     __IOM uint32_t FUPD;                        /*!< (@ 0x0000010C) FIFO Update Status                                         */
17796 
17797     struct {
17798       __IOM uint32_t FIFOUPD    : 1;            /*!< [0..0] This bit indicates that a FIFO update is underway.                 */
17799       __IOM uint32_t IOREAD     : 1;            /*!< [1..1] This bitfield indicates an IO read is active.                      */
17800             uint32_t            : 30;
17801     } FUPD_b;
17802   } ;
17803 
17804   union {
17805     __IOM uint32_t FIFOCTR;                     /*!< (@ 0x00000110) Overall FIFO Counter                                       */
17806 
17807     struct {
17808       __IOM uint32_t FIFOCTR    : 10;           /*!< [9..0] Virtual FIFO byte count                                            */
17809             uint32_t            : 22;
17810     } FIFOCTR_b;
17811   } ;
17812 
17813   union {
17814     __IOM uint32_t FIFOINC;                     /*!< (@ 0x00000114) Overall FIFO Counter Increment                             */
17815 
17816     struct {
17817       __IOM uint32_t FIFOINC    : 10;           /*!< [9..0] Increment the Overall FIFO Counter by this value on a
17818                                                      write                                                                     */
17819             uint32_t            : 22;
17820     } FIFOINC_b;
17821   } ;
17822 
17823   union {
17824     __IOM uint32_t CFG;                         /*!< (@ 0x00000118) I/O Slave Configuration                                    */
17825 
17826     struct {
17827       __IOM uint32_t IFCSEL     : 1;            /*!< [0..0] This bit selects the I/O interface.                                */
17828       __IOM uint32_t SPOL       : 1;            /*!< [1..1] This bit selects SPI polarity.                                     */
17829       __IOM uint32_t LSB        : 1;            /*!< [2..2] This bit selects the transfer bit ordering.                        */
17830             uint32_t            : 1;
17831       __IOM uint32_t STARTRD    : 1;            /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read.              */
17832             uint32_t            : 3;
17833       __IOM uint32_t I2CADDR    : 12;           /*!< [19..8] 7-bit or 10-bit I2C device address.                               */
17834       __IOM uint32_t WRAPPTR    : 1;            /*!< [20..20] Address pointer wrap mode enable.                                */
17835             uint32_t            : 10;
17836       __IOM uint32_t IFCEN      : 1;            /*!< [31..31] IOSLAVE interface enable.                                        */
17837     } CFG_b;
17838   } ;
17839 
17840   union {
17841     __IOM uint32_t PRENC;                       /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode                        */
17842 
17843     struct {
17844       __IOM uint32_t PRENC      : 5;            /*!< [4..0] These bits hold the priority encode of the REGACC interrupts.      */
17845             uint32_t            : 27;
17846     } PRENC_b;
17847   } ;
17848 
17849   union {
17850     __IOM uint32_t IOINTCTL;                    /*!< (@ 0x00000120) I/O Interrupt Control                                      */
17851 
17852     struct {
17853       __IOM uint32_t IOINTEN    : 8;            /*!< [7..0] These read-only bits indicate whether the IOINT interrupts
17854                                                      are enabled.                                                              */
17855       __IOM uint32_t IOINT      : 8;            /*!< [15..8] These bits read the IOINT interrupts.                             */
17856       __IOM uint32_t IOINTCLR   : 1;            /*!< [16..16] This bit clears all of the IOINT interrupts when written
17857                                                      with a 1.                                                                 */
17858             uint32_t            : 7;
17859       __IOM uint32_t IOINTSET   : 8;            /*!< [31..24] These bits set the IOINT interrupts when written with
17860                                                      a 1.                                                                      */
17861     } IOINTCTL_b;
17862   } ;
17863 
17864   union {
17865     __IOM uint32_t GENADD;                      /*!< (@ 0x00000124) General Address Data                                       */
17866 
17867     struct {
17868       __IOM uint32_t GADATA     : 8;            /*!< [7..0] The data supplied on the last General Address reference.           */
17869             uint32_t            : 24;
17870     } GENADD_b;
17871   } ;
17872 
17873   union {
17874     __IOM uint32_t ADDPTR;                      /*!< (@ 0x00000128) Address pointer                                            */
17875 
17876     struct {
17877       __IOM uint32_t ADDPTR     : 8;            /*!< [7..0] The current value in the Address pointer.                          */
17878             uint32_t            : 24;
17879     } ADDPTR_b;
17880   } ;
17881   __IM  uint32_t  RESERVED1[53];
17882 
17883   union {
17884     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
17885                                                                     to generate the corresponding interrupt.                   */
17886 
17887     struct {
17888       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
17889       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
17890       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
17891       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
17892       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
17893       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
17894       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
17895       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
17896       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
17897       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
17898             uint32_t            : 22;
17899     } INTEN_b;
17900   } ;
17901 
17902   union {
17903     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
17904                                                                     cause of a recent interrupt.                               */
17905 
17906     struct {
17907       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
17908       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
17909       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
17910       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
17911       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
17912       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
17913       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
17914       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
17915       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
17916       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
17917             uint32_t            : 22;
17918     } INTSTAT_b;
17919   } ;
17920 
17921   union {
17922     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
17923                                                                     the interrupt status associated with that
17924                                                                     bit.                                                       */
17925 
17926     struct {
17927       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
17928       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
17929       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
17930       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
17931       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
17932       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
17933       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
17934       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
17935       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
17936       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
17937             uint32_t            : 22;
17938     } INTCLR_b;
17939   } ;
17940 
17941   union {
17942     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
17943                                                                     generate an interrupt from this module.
17944                                                                     (Generally used for testing purposes).                     */
17945 
17946     struct {
17947       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
17948       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
17949       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
17950       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
17951       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
17952       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
17953       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
17954       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
17955       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
17956       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
17957             uint32_t            : 22;
17958     } INTSET_b;
17959   } ;
17960 
17961   union {
17962     __IOM uint32_t REGACCINTEN;                 /*!< (@ 0x00000210) Set bits in this register to allow this module
17963                                                                     to generate the corresponding interrupt.                   */
17964 
17965     struct {
17966       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
17967     } REGACCINTEN_b;
17968   } ;
17969 
17970   union {
17971     __IOM uint32_t REGACCINTSTAT;               /*!< (@ 0x00000214) Read bits from this register to discover the
17972                                                                     cause of a recent interrupt.                               */
17973 
17974     struct {
17975       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
17976     } REGACCINTSTAT_b;
17977   } ;
17978 
17979   union {
17980     __IOM uint32_t REGACCINTCLR;                /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
17981                                                                     the interrupt status associated with that
17982                                                                     bit.                                                       */
17983 
17984     struct {
17985       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
17986     } REGACCINTCLR_b;
17987   } ;
17988 
17989   union {
17990     __IOM uint32_t REGACCINTSET;                /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
17991                                                                     generate an interrupt from this module.
17992                                                                     (Generally used for testing purposes).                     */
17993 
17994     struct {
17995       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
17996     } REGACCINTSET_b;
17997   } ;
17998 } IOSLAVE_Type;                                 /*!< Size = 544 (0x220)                                                        */
17999 
18000 
18001 
18002 /* =========================================================================================================================== */
18003 /* ================                                          MCUCTRL                                          ================ */
18004 /* =========================================================================================================================== */
18005 
18006 
18007 /**
18008   * @brief MCU Miscellaneous Control Logic (MCUCTRL)
18009   */
18010 
18011 typedef struct {                                /*!< (@ 0x40020000) MCUCTRL Structure                                          */
18012 
18013   union {
18014     __IOM uint32_t CHIPPN;                      /*!< (@ 0x00000000) Chip Information                                           */
18015 
18016     struct {
18017             uint32_t            : 1;
18018       __IOM uint32_t TEMP       : 2;            /*!< [2..1] Temperature.                                                       */
18019       __IOM uint32_t PINS       : 3;            /*!< [5..3] Number of pins for this package.                                   */
18020       __IOM uint32_t PKG        : 2;            /*!< [7..6] Package type.                                                      */
18021       __IOM uint32_t REVMIN     : 4;            /*!< [11..8] Minor revision.                                                   */
18022       __IOM uint32_t REVMAJ     : 4;            /*!< [15..12] Major revision.                                                  */
18023       __IOM uint32_t SRAMSIZE   : 4;            /*!< [19..16] SRAM size.                                                       */
18024       __IOM uint32_t MRAMSIZE   : 4;            /*!< [23..20] MRAM size.                                                       */
18025       __IOM uint32_t PN         : 8;            /*!< [31..24] Apollo family device type.                                       */
18026     } CHIPPN_b;
18027   } ;
18028 
18029   union {
18030     __IOM uint32_t CHIPID0;                     /*!< (@ 0x00000004) Unique Chip ID 0                                           */
18031 
18032     struct {
18033       __IOM uint32_t CHIPID0    : 32;           /*!< [31..0] Unique chip ID 0.                                                 */
18034     } CHIPID0_b;
18035   } ;
18036 
18037   union {
18038     __IOM uint32_t CHIPID1;                     /*!< (@ 0x00000008) Unique Chip ID 1                                           */
18039 
18040     struct {
18041       __IOM uint32_t CHIPID1    : 32;           /*!< [31..0] Unique chip ID 1.                                                 */
18042     } CHIPID1_b;
18043   } ;
18044 
18045   union {
18046     __IOM uint32_t CHIPREV;                     /*!< (@ 0x0000000C) Chip Revision                                              */
18047 
18048     struct {
18049       __IOM uint32_t REVMIN     : 4;            /*!< [3..0] Minor Revision ID.                                                 */
18050       __IOM uint32_t REVMAJ     : 4;            /*!< [7..4] Major Revision ID.                                                 */
18051       __IOM uint32_t SIPART     : 12;           /*!< [19..8] Silicon Part ID                                                   */
18052             uint32_t            : 12;
18053     } CHIPREV_b;
18054   } ;
18055 
18056   union {
18057     __IOM uint32_t VENDORID;                    /*!< (@ 0x00000010) Unique Vendor ID                                           */
18058 
18059     struct {
18060       __IOM uint32_t VENDORID   : 32;           /*!< [31..0] Unique Vendor ID                                                  */
18061     } VENDORID_b;
18062   } ;
18063 
18064   union {
18065     __IOM uint32_t SKU;                         /*!< (@ 0x00000014) Unique Chip SKU                                            */
18066 
18067     struct {
18068       __IOM uint32_t SKUSRAMSIZE : 2;           /*!< [1..0] SRAM SKU dictates the available memory for MCU. All of
18069                                                      the MCU TCM (384KB) and System SRAM (2MB) available by
18070                                                      default. Memory SU disabled                                               */
18071       __IOM uint32_t SKUMRAMSIZE : 2;           /*!< [3..2] MRAM size SKU. All of 2MB Available by default. Memory
18072                                                      SU disabled                                                               */
18073       __IOM uint32_t SKUDSP     : 2;            /*!< [5..4] DSP availability SKU setting. 384K available by default.
18074                                                      Memory SU disabled                                                        */
18075       __IOM uint32_t SKUTURBOSPOT : 1;          /*!< [6..6] High performance mode for MCU and DSPs.                            */
18076       __IOM uint32_t SKUMIPIDSI : 1;            /*!< [7..7] MIPI DSI available                                                 */
18077       __IOM uint32_t SKUGFX     : 1;            /*!< [8..8] GFX available                                                      */
18078       __IOM uint32_t SKUUSB     : 1;            /*!< [9..9] USB available                                                      */
18079       __IOM uint32_t SKUSECURESPOT : 1;         /*!< [10..10] Secure boot feature                                              */
18080             uint32_t            : 21;
18081     } SKU_b;
18082   } ;
18083   __IM  uint32_t  RESERVED[2];
18084 
18085   union {
18086     __IOM uint32_t DEBUGGER;                    /*!< (@ 0x00000020) Debugger Control                                           */
18087 
18088     struct {
18089       __IOM uint32_t LOCKOUT    : 32;           /*!< [31..0] Lockout of debugger (SWD).                                        */
18090     } DEBUGGER_b;
18091   } ;
18092   __IM  uint32_t  RESERVED1;
18093 
18094   union {
18095     __IOM uint32_t ACRG;                        /*!< (@ 0x00000028) Active Current Reference Generator Control                 */
18096 
18097     struct {
18098       __IOM uint32_t ACRGSWE    : 1;            /*!< [0..0] Software enablement for ACRG register. A value of 1 will
18099                                                      allow writes to the register                                              */
18100       __IOM uint32_t ACRGPWD    : 1;            /*!< [1..1] Power down the ACRG.                                               */
18101       __IOM uint32_t ACRGIBIASSEL : 1;          /*!< [2..2] Set the ACRG ibias. Note: the SWE mux select in PWRSEQ2SWE
18102                                                      must be set for this to take effect. The inversion of this
18103                                                      register is driven to analog.                                             */
18104       __IOM uint32_t ACRGTRIM   : 5;            /*!< [7..3] ACRG Trim value                                                    */
18105             uint32_t            : 24;
18106     } ACRG_b;
18107   } ;
18108   __IM  uint32_t  RESERVED2[6];
18109 
18110   union {
18111     __IOM uint32_t VREFGEN2;                    /*!< (@ 0x00000044) Voltage Reference Generator 2 Control                      */
18112 
18113     struct {
18114       __IOM uint32_t TVRGTEMPCOTRIM : 5;        /*!< [4..0] Calibrated Voltage Reference Generator tc trim (bottom
18115                                                      transistor)                                                               */
18116       __IOM uint32_t TVRGPWD    : 1;            /*!< [5..5] Power Down, Calibrated Voltage Reference Generator.                */
18117       __IOM uint32_t TVRGCURRENTTRIM : 1;       /*!< [6..6] Calibrated voltage reference current trim.                         */
18118       __IOM uint32_t TVRGVREFTRIM : 7;          /*!< [13..7] Calibrated voltage reference 580m trim                            */
18119       __IOM uint32_t TVRG2TEMPCOTRIM : 5;       /*!< [18..14] Calibrated Voltage Reference Generator tc trim (bottom
18120                                                      transistor)                                                               */
18121       __IOM uint32_t TVRG2PWD   : 1;            /*!< [19..19] Power Down, Calibrated Voltage Reference Generator.              */
18122       __IOM uint32_t TVRG2CURRENTTRIM : 1;      /*!< [20..20] Calibrated voltage reference current trim.                       */
18123       __IOM uint32_t TVRG2VREFTRIM : 7;         /*!< [27..21] Calibrated voltage reference 580m trim                           */
18124       __IOM uint32_t TVRGSELVREF : 1;           /*!< [28..28] TVRG SEL VREF                                                    */
18125       __IOM uint32_t TVRG2SELVREF : 1;          /*!< [29..29] TVRG2 SEL VREF                                                   */
18126             uint32_t            : 2;
18127     } VREFGEN2_b;
18128   } ;
18129   __IM  uint32_t  RESERVED3[6];
18130 
18131   union {
18132     __IOM uint32_t VRCTRL;                      /*!< (@ 0x00000060) Overrides for Voltage Regulators Controls                  */
18133 
18134     struct {
18135       __IOM uint32_t CORELDOOVER : 1;           /*!< [0..0] Override control for CORE LDO signals                              */
18136       __IOM uint32_t CORELDOPDNB : 1;           /*!< [1..1] CORE LDO PDNB control. Override for PWRCTRL going to
18137                                                      analog when CORELDOOVER = 1                                               */
18138       __IOM uint32_t CORELDOACTIVEEARLY : 1;    /*!< [2..2] CORE LDO EARLY ACTIVE control. Override for PWRCTRL going
18139                                                      to analog when CORELDOOVER = 1                                            */
18140       __IOM uint32_t CORELDOACTIVE : 1;         /*!< [3..3] CORE LDO ACTIVE control. Override for PWRCTRL going to
18141                                                      analog when CORELDOOVER = 1                                               */
18142       __IOM uint32_t CORELDOCOLDSTARTEN : 1;    /*!< [4..4] CORE LDO COLDSTART EN control. This is a shadow backed
18143                                                      register and no need to set CORELDOOVER.                                  */
18144       __IOM uint32_t MEMLDOOVER : 1;            /*!< [5..5] Override control for MEM LDO signals                               */
18145       __IOM uint32_t MEMLDOPDNB : 1;            /*!< [6..6] MEM LDO PDNB control. Override signal for PWRCTRL going
18146                                                      to analog when MEMLDOOVER = 1                                             */
18147       __IOM uint32_t MEMLDOACTIVEEARLY : 1;     /*!< [7..7] MEM LDO EARLY ACTIVE control. Override for PWRCTRL going
18148                                                      to analog when MEMLDOOVER = 1                                             */
18149       __IOM uint32_t MEMLDOACTIVE : 1;          /*!< [8..8] MEM LDO ACTIVE control. Override for PWRCTRL going to
18150                                                      analog when MEMLDOOVER = 1                                                */
18151       __IOM uint32_t MEMLDOCOLDSTARTEN : 1;     /*!< [9..9] MEM LDO COLDSTART EN control. This is a shadow backed
18152                                                      register and no need to set MEMLDOOVER.                                   */
18153       __IOM uint32_t MEMLPLDOOVER : 1;          /*!< [10..10] Override control for MEM LP LDO signals                          */
18154       __IOM uint32_t MEMLPLDOPDNB : 1;          /*!< [11..11] MEM LP LDO PDNB control. Override for PWRCTRL going
18155                                                      to analog when MEMLPLDOOVER = 1                                           */
18156       __IOM uint32_t MEMLPLDOACTIVE : 1;        /*!< [12..12] MEM LP LDO ACTVIVE control. Override for PWRCTRL going
18157                                                      to analog when MEMLPLDOOVER = 1                                           */
18158       __IOM uint32_t ANALDOOVER : 1;            /*!< [13..13] Override control for ANALDO signals                              */
18159       __IOM uint32_t ANALDOPDNB : 1;            /*!< [14..14] ANALDO PDNB control. Override for PWRCTRL going to
18160                                                      analog when ANALDOOVER = 1                                                */
18161       __IOM uint32_t ANALDOACTIVE : 1;          /*!< [15..15] ANALDO LDO ACTIVE control. Override for PWRCTRL going
18162                                                      to analog when ANALDOOVER = 1                                             */
18163       __IOM uint32_t SIMOBUCKOVER : 1;          /*!< [16..16] Override control for SIMO BUCK signals                           */
18164       __IOM uint32_t SIMOBUCKPDNB : 1;          /*!< [17..17] SIMO BUCK PDNB control. Override for PWRCTRL going
18165                                                      to analog when SIMOBUCKOVER = 1                                           */
18166       __IOM uint32_t SIMOBUCKRSTB : 1;          /*!< [18..18] SIMO BUCK RSTB control. Override for PWRCTRL going
18167                                                      to analog when SIMOBUCKOVER = 1                                           */
18168       __IOM uint32_t SIMOBUCKACTIVE : 1;        /*!< [19..19] SIMO BUCK ACTIVE control. Override for PWRCTRL going
18169                                                      to analog when SIMOBUCKOVER = 1                                           */
18170             uint32_t            : 12;
18171     } VRCTRL_b;
18172   } ;
18173   __IM  uint32_t  RESERVED4[7];
18174 
18175   union {
18176     __IOM uint32_t LDOREG1;                     /*!< (@ 0x00000080) CORELDO trims Reg                                          */
18177 
18178     struct {
18179       __IOM uint32_t CORELDOACTIVETRIM : 10;    /*!< [9..0] CORE LDO active trim                                               */
18180       __IOM uint32_t CORELDOTEMPCOTRIM : 4;     /*!< [13..10] CORE LDO TEMPCO trim                                             */
18181       __IOM uint32_t CORELDOLPTRIM : 6;         /*!< [19..14] CORE LDO Low Power Trim                                          */
18182       __IOM uint32_t CORELDOIBIASTRIM : 1;      /*!< [20..20] CORE LDO IBIAS Trim                                              */
18183       __IOM uint32_t CORELDOIBIASSEL : 1;       /*!< [21..21] Core LDO IBIAS sel. Note: the SWE mux select in PWRSEQ2SWE
18184                                                      must be set for this to take effect.                                      */
18185             uint32_t            : 10;
18186     } LDOREG1_b;
18187   } ;
18188   __IM  uint32_t  RESERVED5;
18189 
18190   union {
18191     __IOM uint32_t LDOREG2;                     /*!< (@ 0x00000088) MEMLDO and MEMLPLDO Trims                                  */
18192 
18193     struct {
18194       __IOM uint32_t MEMLDOACTIVETRIM : 6;      /*!< [5..0] MEM LDO active trim                                                */
18195       __IOM uint32_t MEMLDOLPTRIM : 6;          /*!< [11..6] MEM LDO LP trim                                                   */
18196       __IOM uint32_t MEMLDOLPALTTRIM : 6;       /*!< [17..12] MEM LDO TRIM LP ALT SET                                          */
18197       __IOM uint32_t MEMLPLDOTRIM : 6;          /*!< [23..18] MEM LPLDO TRIM                                                   */
18198       __IOM uint32_t MEMLPLDOIBIASTRIM : 1;     /*!< [24..24] Mem LPLDO IBIAS trim                                             */
18199       __IOM uint32_t MEMLDOIBIASSEL : 1;        /*!< [25..25] Mem LDO IBIAS sel. Note: the SWE mux select in PWRSEQ2SWE
18200                                                      must be set for this to take effect.                                      */
18201       __IOM uint32_t TRIMANALDO : 4;            /*!< [29..26] Analog LDO Trim.                                                 */
18202             uint32_t            : 2;
18203     } LDOREG2_b;
18204   } ;
18205   __IM  uint32_t  RESERVED6[21];
18206 
18207   union {
18208     __IOM uint32_t LFRC;                        /*!< (@ 0x000000E0) LFRC Control                                               */
18209 
18210     struct {
18211       __IOM uint32_t LFRCSWE    : 1;            /*!< [0..0] LFRC Software Override Enable.                                     */
18212       __IOM uint32_t TRIMTUNELFRC : 5;          /*!< [5..1] LFRC Frequency Tune trim bits                                      */
18213       __IOM uint32_t PWDLFRC    : 1;            /*!< [6..6] Power Down LFRC.                                                   */
18214       __IOM uint32_t RESETLFRC  : 1;            /*!< [7..7] LFRC Reset.                                                        */
18215       __IOM uint32_t LFRCITAILTRIM : 2;         /*!< [9..8] LFRC ITAIL trim                                                    */
18216       __IOM uint32_t LFRCSIMOCLKDIV : 3;        /*!< [12..10] SIMOBUCK LP mode clock divider                                   */
18217             uint32_t            : 19;
18218     } LFRC_b;
18219   } ;
18220   __IM  uint32_t  RESERVED7[7];
18221 
18222   union {
18223     __IOM uint32_t BODCTRL;                     /*!< (@ 0x00000100) BOD control                                                */
18224 
18225     struct {
18226       __IOM uint32_t BODLPWD    : 1;            /*!< [0..0] BODL Power Down.                                                   */
18227       __IOM uint32_t BODHPWD    : 1;            /*!< [1..1] BODH Power Down.                                                   */
18228       __IOM uint32_t BODCPWD    : 1;            /*!< [2..2] BODC Power Down.                                                   */
18229       __IOM uint32_t BODFPWD    : 1;            /*!< [3..3] BODF Power Down.                                                   */
18230       __IOM uint32_t BODSPWD    : 1;            /*!< [4..4] BODS Power Down.                                                   */
18231       __IOM uint32_t BODCLVPWD  : 1;            /*!< [5..5] BODC_LV Power Down.                                                */
18232       __IOM uint32_t BODLVREFSEL : 1;           /*!< [6..6] BODL External Reference Select. Note: the SWE mux select
18233                                                      in PWRSEQ2SWE must be set for this to take effect.                        */
18234       __IOM uint32_t BODHVREFSEL : 1;           /*!< [7..7] BODH External Reference Select. Note: the SWE mux select
18235                                                      in PWRSEQ2SWE must be set for this to take effect.                        */
18236             uint32_t            : 24;
18237     } BODCTRL_b;
18238   } ;
18239 
18240   union {
18241     __IOM uint32_t ADCPWRDLY;                   /*!< (@ 0x00000104) ADC Power Up Delay Control                                 */
18242 
18243     struct {
18244       __IOM uint32_t ADCPWR0    : 8;            /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK
18245                                                      increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments
18246                                                      for ADC_CLKSEL = 0x2.                                                     */
18247       __IOM uint32_t ADCPWR1    : 8;            /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments
18248                                                      for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL
18249                                                      = 0x2.                                                                    */
18250             uint32_t            : 16;
18251     } ADCPWRDLY_b;
18252   } ;
18253 
18254   union {
18255     __IOM uint32_t ADCPWRCTRL;                  /*!< (@ 0x00000108) ADC Power Control                                          */
18256 
18257     struct {
18258       __IOM uint32_t ADCPWRCTRLSWE : 1;         /*!< [0..0] ADC Power Control Software Override Enable                         */
18259       __IOM uint32_t ADCAPSEN   : 1;            /*!< [1..1] Enable the Global ADC Power Switch on when set to 1 if
18260                                                      the ADCPWRCTRLSWE bit is set.                                             */
18261       __IOM uint32_t ADCBPSEN   : 1;            /*!< [2..2] Enable the Analog, IO and SAR Digital logic Power Switch
18262                                                      on when set to 1 if the ADCPWRCTRLSWE bit is set.                         */
18263       __IOM uint32_t BGTPEN     : 1;            /*!< [3..3] Bandgap and Temperature Sensor Power Switch Enable                 */
18264       __IOM uint32_t BGTLPPEN   : 1;            /*!< [4..4] Bandgap and Temperature Sensor Power Switch Enable                 */
18265       __IOM uint32_t REFBUFPEN  : 1;            /*!< [5..5] Reference Buffer Power Switch Enable                               */
18266       __IOM uint32_t REFKEEPPEN : 1;            /*!< [6..6] Reference Buffer Keeper Power Switch Enable                        */
18267       __IOM uint32_t VDDADCSARISOLATE : 1;      /*!< [7..7] ISOLATE signal for Power Switched SAR ( when ADCBPSEN
18268                                                      is switched off )                                                         */
18269       __IOM uint32_t VDDADCDIGISOLATE : 1;      /*!< [8..8] ISOLATE signal for ADC Digital Contoller ( when ADCAPSEN
18270                                                      is switched off and if the ADCPWRCTRLSWE bit is set)                      */
18271       __IOM uint32_t VDDADCRESETN : 1;          /*!< [9..9] RESETN signal for Power Switched SAR and Digital Controller
18272                                                      (when global power switch is off and if the ADCPWRCTRLSWE
18273                                                      bit is set)                                                               */
18274             uint32_t            : 1;
18275       __IOM uint32_t ADCVBATDIVEN : 1;          /*!< [11..11] ADC VBAT DIV Power Enable ( if the ADCPWRCTRLSWE bit
18276                                                      is set )                                                                  */
18277       __IOM uint32_t ADCINBUFSEL : 2;           /*!< [13..12] ADC input buffer mux select                                      */
18278       __IOM uint32_t ADCINBUFEN : 1;            /*!< [14..14] ADC Input Buffer Power Enable ( if the ADCPWRCTRLSWE
18279                                                      bit is set )                                                              */
18280       __IOM uint32_t ADCRFBUFSLWEN : 1;         /*!< [15..15] ADC reference buffer slew enable                                 */
18281       __IOM uint32_t ADCKEEPOUTEN : 1;          /*!< [16..16] ADC reference keeper out en                                      */
18282             uint32_t            : 15;
18283     } ADCPWRCTRL_b;
18284   } ;
18285 
18286   union {
18287     __IOM uint32_t ADCCAL;                      /*!< (@ 0x0000010C) ADC Calibration Control                                    */
18288 
18289     struct {
18290       __IOM uint32_t CALONPWRUP : 1;            /*!< [0..0] Run ADC Calibration on initial power up sequence                   */
18291       __IOM uint32_t ADCCALIBRATED : 1;         /*!< [1..1] Status for ADC Calibration                                         */
18292             uint32_t            : 30;
18293     } ADCCAL_b;
18294   } ;
18295 
18296   union {
18297     __IOM uint32_t ADCBATTLOAD;                 /*!< (@ 0x00000110) ADC Battery Load Enable                                    */
18298 
18299     struct {
18300       __IOM uint32_t BATTLOAD   : 1;            /*!< [0..0] Enable the ADC battery load resistor                               */
18301             uint32_t            : 31;
18302     } ADCBATTLOAD_b;
18303   } ;
18304   __IM  uint32_t  RESERVED8[3];
18305 
18306   union {
18307     __IOM uint32_t XTALCTRL;                    /*!< (@ 0x00000120) XTAL Oscillator Control                                    */
18308 
18309     struct {
18310       __IOM uint32_t XTALSWE    : 1;            /*!< [0..0] XTAL Software Override Enable.                                     */
18311       __IOM uint32_t XTALCOREDISFB : 1;         /*!< [1..1] XTAL Oscillator Disable Feedback.                                  */
18312       __IOM uint32_t XTALCOMPBYPASS : 1;        /*!< [2..2] XTAL Oscillator Bypass Comparator.                                 */
18313       __IOM uint32_t XTALPDNB   : 1;            /*!< [3..3] XTAL Oscillator Power Down Core.                                   */
18314       __IOM uint32_t XTALCOMPPDNB : 1;          /*!< [4..4] XTAL Oscillator Power Down Comparator.                             */
18315       __IOM uint32_t XTALIBUFTRIM : 2;          /*!< [6..5] XTAL IBUFF trim                                                    */
18316       __IOM uint32_t XTALICOMPTRIM : 2;         /*!< [8..7] XTAL ICOMP trim                                                    */
18317             uint32_t            : 23;
18318     } XTALCTRL_b;
18319   } ;
18320 
18321   union {
18322     __IOM uint32_t XTALGENCTRL;                 /*!< (@ 0x00000124) XTAL Oscillator General Control                            */
18323 
18324     struct {
18325       __IOM uint32_t ACWARMUP   : 2;            /*!< [1..0] Auto-calibration delay control                                     */
18326       __IOM uint32_t XTALBIASTRIM : 6;          /*!< [7..2] XTAL BIAS trim                                                     */
18327       __IOM uint32_t XTALKSBIASTRIM : 6;        /*!< [13..8] XTAL IBIAS Kick start trim. This trim value is used
18328                                                      during the startup process to enable a faster lock.                       */
18329             uint32_t            : 18;
18330     } XTALGENCTRL_b;
18331   } ;
18332 
18333   union {
18334     __IOM uint32_t XTALHSTRIMS;                 /*!< (@ 0x00000128) XTALHS Trims                                               */
18335 
18336     struct {
18337       __IOM uint32_t XTALHSCAP2TRIM : 6;        /*!< [5..0] xtalhs_cap2_trim                                                   */
18338       __IOM uint32_t XTALHSCAPTRIM : 4;         /*!< [9..6] xtalhs_cap_trim                                                    */
18339       __IOM uint32_t XTALHSDRIVETRIM : 2;       /*!< [11..10] xtalhs_drive_trim                                                */
18340       __IOM uint32_t XTALHSDRIVERSTRENGTH : 3;  /*!< [14..12] xtalhs_driver_strength                                           */
18341       __IOM uint32_t XTALHSIBIASCOMP2TRIM : 2;  /*!< [16..15] xtalhs_ibias_comp2_trim                                          */
18342       __IOM uint32_t XTALHSIBIASCOMPTRIM : 4;   /*!< [20..17] xtalhs_ibias_comp_trim                                           */
18343       __IOM uint32_t XTALHSIBIASTRIM : 7;       /*!< [27..21] xtalhs_ibias_trim                                                */
18344       __IOM uint32_t XTALHSRSTRIM : 1;          /*!< [28..28] xtalhs_rs_trim                                                   */
18345       __IOM uint32_t XTALHSSPARE : 1;           /*!< [29..29] xtalhs_spare                                                     */
18346             uint32_t            : 2;
18347     } XTALHSTRIMS_b;
18348   } ;
18349 
18350   union {
18351     __IOM uint32_t XTALHSCTRL;                  /*!< (@ 0x0000012C) XTALHS Control                                             */
18352 
18353     struct {
18354       __IOM uint32_t XTALHSPDNB : 1;            /*!< [0..0] xtalhs_pdnb                                                        */
18355       __IOM uint32_t XTALHSCOMPPDNB : 1;        /*!< [1..1] xtalhs_comp_pdnb                                                   */
18356       __IOM uint32_t XTALHSCOMPSEL : 1;         /*!< [2..2] xtalhs_comp_sel                                                    */
18357       __IOM uint32_t XTALHSIBSTENABLE : 1;      /*!< [3..3] xtalhs_ibst_enable                                                 */
18358       __IOM uint32_t XTALHSINJECTIONENABLE : 1; /*!< [4..4] xtalhs_injection_enable                                            */
18359       __IOM uint32_t XTALHSPDNPNIMPROVE : 1;    /*!< [5..5] xtalhs_pdn_pn_improve                                              */
18360       __IOM uint32_t XTALHSSELRCOM : 1;         /*!< [6..6] xtalhs_sel_rcom                                                    */
18361       __IOM uint32_t XTALHSPADOUTEN : 1;        /*!< [7..7] xtalhs_padout_en                                                   */
18362       __IOM uint32_t XTALHSEXTERNALCLOCK : 1;   /*!< [8..8] xtalhs_external_clock                                              */
18363             uint32_t            : 23;
18364     } XTALHSCTRL_b;
18365   } ;
18366   __IM  uint32_t  RESERVED9[20];
18367 
18368   union {
18369     __IOM uint32_t MRAMPWRCTRL;                 /*!< (@ 0x00000180) MRAM Power Control                                         */
18370 
18371     struct {
18372       __IOM uint32_t MRAMLPREN  : 1;            /*!< [0..0] MRAM low power mode enable                                         */
18373       __IOM uint32_t MRAMSLPEN  : 1;            /*!< [1..1] MRAM sleep mode enable                                             */
18374       __IOM uint32_t MRAMPWRCTRL : 1;           /*!< [2..2] MRAM low power mode control. When set to 1, tmc_lpr and
18375                                                      tmc_slp are driven by the value of MRAMLPREN and MRAMSLPEN
18376                                                      of this register.                                                         */
18377             uint32_t            : 29;
18378     } MRAMPWRCTRL_b;
18379   } ;
18380   __IM  uint32_t  RESERVED10[10];
18381 
18382   union {
18383     __IOM uint32_t BODISABLE;                   /*!< (@ 0x000001AC) Brownout Disable                                           */
18384 
18385     struct {
18386       __IOM uint32_t BODLRDE    : 1;            /*!< [0..0] Disable Unregulated 1.8V Brown-out reset.                          */
18387       __IOM uint32_t BODCREN    : 1;            /*!< [1..1] Disable VDDC Brown Out reset.                                      */
18388       __IOM uint32_t BODFREN    : 1;            /*!< [2..2] Disable VDDF Brown Out reset.                                      */
18389       __IOM uint32_t BODSREN    : 1;            /*!< [3..3] Disable VDDS Brown Out reset.                                      */
18390       __IOM uint32_t BODCLVREN  : 1;            /*!< [4..4] Disable VDDC_LV Brown Out reset.                                   */
18391             uint32_t            : 27;
18392     } BODISABLE_b;
18393   } ;
18394 
18395   union {
18396     __IOM uint32_t D2ASPARE;                    /*!< (@ 0x000001B0) Spare registers to analog module                           */
18397 
18398     struct {
18399             uint32_t            : 3;
18400       __IOM uint32_t VDDCPUOVERRIDE : 1;        /*!< [3..3] VDDCPU Override. Set to 1 to connect to the VDDC rail,
18401                                                      set to 0 to connect to the VDDC_LV rail. Before setting
18402                                                      this bit to 0, the VDDC_LV rail must first be enabled by
18403                                                      setting SIMOBUCK0_b.VDDCLVRXCOMPEN. Do not modify this
18404                                                      field unless directed to do so by Ambiq engineering. If
18405                                                      modifying, a RMW operation such as MCUCTRL->D2ASPARE_b.VDDCPUOVERRIDE=1
18406                                                      must be used.                                                             */
18407       __IOM uint32_t VDDCAOROVERRIDE : 1;       /*!< [4..4] VDDCAOR Override. Set to 1 to connect to the VDDC rail,
18408                                                      set to 0 to connect to the VDDC_LV rail. Before setting
18409                                                      this bit to 0, the VDDC_LV rail must first be enabled by
18410                                                      setting SIMOBUCK0_b.VDDCLVRXCOMPEN. Do not modify this
18411                                                      field unless directed to do so by Ambiq engineering. If
18412                                                      modifying, a RMW operation such as MCUCTRL->D2ASPARE_b.VDDCAOROVERRIDE=1
18413                                                      must be used.                                                             */
18414             uint32_t            : 27;
18415     } D2ASPARE_b;
18416   } ;
18417   __IM  uint32_t  RESERVED11;
18418 
18419   union {
18420     __IOM uint32_t BOOTLOADER;                  /*!< (@ 0x000001B8) Bootloader and secure boot functions                       */
18421 
18422     struct {
18423       __IOM uint32_t BOOTLOADERLOW : 1;         /*!< [0..0] Determines whether the bootloader code is visible at
18424                                                      address 0x00000000 or not. Resets to 1, write 1 to clear.                 */
18425       __IOM uint32_t SBRLOCK    : 1;            /*!< [1..1] Secure boot ROM lock. Always resets to 1, write 1 to
18426                                                      clear. Enables system visibility to bootloader until set.                 */
18427       __IOM uint32_t PROTLOCK   : 1;            /*!< [2..2] Flash protection lock. Always resets to 1, write 1 to
18428                                                      clear. Enables writes to flash protection register set.                   */
18429       __IOM uint32_t SBLLOCK    : 1;            /*!< [3..3] Secure boot loader lock. Always resets to 1, write 1
18430                                                      to clear. Enables system visibility to bootloader until
18431                                                      set.                                                                      */
18432             uint32_t            : 22;
18433       __IOM uint32_t SECBOOTFEATURE : 2;        /*!< [27..26] Indicates whether the secure boot feature is enabled.            */
18434       __IOM uint32_t SECBOOT    : 2;            /*!< [29..28] Indicates whether the secure boot on cold reset is
18435                                                      enabled                                                                   */
18436       __IOM uint32_t SECBOOTONRST : 2;          /*!< [31..30] Indicates whether the secure boot on warm reset is
18437                                                      enabled                                                                   */
18438     } BOOTLOADER_b;
18439   } ;
18440 
18441   union {
18442     __IOM uint32_t SHADOWVALID;                 /*!< (@ 0x000001BC) Register to indicate whether the shadow registers
18443                                                                     have been successfully loaded from the Flash
18444                                                                     Information Space.                                         */
18445 
18446     struct {
18447       __IOM uint32_t VALID      : 1;            /*!< [0..0] Indicates whether the shadow registers contain valid
18448                                                      data from the Flash Information Space.                                    */
18449       __IOM uint32_t BLDSLEEP   : 1;            /*!< [1..1] Indicates whether the bootloader should sleep or deep
18450                                                      sleep if no image loaded.                                                 */
18451       __IOM uint32_t INFO0VALID : 1;            /*!< [2..2] Indicates whether info0 contains valid data                        */
18452             uint32_t            : 29;
18453     } SHADOWVALID_b;
18454   } ;
18455 
18456   union {
18457     __IOM uint32_t SCRATCH0;                    /*!< (@ 0x000001C0) Scratch register that is not reset by any reset            */
18458 
18459     struct {
18460       __IOM uint32_t SCRATCH0   : 32;           /*!< [31..0] Scratch register 0.                                               */
18461     } SCRATCH0_b;
18462   } ;
18463 
18464   union {
18465     __IOM uint32_t SCRATCH1;                    /*!< (@ 0x000001C4) Scratch register that is not reset by any reset            */
18466 
18467     struct {
18468       __IOM uint32_t SCRATCH1   : 32;           /*!< [31..0] Scratch register 1.                                               */
18469     } SCRATCH1_b;
18470   } ;
18471   __IM  uint32_t  RESERVED12[14];
18472 
18473   union {
18474     __IOM uint32_t DBGR1;                       /*!< (@ 0x00000200) Read-only debug 1                                          */
18475 
18476     struct {
18477       __IOM uint32_t ONETO8     : 32;           /*!< [31..0] Read-only register for communication validation                   */
18478     } DBGR1_b;
18479   } ;
18480 
18481   union {
18482     __IOM uint32_t DBGR2;                       /*!< (@ 0x00000204) Read-only debug 2                                          */
18483 
18484     struct {
18485       __IOM uint32_t COOLCODE   : 32;           /*!< [31..0] Read-only register for communication validation                   */
18486     } DBGR2_b;
18487   } ;
18488   __IM  uint32_t  RESERVED13[6];
18489 
18490   union {
18491     __IOM uint32_t PMUENABLE;                   /*!< (@ 0x00000220) Control bit to enable/disable the PMU                      */
18492 
18493     struct {
18494       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will
18495                                                      place the MCU into the lowest power consuming Deep Sleep
18496                                                      mode upon execution of a WFI instruction (dependent on
18497                                                      the setting of the SLEEPDEEP bit in the ARM SCR register).
18498                                                      When cleared, regardless of the requested sleep mode, the
18499                                                      PMU will not enter the lowest power Deep Sleep mode, instead
18500                                                      entering the Sleep mode.                                                  */
18501             uint32_t            : 31;
18502     } PMUENABLE_b;
18503   } ;
18504   __IM  uint32_t  RESERVED14[11];
18505 
18506   union {
18507     __IOM uint32_t DBGCTRL;                     /*!< (@ 0x00000250) Debug subsystem Control. Determines the debug
18508                                                                     components enable and clk frequency.                       */
18509 
18510     struct {
18511       __IOM uint32_t CM4TPIUENABLE : 1;         /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled
18512                                                      and data can be streamed out trace data from ARM ITM and
18513                                                      ETM modules through either SWO or TRACEDATA ports                         */
18514       __IOM uint32_t CM4CLKSEL  : 3;            /*!< [3..1] This field selects the frequency of the ARM M4 TPIU port.          */
18515             uint32_t            : 4;
18516       __IOM uint32_t DBGETBENABLE : 1;          /*!< [8..8] Debug subsystem ETB enable to store the trace data.                */
18517       __IOM uint32_t DBGETMTRACEEN : 1;         /*!< [9..9] Debug subsystem ETM trace enable                                   */
18518       __IOM uint32_t DBGDSP0TRACEEN : 1;        /*!< [10..10] Debug subsystem DSP0 trace enable                                */
18519       __IOM uint32_t DBGDSP1TRACEEN : 1;        /*!< [11..11] Debug subsystem DSP1 trace enable                                */
18520       __IOM uint32_t DBGTSCLKSEL : 3;           /*!< [14..12] This field selects the frequency of the ARM M4 dbg
18521                                                      ts port.                                                                  */
18522             uint32_t            : 1;
18523       __IOM uint32_t DBGDSP0OCDHALTONRST : 1;   /*!< [16..16] Debug subsystem DSP0 OCD Halt on Reset                           */
18524       __IOM uint32_t DBGDSP1OCDHALTONRST : 1;   /*!< [17..17] Debug subsystem DSP1 OCD Halt on Reset                           */
18525             uint32_t            : 14;
18526     } DBGCTRL_b;
18527   } ;
18528   __IM  uint32_t  RESERVED15[4];
18529 
18530   union {
18531     __IOM uint32_t OTAPOINTER;                  /*!< (@ 0x00000264) OTA (Over the Air) Update Pointer/Status. Reset
18532                                                                     only by POA                                                */
18533 
18534     struct {
18535       __IOM uint32_t OTAVALID   : 1;            /*!< [0..0] Indicates that an OTA update is valid                              */
18536       __IOM uint32_t OTASBLUPDATE : 1;          /*!< [1..1] Indicates that the sbl_init has been updated                       */
18537       __IOM uint32_t OTAPOINTER : 30;           /*!< [31..2] Flash page pointer with updated OTA image                         */
18538     } OTAPOINTER_b;
18539   } ;
18540   __IM  uint32_t  RESERVED16[6];
18541 
18542   union {
18543     __IOM uint32_t APBDMACTRL;                  /*!< (@ 0x00000280) DMA Control Register. Determines misc settings
18544                                                                     for DMA operation                                          */
18545 
18546     struct {
18547       __IOM uint32_t DMAENABLE  : 1;            /*!< [0..0] Enable the DMA controller. When disabled, DMA requests
18548                                                      will be ignored by the controller                                         */
18549       __IOM uint32_t DECODEABORT : 1;           /*!< [1..1] APB Decode Abort. When set, the APB bridge will issue
18550                                                      a data abort (bus fault) on transactions to peripherals
18551                                                      that are powered down. When set to 0, writes are quietly
18552                                                      discarded and reads return 0.                                             */
18553             uint32_t            : 6;
18554       __IOM uint32_t HYSTERESIS : 8;            /*!< [15..8] This field determines how long the DMA engine of apb/disp/gfx
18555                                                      will remain active during deep sleep before shutting down
18556                                                      and returning the system to full deep sleep. Values are
18557                                                      based on a 94KHz clock and are roughly 10us increments
18558                                                      for a range of ~10us to 2.55ms                                            */
18559             uint32_t            : 16;
18560     } APBDMACTRL_b;
18561   } ;
18562   __IM  uint32_t  RESERVED17[45];
18563 
18564   union {
18565     __IOM uint32_t KEXTCLKSEL;                  /*!< (@ 0x00000338) Locks the state of the EXTCLKSEL register from
18566                                                                     writes. This is done to prevent errant writes
18567                                                                     to the register, as this could cause the
18568                                                                     chip to halt. Write a value of 0x53 to unlock
18569                                                                     write access to the EXTCLKSEL register.
18570                                                                     Once unlocked, the register will read back
18571                                                                     a 1 to undicate this is unlocked. Writing
18572                                                                     the register with any other value other
18573                                                                     than 0x53 will enable the lock.                            */
18574 
18575     struct {
18576       __IOM uint32_t KEXTCLKSEL : 32;           /*!< [31..0] Key register value.                                               */
18577     } KEXTCLKSEL_b;
18578   } ;
18579 
18580   union {
18581     __IOM uint32_t SIMOBUCK0;                   /*!< (@ 0x0000033C) This WRITE_ONLY register controls various buck
18582                                                                     parameters. It will read back as 0x00000000.               */
18583 
18584     struct {
18585       __IOM uint32_t VDDCRXCOMPEN : 1;          /*!< [0..0] Enable the VDDC rail.                                              */
18586       __IOM uint32_t VDDFRXCOMPEN : 1;          /*!< [1..1] Enable the VDDS rail.                                              */
18587       __IOM uint32_t VDDSRXCOMPEN : 1;          /*!< [2..2] Enable the VDDS rail.                                              */
18588       __IOM uint32_t VDDCLVRXCOMPEN : 1;        /*!< [3..3] Enable the VDDC LV rail.                                           */
18589       __IOM uint32_t TONTOFFNODEGLITCH : 1;     /*!< [4..4] Enable the ton and toff signals no deglitch output.                */
18590             uint32_t            : 27;
18591     } SIMOBUCK0_b;
18592   } ;
18593 
18594   union {
18595     __IOM uint32_t SIMOBUCK1;                   /*!< (@ 0x00000340) 1. Control the even division of 3 clocks: refresh,
18596                                                                     low power and TONCLK. 2. Control gap bewteen
18597                                                                     secondary switches. 3. Debug features: control
18598                                                                     the amount of time TONCLK is on, and the
18599                                                                     time before snubber asserts for each buck
18600                                                                     sequence. 4. Enable or disable the observation
18601                                                                     bus. 5. Select the buck sequence operation
18602                                                                     mode. 6. Control delay between primary Pmos
18603                                                                     and Nmos transitions.                                      */
18604 
18605     struct {
18606             uint32_t            : 6;
18607       __IOM uint32_t RXCLKACTTRIM : 5;          /*!< [10..6] This divides the 5 MHz refresh clock. Even divides are
18608                                                      supported only. This value represents the division amount
18609                                                      minus 1.                                                                  */
18610             uint32_t            : 11;
18611       __IOM uint32_t TONCLKTRIM : 4;            /*!< [25..22] This divides the 100 MHz ton clock. Even divides are
18612                                                      supported only. This value represents the division amount
18613                                                      minus 1.                                                                  */
18614             uint32_t            : 6;
18615     } SIMOBUCK1_b;
18616   } ;
18617 
18618   union {
18619     __IOM uint32_t SIMOBUCK2;                   /*!< (@ 0x00000344) SIMO Buck Muxed VDDC Active Sequence Trim Control          */
18620 
18621     struct {
18622             uint32_t            : 11;
18623       __IOM uint32_t VDDCACTHIGHTONTRIM : 4;    /*!< [14..11] VDDC active high ton trim control for Buck sequence.             */
18624             uint32_t            : 9;
18625       __IOM uint32_t VDDCACTLOWTONTRIM : 5;     /*!< [28..24] VDDC active high ton trim control for Buck sequence.             */
18626             uint32_t            : 3;
18627     } SIMOBUCK2_b;
18628   } ;
18629 
18630   union {
18631     __IOM uint32_t SIMOBUCK3;                   /*!< (@ 0x00000348) SIMO Buck Muxed VDDC low power Sequence Trim
18632                                                                     Control                                                    */
18633 
18634     struct {
18635             uint32_t            : 13;
18636       __IOM uint32_t VDDCLPHIGHTONTRIM : 4;     /*!< [16..13] VDDC LP high ton trim control for Buck sequence.                 */
18637             uint32_t            : 9;
18638       __IOM uint32_t VDDCLPLOWTONTRIM : 4;      /*!< [29..26] VDDC LP low ton trim control for Buck sequence.                  */
18639             uint32_t            : 2;
18640     } SIMOBUCK3_b;
18641   } ;
18642   __IM  uint32_t  RESERVED18[2];
18643 
18644   union {
18645     __IOM uint32_t SIMOBUCK6;                   /*!< (@ 0x00000354) SIMO Buck Muxed VDDF Active Sequence Trim Control          */
18646 
18647     struct {
18648             uint32_t            : 17;
18649       __IOM uint32_t VDDFACTHIGHTONTRIM : 4;    /*!< [20..17] VDDF active high ton trim control for Buck sequence.             */
18650             uint32_t            : 11;
18651     } SIMOBUCK6_b;
18652   } ;
18653 
18654   union {
18655     __IOM uint32_t SIMOBUCK7;                   /*!< (@ 0x00000358) SIMO Buck Muxed VDDF active Sequence Trim Control          */
18656 
18657     struct {
18658             uint32_t            : 8;
18659       __IOM uint32_t VDDFACTLOWTONTRIM : 5;     /*!< [12..8] VDDF active low ton trim control for Buck sequence.               */
18660             uint32_t            : 5;
18661       __IOM uint32_t ZXCOMPZXTRIM : 5;          /*!< [22..18] Zxcomp trim. Feedthrough to analog.                              */
18662             uint32_t            : 9;
18663     } SIMOBUCK7_b;
18664   } ;
18665 
18666   union {
18667     __IOM uint32_t SIMOBUCK8;                   /*!< (@ 0x0000035C) SIMO Buck Muxed VDDF Low Power Sequence Trim
18668                                                                     Control                                                    */
18669 
18670     struct {
18671             uint32_t            : 9;
18672       __IOM uint32_t VDDFLPHIGHTONTRIM : 4;     /*!< [12..9] VDDF low power high ton trim control for Buck sequence.           */
18673             uint32_t            : 9;
18674       __IOM uint32_t VDDFLPLOWTONTRIM : 4;      /*!< [25..22] VDDF low power low ton trim control for Buck sequence.           */
18675             uint32_t            : 6;
18676     } SIMOBUCK8_b;
18677   } ;
18678 
18679   union {
18680     __IOM uint32_t SIMOBUCK9;                   /*!< (@ 0x00000360) SIMO Buck Muxed VDDS Active Sequence Trim Control          */
18681 
18682     struct {
18683             uint32_t            : 17;
18684       __IOM uint32_t VDDSACTHIGHTONTRIM : 4;    /*!< [20..17] VDDS active high ton trim control for Buck sequence.             */
18685             uint32_t            : 1;
18686       __IOM uint32_t VDDSACTLOWTONTRIM : 5;     /*!< [26..22] VDDS active low ton trim control for Buck sequence.              */
18687             uint32_t            : 5;
18688     } SIMOBUCK9_b;
18689   } ;
18690   __IM  uint32_t  RESERVED19[2];
18691 
18692   union {
18693     __IOM uint32_t SIMOBUCK12;                  /*!< (@ 0x0000036C) SIMO Buck Compare, Brown out, Active, Low power
18694                                                                     Trim Control                                               */
18695 
18696     struct {
18697             uint32_t            : 20;
18698       __IOM uint32_t ACTTRIMVDDF : 6;           /*!< [25..20] Active VDDF trim.                                                */
18699       __IOM uint32_t LPTRIMVDDF : 6;            /*!< [31..26] Low power VDDF trim.                                             */
18700     } SIMOBUCK12_b;
18701   } ;
18702 
18703   union {
18704     __IOM uint32_t SIMOBUCK13;                  /*!< (@ 0x00000370) SIMO Buck Compare, Brown out, Active, Low power
18705                                                                     Trim Control                                               */
18706 
18707     struct {
18708             uint32_t            : 20;
18709       __IOM uint32_t ACTTRIMVDDS : 6;           /*!< [25..20] Active VDDS trim.                                                */
18710       __IOM uint32_t LPTRIMVDDS : 6;            /*!< [31..26] Low power VDDS trim.                                             */
18711     } SIMOBUCK13_b;
18712   } ;
18713   __IM  uint32_t  RESERVED20;
18714 
18715   union {
18716     __IOM uint32_t SIMOBUCK15;                  /*!< (@ 0x00000378) SIMO Buck Compare, Brown out, Active and Low
18717                                                                     power Trim Control                                         */
18718 
18719     struct {
18720             uint32_t            : 24;
18721       __IOM uint32_t ZXCOMPOFFSETTRIM : 5;      /*!< [28..24] Zxcomp offset trim. Feedthrough to analog.                       */
18722             uint32_t            : 2;
18723       __IOM uint32_t TRIMLATCHOVER : 1;         /*!< [31..31] Override / Bypass the simobuck trim latch to enable
18724                                                      on-the-fly trimming for VDDF and VDDS active and LP trims                 */
18725     } SIMOBUCK15_b;
18726   } ;
18727 
18728   union {
18729     __IOM uint32_t PWRSW0;                      /*!< (@ 0x0000037C) PWRSW Control 0                                            */
18730 
18731     struct {
18732       __IOM uint32_t PWRSWVDDCPUDYNSEL : 2;     /*!< [1..0] override value for pwrsw_vddcpu_dynsel                             */
18733       __IOM uint32_t PWRSWVDDCPUPGN : 1;        /*!< [2..2] override value for pwrsw_vddcpu_pgn                                */
18734       __IOM uint32_t PWRSWVDDCPUOVERRIDE : 1;   /*!< [3..3] override enable for pwrsw_vddcpu_dynsel and pgn                    */
18735       __IOM uint32_t PWRSWVDDCAORDYNSEL : 2;    /*!< [5..4] override value for pwrsw_vddcaor_dynsel                            */
18736       __IOM uint32_t PWRSWVDDCAOROVERRIDE : 1;  /*!< [6..6] override enable for pwrsw_vddcaor_dynsel                           */
18737       __IOM uint32_t PWRSWVDDDSP0DYNSEL : 2;    /*!< [8..7] override value for pwrsw_vdddsp0_dynsel                            */
18738       __IOM uint32_t PWRSWVDDDSP0PGN : 1;       /*!< [9..9] override value for pwrsw_vdddsp0_pgn                               */
18739       __IOM uint32_t PWRSWVDDDSP0OVERRIDE : 1;  /*!< [10..10] override enable for pwrsw_vdddsp0_dynsel and pgn                 */
18740       __IOM uint32_t PWRSWVDDDSP1DYNSEL : 2;    /*!< [12..11] override value for pwrsw_vdddsp1_dynsel                          */
18741       __IOM uint32_t PWRSWVDDDSP1PGN : 1;       /*!< [13..13] override value for pwrsw_vdddsp1_pgn                             */
18742       __IOM uint32_t PWRSWVDDDSP1OVERRIDE : 1;  /*!< [14..14] override enable for pwrsw_vdddsp1_dynsel and pgn                 */
18743       __IOM uint32_t PWRSWVDDMCPUDYNSEL : 1;    /*!< [15..15] override value for pwrsw_vddmcpu_dynsel                          */
18744       __IOM uint32_t PWRSWVDDMCPUSTATSEL : 1;   /*!< [16..16] VDDMCPU power switch static select                               */
18745       __IOM uint32_t PWRSWVDDMCPUOVERRIDE : 1;  /*!< [17..17] override enable for pwrsw_vddmcpu_dynsel                         */
18746       __IOM uint32_t PWRSWVDDMDSP0DYNSEL : 1;   /*!< [18..18] override value for pwrsw_vddmdsp0_dynsel                         */
18747       __IOM uint32_t PWRSWVDDMDSP0STATSEL : 1;  /*!< [19..19] VDDMDSP0 power switch static select                              */
18748       __IOM uint32_t PWRSWVDDMDSP0OVERRIDE : 1; /*!< [20..20] override enable for pwrsw_vddmdsp0_dynsel                        */
18749       __IOM uint32_t PWRSWVDDMDSP1DYNSEL : 1;   /*!< [21..21] override value for pwrsw_vddmdsp1_dynsel                         */
18750       __IOM uint32_t PWRSWVDDMDSP1STATSEL : 1;  /*!< [22..22] VDDMDSP1 power switch static select                              */
18751       __IOM uint32_t PWRSWVDDMDSP1OVERRIDE : 1; /*!< [23..23] override enable for pwrsw_vddmdsp1_dynsel                        */
18752       __IOM uint32_t PWRSWVDDMLDYNSEL : 1;      /*!< [24..24] override value for pwrsw_vddml_dynsel                            */
18753       __IOM uint32_t PWRSWVDDMLSTATSEL : 1;     /*!< [25..25] VDDML power switch static select                                 */
18754       __IOM uint32_t PWRSWVDDMLOVERRIDE : 1;    /*!< [26..26] override enable for pwrsw_vddml_dynsel                           */
18755       __IOM uint32_t PWRSWVDDRCPUDYNSEL : 2;    /*!< [28..27] override value for pwrsw_vddrcpu_dynsel                          */
18756       __IOM uint32_t PWRSWVDDRCPUPGN : 1;       /*!< [29..29] override value for pwrsw_vddrcpu_pgn                             */
18757       __IOM uint32_t PWRSWVDDRCPUSTATSEL : 1;   /*!< [30..30] VDDRCPU power switch static select                               */
18758       __IOM uint32_t PWRSWVDDRCPUOVERRIDE : 1;  /*!< [31..31] override enable for pwrsw_vddrcpu_dynsel and pgn                 */
18759     } PWRSW0_b;
18760   } ;
18761 
18762   union {
18763     __IOM uint32_t PWRSW1;                      /*!< (@ 0x00000380) PWRSW Control 1                                            */
18764 
18765     struct {
18766       __IOM uint32_t PWRSWVDDRDSP0DYNSEL : 2;   /*!< [1..0] override value for pwrsw_vddrdsp0_dynsel                           */
18767       __IOM uint32_t PWRSWVDDRDSP0PGN : 1;      /*!< [2..2] override value for pwrsw_vddrdsp0_pgn                              */
18768       __IOM uint32_t PWRSWVDDRDSP0STATSEL : 1;  /*!< [3..3] VDDRDSP0 power switch static select                                */
18769       __IOM uint32_t PWRSWVDDRDSP0OVERRIDE : 1; /*!< [4..4] override enable for pwrsw_vddrdsp0_dynsel and pgn                  */
18770       __IOM uint32_t PWRSWVDDRDSP1DYNSEL : 2;   /*!< [6..5] override value for pwrsw_vddrdsp1_dynsel                           */
18771       __IOM uint32_t PWRSWVDDRDSP1PGN : 1;      /*!< [7..7] override value for pwrsw_vddrdsp1_pgn                              */
18772       __IOM uint32_t PWRSWVDDRDSP1STATSEL : 1;  /*!< [8..8] VDDRDSP1 power switch static select                                */
18773       __IOM uint32_t PWRSWVDDRDSP1OVERRIDE : 1; /*!< [9..9] override enable for pwrsw_vddrdsp1_dynsel and pgn                  */
18774       __IOM uint32_t PWRSWVDDRLDYNSEL : 1;      /*!< [10..10] override value for pwrsw_vddrl_dynsel                            */
18775       __IOM uint32_t PWRSWVDDRLPGN : 1;         /*!< [11..11] override value for pwrsw_vddrl_pgn                               */
18776       __IOM uint32_t PWRSWVDDRLSTATSEL : 1;     /*!< [12..12] VDDRL power switch static select                                 */
18777       __IOM uint32_t PWRSWVDDRLOVERRIDE : 1;    /*!< [13..13] override enable for pwrsw_vddrl_dynsel and pgn                   */
18778       __IOM uint32_t PWRSWVDDRMDYNSEL : 1;      /*!< [14..14] override value for pwrsw_vddrm_dynsel                            */
18779       __IOM uint32_t PWRSWVDDRMPGN : 1;         /*!< [15..15] override value for pwrsw_vddrm_pgn                               */
18780       __IOM uint32_t PWRSWVDDRMSTATSEL : 1;     /*!< [16..16] VDDRM power switch static select                                 */
18781       __IOM uint32_t PWRSWVDDRMOVERRIDE : 1;    /*!< [17..17] override enable for pwrsw_vddrm_dynsel and pgn                   */
18782       __IOM uint32_t PWRSWVDDLPGN : 1;          /*!< [18..18] override value for pwrsw_vddl_pgn                                */
18783       __IOM uint32_t PWRSWVDDLOVERRIDE : 1;     /*!< [19..19] override enable for pwrsw_vddl_pgn                               */
18784       __IOM uint32_t PWRSWCOMPPDNB : 1;         /*!< [20..20] pwrsw_comp_pdnb                                                  */
18785       __IOM uint32_t PWRSWOVRDRVEN : 1;         /*!< [21..21] pwrsw_ovrdrv_en                                                  */
18786       __IOM uint32_t DIGPWRSWOVRDRVEN : 1;      /*!< [22..22] digpwrsw_ovrdrv_en                                               */
18787       __IOM uint32_t DIGPWRSWOVRDRVSEL : 2;     /*!< [24..23] digpwrsw_ovrdrv_sel                                              */
18788       __IOM uint32_t USEVDDF4VDDRCPUINHP : 1;   /*!< [25..25] Setting this bit selects VDDF for VDDRCPU in when MCU
18789                                                      is in HP mode. This is valid for only normal operational
18790                                                      mode (i.e without overrides).                                             */
18791       __IOM uint32_t FORCEVDDRMVDDS : 1;        /*!< [26..26] Setting this bit selects VDDS for VDDRM when Flash
18792                                                      is off. This is valid for only normal operational mode
18793                                                      (i.e. without overrides).                                                 */
18794       __IOM uint32_t FORCEVDDRMOFF : 1;         /*!< [27..27] Setting this bit forces VDDRM to be open when Flash
18795                                                      is off. This is valid for only normal operational mode
18796                                                      (i.e. without overrides).                                                 */
18797       __IOM uint32_t SHORTVDDCVDDCLVOREN : 1;   /*!< [28..28] pwrsw short override select for vddc/vddclv                      */
18798       __IOM uint32_t SHORTVDDCVDDCLVORVAL : 1;  /*!< [29..29] pwrsw short override value for vddc/vddclv                       */
18799       __IOM uint32_t SHORTVDDFVDDSOREN : 1;     /*!< [30..30] pwrsw short override select for vddf/vdds                        */
18800       __IOM uint32_t SHORTVDDFVDDSORVAL : 1;    /*!< [31..31] pwrsw short override value for vddf/vdds                         */
18801     } PWRSW1_b;
18802   } ;
18803   __IM  uint32_t  RESERVED21;
18804 
18805   union {
18806     __IOM uint32_t USBRSTCTRL;                  /*!< (@ 0x00000388) USB Reset Startup Control                                  */
18807 
18808     struct {
18809       __IOM uint32_t USBRSTENABLE : 1;          /*!< [0..0] This bit enables this register control. If set to '1',
18810                                                      the reset release bits will be active. If set to '0', this
18811                                                      register is not controlling the USB override bits.                        */
18812       __IOM uint32_t USBPORRSTRELEASE : 1;      /*!< [1..1] Set this bit to '1' after USB power domain is up. This
18813                                                      will release the reset override condition                                 */
18814       __IOM uint32_t USBUTMIRSTRELEASE : 1;     /*!< [2..2] Set this bit to '1' after USB power domain is up. This
18815                                                      will release the reset override condition                                 */
18816             uint32_t            : 29;
18817     } USBRSTCTRL_b;
18818   } ;
18819   __IM  uint32_t  RESERVED22[7];
18820 
18821   union {
18822     __IOM uint32_t FLASHWPROT0;                 /*!< (@ 0x000003A8) These bits write-protect flash in 16KB chunks.             */
18823 
18824     struct {
18825       __IOM uint32_t FW0BITS    : 32;           /*!< [31..0] Write protect flash 0x00000000 - 0x0007FFFF. Each bit
18826                                                      provides write protection for 16KB chunks of flash data
18827                                                      space. Bits are cleared by writing a 1 to the bit. When
18828                                                      read, 0 indicates the region is protected. Bits are sticky
18829                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
18830     } FLASHWPROT0_b;
18831   } ;
18832 
18833   union {
18834     __IOM uint32_t FLASHWPROT1;                 /*!< (@ 0x000003AC) These bits write-protect flash in 16KB chunks.             */
18835 
18836     struct {
18837       __IOM uint32_t FW1BITS    : 32;           /*!< [31..0] Write protect flash 0x00080000 - 0x000FFFFF. Each bit
18838                                                      provides write protection for 16KB chunks of flash data
18839                                                      space. Bits are cleared by writing a 1 to the bit. When
18840                                                      read, 0 indicates the region is protected. Bits are sticky
18841                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
18842     } FLASHWPROT1_b;
18843   } ;
18844 
18845   union {
18846     __IOM uint32_t FLASHWPROT2;                 /*!< (@ 0x000003B0) These bits write-protect flash in 16KB chunks.             */
18847 
18848     struct {
18849       __IOM uint32_t FW2BITS    : 32;           /*!< [31..0] Write protect flash 0x00100000 - 0x0017FFFF. Each bit
18850                                                      provides write protection for 16KB chunks of flash data
18851                                                      space. Bits are cleared by writing a 1 to the bit. When
18852                                                      read, 0 indicates the region is protected. Bits are sticky
18853                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
18854     } FLASHWPROT2_b;
18855   } ;
18856 
18857   union {
18858     __IOM uint32_t FLASHWPROT3;                 /*!< (@ 0x000003B4) These bits write-protect flash in 16KB chunks.             */
18859 
18860     struct {
18861       __IOM uint32_t FW3BITS    : 32;           /*!< [31..0] Write protect flash 0x00180000 - 0x001FFFFF. Each bit
18862                                                      provides write protection for 16KB chunks of flash data
18863                                                      space. Bits are cleared by writing a 1 to the bit. When
18864                                                      read, 0 indicates the region is protected. Bits are sticky
18865                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
18866     } FLASHWPROT3_b;
18867   } ;
18868 
18869   union {
18870     __IOM uint32_t FLASHRPROT0;                 /*!< (@ 0x000003B8) These bits read-protect flash in 16KB chunks.              */
18871 
18872     struct {
18873       __IOM uint32_t FR0BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each
18874                                                      bit provides read protection for 16KB chunks of flash.
18875                                                      Bits are cleared by writing a 1 to the bit. When read,
18876                                                      0 indicates the region is protected. Bits are sticky (can
18877                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
18878     } FLASHRPROT0_b;
18879   } ;
18880 
18881   union {
18882     __IOM uint32_t FLASHRPROT1;                 /*!< (@ 0x000003BC) These bits read-protect flash in 16KB chunks.              */
18883 
18884     struct {
18885       __IOM uint32_t FR1BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each
18886                                                      bit provides read protection for 16KB chunks of flash.
18887                                                      Bits are cleared by writing a 1 to the bit. When read,
18888                                                      0 indicates the region is protected. Bits are sticky (can
18889                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
18890     } FLASHRPROT1_b;
18891   } ;
18892 
18893   union {
18894     __IOM uint32_t FLASHRPROT2;                 /*!< (@ 0x000003C0) These bits read-protect flash in 16KB chunks.              */
18895 
18896     struct {
18897       __IOM uint32_t FR2BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00100000 - 0x0017FFFF. Each
18898                                                      bit provides read protection for 16KB chunks of flash.
18899                                                      Bits are cleared by writing a 1 to the bit. When read,
18900                                                      0 indicates the region is protected. Bits are sticky (can
18901                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
18902     } FLASHRPROT2_b;
18903   } ;
18904 
18905   union {
18906     __IOM uint32_t FLASHRPROT3;                 /*!< (@ 0x000003C4) These bits read-protect flash in 16KB chunks.              */
18907 
18908     struct {
18909       __IOM uint32_t FR3BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00180000 - 0x001FFFFF. Each
18910                                                      bit provides read protection for 16KB chunks of flash.
18911                                                      Bits are cleared by writing a 1 to the bit. When read,
18912                                                      0 indicates the region is protected. Bits are sticky (can
18913                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
18914     } FLASHRPROT3_b;
18915   } ;
18916 
18917   union {
18918     __IOM uint32_t DMASRAMWPROT0;               /*!< (@ 0x000003C8) These bits write-protect system SRAM from DMA
18919                                                                     operations in 8KB chunks.                                  */
18920 
18921     struct {
18922       __IOM uint32_t DMAWPROT0  : 32;           /*!< [31..0] Write protect SRAM from DMA. Each bit provides write
18923                                                      protection for an 8KB region of memory. When set to 1,
18924                                                      the region will be protected from DMA writes, when set
18925                                                      to 0, DMA may write the region.                                           */
18926     } DMASRAMWPROT0_b;
18927   } ;
18928 
18929   union {
18930     __IOM uint32_t DMASRAMWPROT1;               /*!< (@ 0x000003CC) These bits write-protect system SRAM from DMA
18931                                                                     operations in 8KB chunks.                                  */
18932 
18933     struct {
18934       __IOM uint32_t DMAWPROT1  : 16;           /*!< [15..0] Write protect SRAM from DMA. Each bit provides write
18935                                                      protection for an 8KB region of memory. When set to 1,
18936                                                      the region will be protected from DMA writes, when set
18937                                                      to 0, DMA may write the region.                                           */
18938             uint32_t            : 16;
18939     } DMASRAMWPROT1_b;
18940   } ;
18941 
18942   union {
18943     __IOM uint32_t DMASRAMRPROT0;               /*!< (@ 0x000003D0) These bits read-protect system SRAM from DMA
18944                                                                     operations in 8KB chunks.                                  */
18945 
18946     struct {
18947       __IOM uint32_t DMARPROT0  : 32;           /*!< [31..0] Read protect SRAM from DMA. Each bit provides write
18948                                                      protection for an 8KB region of memory. When set to 1,
18949                                                      the region will be protected from DMA reads, when set to
18950                                                      0, DMA may read the region.                                               */
18951     } DMASRAMRPROT0_b;
18952   } ;
18953 
18954   union {
18955     __IOM uint32_t DMASRAMRPROT1;               /*!< (@ 0x000003D4) These bits read-protect system SRAM from DMA
18956                                                                     operations in 8KB chunks.                                  */
18957 
18958     struct {
18959       __IOM uint32_t DMARPROT1  : 16;           /*!< [15..0] Read protect SRAM from DMA. Each bit provides write
18960                                                      protection for an 8KB region of memory. When set to 1,
18961                                                      the region will be protected from DMA reads, when set to
18962                                                      0, DMA may read the region.                                               */
18963             uint32_t            : 16;
18964     } DMASRAMRPROT1_b;
18965   } ;
18966   __IM  uint32_t  RESERVED23[16];
18967 
18968   union {
18969     __IOM uint32_t USBPHYRESET;                 /*!< (@ 0x00000418) DSP0 CACHE RAM TRIM                                        */
18970 
18971     struct {
18972       __IOM uint32_t USBPHYPORRSTDIS : 1;       /*!< [0..0] De-assert USB PHY POR reset override                               */
18973       __IOM uint32_t USBPHYUTMIRSTDIS : 1;      /*!< [1..1] De-assert USB PHY UTMI reset override                              */
18974       __IOM uint32_t RESERVED01 : 3;            /*!< [4..2] DSP0 ICACHE TAG EMA                                                */
18975       __IOM uint32_t RESERVED02 : 1;            /*!< [5..5] DSP0 ICACHE TAG EMAS                                               */
18976       __IOM uint32_t RESERVED03 : 2;            /*!< [7..6] DSP0 ICACHE TAG EMAW                                               */
18977       __IOM uint32_t RESERVED04 : 1;            /*!< [8..8] DSP0 ICACHE TAG RAWL                                               */
18978       __IOM uint32_t RESERVED05 : 2;            /*!< [10..9] DSP0 ICACHE TAG RAWLM                                             */
18979       __IOM uint32_t RESERVED06 : 1;            /*!< [11..11] DSP0 ICACHE TAG RAM WABL - Write Assist Enable (active
18980                                                      high)                                                                     */
18981       __IOM uint32_t RESERVED07 : 3;            /*!< [14..12] DSP0 ICACHE TAG WABLM - 00=No adjust 11=increased delay,
18982                                                      enabled by WABL                                                           */
18983             uint32_t            : 1;
18984       __IOM uint32_t RESERVED09 : 1;            /*!< [16..16] DSP0 ICACHE DATA RET1N value                                     */
18985       __IOM uint32_t RESERVED10 : 1;            /*!< [17..17] Override for DSP0 ICACHE DATA RET1N override enable              */
18986       __IOM uint32_t RESERVED11 : 3;            /*!< [20..18] DSP0 ICACHE DATA EMA                                             */
18987       __IOM uint32_t RESERVED12 : 1;            /*!< [21..21] DSP0 ICACHE DATA EMAS                                            */
18988       __IOM uint32_t RESERVED13 : 2;            /*!< [23..22] DSP0 ICACHE DATA EMAW                                            */
18989       __IOM uint32_t RESERVED14 : 1;            /*!< [24..24] DSP0 ICACHE DATA RAWL                                            */
18990       __IOM uint32_t RESERVED15 : 2;            /*!< [26..25] DSP0 ICACHE DATA RAWLM                                           */
18991       __IOM uint32_t RESERVED16 : 1;            /*!< [27..27] DSP0 ICACHE DATA RAM WABL - Write Assist Enable (active
18992                                                      high)                                                                     */
18993       __IOM uint32_t RESERVED17 : 3;            /*!< [30..28] DSP0 ICACHE DATA WABLM - 00=No adjust 11=increased
18994                                                      delay, enabled by WABL                                                    */
18995       __IOM uint32_t RESERVED18 : 1;            /*!< [31..31] Self-timed override (test mode only)                             */
18996     } USBPHYRESET_b;
18997   } ;
18998   __IM  uint32_t  RESERVED24[4];
18999 
19000   union {
19001     __IOM uint32_t AUDADCPWRCTRL;               /*!< (@ 0x0000042C) Audio ADC Power Control                                    */
19002 
19003     struct {
19004       __IOM uint32_t AUDADCPWRCTRLSWE : 1;      /*!< [0..0] Audio ADC Power Control Software Override Enable                   */
19005       __IOM uint32_t AUDADCAPSEN : 1;           /*!< [1..1] Enable the Global audio ADC Power Switch on when set
19006                                                      to 1 if the AUDADCPWRCTRLSWE bit is set.                                  */
19007       __IOM uint32_t AUDADCBPSEN : 1;           /*!< [2..2] Enable the Analog, IO and SAR Digital logic Power Switch
19008                                                      on when set to 1 if the AUDADCPWRCTRLSWE bit is set.                      */
19009       __IOM uint32_t AUDBGTPEN  : 1;            /*!< [3..3] Bandgap and Temperature Sensor Power Switch Enable                 */
19010       __IOM uint32_t AUDREFBUFPEN : 1;          /*!< [4..4] Reference Buffer Power Switch Enable                               */
19011       __IOM uint32_t AUDREFKEEPPEN : 1;         /*!< [5..5] Reference Buffer Keeper Power Switch Enable                        */
19012             uint32_t            : 2;
19013       __IOM uint32_t VDDAUDADCSARISOLATE : 1;   /*!< [8..8] ISOLATE signal for Power Switched SAR ( when AUDADCBPSEN
19014                                                      is switched off )                                                         */
19015       __IOM uint32_t VDDAUDADCDIGISOLATE : 1;   /*!< [9..9] ISOLATE signal for audio ADC Digital Contoller ( when
19016                                                      AUDADCAPSEN is switched off and if the AUDADCPWRCTRLSWE
19017                                                      bit is set)                                                               */
19018       __IOM uint32_t VDDAUDADCRESETN : 1;       /*!< [10..10] RESETN signal for Power Switched SAR and Digital Controller
19019                                                      (when global power switch is off and if the AUDADCPWRCTRLSWE
19020                                                      bit is set)                                                               */
19021             uint32_t            : 1;
19022       __IOM uint32_t AUDADCVBATDIVEN : 1;       /*!< [12..12] Audio ADC VBAT DIV Power Enable ( if the AUDADCPWRCTRLSWE
19023                                                      bit is set )                                                              */
19024             uint32_t            : 1;
19025       __IOM uint32_t AUDADCINBUFSEL : 2;        /*!< [15..14] Audio ADC input buffer mux select                                */
19026       __IOM uint32_t AUDADCINBUFEN : 1;         /*!< [16..16] Audio ADC Input Buffer Power Enable ( if the AUDADCPWRCTRLSWE
19027                                                      bit is set )                                                              */
19028       __IOM uint32_t AUDADCRFBUFSLWEN : 1;      /*!< [17..17] Audio ADC reference buffer slew enable                           */
19029       __IOM uint32_t AUDADCKEEPOUTEN : 1;       /*!< [18..18] Audio ADC reference keeper out en                                */
19030             uint32_t            : 13;
19031     } AUDADCPWRCTRL_b;
19032   } ;
19033 
19034   union {
19035     __IOM uint32_t AUDIO1;                      /*!< (@ 0x00000430) Audio trims 1                                              */
19036 
19037     struct {
19038             uint32_t            : 6;
19039       __IOM uint32_t MICBIASVOLTAGETRIM : 6;    /*!< [11..6] Output voltage trim                                               */
19040       __IOM uint32_t MICBIASPDNB : 1;           /*!< [12..12] Power down control for the block                                 */
19041             uint32_t            : 19;
19042     } AUDIO1_b;
19043   } ;
19044   __IM  uint32_t  RESERVED25;
19045 
19046   union {
19047     __IOM uint32_t PGAADCIFCTRL;                /*!< (@ 0x00000438) PGA ADCIF control                                          */
19048 
19049     struct {
19050       __IOM uint32_t PGAADCIFCHAACTIVE : 2;     /*!< [1..0] PGAADCIF active signal for channels A0 and A1. Starts
19051                                                      and stops 2 clocks after demultiplexed SOC signal.                        */
19052       __IOM uint32_t PGAADCIFCHAPDNB : 2;       /*!< [3..2] Power down for channels A0 and A1 (0 = powered down;
19053                                                      1 = standby)                                                              */
19054       __IOM uint32_t PGAADCIFCHBACTIVE : 2;     /*!< [5..4] PGAADCIF active signal for channels B0 and B1. Starts
19055                                                      and stops 2 clocks after demultiplexed SOC signal.                        */
19056       __IOM uint32_t PGAADCIFCHBPDNB : 2;       /*!< [7..6] Power down for channels B0 and B1 (0 = powered down;
19057                                                      1 = standby)                                                              */
19058             uint32_t            : 4;
19059       __IOM uint32_t PGAADCIFVCOMPEN : 1;       /*!< [12..12] Enable for VCOMP output                                          */
19060       __IOM uint32_t PGAADCIFVCOMPSEL : 2;      /*!< [14..13] Select for VCOMP output (0: A0, 1: A1, 2: B0, 3: B1)             */
19061             uint32_t            : 17;
19062     } PGAADCIFCTRL_b;
19063   } ;
19064 
19065   union {
19066     __IOM uint32_t PGACTRL1;                    /*!< (@ 0x0000043C) PGA control 1                                              */
19067 
19068     struct {
19069       __IOM uint32_t PGACHA0GAIN1SEL : 3;       /*!< [2..0] Channel A0 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
19070                                                      steps)                                                                    */
19071       __IOM uint32_t PGACHA0GAIN2DIV2SEL : 1;   /*!< [3..3] Channel A0 PGA divide by two select (0: 0 dB, 1: -6dB),
19072                                                      needed for fully differential inputs                                      */
19073       __IOM uint32_t PGACHA0GAIN2SEL : 5;       /*!< [8..4] Channel A0 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5 dB
19074                                                      steps)                                                                    */
19075       __IOM uint32_t PGACHA1GAIN1SEL : 3;       /*!< [11..9] Channel A1 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
19076                                                      steps)                                                                    */
19077       __IOM uint32_t PGACHA1GAIN2DIV2SEL : 1;   /*!< [12..12] Channel A1 PGA divide by two select (0: 0 dB, 1: -6dB),
19078                                                      needed for fully differential inputs                                      */
19079       __IOM uint32_t PGACHA1GAIN2SEL : 5;       /*!< [17..13] Channel A1 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5
19080                                                      dB steps)                                                                 */
19081       __IOM uint32_t PGACHABYPASSEN : 2;        /*!< [19..18] Bypass enable for Channels A0 and A1 (1: bypass, when
19082                                                      gain LT 12 dB; 0: otherwise)                                              */
19083       __IOM uint32_t PGACHAOPAMPINPDNB : 2;     /*!< [21..20] Channels A0 and A1 input stage opamp power down (0:
19084                                                      powered down, 1: powered up). Must be 1 when respective
19085                                                      PGACHABYPASSEN = 0.                                                       */
19086       __IOM uint32_t PGACHAOPAMPOUTPDNB : 2;    /*!< [23..22] Channels A0 and A1 output stage opamp power down (0:
19087                                                      powered down, 1: powered up)                                              */
19088       __IOM uint32_t PGACHAVCMGENPDNB : 1;      /*!< [24..24] Channel A VCMGEN power down (0: powered down, 1: powered
19089                                                      up)                                                                       */
19090       __IOM uint32_t PGACHAVCMGENQCHARGEEN : 1; /*!< [25..25] Channel A VCMGEN quick charge enable (pulsed during
19091                                                      channel powerup)                                                          */
19092       __IOM uint32_t PGAIREFGENPDNB : 1;        /*!< [26..26] IREFGEN power down (0: powered down, 1: powered up)              */
19093       __IOM uint32_t PGAVREFGENPDNB : 1;        /*!< [27..27] VREFGEN power down (0: powered down, 1: powered up)              */
19094       __IOM uint32_t PGAVREFGENQUICKSTARTEN : 1;/*!< [28..28] VREFGEN quick start enable (pulsed during startup)               */
19095       __IOM uint32_t VCOMPSELPGA : 1;           /*!< [29..29] Select for VCOMP output (0: A0, 1: A1, 2: B0, 3: B1)             */
19096             uint32_t            : 1;
19097       __IOM uint32_t PGAGAINAOVRD : 1;          /*!< [31..31] Apply BYPASS and GAIN bits from this register (for
19098                                                      channel A) instead of automatically via audio ADC. Note
19099                                                      that audio ADC FIFO meta data will not reflect dB gain
19100                                                      as used when configuring audio ADC.                                       */
19101     } PGACTRL1_b;
19102   } ;
19103 
19104   union {
19105     __IOM uint32_t PGACTRL2;                    /*!< (@ 0x00000440) PGA control 2                                              */
19106 
19107     struct {
19108       __IOM uint32_t PGACHB0GAIN1SEL : 3;       /*!< [2..0] Channel B0 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
19109                                                      steps)                                                                    */
19110       __IOM uint32_t PGACHB0GAIN2DIV2SEL : 1;   /*!< [3..3] Channel B0 PGA divide by two select (0: 0 dB, 1: -6dB),
19111                                                      needed for fully differential inputs                                      */
19112       __IOM uint32_t PGACHB0GAIN2SEL : 5;       /*!< [8..4] Channel B0 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5 dB
19113                                                      steps)                                                                    */
19114       __IOM uint32_t PGACHB1GAIN1SEL : 3;       /*!< [11..9] Channel B1 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
19115                                                      steps)                                                                    */
19116       __IOM uint32_t PGACHB1GAIN2DIV2SEL : 1;   /*!< [12..12] Channel B1 PGA divide by two select (0: 0 dB, 1: -6dB),
19117                                                      needed for fully differential inputs                                      */
19118       __IOM uint32_t PGACHB1GAIN2SEL : 5;       /*!< [17..13] Channel B1 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5
19119                                                      dB steps)                                                                 */
19120       __IOM uint32_t PGACHBBYPASSEN : 2;        /*!< [19..18] Bypass enable for Channels B0 and B1 (1: bypass, when
19121                                                      gain LT 12 dB; 0: otherwise)                                              */
19122       __IOM uint32_t PGACHBOPAMPINPDNB : 2;     /*!< [21..20] Channels B0 and B1 input stage opamp power down (0:
19123                                                      powered down, 1: powered up). Must be 1 when respective
19124                                                      PGACHBBYPASSEN = 0.                                                       */
19125       __IOM uint32_t PGACHBOPAMPOUTPDNB : 2;    /*!< [23..22] Channels B0 and B1 output stage opamp power down (0:
19126                                                      powered down, 1: powered up)                                              */
19127       __IOM uint32_t PGACHBVCMGENPDNB : 1;      /*!< [24..24] Channel B VCMGEN power down (0: powered down, 1: powered
19128                                                      up)                                                                       */
19129       __IOM uint32_t PGACHBVCMGENQCHARGEEN : 1; /*!< [25..25] Channel B VCMGEN quick charge enable (pulsed during
19130                                                      channel powerup)                                                          */
19131             uint32_t            : 5;
19132       __IOM uint32_t PGAGAINBOVRD : 1;          /*!< [31..31] Apply BYPASS and GAIN bits from this register (for
19133                                                      channel B) instead of automatically via audio ADC. Note
19134                                                      that audio ADC FIFO meta data will not reflect dB gain
19135                                                      as used when configuring audio ADC.                                       */
19136     } PGACTRL2_b;
19137   } ;
19138 
19139   union {
19140     __IOM uint32_t AUDADCPWRDLY;                /*!< (@ 0x00000444) Audio ADC Power Up Delay Control                           */
19141 
19142     struct {
19143       __IOM uint32_t AUDADCPWR0 : 8;            /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK
19144                                                      increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments
19145                                                      for ADC_CLKSEL = 0x2.                                                     */
19146       __IOM uint32_t AUDADCPWR1 : 8;            /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments
19147                                                      for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL
19148                                                      = 0x2.                                                                    */
19149             uint32_t            : 16;
19150     } AUDADCPWRDLY_b;
19151   } ;
19152   __IM  uint32_t  RESERVED26[2];
19153 
19154   union {
19155     __IOM uint32_t SDIOCTRL;                    /*!< (@ 0x00000450) SDIO/eMMC Control                                          */
19156 
19157     struct {
19158       __IOM uint32_t SDIOSYSCLKEN : 1;          /*!< [0..0] SDIO system clock enable.                                          */
19159       __IOM uint32_t SDIOXINCLKEN : 1;          /*!< [1..1] SDIO serial clock source enable.                                   */
19160       __IOM uint32_t SDIOITAPCHGWIN : 1;        /*!< [2..2] This is used to gate the output of the Tap Delay lines
19161                                                      so as to avoid glithches being propagated into the Core.
19162                                                      This signal should be asserted few clocks before the itapdlysel
19163                                                      changes and should be asserted for few clocks after.                      */
19164       __IOM uint32_t SDIOITAPDLYENA : 1;        /*!< [3..3] Used to enable selective Tap delay line on the Looped
19165                                                      back SD Clock (rxclk_in). This signal along with the itapdlysel[4:0]
19166                                                      selects the the amount of delay to be inserted on the line.
19167                                                      When Tuning is enabled (for SDR104 and optionally for SDR50),
19168                                                      this signal is ignored and internalcontrols are used instead.
19169                                                      This should not be asserted when operating in DS mode.                    */
19170       __IOM uint32_t SDIOITAPDLYSEL : 5;        /*!< [8..4] Selects one of the 32 Taps on the rxclk_in line. This
19171                                                      is effective only when itapdlyena is asserted and Tuning
19172                                                      is not enabled.                                                           */
19173       __IOM uint32_t SDIOOTAPDLYENA : 1;        /*!< [9..9] Used to enable the selective Tap delay on the sdcard_clk
19174                                                      so as to generate the delayed sdcard_clk. This is used
19175                                                      to latch the CMD/DAT outputs to generate delay on them
19176                                                      w.r.t CLK going out. This signal along with otapdlysel[3:0]
19177                                                      selects the amount of delay to be inserted on the Clock
19178                                                      line. This signal should not be asserted when operating
19179                                                      in DS mode.                                                               */
19180       __IOM uint32_t SDIOOTAPDLYSEL : 4;        /*!< [13..10] Selects one of the 16 Taps on the sdcard_clk. This
19181                                                      is effective only when otapdlyena is asserted.                            */
19182       __IOM uint32_t SDIOASYNCWKUPENA : 1;      /*!< [14..14] SDIO asynchronous wakeup mode. 0: Synchronous wakeup
19183                                                      mode, 1: Asynchronous wakeup mode                                         */
19184       __IOM uint32_t SDIOXINCLKSEL : 2;         /*!< [16..15] Select clock source for SDIO xin_clk.                            */
19185       __IOM uint32_t SDIOCMDOPENDRAINEN : 1;    /*!< [17..17] SDIO CMD line configured as open-drian. 0: Push-pull
19186                                                      mode, 1: Open-drain mode                                                  */
19187       __IOM uint32_t SDIODATOPENDRAINEN : 1;    /*!< [18..18] SDIO DAT line configured as open-drian. 0: Push-pull
19188                                                      mode, 1: Open-drain mode                                                  */
19189             uint32_t            : 13;
19190     } SDIOCTRL_b;
19191   } ;
19192 
19193   union {
19194     __IOM uint32_t PDMCTRL;                     /*!< (@ 0x00000454) PDM Control                                                */
19195 
19196     struct {
19197       __IOM uint32_t PDMGLOBALEN : 1;           /*!< [0..0] PDM global enable to allow all PDMs to have synchronized
19198                                                      interface clocks and FIFO sampling.                                       */
19199             uint32_t            : 31;
19200     } PDMCTRL_b;
19201   } ;
19202 } MCUCTRL_Type;                                 /*!< Size = 1112 (0x458)                                                       */
19203 
19204 
19205 
19206 /* =========================================================================================================================== */
19207 /* ================                                           MSPI0                                           ================ */
19208 /* =========================================================================================================================== */
19209 
19210 
19211 /**
19212   * @brief Multi-bit SPI Master (MSPI0)
19213   */
19214 
19215 typedef struct {                                /*!< (@ 0x40060000) MSPI0 Structure                                            */
19216 
19217   union {
19218     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) This register is used to enable individual PIO
19219                                                                     based transactions to a device on the bus.
19220                                                                     The CFG register must be programmed properly
19221                                                                     for the transfer, and the ADDR and INSTR
19222                                                                     registers should be programmed if the SENDI
19223                                                                     and SENDA fields are enabled.                              */
19224 
19225     struct {
19226       __IOM uint32_t START      : 1;            /*!< [0..0] Write to 1 to initiate a PIO transaction on the bus (typically
19227                                                      the entire register should be written at once with this
19228                                                      bit set).                                                                 */
19229       __IOM uint32_t STATUS     : 1;            /*!< [1..1] Command status: 1 indicates command has completed. Cleared
19230                                                      by writing 1 to this bit or starting a new transfer.                      */
19231       __IOM uint32_t BUSY       : 1;            /*!< [2..2] Command status: 1 indicates controller is busy (command
19232                                                      in progress)                                                              */
19233             uint32_t            : 1;
19234       __IOM uint32_t PIODEV     : 1;            /*!< [4..4] Selects the Device configutation to use for PIO requests           */
19235       __IOM uint32_t SENDA      : 1;            /*!< [5..5] Indicates whether an address phase should be sent (see
19236                                                      ADDR register and ASIZE field in CFG register)                            */
19237       __IOM uint32_t SENDI      : 1;            /*!< [6..6] Indicates whether an instruction phase should be sent
19238                                                      (see INSTR field and ISIZE field in CFG register)                         */
19239       __IOM uint32_t TXRX       : 1;            /*!< [7..7] 1 Indicates a TX operation, 0 indicates an RX operation
19240                                                      of XFERBYTES                                                              */
19241       __IOM uint32_t BIGENDIAN  : 1;            /*!< [8..8] 1 indicates data in FIFO is in big endian format (MSB
19242                                                      first); 0 indicates little endian data (default, LSB first).              */
19243       __IOM uint32_t PIOSCRAMBLE : 1;           /*!< [9..9] Enables data scrambling for PIO opertions. This should
19244                                                      only be used for data operations and never for commands
19245                                                      to a device.                                                              */
19246       __IOM uint32_t ENTURN     : 1;            /*!< [10..10] Indicates whether TX->RX turnaround cycles should be
19247                                                      enabled for this operation (see TURNAROUND field in CFG
19248                                                      register).                                                                */
19249       __IOM uint32_t ENDCX      : 1;            /*!< [11..11] Enable DCX signal on data [1]                                    */
19250       __IOM uint32_t ENWLAT     : 1;            /*!< [12..12] Enable Write Latency Counter (time between address
19251                                                      and first data byte). Counter value is WRITELATENCY.                      */
19252             uint32_t            : 3;
19253       __IOM uint32_t XFERBYTES  : 16;           /*!< [31..16] Number of bytes to transmit or receive (based on TXRX
19254                                                      bit)                                                                      */
19255     } CTRL_b;
19256   } ;
19257 
19258   union {
19259     __IOM uint32_t CTRL1;                       /*!< (@ 0x00000004) These registers are used to enable individual
19260                                                                     PIO based transactions to a device on the
19261                                                                     bus. The CFG register must be programmed
19262                                                                     properly for the transfer, and the ADDR
19263                                                                     and INSTR registers should be programmed
19264                                                                     if the SENDI and SENDA fields are enabled.                 */
19265 
19266     struct {
19267       __IOM uint32_t PIOMIXED   : 4;            /*!< [3..0] Provides override controls for data operations where
19268                                                      instruction, address, and data may transfer in different
19269                                                      rates.                                                                    */
19270             uint32_t            : 28;
19271     } CTRL1_b;
19272   } ;
19273 
19274   union {
19275     __IOM uint32_t ADDR;                        /*!< (@ 0x00000008) Optional Address field to send for PIO transfers           */
19276 
19277     struct {
19278       __IOM uint32_t ADDR       : 32;           /*!< [31..0] Optional Address field to send (after optional instruction
19279                                                      field) - qualified by ASIZE in CMD register. NOTE: This
19280                                                      register is aliased to DMADEVADDR.                                        */
19281     } ADDR_b;
19282   } ;
19283 
19284   union {
19285     __IOM uint32_t INSTR;                       /*!< (@ 0x0000000C) Optional Instruction field to send for PIO transfers       */
19286 
19287     struct {
19288       __IOM uint32_t INSTR      : 16;           /*!< [15..0] Optional Instruction field to send (1st byte) - qualified
19289                                                      by ISEND/ISIZE                                                            */
19290             uint32_t            : 16;
19291     } INSTR_b;
19292   } ;
19293 
19294   union {
19295     __IOM uint32_t TXFIFO;                      /*!< (@ 0x00000010) TX Data FIFO                                               */
19296 
19297     struct {
19298       __IOM uint32_t TXFIFO     : 32;           /*!< [31..0] Data to be transmitted. Data should normally be aligned
19299                                                      to the LSB (pad the upper bits with zeros) unless BIGENDIAN
19300                                                      is set.                                                                   */
19301     } TXFIFO_b;
19302   } ;
19303 
19304   union {
19305     __IOM uint32_t RXFIFO;                      /*!< (@ 0x00000014) RX Data FIFO                                               */
19306 
19307     struct {
19308       __IOM uint32_t RXFIFO     : 32;           /*!< [31..0] Receive data. Data is aligned to the LSB (padded zeros
19309                                                      on upper bits) unless BIGENDIAN is set.                                   */
19310     } RXFIFO_b;
19311   } ;
19312 
19313   union {
19314     __IOM uint32_t TXENTRIES;                   /*!< (@ 0x00000018) Number of words in TX FIFO                                 */
19315 
19316     struct {
19317       __IOM uint32_t TXENTRIES  : 6;            /*!< [5..0] Number of 32-bit words/entries in TX FIFO                          */
19318             uint32_t            : 26;
19319     } TXENTRIES_b;
19320   } ;
19321 
19322   union {
19323     __IOM uint32_t RXENTRIES;                   /*!< (@ 0x0000001C) Number of words in RX FIFO                                 */
19324 
19325     struct {
19326       __IOM uint32_t RXENTRIES  : 6;            /*!< [5..0] Number of 32-bit words/entries in RX FIFO                          */
19327             uint32_t            : 26;
19328     } RXENTRIES_b;
19329   } ;
19330 
19331   union {
19332     __IOM uint32_t THRESHOLD;                   /*!< (@ 0x00000020) Threshold levels that trigger RXFull and TXEmpty
19333                                                                     interrupts                                                 */
19334 
19335     struct {
19336       __IOM uint32_t TXTHRESH   : 6;            /*!< [5..0] Number of entries in TX FIFO that cause TXF interrupt              */
19337             uint32_t            : 2;
19338       __IOM uint32_t RXTHRESH   : 6;            /*!< [13..8] Number of entries in TX FIFO that cause RXE interrupt             */
19339             uint32_t            : 18;
19340     } THRESHOLD_b;
19341   } ;
19342   __IM  uint32_t  RESERVED[3];
19343 
19344   union {
19345     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000030) Timing configuration bits for the MSPI module.
19346                                                                     PRSTN, IPRSTN, and FIFORESET can be used
19347                                                                     to reset portions of the MSPI interface
19348                                                                     in order to clear error conditions. The
19349                                                                     remaining bits control clock frequency and
19350                                                                     TX/RX capture timings.                                     */
19351 
19352     struct {
19353       __IOM uint32_t APBCLK     : 1;            /*!< [0..0] Enable continuous APB clock. For power-efficient operation,
19354                                                      APBCLK should be set to 0.                                                */
19355             uint32_t            : 3;
19356       __IOM uint32_t IOMSEL     : 4;            /*!< [7..4] Selects which IOM is selected for CQ handshake status.             */
19357             uint32_t            : 21;
19358       __IOM uint32_t FIFORESET  : 1;            /*!< [29..29] Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal
19359                                                      operation. May be used to manually flush the FIFO in error
19360                                                      handling.                                                                 */
19361       __IOM uint32_t IPRSTN     : 1;            /*!< [30..30] IP block reset. Write to 0 to put the transfer module
19362                                                      in reset or 1 for normal operation. This may be required
19363                                                      after error conditions to clear the transfer on the bus.                  */
19364       __IOM uint32_t PRSTN      : 1;            /*!< [31..31] Peripheral reset. Master reset to the entire MSPI module
19365                                                      (DMA, XIP, and transfer state machines). 1=normal operation,
19366                                                      0=in reset.                                                               */
19367     } MSPICFG_b;
19368   } ;
19369   __IM  uint32_t  RESERVED1[4];
19370 
19371   union {
19372     __IOM uint32_t PADOUTEN;                    /*!< (@ 0x00000044) Enable bits for the MSPI output pads. Each active
19373                                                                     MSPI line should be set to 1 in the OUTEN
19374                                                                     field below.                                               */
19375 
19376     struct {
19377       __IOM uint32_t OUTEN      : 20;           /*!< [19..0] Output pad enable configuration. Indicates which pads
19378                                                      should be driven. Bits [3:0] are Quad0 data. Bits [7:4]
19379                                                      are Quad1 data. Bit [8] is clock. Bit [9] is BM/DQS. Bit
19380                                                      [10:17] are data for 16-bit. Bit[18] is BM/DQS for 16-bit.
19381                                                      Bit[19] is not used.                                                      */
19382             uint32_t            : 10;
19383       __IOM uint32_t PADSET1    : 1;            /*!< [30..30] Only applicable on mspi1. When set, use gpio95 .. gpio
19384                                                      104 as the pads. This extra set of pads is to run mspi0
19385                                                      on HEX and mspi1 concurrently. Note that the timing of
19386                                                      this extra pads may not be as good as the origianl pads.                  */
19387       __IOM uint32_t CLKOND4    : 1;            /*!< [31..31] Output clock on MSPI data[4]                                     */
19388     } PADOUTEN_b;
19389   } ;
19390 
19391   union {
19392     __IOM uint32_t PADOVEREN;                   /*!< (@ 0x00000048) Enables PIO-like pad override control                      */
19393 
19394     struct {
19395       __IOM uint32_t OVERRIDEEN : 20;           /*!< [19..0] Output pad override enable. Bit mask for pad outputs.
19396                                                      When set to 1, the values in the OVERRIDE field are driven
19397                                                      on the pad (output enable is implicitly set in this mode).
19398                                                      [7:0]=data [8]=clock [9]=DM                                               */
19399             uint32_t            : 12;
19400     } PADOVEREN_b;
19401   } ;
19402 
19403   union {
19404     __IOM uint32_t PADOVER;                     /*!< (@ 0x0000004C) Override data value                                        */
19405 
19406     struct {
19407       __IOM uint32_t OVERRIDE   : 20;           /*!< [19..0] Output pad override value. [7:0]=data [8]=clock [9]=DM            */
19408             uint32_t            : 12;
19409     } PADOVER_b;
19410   } ;
19411   __IM  uint32_t  RESERVED2[12];
19412 
19413   union {
19414     __IOM uint32_t DEV0AXI;                     /*!< (@ 0x00000080) Specifies the base address and aperture range
19415                                                                     of the device as mapped onto the AXI bus                   */
19416 
19417     struct {
19418       __IOM uint32_t SIZE0      : 4;            /*!< [3..0] Indicates the AXI aperture size                                    */
19419       __IOM uint32_t READONLY0  : 1;            /*!< [4..4] Indicates the AXI aperture is read-only                            */
19420             uint32_t            : 11;
19421       __IOM uint32_t BASE0      : 10;           /*!< [25..16] XIPEN has to be enabled to enable aperture. The BASE
19422                                                      address needs to be SIZE aligned.                                         */
19423             uint32_t            : 6;
19424     } DEV0AXI_b;
19425   } ;
19426 
19427   union {
19428     __IOM uint32_t DEV0CFG;                     /*!< (@ 0x00000084) Command formatting for PIO based transactions
19429                                                                     (initiated by writes to CTRL register)                     */
19430 
19431     struct {
19432       __IOM uint32_t DEVCFG0    : 5;            /*!< [4..0] Flash configuration for XIP and AUTO DMA operations.
19433                                                      Controls value for SER (Slave Enable) for XIP operations
19434                                                      and address generation for DMA/XIP modes. Also used to
19435                                                      configure SPIFRF (frame format).                                          */
19436       __IOM uint32_t ASIZE0     : 2;            /*!< [6..5] Address Size. Address bytes to send from ADDR register             */
19437       __IOM uint32_t ISIZE0     : 1;            /*!< [7..7] Instruction Size                                                   */
19438       __IOM uint32_t TURNAROUND0 : 6;           /*!< [13..8] Number of turnaound cycles (for TX->RX transitions).
19439                                                      Qualified by ENTURN bit field.                                            */
19440       __IOM uint32_t CPHA0      : 1;            /*!< [14..14] Serial clock phase.                                              */
19441       __IOM uint32_t CPOL0      : 1;            /*!< [15..15] Serial clock polarity.                                           */
19442       __IOM uint32_t CLKDIV0    : 6;            /*!< [21..16] Clock Divider. Allows dividing 96 MHz base clock by
19443                                                      integer multiples. Enumerations are provided for common
19444                                                      frequency, but any integer divide from 96 MHz is allowed.
19445                                                      Odd divide ratios will result in a 33/66 percent duty cycle
19446                                                      with a long low clock pulse (to allow longer round-trip
19447                                                      for read data).                                                           */
19448       __IOM uint32_t RXCAP0     : 1;            /*!< [22..22] Controls RX data capture phase. A setting of 0 (NORMAL)
19449                                                      captures read data at the normal capture point relative
19450                                                      to the internal clock launch point. However, to accomodate
19451                                                      chip/pad/board delays, a setting of RXCAP of 1 is expected
19452                                                      to be used to align the capture point with the return data
19453                                                      window. This bit is used in conjunction with RXNEG to provide
19454                                                      4 unique capture points, all about 10ns apart.                            */
19455       __IOM uint32_t RXNEG0     : 1;            /*!< [23..23] Adjusts the RX capture phase to the negedge of the
19456                                                      48MHz internal clock (~10ns early). For normal operation,
19457                                                      it is expected that RXNEG will be set to 0.                               */
19458       __IOM uint32_t TXNEG0     : 1;            /*!< [24..24] Launches TX data a half clock cycle (~10ns) early.
19459                                                      This should normally be programmed to zero (NORMAL).                      */
19460       __IOM uint32_t SEPIO0     : 1;            /*!< [25..25] Separate IO configuration. This bit should be set when
19461                                                      the target device has separate MOSI and MISO pins. Respective
19462                                                      IN/OUT bits below should be set to map pins.                              */
19463       __IOM uint32_t WRITELATENCY0 : 6;         /*!< [31..26] Number of write Latency cycles. Qualified by ENTURN
19464                                                      bit field.                                                                */
19465     } DEV0CFG_b;
19466   } ;
19467 
19468   union {
19469     __IOM uint32_t DEV0DDR;                     /*!< (@ 0x00000088) Timing configuration bits for DDR operation of
19470                                                                     the MSPI module.                                           */
19471 
19472     struct {
19473       __IOM uint32_t EMULATEDDR0 : 1;           /*!< [0..0] Drive external clock at 1/2 rate to emulate DDR mode               */
19474       __IOM uint32_t QUADDDR0   : 1;            /*!< [1..1] Deprecated. No effect on RevC.                                     */
19475       __IOM uint32_t ENABLEDQS0 : 1;            /*!< [2..2] In EMULATEDDR mode, enable DQS for read capture                    */
19476       __IOM uint32_t DQSSYNCNEG0 : 1;           /*!< [3..3] Use negative edge of clock for DDR data sync                       */
19477       __IOM uint32_t ENABLEFINEDELAY0 : 1;      /*!< [4..4] Enables use of delay line to provide fine control over
19478                                                      traditional RX capture clock.                                             */
19479       __IOM uint32_t TXDQSDELAY0 : 5;           /*!< [9..5] This acts as an offset to the computed value (should
19480                                                      be set to 0 by default)                                                   */
19481       __IOM uint32_t RXDQSDELAY0 : 5;           /*!< [14..10] This acts as an offset to the computed value (should
19482                                                      be set to 0 by default)                                                   */
19483       __IOM uint32_t RXDQSDELAYNEG0 : 5;        /*!< [19..15] This acts as an offset to the computed value (should
19484                                                      be set to 0 by default) of falling edge.                                  */
19485       __IOM uint32_t RXDQSDELAYNEGEN0 : 1;      /*!< [20..20] When 1, RXDQSDELAYNEG is used for falling edge of the
19486                                                      clock.                                                                    */
19487       __IOM uint32_t RXDQSDELAYHI0 : 5;         /*!< [25..21] This acts as an offset to the computed value (should
19488                                                      be set to 0 by default) for 2nd DQS on HEX mode.                          */
19489       __IOM uint32_t RXDQSDELAYNEGHI0 : 5;      /*!< [30..26] This acts as an offset to the computed value (should
19490                                                      be set to 0 by default) of falling edge for 2nd DQS on
19491                                                      HEX mode.                                                                 */
19492       __IOM uint32_t RXDQSDELAYHIEN0 : 1;       /*!< [31..31] When 1, RXDQSDELAYHI and RXDQSDELAYNEGHI is used for
19493                                                      falling edge of the clock.                                                */
19494     } DEV0DDR_b;
19495   } ;
19496 
19497   union {
19498     __IOM uint32_t DEV0CFG1;                    /*!< (@ 0x0000008C) Timing and mode configuration bits for the MSPI
19499                                                                     module.                                                    */
19500 
19501     struct {
19502       __IOM uint32_t SFTURN0    : 4;            /*!< [3..0] Subtract from internal counter of write latency and turnaround     */
19503       __IOM uint32_t RXCAPEXT0  : 1;            /*!< [4..4] Specify the number of apb_clk of RX capture phse {RXCAPEXT,
19504                                                      RXCAP}                                                                    */
19505       __IOM uint32_t SCLKRXHALT0 : 1;           /*!< [5..5] Halt sclk based on xfer_count                                      */
19506             uint32_t            : 1;
19507       __IOM uint32_t WBX0       : 1;            /*!< [7..7] Enable the support of WBX ( page boundary crossing on
19508                                                      write )                                                                   */
19509       __IOM uint32_t RBX0       : 1;            /*!< [8..8] Enable the support of RBX ( page boundary crossing on
19510                                                      read )                                                                    */
19511       __IOM uint32_t RXSMP0     : 2;            /*!< [10..9] Sampling edge based on sclk edge. No effect when div1             */
19512       __IOM uint32_t HYPERIO0   : 1;            /*!< [11..11] When using Windbond, set this bit to 1 to generate
19513                                                      CA[47:0] in hardware.                                                     */
19514       __IOM uint32_t TAFOURTH0  : 1;            /*!< [12..12] Add 1/4th mspi_clk in DDR to turnaround. Recommended
19515                                                      set this to 1 when EMULATEDDR is set in non-DQS mode (ENABLEDQS
19516                                                      = 0).                                                                     */
19517       __IOM uint32_t RXHI0      : 1;            /*!< [13..13] Force st_rx to start at clock high of mspi_clk                   */
19518       __IOM uint32_t DQSTURN0   : 3;            /*!< [16..14] In DQS mode, the internal cycle count to enable DQS
19519                                                      path.                                                                     */
19520             uint32_t            : 15;
19521     } DEV0CFG1_b;
19522   } ;
19523 
19524   union {
19525     __IOM uint32_t DEV0XIP;                     /*!< (@ 0x00000090) When any SPI flash is configured, this register
19526                                                                     must be properly programmed before XIP or
19527                                                                     AUTO DMA operations commence.                              */
19528 
19529     struct {
19530       __IOM uint32_t XIPEN0     : 1;            /*!< [0..0] Enable the XIP (eXecute In Place) function which effectively
19531                                                      enables the address decoding of the MSPI device in the
19532                                                      flash/cache address space at address 0x04000000-0x07FFFFFF.               */
19533             uint32_t            : 1;
19534       __IOM uint32_t XIPACK0    : 2;            /*!< [3..2] Controls transmission of Micron XIP acknowledge cycles
19535                                                      (Micron Flash devices only)                                               */
19536       __IOM uint32_t XIPBIGENDIAN0 : 1;         /*!< [4..4] Indicates whether XIP/AUTO DMA data transfers are in
19537                                                      big or little endian format                                               */
19538       __IOM uint32_t XIPENTURN0 : 1;            /*!< [5..5] Indicates whether XIP/AUTO DMA operations should enable
19539                                                      TX->RX turnaround cycles                                                  */
19540       __IOM uint32_t XIPSENDA0  : 1;            /*!< [6..6] Indicates whether XIP/AUTO DMA operations should send
19541                                                      an an address phase (see DMADEVADDR register and ASIZE
19542                                                      field in CFG)                                                             */
19543       __IOM uint32_t XIPSENDI0  : 1;            /*!< [7..7] Indicates whether XIP/AUTO DMA operations should send
19544                                                      an instruction (see READINSTR field and ISIZE field in
19545                                                      CFG)                                                                      */
19546       __IOM uint32_t XIPMIXED0  : 4;            /*!< [11..8] Provides override controls for data operations where
19547                                                      instruction, address, and data may transfer in different
19548                                                      rates.                                                                    */
19549       __IOM uint32_t XIPENDCX0  : 1;            /*!< [12..12] Enable DCX signal on data [1] for XIP/DMA operations             */
19550       __IOM uint32_t XIPENWLAT0 : 1;            /*!< [13..13] Enable Write Latency counter for XIP write transactions          */
19551       __IOM uint32_t XIPTURNAROUND0 : 6;        /*!< [19..14] Number of turnaound cycles (for TX->RX transitions).
19552                                                      Qualified by XIPENTURN bit field.                                         */
19553       __IOM uint32_t XIPWRITELATENCY0 : 6;      /*!< [25..20] Number of write Latency cycles. Qualified by XIPENWLAT
19554                                                      bit field.                                                                */
19555             uint32_t            : 6;
19556     } DEV0XIP_b;
19557   } ;
19558 
19559   union {
19560     __IOM uint32_t DEV0INSTR;                   /*!< (@ 0x00000094) When any SPI flash is configured, this register
19561                                                                     must be properly programmed before XIP or
19562                                                                     AUTO DMA operations commence.                              */
19563 
19564     struct {
19565       __IOM uint32_t WRITEINSTR0 : 16;          /*!< [15..0] Write command sent for DMA operations                             */
19566       __IOM uint32_t READINSTR0 : 16;           /*!< [31..16] Read command sent to flash for DMA/XIP operations                */
19567     } DEV0INSTR_b;
19568   } ;
19569 
19570   union {
19571     __IOM uint32_t DEV0BOUNDARY;                /*!< (@ 0x00000098) Allows large transfers to be broken up into smaller
19572                                                                     ones in hardware to accommodate needs of
19573                                                                     external devices and allow XIP/XIPMM. Only
19574                                                                     applicable for memory-mapped devices (PSRAM,
19575                                                                     Flash, etc) where address can be retransmitted
19576                                                                     without side effects.                                      */
19577 
19578     struct {
19579       __IOM uint32_t DMATIMELIMIT0 : 12;        /*!< [11..0] DMA time limit. Can be used to limit the transaction
19580                                                      time on the MSPI bus. The count is in ~100 ns increments
19581                                                      for the 96 MHz clock input. A value of 0 disables the counter.            */
19582       __IOM uint32_t DMABOUND0  : 4;            /*!< [15..12] DMA Address boundary                                             */
19583             uint32_t            : 16;
19584     } DEV0BOUNDARY_b;
19585   } ;
19586 
19587   union {
19588     __IOM uint32_t DEV0SCRAMBLING;              /*!< (@ 0x0000009C) Enables data scrambling for the specified range
19589                                                                     external flash addresses. Scrambling does
19590                                                                     not impact flash access performance.                       */
19591 
19592     struct {
19593       __IOM uint32_t SCRSTART0  : 10;           /*!< [9..0] Scrambling region start address [25:16] (64K block granularity).
19594                                                      The START block is the FIRST block included in the scrambled
19595                                                      address range.                                                            */
19596             uint32_t            : 6;
19597       __IOM uint32_t SCREND0    : 10;           /*!< [25..16] Scrambling region end address [25:16] (64K block granularity).
19598                                                      The END block is the LAST block included in the scrambled
19599                                                      address range.                                                            */
19600             uint32_t            : 5;
19601       __IOM uint32_t SCRENABLE0 : 1;            /*!< [31..31] Enables Data Scrambling Region. When 1 reads and writes
19602                                                      to the range will be scrambled. When 0, data will be read/written
19603                                                      unmodified. Address range is specified in 64K granularity
19604                                                      and the START/END ranges are included within the range.                   */
19605     } DEV0SCRAMBLING_b;
19606   } ;
19607 
19608   union {
19609     __IOM uint32_t DEV0XIPMISC;                 /*!< (@ 0x000000A0) Miscellaneous XIP control registers for AXI logic          */
19610 
19611     struct {
19612       __IOM uint32_t CEBREAK0   : 12;           /*!< [11..0] CEBREAK0 field description needed.                                */
19613       __IOM uint32_t XIPODD0    : 1;            /*!< [12..12] Convert odd starting address to word-aligned starting
19614                                                      address with byte-enables for holes. For example, an AXI
19615                                                      transaction with wstrb of 0x0600 results in mspi transaction
19616                                                      of addr=8 and BE=0b1001 ( active low ).                                   */
19617       __IOM uint32_t BEPOL0     : 1;            /*!< [13..13] byte mask polarity to MSPI xfer                                  */
19618       __IOM uint32_t BEON0      : 1;            /*!< [14..14] Byte enable always on for all lanes                              */
19619       __IOM uint32_t XIPBOUNDARY0 : 1;          /*!< [15..15] Deprecated. No effect on RevC.                                   */
19620             uint32_t            : 5;
19621       __IOM uint32_t APNDODD0   : 1;            /*!< [21..21] Append dummy byte to odd number of write                         */
19622             uint32_t            : 10;
19623     } DEV0XIPMISC_b;
19624   } ;
19625   __IM  uint32_t  RESERVED3[23];
19626 
19627   union {
19628     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000100) DMA Configuration                                          */
19629 
19630     struct {
19631       __IOM uint32_t DMAEN      : 2;            /*!< [1..0] DMA Enable. Setting this bit to EN will start the DMA
19632                                                      operation                                                                 */
19633       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
19634       __IOM uint32_t DMADEV     : 1;            /*!< [3..3] DMA Device Select                                                  */
19635       __IOM uint32_t DMAPRI     : 2;            /*!< [5..4] Sets the Priority of the DMA request                               */
19636             uint32_t            : 11;
19637       __IOM uint32_t DMATXEMPT  : 1;            /*!< [17..17] For DMA_M2P, only start when DMA fifo is not empty.              */
19638       __IOM uint32_t DMAPWROFF  : 1;            /*!< [18..18] Power off MSPI domain upon completion of DMA operation.          */
19639             uint32_t            : 13;
19640     } DMACFG_b;
19641   } ;
19642 
19643   union {
19644     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000104) DMA Status                                                 */
19645 
19646     struct {
19647       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
19648                                                      a DMA transfer is active. The DMA transfer may be waiting
19649                                                      on data, transferring data, or waiting for priority. All
19650                                                      of these will be indicated with a 1. A 0 will indicate
19651                                                      that the DMA is fully complete and no further transactions
19652                                                      will be done.                                                             */
19653       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
19654                                                      operation.                                                                */
19655       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals that an error
19656                                                      was encountered during the DMA operation.                                 */
19657       __IOM uint32_t SCRERR     : 1;            /*!< [3..3] Scrambling Access Alignment Error. This active high bit
19658                                                      signals that a scrambling operation was specified for a
19659                                                      non-word aligned DEVADDR.                                                 */
19660             uint32_t            : 28;
19661     } DMASTAT_b;
19662   } ;
19663 
19664   union {
19665     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000108) DMA Target Address                                         */
19666 
19667     struct {
19668       __IOM uint32_t TARGADDR   : 32;           /*!< [31..0] Target byte address for source of DMA (either read or
19669                                                      write). In cases of non-word aligned addresses, the DMA
19670                                                      logic will take care for ensuring only the target bytes
19671                                                      are read/written.                                                         */
19672     } DMATARGADDR_b;
19673   } ;
19674 
19675   union {
19676     __IOM uint32_t DMADEVADDR;                  /*!< (@ 0x0000010C) DMA Device Address                                         */
19677 
19678     struct {
19679       __IOM uint32_t DEVADDR    : 32;           /*!< [31..0] SPI Device address for automated DMA transactions (both
19680                                                      read and write).                                                          */
19681     } DMADEVADDR_b;
19682   } ;
19683 
19684   union {
19685     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000110) DMA Total Transfer Count                                   */
19686 
19687     struct {
19688       __IOM uint32_t TOTCOUNT   : 24;           /*!< [23..0] Total Transfer Count in bytes.                                    */
19689             uint32_t            : 8;
19690     } DMATOTCOUNT_b;
19691   } ;
19692 
19693   union {
19694     __IOM uint32_t DMABCOUNT;                   /*!< (@ 0x00000114) DMA BYTE Transfer Count                                    */
19695 
19696     struct {
19697       __IOM uint32_t BCOUNT     : 8;            /*!< [7..0] Burst transfer size in bytes. This is the number of bytes
19698                                                      transferred when a FIFO trigger event occurs. Recommended
19699                                                      value is 32.                                                              */
19700             uint32_t            : 24;
19701     } DMABCOUNT_b;
19702   } ;
19703 
19704   union {
19705     __IOM uint32_t DMATHRESH;                   /*!< (@ 0x00000118) Indicates FIFO level at which a DMA should be
19706                                                                     triggered. For most configurations, a setting
19707                                                                     of 8 is recommended for both read and write
19708                                                                     operations.                                                */
19709 
19710     struct {
19711       __IOM uint32_t DMATXTHRESH : 5;           /*!< [4..0] DMA transfer FIFO level trigger. For read operations,
19712                                                      DMA is triggered when the FIFO level is greater than this
19713                                                      value. For write operations, DMA is triggered when the
19714                                                      FIFO level is less than this level. Each DMA operation
19715                                                      will consist of BCOUNT bytes.                                             */
19716             uint32_t            : 3;
19717       __IOM uint32_t DMARXTHRESH : 5;           /*!< [12..8] DMA transfer FIFO level trigger. For read operations,
19718                                                      DMA is triggered when the FIFO level is greater than this
19719                                                      value. For write operations, DMA is triggered when the
19720                                                      FIFO level is less than this level. Each DMA operation
19721                                                      will consist of BCOUNT bytes. This value should not be
19722                                                      set more than ALTRXFIFOFULL.                                              */
19723             uint32_t            : 19;
19724     } DMATHRESH_b;
19725   } ;
19726   __IM  uint32_t  RESERVED4[57];
19727 
19728   union {
19729     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
19730                                                                     to generate the corresponding interrupt.                   */
19731 
19732     struct {
19733       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
19734                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
19735       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
19736       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
19737                                                      a full FIFO).                                                             */
19738       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
19739                                                      an empty FIFO)                                                            */
19740       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
19741                                                      MSPI bus pins will stall)                                                 */
19742       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
19743       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
19744       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
19745       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
19746       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
19747                                                      performs an operation where address bit[0] is set. Useful
19748                                                      for triggering CURIDX interrupts.                                         */
19749       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
19750       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
19751       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
19752                                                      be aligned to word (4-byte) start address.                                */
19753       __IOM uint32_t APBDMAERR  : 1;            /*!< [13..13] MSPI is dma target as well as dma source, which may
19754                                                      result in deadlock.                                                       */
19755             uint32_t            : 18;
19756     } INTEN_b;
19757   } ;
19758 
19759   union {
19760     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
19761                                                                     cause of a recent interrupt.                               */
19762 
19763     struct {
19764       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
19765                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
19766       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
19767       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
19768                                                      a full FIFO).                                                             */
19769       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
19770                                                      an empty FIFO)                                                            */
19771       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
19772                                                      MSPI bus pins will stall)                                                 */
19773       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
19774       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
19775       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
19776       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
19777       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
19778                                                      performs an operation where address bit[0] is set. Useful
19779                                                      for triggering CURIDX interrupts.                                         */
19780       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
19781       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
19782       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
19783                                                      be aligned to word (4-byte) start address.                                */
19784       __IOM uint32_t APBDMAERR  : 1;            /*!< [13..13] MSPI is dma target as well as dma source, which may
19785                                                      result in deadlock.                                                       */
19786             uint32_t            : 18;
19787     } INTSTAT_b;
19788   } ;
19789 
19790   union {
19791     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
19792                                                                     the interrupt status associated with that
19793                                                                     bit.                                                       */
19794 
19795     struct {
19796       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
19797                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
19798       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
19799       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
19800                                                      a full FIFO).                                                             */
19801       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
19802                                                      an empty FIFO)                                                            */
19803       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
19804                                                      MSPI bus pins will stall)                                                 */
19805       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
19806       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
19807       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
19808       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
19809       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
19810                                                      performs an operation where address bit[0] is set. Useful
19811                                                      for triggering CURIDX interrupts.                                         */
19812       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
19813       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
19814       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
19815                                                      be aligned to word (4-byte) start address.                                */
19816       __IOM uint32_t APBDMAERR  : 1;            /*!< [13..13] MSPI is dma target as well as dma source, which may
19817                                                      result in deadlock.                                                       */
19818             uint32_t            : 18;
19819     } INTCLR_b;
19820   } ;
19821 
19822   union {
19823     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
19824                                                                     generate an interrupt from this module.
19825                                                                     (Generally used for testing purposes).                     */
19826 
19827     struct {
19828       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
19829                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
19830       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
19831       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
19832                                                      a full FIFO).                                                             */
19833       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
19834                                                      an empty FIFO)                                                            */
19835       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
19836                                                      MSPI bus pins will stall)                                                 */
19837       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
19838       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
19839       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
19840       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
19841       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
19842                                                      performs an operation where address bit[0] is set. Useful
19843                                                      for triggering CURIDX interrupts.                                         */
19844       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
19845       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
19846       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
19847                                                      be aligned to word (4-byte) start address.                                */
19848       __IOM uint32_t APBDMAERR  : 1;            /*!< [13..13] MSPI is dma target as well as dma source, which may
19849                                                      result in deadlock.                                                       */
19850             uint32_t            : 18;
19851     } INTSET_b;
19852   } ;
19853   __IM  uint32_t  RESERVED5[36];
19854 
19855   union {
19856     __IOM uint32_t CQCFG;                       /*!< (@ 0x000002A0) This register controls Command Queuing (CQ) operations
19857                                                                     in a manner similar to the DMACFG register.                */
19858 
19859     struct {
19860       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
19861                                                      of the command queue                                                      */
19862       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue DMA request                 */
19863       __IOM uint32_t CQPWROFF   : 1;            /*!< [2..2] Power off MSPI domain upon completion of DMA operation.            */
19864       __IOM uint32_t CQAUTOCLEARMASK : 1;       /*!< [3..3] Enable clear of CQMASK after each pause operation. This
19865                                                      may be useful when using software flags to pause CQ.                      */
19866       __IOM uint32_t CQPAUSEOP  : 1;            /*!< [4..4] CQPAUSEOP register description needed.                             */
19867             uint32_t            : 27;
19868     } CQCFG_b;
19869   } ;
19870   __IM  uint32_t  RESERVED6;
19871 
19872   union {
19873     __IOM uint32_t CQADDR;                      /*!< (@ 0x000002A8) Location of the command queue in SRAM or flash
19874                                                                     memory. This register will increment as
19875                                                                     CQ operations commence. Software should
19876                                                                     only write CQADDR when CQEN is disabled,
19877                                                                     however the command queue script itself
19878                                                                     may update CQADDR in order to perform queue
19879                                                                     management functions (like resetting the
19880                                                                     pointers)                                                  */
19881 
19882     struct {
19883       __IOM uint32_t CQADDR     : 29;           /*!< [28..0] Address of command queue buffer in SRAM or flash. The
19884                                                      buffer address must be aligned to a word boundary.                        */
19885             uint32_t            : 3;
19886     } CQADDR_b;
19887   } ;
19888 
19889   union {
19890     __IOM uint32_t CQSTAT;                      /*!< (@ 0x000002AC) Command Queue Status                                       */
19891 
19892     struct {
19893       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
19894                                                      indicate that a CQ transfer is active and this will remain
19895                                                      active even when paused waiting for external event.                       */
19896       __IOM uint32_t CQCPL      : 1;            /*!< [1..1] Command queue operation Complete. This signals the end
19897                                                      of the command queue operation.                                           */
19898       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
19899                                                      signals that an error was encountered during the CQ operation.            */
19900       __IOM uint32_t CQPAUSED   : 1;            /*!< [3..3] Command queue is currently paused status.                          */
19901             uint32_t            : 28;
19902     } CQSTAT_b;
19903   } ;
19904 
19905   union {
19906     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x000002B0) Command Queue Flags                                        */
19907 
19908     struct {
19909       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
19910                                                      controllable and bits [15:8] are hardware status.                         */
19911             uint32_t            : 16;
19912     } CQFLAGS_b;
19913   } ;
19914 
19915   union {
19916     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x000002B4) Command Queue Flag Set/Clear                               */
19917 
19918     struct {
19919       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Set has priority over clear if
19920                                                      both are high.                                                            */
19921       __IOM uint32_t CQFTOGGLE  : 8;            /*!< [15..8] Toggle CQFlag status bits                                         */
19922       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits.                                        */
19923             uint32_t            : 8;
19924     } CQSETCLEAR_b;
19925   } ;
19926 
19927   union {
19928     __IOM uint32_t CQPAUSE;                     /*!< (@ 0x000002B8) Command Queue Pause Mask                                   */
19929 
19930     struct {
19931       __IOM uint32_t CQMASK     : 16;           /*!< [15..0] CQ will pause processing when ALL specified events are
19932                                                      satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK.                      */
19933             uint32_t            : 16;
19934     } CQPAUSE_b;
19935   } ;
19936   __IM  uint32_t  RESERVED7;
19937 
19938   union {
19939     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x000002C0) This register can be used in conjunction with
19940                                                                     the CQENDIDX register to manage the command
19941                                                                     queue. Typically software will initialize
19942                                                                     the CQCURIDX and CQENDIDX to the same value,
19943                                                                     which will cause the CQ to be paused when
19944                                                                     enabled. Software may then add entries to
19945                                                                     the command queue (in SRAM) and update CQENDIDX.
19946                                                                     The command queue operations will then increment
19947                                                                     CQCURIDX as it processes operations. Once
19948                                                                     CQCURIDX==CQENDIDX, the command queue hardware
19949                                                                     will automatically pause since no additional
19950                                                                     ope                                                        */
19951 
19952     struct {
19953       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Can be used to indicate the current position of the command
19954                                                      queue by having CQ operations write this field. A CQ hardware
19955                                                      status flag indicates when CURIDX and ENDIDX are not equal,
19956                                                      allowing SW to pause the CQ processing until the end index
19957                                                      is updated.                                                               */
19958             uint32_t            : 24;
19959     } CQCURIDX_b;
19960   } ;
19961 
19962   union {
19963     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x000002C4) Command Queue End Index                                    */
19964 
19965     struct {
19966       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Can be used to indicate the end position of the command
19967                                                      queue. A CQ hardware status bit indices when CURIDX !=
19968                                                      ENDIDX so that the CQ can be paused when it reaches the
19969                                                      end pointer.                                                              */
19970             uint32_t            : 24;
19971     } CQENDIDX_b;
19972   } ;
19973   __IM  uint32_t  RESERVED8[18];
19974 
19975   union {
19976     __IOM uint32_t STATXIPDMA;                  /*!< (@ 0x00000310) Debug XIP DMA State                                        */
19977 
19978     struct {
19979       __IOM uint32_t FLD32      : 32;           /*!< [31..0] XIP/DMA module debug                                              */
19980     } STATXIPDMA_b;
19981   } ;
19982 } MSPI0_Type;                                   /*!< Size = 788 (0x314)                                                        */
19983 
19984 
19985 
19986 /* =========================================================================================================================== */
19987 /* ================                                           PDM0                                            ================ */
19988 /* =========================================================================================================================== */
19989 
19990 
19991 /**
19992   * @brief PDM Audio (PDM0)
19993   */
19994 
19995 typedef struct {                                /*!< (@ 0x40201000) PDM0 Structure                                             */
19996 
19997   union {
19998     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) PDM Control                                                */
19999 
20000     struct {
20001       __IOM uint32_t CLKEN      : 1;            /*!< [0..0] PDM Clock enable.If multiple clocks are enabled, priority
20002                                                      is HFRC2, HF XTAL, HFRC.                                                  */
20003       __IOM uint32_t CLKSEL     : 2;            /*!< [2..1] PDM Master Clock select (24.576MHz).0: HFRC2_192MHz div8
20004                                                      with HFAdj21: XTAL_HS Byapss2: HFRC_96MHz div4                            */
20005             uint32_t            : 1;
20006       __IOM uint32_t RSTB       : 1;            /*!< [4..4] Reset IP core. 0 puts the core in reset; 1 takes the
20007                                                      core out of reset.                                                        */
20008       __IOM uint32_t PCMPACK    : 1;            /*!< [5..5] Enable PCM packing. Only 24-bit unpacked mode supported.           */
20009       __IOM uint32_t EN         : 1;            /*!< [6..6] PDM enable register                                                */
20010             uint32_t            : 25;
20011     } CTRL_b;
20012   } ;
20013 
20014   union {
20015     __IOM uint32_t CORECFG0;                    /*!< (@ 0x00000004) PDM to PCM Core Configuration                              */
20016 
20017     struct {
20018       __IOM uint32_t LRSWAP     : 1;            /*!< [0..0] Left/Right channel swap when = 1                                   */
20019       __IOM uint32_t SOFTMUTE   : 1;            /*!< [1..1] Soft mute enable when = 1                                          */
20020       __IOM uint32_t SCYCLES    : 3;            /*!< [4..2] Set number of PDMA_CKO cycles during gain setting changes
20021                                                      or soft mute                                                              */
20022       __IOM uint32_t HPGAIN     : 4;            /*!< [8..5] Adjust High Pass filter coefficients                               */
20023       __IOM uint32_t ADCHPD     : 1;            /*!< [9..9] Disable high pass filter when = 1                                  */
20024       __IOM uint32_t MCLKDIV    : 4;            /*!< [13..10] PDMA_CKO frequency divisor.MCLKDIV > 0. MCLKDIV = 0
20025                                                      PROHIBITED.MCLKDIV = (PDM_CLK /Fsin / (DIVMCLKQ + 1)) -1                  */
20026       __IOM uint32_t SINCRATE   : 7;            /*!< [20..14] Sinc decimation rate.SINC_RATE = OSR /2. OSR = Fsin
20027                                                      / Fsout.Must be even.16 to 64 allowed.96 allowed for special
20028                                                      configuration.                                                            */
20029       __IOM uint32_t PGAL       : 5;            /*!< [25..21] Left Channel PGA Gain: +1.5dB/step, -12dB ~ +34.5dB;enum
20030                                                      name = M12_0DB value = 0x0 desc = Left channel PGA gain
20031                                                      = -12.0 dB                                                                */
20032       __IOM uint32_t PGAR       : 5;            /*!< [30..26] Right Channel PGA Gain:+1.5dB/step, -12dB ~ +34.5dB;             */
20033             uint32_t            : 1;
20034     } CORECFG0_b;
20035   } ;
20036 
20037   union {
20038     __IOM uint32_t CORECFG1;                    /*!< (@ 0x00000008) PDM to PCM Extra Configuration                             */
20039 
20040     struct {
20041       __IOM uint32_t PCMCHSET   : 2;            /*!< [1..0] PCM output chanel 0xsetting                                        */
20042       __IOM uint32_t DIVMCLKQ   : 2;            /*!< [3..2] Divide down ratio for generating internal master MCLKQ.DIVMCLKQ
20043                                                      > 0. DIVMCLKQ = 0 PROHIBITED.Recommend value of 1.Fmclkq
20044                                                      = Fpdmclk/(DIVMCLKQ+1).                                                   */
20045       __IOM uint32_t CKODLY     : 3;            /*!< [6..4] PDMA_CKO clock phase delay in terms of PDMCLK period
20046                                                      to internal sampler                                                       */
20047       __IOM uint32_t SELSTEP    : 1;            /*!< [7..7] Fine grain step size for smooth PGA or Softmute attenuation
20048                                                      transition0: 0.13dB1: 0.26dB                                              */
20049             uint32_t            : 24;
20050     } CORECFG1_b;
20051   } ;
20052 
20053   union {
20054     __IOM uint32_t CORECTRL;                    /*!< (@ 0x0000000C) PDM to PCM Control                                         */
20055 
20056     struct {
20057       __IOM uint32_t CORECTRL   : 32;           /*!< [31..0] Overall control of PDM core. Internal use only                    */
20058     } CORECTRL_b;
20059   } ;
20060 
20061   union {
20062     __IOM uint32_t FIFOCNT;                     /*!< (@ 0x00000010) FIFO count                                                 */
20063 
20064     struct {
20065       __IOM uint32_t FIFOCNT    : 6;            /*!< [5..0] Valid 32-bit entries currently in the FIFO.                        */
20066             uint32_t            : 26;
20067     } FIFOCNT_b;
20068   } ;
20069 
20070   union {
20071     __IOM uint32_t FIFOREAD;                    /*!< (@ 0x00000014) FIFO Read                                                  */
20072 
20073     struct {
20074       __IOM uint32_t FIFOREAD   : 32;           /*!< [31..0] FIFO read data.                                                   */
20075     } FIFOREAD_b;
20076   } ;
20077 
20078   union {
20079     __IOM uint32_t FIFOFLUSH;                   /*!< (@ 0x00000018) FIFO Flush                                                 */
20080 
20081     struct {
20082       __IOM uint32_t FIFOFLUSH  : 1;            /*!< [0..0] FIFO FLUSH.                                                        */
20083             uint32_t            : 31;
20084     } FIFOFLUSH_b;
20085   } ;
20086 
20087   union {
20088     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x0000001C) FIFO Threshold                                             */
20089 
20090     struct {
20091       __IOM uint32_t FIFOTHR    : 5;            /*!< [4..0] FIFO Threshold value. When the FIFO count is equal to,
20092                                                      or larger than this value (in words), a THR interrupt is
20093                                                      generated (if enabled). If used for DMA purposes then only
20094                                                      supported values are 0x4, 0x8, 0xc, 0x10, 0x14, 0x18 and
20095                                                      0x1C.                                                                     */
20096             uint32_t            : 27;
20097     } FIFOTHR_b;
20098   } ;
20099   __IM  uint32_t  RESERVED[56];
20100 
20101   union {
20102     __IOM uint32_t INTEN;                       /*!< (@ 0x00000100) Set bits in this register to allow this module
20103                                                                     to generate the corresponding interrupt.                   */
20104 
20105     struct {
20106       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
20107       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
20108       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
20109       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
20110       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
20111             uint32_t            : 27;
20112     } INTEN_b;
20113   } ;
20114 
20115   union {
20116     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000104) Read bits from this register to discover the
20117                                                                     cause of a recent interrupt.                               */
20118 
20119     struct {
20120       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
20121       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
20122       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
20123       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
20124       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
20125             uint32_t            : 27;
20126     } INTSTAT_b;
20127   } ;
20128 
20129   union {
20130     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
20131                                                                     the interrupt status associated with that
20132                                                                     bit.                                                       */
20133 
20134     struct {
20135       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
20136       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
20137       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
20138       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
20139       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
20140             uint32_t            : 27;
20141     } INTCLR_b;
20142   } ;
20143 
20144   union {
20145     __IOM uint32_t INTSET;                      /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
20146                                                                     generate an interrupt from this module.
20147                                                                     (Generally used for testing purposes).                     */
20148 
20149     struct {
20150       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
20151       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
20152       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
20153       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
20154       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
20155             uint32_t            : 27;
20156     } INTSET_b;
20157   } ;
20158   __IM  uint32_t  RESERVED1[12];
20159 
20160   union {
20161     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000140) DMA Trigger Enable                                         */
20162 
20163     struct {
20164       __IOM uint32_t DTHR       : 1;            /*!< [0..0] Trigger DMA upon when FIFO iss filled to level indicated
20165                                                      by the FIFO THRESHOLD,at granularity of 16 bytes only                     */
20166       __IOM uint32_t DTHR90     : 1;            /*!< [1..1] Trigger DMA at FIFO 90 percent full. This signal is also
20167                                                      used internally for AUTOHIP function                                      */
20168             uint32_t            : 30;
20169     } DMATRIGEN_b;
20170   } ;
20171 
20172   union {
20173     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000144) DMA Trigger Status                                         */
20174 
20175     struct {
20176       __IOM uint32_t DTHRSTAT   : 1;            /*!< [0..0] Triggered DMA from FIFO reaching threshold                         */
20177       __IOM uint32_t DTHR90STAT : 1;            /*!< [1..1] Triggered DMA from FIFO reaching 90 percent full                   */
20178             uint32_t            : 30;
20179     } DMATRIGSTAT_b;
20180   } ;
20181 
20182   union {
20183     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000148) DMA Configuration                                          */
20184 
20185     struct {
20186       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
20187             uint32_t            : 1;
20188       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
20189             uint32_t            : 5;
20190       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
20191       __IOM uint32_t DAUTOHIP   : 1;            /*!< [9..9] Raise priority to high on fifo full, and DMAPRI set to
20192                                                      low                                                                       */
20193       __IOM uint32_t DPWROFF    : 1;            /*!< [10..10] Power Off the ADC System upon DMACPL.                            */
20194             uint32_t            : 21;
20195     } DMACFG_b;
20196   } ;
20197   __IM  uint32_t  RESERVED2[2];
20198 
20199   union {
20200     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000154) DMA Target Address                                         */
20201 
20202     struct {
20203       __IOM uint32_t LTARGADDR  : 28;           /*!< [27..0] DMA Target Address. This register is not updated with
20204                                                      the current address of the DMA, but will remain static
20205                                                      with the original address during the DMA transfer.                        */
20206       __IOM uint32_t UTARGADDR  : 4;            /*!< [31..28] SRAM Target                                                      */
20207     } DMATARGADDR_b;
20208   } ;
20209 
20210   union {
20211     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000158) DMA Status                                                 */
20212 
20213     struct {
20214       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
20215       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
20216       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
20217             uint32_t            : 29;
20218     } DMASTAT_b;
20219   } ;
20220   __IM  uint32_t  RESERVED3[61];
20221 
20222   union {
20223     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000250) DMA Total Transfer Count                                   */
20224 
20225     struct {
20226       __IOM uint32_t TOTCOUNT   : 20;           /*!< [19..0] Total Transfer Count. The transfer count must be a multiple
20227                                                      of the THR setting to avoid DMA overruns.                                 */
20228             uint32_t            : 12;
20229     } DMATOTCOUNT_b;
20230   } ;
20231 } PDM0_Type;                                    /*!< Size = 596 (0x254)                                                        */
20232 
20233 
20234 
20235 /* =========================================================================================================================== */
20236 /* ================                                          PWRCTRL                                          ================ */
20237 /* =========================================================================================================================== */
20238 
20239 
20240 /**
20241   * @brief PWR Controller Register Bank (PWRCTRL)
20242   */
20243 
20244 typedef struct {                                /*!< (@ 0x40021000) PWRCTRL Structure                                          */
20245 
20246   union {
20247     __IOM uint32_t MCUPERFREQ;                  /*!< (@ 0x00000000) This register provides the performance mode knobs
20248                                                                     for MCU. S/w should write the *PERFREQ field
20249                                                                     to desired mode and wait for the *PERFACK
20250                                                                     and check for the *PERFSTATUS. Some times
20251                                                                     system may not allow certain modes but *PERFACK
20252                                                                     should always follow *PERFREQ change.                      */
20253 
20254     struct {
20255       __IOM uint32_t MCUPERFREQ : 2;            /*!< [1..0] MCU Performance mode request                                       */
20256       __IOM uint32_t MCUPERFACK : 1;            /*!< [2..2] Indicates the MCU performance status indicated in STATUS
20257                                                      register is valid.                                                        */
20258       __IOM uint32_t MCUPERFSTATUS : 2;         /*!< [4..3] MCU Performance mode request                                       */
20259             uint32_t            : 27;
20260     } MCUPERFREQ_b;
20261   } ;
20262 
20263   union {
20264     __IOM uint32_t DEVPWREN;                    /*!< (@ 0x00000004) This enables various peripherals power domains.            */
20265 
20266     struct {
20267       __IOM uint32_t PWRENIOS   : 1;            /*!< [0..0] Power up IO Slave                                                  */
20268       __IOM uint32_t PWRENIOM0  : 1;            /*!< [1..1] Power up IO Master 0                                               */
20269       __IOM uint32_t PWRENIOM1  : 1;            /*!< [2..2] Power up IO Master 1                                               */
20270       __IOM uint32_t PWRENIOM2  : 1;            /*!< [3..3] Power up IO Master 2                                               */
20271       __IOM uint32_t PWRENIOM3  : 1;            /*!< [4..4] Power up IO Master 3                                               */
20272       __IOM uint32_t PWRENIOM4  : 1;            /*!< [5..5] Power up IO Master 4                                               */
20273       __IOM uint32_t PWRENIOM5  : 1;            /*!< [6..6] Power up IO Master 5                                               */
20274       __IOM uint32_t PWRENIOM6  : 1;            /*!< [7..7] Power up IO Master 6                                               */
20275       __IOM uint32_t PWRENIOM7  : 1;            /*!< [8..8] Power up IO Master 7                                               */
20276       __IOM uint32_t PWRENUART0 : 1;            /*!< [9..9] Power up UART Controller 0                                         */
20277       __IOM uint32_t PWRENUART1 : 1;            /*!< [10..10] Power up UART Controller 1                                       */
20278       __IOM uint32_t PWRENUART2 : 1;            /*!< [11..11] Power up UART Controller 2                                       */
20279       __IOM uint32_t PWRENUART3 : 1;            /*!< [12..12] Power up UART Controller 3                                       */
20280       __IOM uint32_t PWRENADC   : 1;            /*!< [13..13] Power up ADC Digital Controller                                  */
20281       __IOM uint32_t PWRENMSPI0 : 1;            /*!< [14..14] Power up MSPI Controller0                                        */
20282       __IOM uint32_t PWRENMSPI1 : 1;            /*!< [15..15] Power up MSPI Controller1                                        */
20283       __IOM uint32_t PWRENMSPI2 : 1;            /*!< [16..16] Power up MSPI Controller2                                        */
20284       __IOM uint32_t PWRENGFX   : 1;            /*!< [17..17] Power up GFX controller                                          */
20285       __IOM uint32_t PWRENDISP  : 1;            /*!< [18..18] Power up DISP controller                                         */
20286       __IOM uint32_t PWRENDISPPHY : 1;          /*!< [19..19] Power up DISP PHY                                                */
20287       __IOM uint32_t PWRENCRYPTO : 1;           /*!< [20..20] Power up CRYPTO module                                           */
20288       __IOM uint32_t PWRENSDIO  : 1;            /*!< [21..21] Power up SDIO controller                                         */
20289       __IOM uint32_t PWRENUSB   : 1;            /*!< [22..22] Power up USB controller                                          */
20290       __IOM uint32_t PWRENUSBPHY : 1;           /*!< [23..23] Power up USB PHY                                                 */
20291       __IOM uint32_t PWRENDBG   : 1;            /*!< [24..24] Powerup DBG power domain                                         */
20292       __IOM uint32_t PWRENI3C0  : 1;            /*!< [25..25] Powerup I3C0 power domain                                        */
20293       __IOM uint32_t PWRENI3C1  : 1;            /*!< [26..26] Powerup I3C1 power domain                                        */
20294             uint32_t            : 5;
20295     } DEVPWREN_b;
20296   } ;
20297 
20298   union {
20299     __IOM uint32_t DEVPWRSTATUS;                /*!< (@ 0x00000008) This provides the power status for the peripheral
20300                                                                     device domains controlled through DEVPWREN
20301                                                                     register. Value of 1 means the device is
20302                                                                     powred up and ready to be used and 0 means
20303                                                                     its not powered up.                                        */
20304 
20305     struct {
20306       __IOM uint32_t PWRSTIOS   : 1;            /*!< [0..0] Power status IO Slave                                              */
20307       __IOM uint32_t PWRSTIOM0  : 1;            /*!< [1..1] Power status IO Master 0                                           */
20308       __IOM uint32_t PWRSTIOM1  : 1;            /*!< [2..2] Power status IO Master 1                                           */
20309       __IOM uint32_t PWRSTIOM2  : 1;            /*!< [3..3] Power status IO Master 2                                           */
20310       __IOM uint32_t PWRSTIOM3  : 1;            /*!< [4..4] Power status IO Master 3                                           */
20311       __IOM uint32_t PWRSTIOM4  : 1;            /*!< [5..5] Power status IO Master 4                                           */
20312       __IOM uint32_t PWRSTIOM5  : 1;            /*!< [6..6] Power Status IO Master 5                                           */
20313       __IOM uint32_t PWRSTIOM6  : 1;            /*!< [7..7] Power Status IO Master 6                                           */
20314       __IOM uint32_t PWRSTIOM7  : 1;            /*!< [8..8] Power Status IO Master 7                                           */
20315       __IOM uint32_t PWRSTUART0 : 1;            /*!< [9..9] Power Status UART Controller 0                                     */
20316       __IOM uint32_t PWRSTUART1 : 1;            /*!< [10..10] Power Status UART Controller 1                                   */
20317       __IOM uint32_t PWRSTUART2 : 1;            /*!< [11..11] Power Status UART Controller 2                                   */
20318       __IOM uint32_t PWRSTUART3 : 1;            /*!< [12..12] Power Status UART Controller 3                                   */
20319       __IOM uint32_t PWRSTADC   : 1;            /*!< [13..13] Power Status ADC Digital Controller                              */
20320       __IOM uint32_t PWRSTMSPI0 : 1;            /*!< [14..14] Power Status MSPI Controller0                                    */
20321       __IOM uint32_t PWRSTMSPI1 : 1;            /*!< [15..15] Power Status MSPI Controller1                                    */
20322       __IOM uint32_t PWRSTMSPI2 : 1;            /*!< [16..16] Power Status MSPI Controller2                                    */
20323       __IOM uint32_t PWRSTGFX   : 1;            /*!< [17..17] Power Status GFX controller                                      */
20324       __IOM uint32_t PWRSTDISP  : 1;            /*!< [18..18] Power Status DISP controller                                     */
20325       __IOM uint32_t PWRSTDISPPHY : 1;          /*!< [19..19] Power Status DISP PHY                                            */
20326       __IOM uint32_t PWRSTCRYPTO : 1;           /*!< [20..20] Power Status CRYPTO module                                       */
20327       __IOM uint32_t PWRSTSDIO  : 1;            /*!< [21..21] Power Status SDIO controller                                     */
20328       __IOM uint32_t PWRSTUSB   : 1;            /*!< [22..22] Power Status USB controller                                      */
20329       __IOM uint32_t PWRSTUSBPHY : 1;           /*!< [23..23] Power Status USB PHY                                             */
20330       __IOM uint32_t PWRSTDBG   : 1;            /*!< [24..24] Power Status DBG subsystem                                       */
20331       __IOM uint32_t PWRSTI3C0  : 1;            /*!< [25..25] Power Status I3C0                                                */
20332       __IOM uint32_t PWRSTI3C1  : 1;            /*!< [26..26] Power Status I3C1                                                */
20333             uint32_t            : 5;
20334     } DEVPWRSTATUS_b;
20335   } ;
20336 
20337   union {
20338     __IOM uint32_t AUDSSPWREN;                  /*!< (@ 0x0000000C) This enables various power domains in audio subsystem.     */
20339 
20340     struct {
20341       __IOM uint32_t PWRENAUDREC : 1;           /*!< [0..0] Power up Audio Record                                              */
20342       __IOM uint32_t PWRENAUDPB : 1;            /*!< [1..1] Power up Audio Playback                                            */
20343       __IOM uint32_t PWRENPDM0  : 1;            /*!< [2..2] Power up audio subsystem PDM0 domain                               */
20344       __IOM uint32_t PWRENPDM1  : 1;            /*!< [3..3] Power up audio subsystem PDM1 domain                               */
20345       __IOM uint32_t PWRENPDM2  : 1;            /*!< [4..4] Power up audio subsystem PDM2 domain                               */
20346       __IOM uint32_t PWRENPDM3  : 1;            /*!< [5..5] Power up audio subsystem PDM3 domain                               */
20347       __IOM uint32_t PWRENI2S0  : 1;            /*!< [6..6] Power up audio subsystem I2S0 domain                               */
20348       __IOM uint32_t PWRENI2S1  : 1;            /*!< [7..7] Power up audio subsystem I2S1 domain                               */
20349             uint32_t            : 2;
20350       __IOM uint32_t PWRENAUDADC : 1;           /*!< [10..10] Power up audio subsystem ADC domain                              */
20351       __IOM uint32_t PWRENDSPA  : 1;            /*!< [11..11] Enable one or more DSP subsystems                                */
20352             uint32_t            : 20;
20353     } AUDSSPWREN_b;
20354   } ;
20355 
20356   union {
20357     __IOM uint32_t AUDSSPWRSTATUS;              /*!< (@ 0x00000010) This provides the power status for the peripheral
20358                                                                     domains controlled through AUDSSPWREN register.
20359                                                                     Value of 1 means the device is powred up
20360                                                                     and ready to be used and 0 means its not
20361                                                                     powered up.                                                */
20362 
20363     struct {
20364       __IOM uint32_t PWRSTAUDREC : 1;           /*!< [0..0] Power Status Audio Record block                                    */
20365       __IOM uint32_t PWRSTAUDPB : 1;            /*!< [1..1] Power Status Audio Playback block                                  */
20366       __IOM uint32_t PWRSTPDM0  : 1;            /*!< [2..2] Power Status audio subsystem PDM0 domain                           */
20367       __IOM uint32_t PWRSTPDM1  : 1;            /*!< [3..3] Power Status audio subsystem PDM1 domain                           */
20368       __IOM uint32_t PWRSTPDM2  : 1;            /*!< [4..4] Power Status audio subsystem PDM2 domain                           */
20369       __IOM uint32_t PWRSTPDM3  : 1;            /*!< [5..5] Power Status audio subsystem PDM3 domain                           */
20370       __IOM uint32_t PWRSTI2S0  : 1;            /*!< [6..6] Power Status audio subsystem I2S0 domain                           */
20371       __IOM uint32_t PWRSTI2S1  : 1;            /*!< [7..7] Power Status audio subsystem I2S1 domain                           */
20372             uint32_t            : 2;
20373       __IOM uint32_t PWRSTAUDADC : 1;           /*!< [10..10] Power Status audio subsystem ADC domain                          */
20374       __IOM uint32_t PWRSTDSPA  : 1;            /*!< [11..11] Power Status DSPA subsystem                                      */
20375             uint32_t            : 20;
20376     } AUDSSPWRSTATUS_b;
20377   } ;
20378 
20379   union {
20380     __IOM uint32_t MEMPWREN;                    /*!< (@ 0x00000014) This register enables the individual banks for
20381                                                                     the memories. When set, power will be enabled
20382                                                                     to the banks. This register works in conjunction
20383                                                                     with the MEMRETCFG register. If this register
20384                                                                     is not set, then power will always be disabled
20385                                                                     to the memory bank.                                        */
20386 
20387     struct {
20388       __IOM uint32_t PWRENDTCM  : 3;            /*!< [2..0] Power up DTCM                                                      */
20389       __IOM uint32_t PWRENNVM0  : 1;            /*!< [3..3] Power up NVM0                                                      */
20390       __IOM uint32_t PWRENCACHEB0 : 1;          /*!< [4..4] Power up Cache Bank 0. This works in conjunction with
20391                                                      Cache enable from flash_cache module. To power up cache
20392                                                      bank0, cache has to be enabled and this bit has to be set.                */
20393       __IOM uint32_t PWRENCACHEB2 : 1;          /*!< [5..5] Power up Cache Bank 2. This works in conjunction with
20394                                                      Cache enable from flash_cache module. To power up cache
20395                                                      bank2, cache has to be enabled and this bit has to be set.                */
20396             uint32_t            : 26;
20397     } MEMPWREN_b;
20398   } ;
20399 
20400   union {
20401     __IOM uint32_t MEMPWRSTATUS;                /*!< (@ 0x00000018) It provides the power status for all the memory
20402                                                                     banks including- caches, nvm (0 and 1) and
20403                                                                     all the SRAM groups. The status here should
20404                                                                     reflect the enable provided by the MEMPWREN
20405                                                                     register. There may be a lag time between
20406                                                                     setting the bits in MEMPWREN register and
20407                                                                     MEMPWRSTATUS register, due to the need to
20408                                                                     cycle the power gate and isolation seqeunces
20409                                                                     to the memory banks.                                       */
20410 
20411     struct {
20412       __IOM uint32_t PWRSTDTCM  : 3;            /*!< [2..0] Power status for DTCM. Each bit corresponds to one of
20413                                                      the TCMs. bit0=DTCM0_0, bit1=DTCM0_1, bit2=DTCM1.                         */
20414       __IOM uint32_t PWRSTNVM0  : 1;            /*!< [3..3] This bit is 1 if power is supplied to NVM 0                        */
20415       __IOM uint32_t PWRSTCACHEB0 : 1;          /*!< [4..4] This bit is 1 if power is supplied to Cache Bank 0                 */
20416       __IOM uint32_t PWRSTCACHEB2 : 1;          /*!< [5..5] This bit is 1 if power is supplied to Cache Bank 2                 */
20417             uint32_t            : 26;
20418     } MEMPWRSTATUS_b;
20419   } ;
20420 
20421   union {
20422     __IOM uint32_t MEMRETCFG;                   /*!< (@ 0x0000001C) This controls the power down of the SRAM banks
20423                                                                     in deep sleep mode. If this is set, then
20424                                                                     the power for that SRAM bank will be gated
20425                                                                     when the core goes into deep sleep. Upon
20426                                                                     wake, the data within the SRAMs will be
20427                                                                     erased. If this is not set, retention voltage
20428                                                                     will be applied to the SRAM bank when the
20429                                                                     core goes into deep sleep. Upon wake, the
20430                                                                     data within the SRAMs are retained. Do not
20431                                                                     set this if the SRAM bank is used as the
20432                                                                     target for DMA transfer while CPU in deepsleep.            */
20433 
20434     struct {
20435       __IOM uint32_t DTCMPWDSLP : 3;            /*!< [2..0] power down DTCM in deep sleep                                      */
20436       __IOM uint32_t NVM0PWDSLP : 1;            /*!< [3..3] Powerdown NVM0 in deep sleep                                       */
20437       __IOM uint32_t CACHEPWDSLP : 1;           /*!< [4..4] power down cache in deep sleep                                     */
20438             uint32_t            : 27;
20439     } MEMRETCFG_b;
20440   } ;
20441 
20442   union {
20443     __IOM uint32_t SYSPWRSTATUS;                /*!< (@ 0x00000020) Power ON Status for domains that are not part
20444                                                                     of devpwrstatus or mempwrstatus                            */
20445 
20446     struct {
20447       __IOM uint32_t PWRSTMCUL  : 1;            /*!< [0..0] Power Domain status for MCUL                                       */
20448       __IOM uint32_t PWRSTMCUH  : 1;            /*!< [1..1] Power Domain status for MCUH                                       */
20449       __IOM uint32_t PWRSTDSP0H : 1;            /*!< [2..2] Power Domain status for DSP0H                                      */
20450       __IOM uint32_t PWRSTDSP1H : 1;            /*!< [3..3] Power Domain status for DSP1H                                      */
20451             uint32_t            : 25;
20452       __IOM uint32_t CORESLEEP  : 1;            /*!< [29..29] Indicates MCU entered SLEEP state since it was last
20453                                                      cleared. Write 1 to to clear it.                                          */
20454       __IOM uint32_t COREDEEPSLEEP : 1;         /*!< [30..30] Indicates MCU entered DEEPSLEEP state since it was
20455                                                      last cleared. Write 1 to to clear it.                                     */
20456       __IOM uint32_t SYSDEEPSLEEP : 1;          /*!< [31..31] Indicates all device domains powered down and MCU entered
20457                                                      DEEPSLEEP state since it was last cleared. Write 1 to to
20458                                                      clear it.                                                                 */
20459     } SYSPWRSTATUS_b;
20460   } ;
20461 
20462   union {
20463     __IOM uint32_t SSRAMPWREN;                  /*!< (@ 0x00000024) This register enables the individual banks for
20464                                                                     the memories. When set, power will be enabled
20465                                                                     to the banks. This register works in conjunction
20466                                                                     with the SSRAMRETCFG register. If this register
20467                                                                     is not set, then power will always be disabled
20468                                                                     to the memory bank.                                        */
20469 
20470     struct {
20471       __IOM uint32_t PWRENSSRAM : 2;            /*!< [1..0] Power up SRAM groups                                               */
20472             uint32_t            : 30;
20473     } SSRAMPWREN_b;
20474   } ;
20475 
20476   union {
20477     __IOM uint32_t SSRAMPWRST;                  /*!< (@ 0x00000028) It provides the power status for shared sram
20478                                                                     banks. The status here should reflect the
20479                                                                     enable provided by the SSRAMPWREN register.                */
20480 
20481     struct {
20482       __IOM uint32_t SSRAMPWRST : 2;            /*!< [1..0] Each bit corresponds to one 1M SSRAM group. Power Status-
20483                                                      1:ON, 0:OFF See SSRAMPWREN PWRENSSRAM for bit mapping.
20484                                                      For example, a value of 2 in this field would mean that
20485                                                      SSRAM1 is powered up and SSRAM0 is powered down.                          */
20486             uint32_t            : 30;
20487     } SSRAMPWRST_b;
20488   } ;
20489 
20490   union {
20491     __IOM uint32_t SSRAMRETCFG;                 /*!< (@ 0x0000002C) This controls the power down of the Shared SRAM
20492                                                                     banks in deep sleep mode. If this is set,
20493                                                                     then the power for that SRAM bank will be
20494                                                                     gated when the core goes into deep sleep.
20495                                                                     Upon wake, the data within the SRAMs will
20496                                                                     be erased. If this is not set, retention
20497                                                                     voltage will be applied to the SRAM bank
20498                                                                     when none of the CPU agents are in powered
20499                                                                     up and active mode. Do not set this if the
20500                                                                     SRAM bank is used as the target for DMA
20501                                                                     transfer while CPU in deepsleep.                           */
20502 
20503     struct {
20504       __IOM uint32_t SSRAMPWDSLP : 2;           /*!< [1..0] Selects which shared SRAM banks are powered down in deep
20505                                                      sleep mode, causing the contents of the bank to be lost.                  */
20506       __IOM uint32_t SSRAMACTMCU : 2;           /*!< [3..2] Keep the memory domain active based on MCU state. Each
20507                                                      bit corresponds to a domain. 1: Keep SRAM active 0: Wakeup
20508                                                      on demand (i.e. when MCU is powered up)                                   */
20509       __IOM uint32_t SSRAMACTDSP : 2;           /*!< [5..4] Keep the memory domain active based on DSP state. Each
20510                                                      bit corresponds to a domain. 1: Keep SRAM active 0: Powerup
20511                                                      on demand (i.e. when DSP is powered up)                                   */
20512       __IOM uint32_t SSRAMACTGFX : 2;           /*!< [7..6] Keep the memory domain active based on GFX state. Each
20513                                                      bit corresponds to a domain. 1: Keep SRAM active 0: Powerup
20514                                                      on demand (i.e. when GFX is powered up)                                   */
20515       __IOM uint32_t SSRAMACTDISP : 2;          /*!< [9..8] Keep the memory domain active based on DISP state. Each
20516                                                      bit corresponds to a domain. 1: Keep SRAM active 0: Powerup
20517                                                      on demand (i.e. when DISP is powered up)                                  */
20518             uint32_t            : 22;
20519     } SSRAMRETCFG_b;
20520   } ;
20521 
20522   union {
20523     __IOM uint32_t DEVPWREVENTEN;               /*!< (@ 0x00000030) This register controls which feature trigger
20524                                                                     will result in an event to the CPU. It includes
20525                                                                     all the power on status for the core domains.
20526                                                                     If any bits are set, then if the domain
20527                                                                     is turned on, it will result in an event
20528                                                                     to the ARM core.                                           */
20529 
20530     struct {
20531       __IOM uint32_t MCULEVEN   : 1;            /*!< [0..0] Control MCUL power-on status event                                 */
20532       __IOM uint32_t MCUHEVEN   : 1;            /*!< [1..1] Control MCUH power-on status event                                 */
20533       __IOM uint32_t HCPAEVEN   : 1;            /*!< [2..2] Control HCPA power-on status event                                 */
20534       __IOM uint32_t HCPBEVEN   : 1;            /*!< [3..3] Control HCPB power-on status event                                 */
20535       __IOM uint32_t HCPCEVEN   : 1;            /*!< [4..4] Control HCPC power-on status event                                 */
20536       __IOM uint32_t ADCEVEN    : 1;            /*!< [5..5] Control ADC power-on status event                                  */
20537       __IOM uint32_t MSPIEVEN   : 1;            /*!< [6..6] Control MSPI power-on status event                                 */
20538       __IOM uint32_t AUDEVEN    : 1;            /*!< [7..7] Control AUD power-on status event                                  */
20539             uint32_t            : 24;
20540     } DEVPWREVENTEN_b;
20541   } ;
20542 
20543   union {
20544     __IOM uint32_t MEMPWREVENTEN;               /*!< (@ 0x00000034) This register controls which power enable for
20545                                                                     the memories will result in an event to
20546                                                                     the CPU. It includes all the power on status
20547                                                                     for the memory domains. If any bits are
20548                                                                     set, then if the domain is turned on, it
20549                                                                     will result in an event to the ARM core.                   */
20550 
20551     struct {
20552       __IOM uint32_t DTCMEN     : 3;            /*!< [2..0] Enable DTCM power-on status event                                  */
20553       __IOM uint32_t NVM0EN     : 1;            /*!< [3..3] Control NVM power-on status event                                  */
20554       __IOM uint32_t CACHEB0EN  : 1;            /*!< [4..4] Control CACHE BANK 0 power-on status event                         */
20555       __IOM uint32_t CACHEB2EN  : 1;            /*!< [5..5] Control CACHEB2 power-on status event                              */
20556             uint32_t            : 26;
20557     } MEMPWREVENTEN_b;
20558   } ;
20559   __IM  uint32_t  RESERVED[2];
20560 
20561   union {
20562     __IOM uint32_t MMSOVERRIDE;                 /*!< (@ 0x00000040) Power domain behavior overrides related to MMS
20563                                                                     ( Multimedia System ).                                     */
20564 
20565     struct {
20566       __IOM uint32_t MMSOVRMCULDISP : 1;        /*!< [0..0] MMS override for MCUL on by PD_DISP setting.                       */
20567       __IOM uint32_t MMSOVRMCULGFX : 1;         /*!< [1..1] MMS override for MCUL on by PD_GFX setting.                        */
20568       __IOM uint32_t MMSOVRSSRAMDISP : 1;       /*!< [2..2] MMS override for SSRAM power state by PD_DISP power setting.       */
20569       __IOM uint32_t MMSOVRSSRAMGFX : 1;        /*!< [3..3] MMS override for SSRAM power state by PD_GFX power setting.        */
20570       __IOM uint32_t MMSOVRDSPRAMRETDISP : 2;   /*!< [5..4] If set, retention equation doesn't consider DISP. Each
20571                                                      bit corresponds to a domain.                                              */
20572       __IOM uint32_t MMSOVRDSPRAMRETGFX : 2;    /*!< [7..6] If set, retention equation doesn't consider GFX. Each
20573                                                      bit corresponds to a domain.                                              */
20574       __IOM uint32_t MMSOVRSSRAMRETDISP : 2;    /*!< [9..8] If set, retention equation doesn't consider DISP. Each
20575                                                      bit corresponds to a domain.                                              */
20576       __IOM uint32_t MMSOVRSSRAMRETGFX : 2;     /*!< [11..10] If set, retention equation doesn't consider GFX. Each
20577                                                      bit corresponds to a domain.                                              */
20578             uint32_t            : 20;
20579     } MMSOVERRIDE_b;
20580   } ;
20581   __IM  uint32_t  RESERVED1[3];
20582 
20583   union {
20584     __IOM uint32_t DSP0PWRCTRL;                 /*!< (@ 0x00000050) Power and RST controls for DSP0                            */
20585 
20586     struct {
20587       __IOM uint32_t DSP0PCMRSTDLY : 4;         /*!< [3..0] PCM Reset delay in number of 24MHz clocks.                         */
20588       __IOM uint32_t DSP0PCMRSTOR : 1;          /*!< [4..4] PCM Reset override. If this is disabled, then h/w will
20589                                                      handle the de-assertion of pcm reset.                                     */
20590             uint32_t            : 27;
20591     } DSP0PWRCTRL_b;
20592   } ;
20593 
20594   union {
20595     __IOM uint32_t DSP0PERFREQ;                 /*!< (@ 0x00000054) This register provides the performance mode knobs
20596                                                                     for DSP0. S/w should write the *PERFREQ
20597                                                                     field to desired mode and wait for the *PERFACK
20598                                                                     and check for the *PERFSTATUS. Some times
20599                                                                     system may not allow certain modes but *PERFACK
20600                                                                     should always follow *PERFREQ change.                      */
20601 
20602     struct {
20603       __IOM uint32_t DSP0PERFREQ : 2;           /*!< [1..0] DSP0 Performance mode request                                      */
20604       __IOM uint32_t DSP0PERFACK : 1;           /*!< [2..2] Indicates the DSP0 performance status indicated in STATUS
20605                                                      register is valid.                                                        */
20606       __IOM uint32_t DSP0PERFSTATUS : 2;        /*!< [4..3] DSP0 Performance mode request                                      */
20607             uint32_t            : 27;
20608     } DSP0PERFREQ_b;
20609   } ;
20610 
20611   union {
20612     __IOM uint32_t DSP0MEMPWREN;                /*!< (@ 0x00000058) This register enables the individual banks for
20613                                                                     the memories. When set, power will be enabled
20614                                                                     to the banks. This register works in conjunction
20615                                                                     with the DSP0MEMRETCFG register when DSP0
20616                                                                     is OFF.                                                    */
20617 
20618     struct {
20619       __IOM uint32_t PWRENDSP0RAM : 1;          /*!< [0..0] Power up DSP0 IRAM and DRAM                                        */
20620       __IOM uint32_t PWRENDSP0ICACHE : 1;       /*!< [1..1] Power up DSP0 ICACHE banks                                         */
20621             uint32_t            : 30;
20622     } DSP0MEMPWREN_b;
20623   } ;
20624 
20625   union {
20626     __IOM uint32_t DSP0MEMPWRST;                /*!< (@ 0x0000005C) It provides the power status for all the memories
20627                                                                     of DSP0 subsystem                                          */
20628 
20629     struct {
20630       __IOM uint32_t PWRSTDSP0RAM : 1;          /*!< [0..0] Status- 1:ON, 0:OFF                                                */
20631       __IOM uint32_t PWRSTDSP0ICACHE : 1;       /*!< [1..1] Power Status- 1:ON, 0:OFF                                          */
20632             uint32_t            : 30;
20633     } DSP0MEMPWRST_b;
20634   } ;
20635 
20636   union {
20637     __IOM uint32_t DSP0MEMRETCFG;               /*!< (@ 0x00000060) This controls the power down of the DRAM/IRAM/CACHE
20638                                                                     banks when DSP0 is powered off. If this
20639                                                                     is set, then the power for that corresponding
20640                                                                     SRAM bank will be gated when the DSP0 is
20641                                                                     powered off and data is erased. If this
20642                                                                     is not set, retention voltage will be applied
20643                                                                     when DSP0 is powered off. Do not set this
20644                                                                     if the SRAM bank is used as the target for
20645                                                                     DMA transfer while DSP0 is powered off.                    */
20646 
20647     struct {
20648       __IOM uint32_t RAMPWDDSP0OFF : 1;         /*!< [0..0] IRAM/DRAM banks are powered down when DSP0 is switched
20649                                                      off, causing the contents of the bank to be lost.                         */
20650       __IOM uint32_t DSP0RAMACTMCU : 1;         /*!< [1..1] Keep the memory domain active based on MCU state.                  */
20651       __IOM uint32_t ICACHEPWDDSP0OFF : 1;      /*!< [2..2] ICACHE is powered down when DSP0 is switched off, causing
20652                                                      the contents of the bank to be lost.                                      */
20653       __IOM uint32_t DSP0RAMACTDISP : 1;        /*!< [3..3] Keep the memory domain active based on DISP state.                 */
20654       __IOM uint32_t DSP0RAMACTGFX : 1;         /*!< [4..4] Keep the memory domain active based on GFX state.                  */
20655             uint32_t            : 27;
20656     } DSP0MEMRETCFG_b;
20657   } ;
20658   __IM  uint32_t  RESERVED2[3];
20659 
20660   union {
20661     __IOM uint32_t DSP1PWRCTRL;                 /*!< (@ 0x00000070) Power and RST controls for DSP1                            */
20662 
20663     struct {
20664       __IOM uint32_t DSP1PCMRSTDLY : 4;         /*!< [3..0] PCM Reset delay in number of 24MHz clocks.                         */
20665       __IOM uint32_t DSP1PCMRSTOR : 1;          /*!< [4..4] PCM Reset override. If this is disabled, then h/w will
20666                                                      handle the de-assertion of pcm reset.                                     */
20667             uint32_t            : 27;
20668     } DSP1PWRCTRL_b;
20669   } ;
20670 
20671   union {
20672     __IOM uint32_t DSP1PERFREQ;                 /*!< (@ 0x00000074) This register provides the performance mode knobs
20673                                                                     for DSP1. S/w should write the *PERFREQ
20674                                                                     field to desired mode and wait for the *PERFACK
20675                                                                     and check for the *PERFSTATUS. Some times
20676                                                                     system may not allow certain modes but *PERFACK
20677                                                                     should always follow *PERFREQ change.                      */
20678 
20679     struct {
20680       __IOM uint32_t DSP1PERFREQ : 2;           /*!< [1..0] DSP1 Performance mode request                                      */
20681       __IOM uint32_t DSP1PERFACK : 1;           /*!< [2..2] Indicates the DSP1 performance status indicated in STATUS
20682                                                      register is valid.                                                        */
20683       __IOM uint32_t DSP1PERFSTATUS : 2;        /*!< [4..3] DSP1 Performance mode request                                      */
20684             uint32_t            : 27;
20685     } DSP1PERFREQ_b;
20686   } ;
20687 
20688   union {
20689     __IOM uint32_t DSP1MEMPWREN;                /*!< (@ 0x00000078) This register enables the individual banks for
20690                                                                     the memories. When set, power will be enabled
20691                                                                     to the banks. This register works in conjunction
20692                                                                     with the DSP1MEMRETCFG register when DSP1
20693                                                                     is OFF.                                                    */
20694 
20695     struct {
20696       __IOM uint32_t PWRENDSP1RAM : 1;          /*!< [0..0] Power up DSP1 IRAM and DRAM                                        */
20697       __IOM uint32_t PWRENDSP1ICACHE : 1;       /*!< [1..1] Power up DSP1 ICACHE banks                                         */
20698             uint32_t            : 30;
20699     } DSP1MEMPWREN_b;
20700   } ;
20701 
20702   union {
20703     __IOM uint32_t DSP1MEMPWRST;                /*!< (@ 0x0000007C) It provides the power status for all the memories
20704                                                                     of DSP1 subsystem                                          */
20705 
20706     struct {
20707       __IOM uint32_t PWRSTDSP1RAM : 1;          /*!< [0..0] Status- 1:ON, 0:OFF                                                */
20708       __IOM uint32_t PWRSTDSP1ICACHE : 1;       /*!< [1..1] Power Status- 1:ON, 0:OFF                                          */
20709             uint32_t            : 30;
20710     } DSP1MEMPWRST_b;
20711   } ;
20712 
20713   union {
20714     __IOM uint32_t DSP1MEMRETCFG;               /*!< (@ 0x00000080) This controls the power down of the DRAM/IRAM/CACHE
20715                                                                     banks when DSP1 is powered off. If this
20716                                                                     is set, then the power for that corresponding
20717                                                                     SRAM bank will be gated when the DSP1 is
20718                                                                     powered off and data is erased. If this
20719                                                                     is not set, retention voltage will be applied
20720                                                                     when DSP1 is powered off. Do not set this
20721                                                                     if the SRAM bank is used as the target for
20722                                                                     DMA transfer while DSP1 is powered off.                    */
20723 
20724     struct {
20725       __IOM uint32_t RAMPWDDSP1OFF : 1;         /*!< [0..0] IRAM/DRAM banks are powered down when DSP1 is switched
20726                                                      off, causing the contents of the bank to be lost.                         */
20727       __IOM uint32_t DSP1RAMACTMCU : 1;         /*!< [1..1] Keep the memory domain active based on MCU state.                  */
20728       __IOM uint32_t ICACHEPWDDSP1OFF : 1;      /*!< [2..2] ICACHE is powered down when DSP1 is switched off, causing
20729                                                      the contents of the bank to be lost.                                      */
20730       __IOM uint32_t DSP1RAMACTDISP : 1;        /*!< [3..3] Keep the memory domain active based on DISP state.                 */
20731       __IOM uint32_t DSP1RAMACTGFX : 1;         /*!< [4..4] Keep the memory domain active based on GFX state.                  */
20732             uint32_t            : 27;
20733     } DSP1MEMRETCFG_b;
20734   } ;
20735 
20736   union {
20737     __IOM uint32_t PWRACKOVR;                   /*!< (@ 0x00000084) This register contains override bit fields for
20738                                                                     various power domain power switch acknowledge
20739                                                                     notification. As a part of power up sequnce,
20740                                                                     Power controller will look for power switch
20741                                                                     ack to advance power up sequence. It is
20742                                                                     possible for power controller to be a forever
20743                                                                     wait state in case of a unforeseen HW bug.
20744                                                                     This register defines a bit fileds to work
20745                                                                     around if needed in such a situation. The
20746                                                                     default behavior is to use HW power switch
20747                                                                     ack. Software can set it to override this
20748                                                                     feature for ea                                             */
20749 
20750     struct {
20751       __IOM uint32_t PWRACKOVERRIDEADC : 1;     /*!< [0..0] Power switch acknowledgement override from Power switch
20752                                                      to power control ST MC                                                    */
20753       __IOM uint32_t PWRACKOVERRIDEAUD : 1;     /*!< [1..1] Power switch acknowledgement override from Power switch
20754                                                      to power control ST MC                                                    */
20755       __IOM uint32_t PWRACKOVERRIDEAUDADC : 1;  /*!< [2..2] Power switch acknowledgement override from Power switch
20756                                                      to power control ST MC                                                    */
20757       __IOM uint32_t PWRACKOVERRIDECRYPTO : 1;  /*!< [3..3] Power switch acknowledgement override from Power switch
20758                                                      to power control ST MC                                                    */
20759       __IOM uint32_t PWRACKOVERRIDEDBG : 1;     /*!< [4..4] Power switch acknowledgement override from Power switch
20760                                                      to power control ST MC                                                    */
20761       __IOM uint32_t PWRACKOVERRIDEDISP : 1;    /*!< [5..5] Power switch acknowledgement override from Power switch
20762                                                      to power control ST MC                                                    */
20763       __IOM uint32_t PWRACKOVERRIDEDISPPHY : 1; /*!< [6..6] Power switch acknowledgement override from Power switch
20764                                                      to power control ST MC                                                    */
20765       __IOM uint32_t PWRACKOVERRIDEGFX : 1;     /*!< [7..7] Power switch acknowledgement override from Power switch
20766                                                      to power control ST MC                                                    */
20767       __IOM uint32_t PWRACKOVERRIDEHCPA : 1;    /*!< [8..8] Power switch acknowledgement override from Power switch
20768                                                      to power control ST MC                                                    */
20769       __IOM uint32_t PWRACKOVERRIDEHCPB : 1;    /*!< [9..9] Power switch acknowledgement override from Power switch
20770                                                      to power control ST MC                                                    */
20771       __IOM uint32_t PWRACKOVERRIDEHCPC : 1;    /*!< [10..10] Power switch acknowledgement override from Power switch
20772                                                      to power control ST MC                                                    */
20773       __IOM uint32_t PWRACKOVERRIDEIOS : 1;     /*!< [11..11] Power switch acknowledgement override from Power switch
20774                                                      to power control ST MC                                                    */
20775       __IOM uint32_t PWRACKOVERRIDEMCUL : 1;    /*!< [12..12] Power switch acknowledgement override from Power switch
20776                                                      to power control ST MC                                                    */
20777       __IOM uint32_t PWRACKOVERRIDEMSPI : 1;    /*!< [13..13] Power switch acknowledgement override from Power switch
20778                                                      to power control ST MC                                                    */
20779       __IOM uint32_t PWRACKOVERRIDESDIO : 1;    /*!< [14..14] Power switch acknowledgement override from Power switch
20780                                                      to power control ST MC                                                    */
20781       __IOM uint32_t PWRACKOVERRIDEUSB : 1;     /*!< [15..15] Power switch acknowledgement override from Power switch
20782                                                      to power control ST MC                                                    */
20783       __IOM uint32_t PWRACKOVERRIDEUSBPHY : 1;  /*!< [16..16] Power switch acknowledgement override from Power switch
20784                                                      to power control ST MC                                                    */
20785       __IOM uint32_t PWRACKOVERRIDEDSPA : 1;    /*!< [17..17] Power switch acknowledgement override from Power switch
20786                                                      to power control ST MC                                                    */
20787             uint32_t            : 14;
20788     } PWRACKOVR_b;
20789   } ;
20790 
20791   union {
20792     __IOM uint32_t PWRCNTDEFVAL;                /*!< (@ 0x00000088) This register contains programmble dealy values
20793                                                                     for various state michines. Fields contain
20794                                                                     dev st machine default value, SIMOBUCK state
20795                                                                     machine wait delay counter etc.                            */
20796 
20797     struct {
20798       __IOM uint32_t PWRDEFVALDEVSTMC : 6;      /*!< [5..0] Default count max value for dev ST MC                              */
20799       __IOM uint32_t PWRACKWAITDELSIMOSTMC : 10;/*!< [15..6] Default counter max for buck ST MC                                */
20800             uint32_t            : 16;
20801     } PWRCNTDEFVAL_b;
20802   } ;
20803   __IM  uint32_t  RESERVED3[29];
20804 
20805   union {
20806     __IOM uint32_t VRCTRL;                      /*!< (@ 0x00000100) This register includes additional debug control
20807                                                                     bits. This is an internal Ambiq-only register.
20808                                                                     Customers should not attempt to change this
20809                                                                     or else functionality cannot be guaranteed.                */
20810 
20811     struct {
20812       __IOM uint32_t SIMOBUCKEN : 1;            /*!< [0..0] Enables and Selects the SIMO Buck as the supply for the
20813                                                      low-voltage power domains. It takes the initial value from
20814                                                      the bit set in Customer INFO space.                                       */
20815             uint32_t            : 31;
20816     } VRCTRL_b;
20817   } ;
20818 
20819   union {
20820     __IOM uint32_t LEGACYVRLPOVR;               /*!< (@ 0x00000104) When an override is set for a power domain, VR
20821                                                                     logic will ignore that power domain state
20822                                                                     in making a decision to go into lp state.                  */
20823 
20824     struct {
20825       __IOM uint32_t IGNOREIOS  : 1;            /*!< [0..0] Ignore IOS                                                         */
20826       __IOM uint32_t IGNOREHCPA : 1;            /*!< [1..1] Ignore HCPA                                                        */
20827       __IOM uint32_t IGNOREHCPB : 1;            /*!< [2..2] Ignore HCPB                                                        */
20828       __IOM uint32_t IGNOREHCPC : 1;            /*!< [3..3] Ignore HCPC                                                        */
20829       __IOM uint32_t IGNOREHCPD : 1;            /*!< [4..4] Ignore HCPD                                                        */
20830       __IOM uint32_t IGNOREHCPE : 1;            /*!< [5..5] Ignore HCPE                                                        */
20831       __IOM uint32_t IGNOREMSPI : 1;            /*!< [6..6] Ignore MSPI                                                        */
20832       __IOM uint32_t IGNOREGFX  : 1;            /*!< [7..7] Ignore GFX                                                         */
20833       __IOM uint32_t IGNOREDISP : 1;            /*!< [8..8] Ignore DISP Control                                                */
20834       __IOM uint32_t IGNOREDISPPHY : 1;         /*!< [9..9] Ignore DISP PHY                                                    */
20835       __IOM uint32_t IGNORECRYPTO : 1;          /*!< [10..10] Ignore CRYPTO                                                    */
20836       __IOM uint32_t IGNORESDIO : 1;            /*!< [11..11] Ignore SDIO                                                      */
20837       __IOM uint32_t IGNOREUSB  : 1;            /*!< [12..12] Ignore USB Control                                               */
20838       __IOM uint32_t IGNOREUSBPHY : 1;          /*!< [13..13] Ignore USB PHY                                                   */
20839       __IOM uint32_t IGNOREAUD  : 1;            /*!< [14..14] Ignore AUD                                                       */
20840       __IOM uint32_t IGNOREDSPA : 1;            /*!< [15..15] Ignore DSPA                                                      */
20841       __IOM uint32_t IGNOREDSP0H : 1;           /*!< [16..16] Ignore DSP0H                                                     */
20842       __IOM uint32_t IGNOREDSP1H : 1;           /*!< [17..17] Ignore DSP1H                                                     */
20843       __IOM uint32_t IGNOREDBG  : 1;            /*!< [18..18] Ignore DBG                                                       */
20844             uint32_t            : 13;
20845     } LEGACYVRLPOVR_b;
20846   } ;
20847 
20848   union {
20849     __IOM uint32_t VRSTATUS;                    /*!< (@ 0x00000108) Provides BUCK and LDOs status.                             */
20850 
20851     struct {
20852       __IOM uint32_t CORELDOST  : 2;            /*!< [1..0] Indicates CORELDO status. bit[1] indicates ON/OFF and
20853                                                      bit[0] indicates ACT/LP.                                                  */
20854       __IOM uint32_t MEMLDOST   : 2;            /*!< [3..2] Indicates MEMLDO status. bit[1] indicates ON/OFF and
20855                                                      bit[0] indicates ACT/LP.                                                  */
20856       __IOM uint32_t SIMOBUCKST : 2;            /*!< [5..4] Indicates SIMO BUCK status. bit[1] indicates ON/OFF and
20857                                                      bit[0] indicates ACT/LP                                                   */
20858             uint32_t            : 26;
20859     } VRSTATUS_b;
20860   } ;
20861   __IM  uint32_t  RESERVED4[13];
20862 
20863   union {
20864     __IOM uint32_t PWRWEIGHTULP0;               /*!< (@ 0x00000140) Weights specified in this register are applied
20865                                                                     to each of the masters active requests.
20866                                                                     The aggregate of all the masters is compared
20867                                                                     against the allowed value to change the
20868                                                                     buck from active to inactive mode.                         */
20869 
20870     struct {
20871       __IOM uint32_t WTULPMCU   : 4;            /*!< [3..0] Weight used for ULP mode MCU                                       */
20872       __IOM uint32_t WTULPDSP0  : 4;            /*!< [7..4] Weight used for ULP mode DSP0                                      */
20873       __IOM uint32_t WTULPDSP1  : 4;            /*!< [11..8] Weight used for ULP mode DSP1                                     */
20874       __IOM uint32_t WTULPIOS   : 4;            /*!< [15..12] Weight used for ULP mode IOS                                     */
20875       __IOM uint32_t WTULPUART0 : 4;            /*!< [19..16] Weight used for ULP mode UART0                                   */
20876       __IOM uint32_t WTULPUART1 : 4;            /*!< [23..20] Weight used for ULP mode UART1                                   */
20877       __IOM uint32_t WTULPUART2 : 4;            /*!< [27..24] Weight used for ULP mode UART2                                   */
20878       __IOM uint32_t WTULPUART3 : 4;            /*!< [31..28] Weight used for ULP mode UART3                                   */
20879     } PWRWEIGHTULP0_b;
20880   } ;
20881 
20882   union {
20883     __IOM uint32_t PWRWEIGHTULP1;               /*!< (@ 0x00000144) Weights specified in this register are applied
20884                                                                     to each of the masters active requests.
20885                                                                     The aggregate of all the masters is compared
20886                                                                     against the allowed value to change the
20887                                                                     buck from active to inactive mode.                         */
20888 
20889     struct {
20890       __IOM uint32_t WTULPIOM0  : 4;            /*!< [3..0] Weight used for ULP mode IOM0                                      */
20891       __IOM uint32_t WTULPIOM1  : 4;            /*!< [7..4] Weight used for ULP mode IOM1                                      */
20892       __IOM uint32_t WTULPIOM2  : 4;            /*!< [11..8] Weight used for ULP mode IOM2                                     */
20893       __IOM uint32_t WTULPIOM3  : 4;            /*!< [15..12] Weight used for ULP mode IOM3                                    */
20894       __IOM uint32_t WTULPIOM4  : 4;            /*!< [19..16] Weight used for ULP mode IOM4                                    */
20895       __IOM uint32_t WTULPIOM5  : 4;            /*!< [23..20] Weight used for ULP mode IOM5                                    */
20896       __IOM uint32_t WTULPIOM6  : 4;            /*!< [27..24] Weight used for ULP mode IOM6                                    */
20897       __IOM uint32_t WTULPIOM7  : 4;            /*!< [31..28] Weight used for ULP mode IOM7                                    */
20898     } PWRWEIGHTULP1_b;
20899   } ;
20900 
20901   union {
20902     __IOM uint32_t PWRWEIGHTULP2;               /*!< (@ 0x00000148) Weights specified in this register are applied
20903                                                                     to each of the masters active requests.
20904                                                                     The aggregate of all the masters is compared
20905                                                                     against the allowed value to change the
20906                                                                     buck from active to inactive mode.                         */
20907 
20908     struct {
20909       __IOM uint32_t WTULPADC   : 4;            /*!< [3..0] Weight used for ULP mode ADC                                       */
20910       __IOM uint32_t WTULPMSPI0 : 4;            /*!< [7..4] Weight used for ULP mode MSPI0                                     */
20911       __IOM uint32_t WTULPMSPI1 : 4;            /*!< [11..8] Weight used for ULP mode MSPI1                                    */
20912       __IOM uint32_t WTULPGFX   : 4;            /*!< [15..12] Weight used for ULP mode GFX                                     */
20913       __IOM uint32_t WTULPDISP  : 4;            /*!< [19..16] Weight used for ULP mode DISP                                    */
20914       __IOM uint32_t WTULPCRYPTO : 4;           /*!< [23..20] Weight used for ULP mode CRYPTO                                  */
20915       __IOM uint32_t WTULPSDIO  : 4;            /*!< [27..24] Weight used for ULP mode SDIO                                    */
20916       __IOM uint32_t WTULPUSB   : 4;            /*!< [31..28] Weight used for ULP mode USB                                     */
20917     } PWRWEIGHTULP2_b;
20918   } ;
20919 
20920   union {
20921     __IOM uint32_t PWRWEIGHTULP3;               /*!< (@ 0x0000014C) Weights specified in this register are applied
20922                                                                     to each of the masters active requests.
20923                                                                     The aggregate of all the masters is compared
20924                                                                     against the allowed value to change the
20925                                                                     buck from active to inactive mode.                         */
20926 
20927     struct {
20928       __IOM uint32_t WTULPDSPA  : 4;            /*!< [3..0] Weight used for ULP mode DSPA                                      */
20929       __IOM uint32_t WTULPDBG   : 4;            /*!< [7..4] Weight used for ULP mode DBG                                       */
20930       __IOM uint32_t WTULPAUDREC : 4;           /*!< [11..8] Weight used for ULP mode AUDREC                                   */
20931       __IOM uint32_t WTULPAUDPB : 4;            /*!< [15..12] Weight used for ULP mode AUDPB                                   */
20932       __IOM uint32_t WTULPAUDADC : 4;           /*!< [19..16] Weight used for ULP mode AUDADC                                  */
20933       __IOM uint32_t WTULPI3C0  : 4;            /*!< [23..20] Weight used for ULP mode I3C0                                    */
20934       __IOM uint32_t WTULPI3C1  : 4;            /*!< [27..24] Weight used for ULP mode I3C1                                    */
20935       __IOM uint32_t WTULPMSPI2 : 4;            /*!< [31..28] Weight used for ULP mode MSPI2                                   */
20936     } PWRWEIGHTULP3_b;
20937   } ;
20938 
20939   union {
20940     __IOM uint32_t PWRWEIGHTULP4;               /*!< (@ 0x00000150) Weights specified in this register are applied
20941                                                                     to each of the masters active requests.
20942                                                                     The aggregate of all the masters is compared
20943                                                                     against the allowed value to change the
20944                                                                     buck from active to inactive mode.                         */
20945 
20946     struct {
20947       __IOM uint32_t WTULPI2S0  : 4;            /*!< [3..0] Weight used for ULP mode I2S0                                      */
20948       __IOM uint32_t WTULPI2S1  : 4;            /*!< [7..4] Weight used for ULP mode I2S1                                      */
20949             uint32_t            : 8;
20950       __IOM uint32_t WTULPPDM0  : 4;            /*!< [19..16] Weight used for ULP mode PDM0                                    */
20951       __IOM uint32_t WTULPPDM1  : 4;            /*!< [23..20] Weight used for ULP mode PDM1                                    */
20952       __IOM uint32_t WTULPPDM2  : 4;            /*!< [27..24] Weight used for ULP mode PDM2                                    */
20953       __IOM uint32_t WTULPPDM3  : 4;            /*!< [31..28] Weight used for ULP mode PDM3                                    */
20954     } PWRWEIGHTULP4_b;
20955   } ;
20956 
20957   union {
20958     __IOM uint32_t PWRWEIGHTULP5;               /*!< (@ 0x00000154) Weights specified in this register are applied
20959                                                                     to each of the masters active requests.
20960                                                                     The aggregate of all the masters is compared
20961                                                                     against the allowed value to change the
20962                                                                     buck from active to inactive mode.                         */
20963 
20964     struct {
20965       __IOM uint32_t WTULPDISPPHY : 4;          /*!< [3..0] Weight used for ULP mode DISP PHY                                  */
20966       __IOM uint32_t WTULPUSBPHY : 4;           /*!< [7..4] Weight used for ULP mode USB PHY                                   */
20967             uint32_t            : 24;
20968     } PWRWEIGHTULP5_b;
20969   } ;
20970 
20971   union {
20972     __IOM uint32_t PWRWEIGHTLP0;                /*!< (@ 0x00000158) Weights specified in this register are applied
20973                                                                     to each of the masters active requests.
20974                                                                     The aggregate of all the masters is compared
20975                                                                     against the allowed value to change the
20976                                                                     buck from active to inactive mode.                         */
20977 
20978     struct {
20979       __IOM uint32_t WTLPMCU    : 4;            /*!< [3..0] Weight used for LP mode MCU                                        */
20980       __IOM uint32_t WTLPDSP0   : 4;            /*!< [7..4] Weight used for LP mode DSP0                                       */
20981       __IOM uint32_t WTLPDSP1   : 4;            /*!< [11..8] Weight used for LP mode DSP1                                      */
20982       __IOM uint32_t WTLPIOS    : 4;            /*!< [15..12] Weight used for LP mode IOS                                      */
20983       __IOM uint32_t WTLPUART0  : 4;            /*!< [19..16] Weight used for LP mode UART0                                    */
20984       __IOM uint32_t WTLPUART1  : 4;            /*!< [23..20] Weight used for LP mode UART1                                    */
20985       __IOM uint32_t WTLPUART2  : 4;            /*!< [27..24] Weight used for LP mode UART2                                    */
20986       __IOM uint32_t WTLPUART3  : 4;            /*!< [31..28] Weight used for LP mode UART3                                    */
20987     } PWRWEIGHTLP0_b;
20988   } ;
20989 
20990   union {
20991     __IOM uint32_t PWRWEIGHTLP1;                /*!< (@ 0x0000015C) Weights specified in this register are applied
20992                                                                     to each of the masters active requests.
20993                                                                     The aggregate of all the masters is compared
20994                                                                     against the allowed value to change the
20995                                                                     buck from active to inactive mode.                         */
20996 
20997     struct {
20998       __IOM uint32_t WTLPIOM0   : 4;            /*!< [3..0] Weight used for LP mode IOM0                                       */
20999       __IOM uint32_t WTLPIOM1   : 4;            /*!< [7..4] Weight used for LP mode IOM1                                       */
21000       __IOM uint32_t WTLPIOM2   : 4;            /*!< [11..8] Weight used for LP mode IOM2                                      */
21001       __IOM uint32_t WTLPIOM3   : 4;            /*!< [15..12] Weight used for LP mode IOM3                                     */
21002       __IOM uint32_t WTLPIOM4   : 4;            /*!< [19..16] Weight used for LP mode IOM4                                     */
21003       __IOM uint32_t WTLPIOM5   : 4;            /*!< [23..20] Weight used for LP mode IOM5                                     */
21004       __IOM uint32_t WTLPIOM6   : 4;            /*!< [27..24] Weight used for LP mode IOM6                                     */
21005       __IOM uint32_t WTLPIOM7   : 4;            /*!< [31..28] Weight used for LP mode IOM7                                     */
21006     } PWRWEIGHTLP1_b;
21007   } ;
21008 
21009   union {
21010     __IOM uint32_t PWRWEIGHTLP2;                /*!< (@ 0x00000160) Weights specified in this register are applied
21011                                                                     to each of the masters active requests.
21012                                                                     The aggregate of all the masters is compared
21013                                                                     against the allowed value to change the
21014                                                                     buck from active to inactive mode.                         */
21015 
21016     struct {
21017       __IOM uint32_t WTLPADC    : 4;            /*!< [3..0] Weight used for LP mode ADC                                        */
21018       __IOM uint32_t WTLPMSPI0  : 4;            /*!< [7..4] Weight used for LP mode MSPI0                                      */
21019       __IOM uint32_t WTLPMSPI1  : 4;            /*!< [11..8] Weight used for LP mode MSPI1                                     */
21020       __IOM uint32_t WTLPGFX    : 4;            /*!< [15..12] Weight used for LP mode GFX                                      */
21021       __IOM uint32_t WTLPDISP   : 4;            /*!< [19..16] Weight used for LP mode DISP                                     */
21022       __IOM uint32_t WTLPCRYPTO : 4;            /*!< [23..20] Weight used for LP mode CRYPTO                                   */
21023       __IOM uint32_t WTLPSDIO   : 4;            /*!< [27..24] Weight used for LP mode SDIO                                     */
21024       __IOM uint32_t WTLPUSB    : 4;            /*!< [31..28] Weight used for LP mode USB                                      */
21025     } PWRWEIGHTLP2_b;
21026   } ;
21027 
21028   union {
21029     __IOM uint32_t PWRWEIGHTLP3;                /*!< (@ 0x00000164) Weights specified in this register are applied
21030                                                                     to each of the masters active requests.
21031                                                                     The aggregate of all the masters is compared
21032                                                                     against the allowed value to change the
21033                                                                     buck from active to inactive mode.                         */
21034 
21035     struct {
21036       __IOM uint32_t WTLPDSPA   : 4;            /*!< [3..0] Weight used for LP mode DSPA                                       */
21037       __IOM uint32_t WTLPDBG    : 4;            /*!< [7..4] Weight used for LP mode DBG                                        */
21038       __IOM uint32_t WTLPAUDREC : 4;            /*!< [11..8] Weight used for LP mode AUDREC                                    */
21039       __IOM uint32_t WTLPAUDPB  : 4;            /*!< [15..12] Weight used for LP mode AUDPB                                    */
21040       __IOM uint32_t WTLPAUDADC : 4;            /*!< [19..16] Weight used for LP mode AUDADC                                   */
21041       __IOM uint32_t WTLPI3C0   : 4;            /*!< [23..20] Weight used for LP mode I3C0                                     */
21042       __IOM uint32_t WTLPI3C1   : 4;            /*!< [27..24] Weight used for LP mode I3C1                                     */
21043       __IOM uint32_t WTLPMSPI2  : 4;            /*!< [31..28] Weight used for LP mode MSPI2                                    */
21044     } PWRWEIGHTLP3_b;
21045   } ;
21046 
21047   union {
21048     __IOM uint32_t PWRWEIGHTLP4;                /*!< (@ 0x00000168) Weights specified in this register are applied
21049                                                                     to each of the masters active requests.
21050                                                                     The aggregate of all the masters is compared
21051                                                                     against the allowed value to change the
21052                                                                     buck from active to inactive mode.                         */
21053 
21054     struct {
21055       __IOM uint32_t WTLPI2S0   : 4;            /*!< [3..0] Weight used for LP mode I2S0                                       */
21056       __IOM uint32_t WTLPI2S1   : 4;            /*!< [7..4] Weight used for LP mode I2S1                                       */
21057             uint32_t            : 8;
21058       __IOM uint32_t WTLPPDM0   : 4;            /*!< [19..16] Weight used for LP mode PDM0                                     */
21059       __IOM uint32_t WTLPPDM1   : 4;            /*!< [23..20] Weight used for LP mode PDM1                                     */
21060       __IOM uint32_t WTLPPDM2   : 4;            /*!< [27..24] Weight used for LP mode PDM2                                     */
21061       __IOM uint32_t WTLPPDM3   : 4;            /*!< [31..28] Weight used for LP mode PDM3                                     */
21062     } PWRWEIGHTLP4_b;
21063   } ;
21064 
21065   union {
21066     __IOM uint32_t PWRWEIGHTLP5;                /*!< (@ 0x0000016C) Weights specified in this register are applied
21067                                                                     to each of the masters active requests.
21068                                                                     The aggregate of all the masters is compared
21069                                                                     against the allowed value to change the
21070                                                                     buck from active to inactive mode.                         */
21071 
21072     struct {
21073       __IOM uint32_t WTLPDISPPHY : 4;           /*!< [3..0] Weight used for LP mode DISP PHY                                   */
21074       __IOM uint32_t WTLPUSBPHY : 4;            /*!< [7..4] Weight used for LP mode USB PHY                                    */
21075             uint32_t            : 24;
21076     } PWRWEIGHTLP5_b;
21077   } ;
21078 
21079   union {
21080     __IOM uint32_t PWRWEIGHTHP0;                /*!< (@ 0x00000170) Weights specified in this register are applied
21081                                                                     to each of the masters active requests.
21082                                                                     The aggregate of all the masters is compared
21083                                                                     against the allowed value to change the
21084                                                                     buck from active to inactive mode.                         */
21085 
21086     struct {
21087       __IOM uint32_t WTHPMCU    : 4;            /*!< [3..0] Weight used for HP mode MCU                                        */
21088       __IOM uint32_t WTHPDSP0   : 4;            /*!< [7..4] Weight used for HP mode DSP0                                       */
21089       __IOM uint32_t WTHPDSP1   : 4;            /*!< [11..8] Weight used for HP mode DSP1                                      */
21090       __IOM uint32_t WTHPIOS    : 4;            /*!< [15..12] Weight used for HP mode IOS                                      */
21091       __IOM uint32_t WTHPUART0  : 4;            /*!< [19..16] Weight used for HP mode UART0                                    */
21092       __IOM uint32_t WTHPUART1  : 4;            /*!< [23..20] Weight used for HP mode UART1                                    */
21093       __IOM uint32_t WTHPUART2  : 4;            /*!< [27..24] Weight used for HP mode UART2                                    */
21094       __IOM uint32_t WTHPUART3  : 4;            /*!< [31..28] Weight used for HP mode UART3                                    */
21095     } PWRWEIGHTHP0_b;
21096   } ;
21097 
21098   union {
21099     __IOM uint32_t PWRWEIGHTHP1;                /*!< (@ 0x00000174) Weights specified in this register are applied
21100                                                                     to each of the masters active requests.
21101                                                                     The aggregate of all the masters is compared
21102                                                                     against the allowed value to change the
21103                                                                     buck from active to inactive mode.                         */
21104 
21105     struct {
21106       __IOM uint32_t WTHPIOM0   : 4;            /*!< [3..0] Weight used for HP mode IOM0                                       */
21107       __IOM uint32_t WTHPIOM1   : 4;            /*!< [7..4] Weight used for HP mode IOM1                                       */
21108       __IOM uint32_t WTHPIOM2   : 4;            /*!< [11..8] Weight used for HP mode IOM2                                      */
21109       __IOM uint32_t WTHPIOM3   : 4;            /*!< [15..12] Weight used for HP mode IOM3                                     */
21110       __IOM uint32_t WTHPIOM4   : 4;            /*!< [19..16] Weight used for HP mode IOM4                                     */
21111       __IOM uint32_t WTHPIOM5   : 4;            /*!< [23..20] Weight used for HP mode IOM5                                     */
21112       __IOM uint32_t WTHPIOM6   : 4;            /*!< [27..24] Weight used for HP mode IOM6                                     */
21113       __IOM uint32_t WTHPIOM7   : 4;            /*!< [31..28] Weight used for HP mode IOM7                                     */
21114     } PWRWEIGHTHP1_b;
21115   } ;
21116 
21117   union {
21118     __IOM uint32_t PWRWEIGHTHP2;                /*!< (@ 0x00000178) Weights specified in this register are applied
21119                                                                     to each of the masters active requests.
21120                                                                     The aggregate of all the masters is compared
21121                                                                     against the allowed value to change the
21122                                                                     buck from active to inactive mode.                         */
21123 
21124     struct {
21125       __IOM uint32_t WTHPADC    : 4;            /*!< [3..0] Weight used for HP mode ADC                                        */
21126       __IOM uint32_t WTHPMSPI0  : 4;            /*!< [7..4] Weight used for HP mode MSPI0                                      */
21127       __IOM uint32_t WTHPMSPI1  : 4;            /*!< [11..8] Weight used for HP mode MSPI1                                     */
21128       __IOM uint32_t WTHPGFX    : 4;            /*!< [15..12] Weight used for HP mode GFX                                      */
21129       __IOM uint32_t WTHPDISP   : 4;            /*!< [19..16] Weight used for HP mode DISP                                     */
21130       __IOM uint32_t WTHPCRYPTO : 4;            /*!< [23..20] Weight used for HP mode CRYPTO                                   */
21131       __IOM uint32_t WTHPSDIO   : 4;            /*!< [27..24] Weight used for HP mode SDIO                                     */
21132       __IOM uint32_t WTHPUSB    : 4;            /*!< [31..28] Weight used for HP mode USB                                      */
21133     } PWRWEIGHTHP2_b;
21134   } ;
21135 
21136   union {
21137     __IOM uint32_t PWRWEIGHTHP3;                /*!< (@ 0x0000017C) Weights specified in this register are applied
21138                                                                     to each of the masters active requests.
21139                                                                     The aggregate of all the masters is compared
21140                                                                     against the allowed value to change the
21141                                                                     buck from active to inactive mode.                         */
21142 
21143     struct {
21144       __IOM uint32_t WTHPDSPA   : 4;            /*!< [3..0] Weight used for HP mode DSPA                                       */
21145       __IOM uint32_t WTHPDBG    : 4;            /*!< [7..4] Weight used for HP mode DBG                                        */
21146       __IOM uint32_t WTHPAUDREC : 4;            /*!< [11..8] Weight used for HP mode AUDREC                                    */
21147       __IOM uint32_t WTHPAUDPB  : 4;            /*!< [15..12] Weight used for HP mode AUDPB                                    */
21148       __IOM uint32_t WTHPAUDADC : 4;            /*!< [19..16] Weight used for HP mode AUDADC                                   */
21149       __IOM uint32_t WTHPI3C0   : 4;            /*!< [23..20] Weight used for HP mode I3C0                                     */
21150       __IOM uint32_t WTHPI3C1   : 4;            /*!< [27..24] Weight used for HP mode I3C1                                     */
21151       __IOM uint32_t WTHPMSPI2  : 4;            /*!< [31..28] Weight used for HP mode MSPI2                                    */
21152     } PWRWEIGHTHP3_b;
21153   } ;
21154 
21155   union {
21156     __IOM uint32_t PWRWEIGHTHP4;                /*!< (@ 0x00000180) Weights specified in this register are applied
21157                                                                     to each of the masters active requests.
21158                                                                     The aggregate of all the masters is compared
21159                                                                     against the allowed value to change the
21160                                                                     buck from active to inactive mode.                         */
21161 
21162     struct {
21163       __IOM uint32_t WTHPI2S0   : 4;            /*!< [3..0] Weight used for HP mode I2S0                                       */
21164       __IOM uint32_t WTHPI2S1   : 4;            /*!< [7..4] Weight used for HP mode I2S1                                       */
21165             uint32_t            : 8;
21166       __IOM uint32_t WTHPPDM0   : 4;            /*!< [19..16] Weight used for HP mode PDM0                                     */
21167       __IOM uint32_t WTHPPDM1   : 4;            /*!< [23..20] Weight used for HP mode PDM1                                     */
21168       __IOM uint32_t WTHPPDM2   : 4;            /*!< [27..24] Weight used for HP mode PDM2                                     */
21169       __IOM uint32_t WTHPPDM3   : 4;            /*!< [31..28] Weight used for HP mode PDM3                                     */
21170     } PWRWEIGHTHP4_b;
21171   } ;
21172 
21173   union {
21174     __IOM uint32_t PWRWEIGHTHP5;                /*!< (@ 0x00000184) Weights specified in this register are applied
21175                                                                     to each of the masters active requests.
21176                                                                     The aggregate of all the masters is compared
21177                                                                     against the allowed value to change the
21178                                                                     buck from active to inactive mode.                         */
21179 
21180     struct {
21181       __IOM uint32_t WTHPDISPPHY : 4;           /*!< [3..0] Weight used for HP mode DISP PHY                                   */
21182       __IOM uint32_t WTHPUSBPHY : 4;            /*!< [7..4] Weight used for HP mode USB PHY                                    */
21183             uint32_t            : 24;
21184     } PWRWEIGHTHP5_b;
21185   } ;
21186 
21187   union {
21188     __IOM uint32_t PWRWEIGHTSLP;                /*!< (@ 0x00000188) Weights specified in this register are applied
21189                                                                     to each of the masters active requests.
21190                                                                     The aggregate of all the masters is compared
21191                                                                     against the allowed value to change the
21192                                                                     buck from active to inactive mode.                         */
21193 
21194     struct {
21195       __IOM uint32_t WTDSMCU    : 4;            /*!< [3..0] Weight used for Deep Sleep mode MCU                                */
21196             uint32_t            : 28;
21197     } PWRWEIGHTSLP_b;
21198   } ;
21199 
21200   union {
21201     __IOM uint32_t VRDEMOTIONTHR;               /*!< (@ 0x0000018C) Weights specified in PWRWEIGHT* registers are
21202                                                                     applied to each of the masters active requests.
21203                                                                     The aggregate of all the masters is compared
21204                                                                     against the this threshold value to change
21205                                                                     the buck from active to inactive mode.                     */
21206 
21207     struct {
21208       __IOM uint32_t VRDEMOTIONTHR : 32;        /*!< [31..0] VR Demotion Threshold                                             */
21209     } VRDEMOTIONTHR_b;
21210   } ;
21211 
21212   union {
21213     __IOM uint32_t SRAMCTRL;                    /*!< (@ 0x00000190) This register provides additional fine-tune power
21214                                                                     management controls for the SRAMs and the
21215                                                                     SRAM controller. This includes enabling
21216                                                                     light sleep for the SRAM and TCM banks,
21217                                                                     and clock gating for reduced dynamic power.                */
21218 
21219     struct {
21220             uint32_t            : 1;
21221       __IOM uint32_t SRAMCLKGATE : 1;           /*!< [1..1] This bit is 1 if clock gating is allowed for individual
21222                                                      system SRAMs                                                              */
21223       __IOM uint32_t SRAMMASTERCLKGATE : 1;     /*!< [2..2] This bit is 1 when the master clock gate is enabled (top-level
21224                                                      clock gate for entire SRAM block)                                         */
21225             uint32_t            : 5;
21226       __IOM uint32_t SRAMLIGHTSLEEP : 12;       /*!< [19..8] Light Sleep enable for each TCM/SRAM bank. When 1, corresponding
21227                                                      bank will be put into light sleep. For optimal power, banks
21228                                                      should be put into light sleep while the system is active
21229                                                      but the bank has minimal or no accesses.                                  */
21230             uint32_t            : 12;
21231     } SRAMCTRL_b;
21232   } ;
21233 
21234   union {
21235     __IOM uint32_t ADCSTATUS;                   /*!< (@ 0x00000194) This provides the power status for various blocks
21236                                                                     within the ADC. These status comes directly
21237                                                                     from the ADC module and is captured through
21238                                                                     this interface.                                            */
21239 
21240     struct {
21241       __IOM uint32_t ADCPWD     : 1;            /*!< [0..0] This bit indicates that the ADC is powered down                    */
21242       __IOM uint32_t BGTPWD     : 1;            /*!< [1..1] This bit indicates that the ADC Band Gap is powered down           */
21243       __IOM uint32_t VPTATPWD   : 1;            /*!< [2..2] This bit indicates that the ADC temperature sensor input
21244                                                      buffer is powered down                                                    */
21245       __IOM uint32_t VBATPWD    : 1;            /*!< [3..3] This bit indicates that the ADC VBAT resistor divider
21246                                                      is powered down                                                           */
21247       __IOM uint32_t REFKEEPPWD : 1;            /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down            */
21248       __IOM uint32_t REFBUFPWD  : 1;            /*!< [5..5] This bit indicates that the ADC REFBUF is powered down             */
21249             uint32_t            : 26;
21250     } ADCSTATUS_b;
21251   } ;
21252 
21253   union {
21254     __IOM uint32_t AUDADCSTATUS;                /*!< (@ 0x00000198) This provides the power status for various blocks
21255                                                                     within the audio ADC. These status comes
21256                                                                     directly from the audio ADC module and is
21257                                                                     captured through this interface.                           */
21258 
21259     struct {
21260       __IOM uint32_t AUDADCPWD  : 1;            /*!< [0..0] This bit indicates that the ADC is powered down                    */
21261       __IOM uint32_t AUDBGTPWD  : 1;            /*!< [1..1] This bit indicates that the ADC Band Gap is powered down           */
21262       __IOM uint32_t AUDVPTATPWD : 1;           /*!< [2..2] This bit indicates that the ADC temperature sensor input
21263                                                      buffer is powered down                                                    */
21264       __IOM uint32_t AUDVBATPWD : 1;            /*!< [3..3] This bit indicates that the ADC VBAT resistor divider
21265                                                      is powered down                                                           */
21266       __IOM uint32_t AUDREFKEEPPWD : 1;         /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down            */
21267       __IOM uint32_t AUDREFBUFPWD : 1;          /*!< [5..5] This bit indicates that the ADC REFBUF is powered down             */
21268             uint32_t            : 26;
21269     } AUDADCSTATUS_b;
21270   } ;
21271   __IM  uint32_t  RESERVED5[25];
21272 
21273   union {
21274     __IOM uint32_t EMONCTRL;                    /*!< (@ 0x00000200) Controls each of the energy monitor conuters               */
21275 
21276     struct {
21277       __IOM uint32_t FREEZE     : 8;            /*!< [7..0] Freeze the counter. Each bit corresponds to a counter.
21278                                                      0: Let the counter run. 1: Stop the counter.                              */
21279       __IOM uint32_t CLEAR      : 8;            /*!< [15..8] Clear the counter. Each bit corresponds to a counter.
21280                                                      0: Let the counter run run on its input clk. 1: Clear the
21281                                                      counter                                                                   */
21282             uint32_t            : 16;
21283     } EMONCTRL_b;
21284   } ;
21285 
21286   union {
21287     __IOM uint32_t EMONCFG0;                    /*!< (@ 0x00000204) The counter increments when the counter is enabled
21288                                                                     and the mode selected here matches the power
21289                                                                     mode.                                                      */
21290 
21291     struct {
21292       __IOM uint32_t EMONSEL0   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21293             uint32_t            : 24;
21294     } EMONCFG0_b;
21295   } ;
21296 
21297   union {
21298     __IOM uint32_t EMONCFG1;                    /*!< (@ 0x00000208) The counter increments when the counter is enabled
21299                                                                     and the mode selected here matches the power
21300                                                                     mode.                                                      */
21301 
21302     struct {
21303       __IOM uint32_t EMONSEL1   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21304             uint32_t            : 24;
21305     } EMONCFG1_b;
21306   } ;
21307 
21308   union {
21309     __IOM uint32_t EMONCFG2;                    /*!< (@ 0x0000020C) The counter increments when the counter is enabled
21310                                                                     and the mode selected here matches the power
21311                                                                     mode.                                                      */
21312 
21313     struct {
21314       __IOM uint32_t EMONSEL2   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21315             uint32_t            : 24;
21316     } EMONCFG2_b;
21317   } ;
21318 
21319   union {
21320     __IOM uint32_t EMONCFG3;                    /*!< (@ 0x00000210) The counter increments when the counter is enabled
21321                                                                     and the mode selected here matches the power
21322                                                                     mode.                                                      */
21323 
21324     struct {
21325       __IOM uint32_t EMONSEL3   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21326             uint32_t            : 24;
21327     } EMONCFG3_b;
21328   } ;
21329 
21330   union {
21331     __IOM uint32_t EMONCFG4;                    /*!< (@ 0x00000214) The counter increments when the counter is enabled
21332                                                                     and the mode selected here matches the power
21333                                                                     mode.                                                      */
21334 
21335     struct {
21336       __IOM uint32_t EMONSEL4   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21337             uint32_t            : 24;
21338     } EMONCFG4_b;
21339   } ;
21340 
21341   union {
21342     __IOM uint32_t EMONCFG5;                    /*!< (@ 0x00000218) The counter increments when the counter is enabled
21343                                                                     and the mode selected here matches the power
21344                                                                     mode.                                                      */
21345 
21346     struct {
21347       __IOM uint32_t EMONSEL5   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21348             uint32_t            : 24;
21349     } EMONCFG5_b;
21350   } ;
21351 
21352   union {
21353     __IOM uint32_t EMONCFG6;                    /*!< (@ 0x0000021C) The counter increments when the counter is enabled
21354                                                                     and the mode selected here matches the power
21355                                                                     mode.                                                      */
21356 
21357     struct {
21358       __IOM uint32_t EMONSEL6   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21359             uint32_t            : 24;
21360     } EMONCFG6_b;
21361   } ;
21362 
21363   union {
21364     __IOM uint32_t EMONCFG7;                    /*!< (@ 0x00000220) The counter increments when the counter is enabled
21365                                                                     and the mode selected here matches the power
21366                                                                     mode.                                                      */
21367 
21368     struct {
21369       __IOM uint32_t EMONSEL7   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
21370             uint32_t            : 24;
21371     } EMONCFG7_b;
21372   } ;
21373   __IM  uint32_t  RESERVED6;
21374 
21375   union {
21376     __IOM uint32_t EMONCOUNT0;                  /*!< (@ 0x00000228) Energy Monitor count value for counter 0                   */
21377 
21378     struct {
21379       __IOM uint32_t EMONCOUNT0 : 32;           /*!< [31..0] Energy Monitor count value counter 0                              */
21380     } EMONCOUNT0_b;
21381   } ;
21382 
21383   union {
21384     __IOM uint32_t EMONCOUNT1;                  /*!< (@ 0x0000022C) Energy Monitor count value for counter 1                   */
21385 
21386     struct {
21387       __IOM uint32_t EMONCOUNT1 : 32;           /*!< [31..0] Energy Monitor count value counter 1                              */
21388     } EMONCOUNT1_b;
21389   } ;
21390 
21391   union {
21392     __IOM uint32_t EMONCOUNT2;                  /*!< (@ 0x00000230) Energy Monitor count value for counter 2                   */
21393 
21394     struct {
21395       __IOM uint32_t EMONCOUNT2 : 32;           /*!< [31..0] Energy Monitor count value counter 2                              */
21396     } EMONCOUNT2_b;
21397   } ;
21398 
21399   union {
21400     __IOM uint32_t EMONCOUNT3;                  /*!< (@ 0x00000234) Energy Monitor count value for counter 3                   */
21401 
21402     struct {
21403       __IOM uint32_t EMONCOUNT3 : 32;           /*!< [31..0] Energy Monitor count value counter 3                              */
21404     } EMONCOUNT3_b;
21405   } ;
21406 
21407   union {
21408     __IOM uint32_t EMONCOUNT4;                  /*!< (@ 0x00000238) Energy Monitor count value for counter 4                   */
21409 
21410     struct {
21411       __IOM uint32_t EMONCOUNT4 : 32;           /*!< [31..0] Energy Monitor count value counter 4                              */
21412     } EMONCOUNT4_b;
21413   } ;
21414 
21415   union {
21416     __IOM uint32_t EMONCOUNT5;                  /*!< (@ 0x0000023C) Energy Monitor count value for counter 5                   */
21417 
21418     struct {
21419       __IOM uint32_t EMONCOUNT5 : 32;           /*!< [31..0] Energy Monitor count value counter 5                              */
21420     } EMONCOUNT5_b;
21421   } ;
21422 
21423   union {
21424     __IOM uint32_t EMONCOUNT6;                  /*!< (@ 0x00000240) Energy Monitor count value for counter 6                   */
21425 
21426     struct {
21427       __IOM uint32_t EMONCOUNT6 : 32;           /*!< [31..0] Energy Monitor count value counter 6                              */
21428     } EMONCOUNT6_b;
21429   } ;
21430 
21431   union {
21432     __IOM uint32_t EMONCOUNT7;                  /*!< (@ 0x00000244) Energy Monitor count value for counter 7                   */
21433 
21434     struct {
21435       __IOM uint32_t EMONCOUNT7 : 32;           /*!< [31..0] Energy Monitor count value counter 7                              */
21436     } EMONCOUNT7_b;
21437   } ;
21438   __IM  uint32_t  RESERVED7;
21439 
21440   union {
21441     __IOM uint32_t EMONSTATUS;                  /*!< (@ 0x0000024C) Energy Monitor status                                      */
21442 
21443     struct {
21444       __IOM uint32_t EMONOVERFLOW0 : 1;         /*!< [0..0] Energy Monitor counter0 overflow                                   */
21445       __IOM uint32_t EMONOVERFLOW1 : 1;         /*!< [1..1] Energy Monitor counter1 overflow                                   */
21446       __IOM uint32_t EMONOVERFLOW2 : 1;         /*!< [2..2] Energy Monitor counter2 overflow                                   */
21447       __IOM uint32_t EMONOVERFLOW3 : 1;         /*!< [3..3] Energy Monitor counter3 overflow                                   */
21448       __IOM uint32_t EMONOVERFLOW4 : 1;         /*!< [4..4] Energy Monitor counter4 overflow                                   */
21449       __IOM uint32_t EMONOVERFLOW5 : 1;         /*!< [5..5] Energy Monitor counter5 overflow                                   */
21450       __IOM uint32_t EMONOVERFLOW6 : 1;         /*!< [6..6] Energy Monitor counter6 overflow                                   */
21451       __IOM uint32_t EMONOVERFLOW7 : 1;         /*!< [7..7] Energy Monitor counter7 overflow                                   */
21452             uint32_t            : 24;
21453     } EMONSTATUS_b;
21454   } ;
21455 } PWRCTRL_Type;                                 /*!< Size = 592 (0x250)                                                        */
21456 
21457 
21458 
21459 /* =========================================================================================================================== */
21460 /* ================                                          RSTGEN                                           ================ */
21461 /* =========================================================================================================================== */
21462 
21463 
21464 /**
21465   * @brief MCU Reset Generator (RSTGEN)
21466   */
21467 
21468 typedef struct {                                /*!< (@ 0x40000000) RSTGEN Structure                                           */
21469 
21470   union {
21471     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) Reset configuration register. This controls the
21472                                                                     reset enables for brownout condition, choice
21473                                                                     of brownout method and for the expiration
21474                                                                     of the watch dog timer.                                    */
21475 
21476     struct {
21477       __IOM uint32_t BODHREN    : 1;            /*!< [0..0] Brown out high (2.1v) reset enable. Note - Enabling this
21478                                                      bit for Apollo4, which operates at 1.8v/1.9v, will cause
21479                                                      a continual reset loop.                                                   */
21480       __IOM uint32_t WDREN      : 1;            /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must
21481                                                      also be configured for WDT reset. This includes enabling
21482                                                      the RESEN bit in WDTCFG register in Watch dog timer block.                */
21483             uint32_t            : 30;
21484     } CFG_b;
21485   } ;
21486 
21487   union {
21488     __IOM uint32_t SWPOI;                       /*!< (@ 0x00000004) This is the software POI reset. writing the key
21489                                                                     value to this register will trigger a POI
21490                                                                     to the system. This will cause a reset to
21491                                                                     all blocks except for registers in clock
21492                                                                     gen, RTC and the stimer.                                   */
21493 
21494     struct {
21495       __IOM uint32_t SWPOIKEY   : 8;            /*!< [7..0] 0x1B generates a software POI reset. This is a write-only
21496                                                      register. Reading from this register will yield only all
21497                                                      0s.                                                                       */
21498             uint32_t            : 24;
21499     } SWPOI_b;
21500   } ;
21501 
21502   union {
21503     __IOM uint32_t SWPOR;                       /*!< (@ 0x00000008) This is the software POR reset. Writing the key
21504                                                                     value to this register will trigger a POR
21505                                                                     to the system. This will cause a reset to
21506                                                                     all blocks except for registers in clock
21507                                                                     gen, RTC, power management unit, the stimer,
21508                                                                     and the power management unit.                             */
21509 
21510     struct {
21511       __IOM uint32_t SWPORKEY   : 8;            /*!< [7..0] 0xD4 generates a software POR reset.                               */
21512             uint32_t            : 24;
21513     } SWPOR_b;
21514   } ;
21515   __IM  uint32_t  RESERVED[2];
21516 
21517   union {
21518     __IOM uint32_t SIMOBODM;                    /*!< (@ 0x00000014) This register unmasks the individual digital
21519                                                                     detection brownout bits into the interrupt
21520                                                                     block                                                      */
21521 
21522     struct {
21523       __IOM uint32_t DIGBOEC    : 1;            /*!< [0..0] Enable the gate into the interrupt block for the digital
21524                                                      brownout detection on VDDC. Note: The interrupt block must
21525                                                      also be unmasked for ISR and interrupt status to be set                   */
21526       __IOM uint32_t DIGBOEF    : 1;            /*!< [1..1] Enable the gate into the interrupt block for the digital
21527                                                      brownout detection on VDDF. Note: The interrupt block must
21528                                                      also be unmasked for ISR and interrupt status to be set                   */
21529       __IOM uint32_t DIGBOES    : 1;            /*!< [2..2] Enable the gate into the interrupt block for the digital
21530                                                      brownout detection on VDDS. Note: The interrupt block must
21531                                                      also be unmasked for ISR and interrupt status to be set                   */
21532       __IOM uint32_t DIGBOECLV  : 1;            /*!< [3..3] Enable the gate into the interrupt block for the digital
21533                                                      brownout detection on VDDC_LV. Note: The interrupt block
21534                                                      must also be unmasked for ISR and interrupt status to be
21535                                                      set                                                                       */
21536             uint32_t            : 28;
21537     } SIMOBODM_b;
21538   } ;
21539   __IM  uint32_t  RESERVED1[122];
21540 
21541   union {
21542     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
21543                                                                     to generate the corresponding interrupt.                   */
21544 
21545     struct {
21546       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
21547                                                      BODH level.                                                               */
21548       __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
21549                                                      detects inactivity on VDDC                                                */
21550       __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
21551                                                      detects inactivity on VDDF                                                */
21552       __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
21553                                                      detects inactivity on VDDS                                                */
21554       __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
21555                                                      detects inactivity on VDDC_LV                                             */
21556             uint32_t            : 27;
21557     } INTEN_b;
21558   } ;
21559 
21560   union {
21561     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
21562                                                                     cause of a recent interrupt.                               */
21563 
21564     struct {
21565       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
21566                                                      BODH level.                                                               */
21567       __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
21568                                                      detects inactivity on VDDC                                                */
21569       __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
21570                                                      detects inactivity on VDDF                                                */
21571       __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
21572                                                      detects inactivity on VDDS                                                */
21573       __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
21574                                                      detects inactivity on VDDC_LV                                             */
21575             uint32_t            : 27;
21576     } INTSTAT_b;
21577   } ;
21578 
21579   union {
21580     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
21581                                                                     the interrupt status associated with that
21582                                                                     bit.                                                       */
21583 
21584     struct {
21585       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
21586                                                      BODH level.                                                               */
21587       __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
21588                                                      detects inactivity on VDDC                                                */
21589       __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
21590                                                      detects inactivity on VDDF                                                */
21591       __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
21592                                                      detects inactivity on VDDS                                                */
21593       __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
21594                                                      detects inactivity on VDDC_LV                                             */
21595             uint32_t            : 27;
21596     } INTCLR_b;
21597   } ;
21598 
21599   union {
21600     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
21601                                                                     generate an interrupt from this module.
21602                                                                     (Generally used for testing purposes).                     */
21603 
21604     struct {
21605       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
21606                                                      BODH level.                                                               */
21607       __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
21608                                                      detects inactivity on VDDC                                                */
21609       __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
21610                                                      detects inactivity on VDDF                                                */
21611       __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
21612                                                      detects inactivity on VDDS                                                */
21613       __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
21614                                                      detects inactivity on VDDC_LV                                             */
21615             uint32_t            : 27;
21616     } INTSET_b;
21617   } ;
21618   __IM  uint32_t  RESERVED2[8595];
21619 
21620   union {
21621     __IOM uint32_t STAT;                        /*!< (@ 0x0000885C) This register contains the status for brownout
21622                                                                     events and the causes for resets.
21623                                                                     NOTE 1: All bits in this register, including
21624                                                                     reserved bits, are writable. Therefore care
21625                                                                     should be taken not to write this register.
21626                                                                     NOTE 2: This register is only reset by POI
21627                                                                     not by HRESETn. Its contents are intended
21628                                                                     to survive all reset level except POI and
21629                                                                     full power cycles.                                         */
21630 
21631     struct {
21632       __IOM uint32_t EXRSTAT    : 1;            /*!< [0..0] Reset was initiated by an External Reset.                          */
21633       __IOM uint32_t PORSTAT    : 1;            /*!< [1..1] Reset was initiated by a Power-On Reset.                           */
21634       __IOM uint32_t BORSTAT    : 1;            /*!< [2..2] Reset was initiated by a Brown-Out Reset.                          */
21635       __IOM uint32_t SWRSTAT    : 1;            /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset.                    */
21636       __IOM uint32_t POIRSTAT   : 1;            /*!< [4..4] Reset was a initiated by Software POI Reset.                       */
21637       __IOM uint32_t DBGRSTAT   : 1;            /*!< [5..5] Reset was a initiated by Debugger Reset.                           */
21638       __IOM uint32_t WDRSTAT    : 1;            /*!< [6..6] Reset was initiated by a Watchdog Timer Reset.                     */
21639       __IOM uint32_t BOUSTAT    : 1;            /*!< [7..7] An Unregulated Supply Brownout Event occured.                      */
21640       __IOM uint32_t BOCSTAT    : 1;            /*!< [8..8] VDDC Analog Brownout Event occured.                                */
21641       __IOM uint32_t BOFSTAT    : 1;            /*!< [9..9] VDDF Analog Brownout Event occured.                                */
21642       __IOM uint32_t BOSSTAT    : 1;            /*!< [10..10] VDDS Analog Brownout Event occured.                              */
21643             uint32_t            : 21;
21644     } STAT_b;
21645   } ;
21646 } RSTGEN_Type;                                  /*!< Size = 34912 (0x8860)                                                     */
21647 
21648 
21649 
21650 /* =========================================================================================================================== */
21651 /* ================                                            RTC                                            ================ */
21652 /* =========================================================================================================================== */
21653 
21654 
21655 /**
21656   * @brief Real Time Clock (RTC)
21657   */
21658 
21659 typedef struct {                                /*!< (@ 0x40004800) RTC Structure                                              */
21660 
21661   union {
21662     __IOM uint32_t RTCCTL;                      /*!< (@ 0x00000000) This is the register control for the RTC module.
21663                                                                     It enables counter writes and sets the alarm
21664                                                                     repeat interval.                                           */
21665 
21666     struct {
21667       __IOM uint32_t WRTC       : 1;            /*!< [0..0] Counter write control                                              */
21668       __IOM uint32_t RPT        : 3;            /*!< [3..1] Alarm repeat interval                                              */
21669       __IOM uint32_t RSTOP      : 1;            /*!< [4..4] RTC input clock control                                            */
21670       __IOM uint32_t HR1224     : 1;            /*!< [5..5] Hours Counter mode Only 24HR mode supported                        */
21671             uint32_t            : 26;
21672     } RTCCTL_b;
21673   } ;
21674 
21675   union {
21676     __IOM uint32_t RTCSTAT;                     /*!< (@ 0x00000004) This is the register status for the RTC module.            */
21677 
21678     struct {
21679       __IOM uint32_t WRITEBUSY  : 1;            /*!< [0..0] Indicates that an RTC update (write) is still in progress.
21680                                                      Writes are initiated by writing the CTTLOW register - CTRUP
21681                                                      must be written before CTRLOW to be updated (otherwise
21682                                                      it will retain its current value)                                         */
21683             uint32_t            : 31;
21684     } RTCSTAT_b;
21685   } ;
21686   __IM  uint32_t  RESERVED[6];
21687 
21688   union {
21689     __IOM uint32_t CTRLOW;                      /*!< (@ 0x00000020) This counter contains the values for hour, minutes,
21690                                                                     seconds and 100ths of a second Counter.                    */
21691 
21692     struct {
21693       __IOM uint32_t CTR100     : 8;            /*!< [7..0] 100ths of a second Counter                                         */
21694       __IOM uint32_t CTRSEC     : 7;            /*!< [14..8] Seconds Counter                                                   */
21695             uint32_t            : 1;
21696       __IOM uint32_t CTRMIN     : 7;            /*!< [22..16] Minutes Counter                                                  */
21697             uint32_t            : 1;
21698       __IOM uint32_t CTRHR      : 6;            /*!< [29..24] Hours Counter                                                    */
21699             uint32_t            : 2;
21700     } CTRLOW_b;
21701   } ;
21702 
21703   union {
21704     __IOM uint32_t CTRUP;                       /*!< (@ 0x00000024) This register contains the day, month and year
21705                                                                     information. It contains which day in the
21706                                                                     week, and the century as well. The information
21707                                                                     of the century can also be derived from
21708                                                                     the year information. The 31st bit contains
21709                                                                     the error bit. See description in the register
21710                                                                     bit for condition when error is triggered.                 */
21711 
21712     struct {
21713       __IOM uint32_t CTRDATE    : 6;            /*!< [5..0] Date Counter                                                       */
21714             uint32_t            : 2;
21715       __IOM uint32_t CTRMO      : 5;            /*!< [12..8] Months Counter                                                    */
21716             uint32_t            : 3;
21717       __IOM uint32_t CTRYR      : 8;            /*!< [23..16] Years Counter                                                    */
21718       __IOM uint32_t CTRWKDY    : 3;            /*!< [26..24] Weekdays Counter                                                 */
21719             uint32_t            : 1;
21720       __IOM uint32_t CB         : 1;            /*!< [28..28] Century                                                          */
21721       __IOM uint32_t CEB        : 1;            /*!< [29..29] Century enable                                                   */
21722             uint32_t            : 1;
21723       __IOM uint32_t CTERR      : 1;            /*!< [31..31] Counter read error status. Error is triggered when
21724                                                      software reads the lower word of the counters, and fails
21725                                                      to read the upper counter within 1/100 second. This is
21726                                                      because when the lower counter is read, the upper counter
21727                                                      is held off from incrementing until it is read so that
21728                                                      the full time stamp can be read.                                          */
21729     } CTRUP_b;
21730   } ;
21731   __IM  uint32_t  RESERVED1[2];
21732 
21733   union {
21734     __IOM uint32_t ALMLOW;                      /*!< (@ 0x00000030) This register is the Alarm settings for hours,
21735                                                                     minutes, second and 1/100th seconds settings.              */
21736 
21737     struct {
21738       __IOM uint32_t ALM100     : 8;            /*!< [7..0] 100ths of a second Alarm                                           */
21739       __IOM uint32_t ALMSEC     : 7;            /*!< [14..8] Seconds Alarm                                                     */
21740             uint32_t            : 1;
21741       __IOM uint32_t ALMMIN     : 7;            /*!< [22..16] Minutes Alarm                                                    */
21742             uint32_t            : 1;
21743       __IOM uint32_t ALMHR      : 6;            /*!< [29..24] Hours Alarm                                                      */
21744             uint32_t            : 2;
21745     } ALMLOW_b;
21746   } ;
21747 
21748   union {
21749     __IOM uint32_t ALMUP;                       /*!< (@ 0x00000034) This register is the alarm settings for week,
21750                                                                     month and day.                                             */
21751 
21752     struct {
21753       __IOM uint32_t ALMDATE    : 6;            /*!< [5..0] Date Alarm                                                         */
21754             uint32_t            : 2;
21755       __IOM uint32_t ALMMO      : 5;            /*!< [12..8] Months Alarm                                                      */
21756             uint32_t            : 3;
21757       __IOM uint32_t ALMWKDY    : 3;            /*!< [18..16] Weekdays Alarm                                                   */
21758             uint32_t            : 13;
21759     } ALMUP_b;
21760   } ;
21761   __IM  uint32_t  RESERVED2[114];
21762 
21763   union {
21764     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
21765                                                                     to generate the corresponding interrupt.                   */
21766 
21767     struct {
21768       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
21769             uint32_t            : 31;
21770     } INTEN_b;
21771   } ;
21772 
21773   union {
21774     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
21775                                                                     cause of a recent interrupt.                               */
21776 
21777     struct {
21778       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
21779             uint32_t            : 31;
21780     } INTSTAT_b;
21781   } ;
21782 
21783   union {
21784     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
21785                                                                     the interrupt status associated with that
21786                                                                     bit.                                                       */
21787 
21788     struct {
21789       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
21790             uint32_t            : 31;
21791     } INTCLR_b;
21792   } ;
21793 
21794   union {
21795     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
21796                                                                     generate an interrupt from this module.
21797                                                                     (Generally used for testing purposes).                     */
21798 
21799     struct {
21800       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
21801             uint32_t            : 31;
21802     } INTSET_b;
21803   } ;
21804 } RTC_Type;                                     /*!< Size = 528 (0x210)                                                        */
21805 
21806 
21807 
21808 /* =========================================================================================================================== */
21809 /* ================                                           SDIO                                            ================ */
21810 /* =========================================================================================================================== */
21811 
21812 
21813 /**
21814   * @brief SDIO Control Registers (SDIO)
21815   */
21816 
21817 typedef struct {                                /*!< (@ 0x40070000) SDIO Structure                                             */
21818 
21819   union {
21820     __IOM uint32_t SDMA;                        /*!< (@ 0x00000000) SDMA system address                                        */
21821 
21822     struct {
21823       __IOM uint32_t SDMASYSTEMADDRESS : 32;    /*!< [31..0] This register contains the physical system memory address
21824                                                      used for DMA transfers or the second argument for the Auto
21825                                                      CMD23. (1) SDMA System Address This register contains the
21826                                                      system memory address for a SDMA transfer. When the Host
21827                                                      Controller stops a SDMA transfer, this register shall point
21828                                                      to the system address of the next contiguous data position.
21829                                                      It can be accessed only if no transaction is executing
21830                                                      (i.e., after a transaction has stopped). Read operations
21831                                                      during transfers may return an invalid value. T                           */
21832     } SDMA_b;
21833   } ;
21834 
21835   union {
21836     __IOM uint32_t BLOCK;                       /*!< (@ 0x00000004) Block size                                                 */
21837 
21838     struct {
21839       __IOM uint32_t TRANSFERBLOCKSIZE : 12;    /*!< [11..0] This register specifies the block size for block data
21840                                                      transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. It
21841                                                      can be accessed only if no transaction is executing (i.e
21842                                                      after a transaction has stopped). Read operations during
21843                                                      transfer return an invalid value and write operations shall
21844                                                      be ignored.                                                               */
21845       __IOM uint32_t HOSTSDMABUFSZ : 3;         /*!< [14..12] To perform long DMA transfer, System Address register
21846                                                      shall be updated at every system boundary during DMA transfer.
21847                                                      These bits specify the size of contiguous buffer in the
21848                                                      system memory. The DMA transfer shall wait at the every
21849                                                      boundary specified by these fields and the HC generates
21850                                                      the DMA Interrupt to request the HD to update the System
21851                                                      Address register. These bits shall support when the DMA
21852                                                      Support in the Capabilities register is set to 1 and this
21853                                                      function is active when the DMA Enable in the Transfer
21854                                                                                                                                */
21855             uint32_t            : 1;
21856       __IOM uint32_t BLKCNT     : 16;           /*!< [31..16] This register is enabled when Block Count Enable in
21857                                                      the Transfer Mode register is set to 1 and is valid only
21858                                                      for multiple block transfers. The HC decrements the block
21859                                                      count after each block transfer and stops when the count
21860                                                      reaches zero. It can be accessed only if no transaction
21861                                                      is executing (i.e. after a transaction has stopped). Read
21862                                                      operations during transfer return an invalid value and
21863                                                      write operations shall be ignored. When saving transfer
21864                                                      context as a result of Suspend command, the number of blocks
21865                                                      y                                                                         */
21866     } BLOCK_b;
21867   } ;
21868 
21869   union {
21870     __IOM uint32_t ARGUMENT1;                   /*!< (@ 0x00000008) Argument1                                                  */
21871 
21872     struct {
21873       __IOM uint32_t CMDARG1    : 32;           /*!< [31..0] The SD Command Argument is specified as bit39-8 of Command-Format. */
21874     } ARGUMENT1_b;
21875   } ;
21876 
21877   union {
21878     __IOM uint32_t TRANSFER;                    /*!< (@ 0x0000000C) Transfer mode                                              */
21879 
21880     struct {
21881       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA can be enabled only if DMA Support bit in the Capabilities
21882                                                      register is set. If this bit is set to 1, a DMA operation
21883                                                      shall begin when the HD writes to the upper byte of Command
21884                                                      register (00Fh).                                                          */
21885       __IOM uint32_t BLKCNTEN   : 1;            /*!< [1..1] This bit is used to enable the Block count register,
21886                                                      which is only relevant for multiple block transfers. When
21887                                                      this bit is 0, the Block Count register is disabled, which
21888                                                      is useful in executing an infinite transfer.                              */
21889       __IOM uint32_t ACMDEN     : 2;            /*!< [3..2] This field determines use of auto command functions.
21890                                                      There are two methods to stop Multiple-block read and write
21891                                                      operation. (1) Auto CMD12 Enable Multiple-block read and
21892                                                      write commands for memory require CMD12 to stop the operation.
21893                                                      When this field is set to 01b, the Host Controller issues
21894                                                      CMD12 automatically when last block transfer is completed.
21895                                                      Auto CMD12 error is indicated to the Auto CMD Error Status
21896                                                      register. The Host Driver shall not set this bit if the
21897                                                      command does not require CMD12. (2) Auto CMD23                            */
21898       __IOM uint32_t DXFERDIRSEL : 1;           /*!< [4..4] Data Transfer Direction Select. This bit defines the
21899                                                      direction of data transfers.                                              */
21900       __IOM uint32_t BLKSEL     : 1;            /*!< [5..5] This bit enables multiple block data transfers.                    */
21901             uint32_t            : 10;
21902       __IOM uint32_t RESPTYPESEL : 2;           /*!< [17..16] Response Type Select                                             */
21903             uint32_t            : 1;
21904       __IOM uint32_t CMDCRCCHKEN : 1;           /*!< [19..19] If this bit is set to 1, the HC shall check the CRC
21905                                                      field in the response. If an error is detected, it is reported
21906                                                      as a Command CRC Error. If this bit is set to 0, the CRC
21907                                                      field is not checked.                                                     */
21908       __IOM uint32_t CMDIDXCHKEN : 1;           /*!< [20..20] If this bit is set to 1, the HC shall check the index
21909                                                      field in the response to see if it has the same value as
21910                                                      the command index. If it is not, it is reported as a Command
21911                                                      Index Error. If this bit is set to 0, the Index field is
21912                                                      not checked.                                                              */
21913       __IOM uint32_t DATAPRSNTSEL : 1;          /*!< [21..21] This bit is set to 1 to indicate that data is present
21914                                                      and shall be transferred using the DAT line. If is set
21915                                                      to 0 for the following: 1. Commands using only CMD line
21916                                                      (ex. CMD52) 2. Commands with no data transfer but using
21917                                                      busy signal on DAT[0] line (R1b or R5b ex. CMD38) 3. Resume
21918                                                      Command                                                                   */
21919       __IOM uint32_t CMDTYPE    : 2;            /*!< [23..22] There are three types of special commands. Suspend,
21920                                                      Resume and Abort. These bits shall bet set to 00b for all
21921                                                      other commands. Suspend Command If the Suspend command
21922                                                      succeeds, the HC shall assume the SD Bus has been released
21923                                                      and that it is possible to issue the next command which
21924                                                      uses the DAT line. The HC shall de-assert Read Wait for
21925                                                      read transactions and stop checking busy for write transactions.
21926                                                      The Interrupt cycle shall start, in 4-bit mode. If the
21927                                                      Suspend command fails, the HC shall maintain its curren                   */
21928       __IOM uint32_t CMDIDX     : 6;            /*!< [29..24] This bit shall be set to the command number (CMD0-63,
21929                                                      ACMD063).                                                                 */
21930             uint32_t            : 2;
21931     } TRANSFER_b;
21932   } ;
21933 
21934   union {
21935     __IOM uint32_t RESPONSE0;                   /*!< (@ 0x00000010) Response0                                                  */
21936 
21937     struct {
21938       __IOM uint32_t CMDRESP0   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
21939                                                      transmitted on the SD Bus, REP[] refers to a bit range
21940                                                      within the Response register.                                             */
21941     } RESPONSE0_b;
21942   } ;
21943 
21944   union {
21945     __IOM uint32_t RESPONSE1;                   /*!< (@ 0x00000014) Response1                                                  */
21946 
21947     struct {
21948       __IOM uint32_t CMDRESP1   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
21949                                                      transmitted on the SD Bus, REP[] refers to a bit range
21950                                                      within the Response register.                                             */
21951     } RESPONSE1_b;
21952   } ;
21953 
21954   union {
21955     __IOM uint32_t RESPONSE2;                   /*!< (@ 0x00000018) Response2                                                  */
21956 
21957     struct {
21958       __IOM uint32_t CMDRESP2   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
21959                                                      transmitted on the SD Bus, REP[] refers to a bit range
21960                                                      within the Response register.                                             */
21961     } RESPONSE2_b;
21962   } ;
21963 
21964   union {
21965     __IOM uint32_t RESPONSE3;                   /*!< (@ 0x0000001C) Response3                                                  */
21966 
21967     struct {
21968       __IOM uint32_t CMDRESP3   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
21969                                                      transmitted on the SD Bus, REP[] refers to a bit range
21970                                                      within the Response register.                                             */
21971     } RESPONSE3_b;
21972   } ;
21973 
21974   union {
21975     __IOM uint32_t BUFFER;                      /*!< (@ 0x00000020) Buffer data port                                           */
21976 
21977     struct {
21978       __IOM uint32_t BUFFERDATA : 32;           /*!< [31..0] The Host Controller Buffer can be accessed through this
21979                                                      32-bit Data Port Register.                                                */
21980     } BUFFER_b;
21981   } ;
21982 
21983   union {
21984     __IOM uint32_t PRESENT;                     /*!< (@ 0x00000024) Present state                                              */
21985 
21986     struct {
21987       __IOM uint32_t CMDINHCMD  : 1;            /*!< [0..0] If this bit is 0, it indicates the CMD line is not in
21988                                                      use and the HC can issue a SD command using the CMD line.
21989                                                      This bit is set immediately after the Command register
21990                                                      (00Fh) is written. This bit is cleared when the command
21991                                                      response is received. Even if the Command Inhibit (DAT)
21992                                                      is set to 1, Commands using only the CMD line can be issued
21993                                                      if this bit is 0. Changing from 1 to 0 generates a Command
21994                                                      complete interrupt in the Normal Interrupt Status register.
21995                                                      If the HC cannot issue the command because of a comma                     */
21996       __IOM uint32_t CMDINHDAT  : 1;            /*!< [1..1] This status bit is generated if either the DAT Line Active
21997                                                      or the Read transfer Active is set to 1. If this bit is
21998                                                      0, it indicates the HC can issue the next SD command. Commands
21999                                                      with busy signal belong to Command Inhibit (DAT) (ex. R1b,
22000                                                      R5b type). Changing from 1 to 0 generates a Transfer Complete
22001                                                      interrupt in the Normal interrupt status register. Note:
22002                                                      The SD Host Driver can save registers in the range of 000-00Dh
22003                                                      for a suspend transaction after this bit has changed from
22004                                                      1 to 0.                                                                   */
22005       __IOM uint32_t DLINEACT   : 1;            /*!< [2..2] This bit indicates whether one of the DAT line on SD
22006                                                      bus is in use.                                                            */
22007       __IOM uint32_t RETUNINGREQUEST : 1;       /*!< [3..3] Re-Tuning Request Host Controller may request Host Driver
22008                                                      to execute re-tuning sequence by setting this bit when
22009                                                      the data window is shifted by temperature drift and a tuned
22010                                                      sampling point does not have a good margin to receive correct
22011                                                      data. This bit is cleared when a command is issued with
22012                                                      setting Execute Tuning in the Host Control 2 register.
22013                                                      Changing of this bit from 0 to 1 generates Re-Tuning Event.
22014                                                      Refer to Normal Interrupt registers for more detail. This
22015                                                      bit isn't set to 1 if Sampling Clock Select in                            */
22016             uint32_t            : 4;
22017       __IOM uint32_t WRXFERACT  : 1;            /*!< [8..8] This status indicates a write transfer is active. If
22018                                                      this bit is 0, it means no valid write data exists in the
22019                                                      HC. This bit is set in either of the following cases: After
22020                                                      the end bit of the write command. When writing a 1 to Continue
22021                                                      Request in the Block Gap Control register to restart a
22022                                                      write transfer. This bit is cleared in either of the following
22023                                                      cases: After getting the CRC status of the last data block
22024                                                      as specified by the transfer count (Single or Multiple)
22025                                                      After getting a CRC status of any block wher                              */
22026       __IOM uint32_t RDXFERACT  : 1;            /*!< [9..9] This status is used for detecting completion of a read
22027                                                      transfer. This bit is set to 1 for either of the following
22028                                                      conditions: After the end bit of the read command When
22029                                                      writing a 1 to continue Request in the Block Gap Control
22030                                                      register to restart a read transfer This bit is cleared
22031                                                      to 0 for either of the following conditions: When the last
22032                                                      data block as specified by block length is transferred
22033                                                      to the system. When all valid data blocks have been transferred
22034                                                      to the system and no current block transfers are be                       */
22035       __IOM uint32_t BUFWREN    : 1;            /*!< [10..10] This status is used for non-DMA write transfers. This
22036                                                      read only flag indicates if space is available for write
22037                                                      data. If this bit is 1, data can be written to the buffer.
22038                                                      A change of this bit from 1 to 0 occurs when all the block
22039                                                      data is written to the buffer. A change of this bit from
22040                                                      0 to 1 occurs when top of block data can be written to
22041                                                      the buffer and generates the Buffer Write Ready Interrupt.                */
22042       __IOM uint32_t BUFRDEN    : 1;            /*!< [11..11] This status is used for non-DMA read transfers. This
22043                                                      read only flag indicates that valid data exists in the
22044                                                      host side buffer status. If this bit is 1, readable data
22045                                                      exists in the buffer. A change of this bit from 1 to 0
22046                                                      occurs when all the block data is read from the buffer.
22047                                                      A change of this bit from 0 to 1 occurs when all the block
22048                                                      data is ready in the buffer and generates the Buffer Read
22049                                                      Ready Interrupt.                                                          */
22050             uint32_t            : 4;
22051       __IOM uint32_t CARDINSERTED : 1;          /*!< [16..16] This bit indicates whether a card has been inserted.
22052                                                      Changing from 0 to 1 generates a Card Insertion interrupt
22053                                                      in the Normal Interrupt Status register and changing from
22054                                                      1 to 0 generates a Card Removal Interrupt in the Normal
22055                                                      Interrupt Status register. The Software Reset For All in
22056                                                      the Software Reset register shall not affect this bit.
22057                                                      If a Card is removed while its power is on and its clock
22058                                                      is oscillating, the HC shall clear SD Bus Power in the
22059                                                      Power Control register and SD Clock Enable in the Clock
22060                                                      contro                                                                    */
22061       __IOM uint32_t CARDSTABLE : 1;            /*!< [17..17] This bit is used for testing. If it is 0, the Card
22062                                                      Detect Pin Level is not stable. If this bit is set to 1,
22063                                                      it means the Card Detect Pin Level is stable. The Software
22064                                                      Reset For All in the Software Reset Register shall not
22065                                                      affect this bit.                                                          */
22066       __IOM uint32_t CARDDET    : 1;            /*!< [18..18] This bit reflects the inverse value of the SDCD# pin.            */
22067       __IOM uint32_t WRPROTSW   : 1;            /*!< [19..19] The Write Protect Switch is supported for memory and
22068                                                      combo cards. This bit reflects the SDWP# pin.                             */
22069       __IOM uint32_t DAT30LINE  : 4;            /*!< [23..20] This status is used to check DAT line level to recover
22070                                                      from errors, and for debugging. This is especially useful
22071                                                      in detecting the busy signal level from DAT[0].                           */
22072       __IOM uint32_t CMDLINE    : 1;            /*!< [24..24] This status is used to check CMD line level to recover
22073                                                      from errors, and for debugging.                                           */
22074       __IOM uint32_t DAT74LINE  : 4;            /*!< [28..25] This status is used to check DAT line level to recover
22075                                                      from errors, and for debugging.                                           */
22076             uint32_t            : 3;
22077     } PRESENT_b;
22078   } ;
22079 
22080   union {
22081     __IOM uint32_t HOSTCTRL1;                   /*!< (@ 0x00000028) Host control 1                                             */
22082 
22083     struct {
22084       __IOM uint32_t LEDCONTROL : 1;            /*!< [0..0] This bit is used to caution the user not to remove the
22085                                                      card while the SD card is being accessed. If the software
22086                                                      is going to issue multiple SD commands, this bit can be
22087                                                      set during all transactions. It is not necessary to change
22088                                                      for each transaction.                                                     */
22089       __IOM uint32_t DATATRANSFERWIDTH : 1;     /*!< [1..1] (SD1 or SD4) This bit selects the data width of the HC.
22090                                                      The HD shall select it to match the data width of the SD
22091                                                      card.                                                                     */
22092       __IOM uint32_t HISPEEDEN  : 1;            /*!< [2..2] This bit is optional. Before setting this bit, the HD
22093                                                      shall check the High Speed Support in the capabilities
22094                                                      register. If this bit is set to 0 (default), the HC outputs
22095                                                      CMD line and DAT lines at the falling edge of the SD clock
22096                                                      (up to 25 MHz/ 20MHz for MMC). If this bit is set to 1,
22097                                                      the HC outputs CMD line and DAT lines at the rising edge
22098                                                      of the SD clock (up to 50 MHz for SD/52MHz for MMC)/ 208Mhz
22099                                                      (for SD3.0) If Preset Value Enable in the Host Control
22100                                                      2 register is set to 1, Host Driver needs to reset SD C                   */
22101       __IOM uint32_t DMASELECT  : 2;            /*!< [4..3] One of supported DMA modes can be selected. The host
22102                                                      driver shall check support of DMA modes by referring the
22103                                                      Capabilities register.                                                    */
22104       __IOM uint32_t XFERWIDTH  : 1;            /*!< [5..5] This bit controls 8-bit bus width mode for embedded device.
22105                                                      Support of this function is indicated in 8-bit Support
22106                                                      for Embedded Device in the Capabilities register. If a
22107                                                      device supports 8-bit bus mode, this bit may be set to
22108                                                      1. If this bit is 0, bus width is controlled by Data Transfer
22109                                                      Width in the Host Control 1 register.This bit is not effective
22110                                                      when multiple devices are installed on a bus slot (Slot
22111                                                      Type is set to 10b in the Capabilities register). In this
22112                                                      case, each device bus width is controlled by Bu                           */
22113       __IOM uint32_t TESTLEVEL  : 1;            /*!< [6..6] This bit is enabled while the Card Detect Signal Selection
22114                                                      is set to 1 and it indicates card inserted or not. Generates
22115                                                      (card ins or card removal) interrupt when the normal int
22116                                                      sts enable bit is set.                                                    */
22117       __IOM uint32_t CARDSRC    : 1;            /*!< [7..7] This bit selects source for card detection.                        */
22118       __IOM uint32_t SDBUSPOWER : 1;            /*!< [8..8] Before setting this bit, the SD host driver shall set
22119                                                      SD Bus Voltage Select. If the HC detects the No Card State,
22120                                                      this bit shall be cleared.                                                */
22121       __IOM uint32_t VOLTSELECT : 3;            /*!< [11..9] By setting these bits, the HD selects the voltage level
22122                                                      for the SD card. Before setting this register, the HD shall
22123                                                      check the voltage support bits in the capabilities register.
22124                                                      If an unsupported voltage is selected, the Host System
22125                                                      shall not supply SD bus voltage. All voltage select values
22126                                                      not enumerated here are reserved.                                         */
22127       __IOM uint32_t HWRESET    : 1;            /*!< [12..12] Hardware reset signal is generated for eMMC card when
22128                                                      this bit is set                                                           */
22129             uint32_t            : 3;
22130       __IOM uint32_t STOPATBLOCKGAPREQUEST : 1; /*!< [16..16] This bit is used to stop executing a transaction at
22131                                                      the next block gap for non- DMA,SDMA and ADMA transfers.
22132                                                      Until the transfer complete is set to 1, indicating a transfer
22133                                                      completion the HD shall leave this bit set to 1. Clearing
22134                                                      both the Stop At Block Gap Request and Continue Request
22135                                                      shall not cause the transaction to restart. Read Wait is
22136                                                      used to stop the read transaction at the block gap. The
22137                                                      HC shall honour Stop At Block Gap Request for write transfers,
22138                                                      but for read transfers it requires that the SD ca                         */
22139       __IOM uint32_t CONTREQ    : 1;            /*!< [17..17] This bit is used to restart a transaction which was
22140                                                      stopped using the Stop At Block Gap Request. To cancel
22141                                                      stop at the block gap, set Stop At block Gap Request to
22142                                                      0 and set this bit to restart the transfer. The HC automatically
22143                                                      clears this bit in either of the following cases: 1) In
22144                                                      the case of a read transaction, the DAT Line Active changes
22145                                                      from 0 to 1 as a read transaction restarts. 2) In the case
22146                                                      of a write transaction, the Write transfer active changes
22147                                                      from 0 to 1 as the write transaction restarts. The                        */
22148       __IOM uint32_t READWAITCTRL : 1;          /*!< [18..18] The read wait function is optional for SDIO cards.
22149                                                      If the card supports read wait, set this bit to enable
22150                                                      use of the read wait protocol to stop read data using DAT[2]
22151                                                      line. Otherwise the HC has to stop the SD clock to hold
22152                                                      read data, which restricts commands generation. When the
22153                                                      HD detects an SD card insertion, it shall set this bit
22154                                                      according to the CCCR of the SDIO card. If the card does
22155                                                      not support read wait, this bit shall never be set to 1
22156                                                      otherwise DAT line conflict may occur. If this bit is set
22157                                                      to 0,                                                                     */
22158       __IOM uint32_t GAP        : 1;            /*!< [19..19] This bit is valid only in 4-bit mode of the SDIO card
22159                                                      and selects a sample point in the interrupt cycle. Setting
22160                                                      to 1 enables interrupt detection at the block gap for a
22161                                                      multiple block transfer. If the SD card cannot signal an
22162                                                      interrupt during a multiple block transfer, this bit should
22163                                                      be set to 0. When the HD detects an SD card insertion,
22164                                                      it shall set this bit according to the CCCR of the SDIO
22165                                                      card.                                                                     */
22166       __IOM uint32_t SPIMODE    : 1;            /*!< [20..20] SPI mode enable bit.                                             */
22167       __IOM uint32_t BOOTEN     : 1;            /*!< [21..21] To start boot code access                                        */
22168       __IOM uint32_t ALTBOOTEN  : 1;            /*!< [22..22] To start boot code access in alternative mode.                   */
22169       __IOM uint32_t BOOTACKCHK : 1;            /*!< [23..23] To check for the boot acknowledge in boot operation.             */
22170       __IOM uint32_t WUENCARDINT : 1;           /*!< [24..24] This bit enables wakeup event via Card Interrupt assertion
22171                                                      in the Normal Interrupt Status register. This bit can be
22172                                                      set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.                  */
22173       __IOM uint32_t WUENCARDINSERT : 1;        /*!< [25..25] This bit enables wakeup event via Card Insertion assertion
22174                                                      in the Normal Interrupt Status register. FN_WUS (Wake up
22175                                                      Support) in CIS does not affect this bit.                                 */
22176       __IOM uint32_t WUENCARDREMOVL : 1;        /*!< [26..26] This bit enables wakeup event via Card Removal assertion
22177                                                      in the Normal Interrupt Status register. FN_WUS (Wake up
22178                                                      Support) in CIS does not affect this bit.                                 */
22179             uint32_t            : 5;
22180     } HOSTCTRL1_b;
22181   } ;
22182 
22183   union {
22184     __IOM uint32_t CLOCKCTRL;                   /*!< (@ 0x0000002C) Clock control                                              */
22185 
22186     struct {
22187       __IOM uint32_t CLKEN      : 1;            /*!< [0..0] This bit is set to 0 when the HD is not using the HC
22188                                                      or the HC awaits a wakeup event. The HC should stop its
22189                                                      internal clock to go very low power state. Still, registers
22190                                                      shall be able to be read and written. Clock starts to oscillate
22191                                                      when this bit is set to 1. When clock oscillation is stable,
22192                                                      the HC shall set Internal Clock Stable in this register
22193                                                      to 1. This bit shall not affect card detection.                           */
22194       __IOM uint32_t CLKSTABLE  : 1;            /*!< [1..1] This bit is set to 1 when SD clock is stable after writing
22195                                                      to Internal Clock Enable in this register to 1. The SD
22196                                                      Host Driver shall wait to set SD Clock Enable until this
22197                                                      bit is set to 1. Note: This is useful when using PLL for
22198                                                      a clock oscillator that requires setup time.                              */
22199       __IOM uint32_t SDCLKEN    : 1;            /*!< [2..2] The HC shall stop SDCLK when writing this bit to 0. SDCLK
22200                                                      frequency Select can be changed when this bit is 0. Then,
22201                                                      the HC shall maintain the same clock frequency until SDCLK
22202                                                      is stopped (Stop at SDCLK = 0). If the HC detects the No
22203                                                      Card state, this bit shall be cleared.                                    */
22204             uint32_t            : 2;
22205       __IOM uint32_t CLKGENSEL  : 1;            /*!< [5..5] This bit is used to select the clock generator mode in
22206                                                      SDCLK Frequency Select. If the Programmable Clock Mode
22207                                                      is supported (non-zero value is set to Clock Multiplier
22208                                                      in the Capabilities register), this bit attribute is RW,
22209                                                      and if not supported, this bit attribute is RO and zero
22210                                                      is read. This bit depends on the setting of Preset Value
22211                                                      Enable in the Host Control 2 register. If the Preset Value
22212                                                      Enable = 0, this bit is set by Host Driver. If the Preset
22213                                                      Value Enable = 1, this bit is automatically set to a value                */
22214       __IOM uint32_t UPRCLKDIV  : 2;            /*!< [7..6] Bit 07-06 is assigned to bit 09-08 of clock divider in
22215                                                      SDCLK Frequency Select                                                    */
22216       __IOM uint32_t FREQSEL    : 8;            /*!< [15..8] This register is used to select the frequency of the
22217                                                      SDCLK pin. The frequency is not programmed directly; rather
22218                                                      this register holds the divisor of the Base Clock Frequency
22219                                                      For SD clock in the capabilities register. Only the following
22220                                                      settings are allowed. (1) 8-bit Divided Clock Mode Setting
22221                                                      00h specifies the highest frequency of the SD Clock. When
22222                                                      setting multiple bits, the most significant bit is used
22223                                                      as the divisor. But multiple bits should not be set. The
22224                                                      two default divider values can be calculated b                            */
22225       __IOM uint32_t TIMEOUTCNT : 4;            /*!< [19..16] This value determines the interval by which DAT line
22226                                                      time-outs are detected. Refer to the Data Time-out Error
22227                                                      in the Error Interrupt Status register for information
22228                                                      on factors that dictate time-out generation. Time-out clock
22229                                                      frequency will be generated by dividing the sdclockTMCLK
22230                                                      by this value. When setting this register, prevent inadvertent
22231                                                      time-out events by clearing the Data Time-out Error Status
22232                                                      Enable (in the Error Interrupt Status Enable register)
22233                                                      At the initialization of the HC, the HD shall set th                      */
22234             uint32_t            : 4;
22235       __IOM uint32_t SWRSTALL   : 1;            /*!< [24..24] This reset affects the entire HC except for the card
22236                                                      detection circuit. Register bits of type ROC, RW, RW1C,
22237                                                      RWAC are cleared to 0. During its initialization, the HD
22238                                                      shall set this bit to 1 to reset the HC. The HC shall reset
22239                                                      this bit to 0 when capabilities registers are valid and
22240                                                      the HD can read them. Additional use of Software Reset
22241                                                      For All may not affect the value of the Capabilities registers.
22242                                                      If this bit is set to 1, the SD card shall reset itself
22243                                                      and must be re initialized by the HD. A reset pulse is                    */
22244       __IOM uint32_t SWRSTCMD   : 1;            /*!< [25..25] Only part of command circuit is reset. The following
22245                                                      registers and bits are cleared by this bit: Present State
22246                                                      register Command Inhibit (CMD) Normal Interrupt Status
22247                                                      register Command Complete                                                 */
22248       __IOM uint32_t SWRSTDAT   : 1;            /*!< [26..26] Only part of data circuit is reset. The following registers
22249                                                      and bits are cleared by this bit: Buffer Data Port Register
22250                                                      Buffer is cleared and Initialized. Present State register
22251                                                      Buffer read Enable Buffer write Enable Read Transfer Active
22252                                                      Write Transfer Active DAT Line Active Command Inhibit (DAT)
22253                                                      Block Gap Control register Continue Request Stop At Block
22254                                                      Gap Request Normal Interrupt Status register Buffer Read
22255                                                      Ready Buffer Write Ready Block Gap Event Transfer Complete                */
22256             uint32_t            : 5;
22257     } CLOCKCTRL_b;
22258   } ;
22259 
22260   union {
22261     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000030) Interrupt enable                                           */
22262 
22263     struct {
22264       __IOM uint32_t COMMANDCOMPLETE : 1;       /*!< [0..0] This bit is set when we get the end bit of the command
22265                                                      response (Except Auto CMD12 and Auto CMD23) Note: Command
22266                                                      Time-out Error has higher priority than Command Complete.
22267                                                      If both are set to 1, it can be considered that the response
22268                                                      was not received correctly.                                               */
22269       __IOM uint32_t TRANSFERCOMPLETE : 1;      /*!< [1..1] This bit is set when a read / write transaction is completed.
22270                                                      Read Transaction: This bit is set at the falling edge of
22271                                                      Read Transfer Active Status. There are two cases in which
22272                                                      the Interrupt is generated. The first is when a data transfer
22273                                                      is completed as specified by data length (After the last
22274                                                      data has been read to the Host System). The second is when
22275                                                      data has stopped at the block gap and completed the data
22276                                                      transfer by setting the Stop At Block Gap Request in the
22277                                                      Block Gap Control Register (After valid da                                */
22278       __IOM uint32_t BLOCKGAPEVENT : 1;         /*!< [2..2] If the Stop At Block Gap Request in the Block Gap Control
22279                                                      Register is set, this bit is set. Read Transaction: This
22280                                                      bit is set at the falling edge of the DAT Line Active Status
22281                                                      (When the transaction is stopped at SD Bus timing. The
22282                                                      Read Wait must be supported inorder to use this function).
22283                                                      Write Transaction: This bit is set at the falling edge
22284                                                      of Write Transfer Active Status (After getting CRC status
22285                                                      at SD Bus timing).                                                        */
22286       __IOM uint32_t DMAINTERRUPT : 1;          /*!< [3..3] This status is set if the HC detects the Host DMA Buffer
22287                                                      Boundary in the Block Size regiser.                                       */
22288       __IOM uint32_t BUFFERWRITEREADY : 1;      /*!< [4..4] This status is set if the Buffer Write Enable changes
22289                                                      from 0 to 1.                                                              */
22290       __IOM uint32_t BUFFERREADREADY : 1;       /*!< [5..5] This status is set if the Buffer Read Enable changes
22291                                                      from 0 to 1. Buffer Read Ready is set to 1 for every CMD19
22292                                                      execution in tuning procedure.                                            */
22293       __IOM uint32_t CARDINSERTION : 1;         /*!< [6..6] This status is set if the Card Inserted in the Present
22294                                                      State register changes from 0 to 1. When the HD writes
22295                                                      this bit to 1 to clear this status the status of the Card
22296                                                      Inserted in the Present State register should be confirmed.
22297                                                      Because the card detect may possibly be changed when the
22298                                                      HD clear this bit an Interrupt event may not be generated.                */
22299       __IOM uint32_t CARDREMOVAL : 1;           /*!< [7..7] This status is set if the Card Inserted in the Present
22300                                                      State register changes from 1 to 0. When the HD writes
22301                                                      this bit to 1 to clear this status the status of the Card
22302                                                      Inserted in the Present State register should be confirmed.
22303                                                      Because the card detect may possibly be changed when the
22304                                                      HD clear this bit an Interrupt event may not be generated.                */
22305       __IOM uint32_t CARDINTERRUPT : 1;         /*!< [8..8] Writing this bit to 1 does not clear this bit. It is
22306                                                      cleared by resetting the SD card interrupt factor. In 1-bit
22307                                                      mode, the HC shall detect the Card Interrupt without SD
22308                                                      Clock to support wakeup. In 4-bit mode, the card interrupt
22309                                                      signal is sampled during the interrupt cycle, so there
22310                                                      are some sample delays between the interrupt signal from
22311                                                      the card and the interrupt to the Host system. when this
22312                                                      status has been set and the HD needs to start this interrupt
22313                                                      service, Card Interrupt Status Enable in the Normal I                     */
22314       __IOM uint32_t INTA       : 1;            /*!< [9..9] This status is set if INT_A is enabled and INT_A# pin
22315                                                      is in low level. Writing this bit to 1 does not clear this
22316                                                      bit. It is cleared by resetting the INT_A interrupt factor                */
22317       __IOM uint32_t INTB       : 1;            /*!< [10..10] This status is set if INT_B is enabled and INT_B# pin
22318                                                      is in low level. Writing this bit to 1 does not clear this
22319                                                      bit. It is cleared by resetting the INT_B interrupt factor                */
22320       __IOM uint32_t INTC       : 1;            /*!< [11..11] This status is set if INT_C is enabled and INT_C# pin
22321                                                      is in low level. Writing this bit to 1 does not clear this
22322                                                      bit. It is cleared by resetting the INT_C interrupt factor                */
22323       __IOM uint32_t RETUNINGEVENT : 1;         /*!< [12..12] This status is set if Re-Tuning Request in the Present
22324                                                      State register changes from 0 to 1. Host Controller requests
22325                                                      Host Driver to perform re-tuning for next data transfer.
22326                                                      Current data transfer (not large block count) can be completed
22327                                                      without re-tuning.                                                        */
22328       __IOM uint32_t BOOTACKRCV : 1;            /*!< [13..13] This status is set if the boot acknowledge is received
22329                                                      from device.                                                              */
22330       __IOM uint32_t BOOTTERMINATE : 1;         /*!< [14..14] Interrupt This status is set if the boot operation
22331                                                      get terminated                                                            */
22332       __IOM uint32_t ERRORINTERRUPT : 1;        /*!< [15..15] If any of the bits in the Error Interrupt Status Register
22333                                                      are set, then this bit is set. Therefore the HD can test
22334                                                      for an error by checking this bit first.                                  */
22335       __IOM uint32_t COMMANDTIMEOUTERROR : 1;   /*!< [16..16] Command CRC Error is generated in two cases. 1. If
22336                                                      a response is returned and the Command Time-out Error is
22337                                                      set to 0, this bit is set to 1 when detecting a CRT error
22338                                                      in the command response 2. The HC detects a CMD line conflict
22339                                                      by monitoring the CMD line when a command is issued. If
22340                                                      the HC drives the CMD line to 1 level, but detects 0 level
22341                                                      on the CMD line at the next SDCLK edge, then the HC shall
22342                                                      abort the command (Stop driving CMD line) and set this
22343                                                      bit to 1. The Command Timeout Error shall also be set t                   */
22344       __IOM uint32_t COMMANDCRCERROR : 1;       /*!< [17..17] Occurs when detecting that the end bit of a command
22345                                                      response is 0.                                                            */
22346       __IOM uint32_t COMMANDENDBITERROR : 1;    /*!< [18..18] Occurs only if the no response is returned within 64
22347                                                      SDCLK cycles from the end bit of the command. If the HC
22348                                                      detects a CMD line conflict, in which case Command CRC
22349                                                      Error shall also be set. This bit shall be set without
22350                                                      waiting for 64 SDCLK cycles because the command will be
22351                                                      aborted by the HC.                                                        */
22352       __IOM uint32_t COMMANDINDEXERROR : 1;     /*!< [19..19] Occurs if a Command Index error occurs in the Command
22353                                                      Response.                                                                 */
22354       __IOM uint32_t DATATIMEOUTERROR : 1;      /*!< [20..20] Occurs when detecting one of following timeout conditions.
22355                                                      1. Busy Timeout for R1b, R5b type. 2. Busy Timeout after
22356                                                      Write CRC status 3. Write CRC status Timeout 4. Read Data
22357                                                      Timeout                                                                   */
22358       __IOM uint32_t DATACRCERROR : 1;          /*!< [21..21] Occurs when detecting CRC error when transferring read
22359                                                      data which uses the DAT line or when detecting the Write
22360                                                      CRC Status having a value of other than 0.                                */
22361       __IOM uint32_t DATAENDBITERROR : 1;       /*!< [22..22] Occurs when detecting 0 at the end bit position of
22362                                                      read data which uses the DAT line or the end bit position
22363                                                      of the CRC status.                                                        */
22364       __IOM uint32_t CURRENTLIMITERROR : 1;     /*!< [23..23] By setting the SD Bus Power bit in the Power Control
22365                                                      Register, the HC is requested to supply power for the SD
22366                                                      Bus. If the HC supports the Current Limit Function, it
22367                                                      can be protected from an Illegal card by stopping power
22368                                                      supply to the card in which case this bit indicates a failure
22369                                                      status. Reading 1 means the HC is not supplying power to
22370                                                      SD card due to some failure. Reading 0 means that the HC
22371                                                      is supplying power and no error has occurred. This bit
22372                                                      shall always set to be 0, if the HC does not support this
22373                                                      f                                                                         */
22374       __IOM uint32_t AUTOCMDERROR : 1;          /*!< [24..24] Auto CMD12 and Auto CMD23 use this error status. This
22375                                                      bit is set when detecting that one of the bits D00-D04
22376                                                      in Auto CMD Error Status register has changed from 0 to
22377                                                      1. In case of Auto CMD12, this bit is set to 1, not only
22378                                                      when the errors in Auto CMD12 occur but also when Auto
22379                                                      CMD12 is not executed due to the previous command error.                  */
22380       __IOM uint32_t ADMAERROR  : 1;            /*!< [25..25] This bit is set when the Host Controller detects errors
22381                                                      during ADMA based data transfer. The state of the ADMA
22382                                                      at an error occurrence is saved in the ADMA Error Status
22383                                                      Register.                                                                 */
22384             uint32_t            : 2;
22385       __IOM uint32_t TGTRESPERR : 1;            /*!< [28..28] Occurs when detecting error in aximst_bresp or aximst_rresp      */
22386       __IOM uint32_t VNDERRSTAT : 3;            /*!< [31..29] Vendor specific error status.                                    */
22387     } INTSTAT_b;
22388   } ;
22389 
22390   union {
22391     __IOM uint32_t INTENABLE;                   /*!< (@ 0x00000034) Normal interrupt status enable                             */
22392 
22393     struct {
22394       __IOM uint32_t COMMANDCOMPLETESTATUSENABLE : 1;/*!< [0..0] Description                                                   */
22395       __IOM uint32_t TRANSFERCOMPLETESTATUSENABLE : 1;/*!< [1..1] Description                                                  */
22396       __IOM uint32_t BLOCKGAPEVENTSTATUSENABLE : 1;/*!< [2..2] Description                                                     */
22397       __IOM uint32_t DMAINTERRUPTSTATUSENABLE : 1;/*!< [3..3] Description                                                      */
22398       __IOM uint32_t BUFFERWRITEREADYSTATUSENABLE : 1;/*!< [4..4] Description                                                  */
22399       __IOM uint32_t BUFFERREADREADYSTATUSENABLE : 1;/*!< [5..5] Description                                                   */
22400       __IOM uint32_t CARDINSERTIONSTATUSENABLE : 1;/*!< [6..6] Description                                                     */
22401       __IOM uint32_t CARDREMOVALSTATUSENABLE : 1;/*!< [7..7] Description                                                       */
22402       __IOM uint32_t CARDINTERRUPTSTATUSENABLE : 1;/*!< [8..8] If this bit is set to 0, the HC shall clear Interrupt
22403                                                      request to the System. The Card Interrupt detection is
22404                                                      stopped when this bit is cleared and restarted when this
22405                                                      bit is set to 1. The HD may clear the Card Interrupt Status
22406                                                      Enable before servicing the Card Interrupt and may set
22407                                                      this bit again after all Interrupt requests from the card
22408                                                      are cleared to prevent inadvertent Interrupts.                            */
22409       __IOM uint32_t INTASTATUSENABLE : 1;      /*!< [9..9] If this bit is set to 0, the Host Controller shall clear
22410                                                      the interrupt request to the System. The Host Driver may
22411                                                      clear this bit before servicing the INT_A and may set this
22412                                                      bit again after all interrupt requests to INT_A pin are
22413                                                      cleared to prevent inadvertent interrupts.                                */
22414       __IOM uint32_t INTBSTATUSENABLE : 1;      /*!< [10..10] If this bit is set to 0, the Host Controller shall
22415                                                      clear the interrupt request to the System. The Host Driver
22416                                                      may clear this bit before servicing the INT_B and may set
22417                                                      this bit again after all interrupt requests to INT_B pin
22418                                                      are cleared to prevent inadvertent interrupts.                            */
22419       __IOM uint32_t INTCSTATUSENABLE : 1;      /*!< [11..11] If this bit is set to 0, the Host Controller shall
22420                                                      clear the interrupt request to the System. The Host Driver
22421                                                      may clear this bit before servicing the INT_C and may set
22422                                                      this bit again after all interrupt requests to INT_C pin
22423                                                      are cleared to prevent inadvertent interrupts. Interrupt
22424                                                      enable                                                                    */
22425       __IOM uint32_t RETUNINGEVENTSTATUSENABLE : 1;/*!< [12..12] Interrupt                                                     */
22426       __IOM uint32_t BOOTACKRCVENABLE : 1;      /*!< [13..13] Interrupt                                                        */
22427       __IOM uint32_t BOOTTERMINATE : 1;         /*!< [14..14] Boot is terminated?                                              */
22428       __IOM uint32_t FIXEDTO0   : 1;            /*!< [15..15] The HC shall control error Interrupts using the Error
22429                                                      Interrupt Status Enable register.                                         */
22430       __IOM uint32_t COMMANDTIMEOUTERRORSTATUSENABLE : 1;/*!< [16..16] Desc                                                    */
22431       __IOM uint32_t COMMANDCRCERRORSTATUSENABLE : 1;/*!< [17..17] Desc                                                        */
22432       __IOM uint32_t COMMANDENDBITERRORSTATUSENABLE : 1;/*!< [18..18] Desc                                                     */
22433       __IOM uint32_t COMMANDINDEXERRORSTATUSENABLE : 1;/*!< [19..19] Desc                                                      */
22434       __IOM uint32_t DATATIMEOUTERRORSTATUSENABLE : 1;/*!< [20..20] Desc                                                       */
22435       __IOM uint32_t DATACRCERRORSTATUSENABLE : 1;/*!< [21..21] Desc                                                           */
22436       __IOM uint32_t DATAENDBITERRORSTATUSENABLE : 1;/*!< [22..22] Desc                                                        */
22437       __IOM uint32_t CURRENTLIMITERRORSTATUSENABLE : 1;/*!< [23..23] Desc                                                      */
22438       __IOM uint32_t AUTOCMD12ERRORSTATUSENABLE : 1;/*!< [24..24] Desc                                                         */
22439       __IOM uint32_t ADMAERRORSTATUSENABLE : 1; /*!< [25..25] Desc                                                             */
22440       __IOM uint32_t TUNINGERRORSTATUS : 1;     /*!< [26..26] enable                                                           */
22441             uint32_t            : 1;
22442       __IOM uint32_t TGTRESPERRHOSTERRSTATEN : 1;/*!< [28..28] Desc                                                            */
22443       __IOM uint32_t VENDORSPECIFICERRORSTATUSENABLE : 3;/*!< [31..29] Vendor-specific error status enable.                    */
22444     } INTENABLE_b;
22445   } ;
22446 
22447   union {
22448     __IOM uint32_t INTSIG;                      /*!< (@ 0x00000038) Normal interrupt signal enable                             */
22449 
22450     struct {
22451       __IOM uint32_t CMDCMPEN   : 1;            /*!< [0..0] Interrupt                                                          */
22452       __IOM uint32_t XFERCMPEN  : 1;            /*!< [1..1] Interrupt                                                          */
22453       __IOM uint32_t BLOCKGAPEN : 1;            /*!< [2..2] Interrupt                                                          */
22454       __IOM uint32_t DMAINTEN   : 1;            /*!< [3..3] Interrupt                                                          */
22455       __IOM uint32_t BUFFERWREN : 1;            /*!< [4..4] Interrupt                                                          */
22456       __IOM uint32_t BUFFERRDEN : 1;            /*!< [5..5] Interrupt                                                          */
22457       __IOM uint32_t CARDINSERTEN : 1;          /*!< [6..6] Interrupt                                                          */
22458       __IOM uint32_t CARDREMOVALEN : 1;         /*!< [7..7] Interrupt                                                          */
22459       __IOM uint32_t CARDINTEN  : 1;            /*!< [8..8] Interrupt                                                          */
22460       __IOM uint32_t INTAEN     : 1;            /*!< [9..9] Interrupt                                                          */
22461       __IOM uint32_t INTBEN     : 1;            /*!< [10..10] Interrupt                                                        */
22462       __IOM uint32_t INTCEN     : 1;            /*!< [11..11] Interrupt                                                        */
22463       __IOM uint32_t RETUNEEVENTEN : 1;         /*!< [12..12] Interrupt signal enable                                          */
22464       __IOM uint32_t BOOTACKEN  : 1;            /*!< [13..13] Interrupt                                                        */
22465       __IOM uint32_t BOOTTERM   : 1;            /*!< [14..14] Boot terminate interrupt signal enable                           */
22466       __IOM uint32_t FIXED0     : 1;            /*!< [15..15] Fixed to 0. The HD shall control error Interrupts using
22467                                                      the Error Interrupt Signal Enable register.                               */
22468       __IOM uint32_t CMDTOERREN : 1;            /*!< [16..16] Desc                                                             */
22469       __IOM uint32_t CMDCRCERREN : 1;           /*!< [17..17] Desc                                                             */
22470       __IOM uint32_t CMDENDBITERREN : 1;        /*!< [18..18] Desc                                                             */
22471       __IOM uint32_t CMDIDXERREN : 1;           /*!< [19..19] Desc                                                             */
22472       __IOM uint32_t DATATOERROREN : 1;         /*!< [20..20] Desc                                                             */
22473       __IOM uint32_t DATACRCERREN : 1;          /*!< [21..21] Desc                                                             */
22474       __IOM uint32_t DATAENDERREN : 1;          /*!< [22..22] Desc                                                             */
22475       __IOM uint32_t CURRLMTERREN : 1;          /*!< [23..23] Desc                                                             */
22476       __IOM uint32_t AUTOCMD12ERREN : 1;        /*!< [24..24] Desc                                                             */
22477       __IOM uint32_t ADMAERREN  : 1;            /*!< [25..25] Desc                                                             */
22478       __IOM uint32_t TUNINGERREN : 1;           /*!< [26..26] Desc                                                             */
22479             uint32_t            : 1;
22480       __IOM uint32_t TGTRESPEN  : 1;            /*!< [28..28] Interrupt                                                        */
22481       __IOM uint32_t VNDERREN   : 3;            /*!< [31..29] VNDERREN field description needed here.                          */
22482     } INTSIG_b;
22483   } ;
22484 
22485   union {
22486     __IOM uint32_t AUTO;                        /*!< (@ 0x0000003C) Auto CMD error status                                      */
22487 
22488     struct {
22489       __IOM uint32_t CMD12NOTEXEC : 1;          /*!< [0..0] If memory multiple block data transfer is not started
22490                                                      due to command error, this bit is not set because it is
22491                                                      not necessary to issue Auto CMD12. Setting this bit to
22492                                                      1 means the HC cannot issue Auto CMD12 to stop memory multiple
22493                                                      block transfer due to some error. If this bit is set to
22494                                                      1, other error status bits (D04 - D01) are meaningless.
22495                                                      This bit is set to 0 when Auto CMD Error is generated by
22496                                                      Auto CMD23                                                                */
22497       __IOM uint32_t CMDTOERR   : 1;            /*!< [1..1] Occurs if the no response is returned within 64 SDCLK
22498                                                      cycles from the end bit of the command. If this bit is
22499                                                      set to 1, the other error status bits (D04 - D02) are meaningless.        */
22500       __IOM uint32_t CMDCRCERR  : 1;            /*!< [2..2] Occurs when detecting a CRC error in the command response.         */
22501       __IOM uint32_t CMDENDERR  : 1;            /*!< [3..3] Occurs when detecting that the end bit of command response
22502                                                      is 0.                                                                     */
22503       __IOM uint32_t CMDIDXERR  : 1;            /*!< [4..4] Occurs if the Command Index error occurs in response
22504                                                      to a command.                                                             */
22505             uint32_t            : 2;
22506       __IOM uint32_t NOTAUTOCMD12ERR : 1;       /*!< [7..7] Setting this bit to 1 means CMD_wo_DAT is not executed
22507                                                      due to an Auto CMD12 error (D04 - D01) in this register.
22508                                                      This bit is set to 0 when Auto CMD Error is generated by
22509                                                      Auto CMD23                                                                */
22510             uint32_t            : 8;
22511       __IOM uint32_t UHSMODESEL : 3;            /*!< [18..16] This field is used to select one of UHS-I modes and
22512                                                      effective when 1.8V Signaling Enable is set to 1. If Preset
22513                                                      Value Enable in the Host Control 2 register is set to 1,
22514                                                      Host Controller sets SDCLK Frequency Select, Clock Generator
22515                                                      Select in the Clock Control register and Driver Strength
22516                                                      Select according to Preset Value registers. In this case,
22517                                                      one of preset value registers is selected by this field.
22518                                                      Host Driver needs to reset SD Clock Enable before changing
22519                                                      this field to avoid generating clock glitch. After                        */
22520       __IOM uint32_t SIGNALVOLT : 1;            /*!< [19..19] This bit controls voltage regulator for I/O cell. 3.3V
22521                                                      is supplied to the card regardless of signaling voltage.
22522                                                      Setting this bit from 0 to 1 starts changing signal voltage
22523                                                      from 3.3V to 1.8V. 1.8V regulator output shall be stable
22524                                                      within 5ms. Host Controller clears this bit if switching
22525                                                      to 1.8V signaling fails. Clearing this bit from 1 to 0
22526                                                      starts changing signal voltage from 1.8V to 3.3V. 3.3V
22527                                                      regulator output shall be stable within 5ms. Host Driver
22528                                                      can set this bit to 1 when Host Controller supports 1.8V
22529                                                      s                                                                         */
22530       __IOM uint32_t DRVRSTRSEL : 2;            /*!< [21..20] Host Controller output driver in 1.8V signaling is
22531                                                      selected by this bit. In 3.3V signaling, this field is
22532                                                      not effective. This field can be set depends on Driver
22533                                                      Type A, C and D support bits in the Capabilities register.
22534                                                      This bit depends on setting of Preset Value Enable. If
22535                                                      Preset Value Enable = 0, this field is set by Host Driver.
22536                                                      If Preset Value Enable = 1, this field is automatically
22537                                                      set by a value specified in the one of Preset Value registers.            */
22538       __IOM uint32_t STARTTUNING : 1;           /*!< [22..22] This bit is set to 1 to start tuning procedure and
22539                                                      automatically cleared when tuning procedure is completed.
22540                                                      The result of tuning is indicated to Sampling Clock Select.
22541                                                      Tuning procedure is aborted by writing 0 for more detail
22542                                                      about tuning procedure.                                                   */
22543       __IOM uint32_t SAMPLCLKSEL : 1;           /*!< [23..23] This bit is set by tuning procedure when Execute Tuning
22544                                                      is cleared. Writing 1 to this bit is meaningless and ignored.
22545                                                      Setting 1 means that tuning is completed successfully and
22546                                                      setting 0 means that tuning is failed. Host Controller
22547                                                      uses this bit to select sampling clock to receive CMD and
22548                                                      DAT. This bit is cleared by writing 0. Change of this bit
22549                                                      is not allowed while the Host Controller is receiving response
22550                                                      or a read data block.                                                     */
22551             uint32_t            : 6;
22552       __IOM uint32_t ASYNCINTEN : 1;            /*!< [30..30] This bit can be set to 1 if a card support asynchronous
22553                                                      interrupt and Asynchronous Interrupt Support is set to
22554                                                      1 in the Capabilities register. Asynchronous interrupt
22555                                                      is effective when DAT[1] interrupt is used in 4-bit SD
22556                                                      mode (and zero is set to Interrupt Pin Select in the Shared
22557                                                      Bus Control register). If this bit is set to 1, the Host
22558                                                      Driver can stop the SDCLK during asynchronous interrupt
22559                                                      period to save power. During this period, the Host Controller
22560                                                      continues to deliver Card Interrupt to the host when it                   */
22561       __IOM uint32_t PRESETEN   : 1;            /*!< [31..31] Host Controller Version 3.00 supports this bit. As
22562                                                      the operating SDCLK frequency and I/O driver strength depend
22563                                                      on the Host System implementation, it is difficult to determine
22564                                                      these parameters in the Standard Host Driver. When Preset
22565                                                      Value Enable is set to automatic. This bit enables the
22566                                                      functions defined in the Preset Value registers. If this
22567                                                      bit is set to 0, SDCLK Frequency Select, Clock Generator
22568                                                      Select in the Clock Control register and Driver Strength
22569                                                      Select in Host Control 2 register are set by Host D                       */
22570     } AUTO_b;
22571   } ;
22572 
22573   union {
22574     __IOM uint32_t CAPABILITIES0;               /*!< (@ 0x00000040) Capabilities                                               */
22575 
22576     struct {
22577       __IOM uint32_t TOCLKFREQ  : 6;            /*!< [5..0] This bit shows the base clock frequency used to detect
22578                                                      Data Timeout Error. Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz
22579                                                      Note: The Host System shall support at least one of these
22580                                                      voltages above. The HD sets the SD Bus Voltage Select in
22581                                                      Power Control register according to these support bits.
22582                                                      If multiple voltages are supported, select the usable lower
22583                                                      voltage by comparing the OCR value from the card. These
22584                                                      registers indicate maximum current capability for each
22585                                                      voltage. The value is meaningful if Voltage Support is
22586                                                                                                                                */
22587             uint32_t            : 1;
22588       __IOM uint32_t TOCLKUNIT  : 1;            /*!< [7..7] This bit shows the unit of base clock frequency used
22589                                                      to detect Data Timeout Error.                                             */
22590       __IOM uint32_t SDCLKFREQ  : 8;            /*!< [15..8] 6-bit Base Clock Frequency This mode is supported by
22591                                                      the Host Controller Version 1.00 and 2.00. Upper 2-bit
22592                                                      is not effective and always 0. Unit values are 1MHz. The
22593                                                      supported clock range is 10MHz to 63MHz. 11xx xxxxb Not
22594                                                      supported 0011 1111b 63MHz 0000 0010b 2MHz 0000 0001b 1MHz
22595                                                      0000 0000b Get information via another method (2) 8-bit
22596                                                      Base Clock Frequency This mode is supported by the Host
22597                                                      Controller Version 3.00.Unit values are 1MHz. The supported
22598                                                      clock range is 10MHz to 255MHz. FFh 255MHz 02h 2MHz 01h
22599                                                      1MH                                                                       */
22600       __IOM uint32_t MAXBLKLEN  : 2;            /*!< [17..16] This value indicates the maximum block size that the
22601                                                      HD can read and write to the buffer in the HC. The buffer
22602                                                      shall transfer this block size without wait cycles. Three
22603                                                      sizes can be defined as indicated below.                                  */
22604       __IOM uint32_t EXTMEDIA   : 1;            /*!< [18..18] This bit indicates whether the Host Controller is capable
22605                                                      of using 8-bit bus width mode. This bit is not effective
22606                                                      when Slot Type is set to 10b. In this case, refer to Bus
22607                                                      Width Preset in the Shared Bus resister. Supported                        */
22608       __IOM uint32_t ADMA2      : 1;            /*!< [19..19] Desc                                                             */
22609             uint32_t            : 1;
22610       __IOM uint32_t HIGHSPEED  : 1;            /*!< [21..21] This bit indicates whether the HC and the Host System
22611                                                      support High Speed mode and they can supply SD Clock frequency
22612                                                      from 25Mhz to 50 Mhz (for SD)/ 20MHz to 52MHz (for MMC).                  */
22613       __IOM uint32_t SDMA       : 1;            /*!< [22..22] This bit indicates whether the HC is capable of using
22614                                                      DMA to transfer data between system memory and the HC directly.           */
22615       __IOM uint32_t SUSPRES    : 1;            /*!< [23..23] This bit indicates whether the HC supports Suspend
22616                                                      / Resume functionality. If this bit is 0, the Suspend and
22617                                                      Resume mechanism are not supported and the HD shall not
22618                                                      issue either Suspend / Resume commands.                                   */
22619       __IOM uint32_t VOLT33V    : 1;            /*!< [24..24] Desc                                                             */
22620       __IOM uint32_t VOLT30V    : 1;            /*!< [25..25] Voltage support 3.0v                                             */
22621       __IOM uint32_t VOLT18V    : 1;            /*!< [26..26] Voltage support 1.8v                                             */
22622             uint32_t            : 1;
22623       __IOM uint32_t SYSBUS64   : 1;            /*!< [28..28] Desc                                                             */
22624       __IOM uint32_t ASYNCINT   : 1;            /*!< [29..29] Refer to SDIO Specification Version 3.00 about asynchronous
22625                                                      interrupt.                                                                */
22626       __IOM uint32_t SLOTTYPE   : 2;            /*!< [31..30] This field indicates usage of a slot by a specific
22627                                                      Host System. (A host controller register set is defined
22628                                                      per slot.) Embedded slot for one device (01b) means that
22629                                                      only one non-removable device is connected to a SD bus
22630                                                      slot. Shared Bus Slot (10b) can be set if Host Controller
22631                                                      supports Shared Bus Control register. The Standard Host
22632                                                      Driver controls only a removable card or one embedded device
22633                                                      is connected to a SD bus slot. If a slot is configured
22634                                                      for shared bus (10b), the Standard Host Driver does not
22635                                                      contro                                                                    */
22636     } CAPABILITIES0_b;
22637   } ;
22638 
22639   union {
22640     __IOM uint32_t CAPABILITIES1;               /*!< (@ 0x00000044) Capabilities                                               */
22641 
22642     struct {
22643       __IOM uint32_t SDR50      : 1;            /*!< [0..0] 1- SDR50 is Supported                                              */
22644       __IOM uint32_t SDR104     : 1;            /*!< [1..1] 1- SDR104 is Supported                                             */
22645       __IOM uint32_t DDR50      : 1;            /*!< [2..2] DDR50 field description needed here.                               */
22646             uint32_t            : 1;
22647       __IOM uint32_t TYPEA      : 1;            /*!< [4..4] This bit indicates support of Driver Type A for 1.8 Signaling.     */
22648       __IOM uint32_t TYPEC      : 1;            /*!< [5..5] This bit indicates support of Driver Type C for 1.8 Signaling.     */
22649       __IOM uint32_t TYPED      : 1;            /*!< [6..6] Reserved This bit indicates support of Driver Type D
22650                                                      for 1.8 Signaling.                                                        */
22651             uint32_t            : 1;
22652       __IOM uint32_t RETUNINGTMRCNT : 4;        /*!< [11..8] This field indicates an initial value of the Re-Tuning
22653                                                      Timer for Re-Tuning Mode 1 to 3. 0h - Get information via
22654                                                      other source.                                                             */
22655             uint32_t            : 1;
22656       __IOM uint32_t TUNINGSDR50 : 1;           /*!< [13..13] If this bit is set to 1, this Host Controller requires
22657                                                      tuning to operate SDR50. (Tuning is always required to
22658                                                      operate SDR104.)                                                          */
22659       __IOM uint32_t RETUNINGMODES : 2;         /*!< [15..14] This field defines the re-tuning capability of a Host
22660                                                      Controller and how to manage the data transfer length and
22661                                                      a Re-Tuning Timer by the Host Driver There are two re-tuning
22662                                                      timings: Re-Tuning Request and expiration of a Re-Tuning
22663                                                      Timer. By receiving either timing, the Host Driver executes
22664                                                      the re-tuning procedure just before a next command issue                  */
22665       __IOM uint32_t CLKMULT    : 8;            /*!< [23..16] This field indicates clock multiplier value of programmable
22666                                                      clock generator. Refer to Clock Control register. Setting
22667                                                      00h means that Host Controller does not support programmable
22668                                                      clock generator. The multiplier is (CLKMULT+1).                           */
22669       __IOM uint32_t SPIMODE    : 1;            /*!< [24..24] Spi mode                                                         */
22670       __IOM uint32_t SPIBLOCKMODE : 1;          /*!< [25..25] Spi block mode                                                   */
22671             uint32_t            : 6;
22672     } CAPABILITIES1_b;
22673   } ;
22674 
22675   union {
22676     __IOM uint32_t MAXIMUM0;                    /*!< (@ 0x00000048) Maximum current capabilities                               */
22677 
22678     struct {
22679       __IOM uint32_t ALLBITSRSVD : 32;          /*!< [31..0] The entire 32-bits of this register are reserved, do
22680                                                      not read or write.                                                        */
22681     } MAXIMUM0_b;
22682   } ;
22683 
22684   union {
22685     __IOM uint32_t MAXIMUM1;                    /*!< (@ 0x0000004C) Maximum current capabilities                               */
22686 
22687     struct {
22688       __IOM uint32_t MAXCURR33V : 8;            /*!< [7..0] Maximum Current for 3.3V. The current value is specified
22689                                                      as MAXCURR18V * 4mA. Some example enums follow:                           */
22690       __IOM uint32_t MAXCURR30V : 8;            /*!< [15..8] Maximum Current for 3.0V. The current value is specified
22691                                                      as MAXCURR18V * 4mA. Some example enums follow:                           */
22692       __IOM uint32_t MAXCURR18V : 8;            /*!< [23..16] Maximum Current for 1.8V. The current value is specified
22693                                                      as MAXCURR18V * 4mA. Some example enums follow:                           */
22694             uint32_t            : 8;
22695     } MAXIMUM1_b;
22696   } ;
22697 
22698   union {
22699     __IOM uint32_t FORCE;                       /*!< (@ 0x00000050) Force event register for error interrupt status            */
22700 
22701     struct {
22702       __IOM uint32_t FORCEACMD12NOT : 1;        /*!< [0..0] Description                                                        */
22703       __IOM uint32_t FORCEACMDTOERR : 1;        /*!< [1..1] Description                                                        */
22704       __IOM uint32_t FORCEACMDCRCERR : 1;       /*!< [2..2] Description                                                        */
22705       __IOM uint32_t FORCEACMDENDERR : 1;       /*!< [3..3] Description                                                        */
22706       __IOM uint32_t FORCEACMDIDXERR : 1;       /*!< [4..4] Desc                                                               */
22707             uint32_t            : 2;
22708       __IOM uint32_t FORCEACMDISSUEDERR : 1;    /*!< [7..7] 1 - Interrupt is generated                                         */
22709             uint32_t            : 8;
22710       __IOM uint32_t FORCECMDTOERR : 1;         /*!< [16..16] Force Event for Command Timeout Error                            */
22711       __IOM uint32_t FORCECMDCRCERR : 1;        /*!< [17..17] Force Event for Command CRC Error                                */
22712       __IOM uint32_t FORCECMDENDERR : 1;        /*!< [18..18] Force Event for Command End Bit Error                            */
22713       __IOM uint32_t FORCECMDIDXERR : 1;        /*!< [19..19] Force Event for Command Index Error                              */
22714       __IOM uint32_t FORCEDATATOERR : 1;        /*!< [20..20] Force Event for Data Timeout Error                               */
22715       __IOM uint32_t FORCEDATACRCERR : 1;       /*!< [21..21] Force Event for Data CRC Error                                   */
22716       __IOM uint32_t FORCEDATAENDERR : 1;       /*!< [22..22] Force Event for Data End Bit Error                               */
22717       __IOM uint32_t FORCECURRLIMITERR : 1;     /*!< [23..23] Force Event for Current Limit Error                              */
22718       __IOM uint32_t FORCEACMDERR : 1;          /*!< [24..24] Force Event for Auto CMD Error                                   */
22719       __IOM uint32_t FORCEADMAERR : 1;          /*!< [25..25] Force event for ADMA error                                       */
22720             uint32_t            : 6;
22721     } FORCE_b;
22722   } ;
22723 
22724   union {
22725     __IOM uint32_t ADMA;                        /*!< (@ 0x00000054) ADMA error status                                          */
22726 
22727     struct {
22728       __IOM uint32_t ADMAERRORSTATE : 2;        /*!< [1..0] This field indicates the state of ADMA when error is
22729                                                      occurred during ADMA data transfer. This field never indicates
22730                                                      10 because ADMA never stops in this state. D01 - D00 :
22731                                                      ADMA Error State when error occurred Contents of SYS_SDR
22732                                                      register                                                                  */
22733       __IOM uint32_t ADMALENMISMATCHERR : 1;    /*!< [2..2] This error occurs in the following 2 cases. While Block
22734                                                      Count Enable being set, the total data length specified
22735                                                      by the Descriptor table is different from that specified
22736                                                      by the Block Count and Block Length. Total data length
22737                                                      can not be divided by the block length.                                   */
22738             uint32_t            : 29;
22739     } ADMA_b;
22740   } ;
22741 
22742   union {
22743     __IOM uint32_t ADMALOWD;                    /*!< (@ 0x00000058) ADMA system address [31:0]                                 */
22744 
22745     struct {
22746       __IOM uint32_t LOWD       : 32;           /*!< [31..0] This register holds byte address of executing command
22747                                                      of the Descriptor table. 32-bit Address Descriptor uses
22748                                                      lower 32bit of this register. At the start of ADMA, the
22749                                                      Host Driver shall set start address of the Descriptor table.
22750                                                      The ADMA increments this register address, which points
22751                                                      to next line, when every fetching a Descriptor line. When
22752                                                      the ADMA Error Interrupt is generated, this register shall
22753                                                      hold valid Descriptor address depending on the ADMA state.
22754                                                      The Host Driver shall program Descriptor Table on 32                      */
22755     } ADMALOWD_b;
22756   } ;
22757 
22758   union {
22759     __IOM uint32_t ADMAHIWD;                    /*!< (@ 0x0000005C) ADMA system address [63:0]                                 */
22760 
22761     struct {
22762       __IOM uint32_t HIWD       : 32;           /*!< [31..0] This register holds byte address of executing command
22763                                                      of the Descriptor table. 32-bit Address Descriptor uses
22764                                                      lower 32bit of this register. At the start of ADMA, the
22765                                                      Host Driver shall set start address of the Descriptor table.
22766                                                      The ADMA increments this register address, which points
22767                                                      to next line, when every fetching a Descriptor line. When
22768                                                      the ADMA Error Interrupt is generated, this register shall
22769                                                      hold valid Descriptor address depending on the ADMA state.
22770                                                      The Host Driver shall program Descriptor Table on 32                      */
22771     } ADMAHIWD_b;
22772   } ;
22773 
22774   union {
22775     __IOM uint32_t PRESET0;                     /*!< (@ 0x00000060) Preset Value initialization and default speed              */
22776 
22777     struct {
22778       __IOM uint32_t HISPSDCLKFREQSEL : 10;     /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
22779                                                      the Clock Control Register is described by a host system.
22780                                                      When Host Controller supports shared bus, a set of Preset
22781                                                      Value registers for each device required and the registers
22782                                                      location are duplicated to the offset 06Fh-060h. A set
22783                                                      of Preset Value registers can be accessible by selecting
22784                                                      Clock Pin Select in the Shared Bus Control register                       */
22785       __IOM uint32_t HISPCLKGENSEL : 1;         /*!< [10..10] This bit is effective when Host Controller supports
22786                                                      programmable clock generator.                                             */
22787             uint32_t            : 3;
22788       __IOM uint32_t HISPDRVRSTRSEL : 2;        /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
22789                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22790       __IOM uint32_t DEFSPSDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
22791                                                      the Clock Control Register is described by a host system.
22792                                                      When Host Controller supports shared bus, a set of Preset
22793                                                      Value registers for each device required and the registers
22794                                                      location are duplicated to the offset 06Fh-060h. A set
22795                                                      of Preset Value registers can be accessible by selecting
22796                                                      Clock Pin Select in the Shared Bus Control register                       */
22797       __IOM uint32_t DEFSPCLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
22798                                                      programmable clock generator.                                             */
22799             uint32_t            : 3;
22800       __IOM uint32_t DEFSPDRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
22801                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22802     } PRESET0_b;
22803   } ;
22804 
22805   union {
22806     __IOM uint32_t PRESET1;                     /*!< (@ 0x00000064) Preset Value for high speed and SDR12                      */
22807 
22808     struct {
22809       __IOM uint32_t HSSDCLKFREQSEL : 10;       /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
22810                                                      the Clock Control Register is described by a host system.
22811                                                      When Host Controller supports shared bus, a set of Preset
22812                                                      Value registers for each device required and the registers
22813                                                      location are duplicated to the offset 06Fh-060h. A set
22814                                                      of Preset Value registers can be accessible by selecting
22815                                                      Clock Pin Select in the Shared Bus Control register                       */
22816       __IOM uint32_t HSCLKGENSEL : 1;           /*!< [10..10] This bit is effective when Host Controller supports
22817                                                      programmable clock generator.                                             */
22818             uint32_t            : 3;
22819       __IOM uint32_t HSDRVRSTRSEL : 2;          /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
22820                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22821       __IOM uint32_t SDR12SDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
22822                                                      the Clock Control Register is described by a host system.
22823                                                      When Host Controller supports shared bus, a set of Preset
22824                                                      Value registers for each device required and the registers
22825                                                      location are duplicated to the offset 06Fh-060h. A set
22826                                                      of Preset Value registers can be accessible by selecting
22827                                                      Clock Pin Select in the Shared Bus Control register                       */
22828       __IOM uint32_t SDR12CLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
22829                                                      programmable clock generator.                                             */
22830             uint32_t            : 3;
22831       __IOM uint32_t SDR12DRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
22832                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22833     } PRESET1_b;
22834   } ;
22835 
22836   union {
22837     __IOM uint32_t PRESET2;                     /*!< (@ 0x00000068) Preset Value for SDR25 and SDR50                           */
22838 
22839     struct {
22840       __IOM uint32_t SDR25SDCLKFREQSEL : 10;    /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
22841                                                      the Clock Control Register is described by a host system.
22842                                                      When Host Controller supports shared bus, a set of Preset
22843                                                      Value registers for each device required and the registers
22844                                                      location are duplicated to the offset 06Fh-060h. A set
22845                                                      of Preset Value registers can be accessible by selecting
22846                                                      Clock Pin Select in the Shared Bus Control register                       */
22847       __IOM uint32_t SDR25CLKGENSEL : 1;        /*!< [10..10] This bit is effective when Host Controller supports
22848                                                      programmable clock generator.                                             */
22849             uint32_t            : 3;
22850       __IOM uint32_t SDR25DRVRSTRSEL : 2;       /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
22851                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22852       __IOM uint32_t SDR50SDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
22853                                                      the Clock Control Register is described by a host system.
22854                                                      When Host Controller supports shared bus, a set of Preset
22855                                                      Value registers for each device required and the registers
22856                                                      location are duplicated to the offset 06Fh-060h. A set
22857                                                      of Preset Value registers can be accessible by selecting
22858                                                      Clock Pin Select in the Shared Bus Control register                       */
22859       __IOM uint32_t SDR50CLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
22860                                                      programmable clock generator.                                             */
22861             uint32_t            : 3;
22862       __IOM uint32_t SDR50DRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
22863                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22864     } PRESET2_b;
22865   } ;
22866 
22867   union {
22868     __IOM uint32_t PRESET3;                     /*!< (@ 0x0000006C) Preset Value for SDR104 and DDR50                          */
22869 
22870     struct {
22871       __IOM uint32_t SDR104SDCLKFREQSEL : 10;   /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
22872                                                      the Clock Control Register is described by a host system.
22873                                                      When Host Controller supports shared bus, a set of Preset
22874                                                      Value registers for each device required and the registers
22875                                                      location are duplicated to the offset 06Fh-060h. A set
22876                                                      of Preset Value registers can be accessible by selecting
22877                                                      Clock Pin Select in the Shared Bus Control register                       */
22878       __IOM uint32_t SDR104CLKGENSEL : 1;       /*!< [10..10] This bit is effective when Host Controller supports
22879                                                      programmable clock generator.                                             */
22880             uint32_t            : 3;
22881       __IOM uint32_t SDR104DRVRSTRSEL : 2;      /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
22882                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22883       __IOM uint32_t DDR50SDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
22884                                                      the Clock Control Register is described by a host system.
22885                                                      When Host Controller supports shared bus, a set of Preset
22886                                                      Value registers for each device required and the registers
22887                                                      location are duplicated to the offset 06Fh-060h. A set
22888                                                      of Preset Value registers can be accessible by selecting
22889                                                      Clock Pin Select in the Shared Bus Control register                       */
22890       __IOM uint32_t DDR50CLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
22891                                                      programmable clock generator.                                             */
22892             uint32_t            : 3;
22893       __IOM uint32_t DDR50DRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
22894                                                      speed modes. This field is meaningless for 3.3V signaling.                */
22895     } PRESET3_b;
22896   } ;
22897 
22898   union {
22899     __IOM uint32_t BOOTTOCTRL;                  /*!< (@ 0x00000070) Boot Data Timeout control                                  */
22900 
22901     struct {
22902       __IOM uint32_t BOOTDATATO : 32;           /*!< [31..0] This value determines the interval by which DAT line
22903                                                      time-outs are detected during boot operation for eMMC card.
22904                                                      The value is in number of sd clock.                                       */
22905     } BOOTTOCTRL_b;
22906   } ;
22907   __IM  uint32_t  RESERVED;
22908 
22909   union {
22910     __IOM uint32_t VENDOR;                      /*!< (@ 0x00000078) Vendor                                                     */
22911 
22912     struct {
22913       __IOM uint32_t GATESDCLKEN : 1;           /*!< [0..0] If this bit is 0, SD_CLK to card will not be gated automatically,
22914                                                      when there is no transfer. If this bit set to 1, SD_CLK
22915                                                      to card will be gated automatically,when there is no transfer.            */
22916       __IOM uint32_t DLYDIS     : 1;            /*!< [1..1] Chicken bit added to enable/disable the rtl fix made
22917                                                      to delay the sampling of cmd_in and data_in.                              */
22918             uint32_t            : 30;
22919     } VENDOR_b;
22920   } ;
22921   __IM  uint32_t  RESERVED1[32];
22922 
22923   union {
22924     __IOM uint32_t SLOTSTAT;                    /*!< (@ 0x000000FC) Slot interrupt status                                      */
22925 
22926     struct {
22927       __IOM uint32_t INTSLOT0   : 1;            /*!< [0..0] This status bit indicates the OR of Interrupt signal
22928                                                      and Wakeup signal for slot                                                */
22929             uint32_t            : 15;
22930       __IOM uint32_t SPECVER    : 8;            /*!< [23..16] The Host Controller Version Number is set to 0x02 (SD
22931                                                      Host Specification Version 3.00).                                         */
22932       __IOM uint32_t VENDORVER  : 8;            /*!< [31..24] The Vendor Version Number is set to 0x10 (1.0)                   */
22933     } SLOTSTAT_b;
22934   } ;
22935 } SDIO_Type;                                    /*!< Size = 256 (0x100)                                                        */
22936 
22937 
22938 
22939 /* =========================================================================================================================== */
22940 /* ================                                         SECURITY                                          ================ */
22941 /* =========================================================================================================================== */
22942 
22943 
22944 /**
22945   * @brief Security Interfaces (SECURITY)
22946   */
22947 
22948 typedef struct {                                /*!< (@ 0x40030000) SECURITY Structure                                         */
22949 
22950   union {
22951     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) Control                                                    */
22952 
22953     struct {
22954       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Function Enable. Software should set the ENABLE bit to
22955                                                      initiate a CRC operation. Hardware will clear the ENABLE
22956                                                      bit upon completion.                                                      */
22957             uint32_t            : 3;
22958       __IOM uint32_t FUNCTION   : 4;            /*!< [7..4] Function Select                                                    */
22959             uint32_t            : 23;
22960       __IOM uint32_t CRCERROR   : 1;            /*!< [31..31] CRC Error Status - Set to 1 if an error occurs during
22961                                                      a CRC operation. Cleared when CTRL register is written
22962                                                      (with any value). Usually indicates an invalid address
22963                                                      range.                                                                    */
22964     } CTRL_b;
22965   } ;
22966   __IM  uint32_t  RESERVED[3];
22967 
22968   union {
22969     __IOM uint32_t SRCADDR;                     /*!< (@ 0x00000010) Source Addresss                                            */
22970 
22971     struct {
22972       __IOM uint32_t ADDR       : 32;           /*!< [31..0] Source Buffer Address. Address may be byte aligned,
22973                                                      but the length must be a multiple of 4 bits.                              */
22974     } SRCADDR_b;
22975   } ;
22976   __IM  uint32_t  RESERVED1[3];
22977 
22978   union {
22979     __IOM uint32_t LEN;                         /*!< (@ 0x00000020) Length                                                     */
22980 
22981     struct {
22982             uint32_t            : 2;
22983       __IOM uint32_t LEN        : 22;           /*!< [23..2] Buffer size (bottom two bits assumed to be zero to ensure
22984                                                      a multiple of 4 bytes)                                                    */
22985             uint32_t            : 8;
22986     } LEN_b;
22987   } ;
22988   __IM  uint32_t  RESERVED2[3];
22989 
22990   union {
22991     __IOM uint32_t RESULT;                      /*!< (@ 0x00000030) CRC Seed/Result                                            */
22992 
22993     struct {
22994       __IOM uint32_t CRC        : 32;           /*!< [31..0] CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF
22995                                                      before starting a CRC operation (unless the CRC is continued
22996                                                      from a previous operation).                                               */
22997     } RESULT_b;
22998   } ;
22999   __IM  uint32_t  RESERVED3[17];
23000 
23001   union {
23002     __IOM uint32_t LOCKCTRL;                    /*!< (@ 0x00000078) LOCK Control                                               */
23003 
23004     struct {
23005       __IOM uint32_t SELECT     : 8;            /*!< [7..0] LOCK Function Select register.                                     */
23006             uint32_t            : 24;
23007     } LOCKCTRL_b;
23008   } ;
23009 
23010   union {
23011     __IOM uint32_t LOCKSTAT;                    /*!< (@ 0x0000007C) LOCK Status                                                */
23012 
23013     struct {
23014       __IOM uint32_t STATUS     : 32;           /*!< [31..0] Lock status. Bit is high to signify it is enabled. 0:
23015                                                      LOCK01, 1: LOCK02, 4: LOCK11, 5: LOCK12, 30: LOCK9D, 31:
23016                                                      LOCK9E                                                                    */
23017     } LOCKSTAT_b;
23018   } ;
23019 
23020   union {
23021     __IOM uint32_t KEY0;                        /*!< (@ 0x00000080) Key0                                                       */
23022 
23023     struct {
23024       __IOM uint32_t KEY0       : 32;           /*!< [31..0] Bits [31:0] of the 128-bit key should be written to
23025                                                      this register. To protect key values, the register always
23026                                                      returns 0x00000000.                                                       */
23027     } KEY0_b;
23028   } ;
23029 
23030   union {
23031     __IOM uint32_t KEY1;                        /*!< (@ 0x00000084) Key1                                                       */
23032 
23033     struct {
23034       __IOM uint32_t KEY1       : 32;           /*!< [31..0] Bits [63:32] of the 128-bit key should be written to
23035                                                      this register. To protect key values, the register always
23036                                                      returns 0x00000000.                                                       */
23037     } KEY1_b;
23038   } ;
23039 
23040   union {
23041     __IOM uint32_t KEY2;                        /*!< (@ 0x00000088) Key2                                                       */
23042 
23043     struct {
23044       __IOM uint32_t KEY2       : 32;           /*!< [31..0] Bits [95:64] of the 128-bit key should be written to
23045                                                      this register. To protect key values, the register always
23046                                                      returns 0x00000000.                                                       */
23047     } KEY2_b;
23048   } ;
23049 
23050   union {
23051     __IOM uint32_t KEY3;                        /*!< (@ 0x0000008C) Key3                                                       */
23052 
23053     struct {
23054       __IOM uint32_t KEY3       : 32;           /*!< [31..0] Bits [127:96] of the 128-bit key should be written to
23055                                                      this register. To protect key values, the register always
23056                                                      returns 0x00000000.                                                       */
23057     } KEY3_b;
23058   } ;
23059 } SECURITY_Type;                                /*!< Size = 144 (0x90)                                                         */
23060 
23061 
23062 
23063 /* =========================================================================================================================== */
23064 /* ================                                          STIMER                                           ================ */
23065 /* =========================================================================================================================== */
23066 
23067 
23068 /**
23069   * @brief Counter/Timer (STIMER)
23070   */
23071 
23072 typedef struct {                                /*!< (@ 0x40008800) STIMER Structure                                           */
23073 
23074   union {
23075     __IOM uint32_t STCFG;                       /*!< (@ 0x00000000) The STIMER Configuration Register contains the
23076                                                                     software control for selecting the clock
23077                                                                     divider and source feeding the system timer.               */
23078 
23079     struct {
23080       __IOM uint32_t CLKSEL     : 4;            /*!< [3..0] Selects an appropriate clock source and divider to use
23081                                                      for the System Timer clock.                                               */
23082             uint32_t            : 4;
23083       __IOM uint32_t COMPAREAEN : 1;            /*!< [8..8] Selects whether compare is enabled for the corresponding
23084                                                      SCMPR register. If compare is enabled, the interrupt status
23085                                                      is set once the comparision is met.                                       */
23086       __IOM uint32_t COMPAREBEN : 1;            /*!< [9..9] Selects whether compare is enabled for the corresponding
23087                                                      SCMPR register. If compare is enabled, the interrupt status
23088                                                      is set once the comparision is met.                                       */
23089       __IOM uint32_t COMPARECEN : 1;            /*!< [10..10] Selects whether compare is enabled for the corresponding
23090                                                      SCMPR register. If compare is enabled, the interrupt status
23091                                                      is set once the comparision is met.                                       */
23092       __IOM uint32_t COMPAREDEN : 1;            /*!< [11..11] Selects whether compare is enabled for the corresponding
23093                                                      SCMPR register. If compare is enabled, the interrupt status
23094                                                      is set once the comparision is met.                                       */
23095       __IOM uint32_t COMPAREEEN : 1;            /*!< [12..12] Selects whether compare is enabled for the corresponding
23096                                                      SCMPR register. If compare is enabled, the interrupt status
23097                                                      is set once the comparision is met.                                       */
23098       __IOM uint32_t COMPAREFEN : 1;            /*!< [13..13] Selects whether compare is enabled for the corresponding
23099                                                      SCMPR register. If compare is enabled, the interrupt status
23100                                                      is set once the comparision is met.                                       */
23101       __IOM uint32_t COMPAREGEN : 1;            /*!< [14..14] Selects whether compare is enabled for the corresponding
23102                                                      SCMPR register. If compare is enabled, the interrupt status
23103                                                      is set once the comparision is met.                                       */
23104       __IOM uint32_t COMPAREHEN : 1;            /*!< [15..15] Selects whether compare is enabled for the corresponding
23105                                                      SCMPR register. If compare is enabled, the interrupt status
23106                                                      is set once the comparision is met.                                       */
23107             uint32_t            : 14;
23108       __IOM uint32_t CLEAR      : 1;            /*!< [30..30] Set this bit to one to clear the System Timer register.
23109                                                      If this bit is set to '1', the system timer register will
23110                                                      stay cleared. It needs to be set to '0' for the system
23111                                                      timer to start running.                                                   */
23112       __IOM uint32_t FREEZE     : 1;            /*!< [31..31] Set this bit to one to freeze the clock input to the
23113                                                      COUNTER register. Once frozen, the value can be safely
23114                                                      written from the MCU. Unfreeze to resume.                                 */
23115     } STCFG_b;
23116   } ;
23117 
23118   union {
23119     __IOM uint32_t STTMR;                       /*!< (@ 0x00000004) The COUNTER Register contains the running count
23120                                                                     of time as maintained by incrementing for
23121                                                                     every rising clock edge of the clock source
23122                                                                     selected in the configuration register.
23123                                                                     It is this counter value that captured in
23124                                                                     the capture registers and it is this counter
23125                                                                     value that is compared against the various
23126                                                                     compare registers. This register cannot
23127                                                                     be written, but can be cleared to 0 for
23128                                                                     a deterministic value. Use the FREEZE bit
23129                                                                     will stop this counter from incrementing.                  */
23130 
23131     struct {
23132       __IOM uint32_t STTMR      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
23133     } STTMR_b;
23134   } ;
23135   __IM  uint32_t  RESERVED[2];
23136 
23137   union {
23138     __IOM uint32_t SCAPCTRL0;                   /*!< (@ 0x00000010) The STIMER Capture Control Register controls
23139                                                                     each of the 4 capture registers. It selects
23140                                                                     their GPIO pin number for a trigger source,
23141                                                                     enables a capture operation and sets the
23142                                                                     input polarity for the capture. NOTE: 8-bit
23143                                                                     writes can control individual capture registers
23144                                                                     atomically.                                                */
23145 
23146     struct {
23147       __IOM uint32_t STSEL0     : 7;            /*!< [6..0] STIMER Capture 0 Select.                                           */
23148             uint32_t            : 1;
23149       __IOM uint32_t STPOL0     : 1;            /*!< [8..8] STIMER Capture 0 Polarity.                                         */
23150       __IOM uint32_t CAPTURE0   : 1;            /*!< [9..9] Selects whether capture 0 is enabled for the specified
23151                                                      capture register.                                                         */
23152             uint32_t            : 22;
23153     } SCAPCTRL0_b;
23154   } ;
23155 
23156   union {
23157     __IOM uint32_t SCAPCTRL1;                   /*!< (@ 0x00000014) The STIMER Capture Control Register controls
23158                                                                     each of the 4 capture registers. It selects
23159                                                                     their GPIO pin number for a trigger source,
23160                                                                     enables a capture operation and sets the
23161                                                                     input polarity for the capture. NOTE: 8-bit
23162                                                                     writes can control individual capture registers
23163                                                                     atomically.                                                */
23164 
23165     struct {
23166       __IOM uint32_t STSEL1     : 7;            /*!< [6..0] STIMER Capture 1 Select.                                           */
23167             uint32_t            : 1;
23168       __IOM uint32_t STPOL1     : 1;            /*!< [8..8] STIMER Capture 1 Polarity.                                         */
23169       __IOM uint32_t CAPTURE1   : 1;            /*!< [9..9] Selects whether capture 1 is enabled for the specified
23170                                                      capture register.                                                         */
23171             uint32_t            : 22;
23172     } SCAPCTRL1_b;
23173   } ;
23174 
23175   union {
23176     __IOM uint32_t SCAPCTRL2;                   /*!< (@ 0x00000018) The STIMER Capture Control Register controls
23177                                                                     each of the 4 capture registers. It selects
23178                                                                     their GPIO pin number for a trigger source,
23179                                                                     enables a capture operation and sets the
23180                                                                     input polarity for the capture. NOTE: 8-bit
23181                                                                     writes can control individual capture registers
23182                                                                     atomically.                                                */
23183 
23184     struct {
23185       __IOM uint32_t STSEL2     : 7;            /*!< [6..0] STIMER Capture 2 Select.                                           */
23186             uint32_t            : 1;
23187       __IOM uint32_t STPOL2     : 1;            /*!< [8..8] STIMER Capture 2 Polarity.                                         */
23188       __IOM uint32_t CAPTURE2   : 1;            /*!< [9..9] Selects whether capture 2 is enabled for the specified
23189                                                      capture register.                                                         */
23190             uint32_t            : 22;
23191     } SCAPCTRL2_b;
23192   } ;
23193 
23194   union {
23195     __IOM uint32_t SCAPCTRL3;                   /*!< (@ 0x0000001C) The STIMER Capture Control Register controls
23196                                                                     each of the 4 capture registers. It selects
23197                                                                     their GPIO pin number for a trigger source,
23198                                                                     enables a capture operation and sets the
23199                                                                     input polarity for the capture. NOTE: 8-bit
23200                                                                     writes can control individual capture registers
23201                                                                     atomically.                                                */
23202 
23203     struct {
23204       __IOM uint32_t STSEL3     : 7;            /*!< [6..0] STIMER Capture 3 Select.                                           */
23205             uint32_t            : 1;
23206       __IOM uint32_t STPOL3     : 1;            /*!< [8..8] STIMER Capture 3 Polarity.                                         */
23207       __IOM uint32_t CAPTURE3   : 1;            /*!< [9..9] Selects whether capture 3 is enabled for the specified
23208                                                      capture register.                                                         */
23209             uint32_t            : 22;
23210     } SCAPCTRL3_b;
23211   } ;
23212 
23213   union {
23214     __IOM uint32_t SCMPR0;                      /*!< (@ 0x00000020) The VALUE in this bit field is used to compare
23215                                                                     against the VALUE in the COUNTER register.
23216                                                                     If the match criterion in the configuration
23217                                                                     register is met then a corresponding interrupt
23218                                                                     status bit is set. The match criterion is
23219                                                                     defined as COUNTER equal to COMPARE. To
23220                                                                     establish a desired value in this COMPARE
23221                                                                     register, write the number of ticks in the
23222                                                                     future to this register to indicate when
23223                                                                     to interrupt. The hardware does the addition
23224                                                                     to the COUNTER value in the STIMER clock
23225                                                                     domain so that the ma                                      */
23226 
23227     struct {
23228       __IOM uint32_t SCMPR0     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23229                                                      according to the match criterion, as selected in the COMPARE_A_EN
23230                                                      bit in the REG_CTIMER_STCFG register.                                     */
23231     } SCMPR0_b;
23232   } ;
23233 
23234   union {
23235     __IOM uint32_t SCMPR1;                      /*!< (@ 0x00000024) The VALUE in this bit field is used to compare
23236                                                                     against the VALUE in the COUNTER register.
23237                                                                     If the match criterion in the configuration
23238                                                                     register is met then a corresponding interrupt
23239                                                                     status bit is set. The match criterion is
23240                                                                     defined as COUNTER equal to COMPARE. To
23241                                                                     establish a desired value in this COMPARE
23242                                                                     register, write the number of ticks in the
23243                                                                     future to this register to indicate when
23244                                                                     to interrupt. The hardware does the addition
23245                                                                     to the COUNTER value in the STIMER clock
23246                                                                     domain so that the ma                                      */
23247 
23248     struct {
23249       __IOM uint32_t SCMPR1     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23250                                                      according to the match criterion, as selected in the COMPARE_A_EN
23251                                                      bit in the REG_CTIMER_STCFG register.                                     */
23252     } SCMPR1_b;
23253   } ;
23254 
23255   union {
23256     __IOM uint32_t SCMPR2;                      /*!< (@ 0x00000028) The VALUE in this bit field is used to compare
23257                                                                     against the VALUE in the COUNTER register.
23258                                                                     If the match criterion in the configuration
23259                                                                     register is met then a corresponding interrupt
23260                                                                     status bit is set. The match criterion is
23261                                                                     defined as COUNTER equal to COMPARE. To
23262                                                                     establish a desired value in this COMPARE
23263                                                                     register, write the number of ticks in the
23264                                                                     future to this register to indicate when
23265                                                                     to interrupt. The hardware does the addition
23266                                                                     to the COUNTER value in the STIMER clock
23267                                                                     domain so that the ma                                      */
23268 
23269     struct {
23270       __IOM uint32_t SCMPR2     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23271                                                      according to the match criterion, as selected in the COMPARE_A_EN
23272                                                      bit in the REG_CTIMER_STCFG register.                                     */
23273     } SCMPR2_b;
23274   } ;
23275 
23276   union {
23277     __IOM uint32_t SCMPR3;                      /*!< (@ 0x0000002C) The VALUE in this bit field is used to compare
23278                                                                     against the VALUE in the COUNTER register.
23279                                                                     If the match criterion in the configuration
23280                                                                     register is met then a corresponding interrupt
23281                                                                     status bit is set. The match criterion is
23282                                                                     defined as COUNTER equal to COMPARE. To
23283                                                                     establish a desired value in this COMPARE
23284                                                                     register, write the number of ticks in the
23285                                                                     future to this register to indicate when
23286                                                                     to interrupt. The hardware does the addition
23287                                                                     to the COUNTER value in the STIMER clock
23288                                                                     domain so that the ma                                      */
23289 
23290     struct {
23291       __IOM uint32_t SCMPR3     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23292                                                      according to the match criterion, as selected in the COMPARE_A_EN
23293                                                      bit in the REG_CTIMER_STCFG register.                                     */
23294     } SCMPR3_b;
23295   } ;
23296 
23297   union {
23298     __IOM uint32_t SCMPR4;                      /*!< (@ 0x00000030) The VALUE in this bit field is used to compare
23299                                                                     against the VALUE in the COUNTER register.
23300                                                                     If the match criterion in the configuration
23301                                                                     register is met then a corresponding interrupt
23302                                                                     status bit is set. The match criterion is
23303                                                                     defined as COUNTER equal to COMPARE. To
23304                                                                     establish a desired value in this COMPARE
23305                                                                     register, write the number of ticks in the
23306                                                                     future to this register to indicate when
23307                                                                     to interrupt. The hardware does the addition
23308                                                                     to the COUNTER value in the STIMER clock
23309                                                                     domain so that the ma                                      */
23310 
23311     struct {
23312       __IOM uint32_t SCMPR4     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23313                                                      according to the match criterion, as selected in the COMPARE_A_EN
23314                                                      bit in the REG_CTIMER_STCFG register.                                     */
23315     } SCMPR4_b;
23316   } ;
23317 
23318   union {
23319     __IOM uint32_t SCMPR5;                      /*!< (@ 0x00000034) The VALUE in this bit field is used to compare
23320                                                                     against the VALUE in the COUNTER register.
23321                                                                     If the match criterion in the configuration
23322                                                                     register is met then a corresponding interrupt
23323                                                                     status bit is set. The match criterion is
23324                                                                     defined as COUNTER equal to COMPARE. To
23325                                                                     establish a desired value in this COMPARE
23326                                                                     register, write the number of ticks in the
23327                                                                     future to this register to indicate when
23328                                                                     to interrupt. The hardware does the addition
23329                                                                     to the COUNTER value in the STIMER clock
23330                                                                     domain so that the ma                                      */
23331 
23332     struct {
23333       __IOM uint32_t SCMPR5     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23334                                                      according to the match criterion, as selected in the COMPARE_A_EN
23335                                                      bit in the REG_CTIMER_STCFG register.                                     */
23336     } SCMPR5_b;
23337   } ;
23338 
23339   union {
23340     __IOM uint32_t SCMPR6;                      /*!< (@ 0x00000038) The VALUE in this bit field is used to compare
23341                                                                     against the VALUE in the COUNTER register.
23342                                                                     If the match criterion in the configuration
23343                                                                     register is met then a corresponding interrupt
23344                                                                     status bit is set. The match criterion is
23345                                                                     defined as COUNTER equal to COMPARE. To
23346                                                                     establish a desired value in this COMPARE
23347                                                                     register, write the number of ticks in the
23348                                                                     future to this register to indicate when
23349                                                                     to interrupt. The hardware does the addition
23350                                                                     to the COUNTER value in the STIMER clock
23351                                                                     domain so that the ma                                      */
23352 
23353     struct {
23354       __IOM uint32_t SCMPR6     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23355                                                      according to the match criterion, as selected in the COMPARE_A_EN
23356                                                      bit in the REG_CTIMER_STCFG register.                                     */
23357     } SCMPR6_b;
23358   } ;
23359 
23360   union {
23361     __IOM uint32_t SCMPR7;                      /*!< (@ 0x0000003C) The VALUE in this bit field is used to compare
23362                                                                     against the VALUE in the COUNTER register.
23363                                                                     If the match criterion in the configuration
23364                                                                     register is met then a corresponding interrupt
23365                                                                     status bit is set. The match criterion is
23366                                                                     defined as COUNTER equal to COMPARE. To
23367                                                                     establish a desired value in this COMPARE
23368                                                                     register, write the number of ticks in the
23369                                                                     future to this register to indicate when
23370                                                                     to interrupt. The hardware does the addition
23371                                                                     to the COUNTER value in the STIMER clock
23372                                                                     domain so that the ma                                      */
23373 
23374     struct {
23375       __IOM uint32_t SCMPR7     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
23376                                                      according to the match criterion, as selected in the COMPARE_A_EN
23377                                                      bit in the REG_CTIMER_STCFG register.                                     */
23378     } SCMPR7_b;
23379   } ;
23380 
23381   union {
23382     __IOM uint32_t SCAPT0;                      /*!< (@ 0x00000040) The STIMER capture Register 0 captures the VALUE
23383                                                                     in the COUNTER register whenever capture
23384                                                                     condition (event) occurs. This register
23385                                                                     holds a time stamp for the event.                          */
23386 
23387     struct {
23388       __IOM uint32_t SCAPT0     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
23389                                                      is copied into this register and the corresponding interrupt
23390                                                      status bit is set.                                                        */
23391     } SCAPT0_b;
23392   } ;
23393 
23394   union {
23395     __IOM uint32_t SCAPT1;                      /*!< (@ 0x00000044) The STIMER capture Register 1 captures the VALUE
23396                                                                     in the COUNTER register whenever capture
23397                                                                     condition (event) occurs. This register
23398                                                                     holds a time stamp for the event.                          */
23399 
23400     struct {
23401       __IOM uint32_t SCAPT1     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
23402                                                      is copied into this register and the corresponding interrupt
23403                                                      status bit is set.                                                        */
23404     } SCAPT1_b;
23405   } ;
23406 
23407   union {
23408     __IOM uint32_t SCAPT2;                      /*!< (@ 0x00000048) The STIMER capture Register 2 captures the VALUE
23409                                                                     in the COUNTER register whenever capture
23410                                                                     condition (event) occurs. This register
23411                                                                     holds a time stamp for the event.                          */
23412 
23413     struct {
23414       __IOM uint32_t SCAPT2     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
23415                                                      is copied into this register and the corresponding interrupt
23416                                                      status bit is set.                                                        */
23417     } SCAPT2_b;
23418   } ;
23419 
23420   union {
23421     __IOM uint32_t SCAPT3;                      /*!< (@ 0x0000004C) The STIMER capture Register 3 captures the VALUE
23422                                                                     in the COUNTER register whenever capture
23423                                                                     condition (event) occurs. This register
23424                                                                     holds a time stamp for the event.                          */
23425 
23426     struct {
23427       __IOM uint32_t SCAPT3     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
23428                                                      is copied into this register and the corresponding interrupt
23429                                                      status bit is set.                                                        */
23430     } SCAPT3_b;
23431   } ;
23432 
23433   union {
23434     __IOM uint32_t SNVR0;                       /*!< (@ 0x00000050) The SNVR0 Register contains a portion of the
23435                                                                     stored epoch offset associated with the
23436                                                                     time in the COUNTER register. This register
23437                                                                     is only reset by POI not by HRESETn. Its
23438                                                                     contents are intended to survive all reset
23439                                                                     level except POI and full power cycles.                    */
23440 
23441     struct {
23442       __IOM uint32_t SNVR0      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
23443     } SNVR0_b;
23444   } ;
23445 
23446   union {
23447     __IOM uint32_t SNVR1;                       /*!< (@ 0x00000054) The SNVR1 Register contains a portion of the
23448                                                                     stored epoch offset associated with the
23449                                                                     time in the COUNTER register. This register
23450                                                                     is only reset by POI not by HRESETn. Its
23451                                                                     contents are intended to survive all reset
23452                                                                     level except POI and full power cycles.                    */
23453 
23454     struct {
23455       __IOM uint32_t SNVR1      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
23456     } SNVR1_b;
23457   } ;
23458 
23459   union {
23460     __IOM uint32_t SNVR2;                       /*!< (@ 0x00000058) The SNVR2 Register contains a portion of the
23461                                                                     stored epoch offset associated with the
23462                                                                     time in the COUNTER register. This register
23463                                                                     is only reset by POI not by HRESETn. Its
23464                                                                     contents are intended to survive all reset
23465                                                                     level except POI and full power cycles.                    */
23466 
23467     struct {
23468       __IOM uint32_t SNVR2      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
23469     } SNVR2_b;
23470   } ;
23471   __IM  uint32_t  RESERVED1[41];
23472 
23473   union {
23474     __IOM uint32_t STMINTEN;                    /*!< (@ 0x00000100) Set bits in this register to allow this module
23475                                                                     to generate the corresponding interrupt.                   */
23476 
23477     struct {
23478       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
23479                                                      A.                                                                        */
23480       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
23481                                                      B.                                                                        */
23482       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
23483                                                      C.                                                                        */
23484       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
23485                                                      D.                                                                        */
23486       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
23487                                                      E.                                                                        */
23488       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
23489                                                      F.                                                                        */
23490       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
23491                                                      G.                                                                        */
23492       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
23493                                                      H.                                                                        */
23494       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
23495       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
23496       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
23497       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
23498       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
23499             uint32_t            : 19;
23500     } STMINTEN_b;
23501   } ;
23502 
23503   union {
23504     __IOM uint32_t STMINTSTAT;                  /*!< (@ 0x00000104) Read bits from this register to discover the
23505                                                                     cause of a recent interrupt.                               */
23506 
23507     struct {
23508       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
23509                                                      A.                                                                        */
23510       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
23511                                                      B.                                                                        */
23512       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
23513                                                      C.                                                                        */
23514       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
23515                                                      D.                                                                        */
23516       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
23517                                                      E.                                                                        */
23518       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
23519                                                      F.                                                                        */
23520       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
23521                                                      G.                                                                        */
23522       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
23523                                                      H.                                                                        */
23524       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
23525       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
23526       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
23527       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
23528       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
23529             uint32_t            : 19;
23530     } STMINTSTAT_b;
23531   } ;
23532 
23533   union {
23534     __IOM uint32_t STMINTCLR;                   /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
23535                                                                     the interrupt status associated with that
23536                                                                     bit.                                                       */
23537 
23538     struct {
23539       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
23540                                                      A.                                                                        */
23541       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
23542                                                      B.                                                                        */
23543       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
23544                                                      C.                                                                        */
23545       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
23546                                                      D.                                                                        */
23547       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
23548                                                      E.                                                                        */
23549       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
23550                                                      F.                                                                        */
23551       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
23552                                                      G.                                                                        */
23553       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
23554                                                      H.                                                                        */
23555       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
23556       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
23557       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
23558       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
23559       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
23560             uint32_t            : 19;
23561     } STMINTCLR_b;
23562   } ;
23563 
23564   union {
23565     __IOM uint32_t STMINTSET;                   /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
23566                                                                     generate an interrupt from this module.
23567                                                                     (Generally used for testing purposes).                     */
23568 
23569     struct {
23570       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
23571                                                      A.                                                                        */
23572       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
23573                                                      B.                                                                        */
23574       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
23575                                                      C.                                                                        */
23576       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
23577                                                      D.                                                                        */
23578       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
23579                                                      E.                                                                        */
23580       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
23581                                                      F.                                                                        */
23582       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
23583                                                      G.                                                                        */
23584       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
23585                                                      H.                                                                        */
23586       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
23587       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
23588       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
23589       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
23590       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
23591             uint32_t            : 19;
23592     } STMINTSET_b;
23593   } ;
23594 } STIMER_Type;                                  /*!< Size = 272 (0x110)                                                        */
23595 
23596 
23597 
23598 /* =========================================================================================================================== */
23599 /* ================                                           TIMER                                           ================ */
23600 /* =========================================================================================================================== */
23601 
23602 
23603 /**
23604   * @brief Counter/Timer (TIMER)
23605   */
23606 
23607 typedef struct {                                /*!< (@ 0x40008000) TIMER Structure                                            */
23608 
23609   union {
23610     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) General Timer Controls                                     */
23611 
23612     struct {
23613             uint32_t            : 31;
23614       __IOM uint32_t RESET      : 1;            /*!< [31..31] Write to 1 to reset all timers (self-clearing)                   */
23615     } CTRL_b;
23616   } ;
23617 
23618   union {
23619     __IOM uint32_t STATUS;                      /*!< (@ 0x00000004) General Timer status                                       */
23620 
23621     struct {
23622       __IOM uint32_t ACTIVE     : 16;           /*!< [15..0] Indicates which timers are currnetly active (enabled)             */
23623       __IOM uint32_t NTIMERS    : 5;            /*!< [20..16] Indicates the number of timer blocks present in the
23624                                                      design                                                                    */
23625             uint32_t            : 11;
23626     } STATUS_b;
23627   } ;
23628   __IM  uint32_t  RESERVED[2];
23629 
23630   union {
23631     __IOM uint32_t GLOBEN;                      /*!< (@ 0x00000010) Alternate enables for all TIMERs.                          */
23632 
23633     struct {
23634       __IOM uint32_t ENB0       : 1;            /*!< [0..0] Alternate enable for timer 0                                       */
23635       __IOM uint32_t ENB1       : 1;            /*!< [1..1] Alternate enable for timer 1                                       */
23636       __IOM uint32_t ENB2       : 1;            /*!< [2..2] Alternate enable for timer 2                                       */
23637       __IOM uint32_t ENB3       : 1;            /*!< [3..3] Alternate enable for timer 3                                       */
23638       __IOM uint32_t ENB4       : 1;            /*!< [4..4] Alternate enable for timer 4                                       */
23639       __IOM uint32_t ENB5       : 1;            /*!< [5..5] Alternate enable for timer 5                                       */
23640       __IOM uint32_t ENB6       : 1;            /*!< [6..6] Alternate enable for timer 6                                       */
23641       __IOM uint32_t ENB7       : 1;            /*!< [7..7] Alternate enable for timer 7                                       */
23642       __IOM uint32_t ENB8       : 1;            /*!< [8..8] Alternate enable for timer 8                                       */
23643       __IOM uint32_t ENB9       : 1;            /*!< [9..9] Alternate enable for timer 9                                       */
23644       __IOM uint32_t ENB10      : 1;            /*!< [10..10] Alternate enable for timer 10                                    */
23645       __IOM uint32_t ENB11      : 1;            /*!< [11..11] Alternate enable for timer 11                                    */
23646       __IOM uint32_t ENB12      : 1;            /*!< [12..12] Alternate enable for timer 12                                    */
23647       __IOM uint32_t ENB13      : 1;            /*!< [13..13] Alternate enable for timer 13                                    */
23648       __IOM uint32_t ENB14      : 1;            /*!< [14..14] Alternate enable for timer 14                                    */
23649       __IOM uint32_t ENB15      : 1;            /*!< [15..15] Alternate enable for timer 15                                    */
23650             uint32_t            : 13;
23651       __IOM uint32_t ENABLEALLINPUTS : 1;       /*!< [29..29] Override to enable all GPIO inputs                               */
23652       __IOM uint32_t AUDADCEN   : 1;            /*!< [30..30] Audio ADC controls enable for timer 6                            */
23653       __IOM uint32_t ADCEN      : 1;            /*!< [31..31] ADC controls enable for timer 7                                  */
23654     } GLOBEN_b;
23655   } ;
23656   __IM  uint32_t  RESERVED1[19];
23657 
23658   union {
23659     __IOM uint32_t INTEN;                       /*!< (@ 0x00000060) Set bits in this register to allow this module
23660                                                                     to generate the corresponding interrupt.                   */
23661 
23662     struct {
23663       __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
23664       __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
23665       __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
23666       __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
23667       __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
23668       __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
23669       __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
23670       __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
23671       __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
23672       __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
23673       __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
23674       __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
23675       __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
23676       __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
23677       __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
23678       __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
23679       __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
23680       __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
23681       __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
23682       __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
23683       __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
23684       __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
23685       __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
23686       __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
23687       __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
23688       __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
23689       __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
23690       __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
23691       __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
23692       __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
23693       __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
23694       __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
23695     } INTEN_b;
23696   } ;
23697 
23698   union {
23699     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000064) Read bits from this register to discover the
23700                                                                     cause of a recent interrupt.                               */
23701 
23702     struct {
23703       __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
23704       __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
23705       __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
23706       __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
23707       __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
23708       __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
23709       __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
23710       __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
23711       __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
23712       __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
23713       __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
23714       __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
23715       __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
23716       __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
23717       __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
23718       __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
23719       __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
23720       __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
23721       __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
23722       __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
23723       __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
23724       __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
23725       __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
23726       __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
23727       __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
23728       __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
23729       __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
23730       __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
23731       __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
23732       __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
23733       __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
23734       __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
23735     } INTSTAT_b;
23736   } ;
23737 
23738   union {
23739     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000068) Write a 1 to a bit in this register to clear
23740                                                                     the interrupt status associated with that
23741                                                                     bit.                                                       */
23742 
23743     struct {
23744       __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
23745       __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
23746       __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
23747       __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
23748       __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
23749       __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
23750       __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
23751       __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
23752       __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
23753       __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
23754       __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
23755       __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
23756       __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
23757       __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
23758       __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
23759       __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
23760       __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
23761       __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
23762       __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
23763       __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
23764       __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
23765       __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
23766       __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
23767       __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
23768       __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
23769       __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
23770       __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
23771       __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
23772       __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
23773       __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
23774       __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
23775       __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
23776     } INTCLR_b;
23777   } ;
23778 
23779   union {
23780     __IOM uint32_t INTSET;                      /*!< (@ 0x0000006C) Write a 1 to a bit in this register to instantly
23781                                                                     generate an interrupt from this module.
23782                                                                     (Generally used for testing purposes).                     */
23783 
23784     struct {
23785       __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
23786       __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
23787       __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
23788       __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
23789       __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
23790       __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
23791       __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
23792       __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
23793       __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
23794       __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
23795       __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
23796       __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
23797       __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
23798       __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
23799       __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
23800       __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
23801       __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
23802       __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
23803       __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
23804       __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
23805       __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
23806       __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
23807       __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
23808       __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
23809       __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
23810       __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
23811       __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
23812       __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
23813       __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
23814       __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
23815       __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
23816       __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
23817     } INTSET_b;
23818   } ;
23819   __IM  uint32_t  RESERVED2[4];
23820 
23821   union {
23822     __IOM uint32_t OUTCFG0;                     /*!< (@ 0x00000080) Pad output configuration 0.                                */
23823 
23824     struct {
23825       __IOM uint32_t OUTCFG0    : 6;            /*!< [5..0] Pad output 0 configuration                                         */
23826             uint32_t            : 2;
23827       __IOM uint32_t OUTCFG1    : 6;            /*!< [13..8] Pad output 1 configuration                                        */
23828             uint32_t            : 2;
23829       __IOM uint32_t OUTCFG2    : 6;            /*!< [21..16] Pad output 2 configuration                                       */
23830             uint32_t            : 2;
23831       __IOM uint32_t OUTCFG3    : 6;            /*!< [29..24] Pad output 3 configuration                                       */
23832             uint32_t            : 2;
23833     } OUTCFG0_b;
23834   } ;
23835 
23836   union {
23837     __IOM uint32_t OUTCFG1;                     /*!< (@ 0x00000084) Pad output configuration 0.                                */
23838 
23839     struct {
23840       __IOM uint32_t OUTCFG4    : 6;            /*!< [5..0] Pad output 4 configuration                                         */
23841             uint32_t            : 2;
23842       __IOM uint32_t OUTCFG5    : 6;            /*!< [13..8] Pad output 5 configuration                                        */
23843             uint32_t            : 2;
23844       __IOM uint32_t OUTCFG6    : 6;            /*!< [21..16] Pad output 6 configuration                                       */
23845             uint32_t            : 2;
23846       __IOM uint32_t OUTCFG7    : 6;            /*!< [29..24] Pad output 7 configuration                                       */
23847             uint32_t            : 2;
23848     } OUTCFG1_b;
23849   } ;
23850 
23851   union {
23852     __IOM uint32_t OUTCFG2;                     /*!< (@ 0x00000088) Pad output configuration 0.                                */
23853 
23854     struct {
23855       __IOM uint32_t OUTCFG8    : 6;            /*!< [5..0] Pad output 8 configuration                                         */
23856             uint32_t            : 2;
23857       __IOM uint32_t OUTCFG9    : 6;            /*!< [13..8] Pad output 9 configuration                                        */
23858             uint32_t            : 2;
23859       __IOM uint32_t OUTCFG10   : 6;            /*!< [21..16] Pad output 10 configuration                                      */
23860             uint32_t            : 2;
23861       __IOM uint32_t OUTCFG11   : 6;            /*!< [29..24] Pad output 11 configuration                                      */
23862             uint32_t            : 2;
23863     } OUTCFG2_b;
23864   } ;
23865 
23866   union {
23867     __IOM uint32_t OUTCFG3;                     /*!< (@ 0x0000008C) Pad output configuration 0.                                */
23868 
23869     struct {
23870       __IOM uint32_t OUTCFG12   : 6;            /*!< [5..0] Pad output 12 configuration                                        */
23871             uint32_t            : 2;
23872       __IOM uint32_t OUTCFG13   : 6;            /*!< [13..8] Pad output 13 configuration                                       */
23873             uint32_t            : 2;
23874       __IOM uint32_t OUTCFG14   : 6;            /*!< [21..16] Pad output 14 configuration                                      */
23875             uint32_t            : 2;
23876       __IOM uint32_t OUTCFG15   : 6;            /*!< [29..24] Pad output 15 configuration                                      */
23877             uint32_t            : 2;
23878     } OUTCFG3_b;
23879   } ;
23880 
23881   union {
23882     __IOM uint32_t OUTCFG4;                     /*!< (@ 0x00000090) Pad output configuration 0.                                */
23883 
23884     struct {
23885       __IOM uint32_t OUTCFG16   : 6;            /*!< [5..0] Pad output 16 configuration                                        */
23886             uint32_t            : 2;
23887       __IOM uint32_t OUTCFG17   : 6;            /*!< [13..8] Pad output 17 configuration                                       */
23888             uint32_t            : 2;
23889       __IOM uint32_t OUTCFG18   : 6;            /*!< [21..16] Pad output 18 configuration                                      */
23890             uint32_t            : 2;
23891       __IOM uint32_t OUTCFG19   : 6;            /*!< [29..24] Pad output 19 configuration                                      */
23892             uint32_t            : 2;
23893     } OUTCFG4_b;
23894   } ;
23895 
23896   union {
23897     __IOM uint32_t OUTCFG5;                     /*!< (@ 0x00000094) Pad output configuration 0.                                */
23898 
23899     struct {
23900       __IOM uint32_t OUTCFG20   : 6;            /*!< [5..0] Pad output 20 configuration                                        */
23901             uint32_t            : 2;
23902       __IOM uint32_t OUTCFG21   : 6;            /*!< [13..8] Pad output 21 configuration                                       */
23903             uint32_t            : 2;
23904       __IOM uint32_t OUTCFG22   : 6;            /*!< [21..16] Pad output 22 configuration                                      */
23905             uint32_t            : 2;
23906       __IOM uint32_t OUTCFG23   : 6;            /*!< [29..24] Pad output 23 configuration                                      */
23907             uint32_t            : 2;
23908     } OUTCFG5_b;
23909   } ;
23910 
23911   union {
23912     __IOM uint32_t OUTCFG6;                     /*!< (@ 0x00000098) Pad output configuration 0.                                */
23913 
23914     struct {
23915       __IOM uint32_t OUTCFG24   : 6;            /*!< [5..0] Pad output 24 configuration                                        */
23916             uint32_t            : 2;
23917       __IOM uint32_t OUTCFG25   : 6;            /*!< [13..8] Pad output 25 configuration                                       */
23918             uint32_t            : 2;
23919       __IOM uint32_t OUTCFG26   : 6;            /*!< [21..16] Pad output 26 configuration                                      */
23920             uint32_t            : 2;
23921       __IOM uint32_t OUTCFG27   : 6;            /*!< [29..24] Pad output 27 configuration                                      */
23922             uint32_t            : 2;
23923     } OUTCFG6_b;
23924   } ;
23925 
23926   union {
23927     __IOM uint32_t OUTCFG7;                     /*!< (@ 0x0000009C) Pad output configuration 0.                                */
23928 
23929     struct {
23930       __IOM uint32_t OUTCFG28   : 6;            /*!< [5..0] Pad output 28 configuration                                        */
23931             uint32_t            : 2;
23932       __IOM uint32_t OUTCFG29   : 6;            /*!< [13..8] Pad output 29 configuration                                       */
23933             uint32_t            : 2;
23934       __IOM uint32_t OUTCFG30   : 6;            /*!< [21..16] Pad output 30 configuration                                      */
23935             uint32_t            : 2;
23936       __IOM uint32_t OUTCFG31   : 6;            /*!< [29..24] Pad output 31 configuration                                      */
23937             uint32_t            : 2;
23938     } OUTCFG7_b;
23939   } ;
23940 
23941   union {
23942     __IOM uint32_t OUTCFG8;                     /*!< (@ 0x000000A0) Pad output configuration 0.                                */
23943 
23944     struct {
23945       __IOM uint32_t OUTCFG32   : 6;            /*!< [5..0] Pad output 32 configuration                                        */
23946             uint32_t            : 2;
23947       __IOM uint32_t OUTCFG33   : 6;            /*!< [13..8] Pad output 33 configuration                                       */
23948             uint32_t            : 2;
23949       __IOM uint32_t OUTCFG34   : 6;            /*!< [21..16] Pad output 34 configuration                                      */
23950             uint32_t            : 2;
23951       __IOM uint32_t OUTCFG35   : 6;            /*!< [29..24] Pad output 35 configuration                                      */
23952             uint32_t            : 2;
23953     } OUTCFG8_b;
23954   } ;
23955 
23956   union {
23957     __IOM uint32_t OUTCFG9;                     /*!< (@ 0x000000A4) Pad output configuration 0.                                */
23958 
23959     struct {
23960       __IOM uint32_t OUTCFG36   : 6;            /*!< [5..0] Pad output 36 configuration                                        */
23961             uint32_t            : 2;
23962       __IOM uint32_t OUTCFG37   : 6;            /*!< [13..8] Pad output 37 configuration                                       */
23963             uint32_t            : 2;
23964       __IOM uint32_t OUTCFG38   : 6;            /*!< [21..16] Pad output 38 configuration                                      */
23965             uint32_t            : 2;
23966       __IOM uint32_t OUTCFG39   : 6;            /*!< [29..24] Pad output 39 configuration                                      */
23967             uint32_t            : 2;
23968     } OUTCFG9_b;
23969   } ;
23970 
23971   union {
23972     __IOM uint32_t OUTCFG10;                    /*!< (@ 0x000000A8) Pad output configuration 0.                                */
23973 
23974     struct {
23975       __IOM uint32_t OUTCFG40   : 6;            /*!< [5..0] Pad output 40 configuration                                        */
23976             uint32_t            : 2;
23977       __IOM uint32_t OUTCFG41   : 6;            /*!< [13..8] Pad output 41 configuration                                       */
23978             uint32_t            : 2;
23979       __IOM uint32_t OUTCFG42   : 6;            /*!< [21..16] Pad output 42 configuration                                      */
23980             uint32_t            : 2;
23981       __IOM uint32_t OUTCFG43   : 6;            /*!< [29..24] Pad output 43 configuration                                      */
23982             uint32_t            : 2;
23983     } OUTCFG10_b;
23984   } ;
23985 
23986   union {
23987     __IOM uint32_t OUTCFG11;                    /*!< (@ 0x000000AC) Pad output configuration 0.                                */
23988 
23989     struct {
23990       __IOM uint32_t OUTCFG44   : 6;            /*!< [5..0] Pad output 44 configuration                                        */
23991             uint32_t            : 2;
23992       __IOM uint32_t OUTCFG45   : 6;            /*!< [13..8] Pad output 45 configuration                                       */
23993             uint32_t            : 2;
23994       __IOM uint32_t OUTCFG46   : 6;            /*!< [21..16] Pad output 46 configuration                                      */
23995             uint32_t            : 2;
23996       __IOM uint32_t OUTCFG47   : 6;            /*!< [29..24] Pad output 47 configuration                                      */
23997             uint32_t            : 2;
23998     } OUTCFG11_b;
23999   } ;
24000 
24001   union {
24002     __IOM uint32_t OUTCFG12;                    /*!< (@ 0x000000B0) Pad output configuration 0.                                */
24003 
24004     struct {
24005       __IOM uint32_t OUTCFG48   : 6;            /*!< [5..0] Pad output 48 configuration                                        */
24006             uint32_t            : 2;
24007       __IOM uint32_t OUTCFG49   : 6;            /*!< [13..8] Pad output 49 configuration                                       */
24008             uint32_t            : 2;
24009       __IOM uint32_t OUTCFG50   : 6;            /*!< [21..16] Pad output 50 configuration                                      */
24010             uint32_t            : 2;
24011       __IOM uint32_t OUTCFG51   : 6;            /*!< [29..24] Pad output 51 configuration                                      */
24012             uint32_t            : 2;
24013     } OUTCFG12_b;
24014   } ;
24015 
24016   union {
24017     __IOM uint32_t OUTCFG13;                    /*!< (@ 0x000000B4) Pad output configuration 0.                                */
24018 
24019     struct {
24020       __IOM uint32_t OUTCFG52   : 6;            /*!< [5..0] Pad output 52 configuration                                        */
24021             uint32_t            : 2;
24022       __IOM uint32_t OUTCFG53   : 6;            /*!< [13..8] Pad output 53 configuration                                       */
24023             uint32_t            : 2;
24024       __IOM uint32_t OUTCFG54   : 6;            /*!< [21..16] Pad output 54 configuration                                      */
24025             uint32_t            : 2;
24026       __IOM uint32_t OUTCFG55   : 6;            /*!< [29..24] Pad output 55 configuration                                      */
24027             uint32_t            : 2;
24028     } OUTCFG13_b;
24029   } ;
24030 
24031   union {
24032     __IOM uint32_t OUTCFG14;                    /*!< (@ 0x000000B8) Pad output configuration 0.                                */
24033 
24034     struct {
24035       __IOM uint32_t OUTCFG56   : 6;            /*!< [5..0] Pad output 56 configuration                                        */
24036             uint32_t            : 2;
24037       __IOM uint32_t OUTCFG57   : 6;            /*!< [13..8] Pad output 57 configuration                                       */
24038             uint32_t            : 2;
24039       __IOM uint32_t OUTCFG58   : 6;            /*!< [21..16] Pad output 58 configuration                                      */
24040             uint32_t            : 2;
24041       __IOM uint32_t OUTCFG59   : 6;            /*!< [29..24] Pad output 59 configuration                                      */
24042             uint32_t            : 2;
24043     } OUTCFG14_b;
24044   } ;
24045 
24046   union {
24047     __IOM uint32_t OUTCFG15;                    /*!< (@ 0x000000BC) Pad output configuration 0.                                */
24048 
24049     struct {
24050       __IOM uint32_t OUTCFG60   : 6;            /*!< [5..0] Pad output 60 configuration                                        */
24051             uint32_t            : 2;
24052       __IOM uint32_t OUTCFG61   : 6;            /*!< [13..8] Pad output 61 configuration                                       */
24053             uint32_t            : 2;
24054       __IOM uint32_t OUTCFG62   : 6;            /*!< [21..16] Pad output 62 configuration                                      */
24055             uint32_t            : 2;
24056       __IOM uint32_t OUTCFG63   : 6;            /*!< [29..24] Pad output 63 configuration                                      */
24057             uint32_t            : 2;
24058     } OUTCFG15_b;
24059   } ;
24060 
24061   union {
24062     __IOM uint32_t OUTCFG16;                    /*!< (@ 0x000000C0) Pad output configuration 0.                                */
24063 
24064     struct {
24065       __IOM uint32_t OUTCFG64   : 6;            /*!< [5..0] Pad output 64 configuration                                        */
24066             uint32_t            : 2;
24067       __IOM uint32_t OUTCFG65   : 6;            /*!< [13..8] Pad output 65 configuration                                       */
24068             uint32_t            : 2;
24069       __IOM uint32_t OUTCFG66   : 6;            /*!< [21..16] Pad output 66 configuration                                      */
24070             uint32_t            : 2;
24071       __IOM uint32_t OUTCFG67   : 6;            /*!< [29..24] Pad output 67 configuration                                      */
24072             uint32_t            : 2;
24073     } OUTCFG16_b;
24074   } ;
24075 
24076   union {
24077     __IOM uint32_t OUTCFG17;                    /*!< (@ 0x000000C4) Pad output configuration 0.                                */
24078 
24079     struct {
24080       __IOM uint32_t OUTCFG68   : 6;            /*!< [5..0] Pad output 68 configuration                                        */
24081             uint32_t            : 2;
24082       __IOM uint32_t OUTCFG69   : 6;            /*!< [13..8] Pad output 69 configuration                                       */
24083             uint32_t            : 2;
24084       __IOM uint32_t OUTCFG70   : 6;            /*!< [21..16] Pad output 70 configuration                                      */
24085             uint32_t            : 2;
24086       __IOM uint32_t OUTCFG71   : 6;            /*!< [29..24] Pad output 71 configuration                                      */
24087             uint32_t            : 2;
24088     } OUTCFG17_b;
24089   } ;
24090 
24091   union {
24092     __IOM uint32_t OUTCFG18;                    /*!< (@ 0x000000C8) Pad output configuration 0.                                */
24093 
24094     struct {
24095       __IOM uint32_t OUTCFG72   : 6;            /*!< [5..0] Pad output 72 configuration                                        */
24096             uint32_t            : 2;
24097       __IOM uint32_t OUTCFG73   : 6;            /*!< [13..8] Pad output 73 configuration                                       */
24098             uint32_t            : 2;
24099       __IOM uint32_t OUTCFG74   : 6;            /*!< [21..16] Pad output 74 configuration                                      */
24100             uint32_t            : 2;
24101       __IOM uint32_t OUTCFG75   : 6;            /*!< [29..24] Pad output 75 configuration                                      */
24102             uint32_t            : 2;
24103     } OUTCFG18_b;
24104   } ;
24105 
24106   union {
24107     __IOM uint32_t OUTCFG19;                    /*!< (@ 0x000000CC) Pad output configuration 0.                                */
24108 
24109     struct {
24110       __IOM uint32_t OUTCFG76   : 6;            /*!< [5..0] Pad output 76 configuration                                        */
24111             uint32_t            : 2;
24112       __IOM uint32_t OUTCFG77   : 6;            /*!< [13..8] Pad output 77 configuration                                       */
24113             uint32_t            : 2;
24114       __IOM uint32_t OUTCFG78   : 6;            /*!< [21..16] Pad output 78 configuration                                      */
24115             uint32_t            : 2;
24116       __IOM uint32_t OUTCFG79   : 6;            /*!< [29..24] Pad output 79 configuration                                      */
24117             uint32_t            : 2;
24118     } OUTCFG19_b;
24119   } ;
24120 
24121   union {
24122     __IOM uint32_t OUTCFG20;                    /*!< (@ 0x000000D0) Pad output configuration 0.                                */
24123 
24124     struct {
24125       __IOM uint32_t OUTCFG80   : 6;            /*!< [5..0] Pad output 80 configuration                                        */
24126             uint32_t            : 2;
24127       __IOM uint32_t OUTCFG81   : 6;            /*!< [13..8] Pad output 81 configuration                                       */
24128             uint32_t            : 2;
24129       __IOM uint32_t OUTCFG82   : 6;            /*!< [21..16] Pad output 82 configuration                                      */
24130             uint32_t            : 2;
24131       __IOM uint32_t OUTCFG83   : 6;            /*!< [29..24] Pad output 83 configuration                                      */
24132             uint32_t            : 2;
24133     } OUTCFG20_b;
24134   } ;
24135 
24136   union {
24137     __IOM uint32_t OUTCFG21;                    /*!< (@ 0x000000D4) Pad output configuration 0.                                */
24138 
24139     struct {
24140       __IOM uint32_t OUTCFG84   : 6;            /*!< [5..0] Pad output 84 configuration                                        */
24141             uint32_t            : 2;
24142       __IOM uint32_t OUTCFG85   : 6;            /*!< [13..8] Pad output 85 configuration                                       */
24143             uint32_t            : 2;
24144       __IOM uint32_t OUTCFG86   : 6;            /*!< [21..16] Pad output 86 configuration                                      */
24145             uint32_t            : 2;
24146       __IOM uint32_t OUTCFG87   : 6;            /*!< [29..24] Pad output 87 configuration                                      */
24147             uint32_t            : 2;
24148     } OUTCFG21_b;
24149   } ;
24150 
24151   union {
24152     __IOM uint32_t OUTCFG22;                    /*!< (@ 0x000000D8) Pad output configuration 0.                                */
24153 
24154     struct {
24155       __IOM uint32_t OUTCFG88   : 6;            /*!< [5..0] Pad output 88 configuration                                        */
24156             uint32_t            : 2;
24157       __IOM uint32_t OUTCFG89   : 6;            /*!< [13..8] Pad output 89 configuration                                       */
24158             uint32_t            : 2;
24159       __IOM uint32_t OUTCFG90   : 6;            /*!< [21..16] Pad output 90 configuration                                      */
24160             uint32_t            : 2;
24161       __IOM uint32_t OUTCFG91   : 6;            /*!< [29..24] Pad output 91 configuration                                      */
24162             uint32_t            : 2;
24163     } OUTCFG22_b;
24164   } ;
24165 
24166   union {
24167     __IOM uint32_t OUTCFG23;                    /*!< (@ 0x000000DC) Pad output configuration 0.                                */
24168 
24169     struct {
24170       __IOM uint32_t OUTCFG92   : 6;            /*!< [5..0] Pad output 92 configuration                                        */
24171             uint32_t            : 2;
24172       __IOM uint32_t OUTCFG93   : 6;            /*!< [13..8] Pad output 93 configuration                                       */
24173             uint32_t            : 2;
24174       __IOM uint32_t OUTCFG94   : 6;            /*!< [21..16] Pad output 94 configuration                                      */
24175             uint32_t            : 2;
24176       __IOM uint32_t OUTCFG95   : 6;            /*!< [29..24] Pad output 95 configuration                                      */
24177             uint32_t            : 2;
24178     } OUTCFG23_b;
24179   } ;
24180 
24181   union {
24182     __IOM uint32_t OUTCFG24;                    /*!< (@ 0x000000E0) Pad output configuration 0.                                */
24183 
24184     struct {
24185       __IOM uint32_t OUTCFG96   : 6;            /*!< [5..0] Pad output 96 configuration                                        */
24186             uint32_t            : 2;
24187       __IOM uint32_t OUTCFG97   : 6;            /*!< [13..8] Pad output 97 configuration                                       */
24188             uint32_t            : 2;
24189       __IOM uint32_t OUTCFG98   : 6;            /*!< [21..16] Pad output 98 configuration                                      */
24190             uint32_t            : 2;
24191       __IOM uint32_t OUTCFG99   : 6;            /*!< [29..24] Pad output 99 configuration                                      */
24192             uint32_t            : 2;
24193     } OUTCFG24_b;
24194   } ;
24195 
24196   union {
24197     __IOM uint32_t OUTCFG25;                    /*!< (@ 0x000000E4) Pad output configuration 0.                                */
24198 
24199     struct {
24200       __IOM uint32_t OUTCFG100  : 6;            /*!< [5..0] Pad output 100 configuration                                       */
24201             uint32_t            : 2;
24202       __IOM uint32_t OUTCFG101  : 6;            /*!< [13..8] Pad output 101 configuration                                      */
24203             uint32_t            : 2;
24204       __IOM uint32_t OUTCFG102  : 6;            /*!< [21..16] Pad output 102 configuration                                     */
24205             uint32_t            : 2;
24206       __IOM uint32_t OUTCFG103  : 6;            /*!< [29..24] Pad output 103 configuration                                     */
24207             uint32_t            : 2;
24208     } OUTCFG25_b;
24209   } ;
24210 
24211   union {
24212     __IOM uint32_t OUTCFG26;                    /*!< (@ 0x000000E8) Pad output configuration 0.                                */
24213 
24214     struct {
24215       __IOM uint32_t OUTCFG104  : 6;            /*!< [5..0] Pad output 104 configuration                                       */
24216             uint32_t            : 2;
24217       __IOM uint32_t OUTCFG105  : 6;            /*!< [13..8] Pad output 105 configuration                                      */
24218             uint32_t            : 2;
24219       __IOM uint32_t OUTCFG106  : 6;            /*!< [21..16] Pad output 106 configuration                                     */
24220             uint32_t            : 2;
24221       __IOM uint32_t OUTCFG107  : 6;            /*!< [29..24] Pad output 107 configuration                                     */
24222             uint32_t            : 2;
24223     } OUTCFG26_b;
24224   } ;
24225 
24226   union {
24227     __IOM uint32_t OUTCFG27;                    /*!< (@ 0x000000EC) Pad output configuration 0.                                */
24228 
24229     struct {
24230       __IOM uint32_t OUTCFG108  : 6;            /*!< [5..0] Pad output 108 configuration                                       */
24231             uint32_t            : 2;
24232       __IOM uint32_t OUTCFG109  : 6;            /*!< [13..8] Pad output 109 configuration                                      */
24233             uint32_t            : 2;
24234       __IOM uint32_t OUTCFG110  : 6;            /*!< [21..16] Pad output 110 configuration                                     */
24235             uint32_t            : 2;
24236       __IOM uint32_t OUTCFG111  : 6;            /*!< [29..24] Pad output 111 configuration                                     */
24237             uint32_t            : 2;
24238     } OUTCFG27_b;
24239   } ;
24240 
24241   union {
24242     __IOM uint32_t OUTCFG28;                    /*!< (@ 0x000000F0) Pad output configuration 0.                                */
24243 
24244     struct {
24245       __IOM uint32_t OUTCFG112  : 6;            /*!< [5..0] Pad output 112 configuration                                       */
24246             uint32_t            : 2;
24247       __IOM uint32_t OUTCFG113  : 6;            /*!< [13..8] Pad output 113 configuration                                      */
24248             uint32_t            : 2;
24249       __IOM uint32_t OUTCFG114  : 6;            /*!< [21..16] Pad output 114 configuration                                     */
24250             uint32_t            : 2;
24251       __IOM uint32_t OUTCFG115  : 6;            /*!< [29..24] Pad output 115 configuration                                     */
24252             uint32_t            : 2;
24253     } OUTCFG28_b;
24254   } ;
24255 
24256   union {
24257     __IOM uint32_t OUTCFG29;                    /*!< (@ 0x000000F4) Pad output configuration 0.                                */
24258 
24259     struct {
24260       __IOM uint32_t OUTCFG116  : 6;            /*!< [5..0] Pad output 116 configuration                                       */
24261             uint32_t            : 2;
24262       __IOM uint32_t OUTCFG117  : 6;            /*!< [13..8] Pad output 117 configuration                                      */
24263             uint32_t            : 2;
24264       __IOM uint32_t OUTCFG118  : 6;            /*!< [21..16] Pad output 118 configuration                                     */
24265             uint32_t            : 2;
24266       __IOM uint32_t OUTCFG119  : 6;            /*!< [29..24] Pad output 119 configuration                                     */
24267             uint32_t            : 2;
24268     } OUTCFG29_b;
24269   } ;
24270 
24271   union {
24272     __IOM uint32_t OUTCFG30;                    /*!< (@ 0x000000F8) Pad output configuration 0.                                */
24273 
24274     struct {
24275       __IOM uint32_t OUTCFG120  : 6;            /*!< [5..0] Pad output 120 configuration                                       */
24276             uint32_t            : 2;
24277       __IOM uint32_t OUTCFG121  : 6;            /*!< [13..8] Pad output 121 configuration                                      */
24278             uint32_t            : 2;
24279       __IOM uint32_t OUTCFG122  : 6;            /*!< [21..16] Pad output 122 configuration                                     */
24280             uint32_t            : 2;
24281       __IOM uint32_t OUTCFG123  : 6;            /*!< [29..24] Pad output 123 configuration                                     */
24282             uint32_t            : 2;
24283     } OUTCFG30_b;
24284   } ;
24285 
24286   union {
24287     __IOM uint32_t OUTCFG31;                    /*!< (@ 0x000000FC) Pad output configuration 0.                                */
24288 
24289     struct {
24290       __IOM uint32_t OUTCFG124  : 6;            /*!< [5..0] Pad output 124 configuration                                       */
24291             uint32_t            : 2;
24292       __IOM uint32_t OUTCFG125  : 6;            /*!< [13..8] Pad output 125 configuration                                      */
24293             uint32_t            : 2;
24294       __IOM uint32_t OUTCFG126  : 6;            /*!< [21..16] Pad output 126 configuration                                     */
24295             uint32_t            : 2;
24296       __IOM uint32_t OUTCFG127  : 6;            /*!< [29..24] Pad output 127 configuration                                     */
24297             uint32_t            : 2;
24298     } OUTCFG31_b;
24299   } ;
24300   __IM  uint32_t  RESERVED3[64];
24301 
24302   union {
24303     __IOM uint32_t CTRL0;                       /*!< (@ 0x00000200) This includes the Control bit fields for timer
24304                                                                     0.                                                         */
24305 
24306     struct {
24307       __IOM uint32_t TMR0EN     : 1;            /*!< [0..0] Counter/Timer 0 Enable bit.                                        */
24308       __IOM uint32_t TMR0CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24309       __IOM uint32_t TMR0POL0   : 1;            /*!< [2..2] Counter/Timer 0 output 0 polarity.                                 */
24310       __IOM uint32_t TMR0POL1   : 1;            /*!< [3..3] Counter/Timer 0 output 1 polarity.                                 */
24311       __IOM uint32_t TMR0FN     : 4;            /*!< [7..4] Counter/Timer 0 Function Select. For all Functions, CMP0
24312                                                      marks the end of timer cycle, and thus restarts the timer.                */
24313       __IOM uint32_t TMR0CLK    : 8;            /*!< [15..8] Counter/Timer 0 Clock Select.                                     */
24314       __IOM uint32_t TMR0TMODE  : 2;            /*!< [17..16] Counter/Timer 0 Trigger Mode                                     */
24315             uint32_t            : 6;
24316       __IOM uint32_t TMR0LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
24317                                                      0. For Single/Repeat Patterns, it indicates number of bits
24318                                                      to be shifted out and so, max value is 63.                                */
24319     } CTRL0_b;
24320   } ;
24321 
24322   union {
24323     __IOM uint32_t TIMER0;                      /*!< (@ 0x00000204) This register holds the running time or event
24324                                                                     count for timer 0.                                         */
24325 
24326     struct {
24327       __IOM uint32_t TIMER0     : 32;           /*!< [31..0] Counter/Timer 0                                                   */
24328     } TIMER0_b;
24329   } ;
24330 
24331   union {
24332     __IOM uint32_t TMR0CMP0;                    /*!< (@ 0x00000208) This contains the Compare limits for timer 0.
24333                                                                     This is the primary comparator that can
24334                                                                     be used to mark the END of a timer cycle
24335                                                                     (and thus restart the timer for repeat modes)              */
24336 
24337     struct {
24338       __IOM uint32_t TMR0CMP0   : 32;           /*!< [31..0] Counter/Timer 0 End Compare Register. For MEASURE mode
24339                                                      indicates the high phase sample count.                                    */
24340     } TMR0CMP0_b;
24341   } ;
24342 
24343   union {
24344     __IOM uint32_t TMR0CMP1;                    /*!< (@ 0x0000020C) This comparator is used as a secondary compare
24345                                                                     count for modes that generate pulses. For
24346                                                                     MEASURE mode indicates the low phase sample
24347                                                                     count.                                                     */
24348 
24349     struct {
24350       __IOM uint32_t TMR0CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24351                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24352                                                      be used first.                                                            */
24353     } TMR0CMP1_b;
24354   } ;
24355 
24356   union {
24357     __IOM uint32_t MODE0;                       /*!< (@ 0x00000210) The mode register contains optional mode controls
24358                                                                     for the timer                                              */
24359 
24360     struct {
24361             uint32_t            : 8;
24362       __IOM uint32_t TMR0TRIGSEL : 8;           /*!< [15..8] Counter/Timer 0 Trigger Source Selection                          */
24363             uint32_t            : 16;
24364     } MODE0_b;
24365   } ;
24366 
24367   union {
24368     __IOM uint32_t TMR0LMTVAL;                  /*!< (@ 0x00000214) This is an internal counter in the hardware that
24369                                                                     counts down from TMR_LMT to 1                              */
24370 
24371     struct {
24372       __IOM uint32_t TMR0LMTVAL : 8;            /*!< [7..0] Counter/Timer 0 Limit Readback                                     */
24373             uint32_t            : 24;
24374     } TMR0LMTVAL_b;
24375   } ;
24376   __IM  uint32_t  RESERVED4[2];
24377 
24378   union {
24379     __IOM uint32_t CTRL1;                       /*!< (@ 0x00000220) This includes the Control bit fields for timer
24380                                                                     1.                                                         */
24381 
24382     struct {
24383       __IOM uint32_t TMR1EN     : 1;            /*!< [0..0] Counter/Timer 1 Enable bit.                                        */
24384       __IOM uint32_t TMR1CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24385       __IOM uint32_t TMR1POL0   : 1;            /*!< [2..2] Counter/Timer 1 output 0 polarity.                                 */
24386       __IOM uint32_t TMR1POL1   : 1;            /*!< [3..3] Counter/Timer 1 output 1 polarity.                                 */
24387       __IOM uint32_t TMR1FN     : 4;            /*!< [7..4] Counter/Timer 1 Function Select. For all Functions, CMP0
24388                                                      marks the end of timer cycle, and thus restarts the timer.                */
24389       __IOM uint32_t TMR1CLK    : 8;            /*!< [15..8] Counter/Timer 1 Clock Select.                                     */
24390       __IOM uint32_t TMR1TMODE  : 2;            /*!< [17..16] Counter/Timer 1 Trigger Mode                                     */
24391             uint32_t            : 6;
24392       __IOM uint32_t TMR1LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
24393                                                      1. For Single/Repeat Patterns, it indicates number of bits
24394                                                      to be shifted out and so, max value is 63.                                */
24395     } CTRL1_b;
24396   } ;
24397 
24398   union {
24399     __IOM uint32_t TIMER1;                      /*!< (@ 0x00000224) This register holds the running time or event
24400                                                                     count for timer 1.                                         */
24401 
24402     struct {
24403       __IOM uint32_t TIMER1     : 32;           /*!< [31..0] Counter/Timer 1                                                   */
24404     } TIMER1_b;
24405   } ;
24406 
24407   union {
24408     __IOM uint32_t TMR1CMP0;                    /*!< (@ 0x00000228) This contains the Compare limits for timer 1.
24409                                                                     This is the primary comparator that can
24410                                                                     be used to mark the END of a timer cycle
24411                                                                     (and thus restart the timer for repeat modes)              */
24412 
24413     struct {
24414       __IOM uint32_t TMR1CMP0   : 32;           /*!< [31..0] Counter/Timer 1 End Compare Register. For MEASURE mode
24415                                                      indicates the high phase sample count.                                    */
24416     } TMR1CMP0_b;
24417   } ;
24418 
24419   union {
24420     __IOM uint32_t TMR1CMP1;                    /*!< (@ 0x0000022C) This comparator is used as a secondary compare
24421                                                                     count for modes that generate pulses. For
24422                                                                     MEASURE mode indicates the low phase sample
24423                                                                     count.                                                     */
24424 
24425     struct {
24426       __IOM uint32_t TMR1CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24427                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24428                                                      be used first.                                                            */
24429     } TMR1CMP1_b;
24430   } ;
24431 
24432   union {
24433     __IOM uint32_t MODE1;                       /*!< (@ 0x00000230) The mode register contains optional mode controls
24434                                                                     for the timer                                              */
24435 
24436     struct {
24437             uint32_t            : 8;
24438       __IOM uint32_t TMR1TRIGSEL : 8;           /*!< [15..8] Counter/Timer 1 Trigger Source Selection                          */
24439             uint32_t            : 16;
24440     } MODE1_b;
24441   } ;
24442 
24443   union {
24444     __IOM uint32_t TMR1LMTVAL;                  /*!< (@ 0x00000234) This is an internal counter in the hardware that
24445                                                                     counts down from TMR_LMT to 1                              */
24446 
24447     struct {
24448       __IOM uint32_t TMR1LMTVAL : 8;            /*!< [7..0] Counter/Timer 1 Limit Readback                                     */
24449             uint32_t            : 24;
24450     } TMR1LMTVAL_b;
24451   } ;
24452   __IM  uint32_t  RESERVED5[2];
24453 
24454   union {
24455     __IOM uint32_t CTRL2;                       /*!< (@ 0x00000240) This includes the Control bit fields for timer
24456                                                                     2.                                                         */
24457 
24458     struct {
24459       __IOM uint32_t TMR2EN     : 1;            /*!< [0..0] Counter/Timer 2 Enable bit.                                        */
24460       __IOM uint32_t TMR2CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24461       __IOM uint32_t TMR2POL0   : 1;            /*!< [2..2] Counter/Timer 2 output 0 polarity.                                 */
24462       __IOM uint32_t TMR2POL1   : 1;            /*!< [3..3] Counter/Timer 2 output 1 polarity.                                 */
24463       __IOM uint32_t TMR2FN     : 4;            /*!< [7..4] Counter/Timer 2 Function Select. For all Functions, CMP0
24464                                                      marks the end of timer cycle, and thus restarts the timer.                */
24465       __IOM uint32_t TMR2CLK    : 8;            /*!< [15..8] Counter/Timer 2 Clock Select.                                     */
24466       __IOM uint32_t TMR2TMODE  : 2;            /*!< [17..16] Counter/Timer 2 Trigger Mode                                     */
24467             uint32_t            : 6;
24468       __IOM uint32_t TMR2LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
24469                                                      2. For Single/Repeat Patterns, it indicates number of bits
24470                                                      to be shifted out and so, max value is 63.                                */
24471     } CTRL2_b;
24472   } ;
24473 
24474   union {
24475     __IOM uint32_t TIMER2;                      /*!< (@ 0x00000244) This register holds the running time or event
24476                                                                     count for timer 2.                                         */
24477 
24478     struct {
24479       __IOM uint32_t TIMER2     : 32;           /*!< [31..0] Counter/Timer 2                                                   */
24480     } TIMER2_b;
24481   } ;
24482 
24483   union {
24484     __IOM uint32_t TMR2CMP0;                    /*!< (@ 0x00000248) This contains the Compare limits for timer 2.
24485                                                                     This is the primary comparator that can
24486                                                                     be used to mark the END of a timer cycle
24487                                                                     (and thus restart the timer for repeat modes)              */
24488 
24489     struct {
24490       __IOM uint32_t TMR2CMP0   : 32;           /*!< [31..0] Counter/Timer 2 End Compare Register. For MEASURE mode
24491                                                      indicates the high phase sample count.                                    */
24492     } TMR2CMP0_b;
24493   } ;
24494 
24495   union {
24496     __IOM uint32_t TMR2CMP1;                    /*!< (@ 0x0000024C) This comparator is used as a secondary compare
24497                                                                     count for modes that generate pulses. For
24498                                                                     MEASURE mode indicates the low phase sample
24499                                                                     count.                                                     */
24500 
24501     struct {
24502       __IOM uint32_t TMR2CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24503                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24504                                                      be used first.                                                            */
24505     } TMR2CMP1_b;
24506   } ;
24507 
24508   union {
24509     __IOM uint32_t MODE2;                       /*!< (@ 0x00000250) The mode register contains optional mode controls
24510                                                                     for the timer                                              */
24511 
24512     struct {
24513             uint32_t            : 8;
24514       __IOM uint32_t TMR2TRIGSEL : 8;           /*!< [15..8] Counter/Timer 2 Trigger Source Selection                          */
24515             uint32_t            : 16;
24516     } MODE2_b;
24517   } ;
24518 
24519   union {
24520     __IOM uint32_t TMR2LMTVAL;                  /*!< (@ 0x00000254) This is an internal counter in the hardware that
24521                                                                     counts down from TMR_LMT to 1                              */
24522 
24523     struct {
24524       __IOM uint32_t TMR2LMTVAL : 8;            /*!< [7..0] Counter/Timer 2 Limit Readback                                     */
24525             uint32_t            : 24;
24526     } TMR2LMTVAL_b;
24527   } ;
24528   __IM  uint32_t  RESERVED6[2];
24529 
24530   union {
24531     __IOM uint32_t CTRL3;                       /*!< (@ 0x00000260) This includes the Control bit fields for timer
24532                                                                     3.                                                         */
24533 
24534     struct {
24535       __IOM uint32_t TMR3EN     : 1;            /*!< [0..0] Counter/Timer 3 Enable bit.                                        */
24536       __IOM uint32_t TMR3CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24537       __IOM uint32_t TMR3POL0   : 1;            /*!< [2..2] Counter/Timer 3 output 0 polarity.                                 */
24538       __IOM uint32_t TMR3POL1   : 1;            /*!< [3..3] Counter/Timer 3 output 1 polarity.                                 */
24539       __IOM uint32_t TMR3FN     : 4;            /*!< [7..4] Counter/Timer 3 Function Select. For all Functions, CMP0
24540                                                      marks the end of timer cycle, and thus restarts the timer.                */
24541       __IOM uint32_t TMR3CLK    : 8;            /*!< [15..8] Counter/Timer 3 Clock Select.                                     */
24542       __IOM uint32_t TMR3TMODE  : 2;            /*!< [17..16] Counter/Timer 3 Trigger Mode                                     */
24543             uint32_t            : 6;
24544       __IOM uint32_t TMR3LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
24545                                                      3. For Single/Repeat Patterns, it indicates number of bits
24546                                                      to be shifted out and so, max value is 63.                                */
24547     } CTRL3_b;
24548   } ;
24549 
24550   union {
24551     __IOM uint32_t TIMER3;                      /*!< (@ 0x00000264) This register holds the running time or event
24552                                                                     count for timer 3.                                         */
24553 
24554     struct {
24555       __IOM uint32_t TIMER3     : 32;           /*!< [31..0] Counter/Timer 3                                                   */
24556     } TIMER3_b;
24557   } ;
24558 
24559   union {
24560     __IOM uint32_t TMR3CMP0;                    /*!< (@ 0x00000268) This contains the Compare limits for timer 3.
24561                                                                     This is the primary comparator that can
24562                                                                     be used to mark the END of a timer cycle
24563                                                                     (and thus restart the timer for repeat modes)              */
24564 
24565     struct {
24566       __IOM uint32_t TMR3CMP0   : 32;           /*!< [31..0] Counter/Timer 3 End Compare Register. For MEASURE mode
24567                                                      indicates the high phase sample count.                                    */
24568     } TMR3CMP0_b;
24569   } ;
24570 
24571   union {
24572     __IOM uint32_t TMR3CMP1;                    /*!< (@ 0x0000026C) This comparator is used as a secondary compare
24573                                                                     count for modes that generate pulses. For
24574                                                                     MEASURE mode indicates the low phase sample
24575                                                                     count.                                                     */
24576 
24577     struct {
24578       __IOM uint32_t TMR3CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24579                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24580                                                      be used first.                                                            */
24581     } TMR3CMP1_b;
24582   } ;
24583 
24584   union {
24585     __IOM uint32_t MODE3;                       /*!< (@ 0x00000270) The mode register contains optional mode controls
24586                                                                     for the timer                                              */
24587 
24588     struct {
24589             uint32_t            : 8;
24590       __IOM uint32_t TMR3TRIGSEL : 8;           /*!< [15..8] Counter/Timer 3 Trigger Source Selection                          */
24591             uint32_t            : 16;
24592     } MODE3_b;
24593   } ;
24594 
24595   union {
24596     __IOM uint32_t TMR3LMTVAL;                  /*!< (@ 0x00000274) This is an internal counter in the hardware that
24597                                                                     counts down from TMR_LMT to 1                              */
24598 
24599     struct {
24600       __IOM uint32_t TMR3LMTVAL : 8;            /*!< [7..0] Counter/Timer 3 Limit Readback                                     */
24601             uint32_t            : 24;
24602     } TMR3LMTVAL_b;
24603   } ;
24604   __IM  uint32_t  RESERVED7[2];
24605 
24606   union {
24607     __IOM uint32_t CTRL4;                       /*!< (@ 0x00000280) This includes the Control bit fields for timer
24608                                                                     4.                                                         */
24609 
24610     struct {
24611       __IOM uint32_t TMR4EN     : 1;            /*!< [0..0] Counter/Timer 4 Enable bit.                                        */
24612       __IOM uint32_t TMR4CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24613       __IOM uint32_t TMR4POL0   : 1;            /*!< [2..2] Counter/Timer 4 output 0 polarity.                                 */
24614       __IOM uint32_t TMR4POL1   : 1;            /*!< [3..3] Counter/Timer 4 output 1 polarity.                                 */
24615       __IOM uint32_t TMR4FN     : 4;            /*!< [7..4] Counter/Timer 4 Function Select. For all Functions, CMP0
24616                                                      marks the end of timer cycle, and thus restarts the timer.                */
24617       __IOM uint32_t TMR4CLK    : 8;            /*!< [15..8] Counter/Timer 4 Clock Select.                                     */
24618       __IOM uint32_t TMR4TMODE  : 2;            /*!< [17..16] Counter/Timer 4 Trigger Mode                                     */
24619             uint32_t            : 6;
24620       __IOM uint32_t TMR4LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
24621                                                      4. For Single/Repeat Patterns, it indicates number of bits
24622                                                      to be shifted out and so, max value is 63.                                */
24623     } CTRL4_b;
24624   } ;
24625 
24626   union {
24627     __IOM uint32_t TIMER4;                      /*!< (@ 0x00000284) This register holds the running time or event
24628                                                                     count for timer 4.                                         */
24629 
24630     struct {
24631       __IOM uint32_t TIMER4     : 32;           /*!< [31..0] Counter/Timer 4                                                   */
24632     } TIMER4_b;
24633   } ;
24634 
24635   union {
24636     __IOM uint32_t TMR4CMP0;                    /*!< (@ 0x00000288) This contains the Compare limits for timer 4.
24637                                                                     This is the primary comparator that can
24638                                                                     be used to mark the END of a timer cycle
24639                                                                     (and thus restart the timer for repeat modes)              */
24640 
24641     struct {
24642       __IOM uint32_t TMR4CMP0   : 32;           /*!< [31..0] Counter/Timer 4 End Compare Register. For MEASURE mode
24643                                                      indicates the high phase sample count.                                    */
24644     } TMR4CMP0_b;
24645   } ;
24646 
24647   union {
24648     __IOM uint32_t TMR4CMP1;                    /*!< (@ 0x0000028C) This comparator is used as a secondary compare
24649                                                                     count for modes that generate pulses. For
24650                                                                     MEASURE mode indicates the low phase sample
24651                                                                     count.                                                     */
24652 
24653     struct {
24654       __IOM uint32_t TMR4CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24655                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24656                                                      be used first.                                                            */
24657     } TMR4CMP1_b;
24658   } ;
24659 
24660   union {
24661     __IOM uint32_t MODE4;                       /*!< (@ 0x00000290) The mode register contains optional mode controls
24662                                                                     for the timer                                              */
24663 
24664     struct {
24665             uint32_t            : 8;
24666       __IOM uint32_t TMR4TRIGSEL : 8;           /*!< [15..8] Counter/Timer 4 Trigger Source Selection                          */
24667             uint32_t            : 16;
24668     } MODE4_b;
24669   } ;
24670 
24671   union {
24672     __IOM uint32_t TMR4LMTVAL;                  /*!< (@ 0x00000294) This is an internal counter in the hardware that
24673                                                                     counts down from TMR_LMT to 1                              */
24674 
24675     struct {
24676       __IOM uint32_t TMR4LMTVAL : 8;            /*!< [7..0] Counter/Timer 4 Limit Readback                                     */
24677             uint32_t            : 24;
24678     } TMR4LMTVAL_b;
24679   } ;
24680   __IM  uint32_t  RESERVED8[2];
24681 
24682   union {
24683     __IOM uint32_t CTRL5;                       /*!< (@ 0x000002A0) This includes the Control bit fields for timer
24684                                                                     5.                                                         */
24685 
24686     struct {
24687       __IOM uint32_t TMR5EN     : 1;            /*!< [0..0] Counter/Timer 5 Enable bit.                                        */
24688       __IOM uint32_t TMR5CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24689       __IOM uint32_t TMR5POL0   : 1;            /*!< [2..2] Counter/Timer 5 output 0 polarity.                                 */
24690       __IOM uint32_t TMR5POL1   : 1;            /*!< [3..3] Counter/Timer 5 output 1 polarity.                                 */
24691       __IOM uint32_t TMR5FN     : 4;            /*!< [7..4] Counter/Timer 5 Function Select. For all Functions, CMP0
24692                                                      marks the end of timer cycle, and thus restarts the timer.                */
24693       __IOM uint32_t TMR5CLK    : 8;            /*!< [15..8] Counter/Timer 5 Clock Select.                                     */
24694       __IOM uint32_t TMR5TMODE  : 2;            /*!< [17..16] Counter/Timer 5 Trigger Mode                                     */
24695             uint32_t            : 6;
24696       __IOM uint32_t TMR5LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
24697                                                      5. For Single/Repeat Patterns, it indicates number of bits
24698                                                      to be shifted out and so, max value is 63.                                */
24699     } CTRL5_b;
24700   } ;
24701 
24702   union {
24703     __IOM uint32_t TIMER5;                      /*!< (@ 0x000002A4) This register holds the running time or event
24704                                                                     count for timer 5.                                         */
24705 
24706     struct {
24707       __IOM uint32_t TIMER5     : 32;           /*!< [31..0] Counter/Timer 5                                                   */
24708     } TIMER5_b;
24709   } ;
24710 
24711   union {
24712     __IOM uint32_t TMR5CMP0;                    /*!< (@ 0x000002A8) This contains the Compare limits for timer 5.
24713                                                                     This is the primary comparator that can
24714                                                                     be used to mark the END of a timer cycle
24715                                                                     (and thus restart the timer for repeat modes)              */
24716 
24717     struct {
24718       __IOM uint32_t TMR5CMP0   : 32;           /*!< [31..0] Counter/Timer 5 End Compare Register. For MEASURE mode
24719                                                      indicates the high phase sample count.                                    */
24720     } TMR5CMP0_b;
24721   } ;
24722 
24723   union {
24724     __IOM uint32_t TMR5CMP1;                    /*!< (@ 0x000002AC) This comparator is used as a secondary compare
24725                                                                     count for modes that generate pulses. For
24726                                                                     MEASURE mode indicates the low phase sample
24727                                                                     count.                                                     */
24728 
24729     struct {
24730       __IOM uint32_t TMR5CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24731                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24732                                                      be used first.                                                            */
24733     } TMR5CMP1_b;
24734   } ;
24735 
24736   union {
24737     __IOM uint32_t MODE5;                       /*!< (@ 0x000002B0) The mode register contains optional mode controls
24738                                                                     for the timer                                              */
24739 
24740     struct {
24741             uint32_t            : 8;
24742       __IOM uint32_t TMR5TRIGSEL : 8;           /*!< [15..8] Counter/Timer 5 Trigger Source Selection                          */
24743             uint32_t            : 16;
24744     } MODE5_b;
24745   } ;
24746 
24747   union {
24748     __IOM uint32_t TMR5LMTVAL;                  /*!< (@ 0x000002B4) This is an internal counter in the hardware that
24749                                                                     counts down from TMR_LMT to 1                              */
24750 
24751     struct {
24752       __IOM uint32_t TMR5LMTVAL : 8;            /*!< [7..0] Counter/Timer 5 Limit Readback                                     */
24753             uint32_t            : 24;
24754     } TMR5LMTVAL_b;
24755   } ;
24756   __IM  uint32_t  RESERVED9[2];
24757 
24758   union {
24759     __IOM uint32_t CTRL6;                       /*!< (@ 0x000002C0) This includes the Control bit fields for timer
24760                                                                     6.                                                         */
24761 
24762     struct {
24763       __IOM uint32_t TMR6EN     : 1;            /*!< [0..0] Counter/Timer 6 Enable bit.                                        */
24764       __IOM uint32_t TMR6CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24765       __IOM uint32_t TMR6POL0   : 1;            /*!< [2..2] Counter/Timer 6 output 0 polarity.                                 */
24766       __IOM uint32_t TMR6POL1   : 1;            /*!< [3..3] Counter/Timer 6 output 1 polarity.                                 */
24767       __IOM uint32_t TMR6FN     : 4;            /*!< [7..4] Counter/Timer 6 Function Select. For all Functions, CMP0
24768                                                      marks the end of timer cycle, and thus restarts the timer.                */
24769       __IOM uint32_t TMR6CLK    : 8;            /*!< [15..8] Counter/Timer 6 Clock Select.                                     */
24770       __IOM uint32_t TMR6TMODE  : 2;            /*!< [17..16] Counter/Timer 6 Trigger Mode                                     */
24771             uint32_t            : 6;
24772       __IOM uint32_t TMR6LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
24773                                                      6. For Single/Repeat Patterns, it indicates number of bits
24774                                                      to be shifted out and so, max value is 63.                                */
24775     } CTRL6_b;
24776   } ;
24777 
24778   union {
24779     __IOM uint32_t TIMER6;                      /*!< (@ 0x000002C4) This register holds the running time or event
24780                                                                     count for timer 6.                                         */
24781 
24782     struct {
24783       __IOM uint32_t TIMER6     : 32;           /*!< [31..0] Counter/Timer 6                                                   */
24784     } TIMER6_b;
24785   } ;
24786 
24787   union {
24788     __IOM uint32_t TMR6CMP0;                    /*!< (@ 0x000002C8) This contains the Compare limits for timer 6.
24789                                                                     This is the primary comparator that can
24790                                                                     be used to mark the END of a timer cycle
24791                                                                     (and thus restart the timer for repeat modes)              */
24792 
24793     struct {
24794       __IOM uint32_t TMR6CMP0   : 32;           /*!< [31..0] Counter/Timer 6 End Compare Register. For MEASURE mode
24795                                                      indicates the high phase sample count.                                    */
24796     } TMR6CMP0_b;
24797   } ;
24798 
24799   union {
24800     __IOM uint32_t TMR6CMP1;                    /*!< (@ 0x000002CC) This comparator is used as a secondary compare
24801                                                                     count for modes that generate pulses. For
24802                                                                     MEASURE mode indicates the low phase sample
24803                                                                     count.                                                     */
24804 
24805     struct {
24806       __IOM uint32_t TMR6CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24807                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24808                                                      be used first.                                                            */
24809     } TMR6CMP1_b;
24810   } ;
24811 
24812   union {
24813     __IOM uint32_t MODE6;                       /*!< (@ 0x000002D0) The mode register contains optional mode controls
24814                                                                     for the timer                                              */
24815 
24816     struct {
24817             uint32_t            : 8;
24818       __IOM uint32_t TMR6TRIGSEL : 8;           /*!< [15..8] Counter/Timer 6 Trigger Source Selection                          */
24819             uint32_t            : 16;
24820     } MODE6_b;
24821   } ;
24822 
24823   union {
24824     __IOM uint32_t TMR6LMTVAL;                  /*!< (@ 0x000002D4) This is an internal counter in the hardware that
24825                                                                     counts down from TMR_LMT to 1                              */
24826 
24827     struct {
24828       __IOM uint32_t TMR6LMTVAL : 8;            /*!< [7..0] Counter/Timer 6 Limit Readback                                     */
24829             uint32_t            : 24;
24830     } TMR6LMTVAL_b;
24831   } ;
24832   __IM  uint32_t  RESERVED10[2];
24833 
24834   union {
24835     __IOM uint32_t CTRL7;                       /*!< (@ 0x000002E0) This includes the Control bit fields for timer
24836                                                                     7.                                                         */
24837 
24838     struct {
24839       __IOM uint32_t TMR7EN     : 1;            /*!< [0..0] Counter/Timer 7 Enable bit.                                        */
24840       __IOM uint32_t TMR7CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24841       __IOM uint32_t TMR7POL0   : 1;            /*!< [2..2] Counter/Timer 7 output 0 polarity.                                 */
24842       __IOM uint32_t TMR7POL1   : 1;            /*!< [3..3] Counter/Timer 7 output 1 polarity.                                 */
24843       __IOM uint32_t TMR7FN     : 4;            /*!< [7..4] Counter/Timer 7 Function Select. For all Functions, CMP0
24844                                                      marks the end of timer cycle, and thus restarts the timer.                */
24845       __IOM uint32_t TMR7CLK    : 8;            /*!< [15..8] Counter/Timer 7 Clock Select.                                     */
24846       __IOM uint32_t TMR7TMODE  : 2;            /*!< [17..16] Counter/Timer 7 Trigger Mode                                     */
24847             uint32_t            : 6;
24848       __IOM uint32_t TMR7LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
24849                                                      7. For Single/Repeat Patterns, it indicates number of bits
24850                                                      to be shifted out and so, max value is 63.                                */
24851     } CTRL7_b;
24852   } ;
24853 
24854   union {
24855     __IOM uint32_t TIMER7;                      /*!< (@ 0x000002E4) This register holds the running time or event
24856                                                                     count for timer 7.                                         */
24857 
24858     struct {
24859       __IOM uint32_t TIMER7     : 32;           /*!< [31..0] Counter/Timer 7                                                   */
24860     } TIMER7_b;
24861   } ;
24862 
24863   union {
24864     __IOM uint32_t TMR7CMP0;                    /*!< (@ 0x000002E8) This contains the Compare limits for timer 7.
24865                                                                     This is the primary comparator that can
24866                                                                     be used to mark the END of a timer cycle
24867                                                                     (and thus restart the timer for repeat modes)              */
24868 
24869     struct {
24870       __IOM uint32_t TMR7CMP0   : 32;           /*!< [31..0] Counter/Timer 7 End Compare Register. For MEASURE mode
24871                                                      indicates the high phase sample count.                                    */
24872     } TMR7CMP0_b;
24873   } ;
24874 
24875   union {
24876     __IOM uint32_t TMR7CMP1;                    /*!< (@ 0x000002EC) This comparator is used as a secondary compare
24877                                                                     count for modes that generate pulses. For
24878                                                                     MEASURE mode indicates the low phase sample
24879                                                                     count.                                                     */
24880 
24881     struct {
24882       __IOM uint32_t TMR7CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24883                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24884                                                      be used first.                                                            */
24885     } TMR7CMP1_b;
24886   } ;
24887 
24888   union {
24889     __IOM uint32_t MODE7;                       /*!< (@ 0x000002F0) The mode register contains optional mode controls
24890                                                                     for the timer                                              */
24891 
24892     struct {
24893             uint32_t            : 8;
24894       __IOM uint32_t TMR7TRIGSEL : 8;           /*!< [15..8] Counter/Timer 7 Trigger Source Selection                          */
24895             uint32_t            : 16;
24896     } MODE7_b;
24897   } ;
24898 
24899   union {
24900     __IOM uint32_t TMR7LMTVAL;                  /*!< (@ 0x000002F4) This is an internal counter in the hardware that
24901                                                                     counts down from TMR_LMT to 1                              */
24902 
24903     struct {
24904       __IOM uint32_t TMR7LMTVAL : 8;            /*!< [7..0] Counter/Timer 7 Limit Readback                                     */
24905             uint32_t            : 24;
24906     } TMR7LMTVAL_b;
24907   } ;
24908   __IM  uint32_t  RESERVED11[2];
24909 
24910   union {
24911     __IOM uint32_t CTRL8;                       /*!< (@ 0x00000300) This includes the Control bit fields for timer
24912                                                                     8.                                                         */
24913 
24914     struct {
24915       __IOM uint32_t TMR8EN     : 1;            /*!< [0..0] Counter/Timer 8 Enable bit.                                        */
24916       __IOM uint32_t TMR8CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24917       __IOM uint32_t TMR8POL0   : 1;            /*!< [2..2] Counter/Timer 8 output 0 polarity.                                 */
24918       __IOM uint32_t TMR8POL1   : 1;            /*!< [3..3] Counter/Timer 8 output 1 polarity.                                 */
24919       __IOM uint32_t TMR8FN     : 4;            /*!< [7..4] Counter/Timer 8 Function Select. For all Functions, CMP0
24920                                                      marks the end of timer cycle, and thus restarts the timer.                */
24921       __IOM uint32_t TMR8CLK    : 8;            /*!< [15..8] Counter/Timer 8 Clock Select.                                     */
24922       __IOM uint32_t TMR8TMODE  : 2;            /*!< [17..16] Counter/Timer 8 Trigger Mode                                     */
24923             uint32_t            : 6;
24924       __IOM uint32_t TMR8LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
24925                                                      8. For Single/Repeat Patterns, it indicates number of bits
24926                                                      to be shifted out and so, max value is 63.                                */
24927     } CTRL8_b;
24928   } ;
24929 
24930   union {
24931     __IOM uint32_t TIMER8;                      /*!< (@ 0x00000304) This register holds the running time or event
24932                                                                     count for timer 8.                                         */
24933 
24934     struct {
24935       __IOM uint32_t TIMER8     : 32;           /*!< [31..0] Counter/Timer 8                                                   */
24936     } TIMER8_b;
24937   } ;
24938 
24939   union {
24940     __IOM uint32_t TMR8CMP0;                    /*!< (@ 0x00000308) This contains the Compare limits for timer 8.
24941                                                                     This is the primary comparator that can
24942                                                                     be used to mark the END of a timer cycle
24943                                                                     (and thus restart the timer for repeat modes)              */
24944 
24945     struct {
24946       __IOM uint32_t TMR8CMP0   : 32;           /*!< [31..0] Counter/Timer 8 End Compare Register. For MEASURE mode
24947                                                      indicates the high phase sample count.                                    */
24948     } TMR8CMP0_b;
24949   } ;
24950 
24951   union {
24952     __IOM uint32_t TMR8CMP1;                    /*!< (@ 0x0000030C) This comparator is used as a secondary compare
24953                                                                     count for modes that generate pulses. For
24954                                                                     MEASURE mode indicates the low phase sample
24955                                                                     count.                                                     */
24956 
24957     struct {
24958       __IOM uint32_t TMR8CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
24959                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
24960                                                      be used first.                                                            */
24961     } TMR8CMP1_b;
24962   } ;
24963 
24964   union {
24965     __IOM uint32_t MODE8;                       /*!< (@ 0x00000310) The mode register contains optional mode controls
24966                                                                     for the timer                                              */
24967 
24968     struct {
24969             uint32_t            : 8;
24970       __IOM uint32_t TMR8TRIGSEL : 8;           /*!< [15..8] Counter/Timer 8 Trigger Source Selection                          */
24971             uint32_t            : 16;
24972     } MODE8_b;
24973   } ;
24974 
24975   union {
24976     __IOM uint32_t TMR8LMTVAL;                  /*!< (@ 0x00000314) This is an internal counter in the hardware that
24977                                                                     counts down from TMR_LMT to 1                              */
24978 
24979     struct {
24980       __IOM uint32_t TMR8LMTVAL : 8;            /*!< [7..0] Counter/Timer 8 Limit Readback                                     */
24981             uint32_t            : 24;
24982     } TMR8LMTVAL_b;
24983   } ;
24984   __IM  uint32_t  RESERVED12[2];
24985 
24986   union {
24987     __IOM uint32_t CTRL9;                       /*!< (@ 0x00000320) This includes the Control bit fields for timer
24988                                                                     9.                                                         */
24989 
24990     struct {
24991       __IOM uint32_t TMR9EN     : 1;            /*!< [0..0] Counter/Timer 9 Enable bit.                                        */
24992       __IOM uint32_t TMR9CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
24993       __IOM uint32_t TMR9POL0   : 1;            /*!< [2..2] Counter/Timer 9 output 0 polarity.                                 */
24994       __IOM uint32_t TMR9POL1   : 1;            /*!< [3..3] Counter/Timer 9 output 1 polarity.                                 */
24995       __IOM uint32_t TMR9FN     : 4;            /*!< [7..4] Counter/Timer 9 Function Select. For all Functions, CMP0
24996                                                      marks the end of timer cycle, and thus restarts the timer.                */
24997       __IOM uint32_t TMR9CLK    : 8;            /*!< [15..8] Counter/Timer 9 Clock Select.                                     */
24998       __IOM uint32_t TMR9TMODE  : 2;            /*!< [17..16] Counter/Timer 9 Trigger Mode                                     */
24999             uint32_t            : 6;
25000       __IOM uint32_t TMR9LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
25001                                                      9. For Single/Repeat Patterns, it indicates number of bits
25002                                                      to be shifted out and so, max value is 63.                                */
25003     } CTRL9_b;
25004   } ;
25005 
25006   union {
25007     __IOM uint32_t TIMER9;                      /*!< (@ 0x00000324) This register holds the running time or event
25008                                                                     count for timer 9.                                         */
25009 
25010     struct {
25011       __IOM uint32_t TIMER9     : 32;           /*!< [31..0] Counter/Timer 9                                                   */
25012     } TIMER9_b;
25013   } ;
25014 
25015   union {
25016     __IOM uint32_t TMR9CMP0;                    /*!< (@ 0x00000328) This contains the Compare limits for timer 9.
25017                                                                     This is the primary comparator that can
25018                                                                     be used to mark the END of a timer cycle
25019                                                                     (and thus restart the timer for repeat modes)              */
25020 
25021     struct {
25022       __IOM uint32_t TMR9CMP0   : 32;           /*!< [31..0] Counter/Timer 9 End Compare Register. For MEASURE mode
25023                                                      indicates the high phase sample count.                                    */
25024     } TMR9CMP0_b;
25025   } ;
25026 
25027   union {
25028     __IOM uint32_t TMR9CMP1;                    /*!< (@ 0x0000032C) This comparator is used as a secondary compare
25029                                                                     count for modes that generate pulses. For
25030                                                                     MEASURE mode indicates the low phase sample
25031                                                                     count.                                                     */
25032 
25033     struct {
25034       __IOM uint32_t TMR9CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
25035                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
25036                                                      be used first.                                                            */
25037     } TMR9CMP1_b;
25038   } ;
25039 
25040   union {
25041     __IOM uint32_t MODE9;                       /*!< (@ 0x00000330) The mode register contains optional mode controls
25042                                                                     for the timer                                              */
25043 
25044     struct {
25045             uint32_t            : 8;
25046       __IOM uint32_t TMR9TRIGSEL : 8;           /*!< [15..8] Counter/Timer 9 Trigger Source Selection                          */
25047             uint32_t            : 16;
25048     } MODE9_b;
25049   } ;
25050 
25051   union {
25052     __IOM uint32_t TMR9LMTVAL;                  /*!< (@ 0x00000334) This is an internal counter in the hardware that
25053                                                                     counts down from TMR_LMT to 1                              */
25054 
25055     struct {
25056       __IOM uint32_t TMR9LMTVAL : 8;            /*!< [7..0] Counter/Timer 9 Limit Readback                                     */
25057             uint32_t            : 24;
25058     } TMR9LMTVAL_b;
25059   } ;
25060   __IM  uint32_t  RESERVED13[2];
25061 
25062   union {
25063     __IOM uint32_t CTRL10;                      /*!< (@ 0x00000340) This includes the Control bit fields for timer
25064                                                                     10.                                                        */
25065 
25066     struct {
25067       __IOM uint32_t TMR10EN    : 1;            /*!< [0..0] Counter/Timer 10 Enable bit.                                       */
25068       __IOM uint32_t TMR10CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
25069       __IOM uint32_t TMR10POL0  : 1;            /*!< [2..2] Counter/Timer 10 output 0 polarity.                                */
25070       __IOM uint32_t TMR10POL1  : 1;            /*!< [3..3] Counter/Timer 10 output 1 polarity.                                */
25071       __IOM uint32_t TMR10FN    : 4;            /*!< [7..4] Counter/Timer 10 Function Select. For all Functions,
25072                                                      CMP0 marks the end of timer cycle, and thus restarts the
25073                                                      timer.                                                                    */
25074       __IOM uint32_t TMR10CLK   : 8;            /*!< [15..8] Counter/Timer 10 Clock Select.                                    */
25075       __IOM uint32_t TMR10TMODE : 2;            /*!< [17..16] Counter/Timer 10 Trigger Mode                                    */
25076             uint32_t            : 6;
25077       __IOM uint32_t TMR10LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
25078                                                      10. For Single/Repeat Patterns, it indicates number of
25079                                                      bits to be shifted out and so, max value is 63.                           */
25080     } CTRL10_b;
25081   } ;
25082 
25083   union {
25084     __IOM uint32_t TIMER10;                     /*!< (@ 0x00000344) This register holds the running time or event
25085                                                                     count for timer 10.                                        */
25086 
25087     struct {
25088       __IOM uint32_t TIMER10    : 32;           /*!< [31..0] Counter/Timer 10                                                  */
25089     } TIMER10_b;
25090   } ;
25091 
25092   union {
25093     __IOM uint32_t TMR10CMP0;                   /*!< (@ 0x00000348) This contains the Compare limits for timer 10.
25094                                                                     This is the primary comparator that can
25095                                                                     be used to mark the END of a timer cycle
25096                                                                     (and thus restart the timer for repeat modes)              */
25097 
25098     struct {
25099       __IOM uint32_t TMR10CMP0  : 32;           /*!< [31..0] Counter/Timer 10 End Compare Register. For MEASURE mode
25100                                                      indicates the high phase sample count.                                    */
25101     } TMR10CMP0_b;
25102   } ;
25103 
25104   union {
25105     __IOM uint32_t TMR10CMP1;                   /*!< (@ 0x0000034C) This comparator is used as a secondary compare
25106                                                                     count for modes that generate pulses. For
25107                                                                     MEASURE mode indicates the low phase sample
25108                                                                     count.                                                     */
25109 
25110     struct {
25111       __IOM uint32_t TMR10CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
25112                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
25113                                                      be used first.                                                            */
25114     } TMR10CMP1_b;
25115   } ;
25116 
25117   union {
25118     __IOM uint32_t MODE10;                      /*!< (@ 0x00000350) The mode register contains optional mode controls
25119                                                                     for the timer                                              */
25120 
25121     struct {
25122             uint32_t            : 8;
25123       __IOM uint32_t TMR10TRIGSEL : 8;          /*!< [15..8] Counter/Timer 10 Trigger Source Selection                         */
25124             uint32_t            : 16;
25125     } MODE10_b;
25126   } ;
25127 
25128   union {
25129     __IOM uint32_t TMR10LMTVAL;                 /*!< (@ 0x00000354) This is an internal counter in the hardware that
25130                                                                     counts down from TMR_LMT to 1                              */
25131 
25132     struct {
25133       __IOM uint32_t TMR10LMTVAL : 8;           /*!< [7..0] Counter/Timer 10 Limit Readback                                    */
25134             uint32_t            : 24;
25135     } TMR10LMTVAL_b;
25136   } ;
25137   __IM  uint32_t  RESERVED14[2];
25138 
25139   union {
25140     __IOM uint32_t CTRL11;                      /*!< (@ 0x00000360) This includes the Control bit fields for timer
25141                                                                     11.                                                        */
25142 
25143     struct {
25144       __IOM uint32_t TMR11EN    : 1;            /*!< [0..0] Counter/Timer 11 Enable bit.                                       */
25145       __IOM uint32_t TMR11CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
25146       __IOM uint32_t TMR11POL0  : 1;            /*!< [2..2] Counter/Timer 11 output 0 polarity.                                */
25147       __IOM uint32_t TMR11POL1  : 1;            /*!< [3..3] Counter/Timer 11 output 1 polarity.                                */
25148       __IOM uint32_t TMR11FN    : 4;            /*!< [7..4] Counter/Timer 11 Function Select. For all Functions,
25149                                                      CMP0 marks the end of timer cycle, and thus restarts the
25150                                                      timer.                                                                    */
25151       __IOM uint32_t TMR11CLK   : 8;            /*!< [15..8] Counter/Timer 11 Clock Select.                                    */
25152       __IOM uint32_t TMR11TMODE : 2;            /*!< [17..16] Counter/Timer 11 Trigger Mode                                    */
25153             uint32_t            : 6;
25154       __IOM uint32_t TMR11LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
25155                                                      11. For Single/Repeat Patterns, it indicates number of
25156                                                      bits to be shifted out and so, max value is 63.                           */
25157     } CTRL11_b;
25158   } ;
25159 
25160   union {
25161     __IOM uint32_t TIMER11;                     /*!< (@ 0x00000364) This register holds the running time or event
25162                                                                     count for timer 11.                                        */
25163 
25164     struct {
25165       __IOM uint32_t TIMER11    : 32;           /*!< [31..0] Counter/Timer 11                                                  */
25166     } TIMER11_b;
25167   } ;
25168 
25169   union {
25170     __IOM uint32_t TMR11CMP0;                   /*!< (@ 0x00000368) This contains the Compare limits for timer 11.
25171                                                                     This is the primary comparator that can
25172                                                                     be used to mark the END of a timer cycle
25173                                                                     (and thus restart the timer for repeat modes)              */
25174 
25175     struct {
25176       __IOM uint32_t TMR11CMP0  : 32;           /*!< [31..0] Counter/Timer 11 End Compare Register. For MEASURE mode
25177                                                      indicates the high phase sample count.                                    */
25178     } TMR11CMP0_b;
25179   } ;
25180 
25181   union {
25182     __IOM uint32_t TMR11CMP1;                   /*!< (@ 0x0000036C) This comparator is used as a secondary compare
25183                                                                     count for modes that generate pulses. For
25184                                                                     MEASURE mode indicates the low phase sample
25185                                                                     count.                                                     */
25186 
25187     struct {
25188       __IOM uint32_t TMR11CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
25189                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
25190                                                      be used first.                                                            */
25191     } TMR11CMP1_b;
25192   } ;
25193 
25194   union {
25195     __IOM uint32_t MODE11;                      /*!< (@ 0x00000370) The mode register contains optional mode controls
25196                                                                     for the timer                                              */
25197 
25198     struct {
25199             uint32_t            : 8;
25200       __IOM uint32_t TMR11TRIGSEL : 8;          /*!< [15..8] Counter/Timer 11 Trigger Source Selection                         */
25201             uint32_t            : 16;
25202     } MODE11_b;
25203   } ;
25204 
25205   union {
25206     __IOM uint32_t TMR11LMTVAL;                 /*!< (@ 0x00000374) This is an internal counter in the hardware that
25207                                                                     counts down from TMR_LMT to 1                              */
25208 
25209     struct {
25210       __IOM uint32_t TMR11LMTVAL : 8;           /*!< [7..0] Counter/Timer 11 Limit Readback                                    */
25211             uint32_t            : 24;
25212     } TMR11LMTVAL_b;
25213   } ;
25214   __IM  uint32_t  RESERVED15[2];
25215 
25216   union {
25217     __IOM uint32_t CTRL12;                      /*!< (@ 0x00000380) This includes the Control bit fields for timer
25218                                                                     12.                                                        */
25219 
25220     struct {
25221       __IOM uint32_t TMR12EN    : 1;            /*!< [0..0] Counter/Timer 12 Enable bit.                                       */
25222       __IOM uint32_t TMR12CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
25223       __IOM uint32_t TMR12POL0  : 1;            /*!< [2..2] Counter/Timer 12 output 0 polarity.                                */
25224       __IOM uint32_t TMR12POL1  : 1;            /*!< [3..3] Counter/Timer 12 output 1 polarity.                                */
25225       __IOM uint32_t TMR12FN    : 4;            /*!< [7..4] Counter/Timer 12 Function Select. For all Functions,
25226                                                      CMP0 marks the end of timer cycle, and thus restarts the
25227                                                      timer.                                                                    */
25228       __IOM uint32_t TMR12CLK   : 8;            /*!< [15..8] Counter/Timer 12 Clock Select.                                    */
25229       __IOM uint32_t TMR12TMODE : 2;            /*!< [17..16] Counter/Timer 12 Trigger Mode                                    */
25230             uint32_t            : 6;
25231       __IOM uint32_t TMR12LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
25232                                                      12. For Single/Repeat Patterns, it indicates number of
25233                                                      bits to be shifted out and so, max value is 63.                           */
25234     } CTRL12_b;
25235   } ;
25236 
25237   union {
25238     __IOM uint32_t TIMER12;                     /*!< (@ 0x00000384) This register holds the running time or event
25239                                                                     count for timer 12.                                        */
25240 
25241     struct {
25242       __IOM uint32_t TIMER12    : 32;           /*!< [31..0] Counter/Timer 12                                                  */
25243     } TIMER12_b;
25244   } ;
25245 
25246   union {
25247     __IOM uint32_t TMR12CMP0;                   /*!< (@ 0x00000388) This contains the Compare limits for timer 12.
25248                                                                     This is the primary comparator that can
25249                                                                     be used to mark the END of a timer cycle
25250                                                                     (and thus restart the timer for repeat modes)              */
25251 
25252     struct {
25253       __IOM uint32_t TMR12CMP0  : 32;           /*!< [31..0] Counter/Timer 12 End Compare Register. For MEASURE mode
25254                                                      indicates the high phase sample count.                                    */
25255     } TMR12CMP0_b;
25256   } ;
25257 
25258   union {
25259     __IOM uint32_t TMR12CMP1;                   /*!< (@ 0x0000038C) This comparator is used as a secondary compare
25260                                                                     count for modes that generate pulses. For
25261                                                                     MEASURE mode indicates the low phase sample
25262                                                                     count.                                                     */
25263 
25264     struct {
25265       __IOM uint32_t TMR12CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
25266                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
25267                                                      be used first.                                                            */
25268     } TMR12CMP1_b;
25269   } ;
25270 
25271   union {
25272     __IOM uint32_t MODE12;                      /*!< (@ 0x00000390) The mode register contains optional mode controls
25273                                                                     for the timer                                              */
25274 
25275     struct {
25276             uint32_t            : 8;
25277       __IOM uint32_t TMR12TRIGSEL : 8;          /*!< [15..8] Counter/Timer 12 Trigger Source Selection                         */
25278             uint32_t            : 16;
25279     } MODE12_b;
25280   } ;
25281 
25282   union {
25283     __IOM uint32_t TMR12LMTVAL;                 /*!< (@ 0x00000394) This is an internal counter in the hardware that
25284                                                                     counts down from TMR_LMT to 1                              */
25285 
25286     struct {
25287       __IOM uint32_t TMR12LMTVAL : 8;           /*!< [7..0] Counter/Timer 12 Limit Readback                                    */
25288             uint32_t            : 24;
25289     } TMR12LMTVAL_b;
25290   } ;
25291   __IM  uint32_t  RESERVED16[2];
25292 
25293   union {
25294     __IOM uint32_t CTRL13;                      /*!< (@ 0x000003A0) This includes the Control bit fields for timer
25295                                                                     13.                                                        */
25296 
25297     struct {
25298       __IOM uint32_t TMR13EN    : 1;            /*!< [0..0] Counter/Timer 13 Enable bit.                                       */
25299       __IOM uint32_t TMR13CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
25300       __IOM uint32_t TMR13POL0  : 1;            /*!< [2..2] Counter/Timer 13 output 0 polarity.                                */
25301       __IOM uint32_t TMR13POL1  : 1;            /*!< [3..3] Counter/Timer 13 output 1 polarity.                                */
25302       __IOM uint32_t TMR13FN    : 4;            /*!< [7..4] Counter/Timer 13 Function Select. For all Functions,
25303                                                      CMP0 marks the end of timer cycle, and thus restarts the
25304                                                      timer.                                                                    */
25305       __IOM uint32_t TMR13CLK   : 8;            /*!< [15..8] Counter/Timer 13 Clock Select.                                    */
25306       __IOM uint32_t TMR13TMODE : 2;            /*!< [17..16] Counter/Timer 13 Trigger Mode                                    */
25307             uint32_t            : 6;
25308       __IOM uint32_t TMR13LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
25309                                                      13. For Single/Repeat Patterns, it indicates number of
25310                                                      bits to be shifted out and so, max value is 63.                           */
25311     } CTRL13_b;
25312   } ;
25313 
25314   union {
25315     __IOM uint32_t TIMER13;                     /*!< (@ 0x000003A4) This register holds the running time or event
25316                                                                     count for timer 13.                                        */
25317 
25318     struct {
25319       __IOM uint32_t TIMER13    : 32;           /*!< [31..0] Counter/Timer 13                                                  */
25320     } TIMER13_b;
25321   } ;
25322 
25323   union {
25324     __IOM uint32_t TMR13CMP0;                   /*!< (@ 0x000003A8) This contains the Compare limits for timer 13.
25325                                                                     This is the primary comparator that can
25326                                                                     be used to mark the END of a timer cycle
25327                                                                     (and thus restart the timer for repeat modes)              */
25328 
25329     struct {
25330       __IOM uint32_t TMR13CMP0  : 32;           /*!< [31..0] Counter/Timer 13 End Compare Register. For MEASURE mode
25331                                                      indicates the high phase sample count.                                    */
25332     } TMR13CMP0_b;
25333   } ;
25334 
25335   union {
25336     __IOM uint32_t TMR13CMP1;                   /*!< (@ 0x000003AC) This comparator is used as a secondary compare
25337                                                                     count for modes that generate pulses. For
25338                                                                     MEASURE mode indicates the low phase sample
25339                                                                     count.                                                     */
25340 
25341     struct {
25342       __IOM uint32_t TMR13CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
25343                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
25344                                                      be used first.                                                            */
25345     } TMR13CMP1_b;
25346   } ;
25347 
25348   union {
25349     __IOM uint32_t MODE13;                      /*!< (@ 0x000003B0) The mode register contains optional mode controls
25350                                                                     for the timer                                              */
25351 
25352     struct {
25353             uint32_t            : 8;
25354       __IOM uint32_t TMR13TRIGSEL : 8;          /*!< [15..8] Counter/Timer 13 Trigger Source Selection                         */
25355             uint32_t            : 16;
25356     } MODE13_b;
25357   } ;
25358 
25359   union {
25360     __IOM uint32_t TMR13LMTVAL;                 /*!< (@ 0x000003B4) This is an internal counter in the hardware that
25361                                                                     counts down from TMR_LMT to 1                              */
25362 
25363     struct {
25364       __IOM uint32_t TMR13LMTVAL : 8;           /*!< [7..0] Counter/Timer 13 Limit Readback                                    */
25365             uint32_t            : 24;
25366     } TMR13LMTVAL_b;
25367   } ;
25368   __IM  uint32_t  RESERVED17[2];
25369 
25370   union {
25371     __IOM uint32_t CTRL14;                      /*!< (@ 0x000003C0) This includes the Control bit fields for timer
25372                                                                     14.                                                        */
25373 
25374     struct {
25375       __IOM uint32_t TMR14EN    : 1;            /*!< [0..0] Counter/Timer 14 Enable bit.                                       */
25376       __IOM uint32_t TMR14CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
25377       __IOM uint32_t TMR14POL0  : 1;            /*!< [2..2] Counter/Timer 14 output 0 polarity.                                */
25378       __IOM uint32_t TMR14POL1  : 1;            /*!< [3..3] Counter/Timer 14 output 1 polarity.                                */
25379       __IOM uint32_t TMR14FN    : 4;            /*!< [7..4] Counter/Timer 14 Function Select. For all Functions,
25380                                                      CMP0 marks the end of timer cycle, and thus restarts the
25381                                                      timer.                                                                    */
25382       __IOM uint32_t TMR14CLK   : 8;            /*!< [15..8] Counter/Timer 14 Clock Select.                                    */
25383       __IOM uint32_t TMR14TMODE : 2;            /*!< [17..16] Counter/Timer 14 Trigger Mode                                    */
25384             uint32_t            : 6;
25385       __IOM uint32_t TMR14LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
25386                                                      14. For Single/Repeat Patterns, it indicates number of
25387                                                      bits to be shifted out and so, max value is 63.                           */
25388     } CTRL14_b;
25389   } ;
25390 
25391   union {
25392     __IOM uint32_t TIMER14;                     /*!< (@ 0x000003C4) This register holds the running time or event
25393                                                                     count for timer 14.                                        */
25394 
25395     struct {
25396       __IOM uint32_t TIMER14    : 32;           /*!< [31..0] Counter/Timer 14                                                  */
25397     } TIMER14_b;
25398   } ;
25399 
25400   union {
25401     __IOM uint32_t TMR14CMP0;                   /*!< (@ 0x000003C8) This contains the Compare limits for timer 14.
25402                                                                     This is the primary comparator that can
25403                                                                     be used to mark the END of a timer cycle
25404                                                                     (and thus restart the timer for repeat modes)              */
25405 
25406     struct {
25407       __IOM uint32_t TMR14CMP0  : 32;           /*!< [31..0] Counter/Timer 14 End Compare Register. For MEASURE mode
25408                                                      indicates the high phase sample count.                                    */
25409     } TMR14CMP0_b;
25410   } ;
25411 
25412   union {
25413     __IOM uint32_t TMR14CMP1;                   /*!< (@ 0x000003CC) This comparator is used as a secondary compare
25414                                                                     count for modes that generate pulses. For
25415                                                                     MEASURE mode indicates the low phase sample
25416                                                                     count.                                                     */
25417 
25418     struct {
25419       __IOM uint32_t TMR14CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
25420                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
25421                                                      be used first.                                                            */
25422     } TMR14CMP1_b;
25423   } ;
25424 
25425   union {
25426     __IOM uint32_t MODE14;                      /*!< (@ 0x000003D0) The mode register contains optional mode controls
25427                                                                     for the timer                                              */
25428 
25429     struct {
25430             uint32_t            : 8;
25431       __IOM uint32_t TMR14TRIGSEL : 8;          /*!< [15..8] Counter/Timer 14 Trigger Source Selection                         */
25432             uint32_t            : 16;
25433     } MODE14_b;
25434   } ;
25435 
25436   union {
25437     __IOM uint32_t TMR14LMTVAL;                 /*!< (@ 0x000003D4) This is an internal counter in the hardware that
25438                                                                     counts down from TMR_LMT to 1                              */
25439 
25440     struct {
25441       __IOM uint32_t TMR14LMTVAL : 8;           /*!< [7..0] Counter/Timer 14 Limit Readback                                    */
25442             uint32_t            : 24;
25443     } TMR14LMTVAL_b;
25444   } ;
25445   __IM  uint32_t  RESERVED18[2];
25446 
25447   union {
25448     __IOM uint32_t CTRL15;                      /*!< (@ 0x000003E0) This includes the Control bit fields for timer
25449                                                                     15.                                                        */
25450 
25451     struct {
25452       __IOM uint32_t TMR15EN    : 1;            /*!< [0..0] Counter/Timer 15 Enable bit.                                       */
25453       __IOM uint32_t TMR15CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
25454       __IOM uint32_t TMR15POL0  : 1;            /*!< [2..2] Counter/Timer 15 output 0 polarity.                                */
25455       __IOM uint32_t TMR15POL1  : 1;            /*!< [3..3] Counter/Timer 15 output 1 polarity.                                */
25456       __IOM uint32_t TMR15FN    : 4;            /*!< [7..4] Counter/Timer 15 Function Select. For all Functions,
25457                                                      CMP0 marks the end of timer cycle, and thus restarts the
25458                                                      timer.                                                                    */
25459       __IOM uint32_t TMR15CLK   : 8;            /*!< [15..8] Counter/Timer 15 Clock Select.                                    */
25460       __IOM uint32_t TMR15TMODE : 2;            /*!< [17..16] Counter/Timer 15 Trigger Mode                                    */
25461             uint32_t            : 6;
25462       __IOM uint32_t TMR15LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
25463                                                      15. For Single/Repeat Patterns, it indicates number of
25464                                                      bits to be shifted out and so, max value is 63.                           */
25465     } CTRL15_b;
25466   } ;
25467 
25468   union {
25469     __IOM uint32_t TIMER15;                     /*!< (@ 0x000003E4) This register holds the running time or event
25470                                                                     count for timer 15.                                        */
25471 
25472     struct {
25473       __IOM uint32_t TIMER15    : 32;           /*!< [31..0] Counter/Timer 15                                                  */
25474     } TIMER15_b;
25475   } ;
25476 
25477   union {
25478     __IOM uint32_t TMR15CMP0;                   /*!< (@ 0x000003E8) This contains the Compare limits for timer 15.
25479                                                                     This is the primary comparator that can
25480                                                                     be used to mark the END of a timer cycle
25481                                                                     (and thus restart the timer for repeat modes)              */
25482 
25483     struct {
25484       __IOM uint32_t TMR15CMP0  : 32;           /*!< [31..0] Counter/Timer 15 End Compare Register. For MEASURE mode
25485                                                      indicates the high phase sample count.                                    */
25486     } TMR15CMP0_b;
25487   } ;
25488 
25489   union {
25490     __IOM uint32_t TMR15CMP1;                   /*!< (@ 0x000003EC) This comparator is used as a secondary compare
25491                                                                     count for modes that generate pulses. For
25492                                                                     MEASURE mode indicates the low phase sample
25493                                                                     count.                                                     */
25494 
25495     struct {
25496       __IOM uint32_t TMR15CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
25497                                                      a PWM or generate secondary pulses. CMP0 should ALWAYS
25498                                                      be used first.                                                            */
25499     } TMR15CMP1_b;
25500   } ;
25501 
25502   union {
25503     __IOM uint32_t MODE15;                      /*!< (@ 0x000003F0) The mode register contains optional mode controls
25504                                                                     for the timer                                              */
25505 
25506     struct {
25507             uint32_t            : 8;
25508       __IOM uint32_t TMR15TRIGSEL : 8;          /*!< [15..8] Counter/Timer 15 Trigger Source Selection                         */
25509             uint32_t            : 16;
25510     } MODE15_b;
25511   } ;
25512 
25513   union {
25514     __IOM uint32_t TMR15LMTVAL;                 /*!< (@ 0x000003F4) This is an internal counter in the hardware that
25515                                                                     counts down from TMR_LMT to 1                              */
25516 
25517     struct {
25518       __IOM uint32_t TMR15LMTVAL : 8;           /*!< [7..0] Counter/Timer 15 Limit Readback                                    */
25519             uint32_t            : 24;
25520     } TMR15LMTVAL_b;
25521   } ;
25522 
25523   union {
25524     __IOM uint32_t TIMERSPARES;                 /*!< (@ 0x000003F8) Timer Spare Regs                                           */
25525 
25526     struct {
25527       __IOM uint32_t TMRSPARES  : 32;           /*!< [31..0] Placeholer spare registes that can be used as needed
25528                                                      for future use                                                            */
25529     } TIMERSPARES_b;
25530   } ;
25531 } TIMER_Type;                                   /*!< Size = 1020 (0x3fc)                                                       */
25532 
25533 
25534 
25535 /* =========================================================================================================================== */
25536 /* ================                                           UART0                                           ================ */
25537 /* =========================================================================================================================== */
25538 
25539 
25540 /**
25541   * @brief Serial UART (UART0)
25542   */
25543 
25544 typedef struct {                                /*!< (@ 0x4001C000) UART0 Structure                                            */
25545 
25546   union {
25547     __IOM uint32_t DR;                          /*!< (@ 0x00000000) UART Data                                                  */
25548 
25549     struct {
25550       __IOM uint32_t DATA       : 8;            /*!< [7..0] Receive (read) data character. Transmit (write) data
25551                                                      character.                                                                */
25552       __IOM uint32_t FEDATA     : 1;            /*!< [8..8] Framing error. When set to 1, it indicates that the received
25553                                                      character did not have a valid stop bit (a valid stop bit
25554                                                      is 1). In FIFO mode, this error is associated with the
25555                                                      character at the top of the FIFO.                                         */
25556       __IOM uint32_t PEDATA     : 1;            /*!< [9..9] Parity error. When set to 1, it indicates that the parity
25557                                                      of the received data character does not match the parity
25558                                                      that the EPS and SPS bits in the Line Control Register,
25559                                                      UARTLCRH select. In FIFO mode, this error is associated
25560                                                      with the character at the top of the FIFO.                                */
25561       __IOM uint32_t BEDATA     : 1;            /*!< [10..10] Break error. This bit is set to 1 if a break condition
25562                                                      was detected, indicating that the received data input was
25563                                                      held LOW for longer than a full-word transmission time
25564                                                      (defined as start, data, parity and stop bits). In FIFO
25565                                                      mode, this error is associated with the character at the
25566                                                      top of the FIFO. When a break occurs, only one 0 character
25567                                                      is loaded into the FIFO. The next character is only enabled
25568                                                      after the receive data input goes to a 1 (marking state),
25569                                                      and the next valid start bit is received.                                 */
25570       __IOM uint32_t OEDATA     : 1;            /*!< [11..11] Overrun error. This bit is set to 1 if data is received
25571                                                      and the receive FIFO is already full. This is cleared to
25572                                                      0 once there is an empty space in the FIFO and a new character
25573                                                      can be written to it.                                                     */
25574             uint32_t            : 20;
25575     } DR_b;
25576   } ;
25577 
25578   union {
25579     __IOM uint32_t RSR;                         /*!< (@ 0x00000004) UART Status                                                */
25580 
25581     struct {
25582       __IOM uint32_t FESTAT     : 1;            /*!< [0..0] Framing error. When set to 1, it indicates that the received
25583                                                      character did not have a valid stop bit (a valid stop bit
25584                                                      is 1). This bit is cleared to 0 by a write to UARTECR.
25585                                                      In FIFO mode, this error is associated with the character
25586                                                      at the top of the FIFO.                                                   */
25587       __IOM uint32_t PESTAT     : 1;            /*!< [1..1] Parity error. When set to 1, it indicates that the parity
25588                                                      of the received data character does not match the parity
25589                                                      that the EPS and SPS bits in the Line Control Register,
25590                                                      UARTLCRH select. This bit is cleared to 0 by a write to
25591                                                      UARTECR. In FIFO mode, this error is associated with the
25592                                                      character at the top of the FIFO.                                         */
25593       __IOM uint32_t BESTAT     : 1;            /*!< [2..2] Break error. This bit is set to 1 if a break condition
25594                                                      was detected, indicating that the received data input was
25595                                                      held LOW for longer than a full-word transmission time
25596                                                      (defined as start, data, parity, and stop bits). This bit
25597                                                      is cleared to 0 after a write to UARTECR. In FIFO mode,
25598                                                      this error is associated with the character at the top
25599                                                      of the FIFO. When a break occurs, only one 0 character
25600                                                      is loaded into the FIFO. The next character is only enabled
25601                                                      after the receive data input goes to a 1 (marking state)
25602                                                      an                                                                        */
25603       __IOM uint32_t OESTAT     : 1;            /*!< [3..3] Overrun error. This bit is set to 1 if data is received
25604                                                      and the FIFO is already full. This bit is cleared to 0
25605                                                      by a write to UARTECR. The FIFO contents remain valid because
25606                                                      no more data is written when the FIFO is full, only the
25607                                                      contents of the shift register are overwritten. The CPU
25608                                                      must now read the data, to empty the FIFO.                                */
25609             uint32_t            : 28;
25610     } RSR_b;
25611   } ;
25612   __IM  uint32_t  RESERVED[4];
25613 
25614   union {
25615     __IOM uint32_t FR;                          /*!< (@ 0x00000018) Flags                                                      */
25616 
25617     struct {
25618       __IOM uint32_t CTS        : 1;            /*!< [0..0] Clear to send. This bit is the complement of the UART
25619                                                      clear to send, nUARTCTS, modem status input. That is, the
25620                                                      bit is 1 when nUARTCTS is LOW.                                            */
25621       __IOM uint32_t DSR        : 1;            /*!< [1..1] Data set ready. This bit is the complement of the UART
25622                                                      data set ready, nUARTDSR, modem status input. That is,
25623                                                      the bit is 1 when nUARTDSR is LOW.                                        */
25624       __IOM uint32_t DCD        : 1;            /*!< [2..2] Data carrier detect. This bit is the complement of the
25625                                                      UART data carrier detect, nUARTDCD, modem status input.
25626                                                      That is, the bit is 1 when nUARTDCD is LOW.                               */
25627       __IOM uint32_t BUSY       : 1;            /*!< [3..3] UART busy. If this bit is set to 1, the UART is busy
25628                                                      transmitting data. This bit remains set until the complete
25629                                                      byte, including all the stop bits, has been sent from the
25630                                                      shift register. This bit is set as soon as the transmit
25631                                                      FIFO becomes non-empty, regardless of whether the UART
25632                                                      is enabled or not.                                                        */
25633       __IOM uint32_t RXFE       : 1;            /*!< [4..4] Receive FIFO empty. The meaning of this bit depends on
25634                                                      the state of the FEN bit in the UARTLCRH Register. If the
25635                                                      FIFO is disabled, this bit is set when the receive holding
25636                                                      register is empty. If the FIFO is enabled, the RXFE bit
25637                                                      is set when the receive FIFO is empty.                                    */
25638       __IOM uint32_t TXFF       : 1;            /*!< [5..5] Transmit FIFO full. The meaning of this bit depends on
25639                                                      the state of the FEN bit in the UARTLCRH Register. If the
25640                                                      FIFO is disabled, this bit is set when the transmit holding
25641                                                      register is full. If the FIFO is enabled, the TXFF bit
25642                                                      is set when the transmit FIFO is full.                                    */
25643       __IOM uint32_t RXFF       : 1;            /*!< [6..6] Receive FIFO full. The meaning of this bit depends on
25644                                                      the state of the FEN bit in the UARTLCRH Register. If the
25645                                                      FIFO is disabled, this bit is set when the receive holding
25646                                                      register is full. If the FIFO is enabled, the RXFF bit
25647                                                      is set when the receive FIFO is full.                                     */
25648       __IOM uint32_t TXFE       : 1;            /*!< [7..7] Transmit FIFO empty. The meaning of this bit depends
25649                                                      on the state of the FEN bit in the Line Control Register,
25650                                                      UARTLCRH. If the FIFO is disabled, this bit is set when
25651                                                      the transmit holding register is empty. If the FIFO is
25652                                                      enabled, the TXFE bit is set when the transmit FIFO is
25653                                                      empty. This bit does not indicate if there is data in the
25654                                                      transmit shift register.                                                  */
25655       __IOM uint32_t TXBUSY     : 1;            /*!< [8..8] This bit holds the transmit BUSY indicator.                        */
25656             uint32_t            : 23;
25657     } FR_b;
25658   } ;
25659   __IM  uint32_t  RESERVED1;
25660 
25661   union {
25662     __IOM uint32_t ILPR;                        /*!< (@ 0x00000020) IrDA Counter                                               */
25663 
25664     struct {
25665       __IOM uint32_t ILPDVSR    : 8;            /*!< [7..0] 8-bit low-power divisor value. These bits are cleared
25666                                                      to 0 at reset. Programming a zero value results in no IrLPBaud16
25667                                                      pulses being generated.                                                   */
25668             uint32_t            : 24;
25669     } ILPR_b;
25670   } ;
25671 
25672   union {
25673     __IOM uint32_t IBRD;                        /*!< (@ 0x00000024) Integer Baud Rate Divisor                                  */
25674 
25675     struct {
25676       __IOM uint32_t DIVINT     : 16;           /*!< [15..0] These bits hold the baud integer divisor. These bits
25677                                                      are cleared to 0 on reset.                                                */
25678             uint32_t            : 16;
25679     } IBRD_b;
25680   } ;
25681 
25682   union {
25683     __IOM uint32_t FBRD;                        /*!< (@ 0x00000028) Fractional Baud Rate Divisor                               */
25684 
25685     struct {
25686       __IOM uint32_t DIVFRAC    : 6;            /*!< [5..0] These bits hold the baud fractional divisor. These bits
25687                                                      are cleared to 0 on reset.                                                */
25688             uint32_t            : 26;
25689     } FBRD_b;
25690   } ;
25691 
25692   union {
25693     __IOM uint32_t LCRH;                        /*!< (@ 0x0000002C) Line Control High                                          */
25694 
25695     struct {
25696       __IOM uint32_t BRK        : 1;            /*!< [0..0] This bit holds the break set. If this bit is set to 1,
25697                                                      a low-level is continually output on the UARTTXD output,
25698                                                      after completing transmission of the current character.
25699                                                      For the proper execution of the break command, the software
25700                                                      must set this bit for at least two complete frames. For
25701                                                      normal use, this bit must be cleared to 0.                                */
25702       __IOM uint32_t PEN        : 1;            /*!< [1..1] This bit holds the parity enable. 0 = parity is disabled
25703                                                      and no parity bit added to the data frame. 1 = parity checking
25704                                                      and generation is enabled.                                                */
25705       __IOM uint32_t EPS        : 1;            /*!< [2..2] This bit holds the even parity select. Controls the type
25706                                                      of parity the UART uses during transmission and reception:
25707                                                      0 = odd parity. The UART generates or checks for an odd
25708                                                      number of 1s in the data and parity bits. 1 = even parity.
25709                                                      The UART generates or checks for an even number of 1s in
25710                                                      the data and parity bits. This bit has no effect when the
25711                                                      PEN bit disables parity checking and generation.                          */
25712       __IOM uint32_t STP2       : 1;            /*!< [3..3] This bit holds the two stop bits select. If this bit
25713                                                      is set to 1, two stop bits are transmitted at the end of
25714                                                      the frame. The receive logic does not check for two stop
25715                                                      bits being received.                                                      */
25716       __IOM uint32_t FEN        : 1;            /*!< [4..4] This bit holds the FIFO enable. 0 = FIFOs are disabled
25717                                                      (character mode) that is, the FIFOs become 1-byte-deep
25718                                                      holding registers. 1 = transmit and receive FIFO buffers
25719                                                      are enabled (FIFO mode).                                                  */
25720       __IOM uint32_t WLEN       : 2;            /*!< [6..5] These bits hold the write length. These bits indicate
25721                                                      the number of data bits transmitted or received in a frame
25722                                                      as follows: b11 = 8 bits, b10 = 7 bits, b01 = 6 bits, b00
25723                                                      = 5 bits.                                                                 */
25724       __IOM uint32_t SPS        : 1;            /*!< [7..7] This bit holds the stick parity select. If the EPS bit
25725                                                      is 0 then the parity bit is transmitted and checked as
25726                                                      a 1. If the EPS bit is 1 then the parity bit is transmitted
25727                                                      and checked as a 0. This bit has no effect when the PEN
25728                                                      bit disables parity checking and generation.                              */
25729             uint32_t            : 24;
25730     } LCRH_b;
25731   } ;
25732 
25733   union {
25734     __IOM uint32_t CR;                          /*!< (@ 0x00000030) Control                                                    */
25735 
25736     struct {
25737       __IOM uint32_t UARTEN     : 1;            /*!< [0..0] This bit is the UART enable. 0 = UART is disabled. If
25738                                                      the UART is disabled in the middle of transmission or reception,
25739                                                      it completes the current character before stopping. 1 =
25740                                                      the UART is enabled. Data transmission and reception occurs
25741                                                      for either UART signals or SIR signals depending on the
25742                                                      setting of the SIREN bit.                                                 */
25743       __IOM uint32_t SIREN      : 1;            /*!< [1..1] This bit is the SIR ENDEC enable. If this bit is set
25744                                                      to 1, the IrDA SIR ENDEC is enabled. This bit has no effect
25745                                                      if the UART is not enabled by bit 0 being set to 1. When
25746                                                      the IrDA SIR ENDEC is enabled, data is transmitted and
25747                                                      received on nSIROUT and SIRIN. UARTTXD remains in the marking
25748                                                      state (set to 1). Signal transitions on UARTRXD or modem
25749                                                      status inputs have no effect. When the IrDA SIR ENDEC is
25750                                                      disabled, nSIROUT remains cleared to 0 (no light pulse
25751                                                      generated), and signal transitions on SIRIN have no eff                   */
25752       __IOM uint32_t SIRLP      : 1;            /*!< [2..2] This bit is the SIR low power select. This bit selects
25753                                                      the IrDA encoding mode. If this bit is cleared to 0, low-level
25754                                                      bits are transmitted as an active high pulse with a width
25755                                                      of 3/16th of the bit period. If this bit is set to 1, low-level
25756                                                      bits are transmitted with a pulse width which is 3 times
25757                                                      the period of the IrLPBaud16 input signal, regardless of
25758                                                      the selected bit rate. Setting this bit uses less power,
25759                                                      but might reduce transmission distances.                                  */
25760       __IOM uint32_t CLKEN      : 1;            /*!< [3..3] This bit is the UART clock enable.                                 */
25761       __IOM uint32_t CLKSEL     : 3;            /*!< [6..4] This bitfield is the UART clock select.                            */
25762       __IOM uint32_t LBE        : 1;            /*!< [7..7] This bit is the loopback enable. If this bit is set to
25763                                                      1 and the SIREN bit is set to 1 and the SIRTEST bit in
25764                                                      the Test Control Register, UARTTCR is set to 1, then the
25765                                                      nSIROUT path is inverted, and fed through to the SIRIN
25766                                                      path. The SIRTEST bit in the test register must be set
25767                                                      to 1 to override the normal half-duplex SIR operation.
25768                                                      This must be the requirement for accessing the test registers
25769                                                      during normal operation, and SIRTEST must be cleared to
25770                                                      0 when loopback testing is finished. This feature reduces
25771                                                      the                                                                       */
25772       __IOM uint32_t TXE        : 1;            /*!< [8..8] This bit is the transmit enable. If this bit is set to
25773                                                      1, the transmit section of the UART is enabled. Data transmission
25774                                                      occurs for either UART signals, or SIR signals depending
25775                                                      on the setting of the SIREN bit. When the UART is disabled
25776                                                      in the middle of transmission, it completes the current
25777                                                      character before stopping.                                                */
25778       __IOM uint32_t RXE        : 1;            /*!< [9..9] This bit is the receive enable. If this bit is set to
25779                                                      1, the receive section of the UART is enabled. Data reception
25780                                                      occurs for either UART signals or SIR signals depending
25781                                                      on the setting of the SIREN bit. When the UART is disabled
25782                                                      in the middle of reception, it completes the current character
25783                                                      before stopping.                                                          */
25784       __IOM uint32_t DTR        : 1;            /*!< [10..10] This bit enables data transmit ready. This bit is the
25785                                                      complement of the UART data transmit ready, nUARTDTR, modem
25786                                                      status output. That is, when the bit is programmed to a
25787                                                      1 then nUARTDTR is LOW.                                                   */
25788       __IOM uint32_t RTS        : 1;            /*!< [11..11] This bit enables request to send. This bit is the complement
25789                                                      of the UART request to send, nUARTRTS, modem status output.
25790                                                      That is, when the bit is programmed to a 1 then nUARTRTS
25791                                                      is LOW.                                                                   */
25792       __IOM uint32_t OUT1       : 1;            /*!< [12..12] This bit is the complement of the UART Out1 (nUARTOut1)
25793                                                      modem status output. That is, when the bit is programmed
25794                                                      to a 1 the output is 0. For DTE this can be used as Data
25795                                                      Carrier Detect (DCD).                                                     */
25796       __IOM uint32_t OUT2       : 1;            /*!< [13..13] This bit is the complement of the UART Out2 (nUARTOut2)
25797                                                      modem status output. That is, when the bit is programmed
25798                                                      to a 1, the output is 0. For DTE this can be used as Ring
25799                                                      Indicator (RI).                                                           */
25800       __IOM uint32_t RTSEN      : 1;            /*!< [14..14] This bit enables RTS hardware flow control. If this
25801                                                      bit is set to 1, RTS hardware flow control is enabled.
25802                                                      Data is only requested when there is space in the receive
25803                                                      FIFO for it to be received.                                               */
25804       __IOM uint32_t CTSEN      : 1;            /*!< [15..15] This bit enables CTS hardware flow control. If this
25805                                                      bit is set to 1, CTS hardware flow control is enabled.
25806                                                      Data is only transmitted when the nUARTCTS signal is asserted.            */
25807             uint32_t            : 16;
25808     } CR_b;
25809   } ;
25810 
25811   union {
25812     __IOM uint32_t IFLS;                        /*!< (@ 0x00000034) FIFO Interrupt Level Select                                */
25813 
25814     struct {
25815       __IOM uint32_t TXIFLSEL   : 3;            /*!< [2..0] These bits hold the transmit FIFO interrupt level.                 */
25816       __IOM uint32_t RXIFLSEL   : 3;            /*!< [5..3] These bits hold the receive FIFO interrupt level.                  */
25817             uint32_t            : 26;
25818     } IFLS_b;
25819   } ;
25820 
25821   union {
25822     __IOM uint32_t IER;                         /*!< (@ 0x00000038) Interrupt Enable                                           */
25823 
25824     struct {
25825       __IOM uint32_t TXCMPMIM   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt enable.                   */
25826       __IOM uint32_t CTSMIM     : 1;            /*!< [1..1] This bit holds the modem CTS interrupt enable.                     */
25827       __IOM uint32_t DCDMIM     : 1;            /*!< [2..2] This bit holds the modem DCD interrupt enable.                     */
25828       __IOM uint32_t DSRMIM     : 1;            /*!< [3..3] This bit holds the modem DSR interrupt enable.                     */
25829       __IOM uint32_t RXIM       : 1;            /*!< [4..4] This bit holds the receive interrupt enable.                       */
25830       __IOM uint32_t TXIM       : 1;            /*!< [5..5] This bit holds the transmit interrupt enable.                      */
25831       __IOM uint32_t RTIM       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt enable.               */
25832       __IOM uint32_t FEIM       : 1;            /*!< [7..7] This bit holds the framing error interrupt enable.                 */
25833       __IOM uint32_t PEIM       : 1;            /*!< [8..8] This bit holds the parity error interrupt enable.                  */
25834       __IOM uint32_t BEIM       : 1;            /*!< [9..9] This bit holds the break error interrupt enable.                   */
25835       __IOM uint32_t OEIM       : 1;            /*!< [10..10] This bit holds the overflow interrupt enable.                    */
25836             uint32_t            : 21;
25837     } IER_b;
25838   } ;
25839 
25840   union {
25841     __IOM uint32_t IES;                         /*!< (@ 0x0000003C) Interrupt Status                                           */
25842 
25843     struct {
25844       __IOM uint32_t TXCMPMRIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status.                   */
25845       __IOM uint32_t CTSMRIS    : 1;            /*!< [1..1] This bit holds the nUARTCTS modem interrupt status. Returns
25846                                                      the raw interrupt state of the UARTCTSINTR interrupt.                     */
25847       __IOM uint32_t DCDMRIS    : 1;            /*!< [2..2] This bit holds the nUARTDCD modem interrupt status. Returns
25848                                                      the raw interrupt state of the UARTDCDINTR interrupt.                     */
25849       __IOM uint32_t DSRMRIS    : 1;            /*!< [3..3] This bit holds the nUARTDSR modem interrupt status. Returns
25850                                                      the raw interrupt state of the UARTDSRINTR interrupt.                     */
25851       __IOM uint32_t RXRIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status. Returns
25852                                                      the raw interrupt state of the UARTRXINTR interrupt.                      */
25853       __IOM uint32_t TXRIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status. Returns
25854                                                      the raw interrupt state of the UARTTXINTR interrupt.                      */
25855       __IOM uint32_t RTRIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status.
25856                                                      Returns the raw interrupt state of the UARTRTINTR interrupt.              */
25857       __IOM uint32_t FERIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status. Returns
25858                                                      the raw interrupt state of the UARTFEINTR interrupt.                      */
25859       __IOM uint32_t PERIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status. Returns
25860                                                      the raw interrupt state of the UARTPEINTR interrupt.                      */
25861       __IOM uint32_t BERIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status. Returns
25862                                                      the raw interrupt state of the UARTBEINTR interrupt.                      */
25863       __IOM uint32_t OERIS      : 1;            /*!< [10..10] This bit holds the overrun interrupt status. Returns
25864                                                      the raw interrupt state of the UARTOEINTR interrupt.                      */
25865             uint32_t            : 21;
25866     } IES_b;
25867   } ;
25868 
25869   union {
25870     __IOM uint32_t MIS;                         /*!< (@ 0x00000040) Masked Interrupt Status                                    */
25871 
25872     struct {
25873       __IOM uint32_t TXCMPMMIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status masked.            */
25874       __IOM uint32_t CTSMMIS    : 1;            /*!< [1..1] This bit holds the nUARTCTS modem masked interrupt status.
25875                                                      Returns the masked interrupt state of the UARTCTSINTR interrupt.          */
25876       __IOM uint32_t DCDMMIS    : 1;            /*!< [2..2] This bit holds the nUARTDCD modem masked interrupt status.
25877                                                      Returns the masked interrupt state of the UARTDCDINTR interrupt.          */
25878       __IOM uint32_t DSRMMIS    : 1;            /*!< [3..3] This bit holds the nUARTDSR modem masked interrupt status.
25879                                                      Returns the masked interrupt state of the UARTDSRINTR interrupt.          */
25880       __IOM uint32_t RXMIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status masked. Returns
25881                                                      the masked interrupt state of the UARTRXINTR interrupt.                   */
25882       __IOM uint32_t TXMIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status masked.
25883                                                      Returns the masked interrupt state of the UARTTXINTR interrupt.           */
25884       __IOM uint32_t RTMIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status masked.
25885                                                      Returns the masked interrupt state of the UARTRTINTR interrupt.           */
25886       __IOM uint32_t FEMIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status masked.
25887                                                      Returns the masked interrupt state of the UARTFEINTR interrupt.           */
25888       __IOM uint32_t PEMIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status masked.
25889                                                      Returns the masked interrupt state of the UARTPEINTR interrupt.           */
25890       __IOM uint32_t BEMIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status masked.
25891                                                      Returns the masked interrupt state of the UARTBEINTR interrupt.           */
25892       __IOM uint32_t OEMIS      : 1;            /*!< [10..10] This bit holds the overrun interrupt status masked.
25893                                                      Returns the masked interrupt state of the UARTOEINTR interrupt.           */
25894             uint32_t            : 21;
25895     } MIS_b;
25896   } ;
25897 
25898   union {
25899     __IOM uint32_t IEC;                         /*!< (@ 0x00000044) Interrupt Clear                                            */
25900 
25901     struct {
25902       __IOM uint32_t TXCMPMIC   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt clear.                    */
25903       __IOM uint32_t CTSMIC     : 1;            /*!< [1..1] This bit holds the nUARTCTS modem interrupt clear. Clears
25904                                                      the UARTCTSINTR interrupt.                                                */
25905       __IOM uint32_t DCDMIC     : 1;            /*!< [2..2] This bit holds the nUARTDCD modem interrupt clear. Clears
25906                                                      the UARTDCDINTR interrupt.                                                */
25907       __IOM uint32_t DSRMIC     : 1;            /*!< [3..3] This bit holds the nUARTDSR modem interrupt clear. Clears
25908                                                      the UARTDSRINTR interrupt.                                                */
25909       __IOM uint32_t RXIC       : 1;            /*!< [4..4] This bit holds the receive interrupt clear. Clears the
25910                                                      UARTRXINTR interrupt.                                                     */
25911       __IOM uint32_t TXIC       : 1;            /*!< [5..5] This bit holds the transmit interrupt clear. Clears the
25912                                                      UARTTXINTR interrupt.                                                     */
25913       __IOM uint32_t RTIC       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt clear. Clears
25914                                                      the UARTRTINTR interrupt.                                                 */
25915       __IOM uint32_t FEIC       : 1;            /*!< [7..7] This bit holds the framing error interrupt clear. Clears
25916                                                      the UARTFEINTR interrupt.                                                 */
25917       __IOM uint32_t PEIC       : 1;            /*!< [8..8] This bit holds the parity error interrupt clear. Clears
25918                                                      the UARTPEINTR interrupt.                                                 */
25919       __IOM uint32_t BEIC       : 1;            /*!< [9..9] This bit holds the break error interrupt clear. Clears
25920                                                      the UARTBEINTR interrupt.                                                 */
25921       __IOM uint32_t OEIC       : 1;            /*!< [10..10] This bit holds the overrun interrupt clear. Clears
25922                                                      the UARTOEINTR interrupt.                                                 */
25923             uint32_t            : 21;
25924     } IEC_b;
25925   } ;
25926 } UART0_Type;                                   /*!< Size = 72 (0x48)                                                          */
25927 
25928 
25929 
25930 /* =========================================================================================================================== */
25931 /* ================                                          USBPHY                                           ================ */
25932 /* =========================================================================================================================== */
25933 
25934 
25935 /**
25936   * @brief USBPHY device register descriptions. (USBPHY)
25937   */
25938 
25939 typedef struct {                                /*!< (@ 0x400B4000) USBPHY Structure                                           */
25940 
25941   union {
25942     __IOM uint32_t REG00;                       /*!< (@ 0x00000000) Register description here                                  */
25943 
25944     struct {
25945       __IOM uint32_t BF20       : 3;            /*!< [2..0] This bitfield is reserved.                                         */
25946       __IOM uint32_t BF43       : 2;            /*!< [4..3] BG observation enable signal. Active low. When enabled,
25947                                                      vref 400mV can be observed through USB0PP/USB0PN                          */
25948       __IOM uint32_t BF75       : 3;            /*!< [7..5] Manually set the Rx Clock phase select. These bits will
25949                                                      tune the HS RX path sample timing between digital and analog
25950                                                      inside PHY: 3'b000 represents the earliest phase 3'b111
25951                                                      represents the latest phase The delay associated with each
25952                                                      step is 256ps                                                             */
25953             uint32_t            : 24;
25954     } REG00_b;
25955   } ;
25956 
25957   union {
25958     __IOM uint32_t REG04;                       /*!< (@ 0x00000004) Register description here                                  */
25959 
25960     struct {
25961       __IOM uint32_t BF20       : 3;            /*!< [2..0] Manually set the Tx Clock phase select. These bits will
25962                                                      tune the HS TX path sample timing between digital and analog
25963                                                      inside PHY 3'b000 represents the earliest phase 3'b111
25964                                                      represents the latest phase The delay associated with each
25965                                                      step is 256ps                                                             */
25966       __IOM uint32_t BF43       : 2;            /*!< [4..3] Squelch detector bias current tuning, 2'b00 represents
25967                                                      the minimum bias current 2'b11 represents the maximum bias
25968                                                      current                                                                   */
25969       __IOM uint32_t BF55       : 1;            /*!< [5..5] This bitfield is reserved.                                         */
25970       __IOM uint32_t BF76       : 2;            /*!< [7..6] disconnect detector bias current tuning                            */
25971             uint32_t            : 24;
25972     } REG04_b;
25973   } ;
25974 
25975   union {
25976     __IOM uint32_t REG08;                       /*!< (@ 0x00000008) Register description here                                  */
25977 
25978     struct {
25979       __IOM uint32_t BF30       : 4;            /*!< [3..0] 2'b00 represents the minimum bias current 2'b11 represents
25980                                                      the maximum bias current Rx squelch trigger point configures.
25981                                                      Allows tuning of the squelch trigger point in order to
25982                                                      compensate for package and board level parasitic. 4'b0000:112.5mV
25983                                                      4'b0001:150mV 4'b0010:87.5mV 4'b0011:162.5mV 4'b0100:100mV
25984                                                      4'b0101:137.5mV 4'b0110:75mV 4'b0111:150mV 4'b1000:125mV
25985                                                      4'b1001:162.5mV 4'b1010:100mV 4'b1011:175mV 4'b1100:150mV(default)
25986                                                      4'b1101:187.5mV 4'b1110:125mV 4'b1111:200mV                               */
25987       __IOM uint32_t BF64       : 3;            /*!< [6..4] HS eye height tuning 3'b000:400mV(default) 3'b001:475mV
25988                                                      3'b010:350mV 3'b011:500mV 3'b100:412.5mV 3'b101:425mV 3'b110:437.5mV
25989                                                      3'b111:450mV                                                              */
25990       __IOM uint32_t BF77       : 1;            /*!< [7..7] digital squelch filter select, this bit is used to filter
25991                                                      the glitch on the HS RX squelch signal. 1: 1 clock cycle
25992                                                      filter 0: 2 clock cycle fitter                                            */
25993             uint32_t            : 24;
25994     } REG08_b;
25995   } ;
25996 
25997   union {
25998     __IOM uint32_t REG0C;                       /*!< (@ 0x0000000C) Register description here                                  */
25999 
26000     struct {
26001       __IOM uint32_t BF10       : 2;            /*!< [1..0] BG output voltage reference adjust, normally these bits
26002                                                      are recommended to be kept as the default values. 00: standard
26003                                                      center level around 1.25v output, recommended 01: relative
26004                                                      higher output 1x: relative higher output                                  */
26005       __IOM uint32_t BF62       : 5;            /*!< [6..2] 45ohm HS ODT value tuning and FS/LS driver strength tuning
26006                                                      5'b11111: smallest HS ODT value and largest FS/LS driver
26007                                                      strength and fastest FS/LS slew rate 5'b10000: biggest
26008                                                      HS ODT value and smallest FS/LS driver strength and slowest
26009                                                      FS/LS slew rate                                                           */
26010       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
26011             uint32_t            : 24;
26012     } REG0C_b;
26013   } ;
26014 
26015   union {
26016     __IOM uint32_t REG10;                       /*!< (@ 0x00000010) Register description here                                  */
26017 
26018     struct {
26019       __IOM uint32_t BF00       : 1;            /*!< [0..0] Bypass squelch trigger point configure in chirp modes
26020                                                      , active high, keep the default value is strongly recommended
26021                                                      . 1: Bypass squelch trigger point configure in chirp modes
26022                                                      , 0: squelch trigger point set to 250mV in chirp modes.                   */
26023       __IOM uint32_t BF11       : 1;            /*!< [1..1] Turn off LS/FS differential receiver in suspend mode,
26024                                                      active low 1: keep the LS/FS differential receiver , pin
26025                                                      fss_rxrcv will toggling according to the DP/DM state 0:
26026                                                      turn off the LS/FS differential receiver, pin fss_rxrcv
26027                                                      will not toggling according to the DP/DM state                            */
26028       __IOM uint32_t BF22       : 1;            /*!< [2..2] Half bit pre-emphasis enable. Active high 1: half bit
26029                                                      pre-emphasize mode, recommended 0: full bit pre-emphasize
26030                                                      mode                                                                      */
26031       __IOM uint32_t BF33       : 1;            /*!< [3..3] Single ended disconnect detection enable, active high.
26032                                                      1: enable Single ended disconnect detection 0: disenable
26033                                                      Single ended disconnect detection                                         */
26034       __IOM uint32_t BF74       : 4;            /*!< [7..4] HOST disconnect detection trigger point. Only valid in
26035                                                      host mode. Allows compensation for package and board level
26036                                                      parasitics which tend to drop in the input voltage. 4'b0000:625mV
26037                                                      4'b0001:675mV 4'b0010:612.5mV 4'b0011:575mV 4'b0100:550mV
26038                                                      4'b0101:600mV (default) 4'b0110:537.5mV 4'b0111:500mV 4'b1000:600mV
26039                                                      4'b1001:650mV 4'b1010:587.5mV 4'b1011:550mV 4'b1100:575mV
26040                                                      4'b1101:625mV 4'b1110:562.5mV 4'b1111:525mV                               */
26041             uint32_t            : 24;
26042     } REG10_b;
26043   } ;
26044 
26045   union {
26046     __IOM uint32_t REG14;                       /*!< (@ 0x00000014) Register description here                                  */
26047 
26048     struct {
26049       __IOM uint32_t BF00       : 1;            /*!< [0..0] Dflop output select signal delay compared with digital
26050                                                      clock enable signal 1'b0:3 clocks 1'b1:2 clocks                           */
26051       __IOM uint32_t BF11       : 1;            /*!< [1..1] PLL bandwidth option 1'b0 default 1'b1 increases the
26052                                                      PLL bandwidth                                                             */
26053       __IOM uint32_t BF42       : 3;            /*!< [4..2] Tx HS pre-emphasis strength 3'b111 represents the strongest
26054                                                      , 3'b000 the weakest                                                      */
26055       __IOM uint32_t BF55       : 1;            /*!< [5..5] PLL feedback divider ratio option.                                 */
26056       __IOM uint32_t BF66       : 1;            /*!< [6..6] BF66 field description needed.                                     */
26057       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
26058             uint32_t            : 24;
26059     } REG14_b;
26060   } ;
26061 
26062   union {
26063     __IOM uint32_t REG18;                       /*!< (@ 0x00000018) Register description here                                  */
26064 
26065     struct {
26066       __IOM uint32_t BF10       : 2;            /*!< [1..0] HS receiver bias current tuning. 2'b00 represents the
26067                                                      minimum bias current 2'b11 represents the maximum bias
26068                                                      current                                                                   */
26069       __IOM uint32_t BF22       : 1;            /*!< [2..2] Clk60m, clk12m and clk48m enable. 1'b0:disables the clocks
26070                                                      1'b1:enables the clocks                                                   */
26071       __IOM uint32_t BF73       : 5;            /*!< [7..3] This bitfield is reserved.                                         */
26072             uint32_t            : 24;
26073     } REG18_b;
26074   } ;
26075 
26076   union {
26077     __IOM uint32_t REG1C;                       /*!< (@ 0x0000001C) Register description here                                  */
26078 
26079     struct {
26080       __IOM uint32_t BF00       : 1;            /*!< [0..0] Set IO high-Z state. Active high                                   */
26081       __IOM uint32_t BF11       : 1;            /*!< [1..1] Tx power down in suspend state. Active low.                        */
26082       __IOM uint32_t BF22       : 1;            /*!< [2..2] PLL enable bypass from suspend module. 1'b1: bypass enable
26083                                                      1'b0:bypass disable                                                       */
26084       __IOM uint32_t BF33       : 1;            /*!< [3..3] PLL enable value from suspend module. 1'b1:pll enable              */
26085       __IOM uint32_t BF44       : 1;            /*!< [4..4] 480M clock out enable. 1'b0:pll disable 1'b1: 480M clock
26086                                                      out enable 1'b0: 480M clock out disable                                   */
26087       __IOM uint32_t BF55       : 1;            /*!< [5..5] BG power down control bit, active high 1: power down
26088                                                      band-gap 0: normal operation mode                                         */
26089       __IOM uint32_t BF66       : 1;            /*!< [6..6] This bitfield is reserved.                                         */
26090       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
26091             uint32_t            : 24;
26092     } REG1C_b;
26093   } ;
26094 
26095   union {
26096     __IOM uint32_t REG20;                       /*!< (@ 0x00000020) Register description here                                  */
26097 
26098     struct {
26099       __IOM uint32_t BF20       : 3;            /*!< [2..0] Rx enable delay select. 3'b000: 4 clocks (480Mhz clock)
26100                                                      3'b001: 5 clocks 3'b010: 6 clocks 3'b011: 7 clocks 3'b100:
26101                                                      8 clocks 3'b101: 9 clocks 3'b110: 10 clocks 3'b111: 12
26102                                                      clocks                                                                    */
26103       __IOM uint32_t BF33       : 1;            /*!< [3..3] This bitfield is reserved.                                         */
26104       __IOM uint32_t BF54       : 2;            /*!< [5..4] Analog observation port select. for detailed information,
26105                                                      please refer to section 10.3 , Table 30 : Debug and OBS
26106                                                      port                                                                      */
26107       __IOM uint32_t BF76       : 2;            /*!< [7..6] This bitfield is reserved.                                         */
26108             uint32_t            : 24;
26109     } REG20_b;
26110   } ;
26111 
26112   union {
26113     __IOM uint32_t REG24;                       /*!< (@ 0x00000024) Register description here                                  */
26114 
26115     struct {
26116       __IOM uint32_t BF00       : 1;            /*!< [0..0] it0                                                                */
26117       __IOM uint32_t BF71       : 7;            /*!< [7..1] This bitfield is reserved.                                         */
26118             uint32_t            : 24;
26119     } REG24_b;
26120   } ;
26121 
26122   union {
26123     __IOM uint32_t REG28;                       /*!< (@ 0x00000028) Register description here                                  */
26124 
26125     struct {
26126       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26127             uint32_t            : 24;
26128     } REG28_b;
26129   } ;
26130 
26131   union {
26132     __IOM uint32_t REG2C;                       /*!< (@ 0x0000002C) Register description here                                  */
26133 
26134     struct {
26135       __IOM uint32_t BF00       : 1;            /*!< [0..0] All port z bypass value. 1'b1: bypass enable 1'b0:bypass
26136                                                      disable                                                                   */
26137       __IOM uint32_t BF11       : 1;            /*!< [1..1] This bitfield is reserved.                                         */
26138       __IOM uint32_t BF22       : 1;            /*!< [2..2] HS keep alive enable. 1'b1: HS keep alive enable 1'b0:
26139                                                      HS keep alive disable                                                     */
26140       __IOM uint32_t BF33       : 1;            /*!< [3..3] This bitfield is reserved.                                         */
26141       __IOM uint32_t BF44       : 1;            /*!< [4..4] This bitfield is reserved.                                         */
26142       __IOM uint32_t BF75       : 3;            /*!< [7..5] This bitfield is reserved.                                         */
26143             uint32_t            : 24;
26144     } REG2C_b;
26145   } ;
26146 
26147   union {
26148     __IOM uint32_t REG30;                       /*!< (@ 0x00000030) Register description here                                  */
26149 
26150     struct {
26151       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26152             uint32_t            : 24;
26153     } REG30_b;
26154   } ;
26155 
26156   union {
26157     __IOM uint32_t REG34;                       /*!< (@ 0x00000034) Register description here                                  */
26158 
26159     struct {
26160       __IOM uint32_t BF70       : 8;            /*!< [7..0] BF70 field description needed.                                     */
26161             uint32_t            : 24;
26162     } REG34_b;
26163   } ;
26164 
26165   union {
26166     __IOM uint32_t REG38;                       /*!< (@ 0x00000038) Register description here                                  */
26167 
26168     struct {
26169       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26170             uint32_t            : 24;
26171     } REG38_b;
26172   } ;
26173 
26174   union {
26175     __IOM uint32_t REG3C;                       /*!< (@ 0x0000003C) Register description here                                  */
26176 
26177     struct {
26178       __IOM uint32_t BF10       : 2;            /*!< [1..0] BF10 field description needed.                                     */
26179       __IOM uint32_t BF42       : 3;            /*!< [4..2] This bitfield is reserved.                                         */
26180       __IOM uint32_t BF75       : 3;            /*!< [7..5] Host disconnect filter select. 3'b100:6 clocks(480M clock)
26181                                                      3'b101:8 clocks 3'b111:disconnect disable Other: invalid                  */
26182             uint32_t            : 24;
26183     } REG3C_b;
26184   } ;
26185 
26186   union {
26187     __IOM uint32_t REG40;                       /*!< (@ 0x00000040) Register description here                                  */
26188 
26189     struct {
26190       __IOM uint32_t BF60       : 7;            /*!< [6..0] This bitfield is reserved.                                         */
26191       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
26192             uint32_t            : 24;
26193     } REG40_b;
26194   } ;
26195 
26196   union {
26197     __IOM uint32_t REG44;                       /*!< (@ 0x00000044) Register description here                                  */
26198 
26199     struct {
26200       __IOM uint32_t BF00       : 1;            /*!< [0..0] 1: DP/DM will be sampled in HS Tx or Rx state 0: DP/DM
26201                                                      will be sampled only in Hs Rx state                                       */
26202       __IOM uint32_t BF11       : 1;            /*!< [1..1] Disconnect squelch and comparator calibration bypass,
26203                                                      active high                                                               */
26204       __IOM uint32_t BF42       : 3;            /*!< [4..2] This bitfield is reserved.                                         */
26205       __IOM uint32_t BF65       : 2;            /*!< [6..5] This bitfield is reserved.                                         */
26206       __IOM uint32_t BF77       : 1;            /*!< [7..7] This bitfield is reserved.                                         */
26207             uint32_t            : 24;
26208     } REG44_b;
26209   } ;
26210 
26211   union {
26212     __IOM uint32_t REG48;                       /*!< (@ 0x00000048) Register description here                                  */
26213 
26214     struct {
26215       __IOM uint32_t BF00       : 1;            /*!< [0..0] Enable TX shutdown, active LOW. This bit is only used
26216                                                      for debug purpose , nothing to do with the normal operation
26217                                                      and signal quality, keeping the default value is strongly
26218                                                      recommended.                                                              */
26219       __IOM uint32_t BF71       : 7;            /*!< [7..1] This bitfield is reserved.                                         */
26220             uint32_t            : 24;
26221     } REG48_b;
26222   } ;
26223 
26224   union {
26225     __IOM uint32_t REG4C;                       /*!< (@ 0x0000004C) Register description here                                  */
26226 
26227     struct {
26228       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26229             uint32_t            : 24;
26230     } REG4C_b;
26231   } ;
26232 
26233   union {
26234     __IOM uint32_t REG50;                       /*!< (@ 0x00000050) Register description here                                  */
26235 
26236     struct {
26237       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26238             uint32_t            : 24;
26239     } REG50_b;
26240   } ;
26241 
26242   union {
26243     __IOM uint32_t REG54;                       /*!< (@ 0x00000054) Register description here                                  */
26244 
26245     struct {
26246       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26247             uint32_t            : 24;
26248     } REG54_b;
26249   } ;
26250 
26251   union {
26252     __IOM uint32_t REG58;                       /*!< (@ 0x00000058) Register description here                                  */
26253 
26254     struct {
26255       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26256             uint32_t            : 24;
26257     } REG58_b;
26258   } ;
26259 
26260   union {
26261     __IOM uint32_t REG5C;                       /*!< (@ 0x0000005C) Register description here                                  */
26262 
26263     struct {
26264       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26265             uint32_t            : 24;
26266     } REG5C_b;
26267   } ;
26268 
26269   union {
26270     __IOM uint32_t REG60;                       /*!< (@ 0x00000060) Register description here                                  */
26271 
26272     struct {
26273       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26274             uint32_t            : 24;
26275     } REG60_b;
26276   } ;
26277 
26278   union {
26279     __IOM uint32_t REG64;                       /*!< (@ 0x00000064) Register description here                                  */
26280 
26281     struct {
26282       __IOM uint32_t BF00       : 1;            /*!< [0..0] This bitfield is reserved.                                         */
26283             uint32_t            : 31;
26284     } REG64_b;
26285   } ;
26286 
26287   union {
26288     __IOM uint32_t REG68;                       /*!< (@ 0x00000068) Register description here                                  */
26289 
26290     struct {
26291       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26292             uint32_t            : 24;
26293     } REG68_b;
26294   } ;
26295 
26296   union {
26297     __IOM uint32_t REG6C;                       /*!< (@ 0x0000006C) Register description here                                  */
26298 
26299     struct {
26300       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26301             uint32_t            : 24;
26302     } REG6C_b;
26303   } ;
26304 
26305   union {
26306     __IOM uint32_t REG70;                       /*!< (@ 0x00000070) Register description here                                  */
26307 
26308     struct {
26309       __IOM uint32_t BF70       : 8;            /*!< [7..0] BF70 field description needed.                                     */
26310             uint32_t            : 24;
26311     } REG70_b;
26312   } ;
26313 
26314   union {
26315     __IOM uint32_t REG74;                       /*!< (@ 0x00000074) Register description here                                  */
26316 
26317     struct {
26318       __IOM uint32_t BF00       : 1;            /*!< [0..0] Disconnect detection block input res load sel. 1'b0:
26319                                                      disconnect detection block input res load bypass 1'b1:
26320                                                      disconnect detection block input res load enable                          */
26321       __IOM uint32_t BF31       : 3;            /*!< [3..1] HS driver slew rate tuning 001:SR is weakest 111:SR is
26322                                                      strongest.000 is forbidden.                                               */
26323       __IOM uint32_t BF74       : 4;            /*!< [7..4] This bitfield is reserved.                                         */
26324             uint32_t            : 24;
26325     } REG74_b;
26326   } ;
26327 
26328   union {
26329     __IOM uint32_t REG78;                       /*!< (@ 0x00000078) Register description here                                  */
26330 
26331     struct {
26332       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26333             uint32_t            : 24;
26334     } REG78_b;
26335   } ;
26336 
26337   union {
26338     __IOM uint32_t REG7C;                       /*!< (@ 0x0000007C) Register description here                                  */
26339 
26340     struct {
26341       __IOM uint32_t BF40       : 5;            /*!< [4..0] This bitfield is reserved.                                         */
26342       __IOM uint32_t BF55       : 1;            /*!< [5..5] No leakage current on DP/DM pin when VCCA3P3 power down,
26343                                                      active low. Keeping the default value was greatly appreciated             */
26344       __IOM uint32_t BF66       : 1;            /*!< [6..6] Hs chirp mode amplitude increasing register, active high.          */
26345       __IOM uint32_t BF77       : 1;            /*!< [7..7] Clk60m source clock select. 1'b1: free clock 60M 1'b0:
26346                                                      utmi_clk                                                                  */
26347             uint32_t            : 24;
26348     } REG7C_b;
26349   } ;
26350 
26351   union {
26352     __IOM uint32_t REG80;                       /*!< (@ 0x00000080) Register description here                                  */
26353 
26354     struct {
26355       __IOM uint32_t BF00       : 1;            /*!< [0..0] Digital clock enable bypass 1'b1: digital clock bypass
26356                                                      enable 1'b0: digital clock bypass disable                                 */
26357       __IOM uint32_t BF11       : 1;            /*!< [1..1] Digital clock enable bypass value 1'b1: digital clock
26358                                                      enable 1'b0: digital clock disable                                        */
26359       __IOM uint32_t BF22       : 1;            /*!< [2..2] utmi clock always on 1'b1: utmi clock always on 1'b0:
26360                                                      utmi clock relative to suspendm                                           */
26361       __IOM uint32_t BF73       : 5;            /*!< [7..3] This bitfield is reserved.                                         */
26362             uint32_t            : 24;
26363     } REG80_b;
26364   } ;
26365 
26366   union {
26367     __IOM uint32_t REG84;                       /*!< (@ 0x00000084) Register description here                                  */
26368 
26369     struct {
26370       __IOM uint32_t BF70       : 8;            /*!< [7..0] This bitfield is reserved.                                         */
26371             uint32_t            : 24;
26372     } REG84_b;
26373   } ;
26374 } USBPHY_Type;                                  /*!< Size = 136 (0x88)                                                         */
26375 
26376 
26377 
26378 /* =========================================================================================================================== */
26379 /* ================                                            USB                                            ================ */
26380 /* =========================================================================================================================== */
26381 
26382 
26383 /**
26384   * @brief USB device register descriptions. (USB)
26385   */
26386 
26387 typedef struct {                                /*!< (@ 0x400B0000) USB Structure                                              */
26388 
26389   union {
26390     __IOM uint32_t CFG0;                        /*!< (@ 0x00000000) Function address, power management, interrupt
26391                                                                     status register for EP0 and IN Endpoints
26392                                                                     1 to 5                                                     */
26393 
26394     struct {
26395       __IOM uint32_t FuncAddr   : 7;            /*!< [6..0] The function address. This field should be written with
26396                                                      the address value contained in the SET_ADDRESS standard
26397                                                      device request, when it is received on Endpoint 0. The
26398                                                      new address will not take effect immediately as the host
26399                                                      will still be using the old address for the Status stage
26400                                                      of the device request. The USB Controller will continue
26401                                                      to use the old address for decoding packets until the device
26402                                                      request has completed. The status of the device request
26403                                                      can be determined by reading the Update bit. When a new
26404                                                      a                                                                         */
26405       __IOM uint32_t Update     : 1;            /*!< [7..7] Function Address Update. Set when FuncAddr is written.
26406                                                      Cleared when the new address takes effect (at the end of
26407                                                      the current transfer).                                                    */
26408       __IOM uint32_t Enabl      : 1;            /*!< [8..8] Set by the CPU to enable the SUSPENDM signal. The Enabl
26409                                                      bit is set to enable the SUSPENDM signal to put the UTM
26410                                                      (and any other hardware which uses the SUSPENDM signal)
26411                                                      into Suspend mode. If this bit is not set, Suspend mode
26412                                                      will be detected as normal but the SUSPENDM signal will
26413                                                      remain high so that the UTM does not go into its low-power
26414                                                      mode.                                                                     */
26415       __IOM uint32_t Suspen     : 1;            /*!< [9..9] Suspend Status. This read-only bit is set when Suspend
26416                                                      mode is entered. It is cleared when the CPU reads the interrupt
26417                                                      register, or sets the Resume bit of this register. The
26418                                                      Suspen bit is set by the USB Controller when Suspend mode
26419                                                      is entered. It will be cleared when the CFG2_Suspend field
26420                                                      is read (as a result of receiving a Suspend interrupt).
26421                                                      It will also be cleared if Suspend mode is left by setting
26422                                                      the Resume bit to initiate a remote wake-up.                              */
26423       __IOM uint32_t Resume     : 1;            /*!< [10..10] Resume. Set should clear this bit after 10 ms (a maximum
26424                                                      of 15 ms) to end Resume signaling. The Resume bit is used
26425                                                      to force the USB Controller to generate Resume signaling
26426                                                      on the USB to perform remote wake-up from Suspend mode.
26427                                                      Once set high, it should be left high for approximately
26428                                                      10 ms (at least 1 ms and no more than 15 ms), then cleared.               */
26429       __IOM uint32_t Reset      : 1;            /*!< [11..11] Reset Status. Cleared when either HS negotiation has
26430                                                      completed successfully or after 2.1 ms of reset signaling
26431                                                      if HS negotiation fails. The Reset bit can be used to determine
26432                                                      when reset signaling is present on the USB. Set when Reset
26433                                                      signaling is detected and remains high until the bus reverts
26434                                                      to an idle state.                                                         */
26435       __IOM uint32_t HSMode     : 1;            /*!< [12..12] This read-only bit is set when the USB Controller has
26436                                                      successfully negotiated for High-speed mode. The HSMode
26437                                                      bit can be used to determine whether the USB Controller
26438                                                      is in High-speed mode or Full-speed mode. It will go high
26439                                                      when the function has successfully negotiated for high-speed
26440                                                      operation during a USB reset.                                             */
26441       __IOM uint32_t HSEnab     : 1;            /*!< [13..13] High-speed Enable. When set by the CPU, the USB Controller
26442                                                      will negotiate for high-speed mode when the device is reset
26443                                                      by the hub. If not set, the device will only operate in
26444                                                      Full-speed mode. The HSEnab bit can be used to disable
26445                                                      high-speed operation. Normally the USB Controller will
26446                                                      automatically negotiate for high speed operation, when
26447                                                      it is reset, by sending a 'chirp' to the hub. However if
26448                                                      this bit is cleared then the USB Controller will not send
26449                                                      any 'chirps' to the hub so the function will remain in
26450                                                      F                                                                         */
26451       __IOM uint32_t AMSPECIFIC : 1;            /*!< [14..14] Software-enabled Connection (SoftConn). When set to
26452                                                      1, the PHY is placed in its normal mode and the D+/D- lines
26453                                                      of the USB bus are enabled. When bit is cleared, the PHY
26454                                                      is put into non-driving mode and D+ and D- are tri-stated.                */
26455       __IOM uint32_t ISOUpdate  : 1;            /*!< [15..15] Isochronous Transfer Update. When set by the CPU, the
26456                                                      USB Controller will wait for an SOF token from the time
26457                                                      InPktRdy is set before sending the packet. If an IN token
26458                                                      is received before an SOF token, then a zero length data
26459                                                      packet will be sent. Note: This bit only affects endpoints
26460                                                      performing Isochronous transfers. The ISOUpdate bit affects
26461                                                      all IN Isochronous endpoints in the USB Controller. It
26462                                                      is normally used as a method of ensuring 'clean' start-up
26463                                                      of an IN Isochronous pipe.                                                */
26464       __IOM uint32_t EP0InIntStat : 1;          /*!< [16..16] IN Endpoint 0 interrupt status. All interrupts are
26465                                                      cleared when the register is read.                                        */
26466       __IOM uint32_t EP1InIntStat : 1;          /*!< [17..17] IN Endpoint 1 interrupt status. All interrupts are
26467                                                      cleared when the register is read.                                        */
26468       __IOM uint32_t EP2InIntStat : 1;          /*!< [18..18] IN Endpoint 2 interrupt status. All interrupts are
26469                                                      cleared when the register is read.                                        */
26470       __IOM uint32_t EP3InIntStat : 1;          /*!< [19..19] IN Endpoint 3 interrupt status. All interrupts are
26471                                                      cleared when the register is read.                                        */
26472       __IOM uint32_t EP4InIntStat : 1;          /*!< [20..20] IN Endpoint 4 interrupt status. All interrupts are
26473                                                      cleared when the register is read.                                        */
26474       __IOM uint32_t EP5InIntStat : 1;          /*!< [21..21] IN Endpoint 5 interrupt status. All interrupts are
26475                                                      cleared when the register is read.                                        */
26476             uint32_t            : 10;
26477     } CFG0_b;
26478   } ;
26479 
26480   union {
26481     __IOM uint32_t CFG1;                        /*!< (@ 0x00000004) Indicates which of the IN Endpoint 1 - 5 interrupts
26482                                                                     and the single Endpoint 0 interrupt are
26483                                                                     currently active. Also indicates which of
26484                                                                     the interrupts for OUT Endpoint 1 - 5 are
26485                                                                     currently active. All active interrupts
26486                                                                     are cleared when this register is read.                    */
26487 
26488     struct {
26489       __IOM uint32_t EP0OutIntStat : 1;         /*!< [0..0] OUT Endpoint 0 interrupt status. All interrupts are cleared
26490                                                      when the register is read.                                                */
26491       __IOM uint32_t EP1OutIntStat : 1;         /*!< [1..1] OUT Endpoint 1 interrupt status. All interrupts are cleared
26492                                                      when the register is read.                                                */
26493       __IOM uint32_t EP2OutIntStat : 1;         /*!< [2..2] OUT Endpoint 2 interrupt status. All interrupts are cleared
26494                                                      when the register is read.                                                */
26495       __IOM uint32_t EP3OutIntStat : 1;         /*!< [3..3] OUT Endpoint 3 interrupt status. All interrupts are cleared
26496                                                      when the register is read.                                                */
26497       __IOM uint32_t EP4OutIntStat : 1;         /*!< [4..4] OUT Endpoint 4 interrupt status. All interrupts are cleared
26498                                                      when the register is read.                                                */
26499       __IOM uint32_t EP5OutIntStat : 1;         /*!< [5..5] OUT Endpoint 5 interrupt status. All interrupts are cleared
26500                                                      when the register is read.                                                */
26501             uint32_t            : 10;
26502       __IOM uint32_t EP0InIntEn : 1;            /*!< [16..16] IN Endpoint 0 Interrupt Enable                                   */
26503       __IOM uint32_t EP1InIntEn : 1;            /*!< [17..17] IN Endpoint 1 Interrupt Enable                                   */
26504       __IOM uint32_t EP2InIntEn : 1;            /*!< [18..18] IN Endpoint 2 Interrupt Enable                                   */
26505       __IOM uint32_t EP3InIntEn : 1;            /*!< [19..19] IN Endpoint 3 Interrupt Enable                                   */
26506       __IOM uint32_t EP4InIntEn : 1;            /*!< [20..20] IN Endpoint 4 Interrupt Enable                                   */
26507       __IOM uint32_t EP5InIntEn : 1;            /*!< [21..21] IN Endpoint 5 Interrupt Enable                                   */
26508             uint32_t            : 10;
26509     } CFG1_b;
26510   } ;
26511 
26512   union {
26513     __IOM uint32_t CFG2;                        /*!< (@ 0x00000008) Provides interrupt enable and (currently active)
26514                                                                     status bits for each of the state interrupts,
26515                                                                     as well as the IN Endpoint and OUT Endpoint
26516                                                                     nterrupts. All active interrupts are cleared
26517                                                                     when this register is read. On reset, all
26518                                                                     IN and OUT Endpoint interrupts, in addition
26519                                                                     to Endpoint 0, are set to 1 while the remaining
26520                                                                     bits are set to 0.                                         */
26521 
26522     struct {
26523       __IOM uint32_t EP0OutIntEn : 1;           /*!< [0..0] Out Endpoint 0 Interrupt Enable.                                   */
26524       __IOM uint32_t EP1OutIntEn : 1;           /*!< [1..1] Out Endpoint 1 Interrupt Enable.                                   */
26525       __IOM uint32_t EP2OutIntEn : 1;           /*!< [2..2] Out Endpoint 2 Interrupt Enable.                                   */
26526       __IOM uint32_t EP3OutIntEn : 1;           /*!< [3..3] Out Endpoint 3 Interrupt Enable.                                   */
26527       __IOM uint32_t EP4OutIntEn : 1;           /*!< [4..4] Out Endpoint 4 Interrupt Enable.                                   */
26528       __IOM uint32_t EP5OutIntEn : 1;           /*!< [5..5] Out Endpoint 5 Interrupt Enable.                                   */
26529             uint32_t            : 10;
26530       __IOM uint32_t Suspend    : 1;            /*!< [16..16] Suspend Interrupt Status. Set when suspend signaling
26531                                                      is detected on the bus.                                                   */
26532       __IOM uint32_t Resume     : 1;            /*!< [17..17] Resume Interrupt Status. Set when resume signaling
26533                                                      is detected on the bus while the USB Controller is in Suspend
26534                                                      mode.                                                                     */
26535       __IOM uint32_t Reset      : 1;            /*!< [18..18] Reset Detect Interrupt Status. Set when reset signaling
26536                                                      is detected on the bus.                                                   */
26537       __IOM uint32_t SOF        : 1;            /*!< [19..19] Start of Frame Interrupt Status. Set at the start of
26538                                                      frame.                                                                    */
26539             uint32_t            : 4;
26540       __IOM uint32_t SuspendE   : 1;            /*!< [24..24] Suspend Interrupt Enable.                                        */
26541       __IOM uint32_t ResumeE    : 1;            /*!< [25..25] Resume Interrupt Enable.                                         */
26542       __IOM uint32_t ResetE     : 1;            /*!< [26..26] Reset Detect Interrupt Enable.                                   */
26543       __IOM uint32_t SOFE       : 1;            /*!< [27..27] Start of Frame interrupt enable.                                 */
26544             uint32_t            : 4;
26545     } CFG2_b;
26546   } ;
26547 
26548   union {
26549     __IOM uint32_t CFG3;                        /*!< (@ 0x0000000C) Provides Test fields to put the USB Controller
26550                                                                     into one of four test modes described in
26551                                                                     the USB 2.0 specification. Only one of the
26552                                                                     Test fields should be set at any time. (Not
26553                                                                     used in normal operation.) Also includes
26554                                                                     an index field that determines which endpoint
26555                                                                     control,status registers are accessed via
26556                                                                     the IDXn register fields, and a Frame field
26557                                                                     that holds the last received frame number.                 */
26558 
26559     struct {
26560       __IOM uint32_t FRMNUM     : 16;           /*!< [15..0] Frame Number. Read-only field containing the last received
26561                                                      frame number in bits 10:0, 15:11 read 0.                                  */
26562       __IOM uint32_t ENDPOINT   : 4;            /*!< [19..16] Index selected endpoint.                                         */
26563             uint32_t            : 4;
26564       __IOM uint32_t TestSE0NAK : 1;            /*!< [24..24] Test_SE0_NAK Test Mode. The CPU sets this bit to enter
26565                                                      the Test_SE0_NAK test mode. In this mode, the USB Controller
26566                                                      remains in high-speed mode and responds to any valid IN
26567                                                      token with a NAK.                                                         */
26568       __IOM uint32_t TestJ      : 1;            /*!< [25..25] Test_J Test Mode. The CPU sets this bit to enter the
26569                                                      Test_J test mode. In this mode, the USB Controller - in
26570                                                      high-speed mode - transmits a continuous J on the bus.                    */
26571       __IOM uint32_t TestK      : 1;            /*!< [26..26] Test_K Test Mode. The CPU sets this bit to enter the
26572                                                      Test_K test mode. In this mode, the USB Controller - in
26573                                                      high-speed mode - transmits a continuous K on the bus.                    */
26574       __IOM uint32_t TestPacket : 1;            /*!< [27..27] Test Packet Test Mode. The CPU sets this bit to enter
26575                                                      the Test_Packet test mode. In this mode, the USB Controller
26576                                                      - in high-speed mode - repetitively transmits on the bus
26577                                                      a 53-byte test packet. Note: The 53-byte test packet must
26578                                                      be loaded into the Endpoint 0 FIFO before the test mode
26579                                                      is entered.                                                               */
26580       __IOM uint32_t ForceHS    : 1;            /*!< [28..28] Force High-speed Mode. The CPU sets this bit to force
26581                                                      the USB Controller into High-speed mode when it receives
26582                                                      a USB reset.                                                              */
26583       __IOM uint32_t ForceFS    : 1;            /*!< [29..29] Force Full-speed Mode. The CPU sets this bit to force
26584                                                      the USB Controller into Full-speed mode when it receives
26585                                                      a USB reset.                                                              */
26586             uint32_t            : 2;
26587     } CFG3_b;
26588   } ;
26589 
26590   union {
26591     __IOM uint32_t IDX0;                        /*!< (@ 0x00000010) Provides additional control and status for IN
26592                                                                     transactions through the currently-selected
26593                                                                     endpoint. (To avoid CMSIS conflicts, the
26594                                                                     address here includes an additional offset
26595                                                                     of 0x1000. Access to this register must
26596                                                                     take this into account.) The value returned
26597                                                                     when this register is read reflects the
26598                                                                     status of an endpoint specified by setting
26599                                                                     the endpoint index in the CFG3_ENDPOINT
26600                                                                     field. When the endpoint index (CFG3_ENDPOINT)
26601                                                                     = 0, this field provides status and control
26602                                                                     of Endpoint 0. Also, the                                   */
26603 
26604     struct {
26605       __IOM uint32_t MAXPAYLOAD : 11;           /*!< [10..0] Maximum Payload transmitted in a single transaction.
26606                                                      The total amount of data represented by MAXPAYLOAD x (PKTSPLITOPTION
26607                                                      + 1) must not exceed the FIFO size for the IN endpoint,
26608                                                      and should not exceed half the FIFO size if double-buffering
26609                                                      is required. Note: The value written here (multiplied by
26610                                                      PKTSPLITOPTION + 1 in the case of high-bandwidth Isochronous
26611                                                      transfers) must match the value given in the wMaxPacketSize
26612                                                      field of the Standard Endpoint Descriptor for the associated
26613                                                      endpoint (see USB Specification R                                         */
26614       __IOM uint32_t PKTSPLITOPTION : 5;        /*!< [15..11] Packet Split Option. When IDX0_ISO = 1, this bit serves
26615                                                      as the MAXPAYLOAD multiplier for Isochronous IN transfers.
26616                                                      When IDX0_ISO = 0, this bit serves as the MAXPAYLOAD multiplier
26617                                                      for Bulk IN transfers.If IDX0_ISO = 0x1, this field sets
26618                                                      the multiplier for Isochronous transfers. For Isochronous
26619                                                      endpoints operating in High-Speed mode and with the High-bandwidth
26620                                                      option enabled, PKTSPLITOPTION may be either 2 or 3 (corresponding
26621                                                      to this field's bit 0 set or bit 1 set, respectively, and
26622                                                      bits[4:2] are ignored) an                                                 */
26623       __IOM uint32_t InPktRdyOutPktRdy : 1;     /*!< [16..16] IN Packet Ready / OUT Packet Ready. When CFG3_ENDPOINT
26624                                                      > 0, this bit serves as the InPktRdy field. When CFG3_ENDPOINT
26625                                                      = 0, this bit serves as the OutPkyRdy bit.If CFG3_ENDPOINT
26626                                                      = 0x1-0x5, this bit serves as the InPktRdy field. Set this
26627                                                      bit after loading a data packet into the FIFO. It is cleared
26628                                                      automatically when a data packet has been transmitted.
26629                                                      If the FIFO is double-buffered, it is also automatically
26630                                                      cleared when there is space for a second packet in the
26631                                                      FIFO. An interrupt is generate (if enabled) whe                           */
26632       __IOM uint32_t FIFONotEmptyInPktRdy : 1;  /*!< [17..17] FIFO Not Empty / IN Packet Ready. When CFG3_ENDPOINT
26633                                                      = 1 to 5, this bit serves as the FIFONotEmpty field. When
26634                                                      CFG3_ENDPOINT = 0, this bit serves as the InPktRdy bit.If
26635                                                      CFG3_ENDPOINT = 0x1-0x5, this bit serves as the FIFONotEmpty
26636                                                      field. It is set when there is at least 1 packet in the
26637                                                      IN FIFO.If CFG3_ENDPOINT = 0x0, this bit serves as the
26638                                                      InPktRdy bit. Set this bit after loading a data packet
26639                                                      into the FIFO. It is cleared automatically when the data
26640                                                      packet has been transmitted. An interrupt is generated
26641                                                      whe                                                                       */
26642       __IOM uint32_t UnderRunSentStall : 1;     /*!< [18..18] Under Run / Sent Stall. When CFG3_ENDPOINT = 1 to 5,
26643                                                      this bit serves as the UnderRun field. When CFG3_ENDPOINT
26644                                                      = 0, this bit serves as the SentStall field.If CFG3_ENDPOINT
26645                                                      = 0x1-0x5, this bit serves as the UnderRun field. In ISO
26646                                                      mode this bit is set when a zero length data packet is
26647                                                      sent after receiving an IN token with the InPktRdy bit
26648                                                      not set. In Bulk/Interrupt mode, this bit is set when a
26649                                                      NAK is returned in response to an IN token. The CPU should
26650                                                      clear this bit.If CFG3_ENDPOINT = 0x0, this bit serves
26651                                                      as                                                                        */
26652       __IOM uint32_t FlushFIFODataEnd : 1;      /*!< [19..19] When CFG3_ENDPOINT = 1 to 5, this bit serves as the
26653                                                      FlushFIFO field. When CFG3_ENDPOINT = 0, this bit serves
26654                                                      as the DataEnd bit.If CFG3_ENDPOINT = 0x1-0x5, this bit
26655                                                      serves as the FlushFIFO field. Setting this bit flushes
26656                                                      the next packet to be transmitted from the endpoint IN
26657                                                      FIFO. The FIFO pointer is reset and the InPktRdy bit is
26658                                                      cleared. May be set simultaneously with InPktRdy to abort
26659                                                      the packet that has just been loaded into the FIFO.Note
26660                                                      1: FlushFIFO should only be set when InPktRdy is set (at
26661                                                      other ti                                                                  */
26662       __IOM uint32_t SendStallSetupEnd : 1;     /*!< [20..20] When CFG3_ENDPOINT = 1 to 5, this bit serves as the
26663                                                      SendStall field. When CFG3_ENDPOINT = 0, this bit serves
26664                                                      as the SetupEnd field.If CFG3_ENDPOINT = 0x1-0x5, this
26665                                                      bit serves as the SendStall field. Setting this bit issues
26666                                                      a STALL handshake to an IN token. The CPU clears this bit
26667                                                      to terminate the stall condition.Note: This bit has no
26668                                                      effect when the endpoint is being used for Isochronous
26669                                                      transfers.If CFG3_ENDPOINT = 0x0, this bit serves as the
26670                                                      SetupEnd field. It is set when a control transaction ends
26671                                                      befor                                                                     */
26672       __IOM uint32_t SentStallSendStall : 1;    /*!< [21..21] Sent Stall / Send Stall. When CFG3_ENDPOINT = 1 to
26673                                                      5, this bit serves as the SentStall field. When CFG3_ENDPOINT
26674                                                      = 0, this bit serves as the SendStall function.If CFG3_ENDPOINT
26675                                                      = 0x1-0x5, this bit serves as the SentStall field. It is
26676                                                      set when a STALL handshake is transmitted. The FIFO is
26677                                                      flushed and the InPktRdy bit is cleared. The CPU should
26678                                                      clear this bit.If CFG3_ENDPOINT = 0x0, this bit serves
26679                                                      as the SendStall field. The CPU sets this bit to terminate
26680                                                      the current transaction. The STALL handshake will be                      */
26681       __IOM uint32_t ClrDataTogServicedOutPktRdy : 1;/*!< [22..22] Clear Data Toggle / Serviced OUT Packet Ready. When
26682                                                      CFG3_ENDPOINT = 1 to 5, this bit serves as the ClrDataTog
26683                                                      field. When CFG3_ENDPOINT = 0, this bit serves as the ServicedOutPktReady
26684                                                      field.If CFG3_ENDPOINT = 0x1-0x5, this bit serves as the
26685                                                      ClrDataTog field. Setting this bit resets the endpoint
26686                                                      IN data toggle to 0.If CFG3_ENDPOINT = 0x0, this bit serves
26687                                                      as the ServicedOutPktReady field. The CPU writes a 1 to
26688                                                      this bit to clear the OutPktRdy bit. This bit is cleared
26689                                                      automatically.                                                            */
26690       __IOM uint32_t IncompTxServiceSetupEnd : 1;/*!< [23..23] Incomplete Transmission / Service Setup End. When CFG3_ENDPOINT
26691                                                      = 1 to 5, this bit serves as the IncompTx field. When CFG3_ENDPOINT
26692                                                      = 0, this bit serves as the ServiceSetupEnd field.If CFG3_ENDPOINT
26693                                                      = 0x1-0x5, then this bit serves as the IncompTx field.
26694                                                      If the endpoint is being used for high-bandwidth Isochronous
26695                                                      transfers, this bit is set to indicate when a large packet
26696                                                      has been split into 2 or 3 packets for transmission but
26697                                                      insufficient IN tokens have been received to send all the
26698                                                      parts. The remainder of                                                   */
26699       __IOM uint32_t D0         : 1;            /*!< [24..24] Unused, always return 0.                                         */
26700       __IOM uint32_t DPktBufDis : 1;            /*!< [25..25] Double Packet Buffer Disable. This bit is used to control
26701                                                      the use of Double Packet Buffering. It is ignored when
26702                                                      Dynamic FIFO sizing is enabled. Clearing this bit does
26703                                                      NOT necessarily enable Double Packet Buffering but rather
26704                                                      allows Double Packet Buffering to be determined by the
26705                                                      Endpoint's IDX2_INFIFOSZ setting and MAXPAYLOAD size relationship.
26706                                                      Default is enabled.                                                       */
26707             uint32_t            : 1;
26708       __IOM uint32_t FrcDataTog : 1;            /*!< [27..27] Force Data Toggle. The CPU sets this bit to force the
26709                                                      endpoint's IN data toggle to switch after each data packet
26710                                                      is sent regardless of whether an ACK was received. This
26711                                                      can be used by Interrupt IN endpoints that are used to
26712                                                      communicate rate feedback for Isochronous endpoints.                      */
26713             uint32_t            : 1;
26714       __IOM uint32_t Mode       : 1;            /*!< [29..29] OUT/IN Mode. The CPU sets this bit to enable the endpoint
26715                                                      direction as IN or OUT. Note: Only valid where the endpoint
26716                                                      FIFO is used for both IN and OUT transactions, otherwise
26717                                                      ignored.                                                                  */
26718       __IOM uint32_t ISO        : 1;            /*!< [30..30] Isochronous Transfers. The CPU sets this bit to enable
26719                                                      the IN endpoint for Isochronous transfers (ISO mode) or
26720                                                      for Bulk/Interrupt transfers.                                             */
26721       __IOM uint32_t AutoSet    : 1;            /*!< [31..31] Automatically Set InPktRdy. When set, the FIFONotEmptyInPktRdy
26722                                                      field (for IN Endpoint 0) or InPktRdyOutPktRdy field (for
26723                                                      IN Endpoint 1-5) in this register will be automatically
26724                                                      set when data of the maximum packet size (set in MAXPAYLOAD
26725                                                      field) is loaded into the IN FIFO.                                        */
26726     } IDX0_b;
26727   } ;
26728 
26729   union {
26730     __IOM uint32_t IDX1;                        /*!< (@ 0x00000014) Provides control and status bits for OUT transactions
26731                                                                     through the currently-selected endpoint.
26732                                                                     It is reset to 0. The value returned when
26733                                                                     this register is read reflects the status
26734                                                                     of an endpoint specified by setting the
26735                                                                     endpoint index in the CFG3_ENDPOINT field.
26736                                                                     Also, the MAXPAYLOAD field defines the maximum
26737                                                                     amount of data that can be transferred through
26738                                                                     the selected OUT endpoint in a single operation.
26739                                                                     There is a MAXPAYLOAD for each OUT endpoint
26740                                                                     (except Endpoint 0). Note that the action
26741                                                                     initi                                                      */
26742 
26743     struct {
26744       __IOM uint32_t MAXPAYLOAD : 11;           /*!< [10..0] Maximum Payload transmitted in a single transaction.
26745                                                      The value set can be up to 1024 bytes but is subject to
26746                                                      the constraints placed by the USB Specification on packet
26747                                                      sizes for Bulk, Interrupt and Isochronous transfers in
26748                                                      Fullspeed and High-speed operations. The total amount of
26749                                                      data represented by MAXPAYLOAD x (PKTSPLITOPTION + 1) must
26750                                                      not exceed the FIFO size for the OUT endpoint, and should
26751                                                      not exceed half the FIFO size if double-buffering is required.
26752                                                      Note: The value written here (multiplied by m in the                      */
26753       __IOM uint32_t PKTSPLITOPTION : 5;        /*!< [15..11] Packet Split Option. When IDX1_ISO = 1, this bit serves
26754                                                      as the MAXPAYLOAD multiplier for Isochronous OUT transfers.
26755                                                      When IDX1_ISO = 0, this bit serves as the MAXPAYLOAD multiplier
26756                                                      for Bulk IN transfers.If IDX1_ISO = 0x1, this field sets
26757                                                      the multiplier for Isochronous transfers. For Isochronous
26758                                                      endpoints operating in High-Speed mode and with the High-bandwidth
26759                                                      option enabled, PKTSPLITOPTION may be either 2 or 3 (corresponding
26760                                                      to this field's bit 0 set or bit 1 set, respectively, and
26761                                                      bits[4:2] are ignored) a                                                  */
26762       __IOM uint32_t OutPktRdy  : 1;            /*!< [16..16] OUT Packet Ready. This bit is set when a data packet
26763                                                      has been received. Clear this bit when the packet has been
26764                                                      unloaded from the OUT FIFO. An interrupt is generated (if
26765                                                      enabled) when the bit is set.                                             */
26766       __IOM uint32_t FIFOFull   : 1;            /*!< [17..17] FIFO Full. When set, this bit indicates that no more
26767                                                      packets can be loaded into the OUT FIFO.                                  */
26768       __IOM uint32_t OverRun    : 1;            /*!< [18..18] Overrun Condition. Indicates an overrun.If IDX1_ISO
26769                                                      = 0x1 (ISO mode), this bit is set if an OUT packet arrives
26770                                                      while FIFOFull is set, i.e., the OUT packet cannot be loaded
26771                                                      into the OUT FIFO. The CPU should clear this bit.If IDX1_ISO
26772                                                      = 0x0 (Bulk mode), this field always returns zero. This
26773                                                      field is only valid when the endpoint is operating in ISO
26774                                                      mode.                                                                     */
26775       __IOM uint32_t DataError  : 1;            /*!< [19..19] Data Error. Indicates a CRC error.If IDX1_ISO = 0x1
26776                                                      (ISO mode), this bit is set at the same time that OutPktRdy
26777                                                      is set if the data packet has a CRC error. It is cleared
26778                                                      when OutPktRdy is cleared.If IDX1_ISO = 0x0 (Bulk mode),
26779                                                      this field always returns zero. This field is only valid
26780                                                      when the endpoint is operating in ISO mode.                               */
26781       __IOM uint32_t FlushFIFO  : 1;            /*!< [20..20] Flush FIFO. Set this bit to flush the next packet to
26782                                                      be read from the endpoint OUT FIFO. The FIFO pointer is
26783                                                      reset and the OutPktRdy bit is cleared. FlushFIFO should
26784                                                      only be used when OutPktRdy is set. At other times, it
26785                                                      may cause data to be corrupted. If the FIFO is double-buffered,
26786                                                      FlushFIFO may need to be set twice to completely clear
26787                                                      the FIFO.                                                                 */
26788       __IOM uint32_t SendStall  : 1;            /*!< [21..21] Send Stall. Issues a STALL handshake to a DATA packet.If
26789                                                      IDX1_ISO = 0x1, this bit has no effect when the endpoint
26790                                                      is being used for Isochronous transfers.If IDX1_ISO = 0x0,
26791                                                      this field enables Stall Handshakes for Bulk/Interrupt
26792                                                      transactions. Set this bit to issue a STALL handshake to
26793                                                      a DATA packet. Clear this bit to terminate the stall condition.           */
26794       __IOM uint32_t SentStall  : 1;            /*!< [22..22] Sent Stall. This bit is set when a STALL handshake
26795                                                      is transmitted. The CPU should clear this bit.                            */
26796       __IOM uint32_t ClrDataTog : 1;            /*!< [23..23] Clear Data Toggle. Set this bit to reset the endpoint
26797                                                      data toggle to 0.                                                         */
26798       __IOM uint32_t IncompRx   : 1;            /*!< [24..24] Incomplete Receive. This bit is set in a high-bandwidth
26799                                                      Isochronous transfer if the packet in the OUT FIFO is incomplete
26800                                                      because parts of the data were not received. It is cleared
26801                                                      when OutPktRdy is cleared. Note: In anything other than
26802                                                      a high-bandwidth Isochronous transfer, this bit will always
26803                                                      return 0.                                                                 */
26804       __IOM uint32_t DPktBufDis : 1;            /*!< [25..25] Double Packet Buffer Disable. This bit is used to control
26805                                                      the use of Double Packet Buffering. It is ignored when
26806                                                      Dynamic FIFO sizing is enabled. Clearing this bit does
26807                                                      NOT necessarily enable Double Packet Buffering but rather
26808                                                      allows Double Packet Buffering to be determined by the
26809                                                      Endpoint's IDX2_OUTFIFOSZ setting and MAXPAYLOAD size relationship.
26810                                                      Default is enabled.                                                       */
26811             uint32_t            : 2;
26812       __IOM uint32_t DisNye     : 1;            /*!< [28..28] Disable NYET Handshakes / PID Error. For Bulk/Interrupt
26813                                                      transactions, this bit disable the sending of NYET handshakes.
26814                                                      For Bulk/Interrupt transactions, indicates PID errors.If
26815                                                      IDX1_ISO = 0x1, this field is read-only and, when set,
26816                                                      indicates a PID error in the received packet for Isochronous
26817                                                      transfers.If IDX1_ISO = 0x0, this field disables NYET Handshakes
26818                                                      for Bulk/Interrupt transactions. Set this bit to disable
26819                                                      the sending of NYET handshakes. When set, all successfully
26820                                                      received OUT packets are ACK'd includi                                    */
26821             uint32_t            : 1;
26822       __IOM uint32_t ISO        : 1;            /*!< [30..30] Isochronous Transfers. The CPU sets this bit to enable
26823                                                      the OUT endpoint for either Isochronous transfers (ISO
26824                                                      mode) or for Bulk/Interrupt transfers.                                    */
26825       __IOM uint32_t AutoClear  : 1;            /*!< [31..31] Automatically Clear OutPktRdy.                                   */
26826     } IDX1_b;
26827   } ;
26828 
26829   union {
26830     __IOM uint32_t IDX2;                        /*!< (@ 0x00000018) Contains the outcount value for number of received
26831                                                                     bytes in the packet in the OUT FIFO, and
26832                                                                     the configurable IN and OUT Endpoint FIFO
26833                                                                     size.                                                      */
26834 
26835     struct {
26836       __IOM uint32_t ENDPTOUTCOUNT : 13;        /*!< [12..0] Endpoint OUT Count. When CFG3_ENDPOINT = 1 to 5, this
26837                                                      read-only field holds the number of received data bytes
26838                                                      in the packet in the Endpoint's OUT FIFO. When CFG3_ENDPOINT
26839                                                      = 0, this read-only field holds 7-bit data for number of
26840                                                      received data bytes in Endpoint 0 FIFO (OUT count). In
26841                                                      either case, the value returned changes as the contents
26842                                                      of the FIFO change and is only valid while OutPktRdy is
26843                                                      set. (IMPORTANT: The address for the OUTCOUNT register
26844                                                      is actually the same as COUNT0. However to avoid CMSIS
26845                                                      confli                                                                    */
26846             uint32_t            : 3;
26847       __IOM uint32_t INFIFOSZ   : 5;            /*!< [20..16] IN FIFO Size. Sets the size of the selected IN endpoint
26848                                                      FIFO. Bit 4 of this field defines whether double-packet
26849                                                      buffering supported. When set, double-packet buffering
26850                                                      is supported. When cleared, only single-packet buffering
26851                                                      is supported. Bits [3:0] of this field determine maximum
26852                                                      packet size, where 2^^(b3:b0 + 3) is the maximum packet
26853                                                      size to be allowed (before any splitting within the FIFO
26854                                                      of Bulk/High-Bandwidth packets prior to transmission).                    */
26855             uint32_t            : 3;
26856       __IOM uint32_t OUTFIFOSZ  : 5;            /*!< [28..24] OUT FIFO Size. Sets the size of the selected OUT endpoint
26857                                                      FIFO. Bit 4 of this field defines whether double-packet
26858                                                      buffering is supported. When set, double-packet buffering
26859                                                      is supported. When cleared, only single-packet buffering
26860                                                      is supported. Bits [3:0] of this field determine maximum
26861                                                      packet size, where 2^^(b3:b0 + 3) is the maximum packet
26862                                                      size to be allowed (before any splitting within the FIFO
26863                                                      of Bulk/High-Bandwidth packets prior to transmission).                    */
26864             uint32_t            : 3;
26865     } IDX2_b;
26866   } ;
26867 
26868   union {
26869     __IOM uint32_t FIFOADD;                     /*!< (@ 0x0000001C) Sets the start address of the selected IN and
26870                                                                     OUT endpoint FIFOs.                                        */
26871 
26872     struct {
26873       __IOM uint32_t INFIFOADD  : 13;           /*!< [12..0] Sets the start address of the selected IN endpoint FIFO.          */
26874             uint32_t            : 3;
26875       __IOM uint32_t OUTFIFOADD : 13;           /*!< [28..16] Sets the start address of the selected OUT endpoint
26876                                                      FIFO.                                                                     */
26877             uint32_t            : 3;
26878     } FIFOADD_b;
26879   } ;
26880 
26881   union {
26882     __IOM uint32_t FIFO0;                       /*!< (@ 0x00000020) Endpoint 0 FIFO register                                   */
26883 
26884     struct {
26885       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26886                                                      and reading from this register unloads data from the OUT
26887                                                      FIFO for endpoint 0.                                                      */
26888     } FIFO0_b;
26889   } ;
26890 
26891   union {
26892     __IOM uint32_t FIFO1;                       /*!< (@ 0x00000024) Endpoint 1 FIFO register                                   */
26893 
26894     struct {
26895       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26896                                                      and reading from this register unloads data from the OUT
26897                                                      FIFO for endpoint 1.                                                      */
26898     } FIFO1_b;
26899   } ;
26900 
26901   union {
26902     __IOM uint32_t FIFO2;                       /*!< (@ 0x00000028) Endpoint 2 FIFO register                                   */
26903 
26904     struct {
26905       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26906                                                      and reading from this register unloads data from the OUT
26907                                                      FIFO for endpoint 2.                                                      */
26908     } FIFO2_b;
26909   } ;
26910 
26911   union {
26912     __IOM uint32_t FIFO3;                       /*!< (@ 0x0000002C) Endpoint 3 FIFO register                                   */
26913 
26914     struct {
26915       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26916                                                      and reading from this register unloads data from the OUT
26917                                                      FIFO for endpoint 3.                                                      */
26918     } FIFO3_b;
26919   } ;
26920 
26921   union {
26922     __IOM uint32_t FIFO4;                       /*!< (@ 0x00000030) Endpoint 4 FIFO register                                   */
26923 
26924     struct {
26925       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26926                                                      and reading from this register unloads data from the OUT
26927                                                      FIFO for endpoint 4.                                                      */
26928     } FIFO4_b;
26929   } ;
26930 
26931   union {
26932     __IOM uint32_t FIFO5;                       /*!< (@ 0x00000034) Endpoint 5 FIFO register                                   */
26933 
26934     struct {
26935       __IOM uint32_t FIFO       : 32;           /*!< [31..0] Writing to this register loads data into the IN FIFO
26936                                                      and reading from this register unloads data from the OUT
26937                                                      FIFO for endpoint 5.                                                      */
26938     } FIFO5_b;
26939   } ;
26940   __IM  uint32_t  RESERVED[13];
26941 
26942   union {
26943     __IOM uint32_t HWVERS;                      /*!< (@ 0x0000006C) Read-only register that returns version number
26944                                                                     (xx.yyy) of the core hardware.                             */
26945 
26946     struct {
26947       __IOM uint32_t yyy        : 10;           /*!< [9..0] Minor Version Number (Range 0 - 999).                              */
26948       __IOM uint32_t xx         : 5;            /*!< [14..10] Major Version Number (Range 0 - 31).                             */
26949       __IOM uint32_t RC         : 1;            /*!< [15..15] Unused                                                           */
26950             uint32_t            : 16;
26951     } HWVERS_b;
26952   } ;
26953   __IM  uint32_t  RESERVED1[2];
26954 
26955   union {
26956     __IOM uint32_t INFO;                        /*!< (@ 0x00000078) Contains read-only info of the number of IN and
26957                                                                     OUT endpoints included in the design, width
26958                                                                     of the RAM, the ability to reset the USB
26959                                                                     Controller via software, a soft reset bit
26960                                                                     for the CLK clock domain and a soft reset
26961                                                                     bit for the XCLK clock domain.                             */
26962 
26963     struct {
26964       __IOM uint32_t InEndPoints : 4;           /*!< [3..0] Provides the number of implemented IN Endpoints.                   */
26965       __IOM uint32_t OutEndPoints : 4;          /*!< [7..4] Provides the number of implemented OUT Endpoints.                  */
26966       __IOM uint32_t RamBits    : 4;            /*!< [11..8] Provides the width of the RAM address bus.                        */
26967             uint32_t            : 4;
26968       __IOM uint32_t RSTS       : 1;            /*!< [16..16] Soft reset for the CLK domain. cause the output signal
26969                                                      NRSTO to be asserted low. This bit is self-clearing. For
26970                                                      reset to actually occur, the output NRSTO must be connected
26971                                                      to the input NRST.                                                        */
26972       __IOM uint32_t RSTXS      : 1;            /*!< [17..17] Soft reset for the XCLK domain. will cause the output
26973                                                      signal NRSTXO to be asserted low. This bit is self-clearing.
26974                                                      For reset to actually occur, the output NRSTXO must be
26975                                                      connected to the input NRSTX.                                             */
26976             uint32_t            : 14;
26977     } INFO_b;
26978   } ;
26979   __IM  uint32_t  RESERVED2;
26980 
26981   union {
26982     __IOM uint32_t TIMEOUT1;                    /*!< (@ 0x00000080) Holds the configurable chirp timeout value.                */
26983 
26984     struct {
26985       __IOM uint32_t CTUCH      : 16;           /*!< [15..0] Configurable Chirp Timeout timer; default value of 0x4074
26986                                                      corresponds to a delay of 1.1ms (60Mhz clock cycles * 4
26987                                                      * 0x4074).                                                                */
26988             uint32_t            : 16;
26989     } TIMEOUT1_b;
26990   } ;
26991 
26992   union {
26993     __IOM uint32_t TIMEOUT2;                    /*!< (@ 0x00000084) Holds the configurable delay from the end of
26994                                                                     High Speed resume signal to enable UTM normal
26995                                                                     operating mode.                                            */
26996 
26997     struct {
26998       __IOM uint32_t CTHRSTN    : 16;           /*!< [15..0] Configurable delay from the end of High Speed resume
26999                                                      signaling to enabling UTM normal operating mode. Default
27000                                                      value of 0x32 corresponds to a delay of 3us. This programmed
27001                                                      delay is equivalent to the number of 60MHz clock cycles
27002                                                      * 4.                                                                      */
27003             uint32_t            : 16;
27004     } TIMEOUT2_b;
27005   } ;
27006   __IM  uint32_t  RESERVED3[2014];
27007 
27008   union {
27009     __IOM uint32_t CLKCTRL;                     /*!< (@ 0x00002000) Provides optional control for turning off the
27010                                                                     interface clocks to USB Controller and PHY
27011                                                                     as well as the reference clock to the USB
27012                                                                     PHY.                                                       */
27013 
27014     struct {
27015       __IOM uint32_t PHYREFCLKDIS : 1;          /*!< [0..0] Setting this bit turns off the PHY reference clock.                */
27016             uint32_t            : 7;
27017       __IOM uint32_t CTRLAPBCLKDIS : 1;         /*!< [8..8] Setting this bit turns off the Controller logic clock.             */
27018             uint32_t            : 7;
27019       __IOM uint32_t PHYAPBLCLKDIS : 1;         /*!< [16..16] Setting this bit turns off PHY control logic clock.              */
27020             uint32_t            : 7;
27021       __IOM uint32_t PHYREFCLKSEL : 2;          /*!< [25..24] USB PHY reference clock select.For Full_Speed Mode,
27022                                                      set the reference CLKSEL to use HFRC-based clock. For High-Speed
27023                                                      Mode, set the reference CLKSEL to use HFRC2-based clock.
27024                                                      The HFRC2-based clock is higher power, but meets the low-jitter
27025                                                      requirement for High-Speed Mode.                                          */
27026             uint32_t            : 6;
27027     } CLKCTRL_b;
27028   } ;
27029 
27030   union {
27031     __IOM uint32_t SRAMCTRL;                    /*!< (@ 0x00002004) Provides optional SRAM tuning control.                     */
27032 
27033     struct {
27034       __IOM uint32_t RET1N      : 1;            /*!< [0..0] Retention mode 1 enable, active-LOW                                */
27035       __IOM uint32_t EMA        : 3;            /*!< [3..1] Extra margin adjustment                                            */
27036       __IOM uint32_t EMAS       : 1;            /*!< [4..4] Extra margin adjustment sense amplifier pulse                      */
27037       __IOM uint32_t EMAW       : 2;            /*!< [6..5] Extra margin adjustment for write operations                       */
27038       __IOM uint32_t RAWLM      : 2;            /*!< [8..7] SRAM Adjustment for margin for this read assist scheme             */
27039       __IOM uint32_t RAWL       : 1;            /*!< [9..9] SRAM Read assist enable                                            */
27040       __IOM uint32_t WABLM      : 3;            /*!< [12..10] SRAM No margin adjustment                                        */
27041       __IOM uint32_t WABL       : 1;            /*!< [13..13] SRAM write assist enable                                         */
27042       __IOM uint32_t STOV       : 1;            /*!< [14..14] SRAM self-timed override                                         */
27043             uint32_t            : 17;
27044     } SRAMCTRL_b;
27045   } ;
27046   __IM  uint32_t  RESERVED4[3];
27047 
27048   union {
27049     __IOM uint32_t UTMISTICKYSTATUS;            /*!< (@ 0x00002014) This read only register provides the results
27050                                                                     from the PHY OBS port controlled by reg
27051                                                                     0x20[5:4]. IF any bits are set, the bits
27052                                                                     are sticky. Clear this register using the
27053                                                                     OBSCLRSTAT register.                                       */
27054 
27055     struct {
27056       __IOM uint32_t obsportstciky : 2;         /*!< [1..0] These bits are read only status bits from the PHY OBS
27057                                                      port                                                                      */
27058             uint32_t            : 30;
27059     } UTMISTICKYSTATUS_b;
27060   } ;
27061 
27062   union {
27063     __IOM uint32_t OBSCLRSTAT;                  /*!< (@ 0x00002018) Clears all bits in the sticky obs status register.         */
27064 
27065     struct {
27066       __IOM uint32_t CLRSTAT    : 1;            /*!< [0..0] Writing a 1 to this bit clears all bits in the UTMISTICKYSTATUS
27067                                                      register.                                                                 */
27068             uint32_t            : 31;
27069     } OBSCLRSTAT_b;
27070   } ;
27071 
27072   union {
27073     __IOM uint32_t DPDMPULLDOWN;                /*!< (@ 0x0000201C) Enables a pulldown resistor(15K) on D+ or D-               */
27074 
27075     struct {
27076       __IOM uint32_t DMPULLDOWN : 1;            /*!< [0..0] Enables a pulldown resistor(15K) on D-                             */
27077       __IOM uint32_t DPPULLDOWN : 1;            /*!< [1..1] Enables a pulldown resistor(15K) on D+                             */
27078             uint32_t            : 30;
27079     } DPDMPULLDOWN_b;
27080   } ;
27081 
27082   union {
27083     __IOM uint32_t BCDETSTATUS;                 /*!< (@ 0x00002020) USB Battery Charge Detenction Registers                    */
27084 
27085     struct {
27086       __IOM uint32_t DPATTACHED : 1;            /*!< [0..0] Data pin attachment detected                                       */
27087       __IOM uint32_t CPDETECTED : 1;            /*!< [1..1] Charging port detected                                             */
27088       __IOM uint32_t DCPDETECTED : 1;           /*!< [2..2] Dedicated charging port detected                                   */
27089             uint32_t            : 1;
27090       __IOM uint32_t DPCOMPOUT  : 1;            /*!< [4..4] DP comparator output                                               */
27091       __IOM uint32_t DMCOMPOUT  : 1;            /*!< [5..5] DM comparator output                                               */
27092             uint32_t            : 26;
27093     } BCDETSTATUS_b;
27094   } ;
27095 
27096   union {
27097     __IOM uint32_t BCDETCRTL1;                  /*!< (@ 0x00002024) Battery Charging detection main control register           */
27098 
27099     struct {
27100       __IOM uint32_t BCWEAKPULLUPEN : 1;        /*!< [0..0] Enables weak source current to DP and DM                           */
27101       __IOM uint32_t BCWEAKPULLDOWNEN : 1;      /*!< [1..1] Enables weak sink current on DP and DM                             */
27102       __IOM uint32_t IDMSINKEN  : 1;            /*!< [2..2] Enables DM current sink                                            */
27103       __IOM uint32_t IDPSRCEN   : 1;            /*!< [3..3] Enables DP current source                                          */
27104       __IOM uint32_t VDPSRCEN   : 1;            /*!< [4..4] Enables DP voltage source                                          */
27105       __IOM uint32_t RDMPDWNEN  : 1;            /*!< [5..5] Enables DM BC 1.2 pull-down resistor                               */
27106       __IOM uint32_t VDMSRCEN   : 1;            /*!< [6..6] Enables DM voltage source                                          */
27107       __IOM uint32_t IDPSINKEN  : 1;            /*!< [7..7] Enables DP current sink                                            */
27108       __IOM uint32_t USBDCOMPREF : 2;           /*!< [9..8] Sets DP/DM vendor-specific comparator ref voltage                  */
27109             uint32_t            : 1;
27110       __IOM uint32_t USBDCOMPEN : 1;            /*!< [11..11] Enables DP/DM vendor-specific detection comparator               */
27111             uint32_t            : 19;
27112       __IOM uint32_t USBSWRESET : 1;            /*!< [31..31] Holds a USB controller and PHY in the reset for BC
27113                                                      detection                                                                 */
27114     } BCDETCRTL1_b;
27115   } ;
27116 
27117   union {
27118     __IOM uint32_t BCDETCRTL2;                  /*!< (@ 0x00002028) Battery Charging auxillary detection control
27119                                                                     register                                                   */
27120 
27121     struct {
27122       __IOM uint32_t CHARGEDETBYP : 1;          /*!< [0..0] BC detection bypass                                                */
27123       __IOM uint32_t FORCEDPATTACHED : 1;       /*!< [1..1] Force output dp_attached                                           */
27124       __IOM uint32_t FORCECPDET : 1;            /*!< [2..2] Force output charging port detected                                */
27125       __IOM uint32_t FORCEDCPDET : 1;           /*!< [3..3] Force output dedicated charging port detected                      */
27126             uint32_t            : 4;
27127       __IOM uint32_t BCWEAKPULLUPTUNE : 2;      /*!< [9..8] Weak source resistor to both DP and DM tuning. Trimmable.          */
27128       __IOM uint32_t BCWEAKPULLDOWNTUNE : 2;    /*!< [11..10] Weak sink resistor to both DP and DM tuning. Trimmable.          */
27129             uint32_t            : 20;
27130     } BCDETCRTL2_b;
27131   } ;
27132 } USB_Type;                                     /*!< Size = 8236 (0x202c)                                                      */
27133 
27134 
27135 
27136 /* =========================================================================================================================== */
27137 /* ================                                           VCOMP                                           ================ */
27138 /* =========================================================================================================================== */
27139 
27140 
27141 /**
27142   * @brief Voltage Comparator (VCOMP)
27143   */
27144 
27145 typedef struct {                                /*!< (@ 0x4000C000) VCOMP Structure                                            */
27146 
27147   union {
27148     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The Voltage Comparator Configuration Register
27149                                                                     contains the software control for selecting
27150                                                                     beween the 4 options for the positive input
27151                                                                     as well as the multiple options for the
27152                                                                     reference input.                                           */
27153 
27154     struct {
27155       __IOM uint32_t PSEL       : 2;            /*!< [1..0] This bitfield selects the positive input to the comparator.        */
27156             uint32_t            : 6;
27157       __IOM uint32_t NSEL       : 2;            /*!< [9..8] This bitfield selects the negative input to the comparator.        */
27158             uint32_t            : 6;
27159       __IOM uint32_t LVLSEL     : 4;            /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this
27160                                                      bitfield selects the voltage level for the negative input
27161                                                      to the comparator.                                                        */
27162             uint32_t            : 12;
27163     } CFG_b;
27164   } ;
27165 
27166   union {
27167     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) Status                                                     */
27168 
27169     struct {
27170       __IOM uint32_t CMPOUT     : 1;            /*!< [0..0] This bit is 1 if the positive input of the comparator
27171                                                      is greater than the negative input.                                       */
27172       __IOM uint32_t PWDSTAT    : 1;            /*!< [1..1] This bit indicates the power down state of the voltage
27173                                                      comparator.                                                               */
27174             uint32_t            : 30;
27175     } STAT_b;
27176   } ;
27177 
27178   union {
27179     __IOM uint32_t PWDKEY;                      /*!< (@ 0x00000008) Write a value of 0x37 to unlock, write any other
27180                                                                     value to lock. This register also indicates
27181                                                                     lock status when read. When in the unlccked
27182                                                                     state (i.e. 0x37 has been written), it reads
27183                                                                     as 1. When in the locked state, it reads
27184                                                                     as 0.                                                      */
27185 
27186     struct {
27187       __IOM uint32_t PWDKEY     : 32;           /*!< [31..0] Key register value.                                               */
27188     } PWDKEY_b;
27189   } ;
27190   __IM  uint32_t  RESERVED[125];
27191 
27192   union {
27193     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
27194                                                                     to generate the corresponding interrupt.                   */
27195 
27196     struct {
27197       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
27198       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
27199             uint32_t            : 30;
27200     } INTEN_b;
27201   } ;
27202 
27203   union {
27204     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
27205                                                                     cause of a recent interrupt.                               */
27206 
27207     struct {
27208       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
27209       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
27210             uint32_t            : 30;
27211     } INTSTAT_b;
27212   } ;
27213 
27214   union {
27215     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
27216                                                                     the interrupt status associated with that
27217                                                                     bit.                                                       */
27218 
27219     struct {
27220       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
27221       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
27222             uint32_t            : 30;
27223     } INTCLR_b;
27224   } ;
27225 
27226   union {
27227     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
27228                                                                     generate an interrupt from this module.
27229                                                                     (Generally used for testing purposes).                     */
27230 
27231     struct {
27232       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
27233       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
27234             uint32_t            : 30;
27235     } INTSET_b;
27236   } ;
27237 } VCOMP_Type;                                   /*!< Size = 528 (0x210)                                                        */
27238 
27239 
27240 
27241 /* =========================================================================================================================== */
27242 /* ================                                            WDT                                            ================ */
27243 /* =========================================================================================================================== */
27244 
27245 
27246 /**
27247   * @brief Watchdog Timer (WDT)
27248   */
27249 
27250 typedef struct {                                /*!< (@ 0x40024000) WDT Structure                                              */
27251 
27252   union {
27253     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) This is the configuration register for the watch
27254                                                                     dog timer. It controls the enable, interrupt
27255                                                                     set, clocks for the timer, the compare values
27256                                                                     for the counters to trigger a reset or interrupt.
27257                                                                     This register can only be written to if
27258                                                                     the watch dog timer is unlocked (WDTLOCK
27259                                                                     is not set).                                               */
27260 
27261     struct {
27262       __IOM uint32_t WDTEN      : 1;            /*!< [0..0] This bitfield enables the WDT.                                     */
27263       __IOM uint32_t INTEN      : 1;            /*!< [1..1] This bitfield enables the WDT interrupt. Note : This
27264                                                      bit must be set before the interrupt status bit will reflect
27265                                                      a watchdog timer expiration. The IER interrupt register
27266                                                      must also be enabled for a WDT interrupt to be sent to
27267                                                      the NVIC.                                                                 */
27268       __IOM uint32_t RESEN      : 1;            /*!< [2..2] This bitfield enables the WDT reset. This needs to be
27269                                                      set together with the WDREN bit in REG_RSTGEN_CFG register
27270                                                      (in reset gen) to trigger the reset.                                      */
27271       __IOM uint32_t DSPRESETINTEN : 1;         /*!< [3..3] This bitfield enables the DSP Reset Interrupt. This interrupt
27272                                                      is provided to the ARM CPU to notify it that a DSP's WDT
27273                                                      has expired and a reset has been issued to one of the DSP
27274                                                      cores.                                                                    */
27275             uint32_t            : 4;
27276       __IOM uint32_t RESVAL     : 8;            /*!< [15..8] This bitfield is the compare value for counter bits
27277                                                      7:0 to generate a watchdog reset. This will cause a software
27278                                                      reset.                                                                    */
27279       __IOM uint32_t INTVAL     : 8;            /*!< [23..16] This bitfield is the compare value for counter bits
27280                                                      7:0 to generate a watchdog interrupt.                                     */
27281       __IOM uint32_t CLKSEL     : 3;            /*!< [26..24] Select the frequency for the WDT. All values not enumerated
27282                                                      below are undefined.                                                      */
27283             uint32_t            : 5;
27284     } CFG_b;
27285   } ;
27286 
27287   union {
27288     __IOM uint32_t RSTRT;                       /*!< (@ 0x00000004) This register will Restart the watchdog timer.
27289                                                                     Writing a special key value into this register
27290                                                                     will result in the watch dog timer being
27291                                                                     reset, so that the count will start again.
27292                                                                     It is expected that the software will periodically
27293                                                                     write to this register to indicate that
27294                                                                     the system is functional. The watch dog
27295                                                                     timer can continue running when the system
27296                                                                     is in deep sleep, and the interrupt will
27297                                                                     trigger the wake. After the wake, the core
27298                                                                     can reset the watch dog timer.                             */
27299 
27300     struct {
27301       __IOM uint32_t RSTRT      : 8;            /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer.
27302                                                      This is a write only register. Reading this register will
27303                                                      only provide all 0.                                                       */
27304             uint32_t            : 24;
27305     } RSTRT_b;
27306   } ;
27307 
27308   union {
27309     __IOM uint32_t LOCK;                        /*!< (@ 0x00000008) This register locks the watch dog timer. Once
27310                                                                     it is locked, the configuration register
27311                                                                     (WDTCFG) for watch dog timer cannot be written
27312                                                                     to.                                                        */
27313 
27314     struct {
27315       __IOM uint32_t LOCK       : 8;            /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the
27316                                                      WDTCFG reg cannot be written and WDTEN is set.                            */
27317             uint32_t            : 24;
27318     } LOCK_b;
27319   } ;
27320 
27321   union {
27322     __IOM uint32_t COUNT;                       /*!< (@ 0x0000000C) This register holds the current count for the
27323                                                                     watch dog timer. This is a read only register.
27324                                                                     SW cannot set the value in the counter,
27325                                                                     but can reset it.                                          */
27326 
27327     struct {
27328       __IOM uint32_t COUNT      : 8;            /*!< [7..0] Read-Only current value of the WDT counter                         */
27329             uint32_t            : 24;
27330     } COUNT_b;
27331   } ;
27332 
27333   union {
27334     __IOM uint32_t DSP0CFG;                     /*!< (@ 0x00000010) This is the configuration register for the DSP0
27335                                                                     watch dog timer. It controls the enable,
27336                                                                     interrupt set, clocks for the timer, the
27337                                                                     compare values for the counters to trigger
27338                                                                     a reset or interrupt. This register can
27339                                                                     only be written to if the associated DSP0TLOCK
27340                                                                     is not set.                                                */
27341 
27342     struct {
27343       __IOM uint32_t DSP0WDTEN  : 1;            /*!< [0..0] This bitfield enables the WDT. Setting the lock implicitly
27344                                                      sets the WTDEN bit as well.                                               */
27345       __IOM uint32_t DSP0INTEN  : 1;            /*!< [1..1] This bitfield enables the DSP0 WDT interrupt. Note :
27346                                                      This bit must be set before the interrupt status bit will
27347                                                      reflect a watchdog timer expiration. The IER interrupt
27348                                                      register must also be enabled for a WDT interrupt to be
27349                                                      sent to the NVIC.                                                         */
27350       __IOM uint32_t DSP0RESEN  : 1;            /*!< [2..2] This bitfield enables the DSP0 reset.                              */
27351       __IOM uint32_t DSP0PMRESEN : 1;           /*!< [3..3] This bitfield enables the DSP0 Power Controller (PM)
27352                                                      reset. This needs to be set together with the DSP0WDTEN
27353                                                      bit to allow the reset to trigger.                                        */
27354             uint32_t            : 4;
27355       __IOM uint32_t DSP0RESVAL : 8;            /*!< [15..8] This bitfield is the compare value for counter bits
27356                                                      7:0 to generate a watchdog reset for the DSP logic. This
27357                                                      will cause a software reset to the DSP core if the RESEN
27358                                                      bit is set and optionally interrupt the CPU.                              */
27359       __IOM uint32_t DSP0INTVAL : 8;            /*!< [23..16] This bitfield is the compare value for counter bits
27360                                                      7:0 to generate a watchdog interrupt.                                     */
27361       __IOM uint32_t DSP0PMRESVAL : 8;          /*!< [31..24] This bitfield is the compare value for counter bits
27362                                                      7:0 to generate a watchdog reset. This will cause a software
27363                                                      reset to the DSP Power Management logic if the PMRESEN
27364                                                      bit is set and optionally interrupt the CPU.                              */
27365     } DSP0CFG_b;
27366   } ;
27367 
27368   union {
27369     __IOM uint32_t DSP0RSTRT;                   /*!< (@ 0x00000014) This register will restart the watchdog timer.
27370                                                                     Writing a special key value into this register
27371                                                                     will result in the watch dog timer being
27372                                                                     reset, so that the count will start again.
27373                                                                     It is expected that the software will periodically
27374                                                                     write to this register to indicate that
27375                                                                     the system is functional. The watch dog
27376                                                                     timer can continue running when the system
27377                                                                     is in deep sleep, and the interrupt will
27378                                                                     trigger the wake. After the wake, the core
27379                                                                     can reset the watch dog timer.                             */
27380 
27381     struct {
27382       __IOM uint32_t DSP0RSTART : 8;            /*!< [7..0] Writing 0x69 to DSP0RSTRT restarts the watchdog timer.
27383                                                      This is a write only register. Reading this register will
27384                                                      return 0.                                                                 */
27385             uint32_t            : 24;
27386     } DSP0RSTRT_b;
27387   } ;
27388 
27389   union {
27390     __IOM uint32_t DSP0TLOCK;                   /*!< (@ 0x00000018) This register locks the watch dog timer. Once
27391                                                                     it is locked, the configuration register
27392                                                                     (DSP0CFG) for watch dog timer cannot be
27393                                                                     written to and the timer is automatically
27394                                                                     enabled (WDTEN is set).                                    */
27395 
27396     struct {
27397       __IOM uint32_t DSP0LOCK   : 8;            /*!< [7..0] Writing 0xa7 locks the watchdog timer. Once locked, the
27398                                                      WDTCFG reg cannot be written and WDTEN is set.                            */
27399             uint32_t            : 24;
27400     } DSP0TLOCK_b;
27401   } ;
27402 
27403   union {
27404     __IOM uint32_t DSP0COUNT;                   /*!< (@ 0x0000001C) This register holds the current count for the
27405                                                                     watch dog timer. This is a read only register.
27406                                                                     SW cannot set the value in the counter,
27407                                                                     but can reset it.                                          */
27408 
27409     struct {
27410       __IOM uint32_t DSP0COUNT  : 8;            /*!< [7..0] Read-Only current value of the WDT counter                         */
27411             uint32_t            : 24;
27412     } DSP0COUNT_b;
27413   } ;
27414 
27415   union {
27416     __IOM uint32_t DSP1CFG;                     /*!< (@ 0x00000020) This is the configuration register for the DSP1
27417                                                                     watch dog timer. It controls the enable,
27418                                                                     interrupt set, clocks for the timer, the
27419                                                                     compare values for the counters to trigger
27420                                                                     a reset or interrupt. This register can
27421                                                                     only be written to if the associated DSP1TLOCK
27422                                                                     is not set.                                                */
27423 
27424     struct {
27425       __IOM uint32_t DSP1WDTEN  : 1;            /*!< [0..0] This bitfield enables the WDT. Setting the lock implicitly
27426                                                      sets the WTDEN bit as well.                                               */
27427       __IOM uint32_t DSP1INTEN  : 1;            /*!< [1..1] This bitfield enables the DSP1 WDT interrupt. Note :
27428                                                      This bit must be set before the interrupt status bit will
27429                                                      reflect a watchdog timer expiration. The IER interrupt
27430                                                      register must also be enabled for a WDT interrupt to be
27431                                                      sent to the NVIC.                                                         */
27432       __IOM uint32_t DSP1RESEN  : 1;            /*!< [2..2] This bitfield enables the DSP1 reset.                              */
27433       __IOM uint32_t DSP1PMRESEN : 1;           /*!< [3..3] This bitfield enables the DSP1 Power Controller (PM)
27434                                                      reset. This needs to be set together with the DSP1WDTEN
27435                                                      bit to allow the reset to trigger.                                        */
27436             uint32_t            : 4;
27437       __IOM uint32_t DSP1RESVAL : 8;            /*!< [15..8] This bitfield is the compare value for counter bits
27438                                                      7:0 to generate a watchdog reset for the DSP logic. This
27439                                                      will cause a software reset to the DSP core if the RESEN
27440                                                      bit is set and optionally interrupt the CPU.                              */
27441       __IOM uint32_t DSP1INTVAL : 8;            /*!< [23..16] This bitfield is the compare value for counter bits
27442                                                      7:0 to generate a watchdog interrupt.                                     */
27443       __IOM uint32_t DSP1PMRESVAL : 8;          /*!< [31..24] This bitfield is the compare value for counter bits
27444                                                      7:0 to generate a watchdog reset. This will cause a software
27445                                                      reset to the DSP Power Management logic if the PMRESEN
27446                                                      bit is set and optionally interrupt the CPU.                              */
27447     } DSP1CFG_b;
27448   } ;
27449 
27450   union {
27451     __IOM uint32_t DSP1RSTRT;                   /*!< (@ 0x00000024) This register will restart the watchdog timer.
27452                                                                     Writing a special key value into this register
27453                                                                     will result in the watch dog timer being
27454                                                                     reset, so that the count will start again.
27455                                                                     It is expected that the software will periodically
27456                                                                     write to this register to indicate that
27457                                                                     the system is functional. The watch dog
27458                                                                     timer can continue running when the system
27459                                                                     is in deep sleep, and the interrupt will
27460                                                                     trigger the wake. After the wake, the core
27461                                                                     can reset the watch dog timer.                             */
27462 
27463     struct {
27464       __IOM uint32_t DSP1RSTART : 8;            /*!< [7..0] Writing 0xd2 to DSP1RSTRT restarts the watchdog timer.
27465                                                      This is a write only register. Reading this register will
27466                                                      return 0.                                                                 */
27467             uint32_t            : 24;
27468     } DSP1RSTRT_b;
27469   } ;
27470 
27471   union {
27472     __IOM uint32_t DSP1TLOCK;                   /*!< (@ 0x00000028) This register locks the watch dog timer. Once
27473                                                                     it is locked, the configuration register
27474                                                                     (DSP1CFG) for watch dog timer cannot be
27475                                                                     written to and the timer is automatically
27476                                                                     enabled (WDTEN is set).                                    */
27477 
27478     struct {
27479       __IOM uint32_t DSP1LOCK   : 8;            /*!< [7..0] Writing 0x4e locks the watchdog timer. Once locked, the
27480                                                      WDTCFG reg cannot be written and WDTEN is set.                            */
27481             uint32_t            : 24;
27482     } DSP1TLOCK_b;
27483   } ;
27484 
27485   union {
27486     __IOM uint32_t DSP1COUNT;                   /*!< (@ 0x0000002C) This register holds the current count for the
27487                                                                     watch dog timer. This is a read only register.
27488                                                                     SW cannot set the value in the counter,
27489                                                                     but can reset it.                                          */
27490 
27491     struct {
27492       __IOM uint32_t DSP1COUNT  : 8;            /*!< [7..0] Read-Only current value of the WDT counter                         */
27493             uint32_t            : 24;
27494     } DSP1COUNT_b;
27495   } ;
27496   __IM  uint32_t  RESERVED[116];
27497 
27498   union {
27499     __IOM uint32_t WDTIEREN;                    /*!< (@ 0x00000200) Set bits in this register to allow this module
27500                                                                     to generate the corresponding interrupt.                   */
27501 
27502     struct {
27503       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
27504       __IOM uint32_t DSPRESETINT : 1;           /*!< [1..1] Indicates that one of the DSP timers has issued a reset
27505                                                      or pmreset to the DSP core. This is used to interrupt the
27506                                                      main CPU.                                                                 */
27507             uint32_t            : 30;
27508     } WDTIEREN_b;
27509   } ;
27510 
27511   union {
27512     __IOM uint32_t WDTIERSTAT;                  /*!< (@ 0x00000204) Read bits from this register to discover the
27513                                                                     cause of a recent interrupt.                               */
27514 
27515     struct {
27516       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
27517       __IOM uint32_t DSPRESETINT : 1;           /*!< [1..1] Indicates that one of the DSP timers has issued a reset
27518                                                      or pmreset to the DSP core. This is used to interrupt the
27519                                                      main CPU.                                                                 */
27520             uint32_t            : 30;
27521     } WDTIERSTAT_b;
27522   } ;
27523 
27524   union {
27525     __IOM uint32_t WDTIERCLR;                   /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
27526                                                                     the interrupt status associated with that
27527                                                                     bit.                                                       */
27528 
27529     struct {
27530       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
27531       __IOM uint32_t DSPRESETINT : 1;           /*!< [1..1] Indicates that one of the DSP timers has issued a reset
27532                                                      or pmreset to the DSP core. This is used to interrupt the
27533                                                      main CPU.                                                                 */
27534             uint32_t            : 30;
27535     } WDTIERCLR_b;
27536   } ;
27537 
27538   union {
27539     __IOM uint32_t WDTIERSET;                   /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
27540                                                                     generate an interrupt from this module.
27541                                                                     (Generally used for testing purposes).                     */
27542 
27543     struct {
27544       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
27545       __IOM uint32_t DSPRESETINT : 1;           /*!< [1..1] Indicates that one of the DSP timers has issued a reset
27546                                                      or pmreset to the DSP core. This is used to interrupt the
27547                                                      main CPU.                                                                 */
27548             uint32_t            : 30;
27549     } WDTIERSET_b;
27550   } ;
27551 
27552   union {
27553     __IOM uint32_t DSP0IEREN;                   /*!< (@ 0x00000210) Set bits in this register to allow this module
27554                                                                     to generate the corresponding interrupt.                   */
27555 
27556     struct {
27557       __IOM uint32_t DSP0INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27558             uint32_t            : 31;
27559     } DSP0IEREN_b;
27560   } ;
27561 
27562   union {
27563     __IOM uint32_t DSP0IERSTAT;                 /*!< (@ 0x00000214) Read bits from this register to discover the
27564                                                                     cause of a recent interrupt.                               */
27565 
27566     struct {
27567       __IOM uint32_t DSP0INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27568             uint32_t            : 31;
27569     } DSP0IERSTAT_b;
27570   } ;
27571 
27572   union {
27573     __IOM uint32_t DSP0IERCLR;                  /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
27574                                                                     the interrupt status associated with that
27575                                                                     bit.                                                       */
27576 
27577     struct {
27578       __IOM uint32_t DSP0INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27579             uint32_t            : 31;
27580     } DSP0IERCLR_b;
27581   } ;
27582 
27583   union {
27584     __IOM uint32_t DSP0IERSET;                  /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
27585                                                                     generate an interrupt from this module.
27586                                                                     (Generally used for testing purposes).                     */
27587 
27588     struct {
27589       __IOM uint32_t DSP0INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27590             uint32_t            : 31;
27591     } DSP0IERSET_b;
27592   } ;
27593 
27594   union {
27595     __IOM uint32_t DSP1IEREN;                   /*!< (@ 0x00000220) Set bits in this register to allow this module
27596                                                                     to generate the corresponding interrupt.                   */
27597 
27598     struct {
27599       __IOM uint32_t DSP1INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27600             uint32_t            : 31;
27601     } DSP1IEREN_b;
27602   } ;
27603 
27604   union {
27605     __IOM uint32_t DSP1IERSTAT;                 /*!< (@ 0x00000224) Read bits from this register to discover the
27606                                                                     cause of a recent interrupt.                               */
27607 
27608     struct {
27609       __IOM uint32_t DSP1INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27610             uint32_t            : 31;
27611     } DSP1IERSTAT_b;
27612   } ;
27613 
27614   union {
27615     __IOM uint32_t DSP1IERCLR;                  /*!< (@ 0x00000228) Write a 1 to a bit in this register to clear
27616                                                                     the interrupt status associated with that
27617                                                                     bit.                                                       */
27618 
27619     struct {
27620       __IOM uint32_t DSP1INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27621             uint32_t            : 31;
27622     } DSP1IERCLR_b;
27623   } ;
27624 
27625   union {
27626     __IOM uint32_t DSP1IERSET;                  /*!< (@ 0x0000022C) Write a 1 to a bit in this register to instantly
27627                                                                     generate an interrupt from this module.
27628                                                                     (Generally used for testing purposes).                     */
27629 
27630     struct {
27631       __IOM uint32_t DSP1INT    : 1;            /*!< [0..0] DSP0 Watchdog Timer Interrupt.                                     */
27632             uint32_t            : 31;
27633     } DSP1IERSET_b;
27634   } ;
27635 } WDT_Type;                                     /*!< Size = 560 (0x230)                                                        */
27636 
27637 
27638 /** @} */ /* End of group Device_Peripheral_peripherals */
27639 
27640 
27641 /* =========================================================================================================================== */
27642 /* ================                          Device Specific Peripheral Address Map                           ================ */
27643 /* =========================================================================================================================== */
27644 
27645 
27646 /** @addtogroup Device_Peripheral_peripheralAddr
27647   * @{
27648   */
27649 
27650 #define ADC_BASE                    0x40038000UL
27651 #define APBDMA_BASE                 0x40011000UL
27652 #define AUDADC_BASE                 0x40210000UL
27653 #define CLKGEN_BASE                 0x40004000UL
27654 #define CPU_BASE                    0x48000000UL
27655 #define CRYPTO_BASE                 0x400C0000UL
27656 #define DC_BASE                     0x400A0000UL
27657 #define DSI_BASE                    0x400A8000UL
27658 #define DSP_BASE                    0x40100000UL
27659 #define FPIO_BASE                   0x48001000UL
27660 #define GPIO_BASE                   0x40010000UL
27661 #define GPU_BASE                    0x40090000UL
27662 #define I2S0_BASE                   0x40208000UL
27663 #define I2S1_BASE                   0x40209000UL
27664 #define IOM0_BASE                   0x40050000UL
27665 #define IOM1_BASE                   0x40051000UL
27666 #define IOM2_BASE                   0x40052000UL
27667 #define IOM3_BASE                   0x40053000UL
27668 #define IOM4_BASE                   0x40054000UL
27669 #define IOM5_BASE                   0x40055000UL
27670 #define IOM6_BASE                   0x40056000UL
27671 #define IOM7_BASE                   0x40057000UL
27672 #define IOSLAVE_BASE                0x40034000UL
27673 #define MCUCTRL_BASE                0x40020000UL
27674 #define MSPI0_BASE                  0x40060000UL
27675 #define MSPI1_BASE                  0x40061000UL
27676 #define MSPI2_BASE                  0x40062000UL
27677 #define PDM0_BASE                   0x40201000UL
27678 #define PDM1_BASE                   0x40202000UL
27679 #define PDM2_BASE                   0x40203000UL
27680 #define PDM3_BASE                   0x40204000UL
27681 #define PWRCTRL_BASE                0x40021000UL
27682 #define RSTGEN_BASE                 0x40000000UL
27683 #define RTC_BASE                    0x40004800UL
27684 #define SDIO_BASE                   0x40070000UL
27685 #define SECURITY_BASE               0x40030000UL
27686 #define STIMER_BASE                 0x40008800UL
27687 #define TIMER_BASE                  0x40008000UL
27688 #define UART0_BASE                  0x4001C000UL
27689 #define UART1_BASE                  0x4001D000UL
27690 #define UART2_BASE                  0x4001E000UL
27691 #define UART3_BASE                  0x4001F000UL
27692 #define USBPHY_BASE                 0x400B4000UL
27693 #define USB_BASE                    0x400B0000UL
27694 #define VCOMP_BASE                  0x4000C000UL
27695 #define WDT_BASE                    0x40024000UL
27696 
27697 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
27698 
27699 
27700 /* =========================================================================================================================== */
27701 /* ================                                  Peripheral declaration                                   ================ */
27702 /* =========================================================================================================================== */
27703 
27704 
27705 /** @addtogroup Device_Peripheral_declaration
27706   * @{
27707   */
27708 
27709 #define ADC                         ((ADC_Type*)               ADC_BASE)
27710 #define APBDMA                      ((APBDMA_Type*)            APBDMA_BASE)
27711 #define AUDADC                      ((AUDADC_Type*)            AUDADC_BASE)
27712 #define CLKGEN                      ((CLKGEN_Type*)            CLKGEN_BASE)
27713 #define CPU                         ((CPU_Type*)               CPU_BASE)
27714 #define CRYPTO                      ((CRYPTO_Type*)            CRYPTO_BASE)
27715 #define DC                          ((DC_Type*)                DC_BASE)
27716 #define DSI                         ((DSI_Type*)               DSI_BASE)
27717 #define DSP                         ((DSP_Type*)               DSP_BASE)
27718 #define FPIO                        ((FPIO_Type*)              FPIO_BASE)
27719 #define GPIO                        ((GPIO_Type*)              GPIO_BASE)
27720 #define GPU                         ((GPU_Type*)               GPU_BASE)
27721 #define I2S0                        ((I2S0_Type*)              I2S0_BASE)
27722 #define I2S1                        ((I2S0_Type*)              I2S1_BASE)
27723 #define IOM0                        ((IOM0_Type*)              IOM0_BASE)
27724 #define IOM1                        ((IOM0_Type*)              IOM1_BASE)
27725 #define IOM2                        ((IOM0_Type*)              IOM2_BASE)
27726 #define IOM3                        ((IOM0_Type*)              IOM3_BASE)
27727 #define IOM4                        ((IOM0_Type*)              IOM4_BASE)
27728 #define IOM5                        ((IOM0_Type*)              IOM5_BASE)
27729 #define IOM6                        ((IOM0_Type*)              IOM6_BASE)
27730 #define IOM7                        ((IOM0_Type*)              IOM7_BASE)
27731 #define IOSLAVE                     ((IOSLAVE_Type*)           IOSLAVE_BASE)
27732 #define MCUCTRL                     ((MCUCTRL_Type*)           MCUCTRL_BASE)
27733 #define MSPI0                       ((MSPI0_Type*)             MSPI0_BASE)
27734 #define MSPI1                       ((MSPI0_Type*)             MSPI1_BASE)
27735 #define MSPI2                       ((MSPI0_Type*)             MSPI2_BASE)
27736 #define PDM0                        ((PDM0_Type*)              PDM0_BASE)
27737 #define PDM1                        ((PDM0_Type*)              PDM1_BASE)
27738 #define PDM2                        ((PDM0_Type*)              PDM2_BASE)
27739 #define PDM3                        ((PDM0_Type*)              PDM3_BASE)
27740 #define PWRCTRL                     ((PWRCTRL_Type*)           PWRCTRL_BASE)
27741 #define RSTGEN                      ((RSTGEN_Type*)            RSTGEN_BASE)
27742 #define RTC                         ((RTC_Type*)               RTC_BASE)
27743 #define SDIO                        ((SDIO_Type*)              SDIO_BASE)
27744 #define SECURITY                    ((SECURITY_Type*)          SECURITY_BASE)
27745 #define STIMER                      ((STIMER_Type*)            STIMER_BASE)
27746 #define TIMER                       ((TIMER_Type*)             TIMER_BASE)
27747 #define UART0                       ((UART0_Type*)             UART0_BASE)
27748 #define UART1                       ((UART0_Type*)             UART1_BASE)
27749 #define UART2                       ((UART0_Type*)             UART2_BASE)
27750 #define UART3                       ((UART0_Type*)             UART3_BASE)
27751 #define USBPHY                      ((USBPHY_Type*)            USBPHY_BASE)
27752 #define USB                         ((USB_Type*)               USB_BASE)
27753 #define VCOMP                       ((VCOMP_Type*)             VCOMP_BASE)
27754 #define WDT                         ((WDT_Type*)               WDT_BASE)
27755 
27756 /** @} */ /* End of group Device_Peripheral_declaration */
27757 
27758 
27759 /* =========================================  End of section using anonymous unions  ========================================= */
27760 #if defined (__CC_ARM)
27761   #pragma pop
27762 #elif defined (__ICCARM__)
27763   /* leave anonymous unions enabled */
27764 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
27765   #pragma clang diagnostic pop
27766 #elif defined (__GNUC__)
27767   /* anonymous unions are enabled by default */
27768 #elif defined (__TMS470__)
27769   /* anonymous unions are enabled by default */
27770 #elif defined (__TASKING__)
27771   #pragma warning restore
27772 #elif defined (__CSMC__)
27773   /* anonymous unions are enabled by default */
27774 #endif
27775 
27776 
27777 /* =========================================================================================================================== */
27778 /* ================                                Pos/Mask Peripheral Section                                ================ */
27779 /* =========================================================================================================================== */
27780 
27781 
27782 /** @addtogroup PosMask_peripherals
27783   * @{
27784   */
27785 
27786 
27787 
27788 /* =========================================================================================================================== */
27789 /* ================                                            ADC                                            ================ */
27790 /* =========================================================================================================================== */
27791 
27792 /* ==========================================================  CFG  ========================================================== */
27793 #define ADC_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
27794 #define ADC_CFG_CLKSEL_Msk                (0x3000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
27795 #define ADC_CFG_RPTTRIGSEL_Pos            (20UL)                    /*!< RPTTRIGSEL (Bit 20)                                   */
27796 #define ADC_CFG_RPTTRIGSEL_Msk            (0x100000UL)              /*!< RPTTRIGSEL (Bitfield-Mask: 0x01)                      */
27797 #define ADC_CFG_TRIGPOL_Pos               (19UL)                    /*!< TRIGPOL (Bit 19)                                      */
27798 #define ADC_CFG_TRIGPOL_Msk               (0x80000UL)               /*!< TRIGPOL (Bitfield-Mask: 0x01)                         */
27799 #define ADC_CFG_TRIGSEL_Pos               (16UL)                    /*!< TRIGSEL (Bit 16)                                      */
27800 #define ADC_CFG_TRIGSEL_Msk               (0x70000UL)               /*!< TRIGSEL (Bitfield-Mask: 0x07)                         */
27801 #define ADC_CFG_DFIFORDEN_Pos             (12UL)                    /*!< DFIFORDEN (Bit 12)                                    */
27802 #define ADC_CFG_DFIFORDEN_Msk             (0x1000UL)                /*!< DFIFORDEN (Bitfield-Mask: 0x01)                       */
27803 #define ADC_CFG_CKMODE_Pos                (4UL)                     /*!< CKMODE (Bit 4)                                        */
27804 #define ADC_CFG_CKMODE_Msk                (0x10UL)                  /*!< CKMODE (Bitfield-Mask: 0x01)                          */
27805 #define ADC_CFG_LPMODE_Pos                (3UL)                     /*!< LPMODE (Bit 3)                                        */
27806 #define ADC_CFG_LPMODE_Msk                (0x8UL)                   /*!< LPMODE (Bitfield-Mask: 0x01)                          */
27807 #define ADC_CFG_RPTEN_Pos                 (2UL)                     /*!< RPTEN (Bit 2)                                         */
27808 #define ADC_CFG_RPTEN_Msk                 (0x4UL)                   /*!< RPTEN (Bitfield-Mask: 0x01)                           */
27809 #define ADC_CFG_ADCEN_Pos                 (0UL)                     /*!< ADCEN (Bit 0)                                         */
27810 #define ADC_CFG_ADCEN_Msk                 (0x1UL)                   /*!< ADCEN (Bitfield-Mask: 0x01)                           */
27811 /* =========================================================  STAT  ========================================================== */
27812 #define ADC_STAT_PWDSTAT_Pos              (0UL)                     /*!< PWDSTAT (Bit 0)                                       */
27813 #define ADC_STAT_PWDSTAT_Msk              (0x1UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
27814 /* ==========================================================  SWT  ========================================================== */
27815 #define ADC_SWT_SWT_Pos                   (0UL)                     /*!< SWT (Bit 0)                                           */
27816 #define ADC_SWT_SWT_Msk                   (0xffUL)                  /*!< SWT (Bitfield-Mask: 0xff)                             */
27817 /* ========================================================  SL0CFG  ========================================================= */
27818 #define ADC_SL0CFG_ADSEL0_Pos             (24UL)                    /*!< ADSEL0 (Bit 24)                                       */
27819 #define ADC_SL0CFG_ADSEL0_Msk             (0x7000000UL)             /*!< ADSEL0 (Bitfield-Mask: 0x07)                          */
27820 #define ADC_SL0CFG_TRKCYC0_Pos            (18UL)                    /*!< TRKCYC0 (Bit 18)                                      */
27821 #define ADC_SL0CFG_TRKCYC0_Msk            (0xfc0000UL)              /*!< TRKCYC0 (Bitfield-Mask: 0x3f)                         */
27822 #define ADC_SL0CFG_PRMODE0_Pos            (16UL)                    /*!< PRMODE0 (Bit 16)                                      */
27823 #define ADC_SL0CFG_PRMODE0_Msk            (0x30000UL)               /*!< PRMODE0 (Bitfield-Mask: 0x03)                         */
27824 #define ADC_SL0CFG_CHSEL0_Pos             (8UL)                     /*!< CHSEL0 (Bit 8)                                        */
27825 #define ADC_SL0CFG_CHSEL0_Msk             (0xf00UL)                 /*!< CHSEL0 (Bitfield-Mask: 0x0f)                          */
27826 #define ADC_SL0CFG_WCEN0_Pos              (1UL)                     /*!< WCEN0 (Bit 1)                                         */
27827 #define ADC_SL0CFG_WCEN0_Msk              (0x2UL)                   /*!< WCEN0 (Bitfield-Mask: 0x01)                           */
27828 #define ADC_SL0CFG_SLEN0_Pos              (0UL)                     /*!< SLEN0 (Bit 0)                                         */
27829 #define ADC_SL0CFG_SLEN0_Msk              (0x1UL)                   /*!< SLEN0 (Bitfield-Mask: 0x01)                           */
27830 /* ========================================================  SL1CFG  ========================================================= */
27831 #define ADC_SL1CFG_ADSEL1_Pos             (24UL)                    /*!< ADSEL1 (Bit 24)                                       */
27832 #define ADC_SL1CFG_ADSEL1_Msk             (0x7000000UL)             /*!< ADSEL1 (Bitfield-Mask: 0x07)                          */
27833 #define ADC_SL1CFG_TRKCYC1_Pos            (18UL)                    /*!< TRKCYC1 (Bit 18)                                      */
27834 #define ADC_SL1CFG_TRKCYC1_Msk            (0xfc0000UL)              /*!< TRKCYC1 (Bitfield-Mask: 0x3f)                         */
27835 #define ADC_SL1CFG_PRMODE1_Pos            (16UL)                    /*!< PRMODE1 (Bit 16)                                      */
27836 #define ADC_SL1CFG_PRMODE1_Msk            (0x30000UL)               /*!< PRMODE1 (Bitfield-Mask: 0x03)                         */
27837 #define ADC_SL1CFG_CHSEL1_Pos             (8UL)                     /*!< CHSEL1 (Bit 8)                                        */
27838 #define ADC_SL1CFG_CHSEL1_Msk             (0xf00UL)                 /*!< CHSEL1 (Bitfield-Mask: 0x0f)                          */
27839 #define ADC_SL1CFG_WCEN1_Pos              (1UL)                     /*!< WCEN1 (Bit 1)                                         */
27840 #define ADC_SL1CFG_WCEN1_Msk              (0x2UL)                   /*!< WCEN1 (Bitfield-Mask: 0x01)                           */
27841 #define ADC_SL1CFG_SLEN1_Pos              (0UL)                     /*!< SLEN1 (Bit 0)                                         */
27842 #define ADC_SL1CFG_SLEN1_Msk              (0x1UL)                   /*!< SLEN1 (Bitfield-Mask: 0x01)                           */
27843 /* ========================================================  SL2CFG  ========================================================= */
27844 #define ADC_SL2CFG_ADSEL2_Pos             (24UL)                    /*!< ADSEL2 (Bit 24)                                       */
27845 #define ADC_SL2CFG_ADSEL2_Msk             (0x7000000UL)             /*!< ADSEL2 (Bitfield-Mask: 0x07)                          */
27846 #define ADC_SL2CFG_TRKCYC2_Pos            (18UL)                    /*!< TRKCYC2 (Bit 18)                                      */
27847 #define ADC_SL2CFG_TRKCYC2_Msk            (0xfc0000UL)              /*!< TRKCYC2 (Bitfield-Mask: 0x3f)                         */
27848 #define ADC_SL2CFG_PRMODE2_Pos            (16UL)                    /*!< PRMODE2 (Bit 16)                                      */
27849 #define ADC_SL2CFG_PRMODE2_Msk            (0x30000UL)               /*!< PRMODE2 (Bitfield-Mask: 0x03)                         */
27850 #define ADC_SL2CFG_CHSEL2_Pos             (8UL)                     /*!< CHSEL2 (Bit 8)                                        */
27851 #define ADC_SL2CFG_CHSEL2_Msk             (0xf00UL)                 /*!< CHSEL2 (Bitfield-Mask: 0x0f)                          */
27852 #define ADC_SL2CFG_WCEN2_Pos              (1UL)                     /*!< WCEN2 (Bit 1)                                         */
27853 #define ADC_SL2CFG_WCEN2_Msk              (0x2UL)                   /*!< WCEN2 (Bitfield-Mask: 0x01)                           */
27854 #define ADC_SL2CFG_SLEN2_Pos              (0UL)                     /*!< SLEN2 (Bit 0)                                         */
27855 #define ADC_SL2CFG_SLEN2_Msk              (0x1UL)                   /*!< SLEN2 (Bitfield-Mask: 0x01)                           */
27856 /* ========================================================  SL3CFG  ========================================================= */
27857 #define ADC_SL3CFG_ADSEL3_Pos             (24UL)                    /*!< ADSEL3 (Bit 24)                                       */
27858 #define ADC_SL3CFG_ADSEL3_Msk             (0x7000000UL)             /*!< ADSEL3 (Bitfield-Mask: 0x07)                          */
27859 #define ADC_SL3CFG_TRKCYC3_Pos            (18UL)                    /*!< TRKCYC3 (Bit 18)                                      */
27860 #define ADC_SL3CFG_TRKCYC3_Msk            (0xfc0000UL)              /*!< TRKCYC3 (Bitfield-Mask: 0x3f)                         */
27861 #define ADC_SL3CFG_PRMODE3_Pos            (16UL)                    /*!< PRMODE3 (Bit 16)                                      */
27862 #define ADC_SL3CFG_PRMODE3_Msk            (0x30000UL)               /*!< PRMODE3 (Bitfield-Mask: 0x03)                         */
27863 #define ADC_SL3CFG_CHSEL3_Pos             (8UL)                     /*!< CHSEL3 (Bit 8)                                        */
27864 #define ADC_SL3CFG_CHSEL3_Msk             (0xf00UL)                 /*!< CHSEL3 (Bitfield-Mask: 0x0f)                          */
27865 #define ADC_SL3CFG_WCEN3_Pos              (1UL)                     /*!< WCEN3 (Bit 1)                                         */
27866 #define ADC_SL3CFG_WCEN3_Msk              (0x2UL)                   /*!< WCEN3 (Bitfield-Mask: 0x01)                           */
27867 #define ADC_SL3CFG_SLEN3_Pos              (0UL)                     /*!< SLEN3 (Bit 0)                                         */
27868 #define ADC_SL3CFG_SLEN3_Msk              (0x1UL)                   /*!< SLEN3 (Bitfield-Mask: 0x01)                           */
27869 /* ========================================================  SL4CFG  ========================================================= */
27870 #define ADC_SL4CFG_ADSEL4_Pos             (24UL)                    /*!< ADSEL4 (Bit 24)                                       */
27871 #define ADC_SL4CFG_ADSEL4_Msk             (0x7000000UL)             /*!< ADSEL4 (Bitfield-Mask: 0x07)                          */
27872 #define ADC_SL4CFG_TRKCYC4_Pos            (18UL)                    /*!< TRKCYC4 (Bit 18)                                      */
27873 #define ADC_SL4CFG_TRKCYC4_Msk            (0xfc0000UL)              /*!< TRKCYC4 (Bitfield-Mask: 0x3f)                         */
27874 #define ADC_SL4CFG_PRMODE4_Pos            (16UL)                    /*!< PRMODE4 (Bit 16)                                      */
27875 #define ADC_SL4CFG_PRMODE4_Msk            (0x30000UL)               /*!< PRMODE4 (Bitfield-Mask: 0x03)                         */
27876 #define ADC_SL4CFG_CHSEL4_Pos             (8UL)                     /*!< CHSEL4 (Bit 8)                                        */
27877 #define ADC_SL4CFG_CHSEL4_Msk             (0xf00UL)                 /*!< CHSEL4 (Bitfield-Mask: 0x0f)                          */
27878 #define ADC_SL4CFG_WCEN4_Pos              (1UL)                     /*!< WCEN4 (Bit 1)                                         */
27879 #define ADC_SL4CFG_WCEN4_Msk              (0x2UL)                   /*!< WCEN4 (Bitfield-Mask: 0x01)                           */
27880 #define ADC_SL4CFG_SLEN4_Pos              (0UL)                     /*!< SLEN4 (Bit 0)                                         */
27881 #define ADC_SL4CFG_SLEN4_Msk              (0x1UL)                   /*!< SLEN4 (Bitfield-Mask: 0x01)                           */
27882 /* ========================================================  SL5CFG  ========================================================= */
27883 #define ADC_SL5CFG_ADSEL5_Pos             (24UL)                    /*!< ADSEL5 (Bit 24)                                       */
27884 #define ADC_SL5CFG_ADSEL5_Msk             (0x7000000UL)             /*!< ADSEL5 (Bitfield-Mask: 0x07)                          */
27885 #define ADC_SL5CFG_TRKCYC5_Pos            (18UL)                    /*!< TRKCYC5 (Bit 18)                                      */
27886 #define ADC_SL5CFG_TRKCYC5_Msk            (0xfc0000UL)              /*!< TRKCYC5 (Bitfield-Mask: 0x3f)                         */
27887 #define ADC_SL5CFG_PRMODE5_Pos            (16UL)                    /*!< PRMODE5 (Bit 16)                                      */
27888 #define ADC_SL5CFG_PRMODE5_Msk            (0x30000UL)               /*!< PRMODE5 (Bitfield-Mask: 0x03)                         */
27889 #define ADC_SL5CFG_CHSEL5_Pos             (8UL)                     /*!< CHSEL5 (Bit 8)                                        */
27890 #define ADC_SL5CFG_CHSEL5_Msk             (0xf00UL)                 /*!< CHSEL5 (Bitfield-Mask: 0x0f)                          */
27891 #define ADC_SL5CFG_WCEN5_Pos              (1UL)                     /*!< WCEN5 (Bit 1)                                         */
27892 #define ADC_SL5CFG_WCEN5_Msk              (0x2UL)                   /*!< WCEN5 (Bitfield-Mask: 0x01)                           */
27893 #define ADC_SL5CFG_SLEN5_Pos              (0UL)                     /*!< SLEN5 (Bit 0)                                         */
27894 #define ADC_SL5CFG_SLEN5_Msk              (0x1UL)                   /*!< SLEN5 (Bitfield-Mask: 0x01)                           */
27895 /* ========================================================  SL6CFG  ========================================================= */
27896 #define ADC_SL6CFG_ADSEL6_Pos             (24UL)                    /*!< ADSEL6 (Bit 24)                                       */
27897 #define ADC_SL6CFG_ADSEL6_Msk             (0x7000000UL)             /*!< ADSEL6 (Bitfield-Mask: 0x07)                          */
27898 #define ADC_SL6CFG_TRKCYC6_Pos            (18UL)                    /*!< TRKCYC6 (Bit 18)                                      */
27899 #define ADC_SL6CFG_TRKCYC6_Msk            (0xfc0000UL)              /*!< TRKCYC6 (Bitfield-Mask: 0x3f)                         */
27900 #define ADC_SL6CFG_PRMODE6_Pos            (16UL)                    /*!< PRMODE6 (Bit 16)                                      */
27901 #define ADC_SL6CFG_PRMODE6_Msk            (0x30000UL)               /*!< PRMODE6 (Bitfield-Mask: 0x03)                         */
27902 #define ADC_SL6CFG_CHSEL6_Pos             (8UL)                     /*!< CHSEL6 (Bit 8)                                        */
27903 #define ADC_SL6CFG_CHSEL6_Msk             (0xf00UL)                 /*!< CHSEL6 (Bitfield-Mask: 0x0f)                          */
27904 #define ADC_SL6CFG_WCEN6_Pos              (1UL)                     /*!< WCEN6 (Bit 1)                                         */
27905 #define ADC_SL6CFG_WCEN6_Msk              (0x2UL)                   /*!< WCEN6 (Bitfield-Mask: 0x01)                           */
27906 #define ADC_SL6CFG_SLEN6_Pos              (0UL)                     /*!< SLEN6 (Bit 0)                                         */
27907 #define ADC_SL6CFG_SLEN6_Msk              (0x1UL)                   /*!< SLEN6 (Bitfield-Mask: 0x01)                           */
27908 /* ========================================================  SL7CFG  ========================================================= */
27909 #define ADC_SL7CFG_ADSEL7_Pos             (24UL)                    /*!< ADSEL7 (Bit 24)                                       */
27910 #define ADC_SL7CFG_ADSEL7_Msk             (0x7000000UL)             /*!< ADSEL7 (Bitfield-Mask: 0x07)                          */
27911 #define ADC_SL7CFG_TRKCYC7_Pos            (18UL)                    /*!< TRKCYC7 (Bit 18)                                      */
27912 #define ADC_SL7CFG_TRKCYC7_Msk            (0xfc0000UL)              /*!< TRKCYC7 (Bitfield-Mask: 0x3f)                         */
27913 #define ADC_SL7CFG_PRMODE7_Pos            (16UL)                    /*!< PRMODE7 (Bit 16)                                      */
27914 #define ADC_SL7CFG_PRMODE7_Msk            (0x30000UL)               /*!< PRMODE7 (Bitfield-Mask: 0x03)                         */
27915 #define ADC_SL7CFG_CHSEL7_Pos             (8UL)                     /*!< CHSEL7 (Bit 8)                                        */
27916 #define ADC_SL7CFG_CHSEL7_Msk             (0xf00UL)                 /*!< CHSEL7 (Bitfield-Mask: 0x0f)                          */
27917 #define ADC_SL7CFG_WCEN7_Pos              (1UL)                     /*!< WCEN7 (Bit 1)                                         */
27918 #define ADC_SL7CFG_WCEN7_Msk              (0x2UL)                   /*!< WCEN7 (Bitfield-Mask: 0x01)                           */
27919 #define ADC_SL7CFG_SLEN7_Pos              (0UL)                     /*!< SLEN7 (Bit 0)                                         */
27920 #define ADC_SL7CFG_SLEN7_Msk              (0x1UL)                   /*!< SLEN7 (Bitfield-Mask: 0x01)                           */
27921 /* =========================================================  WULIM  ========================================================= */
27922 #define ADC_WULIM_ULIM_Pos                (0UL)                     /*!< ULIM (Bit 0)                                          */
27923 #define ADC_WULIM_ULIM_Msk                (0xfffffUL)               /*!< ULIM (Bitfield-Mask: 0xfffff)                         */
27924 /* =========================================================  WLLIM  ========================================================= */
27925 #define ADC_WLLIM_LLIM_Pos                (0UL)                     /*!< LLIM (Bit 0)                                          */
27926 #define ADC_WLLIM_LLIM_Msk                (0xfffffUL)               /*!< LLIM (Bitfield-Mask: 0xfffff)                         */
27927 /* ========================================================  SCWLIM  ========================================================= */
27928 #define ADC_SCWLIM_SCWLIMEN_Pos           (0UL)                     /*!< SCWLIMEN (Bit 0)                                      */
27929 #define ADC_SCWLIM_SCWLIMEN_Msk           (0x1UL)                   /*!< SCWLIMEN (Bitfield-Mask: 0x01)                        */
27930 /* =========================================================  FIFO  ========================================================== */
27931 #define ADC_FIFO_RSVD_Pos                 (31UL)                    /*!< RSVD (Bit 31)                                         */
27932 #define ADC_FIFO_RSVD_Msk                 (0x80000000UL)            /*!< RSVD (Bitfield-Mask: 0x01)                            */
27933 #define ADC_FIFO_SLOTNUM_Pos              (28UL)                    /*!< SLOTNUM (Bit 28)                                      */
27934 #define ADC_FIFO_SLOTNUM_Msk              (0x70000000UL)            /*!< SLOTNUM (Bitfield-Mask: 0x07)                         */
27935 #define ADC_FIFO_COUNT_Pos                (20UL)                    /*!< COUNT (Bit 20)                                        */
27936 #define ADC_FIFO_COUNT_Msk                (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
27937 #define ADC_FIFO_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
27938 #define ADC_FIFO_DATA_Msk                 (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
27939 /* ========================================================  FIFOPR  ========================================================= */
27940 #define ADC_FIFOPR_RSVDPR_Pos             (31UL)                    /*!< RSVDPR (Bit 31)                                       */
27941 #define ADC_FIFOPR_RSVDPR_Msk             (0x80000000UL)            /*!< RSVDPR (Bitfield-Mask: 0x01)                          */
27942 #define ADC_FIFOPR_SLOTNUMPR_Pos          (28UL)                    /*!< SLOTNUMPR (Bit 28)                                    */
27943 #define ADC_FIFOPR_SLOTNUMPR_Msk          (0x70000000UL)            /*!< SLOTNUMPR (Bitfield-Mask: 0x07)                       */
27944 #define ADC_FIFOPR_COUNT_Pos              (20UL)                    /*!< COUNT (Bit 20)                                        */
27945 #define ADC_FIFOPR_COUNT_Msk              (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
27946 #define ADC_FIFOPR_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
27947 #define ADC_FIFOPR_DATA_Msk               (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
27948 /* =====================================================  INTTRIGTIMER  ====================================================== */
27949 #define ADC_INTTRIGTIMER_TIMEREN_Pos      (31UL)                    /*!< TIMEREN (Bit 31)                                      */
27950 #define ADC_INTTRIGTIMER_TIMEREN_Msk      (0x80000000UL)            /*!< TIMEREN (Bitfield-Mask: 0x01)                         */
27951 #define ADC_INTTRIGTIMER_CLKDIV_Pos       (16UL)                    /*!< CLKDIV (Bit 16)                                       */
27952 #define ADC_INTTRIGTIMER_CLKDIV_Msk       (0x70000UL)               /*!< CLKDIV (Bitfield-Mask: 0x07)                          */
27953 #define ADC_INTTRIGTIMER_TIMERMAX_Pos     (0UL)                     /*!< TIMERMAX (Bit 0)                                      */
27954 #define ADC_INTTRIGTIMER_TIMERMAX_Msk     (0x3ffUL)                 /*!< TIMERMAX (Bitfield-Mask: 0x3ff)                       */
27955 /* =========================================================  ZXCFG  ========================================================= */
27956 #define ADC_ZXCFG_ZXCHANSEL_Pos           (4UL)                     /*!< ZXCHANSEL (Bit 4)                                     */
27957 #define ADC_ZXCFG_ZXCHANSEL_Msk           (0x10UL)                  /*!< ZXCHANSEL (Bitfield-Mask: 0x01)                       */
27958 #define ADC_ZXCFG_ZXEN_Pos                (0UL)                     /*!< ZXEN (Bit 0)                                          */
27959 #define ADC_ZXCFG_ZXEN_Msk                (0x1UL)                   /*!< ZXEN (Bitfield-Mask: 0x01)                            */
27960 /* =========================================================  ZXLIM  ========================================================= */
27961 #define ADC_ZXLIM_UZXC_Pos                (16UL)                    /*!< UZXC (Bit 16)                                         */
27962 #define ADC_ZXLIM_UZXC_Msk                (0xfff0000UL)             /*!< UZXC (Bitfield-Mask: 0xfff)                           */
27963 #define ADC_ZXLIM_LZXC_Pos                (0UL)                     /*!< LZXC (Bit 0)                                          */
27964 #define ADC_ZXLIM_LZXC_Msk                (0xfffUL)                 /*!< LZXC (Bitfield-Mask: 0xfff)                           */
27965 /* ========================================================  GAINCFG  ======================================================== */
27966 #define ADC_GAINCFG_UPDATEMODE_Pos        (4UL)                     /*!< UPDATEMODE (Bit 4)                                    */
27967 #define ADC_GAINCFG_UPDATEMODE_Msk        (0x10UL)                  /*!< UPDATEMODE (Bitfield-Mask: 0x01)                      */
27968 #define ADC_GAINCFG_PGACTRLEN_Pos         (0UL)                     /*!< PGACTRLEN (Bit 0)                                     */
27969 #define ADC_GAINCFG_PGACTRLEN_Msk         (0x1UL)                   /*!< PGACTRLEN (Bitfield-Mask: 0x01)                       */
27970 /* =========================================================  GAIN  ========================================================== */
27971 #define ADC_GAIN_HGBDELTA_Pos             (24UL)                    /*!< HGBDELTA (Bit 24)                                     */
27972 #define ADC_GAIN_HGBDELTA_Msk             (0x7f000000UL)            /*!< HGBDELTA (Bitfield-Mask: 0x7f)                        */
27973 #define ADC_GAIN_LGB_Pos                  (16UL)                    /*!< LGB (Bit 16)                                          */
27974 #define ADC_GAIN_LGB_Msk                  (0x7f0000UL)              /*!< LGB (Bitfield-Mask: 0x7f)                             */
27975 #define ADC_GAIN_HGADELTA_Pos             (8UL)                     /*!< HGADELTA (Bit 8)                                      */
27976 #define ADC_GAIN_HGADELTA_Msk             (0x7f00UL)                /*!< HGADELTA (Bitfield-Mask: 0x7f)                        */
27977 #define ADC_GAIN_LGA_Pos                  (0UL)                     /*!< LGA (Bit 0)                                           */
27978 #define ADC_GAIN_LGA_Msk                  (0x7fUL)                  /*!< LGA (Bitfield-Mask: 0x7f)                             */
27979 /* ========================================================  SATCFG  ========================================================= */
27980 #define ADC_SATCFG_SATCHANSEL_Pos         (4UL)                     /*!< SATCHANSEL (Bit 4)                                    */
27981 #define ADC_SATCFG_SATCHANSEL_Msk         (0x10UL)                  /*!< SATCHANSEL (Bitfield-Mask: 0x01)                      */
27982 #define ADC_SATCFG_SATEN_Pos              (0UL)                     /*!< SATEN (Bit 0)                                         */
27983 #define ADC_SATCFG_SATEN_Msk              (0x1UL)                   /*!< SATEN (Bitfield-Mask: 0x01)                           */
27984 /* ========================================================  SATLIM  ========================================================= */
27985 #define ADC_SATLIM_USATC_Pos              (16UL)                    /*!< USATC (Bit 16)                                        */
27986 #define ADC_SATLIM_USATC_Msk              (0xfff0000UL)             /*!< USATC (Bitfield-Mask: 0xfff)                          */
27987 #define ADC_SATLIM_LSATC_Pos              (0UL)                     /*!< LSATC (Bit 0)                                         */
27988 #define ADC_SATLIM_LSATC_Msk              (0xfffUL)                 /*!< LSATC (Bitfield-Mask: 0xfff)                          */
27989 /* ========================================================  SATMAX  ========================================================= */
27990 #define ADC_SATMAX_SATCBMAX_Pos           (16UL)                    /*!< SATCBMAX (Bit 16)                                     */
27991 #define ADC_SATMAX_SATCBMAX_Msk           (0xfff0000UL)             /*!< SATCBMAX (Bitfield-Mask: 0xfff)                       */
27992 #define ADC_SATMAX_SATCAMAX_Pos           (0UL)                     /*!< SATCAMAX (Bit 0)                                      */
27993 #define ADC_SATMAX_SATCAMAX_Msk           (0xfffUL)                 /*!< SATCAMAX (Bitfield-Mask: 0xfff)                       */
27994 /* ========================================================  SATCLR  ========================================================= */
27995 #define ADC_SATCLR_SATCBCLR_Pos           (1UL)                     /*!< SATCBCLR (Bit 1)                                      */
27996 #define ADC_SATCLR_SATCBCLR_Msk           (0x2UL)                   /*!< SATCBCLR (Bitfield-Mask: 0x01)                        */
27997 #define ADC_SATCLR_SATCACLR_Pos           (0UL)                     /*!< SATCACLR (Bit 0)                                      */
27998 #define ADC_SATCLR_SATCACLR_Msk           (0x1UL)                   /*!< SATCACLR (Bitfield-Mask: 0x01)                        */
27999 /* =========================================================  INTEN  ========================================================= */
28000 #define ADC_INTEN_SATCB_Pos               (11UL)                    /*!< SATCB (Bit 11)                                        */
28001 #define ADC_INTEN_SATCB_Msk               (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
28002 #define ADC_INTEN_SATCA_Pos               (10UL)                    /*!< SATCA (Bit 10)                                        */
28003 #define ADC_INTEN_SATCA_Msk               (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
28004 #define ADC_INTEN_ZXCB_Pos                (9UL)                     /*!< ZXCB (Bit 9)                                          */
28005 #define ADC_INTEN_ZXCB_Msk                (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
28006 #define ADC_INTEN_ZXCA_Pos                (8UL)                     /*!< ZXCA (Bit 8)                                          */
28007 #define ADC_INTEN_ZXCA_Msk                (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
28008 #define ADC_INTEN_DERR_Pos                (7UL)                     /*!< DERR (Bit 7)                                          */
28009 #define ADC_INTEN_DERR_Msk                (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
28010 #define ADC_INTEN_DCMP_Pos                (6UL)                     /*!< DCMP (Bit 6)                                          */
28011 #define ADC_INTEN_DCMP_Msk                (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
28012 #define ADC_INTEN_WCINC_Pos               (5UL)                     /*!< WCINC (Bit 5)                                         */
28013 #define ADC_INTEN_WCINC_Msk               (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
28014 #define ADC_INTEN_WCEXC_Pos               (4UL)                     /*!< WCEXC (Bit 4)                                         */
28015 #define ADC_INTEN_WCEXC_Msk               (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
28016 #define ADC_INTEN_FIFOOVR2_Pos            (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
28017 #define ADC_INTEN_FIFOOVR2_Msk            (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
28018 #define ADC_INTEN_FIFOOVR1_Pos            (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
28019 #define ADC_INTEN_FIFOOVR1_Msk            (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
28020 #define ADC_INTEN_SCNCMP_Pos              (1UL)                     /*!< SCNCMP (Bit 1)                                        */
28021 #define ADC_INTEN_SCNCMP_Msk              (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
28022 #define ADC_INTEN_CNVCMP_Pos              (0UL)                     /*!< CNVCMP (Bit 0)                                        */
28023 #define ADC_INTEN_CNVCMP_Msk              (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
28024 /* ========================================================  INTSTAT  ======================================================== */
28025 #define ADC_INTSTAT_SATCB_Pos             (11UL)                    /*!< SATCB (Bit 11)                                        */
28026 #define ADC_INTSTAT_SATCB_Msk             (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
28027 #define ADC_INTSTAT_SATCA_Pos             (10UL)                    /*!< SATCA (Bit 10)                                        */
28028 #define ADC_INTSTAT_SATCA_Msk             (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
28029 #define ADC_INTSTAT_ZXCB_Pos              (9UL)                     /*!< ZXCB (Bit 9)                                          */
28030 #define ADC_INTSTAT_ZXCB_Msk              (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
28031 #define ADC_INTSTAT_ZXCA_Pos              (8UL)                     /*!< ZXCA (Bit 8)                                          */
28032 #define ADC_INTSTAT_ZXCA_Msk              (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
28033 #define ADC_INTSTAT_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
28034 #define ADC_INTSTAT_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
28035 #define ADC_INTSTAT_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
28036 #define ADC_INTSTAT_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
28037 #define ADC_INTSTAT_WCINC_Pos             (5UL)                     /*!< WCINC (Bit 5)                                         */
28038 #define ADC_INTSTAT_WCINC_Msk             (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
28039 #define ADC_INTSTAT_WCEXC_Pos             (4UL)                     /*!< WCEXC (Bit 4)                                         */
28040 #define ADC_INTSTAT_WCEXC_Msk             (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
28041 #define ADC_INTSTAT_FIFOOVR2_Pos          (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
28042 #define ADC_INTSTAT_FIFOOVR2_Msk          (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
28043 #define ADC_INTSTAT_FIFOOVR1_Pos          (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
28044 #define ADC_INTSTAT_FIFOOVR1_Msk          (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
28045 #define ADC_INTSTAT_SCNCMP_Pos            (1UL)                     /*!< SCNCMP (Bit 1)                                        */
28046 #define ADC_INTSTAT_SCNCMP_Msk            (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
28047 #define ADC_INTSTAT_CNVCMP_Pos            (0UL)                     /*!< CNVCMP (Bit 0)                                        */
28048 #define ADC_INTSTAT_CNVCMP_Msk            (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
28049 /* ========================================================  INTCLR  ========================================================= */
28050 #define ADC_INTCLR_SATCB_Pos              (11UL)                    /*!< SATCB (Bit 11)                                        */
28051 #define ADC_INTCLR_SATCB_Msk              (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
28052 #define ADC_INTCLR_SATCA_Pos              (10UL)                    /*!< SATCA (Bit 10)                                        */
28053 #define ADC_INTCLR_SATCA_Msk              (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
28054 #define ADC_INTCLR_ZXCB_Pos               (9UL)                     /*!< ZXCB (Bit 9)                                          */
28055 #define ADC_INTCLR_ZXCB_Msk               (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
28056 #define ADC_INTCLR_ZXCA_Pos               (8UL)                     /*!< ZXCA (Bit 8)                                          */
28057 #define ADC_INTCLR_ZXCA_Msk               (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
28058 #define ADC_INTCLR_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
28059 #define ADC_INTCLR_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
28060 #define ADC_INTCLR_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
28061 #define ADC_INTCLR_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
28062 #define ADC_INTCLR_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
28063 #define ADC_INTCLR_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
28064 #define ADC_INTCLR_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
28065 #define ADC_INTCLR_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
28066 #define ADC_INTCLR_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
28067 #define ADC_INTCLR_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
28068 #define ADC_INTCLR_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
28069 #define ADC_INTCLR_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
28070 #define ADC_INTCLR_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
28071 #define ADC_INTCLR_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
28072 #define ADC_INTCLR_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
28073 #define ADC_INTCLR_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
28074 /* ========================================================  INTSET  ========================================================= */
28075 #define ADC_INTSET_SATCB_Pos              (11UL)                    /*!< SATCB (Bit 11)                                        */
28076 #define ADC_INTSET_SATCB_Msk              (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
28077 #define ADC_INTSET_SATCA_Pos              (10UL)                    /*!< SATCA (Bit 10)                                        */
28078 #define ADC_INTSET_SATCA_Msk              (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
28079 #define ADC_INTSET_ZXCB_Pos               (9UL)                     /*!< ZXCB (Bit 9)                                          */
28080 #define ADC_INTSET_ZXCB_Msk               (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
28081 #define ADC_INTSET_ZXCA_Pos               (8UL)                     /*!< ZXCA (Bit 8)                                          */
28082 #define ADC_INTSET_ZXCA_Msk               (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
28083 #define ADC_INTSET_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
28084 #define ADC_INTSET_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
28085 #define ADC_INTSET_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
28086 #define ADC_INTSET_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
28087 #define ADC_INTSET_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
28088 #define ADC_INTSET_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
28089 #define ADC_INTSET_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
28090 #define ADC_INTSET_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
28091 #define ADC_INTSET_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
28092 #define ADC_INTSET_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
28093 #define ADC_INTSET_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
28094 #define ADC_INTSET_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
28095 #define ADC_INTSET_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
28096 #define ADC_INTSET_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
28097 #define ADC_INTSET_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
28098 #define ADC_INTSET_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
28099 /* =======================================================  DMATRIGEN  ======================================================= */
28100 #define ADC_DMATRIGEN_DFIFOFULL_Pos       (1UL)                     /*!< DFIFOFULL (Bit 1)                                     */
28101 #define ADC_DMATRIGEN_DFIFOFULL_Msk       (0x2UL)                   /*!< DFIFOFULL (Bitfield-Mask: 0x01)                       */
28102 #define ADC_DMATRIGEN_DFIFO75_Pos         (0UL)                     /*!< DFIFO75 (Bit 0)                                       */
28103 #define ADC_DMATRIGEN_DFIFO75_Msk         (0x1UL)                   /*!< DFIFO75 (Bitfield-Mask: 0x01)                         */
28104 /* ======================================================  DMATRIGSTAT  ====================================================== */
28105 #define ADC_DMATRIGSTAT_DFULLSTAT_Pos     (1UL)                     /*!< DFULLSTAT (Bit 1)                                     */
28106 #define ADC_DMATRIGSTAT_DFULLSTAT_Msk     (0x2UL)                   /*!< DFULLSTAT (Bitfield-Mask: 0x01)                       */
28107 #define ADC_DMATRIGSTAT_D75STAT_Pos       (0UL)                     /*!< D75STAT (Bit 0)                                       */
28108 #define ADC_DMATRIGSTAT_D75STAT_Msk       (0x1UL)                   /*!< D75STAT (Bitfield-Mask: 0x01)                         */
28109 /* ========================================================  DMACFG  ========================================================= */
28110 #define ADC_DMACFG_DPWROFF_Pos            (18UL)                    /*!< DPWROFF (Bit 18)                                      */
28111 #define ADC_DMACFG_DPWROFF_Msk            (0x40000UL)               /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
28112 #define ADC_DMACFG_DMAMSK_Pos             (17UL)                    /*!< DMAMSK (Bit 17)                                       */
28113 #define ADC_DMACFG_DMAMSK_Msk             (0x20000UL)               /*!< DMAMSK (Bitfield-Mask: 0x01)                          */
28114 #define ADC_DMACFG_DMADYNPRI_Pos          (9UL)                     /*!< DMADYNPRI (Bit 9)                                     */
28115 #define ADC_DMACFG_DMADYNPRI_Msk          (0x200UL)                 /*!< DMADYNPRI (Bitfield-Mask: 0x01)                       */
28116 #define ADC_DMACFG_DMAPRI_Pos             (8UL)                     /*!< DMAPRI (Bit 8)                                        */
28117 #define ADC_DMACFG_DMAPRI_Msk             (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
28118 #define ADC_DMACFG_DMADIR_Pos             (2UL)                     /*!< DMADIR (Bit 2)                                        */
28119 #define ADC_DMACFG_DMADIR_Msk             (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
28120 #define ADC_DMACFG_DMAEN_Pos              (0UL)                     /*!< DMAEN (Bit 0)                                         */
28121 #define ADC_DMACFG_DMAEN_Msk              (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
28122 /* ======================================================  DMATOTCOUNT  ====================================================== */
28123 #define ADC_DMATOTCOUNT_TOTCOUNT_Pos      (2UL)                     /*!< TOTCOUNT (Bit 2)                                      */
28124 #define ADC_DMATOTCOUNT_TOTCOUNT_Msk      (0x3fffcUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xffff)                      */
28125 /* ======================================================  DMATARGADDR  ====================================================== */
28126 #define ADC_DMATARGADDR_UTARGADDR_Pos     (28UL)                    /*!< UTARGADDR (Bit 28)                                    */
28127 #define ADC_DMATARGADDR_UTARGADDR_Msk     (0xf0000000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x0f)                       */
28128 #define ADC_DMATARGADDR_LTARGADDR_Pos     (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
28129 #define ADC_DMATARGADDR_LTARGADDR_Msk     (0xfffffffUL)             /*!< LTARGADDR (Bitfield-Mask: 0xfffffff)                  */
28130 /* ========================================================  DMASTAT  ======================================================== */
28131 #define ADC_DMASTAT_DMAERR_Pos            (2UL)                     /*!< DMAERR (Bit 2)                                        */
28132 #define ADC_DMASTAT_DMAERR_Msk            (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
28133 #define ADC_DMASTAT_DMACPL_Pos            (1UL)                     /*!< DMACPL (Bit 1)                                        */
28134 #define ADC_DMASTAT_DMACPL_Msk            (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
28135 #define ADC_DMASTAT_DMATIP_Pos            (0UL)                     /*!< DMATIP (Bit 0)                                        */
28136 #define ADC_DMASTAT_DMATIP_Msk            (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
28137 
28138 
28139 /* =========================================================================================================================== */
28140 /* ================                                          APBDMA                                           ================ */
28141 /* =========================================================================================================================== */
28142 
28143 /* ========================================================  BBVALUE  ======================================================== */
28144 #define APBDMA_BBVALUE_PIN_Pos            (16UL)                    /*!< PIN (Bit 16)                                          */
28145 #define APBDMA_BBVALUE_PIN_Msk            (0xff0000UL)              /*!< PIN (Bitfield-Mask: 0xff)                             */
28146 #define APBDMA_BBVALUE_DATAOUT_Pos        (0UL)                     /*!< DATAOUT (Bit 0)                                       */
28147 #define APBDMA_BBVALUE_DATAOUT_Msk        (0xffUL)                  /*!< DATAOUT (Bitfield-Mask: 0xff)                         */
28148 /* ======================================================  BBSETCLEAR  ======================================================= */
28149 #define APBDMA_BBSETCLEAR_CLEAR_Pos       (16UL)                    /*!< CLEAR (Bit 16)                                        */
28150 #define APBDMA_BBSETCLEAR_CLEAR_Msk       (0xff0000UL)              /*!< CLEAR (Bitfield-Mask: 0xff)                           */
28151 #define APBDMA_BBSETCLEAR_SET_Pos         (0UL)                     /*!< SET (Bit 0)                                           */
28152 #define APBDMA_BBSETCLEAR_SET_Msk         (0xffUL)                  /*!< SET (Bitfield-Mask: 0xff)                             */
28153 /* ========================================================  BBINPUT  ======================================================== */
28154 #define APBDMA_BBINPUT_DATAIN_Pos         (0UL)                     /*!< DATAIN (Bit 0)                                        */
28155 #define APBDMA_BBINPUT_DATAIN_Msk         (0xffUL)                  /*!< DATAIN (Bitfield-Mask: 0xff)                          */
28156 /* =======================================================  DEBUGDATA  ======================================================= */
28157 #define APBDMA_DEBUGDATA_DEBUGDATA_Pos    (0UL)                     /*!< DEBUGDATA (Bit 0)                                     */
28158 #define APBDMA_DEBUGDATA_DEBUGDATA_Msk    (0xffffffffUL)            /*!< DEBUGDATA (Bitfield-Mask: 0xffffffff)                 */
28159 /* =========================================================  DEBUG  ========================================================= */
28160 #define APBDMA_DEBUG_DEBUGEN_Pos          (0UL)                     /*!< DEBUGEN (Bit 0)                                       */
28161 #define APBDMA_DEBUG_DEBUGEN_Msk          (0xfUL)                   /*!< DEBUGEN (Bitfield-Mask: 0x0f)                         */
28162 
28163 
28164 /* =========================================================================================================================== */
28165 /* ================                                          AUDADC                                           ================ */
28166 /* =========================================================================================================================== */
28167 
28168 /* ==========================================================  CFG  ========================================================== */
28169 #define AUDADC_CFG_CLKSEL_Pos             (24UL)                    /*!< CLKSEL (Bit 24)                                       */
28170 #define AUDADC_CFG_CLKSEL_Msk             (0x3000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
28171 #define AUDADC_CFG_RPTTRIGSEL_Pos         (20UL)                    /*!< RPTTRIGSEL (Bit 20)                                   */
28172 #define AUDADC_CFG_RPTTRIGSEL_Msk         (0x100000UL)              /*!< RPTTRIGSEL (Bitfield-Mask: 0x01)                      */
28173 #define AUDADC_CFG_TRIGPOL_Pos            (19UL)                    /*!< TRIGPOL (Bit 19)                                      */
28174 #define AUDADC_CFG_TRIGPOL_Msk            (0x80000UL)               /*!< TRIGPOL (Bitfield-Mask: 0x01)                         */
28175 #define AUDADC_CFG_TRIGSEL_Pos            (16UL)                    /*!< TRIGSEL (Bit 16)                                      */
28176 #define AUDADC_CFG_TRIGSEL_Msk            (0x70000UL)               /*!< TRIGSEL (Bitfield-Mask: 0x07)                         */
28177 #define AUDADC_CFG_SAMPMODE_Pos           (13UL)                    /*!< SAMPMODE (Bit 13)                                     */
28178 #define AUDADC_CFG_SAMPMODE_Msk           (0x2000UL)                /*!< SAMPMODE (Bitfield-Mask: 0x01)                        */
28179 #define AUDADC_CFG_DFIFORDEN_Pos          (12UL)                    /*!< DFIFORDEN (Bit 12)                                    */
28180 #define AUDADC_CFG_DFIFORDEN_Msk          (0x1000UL)                /*!< DFIFORDEN (Bitfield-Mask: 0x01)                       */
28181 #define AUDADC_CFG_CKMODE_Pos             (4UL)                     /*!< CKMODE (Bit 4)                                        */
28182 #define AUDADC_CFG_CKMODE_Msk             (0x10UL)                  /*!< CKMODE (Bitfield-Mask: 0x01)                          */
28183 #define AUDADC_CFG_LPMODE_Pos             (3UL)                     /*!< LPMODE (Bit 3)                                        */
28184 #define AUDADC_CFG_LPMODE_Msk             (0x8UL)                   /*!< LPMODE (Bitfield-Mask: 0x01)                          */
28185 #define AUDADC_CFG_RPTEN_Pos              (2UL)                     /*!< RPTEN (Bit 2)                                         */
28186 #define AUDADC_CFG_RPTEN_Msk              (0x4UL)                   /*!< RPTEN (Bitfield-Mask: 0x01)                           */
28187 #define AUDADC_CFG_ADCEN_Pos              (0UL)                     /*!< ADCEN (Bit 0)                                         */
28188 #define AUDADC_CFG_ADCEN_Msk              (0x1UL)                   /*!< ADCEN (Bitfield-Mask: 0x01)                           */
28189 /* =========================================================  STAT  ========================================================== */
28190 #define AUDADC_STAT_PWDSTAT_Pos           (0UL)                     /*!< PWDSTAT (Bit 0)                                       */
28191 #define AUDADC_STAT_PWDSTAT_Msk           (0x1UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
28192 /* ==========================================================  SWT  ========================================================== */
28193 #define AUDADC_SWT_SWT_Pos                (0UL)                     /*!< SWT (Bit 0)                                           */
28194 #define AUDADC_SWT_SWT_Msk                (0xffUL)                  /*!< SWT (Bitfield-Mask: 0xff)                             */
28195 /* ========================================================  SL0CFG  ========================================================= */
28196 #define AUDADC_SL0CFG_ADSEL0_Pos          (24UL)                    /*!< ADSEL0 (Bit 24)                                       */
28197 #define AUDADC_SL0CFG_ADSEL0_Msk          (0x7000000UL)             /*!< ADSEL0 (Bitfield-Mask: 0x07)                          */
28198 #define AUDADC_SL0CFG_TRKCYC0_Pos         (18UL)                    /*!< TRKCYC0 (Bit 18)                                      */
28199 #define AUDADC_SL0CFG_TRKCYC0_Msk         (0xfc0000UL)              /*!< TRKCYC0 (Bitfield-Mask: 0x3f)                         */
28200 #define AUDADC_SL0CFG_PRMODE0_Pos         (16UL)                    /*!< PRMODE0 (Bit 16)                                      */
28201 #define AUDADC_SL0CFG_PRMODE0_Msk         (0x30000UL)               /*!< PRMODE0 (Bitfield-Mask: 0x03)                         */
28202 #define AUDADC_SL0CFG_CHSEL0_Pos          (8UL)                     /*!< CHSEL0 (Bit 8)                                        */
28203 #define AUDADC_SL0CFG_CHSEL0_Msk          (0xf00UL)                 /*!< CHSEL0 (Bitfield-Mask: 0x0f)                          */
28204 #define AUDADC_SL0CFG_WCEN0_Pos           (1UL)                     /*!< WCEN0 (Bit 1)                                         */
28205 #define AUDADC_SL0CFG_WCEN0_Msk           (0x2UL)                   /*!< WCEN0 (Bitfield-Mask: 0x01)                           */
28206 #define AUDADC_SL0CFG_SLEN0_Pos           (0UL)                     /*!< SLEN0 (Bit 0)                                         */
28207 #define AUDADC_SL0CFG_SLEN0_Msk           (0x1UL)                   /*!< SLEN0 (Bitfield-Mask: 0x01)                           */
28208 /* ========================================================  SL1CFG  ========================================================= */
28209 #define AUDADC_SL1CFG_ADSEL1_Pos          (24UL)                    /*!< ADSEL1 (Bit 24)                                       */
28210 #define AUDADC_SL1CFG_ADSEL1_Msk          (0x7000000UL)             /*!< ADSEL1 (Bitfield-Mask: 0x07)                          */
28211 #define AUDADC_SL1CFG_TRKCYC1_Pos         (18UL)                    /*!< TRKCYC1 (Bit 18)                                      */
28212 #define AUDADC_SL1CFG_TRKCYC1_Msk         (0xfc0000UL)              /*!< TRKCYC1 (Bitfield-Mask: 0x3f)                         */
28213 #define AUDADC_SL1CFG_PRMODE1_Pos         (16UL)                    /*!< PRMODE1 (Bit 16)                                      */
28214 #define AUDADC_SL1CFG_PRMODE1_Msk         (0x30000UL)               /*!< PRMODE1 (Bitfield-Mask: 0x03)                         */
28215 #define AUDADC_SL1CFG_CHSEL1_Pos          (8UL)                     /*!< CHSEL1 (Bit 8)                                        */
28216 #define AUDADC_SL1CFG_CHSEL1_Msk          (0xf00UL)                 /*!< CHSEL1 (Bitfield-Mask: 0x0f)                          */
28217 #define AUDADC_SL1CFG_WCEN1_Pos           (1UL)                     /*!< WCEN1 (Bit 1)                                         */
28218 #define AUDADC_SL1CFG_WCEN1_Msk           (0x2UL)                   /*!< WCEN1 (Bitfield-Mask: 0x01)                           */
28219 #define AUDADC_SL1CFG_SLEN1_Pos           (0UL)                     /*!< SLEN1 (Bit 0)                                         */
28220 #define AUDADC_SL1CFG_SLEN1_Msk           (0x1UL)                   /*!< SLEN1 (Bitfield-Mask: 0x01)                           */
28221 /* ========================================================  SL2CFG  ========================================================= */
28222 #define AUDADC_SL2CFG_ADSEL2_Pos          (24UL)                    /*!< ADSEL2 (Bit 24)                                       */
28223 #define AUDADC_SL2CFG_ADSEL2_Msk          (0x7000000UL)             /*!< ADSEL2 (Bitfield-Mask: 0x07)                          */
28224 #define AUDADC_SL2CFG_TRKCYC2_Pos         (18UL)                    /*!< TRKCYC2 (Bit 18)                                      */
28225 #define AUDADC_SL2CFG_TRKCYC2_Msk         (0xfc0000UL)              /*!< TRKCYC2 (Bitfield-Mask: 0x3f)                         */
28226 #define AUDADC_SL2CFG_PRMODE2_Pos         (16UL)                    /*!< PRMODE2 (Bit 16)                                      */
28227 #define AUDADC_SL2CFG_PRMODE2_Msk         (0x30000UL)               /*!< PRMODE2 (Bitfield-Mask: 0x03)                         */
28228 #define AUDADC_SL2CFG_CHSEL2_Pos          (8UL)                     /*!< CHSEL2 (Bit 8)                                        */
28229 #define AUDADC_SL2CFG_CHSEL2_Msk          (0xf00UL)                 /*!< CHSEL2 (Bitfield-Mask: 0x0f)                          */
28230 #define AUDADC_SL2CFG_WCEN2_Pos           (1UL)                     /*!< WCEN2 (Bit 1)                                         */
28231 #define AUDADC_SL2CFG_WCEN2_Msk           (0x2UL)                   /*!< WCEN2 (Bitfield-Mask: 0x01)                           */
28232 #define AUDADC_SL2CFG_SLEN2_Pos           (0UL)                     /*!< SLEN2 (Bit 0)                                         */
28233 #define AUDADC_SL2CFG_SLEN2_Msk           (0x1UL)                   /*!< SLEN2 (Bitfield-Mask: 0x01)                           */
28234 /* ========================================================  SL3CFG  ========================================================= */
28235 #define AUDADC_SL3CFG_ADSEL3_Pos          (24UL)                    /*!< ADSEL3 (Bit 24)                                       */
28236 #define AUDADC_SL3CFG_ADSEL3_Msk          (0x7000000UL)             /*!< ADSEL3 (Bitfield-Mask: 0x07)                          */
28237 #define AUDADC_SL3CFG_TRKCYC3_Pos         (18UL)                    /*!< TRKCYC3 (Bit 18)                                      */
28238 #define AUDADC_SL3CFG_TRKCYC3_Msk         (0xfc0000UL)              /*!< TRKCYC3 (Bitfield-Mask: 0x3f)                         */
28239 #define AUDADC_SL3CFG_PRMODE3_Pos         (16UL)                    /*!< PRMODE3 (Bit 16)                                      */
28240 #define AUDADC_SL3CFG_PRMODE3_Msk         (0x30000UL)               /*!< PRMODE3 (Bitfield-Mask: 0x03)                         */
28241 #define AUDADC_SL3CFG_CHSEL3_Pos          (8UL)                     /*!< CHSEL3 (Bit 8)                                        */
28242 #define AUDADC_SL3CFG_CHSEL3_Msk          (0xf00UL)                 /*!< CHSEL3 (Bitfield-Mask: 0x0f)                          */
28243 #define AUDADC_SL3CFG_WCEN3_Pos           (1UL)                     /*!< WCEN3 (Bit 1)                                         */
28244 #define AUDADC_SL3CFG_WCEN3_Msk           (0x2UL)                   /*!< WCEN3 (Bitfield-Mask: 0x01)                           */
28245 #define AUDADC_SL3CFG_SLEN3_Pos           (0UL)                     /*!< SLEN3 (Bit 0)                                         */
28246 #define AUDADC_SL3CFG_SLEN3_Msk           (0x1UL)                   /*!< SLEN3 (Bitfield-Mask: 0x01)                           */
28247 /* ========================================================  SL4CFG  ========================================================= */
28248 #define AUDADC_SL4CFG_ADSEL4_Pos          (24UL)                    /*!< ADSEL4 (Bit 24)                                       */
28249 #define AUDADC_SL4CFG_ADSEL4_Msk          (0x7000000UL)             /*!< ADSEL4 (Bitfield-Mask: 0x07)                          */
28250 #define AUDADC_SL4CFG_TRKCYC4_Pos         (18UL)                    /*!< TRKCYC4 (Bit 18)                                      */
28251 #define AUDADC_SL4CFG_TRKCYC4_Msk         (0xfc0000UL)              /*!< TRKCYC4 (Bitfield-Mask: 0x3f)                         */
28252 #define AUDADC_SL4CFG_PRMODE4_Pos         (16UL)                    /*!< PRMODE4 (Bit 16)                                      */
28253 #define AUDADC_SL4CFG_PRMODE4_Msk         (0x30000UL)               /*!< PRMODE4 (Bitfield-Mask: 0x03)                         */
28254 #define AUDADC_SL4CFG_CHSEL4_Pos          (8UL)                     /*!< CHSEL4 (Bit 8)                                        */
28255 #define AUDADC_SL4CFG_CHSEL4_Msk          (0xf00UL)                 /*!< CHSEL4 (Bitfield-Mask: 0x0f)                          */
28256 #define AUDADC_SL4CFG_WCEN4_Pos           (1UL)                     /*!< WCEN4 (Bit 1)                                         */
28257 #define AUDADC_SL4CFG_WCEN4_Msk           (0x2UL)                   /*!< WCEN4 (Bitfield-Mask: 0x01)                           */
28258 #define AUDADC_SL4CFG_SLEN4_Pos           (0UL)                     /*!< SLEN4 (Bit 0)                                         */
28259 #define AUDADC_SL4CFG_SLEN4_Msk           (0x1UL)                   /*!< SLEN4 (Bitfield-Mask: 0x01)                           */
28260 /* ========================================================  SL5CFG  ========================================================= */
28261 #define AUDADC_SL5CFG_ADSEL5_Pos          (24UL)                    /*!< ADSEL5 (Bit 24)                                       */
28262 #define AUDADC_SL5CFG_ADSEL5_Msk          (0x7000000UL)             /*!< ADSEL5 (Bitfield-Mask: 0x07)                          */
28263 #define AUDADC_SL5CFG_TRKCYC5_Pos         (18UL)                    /*!< TRKCYC5 (Bit 18)                                      */
28264 #define AUDADC_SL5CFG_TRKCYC5_Msk         (0xfc0000UL)              /*!< TRKCYC5 (Bitfield-Mask: 0x3f)                         */
28265 #define AUDADC_SL5CFG_PRMODE5_Pos         (16UL)                    /*!< PRMODE5 (Bit 16)                                      */
28266 #define AUDADC_SL5CFG_PRMODE5_Msk         (0x30000UL)               /*!< PRMODE5 (Bitfield-Mask: 0x03)                         */
28267 #define AUDADC_SL5CFG_CHSEL5_Pos          (8UL)                     /*!< CHSEL5 (Bit 8)                                        */
28268 #define AUDADC_SL5CFG_CHSEL5_Msk          (0xf00UL)                 /*!< CHSEL5 (Bitfield-Mask: 0x0f)                          */
28269 #define AUDADC_SL5CFG_WCEN5_Pos           (1UL)                     /*!< WCEN5 (Bit 1)                                         */
28270 #define AUDADC_SL5CFG_WCEN5_Msk           (0x2UL)                   /*!< WCEN5 (Bitfield-Mask: 0x01)                           */
28271 #define AUDADC_SL5CFG_SLEN5_Pos           (0UL)                     /*!< SLEN5 (Bit 0)                                         */
28272 #define AUDADC_SL5CFG_SLEN5_Msk           (0x1UL)                   /*!< SLEN5 (Bitfield-Mask: 0x01)                           */
28273 /* ========================================================  SL6CFG  ========================================================= */
28274 #define AUDADC_SL6CFG_ADSEL6_Pos          (24UL)                    /*!< ADSEL6 (Bit 24)                                       */
28275 #define AUDADC_SL6CFG_ADSEL6_Msk          (0x7000000UL)             /*!< ADSEL6 (Bitfield-Mask: 0x07)                          */
28276 #define AUDADC_SL6CFG_TRKCYC6_Pos         (18UL)                    /*!< TRKCYC6 (Bit 18)                                      */
28277 #define AUDADC_SL6CFG_TRKCYC6_Msk         (0xfc0000UL)              /*!< TRKCYC6 (Bitfield-Mask: 0x3f)                         */
28278 #define AUDADC_SL6CFG_PRMODE6_Pos         (16UL)                    /*!< PRMODE6 (Bit 16)                                      */
28279 #define AUDADC_SL6CFG_PRMODE6_Msk         (0x30000UL)               /*!< PRMODE6 (Bitfield-Mask: 0x03)                         */
28280 #define AUDADC_SL6CFG_CHSEL6_Pos          (8UL)                     /*!< CHSEL6 (Bit 8)                                        */
28281 #define AUDADC_SL6CFG_CHSEL6_Msk          (0xf00UL)                 /*!< CHSEL6 (Bitfield-Mask: 0x0f)                          */
28282 #define AUDADC_SL6CFG_WCEN6_Pos           (1UL)                     /*!< WCEN6 (Bit 1)                                         */
28283 #define AUDADC_SL6CFG_WCEN6_Msk           (0x2UL)                   /*!< WCEN6 (Bitfield-Mask: 0x01)                           */
28284 #define AUDADC_SL6CFG_SLEN6_Pos           (0UL)                     /*!< SLEN6 (Bit 0)                                         */
28285 #define AUDADC_SL6CFG_SLEN6_Msk           (0x1UL)                   /*!< SLEN6 (Bitfield-Mask: 0x01)                           */
28286 /* ========================================================  SL7CFG  ========================================================= */
28287 #define AUDADC_SL7CFG_ADSEL7_Pos          (24UL)                    /*!< ADSEL7 (Bit 24)                                       */
28288 #define AUDADC_SL7CFG_ADSEL7_Msk          (0x7000000UL)             /*!< ADSEL7 (Bitfield-Mask: 0x07)                          */
28289 #define AUDADC_SL7CFG_TRKCYC7_Pos         (18UL)                    /*!< TRKCYC7 (Bit 18)                                      */
28290 #define AUDADC_SL7CFG_TRKCYC7_Msk         (0xfc0000UL)              /*!< TRKCYC7 (Bitfield-Mask: 0x3f)                         */
28291 #define AUDADC_SL7CFG_PRMODE7_Pos         (16UL)                    /*!< PRMODE7 (Bit 16)                                      */
28292 #define AUDADC_SL7CFG_PRMODE7_Msk         (0x30000UL)               /*!< PRMODE7 (Bitfield-Mask: 0x03)                         */
28293 #define AUDADC_SL7CFG_CHSEL7_Pos          (8UL)                     /*!< CHSEL7 (Bit 8)                                        */
28294 #define AUDADC_SL7CFG_CHSEL7_Msk          (0xf00UL)                 /*!< CHSEL7 (Bitfield-Mask: 0x0f)                          */
28295 #define AUDADC_SL7CFG_WCEN7_Pos           (1UL)                     /*!< WCEN7 (Bit 1)                                         */
28296 #define AUDADC_SL7CFG_WCEN7_Msk           (0x2UL)                   /*!< WCEN7 (Bitfield-Mask: 0x01)                           */
28297 #define AUDADC_SL7CFG_SLEN7_Pos           (0UL)                     /*!< SLEN7 (Bit 0)                                         */
28298 #define AUDADC_SL7CFG_SLEN7_Msk           (0x1UL)                   /*!< SLEN7 (Bitfield-Mask: 0x01)                           */
28299 /* =========================================================  WULIM  ========================================================= */
28300 #define AUDADC_WULIM_ULIM_Pos             (0UL)                     /*!< ULIM (Bit 0)                                          */
28301 #define AUDADC_WULIM_ULIM_Msk             (0xfffffUL)               /*!< ULIM (Bitfield-Mask: 0xfffff)                         */
28302 /* =========================================================  WLLIM  ========================================================= */
28303 #define AUDADC_WLLIM_LLIM_Pos             (0UL)                     /*!< LLIM (Bit 0)                                          */
28304 #define AUDADC_WLLIM_LLIM_Msk             (0xfffffUL)               /*!< LLIM (Bitfield-Mask: 0xfffff)                         */
28305 /* ========================================================  SCWLIM  ========================================================= */
28306 #define AUDADC_SCWLIM_SCWLIMEN_Pos        (0UL)                     /*!< SCWLIMEN (Bit 0)                                      */
28307 #define AUDADC_SCWLIM_SCWLIMEN_Msk        (0x1UL)                   /*!< SCWLIMEN (Bitfield-Mask: 0x01)                        */
28308 /* =========================================================  FIFO  ========================================================== */
28309 #define AUDADC_FIFO_HGDATA_Pos            (20UL)                    /*!< HGDATA (Bit 20)                                       */
28310 #define AUDADC_FIFO_HGDATA_Msk            (0xfff00000UL)            /*!< HGDATA (Bitfield-Mask: 0xfff)                         */
28311 #define AUDADC_FIFO_MIC_Pos               (19UL)                    /*!< MIC (Bit 19)                                          */
28312 #define AUDADC_FIFO_MIC_Msk               (0x80000UL)               /*!< MIC (Bitfield-Mask: 0x01)                             */
28313 #define AUDADC_FIFO_METAHI_Pos            (16UL)                    /*!< METAHI (Bit 16)                                       */
28314 #define AUDADC_FIFO_METAHI_Msk            (0x70000UL)               /*!< METAHI (Bitfield-Mask: 0x07)                          */
28315 #define AUDADC_FIFO_LGDATA_Pos            (4UL)                     /*!< LGDATA (Bit 4)                                        */
28316 #define AUDADC_FIFO_LGDATA_Msk            (0xfff0UL)                /*!< LGDATA (Bitfield-Mask: 0xfff)                         */
28317 #define AUDADC_FIFO_METALO_Pos            (0UL)                     /*!< METALO (Bit 0)                                        */
28318 #define AUDADC_FIFO_METALO_Msk            (0xfUL)                   /*!< METALO (Bitfield-Mask: 0x0f)                          */
28319 /* ========================================================  FIFOPR  ========================================================= */
28320 #define AUDADC_FIFOPR_HGDATAPR_Pos        (20UL)                    /*!< HGDATAPR (Bit 20)                                     */
28321 #define AUDADC_FIFOPR_HGDATAPR_Msk        (0xfff00000UL)            /*!< HGDATAPR (Bitfield-Mask: 0xfff)                       */
28322 #define AUDADC_FIFOPR_MICPR_Pos           (19UL)                    /*!< MICPR (Bit 19)                                        */
28323 #define AUDADC_FIFOPR_MICPR_Msk           (0x80000UL)               /*!< MICPR (Bitfield-Mask: 0x01)                           */
28324 #define AUDADC_FIFOPR_METAHIPR_Pos        (16UL)                    /*!< METAHIPR (Bit 16)                                     */
28325 #define AUDADC_FIFOPR_METAHIPR_Msk        (0x70000UL)               /*!< METAHIPR (Bitfield-Mask: 0x07)                        */
28326 #define AUDADC_FIFOPR_LGDATAPR_Pos        (4UL)                     /*!< LGDATAPR (Bit 4)                                      */
28327 #define AUDADC_FIFOPR_LGDATAPR_Msk        (0xfff0UL)                /*!< LGDATAPR (Bitfield-Mask: 0xfff)                       */
28328 #define AUDADC_FIFOPR_METALOPR_Pos        (0UL)                     /*!< METALOPR (Bit 0)                                      */
28329 #define AUDADC_FIFOPR_METALOPR_Msk        (0xfUL)                   /*!< METALOPR (Bitfield-Mask: 0x0f)                        */
28330 /* =====================================================  INTTRIGTIMER  ====================================================== */
28331 #define AUDADC_INTTRIGTIMER_TIMEREN_Pos   (31UL)                    /*!< TIMEREN (Bit 31)                                      */
28332 #define AUDADC_INTTRIGTIMER_TIMEREN_Msk   (0x80000000UL)            /*!< TIMEREN (Bitfield-Mask: 0x01)                         */
28333 #define AUDADC_INTTRIGTIMER_CLKDIV_Pos    (16UL)                    /*!< CLKDIV (Bit 16)                                       */
28334 #define AUDADC_INTTRIGTIMER_CLKDIV_Msk    (0x70000UL)               /*!< CLKDIV (Bitfield-Mask: 0x07)                          */
28335 #define AUDADC_INTTRIGTIMER_TIMERMAX_Pos  (0UL)                     /*!< TIMERMAX (Bit 0)                                      */
28336 #define AUDADC_INTTRIGTIMER_TIMERMAX_Msk  (0x3ffUL)                 /*!< TIMERMAX (Bitfield-Mask: 0x3ff)                       */
28337 /* =======================================================  FIFOSTAT  ======================================================== */
28338 #define AUDADC_FIFOSTAT_FIFOCNT_Pos       (0UL)                     /*!< FIFOCNT (Bit 0)                                       */
28339 #define AUDADC_FIFOSTAT_FIFOCNT_Msk       (0xffUL)                  /*!< FIFOCNT (Bitfield-Mask: 0xff)                         */
28340 /* ======================================================  DATAOFFSET  ======================================================= */
28341 #define AUDADC_DATAOFFSET_OFFSET_Pos      (0UL)                     /*!< OFFSET (Bit 0)                                        */
28342 #define AUDADC_DATAOFFSET_OFFSET_Msk      (0x1fffUL)                /*!< OFFSET (Bitfield-Mask: 0x1fff)                        */
28343 /* =========================================================  ZXCFG  ========================================================= */
28344 #define AUDADC_ZXCFG_ZXCHANSEL_Pos        (4UL)                     /*!< ZXCHANSEL (Bit 4)                                     */
28345 #define AUDADC_ZXCFG_ZXCHANSEL_Msk        (0x10UL)                  /*!< ZXCHANSEL (Bitfield-Mask: 0x01)                       */
28346 #define AUDADC_ZXCFG_ZXEN_Pos             (0UL)                     /*!< ZXEN (Bit 0)                                          */
28347 #define AUDADC_ZXCFG_ZXEN_Msk             (0x1UL)                   /*!< ZXEN (Bitfield-Mask: 0x01)                            */
28348 /* =========================================================  ZXLIM  ========================================================= */
28349 #define AUDADC_ZXLIM_UZXC_Pos             (16UL)                    /*!< UZXC (Bit 16)                                         */
28350 #define AUDADC_ZXLIM_UZXC_Msk             (0xfff0000UL)             /*!< UZXC (Bitfield-Mask: 0xfff)                           */
28351 #define AUDADC_ZXLIM_LZXC_Pos             (0UL)                     /*!< LZXC (Bit 0)                                          */
28352 #define AUDADC_ZXLIM_LZXC_Msk             (0xfffUL)                 /*!< LZXC (Bitfield-Mask: 0xfff)                           */
28353 /* ========================================================  GAINCFG  ======================================================== */
28354 #define AUDADC_GAINCFG_UPDATEMODE_Pos     (4UL)                     /*!< UPDATEMODE (Bit 4)                                    */
28355 #define AUDADC_GAINCFG_UPDATEMODE_Msk     (0x10UL)                  /*!< UPDATEMODE (Bitfield-Mask: 0x01)                      */
28356 #define AUDADC_GAINCFG_PGACTRLEN_Pos      (0UL)                     /*!< PGACTRLEN (Bit 0)                                     */
28357 #define AUDADC_GAINCFG_PGACTRLEN_Msk      (0x1UL)                   /*!< PGACTRLEN (Bitfield-Mask: 0x01)                       */
28358 /* =========================================================  GAIN  ========================================================== */
28359 #define AUDADC_GAIN_HGBDELTA_Pos          (24UL)                    /*!< HGBDELTA (Bit 24)                                     */
28360 #define AUDADC_GAIN_HGBDELTA_Msk          (0x7f000000UL)            /*!< HGBDELTA (Bitfield-Mask: 0x7f)                        */
28361 #define AUDADC_GAIN_LGB_Pos               (16UL)                    /*!< LGB (Bit 16)                                          */
28362 #define AUDADC_GAIN_LGB_Msk               (0x7f0000UL)              /*!< LGB (Bitfield-Mask: 0x7f)                             */
28363 #define AUDADC_GAIN_HGADELTA_Pos          (8UL)                     /*!< HGADELTA (Bit 8)                                      */
28364 #define AUDADC_GAIN_HGADELTA_Msk          (0x7f00UL)                /*!< HGADELTA (Bitfield-Mask: 0x7f)                        */
28365 #define AUDADC_GAIN_LGA_Pos               (0UL)                     /*!< LGA (Bit 0)                                           */
28366 #define AUDADC_GAIN_LGA_Msk               (0x7fUL)                  /*!< LGA (Bitfield-Mask: 0x7f)                             */
28367 /* ========================================================  SATCFG  ========================================================= */
28368 #define AUDADC_SATCFG_SATCHANSEL_Pos      (4UL)                     /*!< SATCHANSEL (Bit 4)                                    */
28369 #define AUDADC_SATCFG_SATCHANSEL_Msk      (0x10UL)                  /*!< SATCHANSEL (Bitfield-Mask: 0x01)                      */
28370 #define AUDADC_SATCFG_SATEN_Pos           (0UL)                     /*!< SATEN (Bit 0)                                         */
28371 #define AUDADC_SATCFG_SATEN_Msk           (0x1UL)                   /*!< SATEN (Bitfield-Mask: 0x01)                           */
28372 /* ========================================================  SATLIM  ========================================================= */
28373 #define AUDADC_SATLIM_USATC_Pos           (16UL)                    /*!< USATC (Bit 16)                                        */
28374 #define AUDADC_SATLIM_USATC_Msk           (0xfff0000UL)             /*!< USATC (Bitfield-Mask: 0xfff)                          */
28375 #define AUDADC_SATLIM_LSATC_Pos           (0UL)                     /*!< LSATC (Bit 0)                                         */
28376 #define AUDADC_SATLIM_LSATC_Msk           (0xfffUL)                 /*!< LSATC (Bitfield-Mask: 0xfff)                          */
28377 /* ========================================================  SATMAX  ========================================================= */
28378 #define AUDADC_SATMAX_SATCBMAX_Pos        (16UL)                    /*!< SATCBMAX (Bit 16)                                     */
28379 #define AUDADC_SATMAX_SATCBMAX_Msk        (0xfff0000UL)             /*!< SATCBMAX (Bitfield-Mask: 0xfff)                       */
28380 #define AUDADC_SATMAX_SATCAMAX_Pos        (0UL)                     /*!< SATCAMAX (Bit 0)                                      */
28381 #define AUDADC_SATMAX_SATCAMAX_Msk        (0xfffUL)                 /*!< SATCAMAX (Bitfield-Mask: 0xfff)                       */
28382 /* ========================================================  SATCLR  ========================================================= */
28383 #define AUDADC_SATCLR_SATCBCLR_Pos        (1UL)                     /*!< SATCBCLR (Bit 1)                                      */
28384 #define AUDADC_SATCLR_SATCBCLR_Msk        (0x2UL)                   /*!< SATCBCLR (Bitfield-Mask: 0x01)                        */
28385 #define AUDADC_SATCLR_SATCACLR_Pos        (0UL)                     /*!< SATCACLR (Bit 0)                                      */
28386 #define AUDADC_SATCLR_SATCACLR_Msk        (0x1UL)                   /*!< SATCACLR (Bitfield-Mask: 0x01)                        */
28387 /* =========================================================  INTEN  ========================================================= */
28388 #define AUDADC_INTEN_SATCB_Pos            (11UL)                    /*!< SATCB (Bit 11)                                        */
28389 #define AUDADC_INTEN_SATCB_Msk            (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
28390 #define AUDADC_INTEN_SATCA_Pos            (10UL)                    /*!< SATCA (Bit 10)                                        */
28391 #define AUDADC_INTEN_SATCA_Msk            (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
28392 #define AUDADC_INTEN_ZXCB_Pos             (9UL)                     /*!< ZXCB (Bit 9)                                          */
28393 #define AUDADC_INTEN_ZXCB_Msk             (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
28394 #define AUDADC_INTEN_ZXCA_Pos             (8UL)                     /*!< ZXCA (Bit 8)                                          */
28395 #define AUDADC_INTEN_ZXCA_Msk             (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
28396 #define AUDADC_INTEN_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
28397 #define AUDADC_INTEN_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
28398 #define AUDADC_INTEN_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
28399 #define AUDADC_INTEN_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
28400 #define AUDADC_INTEN_WCINC_Pos            (5UL)                     /*!< WCINC (Bit 5)                                         */
28401 #define AUDADC_INTEN_WCINC_Msk            (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
28402 #define AUDADC_INTEN_WCEXC_Pos            (4UL)                     /*!< WCEXC (Bit 4)                                         */
28403 #define AUDADC_INTEN_WCEXC_Msk            (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
28404 #define AUDADC_INTEN_FIFOOVR2_Pos         (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
28405 #define AUDADC_INTEN_FIFOOVR2_Msk         (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
28406 #define AUDADC_INTEN_FIFOOVR1_Pos         (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
28407 #define AUDADC_INTEN_FIFOOVR1_Msk         (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
28408 #define AUDADC_INTEN_SCNCMP_Pos           (1UL)                     /*!< SCNCMP (Bit 1)                                        */
28409 #define AUDADC_INTEN_SCNCMP_Msk           (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
28410 #define AUDADC_INTEN_CNVCMP_Pos           (0UL)                     /*!< CNVCMP (Bit 0)                                        */
28411 #define AUDADC_INTEN_CNVCMP_Msk           (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
28412 /* ========================================================  INTSTAT  ======================================================== */
28413 #define AUDADC_INTSTAT_SATCB_Pos          (11UL)                    /*!< SATCB (Bit 11)                                        */
28414 #define AUDADC_INTSTAT_SATCB_Msk          (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
28415 #define AUDADC_INTSTAT_SATCA_Pos          (10UL)                    /*!< SATCA (Bit 10)                                        */
28416 #define AUDADC_INTSTAT_SATCA_Msk          (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
28417 #define AUDADC_INTSTAT_ZXCB_Pos           (9UL)                     /*!< ZXCB (Bit 9)                                          */
28418 #define AUDADC_INTSTAT_ZXCB_Msk           (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
28419 #define AUDADC_INTSTAT_ZXCA_Pos           (8UL)                     /*!< ZXCA (Bit 8)                                          */
28420 #define AUDADC_INTSTAT_ZXCA_Msk           (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
28421 #define AUDADC_INTSTAT_DERR_Pos           (7UL)                     /*!< DERR (Bit 7)                                          */
28422 #define AUDADC_INTSTAT_DERR_Msk           (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
28423 #define AUDADC_INTSTAT_DCMP_Pos           (6UL)                     /*!< DCMP (Bit 6)                                          */
28424 #define AUDADC_INTSTAT_DCMP_Msk           (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
28425 #define AUDADC_INTSTAT_WCINC_Pos          (5UL)                     /*!< WCINC (Bit 5)                                         */
28426 #define AUDADC_INTSTAT_WCINC_Msk          (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
28427 #define AUDADC_INTSTAT_WCEXC_Pos          (4UL)                     /*!< WCEXC (Bit 4)                                         */
28428 #define AUDADC_INTSTAT_WCEXC_Msk          (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
28429 #define AUDADC_INTSTAT_FIFOOVR2_Pos       (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
28430 #define AUDADC_INTSTAT_FIFOOVR2_Msk       (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
28431 #define AUDADC_INTSTAT_FIFOOVR1_Pos       (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
28432 #define AUDADC_INTSTAT_FIFOOVR1_Msk       (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
28433 #define AUDADC_INTSTAT_SCNCMP_Pos         (1UL)                     /*!< SCNCMP (Bit 1)                                        */
28434 #define AUDADC_INTSTAT_SCNCMP_Msk         (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
28435 #define AUDADC_INTSTAT_CNVCMP_Pos         (0UL)                     /*!< CNVCMP (Bit 0)                                        */
28436 #define AUDADC_INTSTAT_CNVCMP_Msk         (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
28437 /* ========================================================  INTCLR  ========================================================= */
28438 #define AUDADC_INTCLR_SATCB_Pos           (11UL)                    /*!< SATCB (Bit 11)                                        */
28439 #define AUDADC_INTCLR_SATCB_Msk           (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
28440 #define AUDADC_INTCLR_SATCA_Pos           (10UL)                    /*!< SATCA (Bit 10)                                        */
28441 #define AUDADC_INTCLR_SATCA_Msk           (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
28442 #define AUDADC_INTCLR_ZXCB_Pos            (9UL)                     /*!< ZXCB (Bit 9)                                          */
28443 #define AUDADC_INTCLR_ZXCB_Msk            (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
28444 #define AUDADC_INTCLR_ZXCA_Pos            (8UL)                     /*!< ZXCA (Bit 8)                                          */
28445 #define AUDADC_INTCLR_ZXCA_Msk            (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
28446 #define AUDADC_INTCLR_DERR_Pos            (7UL)                     /*!< DERR (Bit 7)                                          */
28447 #define AUDADC_INTCLR_DERR_Msk            (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
28448 #define AUDADC_INTCLR_DCMP_Pos            (6UL)                     /*!< DCMP (Bit 6)                                          */
28449 #define AUDADC_INTCLR_DCMP_Msk            (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
28450 #define AUDADC_INTCLR_WCINC_Pos           (5UL)                     /*!< WCINC (Bit 5)                                         */
28451 #define AUDADC_INTCLR_WCINC_Msk           (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
28452 #define AUDADC_INTCLR_WCEXC_Pos           (4UL)                     /*!< WCEXC (Bit 4)                                         */
28453 #define AUDADC_INTCLR_WCEXC_Msk           (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
28454 #define AUDADC_INTCLR_FIFOOVR2_Pos        (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
28455 #define AUDADC_INTCLR_FIFOOVR2_Msk        (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
28456 #define AUDADC_INTCLR_FIFOOVR1_Pos        (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
28457 #define AUDADC_INTCLR_FIFOOVR1_Msk        (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
28458 #define AUDADC_INTCLR_SCNCMP_Pos          (1UL)                     /*!< SCNCMP (Bit 1)                                        */
28459 #define AUDADC_INTCLR_SCNCMP_Msk          (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
28460 #define AUDADC_INTCLR_CNVCMP_Pos          (0UL)                     /*!< CNVCMP (Bit 0)                                        */
28461 #define AUDADC_INTCLR_CNVCMP_Msk          (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
28462 /* ========================================================  INTSET  ========================================================= */
28463 #define AUDADC_INTSET_SATCB_Pos           (11UL)                    /*!< SATCB (Bit 11)                                        */
28464 #define AUDADC_INTSET_SATCB_Msk           (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
28465 #define AUDADC_INTSET_SATCA_Pos           (10UL)                    /*!< SATCA (Bit 10)                                        */
28466 #define AUDADC_INTSET_SATCA_Msk           (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
28467 #define AUDADC_INTSET_ZXCB_Pos            (9UL)                     /*!< ZXCB (Bit 9)                                          */
28468 #define AUDADC_INTSET_ZXCB_Msk            (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
28469 #define AUDADC_INTSET_ZXCA_Pos            (8UL)                     /*!< ZXCA (Bit 8)                                          */
28470 #define AUDADC_INTSET_ZXCA_Msk            (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
28471 #define AUDADC_INTSET_DERR_Pos            (7UL)                     /*!< DERR (Bit 7)                                          */
28472 #define AUDADC_INTSET_DERR_Msk            (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
28473 #define AUDADC_INTSET_DCMP_Pos            (6UL)                     /*!< DCMP (Bit 6)                                          */
28474 #define AUDADC_INTSET_DCMP_Msk            (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
28475 #define AUDADC_INTSET_WCINC_Pos           (5UL)                     /*!< WCINC (Bit 5)                                         */
28476 #define AUDADC_INTSET_WCINC_Msk           (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
28477 #define AUDADC_INTSET_WCEXC_Pos           (4UL)                     /*!< WCEXC (Bit 4)                                         */
28478 #define AUDADC_INTSET_WCEXC_Msk           (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
28479 #define AUDADC_INTSET_FIFOOVR2_Pos        (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
28480 #define AUDADC_INTSET_FIFOOVR2_Msk        (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
28481 #define AUDADC_INTSET_FIFOOVR1_Pos        (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
28482 #define AUDADC_INTSET_FIFOOVR1_Msk        (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
28483 #define AUDADC_INTSET_SCNCMP_Pos          (1UL)                     /*!< SCNCMP (Bit 1)                                        */
28484 #define AUDADC_INTSET_SCNCMP_Msk          (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
28485 #define AUDADC_INTSET_CNVCMP_Pos          (0UL)                     /*!< CNVCMP (Bit 0)                                        */
28486 #define AUDADC_INTSET_CNVCMP_Msk          (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
28487 /* =======================================================  DMATRIGEN  ======================================================= */
28488 #define AUDADC_DMATRIGEN_DFIFOFULL_Pos    (1UL)                     /*!< DFIFOFULL (Bit 1)                                     */
28489 #define AUDADC_DMATRIGEN_DFIFOFULL_Msk    (0x2UL)                   /*!< DFIFOFULL (Bitfield-Mask: 0x01)                       */
28490 #define AUDADC_DMATRIGEN_DFIFO75_Pos      (0UL)                     /*!< DFIFO75 (Bit 0)                                       */
28491 #define AUDADC_DMATRIGEN_DFIFO75_Msk      (0x1UL)                   /*!< DFIFO75 (Bitfield-Mask: 0x01)                         */
28492 /* ======================================================  DMATRIGSTAT  ====================================================== */
28493 #define AUDADC_DMATRIGSTAT_DFULLSTAT_Pos  (1UL)                     /*!< DFULLSTAT (Bit 1)                                     */
28494 #define AUDADC_DMATRIGSTAT_DFULLSTAT_Msk  (0x2UL)                   /*!< DFULLSTAT (Bitfield-Mask: 0x01)                       */
28495 #define AUDADC_DMATRIGSTAT_D75STAT_Pos    (0UL)                     /*!< D75STAT (Bit 0)                                       */
28496 #define AUDADC_DMATRIGSTAT_D75STAT_Msk    (0x1UL)                   /*!< D75STAT (Bitfield-Mask: 0x01)                         */
28497 /* ========================================================  DMACFG  ========================================================= */
28498 #define AUDADC_DMACFG_DPWROFF_Pos         (18UL)                    /*!< DPWROFF (Bit 18)                                      */
28499 #define AUDADC_DMACFG_DPWROFF_Msk         (0x40000UL)               /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
28500 #define AUDADC_DMACFG_DMADYNPRI_Pos       (9UL)                     /*!< DMADYNPRI (Bit 9)                                     */
28501 #define AUDADC_DMACFG_DMADYNPRI_Msk       (0x200UL)                 /*!< DMADYNPRI (Bitfield-Mask: 0x01)                       */
28502 #define AUDADC_DMACFG_DMAPRI_Pos          (8UL)                     /*!< DMAPRI (Bit 8)                                        */
28503 #define AUDADC_DMACFG_DMAPRI_Msk          (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
28504 #define AUDADC_DMACFG_DMADIR_Pos          (2UL)                     /*!< DMADIR (Bit 2)                                        */
28505 #define AUDADC_DMACFG_DMADIR_Msk          (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
28506 #define AUDADC_DMACFG_DMAEN_Pos           (0UL)                     /*!< DMAEN (Bit 0)                                         */
28507 #define AUDADC_DMACFG_DMAEN_Msk           (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
28508 /* ======================================================  DMATOTCOUNT  ====================================================== */
28509 #define AUDADC_DMATOTCOUNT_TOTCOUNT_Pos   (2UL)                     /*!< TOTCOUNT (Bit 2)                                      */
28510 #define AUDADC_DMATOTCOUNT_TOTCOUNT_Msk   (0x3fffcUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xffff)                      */
28511 /* ======================================================  DMATARGADDR  ====================================================== */
28512 #define AUDADC_DMATARGADDR_UTARGADDR_Pos  (28UL)                    /*!< UTARGADDR (Bit 28)                                    */
28513 #define AUDADC_DMATARGADDR_UTARGADDR_Msk  (0xf0000000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x0f)                       */
28514 #define AUDADC_DMATARGADDR_LTARGADDR_Pos  (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
28515 #define AUDADC_DMATARGADDR_LTARGADDR_Msk  (0xfffffffUL)             /*!< LTARGADDR (Bitfield-Mask: 0xfffffff)                  */
28516 /* ========================================================  DMASTAT  ======================================================== */
28517 #define AUDADC_DMASTAT_DMAERR_Pos         (2UL)                     /*!< DMAERR (Bit 2)                                        */
28518 #define AUDADC_DMASTAT_DMAERR_Msk         (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
28519 #define AUDADC_DMASTAT_DMACPL_Pos         (1UL)                     /*!< DMACPL (Bit 1)                                        */
28520 #define AUDADC_DMASTAT_DMACPL_Msk         (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
28521 #define AUDADC_DMASTAT_DMATIP_Pos         (0UL)                     /*!< DMATIP (Bit 0)                                        */
28522 #define AUDADC_DMASTAT_DMATIP_Msk         (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
28523 
28524 
28525 /* =========================================================================================================================== */
28526 /* ================                                          CLKGEN                                           ================ */
28527 /* =========================================================================================================================== */
28528 
28529 /* =========================================================  OCTRL  ========================================================= */
28530 #define CLKGEN_OCTRL_OSEL_Pos             (7UL)                     /*!< OSEL (Bit 7)                                          */
28531 #define CLKGEN_OCTRL_OSEL_Msk             (0x80UL)                  /*!< OSEL (Bitfield-Mask: 0x01)                            */
28532 /* ========================================================  CLKOUT  ========================================================= */
28533 #define CLKGEN_CLKOUT_CKEN_Pos            (7UL)                     /*!< CKEN (Bit 7)                                          */
28534 #define CLKGEN_CLKOUT_CKEN_Msk            (0x80UL)                  /*!< CKEN (Bitfield-Mask: 0x01)                            */
28535 #define CLKGEN_CLKOUT_CKSEL_Pos           (0UL)                     /*!< CKSEL (Bit 0)                                         */
28536 #define CLKGEN_CLKOUT_CKSEL_Msk           (0x3fUL)                  /*!< CKSEL (Bitfield-Mask: 0x3f)                           */
28537 /* =========================================================  HFADJ  ========================================================= */
28538 #define CLKGEN_HFADJ_HFADJMAXDELTA_Pos    (24UL)                    /*!< HFADJMAXDELTA (Bit 24)                                */
28539 #define CLKGEN_HFADJ_HFADJMAXDELTA_Msk    (0x1f000000UL)            /*!< HFADJMAXDELTA (Bitfield-Mask: 0x1f)                   */
28540 #define CLKGEN_HFADJ_HFADJGAIN_Pos        (21UL)                    /*!< HFADJGAIN (Bit 21)                                    */
28541 #define CLKGEN_HFADJ_HFADJGAIN_Msk        (0xe00000UL)              /*!< HFADJGAIN (Bitfield-Mask: 0x07)                       */
28542 #define CLKGEN_HFADJ_HFWARMUP_Pos         (20UL)                    /*!< HFWARMUP (Bit 20)                                     */
28543 #define CLKGEN_HFADJ_HFWARMUP_Msk         (0x100000UL)              /*!< HFWARMUP (Bitfield-Mask: 0x01)                        */
28544 #define CLKGEN_HFADJ_HFXTADJ_Pos          (8UL)                     /*!< HFXTADJ (Bit 8)                                       */
28545 #define CLKGEN_HFADJ_HFXTADJ_Msk          (0xfff00UL)               /*!< HFXTADJ (Bitfield-Mask: 0xfff)                        */
28546 #define CLKGEN_HFADJ_HFADJCK_Pos          (1UL)                     /*!< HFADJCK (Bit 1)                                       */
28547 #define CLKGEN_HFADJ_HFADJCK_Msk          (0xeUL)                   /*!< HFADJCK (Bitfield-Mask: 0x07)                         */
28548 #define CLKGEN_HFADJ_HFADJEN_Pos          (0UL)                     /*!< HFADJEN (Bit 0)                                       */
28549 #define CLKGEN_HFADJ_HFADJEN_Msk          (0x1UL)                   /*!< HFADJEN (Bitfield-Mask: 0x01)                         */
28550 /* ======================================================  CLOCKENSTAT  ====================================================== */
28551 #define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Pos (0UL)                    /*!< CLOCKENSTAT (Bit 0)                                   */
28552 #define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Msk (0xffffffffUL)           /*!< CLOCKENSTAT (Bitfield-Mask: 0xffffffff)               */
28553 /* =====================================================  CLOCKEN2STAT  ====================================================== */
28554 #define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Pos (0UL)                  /*!< CLOCKEN2STAT (Bit 0)                                  */
28555 #define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Msk (0xffffffffUL)         /*!< CLOCKEN2STAT (Bitfield-Mask: 0xffffffff)              */
28556 /* =====================================================  CLOCKEN3STAT  ====================================================== */
28557 #define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Pos (0UL)                  /*!< CLOCKEN3STAT (Bit 0)                                  */
28558 #define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Msk (0xffffffffUL)         /*!< CLOCKEN3STAT (Bitfield-Mask: 0xffffffff)              */
28559 /* =========================================================  MISC  ========================================================== */
28560 #define CLKGEN_MISC_CLKGENMISCSPARE_Pos   (25UL)                    /*!< CLKGENMISCSPARE (Bit 25)                              */
28561 #define CLKGEN_MISC_CLKGENMISCSPARE_Msk   (0x2000000UL)             /*!< CLKGENMISCSPARE (Bitfield-Mask: 0x01)                 */
28562 #define CLKGEN_MISC_HFRC96TRUNKGATE_Pos   (24UL)                    /*!< HFRC96TRUNKGATE (Bit 24)                              */
28563 #define CLKGEN_MISC_HFRC96TRUNKGATE_Msk   (0x1000000UL)             /*!< HFRC96TRUNKGATE (Bitfield-Mask: 0x01)                 */
28564 #define CLKGEN_MISC_HFRCFUNCCLKGATEEN_Pos (23UL)                    /*!< HFRCFUNCCLKGATEEN (Bit 23)                            */
28565 #define CLKGEN_MISC_HFRCFUNCCLKGATEEN_Msk (0x800000UL)              /*!< HFRCFUNCCLKGATEEN (Bitfield-Mask: 0x01)               */
28566 #define CLKGEN_MISC_ETMTRACECLKCLKGATEEN_Pos (22UL)                 /*!< ETMTRACECLKCLKGATEEN (Bit 22)                         */
28567 #define CLKGEN_MISC_ETMTRACECLKCLKGATEEN_Msk (0x400000UL)           /*!< ETMTRACECLKCLKGATEEN (Bitfield-Mask: 0x01)            */
28568 #define CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_Pos (21UL)                /*!< APBDMACPUCLKCLKGATEEN (Bit 21)                        */
28569 #define CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_Msk (0x200000UL)          /*!< APBDMACPUCLKCLKGATEEN (Bitfield-Mask: 0x01)           */
28570 #define CLKGEN_MISC_GFXAXICLKCLKGATEEN_Pos (20UL)                   /*!< GFXAXICLKCLKGATEEN (Bit 20)                           */
28571 #define CLKGEN_MISC_GFXAXICLKCLKGATEEN_Msk (0x100000UL)             /*!< GFXAXICLKCLKGATEEN (Bitfield-Mask: 0x01)              */
28572 #define CLKGEN_MISC_GFXCLKCLKGATEEN_Pos   (19UL)                    /*!< GFXCLKCLKGATEEN (Bit 19)                              */
28573 #define CLKGEN_MISC_GFXCLKCLKGATEEN_Msk   (0x80000UL)               /*!< GFXCLKCLKGATEEN (Bitfield-Mask: 0x01)                 */
28574 #define CLKGEN_MISC_CM4DAXICLKGATEEN_Pos  (18UL)                    /*!< CM4DAXICLKGATEEN (Bit 18)                             */
28575 #define CLKGEN_MISC_CM4DAXICLKGATEEN_Msk  (0x40000UL)               /*!< CM4DAXICLKGATEEN (Bitfield-Mask: 0x01)                */
28576 #define CLKGEN_MISC_PWRONCLKENUSBREFCLK_Pos (17UL)                  /*!< PWRONCLKENUSBREFCLK (Bit 17)                          */
28577 #define CLKGEN_MISC_PWRONCLKENUSBREFCLK_Msk (0x20000UL)             /*!< PWRONCLKENUSBREFCLK (Bitfield-Mask: 0x01)             */
28578 #define CLKGEN_MISC_PWRONCLKENI2S1REFCLK_Pos (16UL)                 /*!< PWRONCLKENI2S1REFCLK (Bit 16)                         */
28579 #define CLKGEN_MISC_PWRONCLKENI2S1REFCLK_Msk (0x10000UL)            /*!< PWRONCLKENI2S1REFCLK (Bitfield-Mask: 0x01)            */
28580 #define CLKGEN_MISC_PWRONCLKENI2S0REFCLK_Pos (15UL)                 /*!< PWRONCLKENI2S0REFCLK (Bit 15)                         */
28581 #define CLKGEN_MISC_PWRONCLKENI2S0REFCLK_Msk (0x8000UL)             /*!< PWRONCLKENI2S0REFCLK (Bitfield-Mask: 0x01)            */
28582 #define CLKGEN_MISC_AXIXACLKENOVRRIDE_Pos (14UL)                    /*!< AXIXACLKENOVRRIDE (Bit 14)                            */
28583 #define CLKGEN_MISC_AXIXACLKENOVRRIDE_Msk (0x4000UL)                /*!< AXIXACLKENOVRRIDE (Bitfield-Mask: 0x01)               */
28584 #define CLKGEN_MISC_PWRONCLKENI2S1_Pos    (13UL)                    /*!< PWRONCLKENI2S1 (Bit 13)                               */
28585 #define CLKGEN_MISC_PWRONCLKENI2S1_Msk    (0x2000UL)                /*!< PWRONCLKENI2S1 (Bitfield-Mask: 0x01)                  */
28586 #define CLKGEN_MISC_PWRONCLKENI2S0_Pos    (12UL)                    /*!< PWRONCLKENI2S0 (Bit 12)                               */
28587 #define CLKGEN_MISC_PWRONCLKENI2S0_Msk    (0x1000UL)                /*!< PWRONCLKENI2S0 (Bitfield-Mask: 0x01)                  */
28588 #define CLKGEN_MISC_PWRONCLKENCRYPTO_Pos  (11UL)                    /*!< PWRONCLKENCRYPTO (Bit 11)                             */
28589 #define CLKGEN_MISC_PWRONCLKENCRYPTO_Msk  (0x800UL)                 /*!< PWRONCLKENCRYPTO (Bitfield-Mask: 0x01)                */
28590 #define CLKGEN_MISC_PWRONCLKENSDIO_Pos    (10UL)                    /*!< PWRONCLKENSDIO (Bit 10)                               */
28591 #define CLKGEN_MISC_PWRONCLKENSDIO_Msk    (0x400UL)                 /*!< PWRONCLKENSDIO (Bitfield-Mask: 0x01)                  */
28592 #define CLKGEN_MISC_PWRONCLKENUSB_Pos     (9UL)                     /*!< PWRONCLKENUSB (Bit 9)                                 */
28593 #define CLKGEN_MISC_PWRONCLKENUSB_Msk     (0x200UL)                 /*!< PWRONCLKENUSB (Bitfield-Mask: 0x01)                   */
28594 #define CLKGEN_MISC_PWRONCLKENGFX_Pos     (8UL)                     /*!< PWRONCLKENGFX (Bit 8)                                 */
28595 #define CLKGEN_MISC_PWRONCLKENGFX_Msk     (0x100UL)                 /*!< PWRONCLKENGFX (Bitfield-Mask: 0x01)                   */
28596 #define CLKGEN_MISC_PWRONCLKENDISPPHY_Pos (7UL)                     /*!< PWRONCLKENDISPPHY (Bit 7)                             */
28597 #define CLKGEN_MISC_PWRONCLKENDISPPHY_Msk (0x80UL)                  /*!< PWRONCLKENDISPPHY (Bitfield-Mask: 0x01)               */
28598 #define CLKGEN_MISC_PWRONCLKENDISP_Pos    (6UL)                     /*!< PWRONCLKENDISP (Bit 6)                                */
28599 #define CLKGEN_MISC_PWRONCLKENDISP_Msk    (0x40UL)                  /*!< PWRONCLKENDISP (Bitfield-Mask: 0x01)                  */
28600 #define CLKGEN_MISC_FRCHFRC2_Pos          (5UL)                     /*!< FRCHFRC2 (Bit 5)                                      */
28601 #define CLKGEN_MISC_FRCHFRC2_Msk          (0x20UL)                  /*!< FRCHFRC2 (Bitfield-Mask: 0x01)                        */
28602 #define CLKGEN_MISC_USEHFRC2FQ192MHZ_Pos  (4UL)                     /*!< USEHFRC2FQ192MHZ (Bit 4)                              */
28603 #define CLKGEN_MISC_USEHFRC2FQ192MHZ_Msk  (0x10UL)                  /*!< USEHFRC2FQ192MHZ (Bitfield-Mask: 0x01)                */
28604 #define CLKGEN_MISC_USEHFRC2FQ96MHZ_Pos   (3UL)                     /*!< USEHFRC2FQ96MHZ (Bit 3)                               */
28605 #define CLKGEN_MISC_USEHFRC2FQ96MHZ_Msk   (0x8UL)                   /*!< USEHFRC2FQ96MHZ (Bitfield-Mask: 0x01)                 */
28606 #define CLKGEN_MISC_USEHFRC2FQ48MHZ_Pos   (2UL)                     /*!< USEHFRC2FQ48MHZ (Bit 2)                               */
28607 #define CLKGEN_MISC_USEHFRC2FQ48MHZ_Msk   (0x4UL)                   /*!< USEHFRC2FQ48MHZ (Bitfield-Mask: 0x01)                 */
28608 #define CLKGEN_MISC_FRCBURSTOFF_Pos       (1UL)                     /*!< FRCBURSTOFF (Bit 1)                                   */
28609 #define CLKGEN_MISC_FRCBURSTOFF_Msk       (0x2UL)                   /*!< FRCBURSTOFF (Bitfield-Mask: 0x01)                     */
28610 #define CLKGEN_MISC_FRCHFRC_Pos           (0UL)                     /*!< FRCHFRC (Bit 0)                                       */
28611 #define CLKGEN_MISC_FRCHFRC_Msk           (0x1UL)                   /*!< FRCHFRC (Bitfield-Mask: 0x01)                         */
28612 /* ========================================================  HF2ADJ0  ======================================================== */
28613 #define CLKGEN_HF2ADJ0_HF2ADJXTHSMUXSEL_Pos (29UL)                  /*!< HF2ADJXTHSMUXSEL (Bit 29)                             */
28614 #define CLKGEN_HF2ADJ0_HF2ADJXTHSMUXSEL_Msk (0x20000000UL)          /*!< HF2ADJXTHSMUXSEL (Bitfield-Mask: 0x01)                */
28615 #define CLKGEN_HF2ADJ0_HF2ADJCNTINOFFSET_Pos (15UL)                 /*!< HF2ADJCNTINOFFSET (Bit 15)                            */
28616 #define CLKGEN_HF2ADJ0_HF2ADJCNTINOFFSET_Msk (0x1fff8000UL)         /*!< HF2ADJCNTINOFFSET (Bitfield-Mask: 0x3fff)             */
28617 #define CLKGEN_HF2ADJ0_HF2ADJFASTSTRDLY_Pos (2UL)                   /*!< HF2ADJFASTSTRDLY (Bit 2)                              */
28618 #define CLKGEN_HF2ADJ0_HF2ADJFASTSTRDLY_Msk (0x7ffcUL)              /*!< HF2ADJFASTSTRDLY (Bitfield-Mask: 0x1fff)              */
28619 #define CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Pos (1UL)                    /*!< HF2ADJFASTSTREN (Bit 1)                               */
28620 #define CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Msk (0x2UL)                  /*!< HF2ADJFASTSTREN (Bitfield-Mask: 0x01)                 */
28621 #define CLKGEN_HF2ADJ0_HF2ADJEN_Pos       (0UL)                     /*!< HF2ADJEN (Bit 0)                                      */
28622 #define CLKGEN_HF2ADJ0_HF2ADJEN_Msk       (0x1UL)                   /*!< HF2ADJEN (Bitfield-Mask: 0x01)                        */
28623 /* ========================================================  HF2ADJ1  ======================================================== */
28624 #define CLKGEN_HF2ADJ1_HF2ADJTRIMOFFSET_Pos (3UL)                   /*!< HF2ADJTRIMOFFSET (Bit 3)                              */
28625 #define CLKGEN_HF2ADJ1_HF2ADJTRIMOFFSET_Msk (0x3ff8UL)              /*!< HF2ADJTRIMOFFSET (Bitfield-Mask: 0x7ff)               */
28626 #define CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Pos   (0UL)                     /*!< HF2ADJTRIMEN (Bit 0)                                  */
28627 #define CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Msk   (0x7UL)                   /*!< HF2ADJTRIMEN (Bitfield-Mask: 0x07)                    */
28628 /* ========================================================  HF2ADJ2  ======================================================== */
28629 #define CLKGEN_HF2ADJ2_HF2ADJRATIO_Pos    (2UL)                     /*!< HF2ADJRATIO (Bit 2)                                   */
28630 #define CLKGEN_HF2ADJ2_HF2ADJRATIO_Msk    (0x7ffffffcUL)            /*!< HF2ADJRATIO (Bitfield-Mask: 0x1fffffff)               */
28631 #define CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Pos (0UL)                 /*!< HF2ADJXTALDIVRATIO (Bit 0)                            */
28632 #define CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Msk (0x3UL)               /*!< HF2ADJXTALDIVRATIO (Bitfield-Mask: 0x03)              */
28633 /* ========================================================  HF2VAL  ========================================================= */
28634 #define CLKGEN_HF2VAL_HF2ADJTRIMOUT_Pos   (0UL)                     /*!< HF2ADJTRIMOUT (Bit 0)                                 */
28635 #define CLKGEN_HF2VAL_HF2ADJTRIMOUT_Msk   (0x7ffUL)                 /*!< HF2ADJTRIMOUT (Bitfield-Mask: 0x7ff)                  */
28636 /* =======================================================  LFRCCTRL  ======================================================== */
28637 #define CLKGEN_LFRCCTRL_LFRCPWD_Pos       (1UL)                     /*!< LFRCPWD (Bit 1)                                       */
28638 #define CLKGEN_LFRCCTRL_LFRCPWD_Msk       (0x2UL)                   /*!< LFRCPWD (Bitfield-Mask: 0x01)                         */
28639 #define CLKGEN_LFRCCTRL_LFRCOUT_Pos       (0UL)                     /*!< LFRCOUT (Bit 0)                                       */
28640 #define CLKGEN_LFRCCTRL_LFRCOUT_Msk       (0x1UL)                   /*!< LFRCOUT (Bitfield-Mask: 0x01)                         */
28641 /* ======================================================  DISPCLKCTRL  ====================================================== */
28642 #define CLKGEN_DISPCLKCTRL_DCCLKEN_Pos    (7UL)                     /*!< DCCLKEN (Bit 7)                                       */
28643 #define CLKGEN_DISPCLKCTRL_DCCLKEN_Msk    (0x80UL)                  /*!< DCCLKEN (Bitfield-Mask: 0x01)                         */
28644 #define CLKGEN_DISPCLKCTRL_DISPCLKSEL_Pos (4UL)                     /*!< DISPCLKSEL (Bit 4)                                    */
28645 #define CLKGEN_DISPCLKCTRL_DISPCLKSEL_Msk (0x30UL)                  /*!< DISPCLKSEL (Bitfield-Mask: 0x03)                      */
28646 #define CLKGEN_DISPCLKCTRL_PLLCLKEN_Pos   (3UL)                     /*!< PLLCLKEN (Bit 3)                                      */
28647 #define CLKGEN_DISPCLKCTRL_PLLCLKEN_Msk   (0x8UL)                   /*!< PLLCLKEN (Bitfield-Mask: 0x01)                        */
28648 #define CLKGEN_DISPCLKCTRL_PLLCLKSEL_Pos  (0UL)                     /*!< PLLCLKSEL (Bit 0)                                     */
28649 #define CLKGEN_DISPCLKCTRL_PLLCLKSEL_Msk  (0x3UL)                   /*!< PLLCLKSEL (Bitfield-Mask: 0x03)                       */
28650 /* =====================================================  CLKGENSPARES  ====================================================== */
28651 #define CLKGEN_CLKGENSPARES_CLKGENSPARES_Pos (0UL)                  /*!< CLKGENSPARES (Bit 0)                                  */
28652 #define CLKGEN_CLKGENSPARES_CLKGENSPARES_Msk (0xffffffffUL)         /*!< CLKGENSPARES (Bitfield-Mask: 0xffffffff)              */
28653 /* ===================================================  HFRCIDLECOUNTERS  ==================================================== */
28654 #define CLKGEN_HFRCIDLECOUNTERS_UPDATEENABLE_Pos (31UL)             /*!< UPDATEENABLE (Bit 31)                                 */
28655 #define CLKGEN_HFRCIDLECOUNTERS_UPDATEENABLE_Msk (0x80000000UL)     /*!< UPDATEENABLE (Bitfield-Mask: 0x01)                    */
28656 #define CLKGEN_HFRCIDLECOUNTERS_HFRC2CLKREQDELAY_Pos (24UL)         /*!< HFRC2CLKREQDELAY (Bit 24)                             */
28657 #define CLKGEN_HFRCIDLECOUNTERS_HFRC2CLKREQDELAY_Msk (0x3f000000UL) /*!< HFRC2CLKREQDELAY (Bitfield-Mask: 0x3f)                */
28658 #define CLKGEN_HFRCIDLECOUNTERS_HFRC2PWRDOWNDELAY_Pos (16UL)        /*!< HFRC2PWRDOWNDELAY (Bit 16)                            */
28659 #define CLKGEN_HFRCIDLECOUNTERS_HFRC2PWRDOWNDELAY_Msk (0x3f0000UL)  /*!< HFRC2PWRDOWNDELAY (Bitfield-Mask: 0x3f)               */
28660 #define CLKGEN_HFRCIDLECOUNTERS_HFRCCLKREQDELAY_Pos (8UL)           /*!< HFRCCLKREQDELAY (Bit 8)                               */
28661 #define CLKGEN_HFRCIDLECOUNTERS_HFRCCLKREQDELAY_Msk (0x3f00UL)      /*!< HFRCCLKREQDELAY (Bitfield-Mask: 0x3f)                 */
28662 #define CLKGEN_HFRCIDLECOUNTERS_HFRCPWRDOWNDELAY_Pos (0UL)          /*!< HFRCPWRDOWNDELAY (Bit 0)                              */
28663 #define CLKGEN_HFRCIDLECOUNTERS_HFRCPWRDOWNDELAY_Msk (0x3fUL)       /*!< HFRCPWRDOWNDELAY (Bitfield-Mask: 0x3f)                */
28664 /* =======================================================  INTRPTEN  ======================================================== */
28665 #define CLKGEN_INTRPTEN_OF_Pos            (0UL)                     /*!< OF (Bit 0)                                            */
28666 #define CLKGEN_INTRPTEN_OF_Msk            (0x1UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
28667 /* ======================================================  INTRPTSTAT  ======================================================= */
28668 #define CLKGEN_INTRPTSTAT_OF_Pos          (0UL)                     /*!< OF (Bit 0)                                            */
28669 #define CLKGEN_INTRPTSTAT_OF_Msk          (0x1UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
28670 /* =======================================================  INTRPTCLR  ======================================================= */
28671 #define CLKGEN_INTRPTCLR_OF_Pos           (0UL)                     /*!< OF (Bit 0)                                            */
28672 #define CLKGEN_INTRPTCLR_OF_Msk           (0x1UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
28673 /* =======================================================  INTRPTSET  ======================================================= */
28674 #define CLKGEN_INTRPTSET_OF_Pos           (0UL)                     /*!< OF (Bit 0)                                            */
28675 #define CLKGEN_INTRPTSET_OF_Msk           (0x1UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
28676 
28677 
28678 /* =========================================================================================================================== */
28679 /* ================                                            CPU                                            ================ */
28680 /* =========================================================================================================================== */
28681 
28682 /* =======================================================  CACHECFG  ======================================================== */
28683 #define CPU_CACHECFG_ENABLEMONITOR_Pos    (24UL)                    /*!< ENABLEMONITOR (Bit 24)                                */
28684 #define CPU_CACHECFG_ENABLEMONITOR_Msk    (0x1000000UL)             /*!< ENABLEMONITOR (Bitfield-Mask: 0x01)                   */
28685 #define CPU_CACHECFG_DATACLKGATE_Pos      (20UL)                    /*!< DATACLKGATE (Bit 20)                                  */
28686 #define CPU_CACHECFG_DATACLKGATE_Msk      (0x100000UL)              /*!< DATACLKGATE (Bitfield-Mask: 0x01)                     */
28687 #define CPU_CACHECFG_NC0CACHELOCK_Pos     (13UL)                    /*!< NC0CACHELOCK (Bit 13)                                 */
28688 #define CPU_CACHECFG_NC0CACHELOCK_Msk     (0x2000UL)                /*!< NC0CACHELOCK (Bitfield-Mask: 0x01)                    */
28689 #define CPU_CACHECFG_NC1CACHELOCK_Pos     (12UL)                    /*!< NC1CACHELOCK (Bit 12)                                 */
28690 #define CPU_CACHECFG_NC1CACHELOCK_Msk     (0x1000UL)                /*!< NC1CACHELOCK (Bitfield-Mask: 0x01)                    */
28691 #define CPU_CACHECFG_LS_Pos               (11UL)                    /*!< LS (Bit 11)                                           */
28692 #define CPU_CACHECFG_LS_Msk               (0x800UL)                 /*!< LS (Bitfield-Mask: 0x01)                              */
28693 #define CPU_CACHECFG_CLKGATE_Pos          (10UL)                    /*!< CLKGATE (Bit 10)                                      */
28694 #define CPU_CACHECFG_CLKGATE_Msk          (0x400UL)                 /*!< CLKGATE (Bitfield-Mask: 0x01)                         */
28695 #define CPU_CACHECFG_DENABLE_Pos          (9UL)                     /*!< DENABLE (Bit 9)                                       */
28696 #define CPU_CACHECFG_DENABLE_Msk          (0x200UL)                 /*!< DENABLE (Bitfield-Mask: 0x01)                         */
28697 #define CPU_CACHECFG_IENABLE_Pos          (8UL)                     /*!< IENABLE (Bit 8)                                       */
28698 #define CPU_CACHECFG_IENABLE_Msk          (0x100UL)                 /*!< IENABLE (Bitfield-Mask: 0x01)                         */
28699 #define CPU_CACHECFG_CONFIG_Pos           (4UL)                     /*!< CONFIG (Bit 4)                                        */
28700 #define CPU_CACHECFG_CONFIG_Msk           (0xf0UL)                  /*!< CONFIG (Bitfield-Mask: 0x0f)                          */
28701 #define CPU_CACHECFG_NC1ENABLE_Pos        (3UL)                     /*!< NC1ENABLE (Bit 3)                                     */
28702 #define CPU_CACHECFG_NC1ENABLE_Msk        (0x8UL)                   /*!< NC1ENABLE (Bitfield-Mask: 0x01)                       */
28703 #define CPU_CACHECFG_NC0ENABLE_Pos        (2UL)                     /*!< NC0ENABLE (Bit 2)                                     */
28704 #define CPU_CACHECFG_NC0ENABLE_Msk        (0x4UL)                   /*!< NC0ENABLE (Bitfield-Mask: 0x01)                       */
28705 #define CPU_CACHECFG_LRU_Pos              (1UL)                     /*!< LRU (Bit 1)                                           */
28706 #define CPU_CACHECFG_LRU_Msk              (0x2UL)                   /*!< LRU (Bitfield-Mask: 0x01)                             */
28707 #define CPU_CACHECFG_ENABLE_Pos           (0UL)                     /*!< ENABLE (Bit 0)                                        */
28708 #define CPU_CACHECFG_ENABLE_Msk           (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
28709 /* =======================================================  CACHECTRL  ======================================================= */
28710 #define CPU_CACHECTRL_CACHEREADY_Pos      (2UL)                     /*!< CACHEREADY (Bit 2)                                    */
28711 #define CPU_CACHECTRL_CACHEREADY_Msk      (0x4UL)                   /*!< CACHEREADY (Bitfield-Mask: 0x01)                      */
28712 #define CPU_CACHECTRL_RESETSTAT_Pos       (1UL)                     /*!< RESETSTAT (Bit 1)                                     */
28713 #define CPU_CACHECTRL_RESETSTAT_Msk       (0x2UL)                   /*!< RESETSTAT (Bitfield-Mask: 0x01)                       */
28714 #define CPU_CACHECTRL_INVALIDATE_Pos      (0UL)                     /*!< INVALIDATE (Bit 0)                                    */
28715 #define CPU_CACHECTRL_INVALIDATE_Msk      (0x1UL)                   /*!< INVALIDATE (Bitfield-Mask: 0x01)                      */
28716 /* =======================================================  NCR0START  ======================================================= */
28717 #define CPU_NCR0START_ADDR_Pos            (4UL)                     /*!< ADDR (Bit 4)                                          */
28718 #define CPU_NCR0START_ADDR_Msk            (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
28719 /* ========================================================  NCR0END  ======================================================== */
28720 #define CPU_NCR0END_ADDR_Pos              (4UL)                     /*!< ADDR (Bit 4)                                          */
28721 #define CPU_NCR0END_ADDR_Msk              (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
28722 /* =======================================================  NCR1START  ======================================================= */
28723 #define CPU_NCR1START_ADDR_Pos            (4UL)                     /*!< ADDR (Bit 4)                                          */
28724 #define CPU_NCR1START_ADDR_Msk            (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
28725 /* ========================================================  NCR1END  ======================================================== */
28726 #define CPU_NCR1END_ADDR_Pos              (4UL)                     /*!< ADDR (Bit 4)                                          */
28727 #define CPU_NCR1END_ADDR_Msk              (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
28728 /* ========================================================  DAXICFG  ======================================================== */
28729 #define CPU_DAXICFG_MRUGROUPLEVEL_Pos     (24UL)                    /*!< MRUGROUPLEVEL (Bit 24)                                */
28730 #define CPU_DAXICFG_MRUGROUPLEVEL_Msk     (0x3000000UL)             /*!< MRUGROUPLEVEL (Bitfield-Mask: 0x03)                   */
28731 #define CPU_DAXICFG_AGINGCOUNTER_Pos      (16UL)                    /*!< AGINGCOUNTER (Bit 16)                                 */
28732 #define CPU_DAXICFG_AGINGCOUNTER_Msk      (0x1f0000UL)              /*!< AGINGCOUNTER (Bitfield-Mask: 0x1f)                    */
28733 #define CPU_DAXICFG_BUFFERENABLE_Pos      (8UL)                     /*!< BUFFERENABLE (Bit 8)                                  */
28734 #define CPU_DAXICFG_BUFFERENABLE_Msk      (0xf00UL)                 /*!< BUFFERENABLE (Bitfield-Mask: 0x0f)                    */
28735 #define CPU_DAXICFG_DAXISTATECLKGATEEN_Pos (5UL)                    /*!< DAXISTATECLKGATEEN (Bit 5)                            */
28736 #define CPU_DAXICFG_DAXISTATECLKGATEEN_Msk (0x20UL)                 /*!< DAXISTATECLKGATEEN (Bitfield-Mask: 0x01)              */
28737 #define CPU_DAXICFG_DAXIDATACLKGATEEN_Pos (4UL)                     /*!< DAXIDATACLKGATEEN (Bit 4)                             */
28738 #define CPU_DAXICFG_DAXIDATACLKGATEEN_Msk (0x10UL)                  /*!< DAXIDATACLKGATEEN (Bitfield-Mask: 0x01)               */
28739 #define CPU_DAXICFG_DAXIBECLKGATEEN_Pos   (3UL)                     /*!< DAXIBECLKGATEEN (Bit 3)                               */
28740 #define CPU_DAXICFG_DAXIBECLKGATEEN_Msk   (0x8UL)                   /*!< DAXIBECLKGATEEN (Bitfield-Mask: 0x01)                 */
28741 #define CPU_DAXICFG_DAXIPASSTHROUGH_Pos   (2UL)                     /*!< DAXIPASSTHROUGH (Bit 2)                               */
28742 #define CPU_DAXICFG_DAXIPASSTHROUGH_Msk   (0x4UL)                   /*!< DAXIPASSTHROUGH (Bitfield-Mask: 0x01)                 */
28743 #define CPU_DAXICFG_AGINGSENABLE_Pos      (1UL)                     /*!< AGINGSENABLE (Bit 1)                                  */
28744 #define CPU_DAXICFG_AGINGSENABLE_Msk      (0x2UL)                   /*!< AGINGSENABLE (Bitfield-Mask: 0x01)                    */
28745 #define CPU_DAXICFG_FLUSHLEVEL_Pos        (0UL)                     /*!< FLUSHLEVEL (Bit 0)                                    */
28746 #define CPU_DAXICFG_FLUSHLEVEL_Msk        (0x1UL)                   /*!< FLUSHLEVEL (Bitfield-Mask: 0x01)                      */
28747 /* =======================================================  DAXICTRL  ======================================================== */
28748 #define CPU_DAXICTRL_DAXIRAXIBUSY_Pos     (12UL)                    /*!< DAXIRAXIBUSY (Bit 12)                                 */
28749 #define CPU_DAXICTRL_DAXIRAXIBUSY_Msk     (0x1000UL)                /*!< DAXIRAXIBUSY (Bitfield-Mask: 0x01)                    */
28750 #define CPU_DAXICTRL_DAXIBRESPPENDING_Pos (11UL)                    /*!< DAXIBRESPPENDING (Bit 11)                             */
28751 #define CPU_DAXICTRL_DAXIBRESPPENDING_Msk (0x800UL)                 /*!< DAXIBRESPPENDING (Bitfield-Mask: 0x01)                */
28752 #define CPU_DAXICTRL_DAXISTORE_Pos        (10UL)                    /*!< DAXISTORE (Bit 10)                                    */
28753 #define CPU_DAXICTRL_DAXISTORE_Msk        (0x400UL)                 /*!< DAXISTORE (Bitfield-Mask: 0x01)                       */
28754 #define CPU_DAXICTRL_DAXIWRLOAD_Pos       (9UL)                     /*!< DAXIWRLOAD (Bit 9)                                    */
28755 #define CPU_DAXICTRL_DAXIWRLOAD_Msk       (0x200UL)                 /*!< DAXIWRLOAD (Bitfield-Mask: 0x01)                      */
28756 #define CPU_DAXICTRL_DAXIWALLOC_Pos       (8UL)                     /*!< DAXIWALLOC (Bit 8)                                    */
28757 #define CPU_DAXICTRL_DAXIWALLOC_Msk       (0x100UL)                 /*!< DAXIWALLOC (Bitfield-Mask: 0x01)                      */
28758 #define CPU_DAXICTRL_DAXIWRITE_Pos        (7UL)                     /*!< DAXIWRITE (Bit 7)                                     */
28759 #define CPU_DAXICTRL_DAXIWRITE_Msk        (0x80UL)                  /*!< DAXIWRITE (Bitfield-Mask: 0x01)                       */
28760 #define CPU_DAXICTRL_DAXIMODIFIED_Pos     (6UL)                     /*!< DAXIMODIFIED (Bit 6)                                  */
28761 #define CPU_DAXICTRL_DAXIMODIFIED_Msk     (0x40UL)                  /*!< DAXIMODIFIED (Bitfield-Mask: 0x01)                    */
28762 #define CPU_DAXICTRL_DAXISHARED_Pos       (5UL)                     /*!< DAXISHARED (Bit 5)                                    */
28763 #define CPU_DAXICTRL_DAXISHARED_Msk       (0x20UL)                  /*!< DAXISHARED (Bitfield-Mask: 0x01)                      */
28764 #define CPU_DAXICTRL_DAXIAHBBUSY_Pos      (4UL)                     /*!< DAXIAHBBUSY (Bit 4)                                   */
28765 #define CPU_DAXICTRL_DAXIAHBBUSY_Msk      (0x10UL)                  /*!< DAXIAHBBUSY (Bitfield-Mask: 0x01)                     */
28766 #define CPU_DAXICTRL_DAXIBUSY_Pos         (3UL)                     /*!< DAXIBUSY (Bit 3)                                      */
28767 #define CPU_DAXICTRL_DAXIBUSY_Msk         (0x8UL)                   /*!< DAXIBUSY (Bitfield-Mask: 0x01)                        */
28768 #define CPU_DAXICTRL_DAXIREADY_Pos        (2UL)                     /*!< DAXIREADY (Bit 2)                                     */
28769 #define CPU_DAXICTRL_DAXIREADY_Msk        (0x4UL)                   /*!< DAXIREADY (Bitfield-Mask: 0x01)                       */
28770 #define CPU_DAXICTRL_DAXIINVALIDATE_Pos   (1UL)                     /*!< DAXIINVALIDATE (Bit 1)                                */
28771 #define CPU_DAXICTRL_DAXIINVALIDATE_Msk   (0x2UL)                   /*!< DAXIINVALIDATE (Bitfield-Mask: 0x01)                  */
28772 #define CPU_DAXICTRL_DAXIFLUSHWRITE_Pos   (0UL)                     /*!< DAXIFLUSHWRITE (Bit 0)                                */
28773 #define CPU_DAXICTRL_DAXIFLUSHWRITE_Msk   (0x1UL)                   /*!< DAXIFLUSHWRITE (Bitfield-Mask: 0x01)                  */
28774 /* ====================================================  ICODEFAULTADDR  ===================================================== */
28775 #define CPU_ICODEFAULTADDR_ICODEFAULTADDR_Pos (0UL)                 /*!< ICODEFAULTADDR (Bit 0)                                */
28776 #define CPU_ICODEFAULTADDR_ICODEFAULTADDR_Msk (0xffffffffUL)        /*!< ICODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
28777 /* ====================================================  DCODEFAULTADDR  ===================================================== */
28778 #define CPU_DCODEFAULTADDR_DCODEFAULTADDR_Pos (0UL)                 /*!< DCODEFAULTADDR (Bit 0)                                */
28779 #define CPU_DCODEFAULTADDR_DCODEFAULTADDR_Msk (0xffffffffUL)        /*!< DCODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
28780 /* =====================================================  SYSFAULTADDR  ====================================================== */
28781 #define CPU_SYSFAULTADDR_SYSFAULTADDR_Pos (0UL)                     /*!< SYSFAULTADDR (Bit 0)                                  */
28782 #define CPU_SYSFAULTADDR_SYSFAULTADDR_Msk (0xffffffffUL)            /*!< SYSFAULTADDR (Bitfield-Mask: 0xffffffff)              */
28783 /* ======================================================  FAULTSTATUS  ====================================================== */
28784 #define CPU_FAULTSTATUS_SYSFAULT_Pos      (2UL)                     /*!< SYSFAULT (Bit 2)                                      */
28785 #define CPU_FAULTSTATUS_SYSFAULT_Msk      (0x4UL)                   /*!< SYSFAULT (Bitfield-Mask: 0x01)                        */
28786 #define CPU_FAULTSTATUS_DCODEFAULT_Pos    (1UL)                     /*!< DCODEFAULT (Bit 1)                                    */
28787 #define CPU_FAULTSTATUS_DCODEFAULT_Msk    (0x2UL)                   /*!< DCODEFAULT (Bitfield-Mask: 0x01)                      */
28788 #define CPU_FAULTSTATUS_ICODEFAULT_Pos    (0UL)                     /*!< ICODEFAULT (Bit 0)                                    */
28789 #define CPU_FAULTSTATUS_ICODEFAULT_Msk    (0x1UL)                   /*!< ICODEFAULT (Bitfield-Mask: 0x01)                      */
28790 /* ====================================================  FAULTCAPTUREEN  ===================================================== */
28791 #define CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Pos (0UL)                 /*!< FAULTCAPTUREEN (Bit 0)                                */
28792 #define CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Msk (0x1UL)               /*!< FAULTCAPTUREEN (Bitfield-Mask: 0x01)                  */
28793 /* =========================================================  INTEN  ========================================================= */
28794 #define CPU_INTEN_AXIWERROR_Pos           (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
28795 #define CPU_INTEN_AXIWERROR_Msk           (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
28796 /* ========================================================  INTSTAT  ======================================================== */
28797 #define CPU_INTSTAT_AXIWERROR_Pos         (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
28798 #define CPU_INTSTAT_AXIWERROR_Msk         (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
28799 /* ========================================================  INTCLR  ========================================================= */
28800 #define CPU_INTCLR_AXIWERROR_Pos          (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
28801 #define CPU_INTCLR_AXIWERROR_Msk          (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
28802 /* ========================================================  INTSET  ========================================================= */
28803 #define CPU_INTSET_AXIWERROR_Pos          (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
28804 #define CPU_INTSET_AXIWERROR_Msk          (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
28805 /* =====================================================  WRITEERRADDR  ====================================================== */
28806 #define CPU_WRITEERRADDR_WERRADDR_Pos     (0UL)                     /*!< WERRADDR (Bit 0)                                      */
28807 #define CPU_WRITEERRADDR_WERRADDR_Msk     (0xffffffffUL)            /*!< WERRADDR (Bitfield-Mask: 0xffffffff)                  */
28808 /* =========================================================  DMON0  ========================================================= */
28809 #define CPU_DMON0_DACCESS_Pos             (0UL)                     /*!< DACCESS (Bit 0)                                       */
28810 #define CPU_DMON0_DACCESS_Msk             (0xffffffffUL)            /*!< DACCESS (Bitfield-Mask: 0xffffffff)                   */
28811 /* =========================================================  DMON1  ========================================================= */
28812 #define CPU_DMON1_DLOOKUP_Pos             (0UL)                     /*!< DLOOKUP (Bit 0)                                       */
28813 #define CPU_DMON1_DLOOKUP_Msk             (0xffffffffUL)            /*!< DLOOKUP (Bitfield-Mask: 0xffffffff)                   */
28814 /* =========================================================  DMON2  ========================================================= */
28815 #define CPU_DMON2_DHIT_Pos                (0UL)                     /*!< DHIT (Bit 0)                                          */
28816 #define CPU_DMON2_DHIT_Msk                (0xffffffffUL)            /*!< DHIT (Bitfield-Mask: 0xffffffff)                      */
28817 /* =========================================================  DMON3  ========================================================= */
28818 #define CPU_DMON3_DLINE_Pos               (0UL)                     /*!< DLINE (Bit 0)                                         */
28819 #define CPU_DMON3_DLINE_Msk               (0xffffffffUL)            /*!< DLINE (Bitfield-Mask: 0xffffffff)                     */
28820 /* =========================================================  IMON0  ========================================================= */
28821 #define CPU_IMON0_IACCESS_Pos             (0UL)                     /*!< IACCESS (Bit 0)                                       */
28822 #define CPU_IMON0_IACCESS_Msk             (0xffffffffUL)            /*!< IACCESS (Bitfield-Mask: 0xffffffff)                   */
28823 /* =========================================================  IMON1  ========================================================= */
28824 #define CPU_IMON1_ILOOKUP_Pos             (0UL)                     /*!< ILOOKUP (Bit 0)                                       */
28825 #define CPU_IMON1_ILOOKUP_Msk             (0xffffffffUL)            /*!< ILOOKUP (Bitfield-Mask: 0xffffffff)                   */
28826 /* =========================================================  IMON2  ========================================================= */
28827 #define CPU_IMON2_IHIT_Pos                (0UL)                     /*!< IHIT (Bit 0)                                          */
28828 #define CPU_IMON2_IHIT_Msk                (0xffffffffUL)            /*!< IHIT (Bitfield-Mask: 0xffffffff)                      */
28829 /* =========================================================  IMON3  ========================================================= */
28830 #define CPU_IMON3_ILINE_Pos               (0UL)                     /*!< ILINE (Bit 0)                                         */
28831 #define CPU_IMON3_ILINE_Msk               (0xffffffffUL)            /*!< ILINE (Bitfield-Mask: 0xffffffff)                     */
28832 
28833 
28834 /* =========================================================================================================================== */
28835 /* ================                                          CRYPTO                                           ================ */
28836 /* =========================================================================================================================== */
28837 
28838 /* ======================================================  MEMORYMAP0  ======================================================= */
28839 #define CRYPTO_MEMORYMAP0_PHYSADDRMAP0_Pos (1UL)                    /*!< PHYSADDRMAP0 (Bit 1)                                  */
28840 #define CRYPTO_MEMORYMAP0_PHYSADDRMAP0_Msk (0x7feUL)                /*!< PHYSADDRMAP0 (Bitfield-Mask: 0x3ff)                   */
28841 /* ======================================================  MEMORYMAP1  ======================================================= */
28842 #define CRYPTO_MEMORYMAP1_PHYSADDRMAP1_Pos (1UL)                    /*!< PHYSADDRMAP1 (Bit 1)                                  */
28843 #define CRYPTO_MEMORYMAP1_PHYSADDRMAP1_Msk (0x7feUL)                /*!< PHYSADDRMAP1 (Bitfield-Mask: 0x3ff)                   */
28844 /* ======================================================  MEMORYMAP2  ======================================================= */
28845 #define CRYPTO_MEMORYMAP2_PHYSADDRMAP2_Pos (1UL)                    /*!< PHYSADDRMAP2 (Bit 1)                                  */
28846 #define CRYPTO_MEMORYMAP2_PHYSADDRMAP2_Msk (0x7feUL)                /*!< PHYSADDRMAP2 (Bitfield-Mask: 0x3ff)                   */
28847 /* ======================================================  MEMORYMAP3  ======================================================= */
28848 #define CRYPTO_MEMORYMAP3_PHYSADDRMAP3_Pos (1UL)                    /*!< PHYSADDRMAP3 (Bit 1)                                  */
28849 #define CRYPTO_MEMORYMAP3_PHYSADDRMAP3_Msk (0x7feUL)                /*!< PHYSADDRMAP3 (Bitfield-Mask: 0x3ff)                   */
28850 /* ======================================================  MEMORYMAP4  ======================================================= */
28851 #define CRYPTO_MEMORYMAP4_PHYSADDRMAP4_Pos (1UL)                    /*!< PHYSADDRMAP4 (Bit 1)                                  */
28852 #define CRYPTO_MEMORYMAP4_PHYSADDRMAP4_Msk (0x7feUL)                /*!< PHYSADDRMAP4 (Bitfield-Mask: 0x3ff)                   */
28853 /* ======================================================  MEMORYMAP5  ======================================================= */
28854 #define CRYPTO_MEMORYMAP5_PHYSADDRMAP5_Pos (1UL)                    /*!< PHYSADDRMAP5 (Bit 1)                                  */
28855 #define CRYPTO_MEMORYMAP5_PHYSADDRMAP5_Msk (0x7feUL)                /*!< PHYSADDRMAP5 (Bitfield-Mask: 0x3ff)                   */
28856 /* ======================================================  MEMORYMAP6  ======================================================= */
28857 #define CRYPTO_MEMORYMAP6_PHYSADDRMAP6_Pos (1UL)                    /*!< PHYSADDRMAP6 (Bit 1)                                  */
28858 #define CRYPTO_MEMORYMAP6_PHYSADDRMAP6_Msk (0x7feUL)                /*!< PHYSADDRMAP6 (Bitfield-Mask: 0x3ff)                   */
28859 /* ======================================================  MEMORYMAP7  ======================================================= */
28860 #define CRYPTO_MEMORYMAP7_PHYSADDRMAP7_Pos (1UL)                    /*!< PHYSADDRMAP7 (Bit 1)                                  */
28861 #define CRYPTO_MEMORYMAP7_PHYSADDRMAP7_Msk (0x7feUL)                /*!< PHYSADDRMAP7 (Bitfield-Mask: 0x3ff)                   */
28862 /* ======================================================  MEMORYMAP8  ======================================================= */
28863 #define CRYPTO_MEMORYMAP8_PHYSADDRMAP8_Pos (1UL)                    /*!< PHYSADDRMAP8 (Bit 1)                                  */
28864 #define CRYPTO_MEMORYMAP8_PHYSADDRMAP8_Msk (0x7feUL)                /*!< PHYSADDRMAP8 (Bitfield-Mask: 0x3ff)                   */
28865 /* ======================================================  MEMORYMAP9  ======================================================= */
28866 #define CRYPTO_MEMORYMAP9_PHYSADDRMAP9_Pos (1UL)                    /*!< PHYSADDRMAP9 (Bit 1)                                  */
28867 #define CRYPTO_MEMORYMAP9_PHYSADDRMAP9_Msk (0x7feUL)                /*!< PHYSADDRMAP9 (Bitfield-Mask: 0x3ff)                   */
28868 /* ======================================================  MEMORYMAP10  ====================================================== */
28869 #define CRYPTO_MEMORYMAP10_PHYSADDRMAP10_Pos (1UL)                  /*!< PHYSADDRMAP10 (Bit 1)                                 */
28870 #define CRYPTO_MEMORYMAP10_PHYSADDRMAP10_Msk (0x7feUL)              /*!< PHYSADDRMAP10 (Bitfield-Mask: 0x3ff)                  */
28871 /* ======================================================  MEMORYMAP11  ====================================================== */
28872 #define CRYPTO_MEMORYMAP11_PHYSADDRMAP11_Pos (1UL)                  /*!< PHYSADDRMAP11 (Bit 1)                                 */
28873 #define CRYPTO_MEMORYMAP11_PHYSADDRMAP11_Msk (0x7feUL)              /*!< PHYSADDRMAP11 (Bitfield-Mask: 0x3ff)                  */
28874 /* ======================================================  MEMORYMAP12  ====================================================== */
28875 #define CRYPTO_MEMORYMAP12_PHYSADDRMAP12_Pos (1UL)                  /*!< PHYSADDRMAP12 (Bit 1)                                 */
28876 #define CRYPTO_MEMORYMAP12_PHYSADDRMAP12_Msk (0x7feUL)              /*!< PHYSADDRMAP12 (Bitfield-Mask: 0x3ff)                  */
28877 /* ======================================================  MEMORYMAP13  ====================================================== */
28878 #define CRYPTO_MEMORYMAP13_PHYSADDRMAP13_Pos (1UL)                  /*!< PHYSADDRMAP13 (Bit 1)                                 */
28879 #define CRYPTO_MEMORYMAP13_PHYSADDRMAP13_Msk (0x7feUL)              /*!< PHYSADDRMAP13 (Bitfield-Mask: 0x3ff)                  */
28880 /* ======================================================  MEMORYMAP14  ====================================================== */
28881 #define CRYPTO_MEMORYMAP14_PHYSADDRMAP14_Pos (1UL)                  /*!< PHYSADDRMAP14 (Bit 1)                                 */
28882 #define CRYPTO_MEMORYMAP14_PHYSADDRMAP14_Msk (0x7feUL)              /*!< PHYSADDRMAP14 (Bitfield-Mask: 0x3ff)                  */
28883 /* ======================================================  MEMORYMAP15  ====================================================== */
28884 #define CRYPTO_MEMORYMAP15_PHYSADDRMAP15_Pos (1UL)                  /*!< PHYSADDRMAP15 (Bit 1)                                 */
28885 #define CRYPTO_MEMORYMAP15_PHYSADDRMAP15_Msk (0x7feUL)              /*!< PHYSADDRMAP15 (Bitfield-Mask: 0x3ff)                  */
28886 /* ======================================================  MEMORYMAP16  ====================================================== */
28887 #define CRYPTO_MEMORYMAP16_PHYSADDRMAP16_Pos (1UL)                  /*!< PHYSADDRMAP16 (Bit 1)                                 */
28888 #define CRYPTO_MEMORYMAP16_PHYSADDRMAP16_Msk (0x7feUL)              /*!< PHYSADDRMAP16 (Bitfield-Mask: 0x3ff)                  */
28889 /* ======================================================  MEMORYMAP17  ====================================================== */
28890 #define CRYPTO_MEMORYMAP17_PHYSADDRMAP17_Pos (1UL)                  /*!< PHYSADDRMAP17 (Bit 1)                                 */
28891 #define CRYPTO_MEMORYMAP17_PHYSADDRMAP17_Msk (0x7feUL)              /*!< PHYSADDRMAP17 (Bitfield-Mask: 0x3ff)                  */
28892 /* ======================================================  MEMORYMAP18  ====================================================== */
28893 #define CRYPTO_MEMORYMAP18_PHYSADDRMAP18_Pos (1UL)                  /*!< PHYSADDRMAP18 (Bit 1)                                 */
28894 #define CRYPTO_MEMORYMAP18_PHYSADDRMAP18_Msk (0x7feUL)              /*!< PHYSADDRMAP18 (Bitfield-Mask: 0x3ff)                  */
28895 /* ======================================================  MEMORYMAP19  ====================================================== */
28896 #define CRYPTO_MEMORYMAP19_PHYSADDRMAP19_Pos (1UL)                  /*!< PHYSADDRMAP19 (Bit 1)                                 */
28897 #define CRYPTO_MEMORYMAP19_PHYSADDRMAP19_Msk (0x7feUL)              /*!< PHYSADDRMAP19 (Bitfield-Mask: 0x3ff)                  */
28898 /* ======================================================  MEMORYMAP20  ====================================================== */
28899 #define CRYPTO_MEMORYMAP20_PHYSADDRMAP20_Pos (1UL)                  /*!< PHYSADDRMAP20 (Bit 1)                                 */
28900 #define CRYPTO_MEMORYMAP20_PHYSADDRMAP20_Msk (0x7feUL)              /*!< PHYSADDRMAP20 (Bitfield-Mask: 0x3ff)                  */
28901 /* ======================================================  MEMORYMAP21  ====================================================== */
28902 #define CRYPTO_MEMORYMAP21_PHYSADDRMAP21_Pos (1UL)                  /*!< PHYSADDRMAP21 (Bit 1)                                 */
28903 #define CRYPTO_MEMORYMAP21_PHYSADDRMAP21_Msk (0x7feUL)              /*!< PHYSADDRMAP21 (Bitfield-Mask: 0x3ff)                  */
28904 /* ======================================================  MEMORYMAP22  ====================================================== */
28905 #define CRYPTO_MEMORYMAP22_PHYSADDRMAP22_Pos (1UL)                  /*!< PHYSADDRMAP22 (Bit 1)                                 */
28906 #define CRYPTO_MEMORYMAP22_PHYSADDRMAP22_Msk (0x7feUL)              /*!< PHYSADDRMAP22 (Bitfield-Mask: 0x3ff)                  */
28907 /* ======================================================  MEMORYMAP23  ====================================================== */
28908 #define CRYPTO_MEMORYMAP23_PHYSADDRMAP23_Pos (1UL)                  /*!< PHYSADDRMAP23 (Bit 1)                                 */
28909 #define CRYPTO_MEMORYMAP23_PHYSADDRMAP23_Msk (0x7feUL)              /*!< PHYSADDRMAP23 (Bitfield-Mask: 0x3ff)                  */
28910 /* ======================================================  MEMORYMAP24  ====================================================== */
28911 #define CRYPTO_MEMORYMAP24_PHYSADDRMAP24_Pos (1UL)                  /*!< PHYSADDRMAP24 (Bit 1)                                 */
28912 #define CRYPTO_MEMORYMAP24_PHYSADDRMAP24_Msk (0x7feUL)              /*!< PHYSADDRMAP24 (Bitfield-Mask: 0x3ff)                  */
28913 /* ======================================================  MEMORYMAP25  ====================================================== */
28914 #define CRYPTO_MEMORYMAP25_PHYSADDRMAP25_Pos (1UL)                  /*!< PHYSADDRMAP25 (Bit 1)                                 */
28915 #define CRYPTO_MEMORYMAP25_PHYSADDRMAP25_Msk (0x7feUL)              /*!< PHYSADDRMAP25 (Bitfield-Mask: 0x3ff)                  */
28916 /* ======================================================  MEMORYMAP26  ====================================================== */
28917 #define CRYPTO_MEMORYMAP26_PHYSADDRMAP26_Pos (1UL)                  /*!< PHYSADDRMAP26 (Bit 1)                                 */
28918 #define CRYPTO_MEMORYMAP26_PHYSADDRMAP26_Msk (0x7feUL)              /*!< PHYSADDRMAP26 (Bitfield-Mask: 0x3ff)                  */
28919 /* ======================================================  MEMORYMAP27  ====================================================== */
28920 #define CRYPTO_MEMORYMAP27_PHYSADDRMAP27_Pos (1UL)                  /*!< PHYSADDRMAP27 (Bit 1)                                 */
28921 #define CRYPTO_MEMORYMAP27_PHYSADDRMAP27_Msk (0x7feUL)              /*!< PHYSADDRMAP27 (Bitfield-Mask: 0x3ff)                  */
28922 /* ======================================================  MEMORYMAP28  ====================================================== */
28923 #define CRYPTO_MEMORYMAP28_PHYSADDRMAP28_Pos (1UL)                  /*!< PHYSADDRMAP28 (Bit 1)                                 */
28924 #define CRYPTO_MEMORYMAP28_PHYSADDRMAP28_Msk (0x7feUL)              /*!< PHYSADDRMAP28 (Bitfield-Mask: 0x3ff)                  */
28925 /* ======================================================  MEMORYMAP29  ====================================================== */
28926 #define CRYPTO_MEMORYMAP29_PHYSADDRMAP29_Pos (1UL)                  /*!< PHYSADDRMAP29 (Bit 1)                                 */
28927 #define CRYPTO_MEMORYMAP29_PHYSADDRMAP29_Msk (0x7feUL)              /*!< PHYSADDRMAP29 (Bitfield-Mask: 0x3ff)                  */
28928 /* ======================================================  MEMORYMAP30  ====================================================== */
28929 #define CRYPTO_MEMORYMAP30_PHYSADDRMAP30_Pos (1UL)                  /*!< PHYSADDRMAP30 (Bit 1)                                 */
28930 #define CRYPTO_MEMORYMAP30_PHYSADDRMAP30_Msk (0x7feUL)              /*!< PHYSADDRMAP30 (Bitfield-Mask: 0x3ff)                  */
28931 /* ======================================================  MEMORYMAP31  ====================================================== */
28932 #define CRYPTO_MEMORYMAP31_PHYSADDRMAP31_Pos (1UL)                  /*!< PHYSADDRMAP31 (Bit 1)                                 */
28933 #define CRYPTO_MEMORYMAP31_PHYSADDRMAP31_Msk (0x7feUL)              /*!< PHYSADDRMAP31 (Bitfield-Mask: 0x3ff)                  */
28934 /* ========================================================  OPCODE  ========================================================= */
28935 #define CRYPTO_OPCODE_OPCODE_Pos          (27UL)                    /*!< OPCODE (Bit 27)                                       */
28936 #define CRYPTO_OPCODE_OPCODE_Msk          (0xf8000000UL)            /*!< OPCODE (Bitfield-Mask: 0x1f)                          */
28937 #define CRYPTO_OPCODE_LEN_Pos             (24UL)                    /*!< LEN (Bit 24)                                          */
28938 #define CRYPTO_OPCODE_LEN_Msk             (0x7000000UL)             /*!< LEN (Bitfield-Mask: 0x07)                             */
28939 #define CRYPTO_OPCODE_REGA_Pos            (18UL)                    /*!< REGA (Bit 18)                                         */
28940 #define CRYPTO_OPCODE_REGA_Msk            (0xfc0000UL)              /*!< REGA (Bitfield-Mask: 0x3f)                            */
28941 #define CRYPTO_OPCODE_REGB_Pos            (12UL)                    /*!< REGB (Bit 12)                                         */
28942 #define CRYPTO_OPCODE_REGB_Msk            (0x3f000UL)               /*!< REGB (Bitfield-Mask: 0x3f)                            */
28943 #define CRYPTO_OPCODE_REGR_Pos            (6UL)                     /*!< REGR (Bit 6)                                          */
28944 #define CRYPTO_OPCODE_REGR_Msk            (0xfc0UL)                 /*!< REGR (Bitfield-Mask: 0x3f)                            */
28945 #define CRYPTO_OPCODE_TAG_Pos             (0UL)                     /*!< TAG (Bit 0)                                           */
28946 #define CRYPTO_OPCODE_TAG_Msk             (0x3fUL)                  /*!< TAG (Bitfield-Mask: 0x3f)                             */
28947 /* ======================================================  NNPT0T1ADDR  ====================================================== */
28948 #define CRYPTO_NNPT0T1ADDR_T1VIRTUALADDR_Pos (15UL)                 /*!< T1VIRTUALADDR (Bit 15)                                */
28949 #define CRYPTO_NNPT0T1ADDR_T1VIRTUALADDR_Msk (0xf8000UL)            /*!< T1VIRTUALADDR (Bitfield-Mask: 0x1f)                   */
28950 #define CRYPTO_NNPT0T1ADDR_T0VIRTUALADDR_Pos (10UL)                 /*!< T0VIRTUALADDR (Bit 10)                                */
28951 #define CRYPTO_NNPT0T1ADDR_T0VIRTUALADDR_Msk (0x7c00UL)             /*!< T0VIRTUALADDR (Bitfield-Mask: 0x1f)                   */
28952 #define CRYPTO_NNPT0T1ADDR_NPVIRTUALADDR_Pos (5UL)                  /*!< NPVIRTUALADDR (Bit 5)                                 */
28953 #define CRYPTO_NNPT0T1ADDR_NPVIRTUALADDR_Msk (0x3e0UL)              /*!< NPVIRTUALADDR (Bitfield-Mask: 0x1f)                   */
28954 #define CRYPTO_NNPT0T1ADDR_NVIRTUALADDR_Pos (0UL)                   /*!< NVIRTUALADDR (Bit 0)                                  */
28955 #define CRYPTO_NNPT0T1ADDR_NVIRTUALADDR_Msk (0x1fUL)                /*!< NVIRTUALADDR (Bitfield-Mask: 0x1f)                    */
28956 /* =======================================================  PKASTATUS  ======================================================= */
28957 #define CRYPTO_PKASTATUS_OPCODE_Pos       (16UL)                    /*!< OPCODE (Bit 16)                                       */
28958 #define CRYPTO_PKASTATUS_OPCODE_Msk       (0x1f0000UL)              /*!< OPCODE (Bitfield-Mask: 0x1f)                          */
28959 #define CRYPTO_PKASTATUS_MODINVOFZERO_Pos (15UL)                    /*!< MODINVOFZERO (Bit 15)                                 */
28960 #define CRYPTO_PKASTATUS_MODINVOFZERO_Msk (0x8000UL)                /*!< MODINVOFZERO (Bitfield-Mask: 0x01)                    */
28961 #define CRYPTO_PKASTATUS_DIVBYZERO_Pos    (14UL)                    /*!< DIVBYZERO (Bit 14)                                    */
28962 #define CRYPTO_PKASTATUS_DIVBYZERO_Msk    (0x4000UL)                /*!< DIVBYZERO (Bitfield-Mask: 0x01)                       */
28963 #define CRYPTO_PKASTATUS_ALUMODOVRFLW_Pos (13UL)                    /*!< ALUMODOVRFLW (Bit 13)                                 */
28964 #define CRYPTO_PKASTATUS_ALUMODOVRFLW_Msk (0x2000UL)                /*!< ALUMODOVRFLW (Bitfield-Mask: 0x01)                    */
28965 #define CRYPTO_PKASTATUS_ALUOUTZERO_Pos   (12UL)                    /*!< ALUOUTZERO (Bit 12)                                   */
28966 #define CRYPTO_PKASTATUS_ALUOUTZERO_Msk   (0x1000UL)                /*!< ALUOUTZERO (Bitfield-Mask: 0x01)                      */
28967 #define CRYPTO_PKASTATUS_ALUSUBISZERO_Pos (11UL)                    /*!< ALUSUBISZERO (Bit 11)                                 */
28968 #define CRYPTO_PKASTATUS_ALUSUBISZERO_Msk (0x800UL)                 /*!< ALUSUBISZERO (Bitfield-Mask: 0x01)                    */
28969 #define CRYPTO_PKASTATUS_ALUCARRYMOD_Pos  (10UL)                    /*!< ALUCARRYMOD (Bit 10)                                  */
28970 #define CRYPTO_PKASTATUS_ALUCARRYMOD_Msk  (0x400UL)                 /*!< ALUCARRYMOD (Bitfield-Mask: 0x01)                     */
28971 #define CRYPTO_PKASTATUS_ALUCARRY_Pos     (9UL)                     /*!< ALUCARRY (Bit 9)                                      */
28972 #define CRYPTO_PKASTATUS_ALUCARRY_Msk     (0x200UL)                 /*!< ALUCARRY (Bitfield-Mask: 0x01)                        */
28973 #define CRYPTO_PKASTATUS_ALUSIGNOUT_Pos   (8UL)                     /*!< ALUSIGNOUT (Bit 8)                                    */
28974 #define CRYPTO_PKASTATUS_ALUSIGNOUT_Msk   (0x100UL)                 /*!< ALUSIGNOUT (Bitfield-Mask: 0x01)                      */
28975 #define CRYPTO_PKASTATUS_ALULSB4BITS_Pos  (4UL)                     /*!< ALULSB4BITS (Bit 4)                                   */
28976 #define CRYPTO_PKASTATUS_ALULSB4BITS_Msk  (0xf0UL)                  /*!< ALULSB4BITS (Bitfield-Mask: 0x0f)                     */
28977 #define CRYPTO_PKASTATUS_ALUMSB4BITS_Pos  (0UL)                     /*!< ALUMSB4BITS (Bit 0)                                   */
28978 #define CRYPTO_PKASTATUS_ALUMSB4BITS_Msk  (0xfUL)                   /*!< ALUMSB4BITS (Bitfield-Mask: 0x0f)                     */
28979 /* ======================================================  PKASWRESET  ======================================================= */
28980 #define CRYPTO_PKASWRESET_PKASWRESET_Pos  (0UL)                     /*!< PKASWRESET (Bit 0)                                    */
28981 #define CRYPTO_PKASWRESET_PKASWRESET_Msk  (0x1UL)                   /*!< PKASWRESET (Bitfield-Mask: 0x01)                      */
28982 /* =========================================================  PKAL0  ========================================================= */
28983 #define CRYPTO_PKAL0_PKAL0_Pos            (0UL)                     /*!< PKAL0 (Bit 0)                                         */
28984 #define CRYPTO_PKAL0_PKAL0_Msk            (0x1fffUL)                /*!< PKAL0 (Bitfield-Mask: 0x1fff)                         */
28985 /* =========================================================  PKAL1  ========================================================= */
28986 #define CRYPTO_PKAL1_PKAL1_Pos            (0UL)                     /*!< PKAL1 (Bit 0)                                         */
28987 #define CRYPTO_PKAL1_PKAL1_Msk            (0x1fffUL)                /*!< PKAL1 (Bitfield-Mask: 0x1fff)                         */
28988 /* =========================================================  PKAL2  ========================================================= */
28989 #define CRYPTO_PKAL2_PKAL2_Pos            (0UL)                     /*!< PKAL2 (Bit 0)                                         */
28990 #define CRYPTO_PKAL2_PKAL2_Msk            (0x1fffUL)                /*!< PKAL2 (Bitfield-Mask: 0x1fff)                         */
28991 /* =========================================================  PKAL3  ========================================================= */
28992 #define CRYPTO_PKAL3_PKAL3_Pos            (0UL)                     /*!< PKAL3 (Bit 0)                                         */
28993 #define CRYPTO_PKAL3_PKAL3_Msk            (0x1fffUL)                /*!< PKAL3 (Bitfield-Mask: 0x1fff)                         */
28994 /* =========================================================  PKAL4  ========================================================= */
28995 #define CRYPTO_PKAL4_PKAL4_Pos            (0UL)                     /*!< PKAL4 (Bit 0)                                         */
28996 #define CRYPTO_PKAL4_PKAL4_Msk            (0x1fffUL)                /*!< PKAL4 (Bitfield-Mask: 0x1fff)                         */
28997 /* =========================================================  PKAL5  ========================================================= */
28998 #define CRYPTO_PKAL5_PKAL5_Pos            (0UL)                     /*!< PKAL5 (Bit 0)                                         */
28999 #define CRYPTO_PKAL5_PKAL5_Msk            (0x1fffUL)                /*!< PKAL5 (Bitfield-Mask: 0x1fff)                         */
29000 /* =========================================================  PKAL6  ========================================================= */
29001 #define CRYPTO_PKAL6_PKAL6_Pos            (0UL)                     /*!< PKAL6 (Bit 0)                                         */
29002 #define CRYPTO_PKAL6_PKAL6_Msk            (0x1fffUL)                /*!< PKAL6 (Bitfield-Mask: 0x1fff)                         */
29003 /* =========================================================  PKAL7  ========================================================= */
29004 #define CRYPTO_PKAL7_PKAL7_Pos            (0UL)                     /*!< PKAL7 (Bit 0)                                         */
29005 #define CRYPTO_PKAL7_PKAL7_Msk            (0x1fffUL)                /*!< PKAL7 (Bitfield-Mask: 0x1fff)                         */
29006 /* ======================================================  PKAPIPERDY  ======================================================= */
29007 #define CRYPTO_PKAPIPERDY_PKAPIPERDY_Pos  (0UL)                     /*!< PKAPIPERDY (Bit 0)                                    */
29008 #define CRYPTO_PKAPIPERDY_PKAPIPERDY_Msk  (0x1UL)                   /*!< PKAPIPERDY (Bitfield-Mask: 0x01)                      */
29009 /* ========================================================  PKADONE  ======================================================== */
29010 #define CRYPTO_PKADONE_PKADONE_Pos        (0UL)                     /*!< PKADONE (Bit 0)                                       */
29011 #define CRYPTO_PKADONE_PKADONE_Msk        (0x1UL)                   /*!< PKADONE (Bitfield-Mask: 0x01)                         */
29012 /* =====================================================  PKAMONSELECT  ====================================================== */
29013 #define CRYPTO_PKAMONSELECT_PKAMONSELECT_Pos (0UL)                  /*!< PKAMONSELECT (Bit 0)                                  */
29014 #define CRYPTO_PKAMONSELECT_PKAMONSELECT_Msk (0xfUL)                /*!< PKAMONSELECT (Bitfield-Mask: 0x0f)                    */
29015 /* ======================================================  PKAVERSION  ======================================================= */
29016 #define CRYPTO_PKAVERSION_PKAVERSION_Pos  (0UL)                     /*!< PKAVERSION (Bit 0)                                    */
29017 #define CRYPTO_PKAVERSION_PKAVERSION_Msk  (0xffffffffUL)            /*!< PKAVERSION (Bitfield-Mask: 0xffffffff)                */
29018 /* ======================================================  PKAMONREAD  ======================================================= */
29019 #define CRYPTO_PKAMONREAD_PKAMONREAD_Pos  (0UL)                     /*!< PKAMONREAD (Bit 0)                                    */
29020 #define CRYPTO_PKAMONREAD_PKAMONREAD_Msk  (0xffffffffUL)            /*!< PKAMONREAD (Bitfield-Mask: 0xffffffff)                */
29021 /* ======================================================  PKASRAMADDR  ====================================================== */
29022 #define CRYPTO_PKASRAMADDR_PKASRAMADDR_Pos (0UL)                    /*!< PKASRAMADDR (Bit 0)                                   */
29023 #define CRYPTO_PKASRAMADDR_PKASRAMADDR_Msk (0xffffffffUL)           /*!< PKASRAMADDR (Bitfield-Mask: 0xffffffff)               */
29024 /* =====================================================  PKASRAMWDATA  ====================================================== */
29025 #define CRYPTO_PKASRAMWDATA_PKASRAMWDATA_Pos (0UL)                  /*!< PKASRAMWDATA (Bit 0)                                  */
29026 #define CRYPTO_PKASRAMWDATA_PKASRAMWDATA_Msk (0xffffffffUL)         /*!< PKASRAMWDATA (Bitfield-Mask: 0xffffffff)              */
29027 /* =====================================================  PKASRAMRDATA  ====================================================== */
29028 #define CRYPTO_PKASRAMRDATA_PKASRAMRDATA_Pos (0UL)                  /*!< PKASRAMRDATA (Bit 0)                                  */
29029 #define CRYPTO_PKASRAMRDATA_PKASRAMRDATA_Msk (0xffffffffUL)         /*!< PKASRAMRDATA (Bitfield-Mask: 0xffffffff)              */
29030 /* =====================================================  PKASRAMWRCLR  ====================================================== */
29031 #define CRYPTO_PKASRAMWRCLR_PKASRAMWRCLR_Pos (0UL)                  /*!< PKASRAMWRCLR (Bit 0)                                  */
29032 #define CRYPTO_PKASRAMWRCLR_PKASRAMWRCLR_Msk (0xffffffffUL)         /*!< PKASRAMWRCLR (Bitfield-Mask: 0xffffffff)              */
29033 /* =====================================================  PKASRAMRADDR  ====================================================== */
29034 #define CRYPTO_PKASRAMRADDR_PKASRAMRADDR_Pos (0UL)                  /*!< PKASRAMRADDR (Bit 0)                                  */
29035 #define CRYPTO_PKASRAMRADDR_PKASRAMRADDR_Msk (0xffffffffUL)         /*!< PKASRAMRADDR (Bitfield-Mask: 0xffffffff)              */
29036 /* =====================================================  PKAWORDACCESS  ===================================================== */
29037 #define CRYPTO_PKAWORDACCESS_PKAWORDACCESS_Pos (0UL)                /*!< PKAWORDACCESS (Bit 0)                                 */
29038 #define CRYPTO_PKAWORDACCESS_PKAWORDACCESS_Msk (0xffffffffUL)       /*!< PKAWORDACCESS (Bitfield-Mask: 0xffffffff)             */
29039 /* ======================================================  PKABUFFADDR  ====================================================== */
29040 #define CRYPTO_PKABUFFADDR_PKABUFADDR_Pos (0UL)                     /*!< PKABUFADDR (Bit 0)                                    */
29041 #define CRYPTO_PKABUFFADDR_PKABUFADDR_Msk (0xfffUL)                 /*!< PKABUFADDR (Bitfield-Mask: 0xfff)                     */
29042 /* ========================================================  RNGIMR  ========================================================= */
29043 #define CRYPTO_RNGIMR_RNGDMADONEINT_Pos   (5UL)                     /*!< RNGDMADONEINT (Bit 5)                                 */
29044 #define CRYPTO_RNGIMR_RNGDMADONEINT_Msk   (0x20UL)                  /*!< RNGDMADONEINT (Bitfield-Mask: 0x01)                   */
29045 #define CRYPTO_RNGIMR_WATCHDOGINTMASK_Pos (4UL)                     /*!< WATCHDOGINTMASK (Bit 4)                               */
29046 #define CRYPTO_RNGIMR_WATCHDOGINTMASK_Msk (0x10UL)                  /*!< WATCHDOGINTMASK (Bitfield-Mask: 0x01)                 */
29047 #define CRYPTO_RNGIMR_VNERRINTMASK_Pos    (3UL)                     /*!< VNERRINTMASK (Bit 3)                                  */
29048 #define CRYPTO_RNGIMR_VNERRINTMASK_Msk    (0x8UL)                   /*!< VNERRINTMASK (Bitfield-Mask: 0x01)                    */
29049 #define CRYPTO_RNGIMR_CRNGTERRINTMASK_Pos (2UL)                     /*!< CRNGTERRINTMASK (Bit 2)                               */
29050 #define CRYPTO_RNGIMR_CRNGTERRINTMASK_Msk (0x4UL)                   /*!< CRNGTERRINTMASK (Bitfield-Mask: 0x01)                 */
29051 #define CRYPTO_RNGIMR_AUTOCORRERRINTMASK_Pos (1UL)                  /*!< AUTOCORRERRINTMASK (Bit 1)                            */
29052 #define CRYPTO_RNGIMR_AUTOCORRERRINTMASK_Msk (0x2UL)                /*!< AUTOCORRERRINTMASK (Bitfield-Mask: 0x01)              */
29053 #define CRYPTO_RNGIMR_EHRVALIDINTMASK_Pos (0UL)                     /*!< EHRVALIDINTMASK (Bit 0)                               */
29054 #define CRYPTO_RNGIMR_EHRVALIDINTMASK_Msk (0x1UL)                   /*!< EHRVALIDINTMASK (Bitfield-Mask: 0x01)                 */
29055 /* ========================================================  RNGISR  ========================================================= */
29056 #define CRYPTO_RNGISR_WHICHKATERR_Pos     (25UL)                    /*!< WHICHKATERR (Bit 25)                                  */
29057 #define CRYPTO_RNGISR_WHICHKATERR_Msk     (0x6000000UL)             /*!< WHICHKATERR (Bitfield-Mask: 0x03)                     */
29058 #define CRYPTO_RNGISR_KATERR_Pos          (24UL)                    /*!< KATERR (Bit 24)                                       */
29059 #define CRYPTO_RNGISR_KATERR_Msk          (0x1000000UL)             /*!< KATERR (Bitfield-Mask: 0x01)                          */
29060 #define CRYPTO_RNGISR_REQSIZE_Pos         (23UL)                    /*!< REQSIZE (Bit 23)                                      */
29061 #define CRYPTO_RNGISR_REQSIZE_Msk         (0x800000UL)              /*!< REQSIZE (Bitfield-Mask: 0x01)                         */
29062 #define CRYPTO_RNGISR_PRNGCRNGTERR_Pos    (22UL)                    /*!< PRNGCRNGTERR (Bit 22)                                 */
29063 #define CRYPTO_RNGISR_PRNGCRNGTERR_Msk    (0x400000UL)              /*!< PRNGCRNGTERR (Bitfield-Mask: 0x01)                    */
29064 #define CRYPTO_RNGISR_RESEEDCNTRTOP40_Pos (21UL)                    /*!< RESEEDCNTRTOP40 (Bit 21)                              */
29065 #define CRYPTO_RNGISR_RESEEDCNTRTOP40_Msk (0x200000UL)              /*!< RESEEDCNTRTOP40 (Bitfield-Mask: 0x01)                 */
29066 #define CRYPTO_RNGISR_RESEEDCNTRFULL_Pos  (20UL)                    /*!< RESEEDCNTRFULL (Bit 20)                               */
29067 #define CRYPTO_RNGISR_RESEEDCNTRFULL_Msk  (0x100000UL)              /*!< RESEEDCNTRFULL (Bitfield-Mask: 0x01)                  */
29068 #define CRYPTO_RNGISR_OUTPUTREADY_Pos     (19UL)                    /*!< OUTPUTREADY (Bit 19)                                  */
29069 #define CRYPTO_RNGISR_OUTPUTREADY_Msk     (0x80000UL)               /*!< OUTPUTREADY (Bitfield-Mask: 0x01)                     */
29070 #define CRYPTO_RNGISR_FINALUPDATEDONE_Pos (18UL)                    /*!< FINALUPDATEDONE (Bit 18)                              */
29071 #define CRYPTO_RNGISR_FINALUPDATEDONE_Msk (0x40000UL)               /*!< FINALUPDATEDONE (Bitfield-Mask: 0x01)                 */
29072 #define CRYPTO_RNGISR_INSTANTIATIONDONE_Pos (17UL)                  /*!< INSTANTIATIONDONE (Bit 17)                            */
29073 #define CRYPTO_RNGISR_INSTANTIATIONDONE_Msk (0x20000UL)             /*!< INSTANTIATIONDONE (Bitfield-Mask: 0x01)               */
29074 #define CRYPTO_RNGISR_RESEEDINGDONE_Pos   (16UL)                    /*!< RESEEDINGDONE (Bit 16)                                */
29075 #define CRYPTO_RNGISR_RESEEDINGDONE_Msk   (0x10000UL)               /*!< RESEEDINGDONE (Bitfield-Mask: 0x01)                   */
29076 #define CRYPTO_RNGISR_RNGDMADONE_Pos      (5UL)                     /*!< RNGDMADONE (Bit 5)                                    */
29077 #define CRYPTO_RNGISR_RNGDMADONE_Msk      (0x20UL)                  /*!< RNGDMADONE (Bitfield-Mask: 0x01)                      */
29078 #define CRYPTO_RNGISR_VNERR_Pos           (3UL)                     /*!< VNERR (Bit 3)                                         */
29079 #define CRYPTO_RNGISR_VNERR_Msk           (0x8UL)                   /*!< VNERR (Bitfield-Mask: 0x01)                           */
29080 #define CRYPTO_RNGISR_CRNGTERR_Pos        (2UL)                     /*!< CRNGTERR (Bit 2)                                      */
29081 #define CRYPTO_RNGISR_CRNGTERR_Msk        (0x4UL)                   /*!< CRNGTERR (Bitfield-Mask: 0x01)                        */
29082 #define CRYPTO_RNGISR_AUTOCORRERR_Pos     (1UL)                     /*!< AUTOCORRERR (Bit 1)                                   */
29083 #define CRYPTO_RNGISR_AUTOCORRERR_Msk     (0x2UL)                   /*!< AUTOCORRERR (Bitfield-Mask: 0x01)                     */
29084 #define CRYPTO_RNGISR_EHRVALID_Pos        (0UL)                     /*!< EHRVALID (Bit 0)                                      */
29085 #define CRYPTO_RNGISR_EHRVALID_Msk        (0x1UL)                   /*!< EHRVALID (Bitfield-Mask: 0x01)                        */
29086 /* ========================================================  RNGICR  ========================================================= */
29087 #define CRYPTO_RNGICR_WHICHKATERR_Pos     (25UL)                    /*!< WHICHKATERR (Bit 25)                                  */
29088 #define CRYPTO_RNGICR_WHICHKATERR_Msk     (0x6000000UL)             /*!< WHICHKATERR (Bitfield-Mask: 0x03)                     */
29089 #define CRYPTO_RNGICR_KATERR_Pos          (24UL)                    /*!< KATERR (Bit 24)                                       */
29090 #define CRYPTO_RNGICR_KATERR_Msk          (0x1000000UL)             /*!< KATERR (Bitfield-Mask: 0x01)                          */
29091 #define CRYPTO_RNGICR_REQSIZE_Pos         (23UL)                    /*!< REQSIZE (Bit 23)                                      */
29092 #define CRYPTO_RNGICR_REQSIZE_Msk         (0x800000UL)              /*!< REQSIZE (Bitfield-Mask: 0x01)                         */
29093 #define CRYPTO_RNGICR_PRNGCRNGTERR_Pos    (22UL)                    /*!< PRNGCRNGTERR (Bit 22)                                 */
29094 #define CRYPTO_RNGICR_PRNGCRNGTERR_Msk    (0x400000UL)              /*!< PRNGCRNGTERR (Bitfield-Mask: 0x01)                    */
29095 #define CRYPTO_RNGICR_RESEEDCNTRTOP40_Pos (21UL)                    /*!< RESEEDCNTRTOP40 (Bit 21)                              */
29096 #define CRYPTO_RNGICR_RESEEDCNTRTOP40_Msk (0x200000UL)              /*!< RESEEDCNTRTOP40 (Bitfield-Mask: 0x01)                 */
29097 #define CRYPTO_RNGICR_RESEEDCNTRFULL_Pos  (20UL)                    /*!< RESEEDCNTRFULL (Bit 20)                               */
29098 #define CRYPTO_RNGICR_RESEEDCNTRFULL_Msk  (0x100000UL)              /*!< RESEEDCNTRFULL (Bitfield-Mask: 0x01)                  */
29099 #define CRYPTO_RNGICR_OUTPUTREADY_Pos     (19UL)                    /*!< OUTPUTREADY (Bit 19)                                  */
29100 #define CRYPTO_RNGICR_OUTPUTREADY_Msk     (0x80000UL)               /*!< OUTPUTREADY (Bitfield-Mask: 0x01)                     */
29101 #define CRYPTO_RNGICR_FINALUPDATEDONE_Pos (18UL)                    /*!< FINALUPDATEDONE (Bit 18)                              */
29102 #define CRYPTO_RNGICR_FINALUPDATEDONE_Msk (0x40000UL)               /*!< FINALUPDATEDONE (Bitfield-Mask: 0x01)                 */
29103 #define CRYPTO_RNGICR_INSTANTIATIONDONE_Pos (17UL)                  /*!< INSTANTIATIONDONE (Bit 17)                            */
29104 #define CRYPTO_RNGICR_INSTANTIATIONDONE_Msk (0x20000UL)             /*!< INSTANTIATIONDONE (Bitfield-Mask: 0x01)               */
29105 #define CRYPTO_RNGICR_RESEEDINGDONE_Pos   (16UL)                    /*!< RESEEDINGDONE (Bit 16)                                */
29106 #define CRYPTO_RNGICR_RESEEDINGDONE_Msk   (0x10000UL)               /*!< RESEEDINGDONE (Bitfield-Mask: 0x01)                   */
29107 #define CRYPTO_RNGICR_RNGDMADONE_Pos      (5UL)                     /*!< RNGDMADONE (Bit 5)                                    */
29108 #define CRYPTO_RNGICR_RNGDMADONE_Msk      (0x20UL)                  /*!< RNGDMADONE (Bitfield-Mask: 0x01)                      */
29109 #define CRYPTO_RNGICR_RNGWATCHDOG_Pos     (4UL)                     /*!< RNGWATCHDOG (Bit 4)                                   */
29110 #define CRYPTO_RNGICR_RNGWATCHDOG_Msk     (0x10UL)                  /*!< RNGWATCHDOG (Bitfield-Mask: 0x01)                     */
29111 #define CRYPTO_RNGICR_VNERR_Pos           (3UL)                     /*!< VNERR (Bit 3)                                         */
29112 #define CRYPTO_RNGICR_VNERR_Msk           (0x8UL)                   /*!< VNERR (Bitfield-Mask: 0x01)                           */
29113 #define CRYPTO_RNGICR_CRNGTERR_Pos        (2UL)                     /*!< CRNGTERR (Bit 2)                                      */
29114 #define CRYPTO_RNGICR_CRNGTERR_Msk        (0x4UL)                   /*!< CRNGTERR (Bitfield-Mask: 0x01)                        */
29115 #define CRYPTO_RNGICR_AUTOCORRERR_Pos     (1UL)                     /*!< AUTOCORRERR (Bit 1)                                   */
29116 #define CRYPTO_RNGICR_AUTOCORRERR_Msk     (0x2UL)                   /*!< AUTOCORRERR (Bitfield-Mask: 0x01)                     */
29117 #define CRYPTO_RNGICR_EHRVALID_Pos        (0UL)                     /*!< EHRVALID (Bit 0)                                      */
29118 #define CRYPTO_RNGICR_EHRVALID_Msk        (0x1UL)                   /*!< EHRVALID (Bitfield-Mask: 0x01)                        */
29119 /* ======================================================  TRNGCONFIG  ======================================================= */
29120 #define CRYPTO_TRNGCONFIG_SOPSEL_Pos      (2UL)                     /*!< SOPSEL (Bit 2)                                        */
29121 #define CRYPTO_TRNGCONFIG_SOPSEL_Msk      (0x4UL)                   /*!< SOPSEL (Bitfield-Mask: 0x01)                          */
29122 #define CRYPTO_TRNGCONFIG_RNDSRCSEL_Pos   (0UL)                     /*!< RNDSRCSEL (Bit 0)                                     */
29123 #define CRYPTO_TRNGCONFIG_RNDSRCSEL_Msk   (0x3UL)                   /*!< RNDSRCSEL (Bitfield-Mask: 0x03)                       */
29124 /* =======================================================  TRNGVALID  ======================================================= */
29125 #define CRYPTO_TRNGVALID_EHRVALID_Pos     (0UL)                     /*!< EHRVALID (Bit 0)                                      */
29126 #define CRYPTO_TRNGVALID_EHRVALID_Msk     (0x1UL)                   /*!< EHRVALID (Bitfield-Mask: 0x01)                        */
29127 /* =======================================================  EHRDATA0  ======================================================== */
29128 #define CRYPTO_EHRDATA0_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
29129 #define CRYPTO_EHRDATA0_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
29130 /* =======================================================  EHRDATA1  ======================================================== */
29131 #define CRYPTO_EHRDATA1_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
29132 #define CRYPTO_EHRDATA1_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
29133 /* =======================================================  EHRDATA2  ======================================================== */
29134 #define CRYPTO_EHRDATA2_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
29135 #define CRYPTO_EHRDATA2_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
29136 /* =======================================================  EHRDATA3  ======================================================== */
29137 #define CRYPTO_EHRDATA3_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
29138 #define CRYPTO_EHRDATA3_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
29139 /* =======================================================  EHRDATA4  ======================================================== */
29140 #define CRYPTO_EHRDATA4_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
29141 #define CRYPTO_EHRDATA4_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
29142 /* =======================================================  EHRDATA5  ======================================================== */
29143 #define CRYPTO_EHRDATA5_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
29144 #define CRYPTO_EHRDATA5_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
29145 /* ====================================================  RNDSOURCEENABLE  ==================================================== */
29146 #define CRYPTO_RNDSOURCEENABLE_RNDSRCEN_Pos (0UL)                   /*!< RNDSRCEN (Bit 0)                                      */
29147 #define CRYPTO_RNDSOURCEENABLE_RNDSRCEN_Msk (0x1UL)                 /*!< RNDSRCEN (Bitfield-Mask: 0x01)                        */
29148 /* ======================================================  SAMPLECNT1  ======================================================= */
29149 #define CRYPTO_SAMPLECNT1_SAMPLECNTR1_Pos (0UL)                     /*!< SAMPLECNTR1 (Bit 0)                                   */
29150 #define CRYPTO_SAMPLECNT1_SAMPLECNTR1_Msk (0xffffffffUL)            /*!< SAMPLECNTR1 (Bitfield-Mask: 0xffffffff)               */
29151 /* ===================================================  AUTOCORRSTATISTIC  =================================================== */
29152 #define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRFAILS_Pos (14UL)           /*!< AUTOCORRFAILS (Bit 14)                                */
29153 #define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRFAILS_Msk (0x3fc000UL)     /*!< AUTOCORRFAILS (Bitfield-Mask: 0xff)                   */
29154 #define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRTRYS_Pos (0UL)             /*!< AUTOCORRTRYS (Bit 0)                                  */
29155 #define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRTRYS_Msk (0x3fffUL)        /*!< AUTOCORRTRYS (Bitfield-Mask: 0x3fff)                  */
29156 /* ===================================================  TRNGDEBUGCONTROL  ==================================================== */
29157 #define CRYPTO_TRNGDEBUGCONTROL_AUTOCORRELATEBYPASS_Pos (3UL)       /*!< AUTOCORRELATEBYPASS (Bit 3)                           */
29158 #define CRYPTO_TRNGDEBUGCONTROL_AUTOCORRELATEBYPASS_Msk (0x8UL)     /*!< AUTOCORRELATEBYPASS (Bitfield-Mask: 0x01)             */
29159 #define CRYPTO_TRNGDEBUGCONTROL_TRNGCRNGTBYPASS_Pos (2UL)           /*!< TRNGCRNGTBYPASS (Bit 2)                               */
29160 #define CRYPTO_TRNGDEBUGCONTROL_TRNGCRNGTBYPASS_Msk (0x4UL)         /*!< TRNGCRNGTBYPASS (Bitfield-Mask: 0x01)                 */
29161 #define CRYPTO_TRNGDEBUGCONTROL_VNCBYPASS_Pos (1UL)                 /*!< VNCBYPASS (Bit 1)                                     */
29162 #define CRYPTO_TRNGDEBUGCONTROL_VNCBYPASS_Msk (0x2UL)               /*!< VNCBYPASS (Bitfield-Mask: 0x01)                       */
29163 /* ======================================================  RNGSWRESET  ======================================================= */
29164 #define CRYPTO_RNGSWRESET_RNGSWRESET_Pos  (0UL)                     /*!< RNGSWRESET (Bit 0)                                    */
29165 #define CRYPTO_RNGSWRESET_RNGSWRESET_Msk  (0x1UL)                   /*!< RNGSWRESET (Bitfield-Mask: 0x01)                      */
29166 /* ====================================================  RNGDEBUGENINPUT  ==================================================== */
29167 #define CRYPTO_RNGDEBUGENINPUT_RNGDEBUGEN_Pos (0UL)                 /*!< RNGDEBUGEN (Bit 0)                                    */
29168 #define CRYPTO_RNGDEBUGENINPUT_RNGDEBUGEN_Msk (0x1UL)               /*!< RNGDEBUGEN (Bitfield-Mask: 0x01)                      */
29169 /* ========================================================  RNGBUSY  ======================================================== */
29170 #define CRYPTO_RNGBUSY_PRNGBUSY_Pos       (2UL)                     /*!< PRNGBUSY (Bit 2)                                      */
29171 #define CRYPTO_RNGBUSY_PRNGBUSY_Msk       (0x4UL)                   /*!< PRNGBUSY (Bitfield-Mask: 0x01)                        */
29172 #define CRYPTO_RNGBUSY_TRNGBUSY_Pos       (1UL)                     /*!< TRNGBUSY (Bit 1)                                      */
29173 #define CRYPTO_RNGBUSY_TRNGBUSY_Msk       (0x2UL)                   /*!< TRNGBUSY (Bitfield-Mask: 0x01)                        */
29174 #define CRYPTO_RNGBUSY_RNGBUSY_Pos        (0UL)                     /*!< RNGBUSY (Bit 0)                                       */
29175 #define CRYPTO_RNGBUSY_RNGBUSY_Msk        (0x1UL)                   /*!< RNGBUSY (Bitfield-Mask: 0x01)                         */
29176 /* ====================================================  RSTBITSCOUNTER  ===================================================== */
29177 #define CRYPTO_RSTBITSCOUNTER_RSTBITSCOUNTER_Pos (0UL)              /*!< RSTBITSCOUNTER (Bit 0)                                */
29178 #define CRYPTO_RSTBITSCOUNTER_RSTBITSCOUNTER_Msk (0x1UL)            /*!< RSTBITSCOUNTER (Bitfield-Mask: 0x01)                  */
29179 /* ======================================================  RNGVERSION  ======================================================= */
29180 #define CRYPTO_RNGVERSION_RNGUSE5SBOXES_Pos (7UL)                   /*!< RNGUSE5SBOXES (Bit 7)                                 */
29181 #define CRYPTO_RNGVERSION_RNGUSE5SBOXES_Msk (0x80UL)                /*!< RNGUSE5SBOXES (Bitfield-Mask: 0x01)                   */
29182 #define CRYPTO_RNGVERSION_RESEEDINGEXISTS_Pos (6UL)                 /*!< RESEEDINGEXISTS (Bit 6)                               */
29183 #define CRYPTO_RNGVERSION_RESEEDINGEXISTS_Msk (0x40UL)              /*!< RESEEDINGEXISTS (Bitfield-Mask: 0x01)                 */
29184 #define CRYPTO_RNGVERSION_KATEXISTS_Pos   (5UL)                     /*!< KATEXISTS (Bit 5)                                     */
29185 #define CRYPTO_RNGVERSION_KATEXISTS_Msk   (0x20UL)                  /*!< KATEXISTS (Bitfield-Mask: 0x01)                       */
29186 #define CRYPTO_RNGVERSION_PRNGEXISTS_Pos  (4UL)                     /*!< PRNGEXISTS (Bit 4)                                    */
29187 #define CRYPTO_RNGVERSION_PRNGEXISTS_Msk  (0x10UL)                  /*!< PRNGEXISTS (Bitfield-Mask: 0x01)                      */
29188 #define CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Pos (3UL)               /*!< TRNGTESTSBYPASSEN (Bit 3)                             */
29189 #define CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Msk (0x8UL)             /*!< TRNGTESTSBYPASSEN (Bitfield-Mask: 0x01)               */
29190 #define CRYPTO_RNGVERSION_AUTOCORREXISTS_Pos (2UL)                  /*!< AUTOCORREXISTS (Bit 2)                                */
29191 #define CRYPTO_RNGVERSION_AUTOCORREXISTS_Msk (0x4UL)                /*!< AUTOCORREXISTS (Bitfield-Mask: 0x01)                  */
29192 #define CRYPTO_RNGVERSION_CRNGTEXISTS_Pos (1UL)                     /*!< CRNGTEXISTS (Bit 1)                                   */
29193 #define CRYPTO_RNGVERSION_CRNGTEXISTS_Msk (0x2UL)                   /*!< CRNGTEXISTS (Bitfield-Mask: 0x01)                     */
29194 #define CRYPTO_RNGVERSION_EHRWIDTH192_Pos (0UL)                     /*!< EHRWIDTH192 (Bit 0)                                   */
29195 #define CRYPTO_RNGVERSION_EHRWIDTH192_Msk (0x1UL)                   /*!< EHRWIDTH192 (Bitfield-Mask: 0x01)                     */
29196 /* =====================================================  RNGCLKENABLE  ====================================================== */
29197 #define CRYPTO_RNGCLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
29198 #define CRYPTO_RNGCLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29199 /* =====================================================  RNGDMAENABLE  ====================================================== */
29200 #define CRYPTO_RNGDMAENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
29201 #define CRYPTO_RNGDMAENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29202 /* =====================================================  RNGDMASRCMASK  ===================================================== */
29203 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL3_Pos (3UL)                    /*!< ENSRCSEL3 (Bit 3)                                     */
29204 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL3_Msk (0x8UL)                  /*!< ENSRCSEL3 (Bitfield-Mask: 0x01)                       */
29205 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL2_Pos (2UL)                    /*!< ENSRCSEL2 (Bit 2)                                     */
29206 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL2_Msk (0x4UL)                  /*!< ENSRCSEL2 (Bitfield-Mask: 0x01)                       */
29207 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL1_Pos (1UL)                    /*!< ENSRCSEL1 (Bit 1)                                     */
29208 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL1_Msk (0x2UL)                  /*!< ENSRCSEL1 (Bitfield-Mask: 0x01)                       */
29209 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL0_Pos (0UL)                    /*!< ENSRCSEL0 (Bit 0)                                     */
29210 #define CRYPTO_RNGDMASRCMASK_ENSRCSEL0_Msk (0x1UL)                  /*!< ENSRCSEL0 (Bitfield-Mask: 0x01)                       */
29211 /* ====================================================  RNGDMASRAMADDR  ===================================================== */
29212 #define CRYPTO_RNGDMASRAMADDR_RNGSRAMDMAADDR_Pos (0UL)              /*!< RNGSRAMDMAADDR (Bit 0)                                */
29213 #define CRYPTO_RNGDMASRAMADDR_RNGSRAMDMAADDR_Msk (0x7ffUL)          /*!< RNGSRAMDMAADDR (Bitfield-Mask: 0x7ff)                 */
29214 /* ====================================================  RNGWATCHDOGVAL  ===================================================== */
29215 #define CRYPTO_RNGWATCHDOGVAL_RNGWATCHDOGVAL_Pos (0UL)              /*!< RNGWATCHDOGVAL (Bit 0)                                */
29216 #define CRYPTO_RNGWATCHDOGVAL_RNGWATCHDOGVAL_Msk (0xffffffffUL)     /*!< RNGWATCHDOGVAL (Bitfield-Mask: 0xffffffff)            */
29217 /* =====================================================  RNGDMASTATUS  ====================================================== */
29218 #define CRYPTO_RNGDMASTATUS_NUMOFSAMPLES_Pos (3UL)                  /*!< NUMOFSAMPLES (Bit 3)                                  */
29219 #define CRYPTO_RNGDMASTATUS_NUMOFSAMPLES_Msk (0x7f8UL)              /*!< NUMOFSAMPLES (Bitfield-Mask: 0xff)                    */
29220 #define CRYPTO_RNGDMASTATUS_DMASRCSEL_Pos (1UL)                     /*!< DMASRCSEL (Bit 1)                                     */
29221 #define CRYPTO_RNGDMASTATUS_DMASRCSEL_Msk (0x6UL)                   /*!< DMASRCSEL (Bitfield-Mask: 0x03)                       */
29222 #define CRYPTO_RNGDMASTATUS_RNGDMABUSY_Pos (0UL)                    /*!< RNGDMABUSY (Bit 0)                                    */
29223 #define CRYPTO_RNGDMASTATUS_RNGDMABUSY_Msk (0x1UL)                  /*!< RNGDMABUSY (Bitfield-Mask: 0x01)                      */
29224 /* ===================================================  CHACHACONTROLREG  ==================================================== */
29225 #define CRYPTO_CHACHACONTROLREG_USEIV96BIT_Pos (10UL)               /*!< USEIV96BIT (Bit 10)                                   */
29226 #define CRYPTO_CHACHACONTROLREG_USEIV96BIT_Msk (0x400UL)            /*!< USEIV96BIT (Bitfield-Mask: 0x01)                      */
29227 #define CRYPTO_CHACHACONTROLREG_RESETBLOCKCNT_Pos (9UL)             /*!< RESETBLOCKCNT (Bit 9)                                 */
29228 #define CRYPTO_CHACHACONTROLREG_RESETBLOCKCNT_Msk (0x200UL)         /*!< RESETBLOCKCNT (Bitfield-Mask: 0x01)                   */
29229 #define CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Pos (4UL)               /*!< NUMOFROUNDS (Bit 4)                                   */
29230 #define CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Msk (0x30UL)            /*!< NUMOFROUNDS (Bitfield-Mask: 0x03)                     */
29231 #define CRYPTO_CHACHACONTROLREG_KEYLEN_Pos (3UL)                    /*!< KEYLEN (Bit 3)                                        */
29232 #define CRYPTO_CHACHACONTROLREG_KEYLEN_Msk (0x8UL)                  /*!< KEYLEN (Bitfield-Mask: 0x01)                          */
29233 #define CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Pos (2UL)        /*!< CALCKEYFORPOLY1305 (Bit 2)                            */
29234 #define CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Msk (0x4UL)      /*!< CALCKEYFORPOLY1305 (Bitfield-Mask: 0x01)              */
29235 #define CRYPTO_CHACHACONTROLREG_INITFROMHOST_Pos (1UL)              /*!< INITFROMHOST (Bit 1)                                  */
29236 #define CRYPTO_CHACHACONTROLREG_INITFROMHOST_Msk (0x2UL)            /*!< INITFROMHOST (Bitfield-Mask: 0x01)                    */
29237 #define CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Pos (0UL)             /*!< CHACHAORSALSA (Bit 0)                                 */
29238 #define CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Msk (0x1UL)           /*!< CHACHAORSALSA (Bitfield-Mask: 0x01)                   */
29239 /* =====================================================  CHACHAVERSION  ===================================================== */
29240 #define CRYPTO_CHACHAVERSION_CHACHAVERSION_Pos (0UL)                /*!< CHACHAVERSION (Bit 0)                                 */
29241 #define CRYPTO_CHACHAVERSION_CHACHAVERSION_Msk (0xffffffffUL)       /*!< CHACHAVERSION (Bitfield-Mask: 0xffffffff)             */
29242 /* ======================================================  CHACHAKEY0  ======================================================= */
29243 #define CRYPTO_CHACHAKEY0_CHACHAKEY0_Pos  (0UL)                     /*!< CHACHAKEY0 (Bit 0)                                    */
29244 #define CRYPTO_CHACHAKEY0_CHACHAKEY0_Msk  (0xffffffffUL)            /*!< CHACHAKEY0 (Bitfield-Mask: 0xffffffff)                */
29245 /* ======================================================  CHACHAKEY1  ======================================================= */
29246 #define CRYPTO_CHACHAKEY1_CHACHAKEY1_Pos  (0UL)                     /*!< CHACHAKEY1 (Bit 0)                                    */
29247 #define CRYPTO_CHACHAKEY1_CHACHAKEY1_Msk  (0xffffffffUL)            /*!< CHACHAKEY1 (Bitfield-Mask: 0xffffffff)                */
29248 /* ======================================================  CHACHAKEY2  ======================================================= */
29249 #define CRYPTO_CHACHAKEY2_CHACHAKEY2_Pos  (0UL)                     /*!< CHACHAKEY2 (Bit 0)                                    */
29250 #define CRYPTO_CHACHAKEY2_CHACHAKEY2_Msk  (0xffffffffUL)            /*!< CHACHAKEY2 (Bitfield-Mask: 0xffffffff)                */
29251 /* ======================================================  CHACHAKEY3  ======================================================= */
29252 #define CRYPTO_CHACHAKEY3_CHACHAKEY3_Pos  (0UL)                     /*!< CHACHAKEY3 (Bit 0)                                    */
29253 #define CRYPTO_CHACHAKEY3_CHACHAKEY3_Msk  (0xffffffffUL)            /*!< CHACHAKEY3 (Bitfield-Mask: 0xffffffff)                */
29254 /* ======================================================  CHACHAKEY4  ======================================================= */
29255 #define CRYPTO_CHACHAKEY4_CHACHAKEY4_Pos  (0UL)                     /*!< CHACHAKEY4 (Bit 0)                                    */
29256 #define CRYPTO_CHACHAKEY4_CHACHAKEY4_Msk  (0xffffffffUL)            /*!< CHACHAKEY4 (Bitfield-Mask: 0xffffffff)                */
29257 /* ======================================================  CHACHAKEY5  ======================================================= */
29258 #define CRYPTO_CHACHAKEY5_CHACHAKEY5_Pos  (0UL)                     /*!< CHACHAKEY5 (Bit 0)                                    */
29259 #define CRYPTO_CHACHAKEY5_CHACHAKEY5_Msk  (0xffffffffUL)            /*!< CHACHAKEY5 (Bitfield-Mask: 0xffffffff)                */
29260 /* ======================================================  CHACHAKEY6  ======================================================= */
29261 #define CRYPTO_CHACHAKEY6_CHACHAKEY6_Pos  (0UL)                     /*!< CHACHAKEY6 (Bit 0)                                    */
29262 #define CRYPTO_CHACHAKEY6_CHACHAKEY6_Msk  (0xffffffffUL)            /*!< CHACHAKEY6 (Bitfield-Mask: 0xffffffff)                */
29263 /* ======================================================  CHACHAKEY7  ======================================================= */
29264 #define CRYPTO_CHACHAKEY7_CHACHAKEY7_Pos  (0UL)                     /*!< CHACHAKEY7 (Bit 0)                                    */
29265 #define CRYPTO_CHACHAKEY7_CHACHAKEY7_Msk  (0xffffffffUL)            /*!< CHACHAKEY7 (Bitfield-Mask: 0xffffffff)                */
29266 /* =======================================================  CHACHAIV0  ======================================================= */
29267 #define CRYPTO_CHACHAIV0_CHACHAIV0_Pos    (0UL)                     /*!< CHACHAIV0 (Bit 0)                                     */
29268 #define CRYPTO_CHACHAIV0_CHACHAIV0_Msk    (0xffffffffUL)            /*!< CHACHAIV0 (Bitfield-Mask: 0xffffffff)                 */
29269 /* =======================================================  CHACHAIV1  ======================================================= */
29270 #define CRYPTO_CHACHAIV1_CHACHAIV1_Pos    (0UL)                     /*!< CHACHAIV1 (Bit 0)                                     */
29271 #define CRYPTO_CHACHAIV1_CHACHAIV1_Msk    (0xffffffffUL)            /*!< CHACHAIV1 (Bitfield-Mask: 0xffffffff)                 */
29272 /* ======================================================  CHACHABUSY  ======================================================= */
29273 #define CRYPTO_CHACHABUSY_CHACHABUSY_Pos  (0UL)                     /*!< CHACHABUSY (Bit 0)                                    */
29274 #define CRYPTO_CHACHABUSY_CHACHABUSY_Msk  (0x1UL)                   /*!< CHACHABUSY (Bitfield-Mask: 0x01)                      */
29275 /* =====================================================  CHACHAHWFLAGS  ===================================================== */
29276 #define CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Pos (2UL)                   /*!< FASTCHACHA (Bit 2)                                    */
29277 #define CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Msk (0x4UL)                 /*!< FASTCHACHA (Bitfield-Mask: 0x01)                      */
29278 #define CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Pos (1UL)                  /*!< SALSAEXISTS (Bit 1)                                   */
29279 #define CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Msk (0x2UL)                /*!< SALSAEXISTS (Bitfield-Mask: 0x01)                     */
29280 #define CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Pos (0UL)                 /*!< CHACHAEXISTS (Bit 0)                                  */
29281 #define CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Msk (0x1UL)               /*!< CHACHAEXISTS (Bitfield-Mask: 0x01)                    */
29282 /* ===================================================  CHACHABLOCKCNTLSB  =================================================== */
29283 #define CRYPTO_CHACHABLOCKCNTLSB_CHACHABLOCKCNTLSB_Pos (0UL)        /*!< CHACHABLOCKCNTLSB (Bit 0)                             */
29284 #define CRYPTO_CHACHABLOCKCNTLSB_CHACHABLOCKCNTLSB_Msk (0xffffffffUL) /*!< CHACHABLOCKCNTLSB (Bitfield-Mask: 0xffffffff)       */
29285 /* ===================================================  CHACHABLOCKCNTMSB  =================================================== */
29286 #define CRYPTO_CHACHABLOCKCNTMSB_CHACHABLOCKCNTMSB_Pos (0UL)        /*!< CHACHABLOCKCNTMSB (Bit 0)                             */
29287 #define CRYPTO_CHACHABLOCKCNTMSB_CHACHABLOCKCNTMSB_Msk (0xffffffffUL) /*!< CHACHABLOCKCNTMSB (Bitfield-Mask: 0xffffffff)       */
29288 /* =====================================================  CHACHASWRESET  ===================================================== */
29289 #define CRYPTO_CHACHASWRESET_CHACHSWRESET_Pos (0UL)                 /*!< CHACHSWRESET (Bit 0)                                  */
29290 #define CRYPTO_CHACHASWRESET_CHACHSWRESET_Msk (0x1UL)               /*!< CHACHSWRESET (Bitfield-Mask: 0x01)                    */
29291 /* ===================================================  CHACHAFORPOLYKEY0  =================================================== */
29292 #define CRYPTO_CHACHAFORPOLYKEY0_CHACHAFORPOLYKEY0_Pos (0UL)        /*!< CHACHAFORPOLYKEY0 (Bit 0)                             */
29293 #define CRYPTO_CHACHAFORPOLYKEY0_CHACHAFORPOLYKEY0_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY0 (Bitfield-Mask: 0xffffffff)       */
29294 /* ===================================================  CHACHAFORPOLYKEY1  =================================================== */
29295 #define CRYPTO_CHACHAFORPOLYKEY1_CHACHAFORPOLYKEY1_Pos (0UL)        /*!< CHACHAFORPOLYKEY1 (Bit 0)                             */
29296 #define CRYPTO_CHACHAFORPOLYKEY1_CHACHAFORPOLYKEY1_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY1 (Bitfield-Mask: 0xffffffff)       */
29297 /* ===================================================  CHACHAFORPOLYKEY2  =================================================== */
29298 #define CRYPTO_CHACHAFORPOLYKEY2_CHACHAFORPOLYKEY2_Pos (0UL)        /*!< CHACHAFORPOLYKEY2 (Bit 0)                             */
29299 #define CRYPTO_CHACHAFORPOLYKEY2_CHACHAFORPOLYKEY2_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY2 (Bitfield-Mask: 0xffffffff)       */
29300 /* ===================================================  CHACHAFORPOLYKEY3  =================================================== */
29301 #define CRYPTO_CHACHAFORPOLYKEY3_CHACHAFORPOLYKEY3_Pos (0UL)        /*!< CHACHAFORPOLYKEY3 (Bit 0)                             */
29302 #define CRYPTO_CHACHAFORPOLYKEY3_CHACHAFORPOLYKEY3_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY3 (Bitfield-Mask: 0xffffffff)       */
29303 /* ===================================================  CHACHAFORPOLYKEY4  =================================================== */
29304 #define CRYPTO_CHACHAFORPOLYKEY4_CHACHAFORPOLYKEY4_Pos (0UL)        /*!< CHACHAFORPOLYKEY4 (Bit 0)                             */
29305 #define CRYPTO_CHACHAFORPOLYKEY4_CHACHAFORPOLYKEY4_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY4 (Bitfield-Mask: 0xffffffff)       */
29306 /* ===================================================  CHACHAFORPOLYKEY5  =================================================== */
29307 #define CRYPTO_CHACHAFORPOLYKEY5_CHACHAFORPOLYKEY5_Pos (0UL)        /*!< CHACHAFORPOLYKEY5 (Bit 0)                             */
29308 #define CRYPTO_CHACHAFORPOLYKEY5_CHACHAFORPOLYKEY5_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY5 (Bitfield-Mask: 0xffffffff)       */
29309 /* ===================================================  CHACHAFORPOLYKEY6  =================================================== */
29310 #define CRYPTO_CHACHAFORPOLYKEY6_CHACHAFORPOLYKEY6_Pos (0UL)        /*!< CHACHAFORPOLYKEY6 (Bit 0)                             */
29311 #define CRYPTO_CHACHAFORPOLYKEY6_CHACHAFORPOLYKEY6_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY6 (Bitfield-Mask: 0xffffffff)       */
29312 /* ===================================================  CHACHAFORPOLYKEY7  =================================================== */
29313 #define CRYPTO_CHACHAFORPOLYKEY7_CHACHAFORPOLYKEY7_Pos (0UL)        /*!< CHACHAFORPOLYKEY7 (Bit 0)                             */
29314 #define CRYPTO_CHACHAFORPOLYKEY7_CHACHAFORPOLYKEY7_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY7 (Bitfield-Mask: 0xffffffff)       */
29315 /* ==============================================  CHACHABYTEWORDORDERCNTLREG  =============================================== */
29316 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Pos (4UL) /*!< CHACHADOUTBYTEORDER (Bit 4)                       */
29317 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Msk (0x10UL) /*!< CHACHADOUTBYTEORDER (Bitfield-Mask: 0x01)      */
29318 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Pos (3UL) /*!< CHACHADOUTWORDORDER (Bit 3)                       */
29319 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Msk (0x8UL) /*!< CHACHADOUTWORDORDER (Bitfield-Mask: 0x01)       */
29320 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Pos (2UL) /*!< CHACHACOREMATRIXLBEORDER (Bit 2)             */
29321 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Msk (0x4UL) /*!< CHACHACOREMATRIXLBEORDER (Bitfield-Mask: 0x01) */
29322 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Pos (1UL) /*!< CHACHADINBYTEORDER (Bit 1)                         */
29323 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Msk (0x2UL) /*!< CHACHADINBYTEORDER (Bitfield-Mask: 0x01)         */
29324 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Pos (0UL) /*!< CHACHADINWORDORDER (Bit 0)                         */
29325 #define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Msk (0x1UL) /*!< CHACHADINWORDORDER (Bitfield-Mask: 0x01)         */
29326 /* ====================================================  CHACHADEBUGREG  ===================================================== */
29327 #define CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Pos (0UL)         /*!< CHACHADEBUGFSMSTATE (Bit 0)                           */
29328 #define CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Msk (0x3UL)       /*!< CHACHADEBUGFSMSTATE (Bitfield-Mask: 0x03)             */
29329 /* =======================================================  AESKEY00  ======================================================== */
29330 #define CRYPTO_AESKEY00_AESKEY00_Pos      (0UL)                     /*!< AESKEY00 (Bit 0)                                      */
29331 #define CRYPTO_AESKEY00_AESKEY00_Msk      (0xffffffffUL)            /*!< AESKEY00 (Bitfield-Mask: 0xffffffff)                  */
29332 /* =======================================================  AESKEY01  ======================================================== */
29333 #define CRYPTO_AESKEY01_AESKEY01_Pos      (0UL)                     /*!< AESKEY01 (Bit 0)                                      */
29334 #define CRYPTO_AESKEY01_AESKEY01_Msk      (0xffffffffUL)            /*!< AESKEY01 (Bitfield-Mask: 0xffffffff)                  */
29335 /* =======================================================  AESKEY02  ======================================================== */
29336 #define CRYPTO_AESKEY02_AESKEY02_Pos      (0UL)                     /*!< AESKEY02 (Bit 0)                                      */
29337 #define CRYPTO_AESKEY02_AESKEY02_Msk      (0xffffffffUL)            /*!< AESKEY02 (Bitfield-Mask: 0xffffffff)                  */
29338 /* =======================================================  AESKEY03  ======================================================== */
29339 #define CRYPTO_AESKEY03_AESKEY03_Pos      (0UL)                     /*!< AESKEY03 (Bit 0)                                      */
29340 #define CRYPTO_AESKEY03_AESKEY03_Msk      (0xffffffffUL)            /*!< AESKEY03 (Bitfield-Mask: 0xffffffff)                  */
29341 /* =======================================================  AESKEY04  ======================================================== */
29342 #define CRYPTO_AESKEY04_AESKEY04_Pos      (0UL)                     /*!< AESKEY04 (Bit 0)                                      */
29343 #define CRYPTO_AESKEY04_AESKEY04_Msk      (0xffffffffUL)            /*!< AESKEY04 (Bitfield-Mask: 0xffffffff)                  */
29344 /* =======================================================  AESKEY05  ======================================================== */
29345 #define CRYPTO_AESKEY05_AESKEY05_Pos      (0UL)                     /*!< AESKEY05 (Bit 0)                                      */
29346 #define CRYPTO_AESKEY05_AESKEY05_Msk      (0xffffffffUL)            /*!< AESKEY05 (Bitfield-Mask: 0xffffffff)                  */
29347 /* =======================================================  AESKEY06  ======================================================== */
29348 #define CRYPTO_AESKEY06_AESKEY06_Pos      (0UL)                     /*!< AESKEY06 (Bit 0)                                      */
29349 #define CRYPTO_AESKEY06_AESKEY06_Msk      (0xffffffffUL)            /*!< AESKEY06 (Bitfield-Mask: 0xffffffff)                  */
29350 /* =======================================================  AESKEY07  ======================================================== */
29351 #define CRYPTO_AESKEY07_AESKEY07_Pos      (0UL)                     /*!< AESKEY07 (Bit 0)                                      */
29352 #define CRYPTO_AESKEY07_AESKEY07_Msk      (0xffffffffUL)            /*!< AESKEY07 (Bitfield-Mask: 0xffffffff)                  */
29353 /* =======================================================  AESKEY10  ======================================================== */
29354 #define CRYPTO_AESKEY10_AESKEY10_Pos      (0UL)                     /*!< AESKEY10 (Bit 0)                                      */
29355 #define CRYPTO_AESKEY10_AESKEY10_Msk      (0xffffffffUL)            /*!< AESKEY10 (Bitfield-Mask: 0xffffffff)                  */
29356 /* =======================================================  AESKEY11  ======================================================== */
29357 #define CRYPTO_AESKEY11_AESKEY11_Pos      (0UL)                     /*!< AESKEY11 (Bit 0)                                      */
29358 #define CRYPTO_AESKEY11_AESKEY11_Msk      (0xffffffffUL)            /*!< AESKEY11 (Bitfield-Mask: 0xffffffff)                  */
29359 /* =======================================================  AESKEY12  ======================================================== */
29360 #define CRYPTO_AESKEY12_AESKEY12_Pos      (0UL)                     /*!< AESKEY12 (Bit 0)                                      */
29361 #define CRYPTO_AESKEY12_AESKEY12_Msk      (0xffffffffUL)            /*!< AESKEY12 (Bitfield-Mask: 0xffffffff)                  */
29362 /* =======================================================  AESKEY13  ======================================================== */
29363 #define CRYPTO_AESKEY13_AESKEY13_Pos      (0UL)                     /*!< AESKEY13 (Bit 0)                                      */
29364 #define CRYPTO_AESKEY13_AESKEY13_Msk      (0xffffffffUL)            /*!< AESKEY13 (Bitfield-Mask: 0xffffffff)                  */
29365 /* =======================================================  AESKEY14  ======================================================== */
29366 #define CRYPTO_AESKEY14_AESKEY14_Pos      (0UL)                     /*!< AESKEY14 (Bit 0)                                      */
29367 #define CRYPTO_AESKEY14_AESKEY14_Msk      (0xffffffffUL)            /*!< AESKEY14 (Bitfield-Mask: 0xffffffff)                  */
29368 /* =======================================================  AESKEY15  ======================================================== */
29369 #define CRYPTO_AESKEY15_AESKEY15_Pos      (0UL)                     /*!< AESKEY15 (Bit 0)                                      */
29370 #define CRYPTO_AESKEY15_AESKEY15_Msk      (0xffffffffUL)            /*!< AESKEY15 (Bitfield-Mask: 0xffffffff)                  */
29371 /* =======================================================  AESKEY16  ======================================================== */
29372 #define CRYPTO_AESKEY16_AESKEY16_Pos      (0UL)                     /*!< AESKEY16 (Bit 0)                                      */
29373 #define CRYPTO_AESKEY16_AESKEY16_Msk      (0xffffffffUL)            /*!< AESKEY16 (Bitfield-Mask: 0xffffffff)                  */
29374 /* =======================================================  AESKEY17  ======================================================== */
29375 #define CRYPTO_AESKEY17_AESKEY17_Pos      (0UL)                     /*!< AESKEY17 (Bit 0)                                      */
29376 #define CRYPTO_AESKEY17_AESKEY17_Msk      (0xffffffffUL)            /*!< AESKEY17 (Bitfield-Mask: 0xffffffff)                  */
29377 /* ========================================================  AESIV00  ======================================================== */
29378 #define CRYPTO_AESIV00_AESIV00_Pos        (0UL)                     /*!< AESIV00 (Bit 0)                                       */
29379 #define CRYPTO_AESIV00_AESIV00_Msk        (0xffffffffUL)            /*!< AESIV00 (Bitfield-Mask: 0xffffffff)                   */
29380 /* ========================================================  AESIV01  ======================================================== */
29381 #define CRYPTO_AESIV01_AESIV01_Pos        (0UL)                     /*!< AESIV01 (Bit 0)                                       */
29382 #define CRYPTO_AESIV01_AESIV01_Msk        (0xffffffffUL)            /*!< AESIV01 (Bitfield-Mask: 0xffffffff)                   */
29383 /* ========================================================  AESIV02  ======================================================== */
29384 #define CRYPTO_AESIV02_AESIV02_Pos        (0UL)                     /*!< AESIV02 (Bit 0)                                       */
29385 #define CRYPTO_AESIV02_AESIV02_Msk        (0xffffffffUL)            /*!< AESIV02 (Bitfield-Mask: 0xffffffff)                   */
29386 /* ========================================================  AESIV03  ======================================================== */
29387 #define CRYPTO_AESIV03_AESIV03_Pos        (0UL)                     /*!< AESIV03 (Bit 0)                                       */
29388 #define CRYPTO_AESIV03_AESIV03_Msk        (0xffffffffUL)            /*!< AESIV03 (Bitfield-Mask: 0xffffffff)                   */
29389 /* ========================================================  AESIV10  ======================================================== */
29390 #define CRYPTO_AESIV10_AESIV10_Pos        (0UL)                     /*!< AESIV10 (Bit 0)                                       */
29391 #define CRYPTO_AESIV10_AESIV10_Msk        (0xffffffffUL)            /*!< AESIV10 (Bitfield-Mask: 0xffffffff)                   */
29392 /* ========================================================  AESIV11  ======================================================== */
29393 #define CRYPTO_AESIV11_AESIV11_Pos        (0UL)                     /*!< AESIV11 (Bit 0)                                       */
29394 #define CRYPTO_AESIV11_AESIV11_Msk        (0xffffffffUL)            /*!< AESIV11 (Bitfield-Mask: 0xffffffff)                   */
29395 /* ========================================================  AESIV12  ======================================================== */
29396 #define CRYPTO_AESIV12_AESIV12_Pos        (0UL)                     /*!< AESIV12 (Bit 0)                                       */
29397 #define CRYPTO_AESIV12_AESIV12_Msk        (0xffffffffUL)            /*!< AESIV12 (Bitfield-Mask: 0xffffffff)                   */
29398 /* ========================================================  AESIV13  ======================================================== */
29399 #define CRYPTO_AESIV13_AESIV13_Pos        (0UL)                     /*!< AESIV13 (Bit 0)                                       */
29400 #define CRYPTO_AESIV13_AESIV13_Msk        (0xffffffffUL)            /*!< AESIV13 (Bitfield-Mask: 0xffffffff)                   */
29401 /* =======================================================  AESCTR00  ======================================================== */
29402 #define CRYPTO_AESCTR00_AESCTR00_Pos      (0UL)                     /*!< AESCTR00 (Bit 0)                                      */
29403 #define CRYPTO_AESCTR00_AESCTR00_Msk      (0xffffffffUL)            /*!< AESCTR00 (Bitfield-Mask: 0xffffffff)                  */
29404 /* =======================================================  AESCTR01  ======================================================== */
29405 #define CRYPTO_AESCTR01_AESCTR01_Pos      (0UL)                     /*!< AESCTR01 (Bit 0)                                      */
29406 #define CRYPTO_AESCTR01_AESCTR01_Msk      (0xffffffffUL)            /*!< AESCTR01 (Bitfield-Mask: 0xffffffff)                  */
29407 /* =======================================================  AESCTR02  ======================================================== */
29408 #define CRYPTO_AESCTR02_AESCTR02_Pos      (0UL)                     /*!< AESCTR02 (Bit 0)                                      */
29409 #define CRYPTO_AESCTR02_AESCTR02_Msk      (0xffffffffUL)            /*!< AESCTR02 (Bitfield-Mask: 0xffffffff)                  */
29410 /* =======================================================  AESCTR03  ======================================================== */
29411 #define CRYPTO_AESCTR03_AESCTR03_Pos      (0UL)                     /*!< AESCTR03 (Bit 0)                                      */
29412 #define CRYPTO_AESCTR03_AESCTR03_Msk      (0xffffffffUL)            /*!< AESCTR03 (Bitfield-Mask: 0xffffffff)                  */
29413 /* ========================================================  AESBUSY  ======================================================== */
29414 #define CRYPTO_AESBUSY_AESBUSY_Pos        (0UL)                     /*!< AESBUSY (Bit 0)                                       */
29415 #define CRYPTO_AESBUSY_AESBUSY_Msk        (0x1UL)                   /*!< AESBUSY (Bitfield-Mask: 0x01)                         */
29416 /* =========================================================  AESSK  ========================================================= */
29417 #define CRYPTO_AESSK_AESSK_Pos            (0UL)                     /*!< AESSK (Bit 0)                                         */
29418 #define CRYPTO_AESSK_AESSK_Msk            (0x1UL)                   /*!< AESSK (Bitfield-Mask: 0x01)                           */
29419 /* ======================================================  AESCMACINIT  ====================================================== */
29420 #define CRYPTO_AESCMACINIT_AESCMACINIT_Pos (0UL)                    /*!< AESCMACINIT (Bit 0)                                   */
29421 #define CRYPTO_AESCMACINIT_AESCMACINIT_Msk (0x1UL)                  /*!< AESCMACINIT (Bitfield-Mask: 0x01)                     */
29422 /* ========================================================  AESSK1  ========================================================= */
29423 #define CRYPTO_AESSK1_AESSK1_Pos          (0UL)                     /*!< AESSK1 (Bit 0)                                        */
29424 #define CRYPTO_AESSK1_AESSK1_Msk          (0x1UL)                   /*!< AESSK1 (Bitfield-Mask: 0x01)                          */
29425 /* ===================================================  AESREMAININGBYTES  =================================================== */
29426 #define CRYPTO_AESREMAININGBYTES_AESREMAININGBYTES_Pos (0UL)        /*!< AESREMAININGBYTES (Bit 0)                             */
29427 #define CRYPTO_AESREMAININGBYTES_AESREMAININGBYTES_Msk (0xffffffffUL) /*!< AESREMAININGBYTES (Bitfield-Mask: 0xffffffff)       */
29428 /* ======================================================  AESCONTROL  ======================================================= */
29429 #define CRYPTO_AESCONTROL_DIRECTACCESS_Pos (31UL)                   /*!< DIRECTACCESS (Bit 31)                                 */
29430 #define CRYPTO_AESCONTROL_DIRECTACCESS_Msk (0x80000000UL)           /*!< DIRECTACCESS (Bitfield-Mask: 0x01)                    */
29431 #define CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Pos (29UL)                /*!< AESXORCRYPTOKEY (Bit 29)                              */
29432 #define CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Msk (0x20000000UL)        /*!< AESXORCRYPTOKEY (Bitfield-Mask: 0x01)                 */
29433 #define CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Pos (28UL)             /*!< AESOUTMIDTUNTOHASH (Bit 28)                           */
29434 #define CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Msk (0x10000000UL)     /*!< AESOUTMIDTUNTOHASH (Bitfield-Mask: 0x01)              */
29435 #define CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Pos (26UL)               /*!< AESTUNNELB1PADEN (Bit 26)                             */
29436 #define CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Msk (0x4000000UL)        /*!< AESTUNNELB1PADEN (Bitfield-Mask: 0x01)                */
29437 #define CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Pos (25UL)         /*!< AESOUTPUTMIDTUNNELDATA (Bit 25)                       */
29438 #define CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Msk (0x2000000UL)  /*!< AESOUTPUTMIDTUNNELDATA (Bitfield-Mask: 0x01)          */
29439 #define CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Pos (24UL)              /*!< AESTUNNEL0ENCRYPT (Bit 24)                            */
29440 #define CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Msk (0x1000000UL)       /*!< AESTUNNEL0ENCRYPT (Bitfield-Mask: 0x01)               */
29441 #define CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Pos (23UL)       /*!< AESTUNB1USESPADDEDDATAIN (Bit 23)                     */
29442 #define CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Msk (0x800000UL) /*!< AESTUNB1USESPADDEDDATAIN (Bitfield-Mask: 0x01)        */
29443 #define CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Pos (22UL)              /*!< AESTUNNEL1DECRYPT (Bit 22)                            */
29444 #define CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Msk (0x400000UL)        /*!< AESTUNNEL1DECRYPT (Bitfield-Mask: 0x01)               */
29445 #define CRYPTO_AESCONTROL_NKKEY1_Pos      (14UL)                    /*!< NKKEY1 (Bit 14)                                       */
29446 #define CRYPTO_AESCONTROL_NKKEY1_Msk      (0xc000UL)                /*!< NKKEY1 (Bitfield-Mask: 0x03)                          */
29447 #define CRYPTO_AESCONTROL_NKKEY0_Pos      (12UL)                    /*!< NKKEY0 (Bit 12)                                       */
29448 #define CRYPTO_AESCONTROL_NKKEY0_Msk      (0x3000UL)                /*!< NKKEY0 (Bitfield-Mask: 0x03)                          */
29449 #define CRYPTO_AESCONTROL_CBCISBITLOCKER_Pos (11UL)                 /*!< CBCISBITLOCKER (Bit 11)                               */
29450 #define CRYPTO_AESCONTROL_CBCISBITLOCKER_Msk (0x800UL)              /*!< CBCISBITLOCKER (Bitfield-Mask: 0x01)                  */
29451 #define CRYPTO_AESCONTROL_AESTUNNELISON_Pos (10UL)                  /*!< AESTUNNELISON (Bit 10)                                */
29452 #define CRYPTO_AESCONTROL_AESTUNNELISON_Msk (0x400UL)               /*!< AESTUNNELISON (Bitfield-Mask: 0x01)                   */
29453 #define CRYPTO_AESCONTROL_CBCISESSIV_Pos  (8UL)                     /*!< CBCISESSIV (Bit 8)                                    */
29454 #define CRYPTO_AESCONTROL_CBCISESSIV_Msk  (0x100UL)                 /*!< CBCISESSIV (Bitfield-Mask: 0x01)                      */
29455 #define CRYPTO_AESCONTROL_MODEKEY1_Pos    (5UL)                     /*!< MODEKEY1 (Bit 5)                                      */
29456 #define CRYPTO_AESCONTROL_MODEKEY1_Msk    (0xe0UL)                  /*!< MODEKEY1 (Bitfield-Mask: 0x07)                        */
29457 #define CRYPTO_AESCONTROL_MODEKEY0_Pos    (2UL)                     /*!< MODEKEY0 (Bit 2)                                      */
29458 #define CRYPTO_AESCONTROL_MODEKEY0_Msk    (0x1cUL)                  /*!< MODEKEY0 (Bitfield-Mask: 0x07)                        */
29459 #define CRYPTO_AESCONTROL_MODE0ISCBCCTS_Pos (1UL)                   /*!< MODE0ISCBCCTS (Bit 1)                                 */
29460 #define CRYPTO_AESCONTROL_MODE0ISCBCCTS_Msk (0x2UL)                 /*!< MODE0ISCBCCTS (Bitfield-Mask: 0x01)                   */
29461 #define CRYPTO_AESCONTROL_DECKEY0_Pos     (0UL)                     /*!< DECKEY0 (Bit 0)                                       */
29462 #define CRYPTO_AESCONTROL_DECKEY0_Msk     (0x1UL)                   /*!< DECKEY0 (Bitfield-Mask: 0x01)                         */
29463 /* ======================================================  AESHWFLAGS  ======================================================= */
29464 #define CRYPTO_AESHWFLAGS_DFACNTRMSREXIST_Pos (12UL)                /*!< DFACNTRMSREXIST (Bit 12)                              */
29465 #define CRYPTO_AESHWFLAGS_DFACNTRMSREXIST_Msk (0x1000UL)            /*!< DFACNTRMSREXIST (Bitfield-Mask: 0x01)                 */
29466 #define CRYPTO_AESHWFLAGS_SECONDREGSSETEXIST_Pos (11UL)             /*!< SECONDREGSSETEXIST (Bit 11)                           */
29467 #define CRYPTO_AESHWFLAGS_SECONDREGSSETEXIST_Msk (0x800UL)          /*!< SECONDREGSSETEXIST (Bitfield-Mask: 0x01)              */
29468 #define CRYPTO_AESHWFLAGS_aestunnelexists_Pos (10UL)                /*!< aestunnelexists (Bit 10)                              */
29469 #define CRYPTO_AESHWFLAGS_aestunnelexists_Msk (0x400UL)             /*!< aestunnelexists (Bitfield-Mask: 0x01)                 */
29470 #define CRYPTO_AESHWFLAGS_AESSUPPORTPREVIV_Pos (9UL)                /*!< AESSUPPORTPREVIV (Bit 9)                              */
29471 #define CRYPTO_AESHWFLAGS_AESSUPPORTPREVIV_Msk (0x200UL)            /*!< AESSUPPORTPREVIV (Bitfield-Mask: 0x01)                */
29472 #define CRYPTO_AESHWFLAGS_USE5SBOXES_Pos  (8UL)                     /*!< USE5SBOXES (Bit 8)                                    */
29473 #define CRYPTO_AESHWFLAGS_USE5SBOXES_Msk  (0x100UL)                 /*!< USE5SBOXES (Bitfield-Mask: 0x01)                      */
29474 #define CRYPTO_AESHWFLAGS_USESBOXTABLE_Pos (5UL)                    /*!< USESBOXTABLE (Bit 5)                                  */
29475 #define CRYPTO_AESHWFLAGS_USESBOXTABLE_Msk (0x20UL)                 /*!< USESBOXTABLE (Bitfield-Mask: 0x01)                    */
29476 #define CRYPTO_AESHWFLAGS_ONLYENCRYPT_Pos (4UL)                     /*!< ONLYENCRYPT (Bit 4)                                   */
29477 #define CRYPTO_AESHWFLAGS_ONLYENCRYPT_Msk (0x10UL)                  /*!< ONLYENCRYPT (Bitfield-Mask: 0x01)                     */
29478 #define CRYPTO_AESHWFLAGS_CTREXIST_Pos    (3UL)                     /*!< CTREXIST (Bit 3)                                      */
29479 #define CRYPTO_AESHWFLAGS_CTREXIST_Msk    (0x8UL)                   /*!< CTREXIST (Bitfield-Mask: 0x01)                        */
29480 #define CRYPTO_AESHWFLAGS_DPACNTRMSREXIST_Pos (2UL)                 /*!< DPACNTRMSREXIST (Bit 2)                               */
29481 #define CRYPTO_AESHWFLAGS_DPACNTRMSREXIST_Msk (0x4UL)               /*!< DPACNTRMSREXIST (Bitfield-Mask: 0x01)                 */
29482 #define CRYPTO_AESHWFLAGS_AESLARGERKEK_Pos (1UL)                    /*!< AESLARGERKEK (Bit 1)                                  */
29483 #define CRYPTO_AESHWFLAGS_AESLARGERKEK_Msk (0x2UL)                  /*!< AESLARGERKEK (Bitfield-Mask: 0x01)                    */
29484 #define CRYPTO_AESHWFLAGS_SUPPORT256192KEY_Pos (0UL)                /*!< SUPPORT256192KEY (Bit 0)                              */
29485 #define CRYPTO_AESHWFLAGS_SUPPORT256192KEY_Msk (0x1UL)              /*!< SUPPORT256192KEY (Bitfield-Mask: 0x01)                */
29486 /* ===================================================  AESCTRNOINCREMENT  =================================================== */
29487 #define CRYPTO_AESCTRNOINCREMENT_AESCTRNOINCREMENT_Pos (0UL)        /*!< AESCTRNOINCREMENT (Bit 0)                             */
29488 #define CRYPTO_AESCTRNOINCREMENT_AESCTRNOINCREMENT_Msk (0x1UL)      /*!< AESCTRNOINCREMENT (Bitfield-Mask: 0x01)               */
29489 /* ======================================================  AESDFAISON  ======================================================= */
29490 #define CRYPTO_AESDFAISON_AESDFAISON_Pos  (0UL)                     /*!< AESDFAISON (Bit 0)                                    */
29491 #define CRYPTO_AESDFAISON_AESDFAISON_Msk  (0x1UL)                   /*!< AESDFAISON (Bitfield-Mask: 0x01)                      */
29492 /* ====================================================  AESDFAERRSTATUS  ==================================================== */
29493 #define CRYPTO_AESDFAERRSTATUS_AESDFAERRSTATUS_Pos (0UL)            /*!< AESDFAERRSTATUS (Bit 0)                               */
29494 #define CRYPTO_AESDFAERRSTATUS_AESDFAERRSTATUS_Msk (0x1UL)          /*!< AESDFAERRSTATUS (Bitfield-Mask: 0x01)                 */
29495 /* ===================================================  AESCMACSIZE0KICK  ==================================================== */
29496 #define CRYPTO_AESCMACSIZE0KICK_AESCMACSIZE0KICK_Pos (0UL)          /*!< AESCMACSIZE0KICK (Bit 0)                              */
29497 #define CRYPTO_AESCMACSIZE0KICK_AESCMACSIZE0KICK_Msk (0x1UL)        /*!< AESCMACSIZE0KICK (Bitfield-Mask: 0x01)                */
29498 /* ========================================================  HASHH0  ========================================================= */
29499 #define CRYPTO_HASHH0_HASHH0_Pos          (0UL)                     /*!< HASHH0 (Bit 0)                                        */
29500 #define CRYPTO_HASHH0_HASHH0_Msk          (0xffffffffUL)            /*!< HASHH0 (Bitfield-Mask: 0xffffffff)                    */
29501 /* ========================================================  HASHH1  ========================================================= */
29502 #define CRYPTO_HASHH1_HASHH1_Pos          (0UL)                     /*!< HASHH1 (Bit 0)                                        */
29503 #define CRYPTO_HASHH1_HASHH1_Msk          (0xffffffffUL)            /*!< HASHH1 (Bitfield-Mask: 0xffffffff)                    */
29504 /* ========================================================  HASHH2  ========================================================= */
29505 #define CRYPTO_HASHH2_HASHH2_Pos          (0UL)                     /*!< HASHH2 (Bit 0)                                        */
29506 #define CRYPTO_HASHH2_HASHH2_Msk          (0xffffffffUL)            /*!< HASHH2 (Bitfield-Mask: 0xffffffff)                    */
29507 /* ========================================================  HASHH3  ========================================================= */
29508 #define CRYPTO_HASHH3_HASHH3_Pos          (0UL)                     /*!< HASHH3 (Bit 0)                                        */
29509 #define CRYPTO_HASHH3_HASHH3_Msk          (0xffffffffUL)            /*!< HASHH3 (Bitfield-Mask: 0xffffffff)                    */
29510 /* ========================================================  HASHH4  ========================================================= */
29511 #define CRYPTO_HASHH4_HASHH4_Pos          (0UL)                     /*!< HASHH4 (Bit 0)                                        */
29512 #define CRYPTO_HASHH4_HASHH4_Msk          (0xffffffffUL)            /*!< HASHH4 (Bitfield-Mask: 0xffffffff)                    */
29513 /* ========================================================  HASHH5  ========================================================= */
29514 #define CRYPTO_HASHH5_HASHH5_Pos          (0UL)                     /*!< HASHH5 (Bit 0)                                        */
29515 #define CRYPTO_HASHH5_HASHH5_Msk          (0xffffffffUL)            /*!< HASHH5 (Bitfield-Mask: 0xffffffff)                    */
29516 /* ========================================================  HASHH6  ========================================================= */
29517 #define CRYPTO_HASHH6_HASHH6_Pos          (0UL)                     /*!< HASHH6 (Bit 0)                                        */
29518 #define CRYPTO_HASHH6_HASHH6_Msk          (0xffffffffUL)            /*!< HASHH6 (Bitfield-Mask: 0xffffffff)                    */
29519 /* ========================================================  HASHH7  ========================================================= */
29520 #define CRYPTO_HASHH7_HASHH7_Pos          (0UL)                     /*!< HASHH7 (Bit 0)                                        */
29521 #define CRYPTO_HASHH7_HASHH7_Msk          (0xffffffffUL)            /*!< HASHH7 (Bitfield-Mask: 0xffffffff)                    */
29522 /* ========================================================  HASHH8  ========================================================= */
29523 #define CRYPTO_HASHH8_HASHH8_Pos          (0UL)                     /*!< HASHH8 (Bit 0)                                        */
29524 #define CRYPTO_HASHH8_HASHH8_Msk          (0xffffffffUL)            /*!< HASHH8 (Bitfield-Mask: 0xffffffff)                    */
29525 /* =====================================================  AUTOHWPADDING  ===================================================== */
29526 #define CRYPTO_AUTOHWPADDING_EN_Pos       (0UL)                     /*!< EN (Bit 0)                                            */
29527 #define CRYPTO_AUTOHWPADDING_EN_Msk       (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29528 /* ======================================================  HASHXORDIN  ======================================================= */
29529 #define CRYPTO_HASHXORDIN_HASHXORDATA_Pos (0UL)                     /*!< HASHXORDATA (Bit 0)                                   */
29530 #define CRYPTO_HASHXORDIN_HASHXORDATA_Msk (0xffffffffUL)            /*!< HASHXORDATA (Bitfield-Mask: 0xffffffff)               */
29531 /* =====================================================  LOADINITSTATE  ===================================================== */
29532 #define CRYPTO_LOADINITSTATE_LOAD_Pos     (0UL)                     /*!< LOAD (Bit 0)                                          */
29533 #define CRYPTO_LOADINITSTATE_LOAD_Msk     (0x1UL)                   /*!< LOAD (Bitfield-Mask: 0x01)                            */
29534 /* =====================================================  HASHSELAESMAC  ===================================================== */
29535 #define CRYPTO_HASHSELAESMAC_GHASHSEL_Pos (1UL)                     /*!< GHASHSEL (Bit 1)                                      */
29536 #define CRYPTO_HASHSELAESMAC_GHASHSEL_Msk (0x2UL)                   /*!< GHASHSEL (Bitfield-Mask: 0x01)                        */
29537 #define CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Pos (0UL)                /*!< HASHSELAESMAC (Bit 0)                                 */
29538 #define CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Msk (0x1UL)              /*!< HASHSELAESMAC (Bitfield-Mask: 0x01)                   */
29539 /* ======================================================  HASHVERSION  ====================================================== */
29540 #define CRYPTO_HASHVERSION_MAJORVERSIONNUMBER_Pos (12UL)            /*!< MAJORVERSIONNUMBER (Bit 12)                           */
29541 #define CRYPTO_HASHVERSION_MAJORVERSIONNUMBER_Msk (0xf000UL)        /*!< MAJORVERSIONNUMBER (Bitfield-Mask: 0x0f)              */
29542 #define CRYPTO_HASHVERSION_MINORVERSIONNUMBER_Pos (8UL)             /*!< MINORVERSIONNUMBER (Bit 8)                            */
29543 #define CRYPTO_HASHVERSION_MINORVERSIONNUMBER_Msk (0xf00UL)         /*!< MINORVERSIONNUMBER (Bitfield-Mask: 0x0f)              */
29544 #define CRYPTO_HASHVERSION_FIXES_Pos      (0UL)                     /*!< FIXES (Bit 0)                                         */
29545 #define CRYPTO_HASHVERSION_FIXES_Msk      (0xffUL)                  /*!< FIXES (Bitfield-Mask: 0xff)                           */
29546 /* ======================================================  HASHCONTROL  ====================================================== */
29547 #define CRYPTO_HASHCONTROL_MODE3_Pos      (3UL)                     /*!< MODE3 (Bit 3)                                         */
29548 #define CRYPTO_HASHCONTROL_MODE3_Msk      (0x8UL)                   /*!< MODE3 (Bitfield-Mask: 0x01)                           */
29549 #define CRYPTO_HASHCONTROL_MODE01_Pos     (0UL)                     /*!< MODE01 (Bit 0)                                        */
29550 #define CRYPTO_HASHCONTROL_MODE01_Msk     (0x3UL)                   /*!< MODE01 (Bitfield-Mask: 0x03)                          */
29551 /* =======================================================  HASHPADEN  ======================================================= */
29552 #define CRYPTO_HASHPADEN_EN_Pos           (0UL)                     /*!< EN (Bit 0)                                            */
29553 #define CRYPTO_HASHPADEN_EN_Msk           (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29554 /* ======================================================  HASHPADCFG  ======================================================= */
29555 #define CRYPTO_HASHPADCFG_DOPAD_Pos       (2UL)                     /*!< DOPAD (Bit 2)                                         */
29556 #define CRYPTO_HASHPADCFG_DOPAD_Msk       (0x4UL)                   /*!< DOPAD (Bitfield-Mask: 0x01)                           */
29557 /* ======================================================  HASHCURLEN0  ====================================================== */
29558 #define CRYPTO_HASHCURLEN0_Length_Pos     (0UL)                     /*!< Length (Bit 0)                                        */
29559 #define CRYPTO_HASHCURLEN0_Length_Msk     (0xffffffffUL)            /*!< Length (Bitfield-Mask: 0xffffffff)                    */
29560 /* ======================================================  HASHCURLEN1  ====================================================== */
29561 #define CRYPTO_HASHCURLEN1_Length_Pos     (0UL)                     /*!< Length (Bit 0)                                        */
29562 #define CRYPTO_HASHCURLEN1_Length_Msk     (0xffffffffUL)            /*!< Length (Bitfield-Mask: 0xffffffff)                    */
29563 /* =======================================================  HASHPARAM  ======================================================= */
29564 #define CRYPTO_HASHPARAM_DUMPHASHTODOUTEXISTS_Pos (18UL)            /*!< DUMPHASHTODOUTEXISTS (Bit 18)                         */
29565 #define CRYPTO_HASHPARAM_DUMPHASHTODOUTEXISTS_Msk (0x40000UL)       /*!< DUMPHASHTODOUTEXISTS (Bitfield-Mask: 0x01)            */
29566 #define CRYPTO_HASHPARAM_HASHCOMPAREEXISTS_Pos (17UL)               /*!< HASHCOMPAREEXISTS (Bit 17)                            */
29567 #define CRYPTO_HASHPARAM_HASHCOMPAREEXISTS_Msk (0x20000UL)          /*!< HASHCOMPAREEXISTS (Bitfield-Mask: 0x01)               */
29568 #define CRYPTO_HASHPARAM_SHA256EXISTS_Pos (16UL)                    /*!< SHA256EXISTS (Bit 16)                                 */
29569 #define CRYPTO_HASHPARAM_SHA256EXISTS_Msk (0x10000UL)               /*!< SHA256EXISTS (Bitfield-Mask: 0x01)                    */
29570 #define CRYPTO_HASHPARAM_HMACEXISTS_Pos   (15UL)                    /*!< HMACEXISTS (Bit 15)                                   */
29571 #define CRYPTO_HASHPARAM_HMACEXISTS_Msk   (0x8000UL)                /*!< HMACEXISTS (Bitfield-Mask: 0x01)                      */
29572 #define CRYPTO_HASHPARAM_MD5EXISTS_Pos    (14UL)                    /*!< MD5EXISTS (Bit 14)                                    */
29573 #define CRYPTO_HASHPARAM_MD5EXISTS_Msk    (0x4000UL)                /*!< MD5EXISTS (Bitfield-Mask: 0x01)                       */
29574 #define CRYPTO_HASHPARAM_PADEXISTS_Pos    (13UL)                    /*!< PADEXISTS (Bit 13)                                    */
29575 #define CRYPTO_HASHPARAM_PADEXISTS_Msk    (0x2000UL)                /*!< PADEXISTS (Bitfield-Mask: 0x01)                       */
29576 #define CRYPTO_HASHPARAM_SHA512EXISTS_Pos (12UL)                    /*!< SHA512EXISTS (Bit 12)                                 */
29577 #define CRYPTO_HASHPARAM_SHA512EXISTS_Msk (0x1000UL)                /*!< SHA512EXISTS (Bitfield-Mask: 0x01)                    */
29578 #define CRYPTO_HASHPARAM_DW_Pos           (8UL)                     /*!< DW (Bit 8)                                            */
29579 #define CRYPTO_HASHPARAM_DW_Msk           (0xf00UL)                 /*!< DW (Bitfield-Mask: 0x0f)                              */
29580 #define CRYPTO_HASHPARAM_CH_Pos           (4UL)                     /*!< CH (Bit 4)                                            */
29581 #define CRYPTO_HASHPARAM_CH_Msk           (0xf0UL)                  /*!< CH (Bitfield-Mask: 0x0f)                              */
29582 #define CRYPTO_HASHPARAM_CW_Pos           (0UL)                     /*!< CW (Bit 0)                                            */
29583 #define CRYPTO_HASHPARAM_CW_Msk           (0xfUL)                   /*!< CW (Bitfield-Mask: 0x0f)                              */
29584 /* ====================================================  HASHAESSWRESET  ===================================================== */
29585 #define CRYPTO_HASHAESSWRESET_HASHAESSWRESET_Pos (0UL)              /*!< HASHAESSWRESET (Bit 0)                                */
29586 #define CRYPTO_HASHAESSWRESET_HASHAESSWRESET_Msk (0x1UL)            /*!< HASHAESSWRESET (Bitfield-Mask: 0x01)                  */
29587 /* =====================================================  HASHENDIANESS  ===================================================== */
29588 #define CRYPTO_HASHENDIANESS_ENDIAN_Pos   (0UL)                     /*!< ENDIAN (Bit 0)                                        */
29589 #define CRYPTO_HASHENDIANESS_ENDIAN_Msk   (0x1UL)                   /*!< ENDIAN (Bitfield-Mask: 0x01)                          */
29590 /* =====================================================  AESCLKENABLE  ====================================================== */
29591 #define CRYPTO_AESCLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
29592 #define CRYPTO_AESCLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29593 /* =====================================================  HASHCLKENABLE  ===================================================== */
29594 #define CRYPTO_HASHCLKENABLE_EN_Pos       (0UL)                     /*!< EN (Bit 0)                                            */
29595 #define CRYPTO_HASHCLKENABLE_EN_Msk       (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29596 /* =====================================================  PKACLKENABLE  ====================================================== */
29597 #define CRYPTO_PKACLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
29598 #define CRYPTO_PKACLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29599 /* =====================================================  DMACLKENABLE  ====================================================== */
29600 #define CRYPTO_DMACLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
29601 #define CRYPTO_DMACLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29602 /* =======================================================  CLKSTATUS  ======================================================= */
29603 #define CRYPTO_CLKSTATUS_DMACLKSTATUS_Pos (8UL)                     /*!< DMACLKSTATUS (Bit 8)                                  */
29604 #define CRYPTO_CLKSTATUS_DMACLKSTATUS_Msk (0x100UL)                 /*!< DMACLKSTATUS (Bitfield-Mask: 0x01)                    */
29605 #define CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Pos (7UL)                  /*!< CHACHACLKSTATUS (Bit 7)                               */
29606 #define CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Msk (0x80UL)               /*!< CHACHACLKSTATUS (Bitfield-Mask: 0x01)                 */
29607 #define CRYPTO_CLKSTATUS_PKACLKSTATUS_Pos (3UL)                     /*!< PKACLKSTATUS (Bit 3)                                  */
29608 #define CRYPTO_CLKSTATUS_PKACLKSTATUS_Msk (0x8UL)                   /*!< PKACLKSTATUS (Bitfield-Mask: 0x01)                    */
29609 #define CRYPTO_CLKSTATUS_HASHCLKSTATUS_Pos (2UL)                    /*!< HASHCLKSTATUS (Bit 2)                                 */
29610 #define CRYPTO_CLKSTATUS_HASHCLKSTATUS_Msk (0x4UL)                  /*!< HASHCLKSTATUS (Bitfield-Mask: 0x01)                   */
29611 #define CRYPTO_CLKSTATUS_AESCLKSTATUS_Pos (0UL)                     /*!< AESCLKSTATUS (Bit 0)                                  */
29612 #define CRYPTO_CLKSTATUS_AESCLKSTATUS_Msk (0x1UL)                   /*!< AESCLKSTATUS (Bitfield-Mask: 0x01)                    */
29613 /* ====================================================  CHACHACLKENABLE  ==================================================== */
29614 #define CRYPTO_CHACHACLKENABLE_EN_Pos     (0UL)                     /*!< EN (Bit 0)                                            */
29615 #define CRYPTO_CHACHACLKENABLE_EN_Msk     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
29616 /* =======================================================  CRYPTOCTL  ======================================================= */
29617 #define CRYPTO_CRYPTOCTL_MODE_Pos         (0UL)                     /*!< MODE (Bit 0)                                          */
29618 #define CRYPTO_CRYPTOCTL_MODE_Msk         (0x1fUL)                  /*!< MODE (Bitfield-Mask: 0x1f)                            */
29619 /* ======================================================  CRYPTOBUSY  ======================================================= */
29620 #define CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Pos  (0UL)                     /*!< CRYPTOBUSY (Bit 0)                                    */
29621 #define CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Msk  (0x1UL)                   /*!< CRYPTOBUSY (Bitfield-Mask: 0x01)                      */
29622 /* =======================================================  HASHBUSY  ======================================================== */
29623 #define CRYPTO_HASHBUSY_HASHBUSY_Pos      (0UL)                     /*!< HASHBUSY (Bit 0)                                      */
29624 #define CRYPTO_HASHBUSY_HASHBUSY_Msk      (0x1UL)                   /*!< HASHBUSY (Bitfield-Mask: 0x01)                        */
29625 /* =======================================================  CONTEXTID  ======================================================= */
29626 #define CRYPTO_CONTEXTID_CONTEXTID_Pos    (0UL)                     /*!< CONTEXTID (Bit 0)                                     */
29627 #define CRYPTO_CONTEXTID_CONTEXTID_Msk    (0xffUL)                  /*!< CONTEXTID (Bitfield-Mask: 0xff)                       */
29628 /* =====================================================  GHASHSUBKEY00  ===================================================== */
29629 #define CRYPTO_GHASHSUBKEY00_GHASHSUBKEY00_Pos (0UL)                /*!< GHASHSUBKEY00 (Bit 0)                                 */
29630 #define CRYPTO_GHASHSUBKEY00_GHASHSUBKEY00_Msk (0xffffffffUL)       /*!< GHASHSUBKEY00 (Bitfield-Mask: 0xffffffff)             */
29631 /* =====================================================  GHASHSUBKEY01  ===================================================== */
29632 #define CRYPTO_GHASHSUBKEY01_GHASHSUBKEY01_Pos (0UL)                /*!< GHASHSUBKEY01 (Bit 0)                                 */
29633 #define CRYPTO_GHASHSUBKEY01_GHASHSUBKEY01_Msk (0xffffffffUL)       /*!< GHASHSUBKEY01 (Bitfield-Mask: 0xffffffff)             */
29634 /* =====================================================  GHASHSUBKEY02  ===================================================== */
29635 #define CRYPTO_GHASHSUBKEY02_GHASHSUBKEY02_Pos (0UL)                /*!< GHASHSUBKEY02 (Bit 0)                                 */
29636 #define CRYPTO_GHASHSUBKEY02_GHASHSUBKEY02_Msk (0xffffffffUL)       /*!< GHASHSUBKEY02 (Bitfield-Mask: 0xffffffff)             */
29637 /* =====================================================  GHASHSUBKEY03  ===================================================== */
29638 #define CRYPTO_GHASHSUBKEY03_GHASHSUBKEY03_Pos (0UL)                /*!< GHASHSUBKEY03 (Bit 0)                                 */
29639 #define CRYPTO_GHASHSUBKEY03_GHASHSUBKEY03_Msk (0xffffffffUL)       /*!< GHASHSUBKEY03 (Bitfield-Mask: 0xffffffff)             */
29640 /* =======================================================  GHASHIV00  ======================================================= */
29641 #define CRYPTO_GHASHIV00_GHASHIV00_Pos    (0UL)                     /*!< GHASHIV00 (Bit 0)                                     */
29642 #define CRYPTO_GHASHIV00_GHASHIV00_Msk    (0xffffffffUL)            /*!< GHASHIV00 (Bitfield-Mask: 0xffffffff)                 */
29643 /* =======================================================  GHASHIV01  ======================================================= */
29644 #define CRYPTO_GHASHIV01_GHASHIV01_Pos    (0UL)                     /*!< GHASHIV01 (Bit 0)                                     */
29645 #define CRYPTO_GHASHIV01_GHASHIV01_Msk    (0xffffffffUL)            /*!< GHASHIV01 (Bitfield-Mask: 0xffffffff)                 */
29646 /* =======================================================  GHASHIV02  ======================================================= */
29647 #define CRYPTO_GHASHIV02_GHASHIV02_Pos    (0UL)                     /*!< GHASHIV02 (Bit 0)                                     */
29648 #define CRYPTO_GHASHIV02_GHASHIV02_Msk    (0xffffffffUL)            /*!< GHASHIV02 (Bitfield-Mask: 0xffffffff)                 */
29649 /* =======================================================  GHASHIV03  ======================================================= */
29650 #define CRYPTO_GHASHIV03_GHASHIV03_Pos    (0UL)                     /*!< GHASHIV03 (Bit 0)                                     */
29651 #define CRYPTO_GHASHIV03_GHASHIV03_Msk    (0xffffffffUL)            /*!< GHASHIV03 (Bitfield-Mask: 0xffffffff)                 */
29652 /* =======================================================  GHASHBUSY  ======================================================= */
29653 #define CRYPTO_GHASHBUSY_GHASHBUSY_Pos    (0UL)                     /*!< GHASHBUSY (Bit 0)                                     */
29654 #define CRYPTO_GHASHBUSY_GHASHBUSY_Msk    (0x1UL)                   /*!< GHASHBUSY (Bitfield-Mask: 0x01)                       */
29655 /* =======================================================  GHASHINIT  ======================================================= */
29656 #define CRYPTO_GHASHINIT_GHASHINIT_Pos    (0UL)                     /*!< GHASHINIT (Bit 0)                                     */
29657 #define CRYPTO_GHASHINIT_GHASHINIT_Msk    (0x1UL)                   /*!< GHASHINIT (Bitfield-Mask: 0x01)                       */
29658 /* ======================================================  HOSTRGFIRR  ======================================================= */
29659 #define CRYPTO_HOSTRGFIRR_SYMDMACOMPLETED_Pos (11UL)                /*!< SYMDMACOMPLETED (Bit 11)                              */
29660 #define CRYPTO_HOSTRGFIRR_SYMDMACOMPLETED_Msk (0x800UL)             /*!< SYMDMACOMPLETED (Bitfield-Mask: 0x01)                 */
29661 #define CRYPTO_HOSTRGFIRR_RNGINT_Pos      (10UL)                    /*!< RNGINT (Bit 10)                                       */
29662 #define CRYPTO_HOSTRGFIRR_RNGINT_Msk      (0x400UL)                 /*!< RNGINT (Bitfield-Mask: 0x01)                          */
29663 #define CRYPTO_HOSTRGFIRR_PKAEXPINT_Pos   (9UL)                     /*!< PKAEXPINT (Bit 9)                                     */
29664 #define CRYPTO_HOSTRGFIRR_PKAEXPINT_Msk   (0x200UL)                 /*!< PKAEXPINT (Bitfield-Mask: 0x01)                       */
29665 #define CRYPTO_HOSTRGFIRR_AHBERRINT_Pos   (8UL)                     /*!< AHBERRINT (Bit 8)                                     */
29666 #define CRYPTO_HOSTRGFIRR_AHBERRINT_Msk   (0x100UL)                 /*!< AHBERRINT (Bitfield-Mask: 0x01)                       */
29667 #define CRYPTO_HOSTRGFIRR_DOUTTOMEMINT_Pos (7UL)                    /*!< DOUTTOMEMINT (Bit 7)                                  */
29668 #define CRYPTO_HOSTRGFIRR_DOUTTOMEMINT_Msk (0x80UL)                 /*!< DOUTTOMEMINT (Bitfield-Mask: 0x01)                    */
29669 #define CRYPTO_HOSTRGFIRR_MEMTODININT_Pos (6UL)                     /*!< MEMTODININT (Bit 6)                                   */
29670 #define CRYPTO_HOSTRGFIRR_MEMTODININT_Msk (0x40UL)                  /*!< MEMTODININT (Bitfield-Mask: 0x01)                     */
29671 #define CRYPTO_HOSTRGFIRR_DOUTTOSRAMINT_Pos (5UL)                   /*!< DOUTTOSRAMINT (Bit 5)                                 */
29672 #define CRYPTO_HOSTRGFIRR_DOUTTOSRAMINT_Msk (0x20UL)                /*!< DOUTTOSRAMINT (Bitfield-Mask: 0x01)                   */
29673 #define CRYPTO_HOSTRGFIRR_SRAMTODININT_Pos (4UL)                    /*!< SRAMTODININT (Bit 4)                                  */
29674 #define CRYPTO_HOSTRGFIRR_SRAMTODININT_Msk (0x10UL)                 /*!< SRAMTODININT (Bitfield-Mask: 0x01)                    */
29675 /* ======================================================  HOSTRGFIMR  ======================================================= */
29676 #define CRYPTO_HOSTRGFIMR_SYMDMACOMPLETEDMASK_Pos (11UL)            /*!< SYMDMACOMPLETEDMASK (Bit 11)                          */
29677 #define CRYPTO_HOSTRGFIMR_SYMDMACOMPLETEDMASK_Msk (0x800UL)         /*!< SYMDMACOMPLETEDMASK (Bitfield-Mask: 0x01)             */
29678 #define CRYPTO_HOSTRGFIMR_RNGINTMASK_Pos  (10UL)                    /*!< RNGINTMASK (Bit 10)                                   */
29679 #define CRYPTO_HOSTRGFIMR_RNGINTMASK_Msk  (0x400UL)                 /*!< RNGINTMASK (Bitfield-Mask: 0x01)                      */
29680 #define CRYPTO_HOSTRGFIMR_PKAEXPMASK_Pos  (9UL)                     /*!< PKAEXPMASK (Bit 9)                                    */
29681 #define CRYPTO_HOSTRGFIMR_PKAEXPMASK_Msk  (0x200UL)                 /*!< PKAEXPMASK (Bitfield-Mask: 0x01)                      */
29682 #define CRYPTO_HOSTRGFIMR_AXIERRMASK_Pos  (8UL)                     /*!< AXIERRMASK (Bit 8)                                    */
29683 #define CRYPTO_HOSTRGFIMR_AXIERRMASK_Msk  (0x100UL)                 /*!< AXIERRMASK (Bitfield-Mask: 0x01)                      */
29684 #define CRYPTO_HOSTRGFIMR_DOUTTOMEMMASK_Pos (7UL)                   /*!< DOUTTOMEMMASK (Bit 7)                                 */
29685 #define CRYPTO_HOSTRGFIMR_DOUTTOMEMMASK_Msk (0x80UL)                /*!< DOUTTOMEMMASK (Bitfield-Mask: 0x01)                   */
29686 #define CRYPTO_HOSTRGFIMR_MEMTODINMASK_Pos (6UL)                    /*!< MEMTODINMASK (Bit 6)                                  */
29687 #define CRYPTO_HOSTRGFIMR_MEMTODINMASK_Msk (0x40UL)                 /*!< MEMTODINMASK (Bitfield-Mask: 0x01)                    */
29688 #define CRYPTO_HOSTRGFIMR_DOUTTOSRAMMASK_Pos (5UL)                  /*!< DOUTTOSRAMMASK (Bit 5)                                */
29689 #define CRYPTO_HOSTRGFIMR_DOUTTOSRAMMASK_Msk (0x20UL)               /*!< DOUTTOSRAMMASK (Bitfield-Mask: 0x01)                  */
29690 #define CRYPTO_HOSTRGFIMR_SRAMTODINMASK_Pos (4UL)                   /*!< SRAMTODINMASK (Bit 4)                                 */
29691 #define CRYPTO_HOSTRGFIMR_SRAMTODINMASK_Msk (0x10UL)                /*!< SRAMTODINMASK (Bitfield-Mask: 0x01)                   */
29692 /* ======================================================  HOSTRGFICR  ======================================================= */
29693 #define CRYPTO_HOSTRGFICR_SYMDMACOMPLETEDCLEAR_Pos (11UL)           /*!< SYMDMACOMPLETEDCLEAR (Bit 11)                         */
29694 #define CRYPTO_HOSTRGFICR_SYMDMACOMPLETEDCLEAR_Msk (0x800UL)        /*!< SYMDMACOMPLETEDCLEAR (Bitfield-Mask: 0x01)            */
29695 #define CRYPTO_HOSTRGFICR_RNGINTCLEAR_Pos (10UL)                    /*!< RNGINTCLEAR (Bit 10)                                  */
29696 #define CRYPTO_HOSTRGFICR_RNGINTCLEAR_Msk (0x400UL)                 /*!< RNGINTCLEAR (Bitfield-Mask: 0x01)                     */
29697 #define CRYPTO_HOSTRGFICR_PKAEXPCLEAR_Pos (9UL)                     /*!< PKAEXPCLEAR (Bit 9)                                   */
29698 #define CRYPTO_HOSTRGFICR_PKAEXPCLEAR_Msk (0x200UL)                 /*!< PKAEXPCLEAR (Bitfield-Mask: 0x01)                     */
29699 #define CRYPTO_HOSTRGFICR_AXIERRCLEAR_Pos (8UL)                     /*!< AXIERRCLEAR (Bit 8)                                   */
29700 #define CRYPTO_HOSTRGFICR_AXIERRCLEAR_Msk (0x100UL)                 /*!< AXIERRCLEAR (Bitfield-Mask: 0x01)                     */
29701 #define CRYPTO_HOSTRGFICR_DOUTTOMEMCLEAR_Pos (7UL)                  /*!< DOUTTOMEMCLEAR (Bit 7)                                */
29702 #define CRYPTO_HOSTRGFICR_DOUTTOMEMCLEAR_Msk (0x80UL)               /*!< DOUTTOMEMCLEAR (Bitfield-Mask: 0x01)                  */
29703 #define CRYPTO_HOSTRGFICR_MEMTODINCLEAR_Pos (6UL)                   /*!< MEMTODINCLEAR (Bit 6)                                 */
29704 #define CRYPTO_HOSTRGFICR_MEMTODINCLEAR_Msk (0x40UL)                /*!< MEMTODINCLEAR (Bitfield-Mask: 0x01)                   */
29705 #define CRYPTO_HOSTRGFICR_DOUTTOSRAMCLEAR_Pos (5UL)                 /*!< DOUTTOSRAMCLEAR (Bit 5)                               */
29706 #define CRYPTO_HOSTRGFICR_DOUTTOSRAMCLEAR_Msk (0x20UL)              /*!< DOUTTOSRAMCLEAR (Bitfield-Mask: 0x01)                 */
29707 #define CRYPTO_HOSTRGFICR_SRAMTODINCLEAR_Pos (4UL)                  /*!< SRAMTODINCLEAR (Bit 4)                                */
29708 #define CRYPTO_HOSTRGFICR_SRAMTODINCLEAR_Msk (0x10UL)               /*!< SRAMTODINCLEAR (Bitfield-Mask: 0x01)                  */
29709 /* =====================================================  HOSTRGFENDIAN  ===================================================== */
29710 #define CRYPTO_HOSTRGFENDIAN_DINRDWBG_Pos (15UL)                    /*!< DINRDWBG (Bit 15)                                     */
29711 #define CRYPTO_HOSTRGFENDIAN_DINRDWBG_Msk (0x8000UL)                /*!< DINRDWBG (Bitfield-Mask: 0x01)                        */
29712 #define CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Pos (11UL)                   /*!< DOUTWRWBG (Bit 11)                                    */
29713 #define CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Msk (0x800UL)                /*!< DOUTWRWBG (Bitfield-Mask: 0x01)                       */
29714 #define CRYPTO_HOSTRGFENDIAN_DINRDBG_Pos  (7UL)                     /*!< DINRDBG (Bit 7)                                       */
29715 #define CRYPTO_HOSTRGFENDIAN_DINRDBG_Msk  (0x80UL)                  /*!< DINRDBG (Bitfield-Mask: 0x01)                         */
29716 #define CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Pos (3UL)                     /*!< DOUTWRBG (Bit 3)                                      */
29717 #define CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Msk (0x8UL)                   /*!< DOUTWRBG (Bitfield-Mask: 0x01)                        */
29718 /* ===================================================  HOSTRGFSIGNATURE  ==================================================== */
29719 #define CRYPTO_HOSTRGFSIGNATURE_HOSTSIGNATURE_Pos (0UL)             /*!< HOSTSIGNATURE (Bit 0)                                 */
29720 #define CRYPTO_HOSTRGFSIGNATURE_HOSTSIGNATURE_Msk (0xffffffffUL)    /*!< HOSTSIGNATURE (Bitfield-Mask: 0xffffffff)             */
29721 /* =======================================================  HOSTBOOT  ======================================================== */
29722 #define CRYPTO_HOSTBOOT_AESEXISTSLOCAL_Pos (30UL)                   /*!< AESEXISTSLOCAL (Bit 30)                               */
29723 #define CRYPTO_HOSTBOOT_AESEXISTSLOCAL_Msk (0x40000000UL)           /*!< AESEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29724 #define CRYPTO_HOSTBOOT_ONLYENCRYPTLOCAL_Pos (29UL)                 /*!< ONLYENCRYPTLOCAL (Bit 29)                             */
29725 #define CRYPTO_HOSTBOOT_ONLYENCRYPTLOCAL_Msk (0x20000000UL)         /*!< ONLYENCRYPTLOCAL (Bitfield-Mask: 0x01)                */
29726 #define CRYPTO_HOSTBOOT_SUPPORT256192KEYLOCAL_Pos (28UL)            /*!< SUPPORT256192KEYLOCAL (Bit 28)                        */
29727 #define CRYPTO_HOSTBOOT_SUPPORT256192KEYLOCAL_Msk (0x10000000UL)    /*!< SUPPORT256192KEYLOCAL (Bitfield-Mask: 0x01)           */
29728 #define CRYPTO_HOSTBOOT_TUNNELINGENBLOCAL_Pos (27UL)                /*!< TUNNELINGENBLOCAL (Bit 27)                            */
29729 #define CRYPTO_HOSTBOOT_TUNNELINGENBLOCAL_Msk (0x8000000UL)         /*!< TUNNELINGENBLOCAL (Bitfield-Mask: 0x01)               */
29730 #define CRYPTO_HOSTBOOT_AESDINBYTERESOLUTIONLOCAL_Pos (26UL)        /*!< AESDINBYTERESOLUTIONLOCAL (Bit 26)                    */
29731 #define CRYPTO_HOSTBOOT_AESDINBYTERESOLUTIONLOCAL_Msk (0x4000000UL) /*!< AESDINBYTERESOLUTIONLOCAL (Bitfield-Mask: 0x01)       */
29732 #define CRYPTO_HOSTBOOT_CTREXISTSLOCAL_Pos (25UL)                   /*!< CTREXISTSLOCAL (Bit 25)                               */
29733 #define CRYPTO_HOSTBOOT_CTREXISTSLOCAL_Msk (0x2000000UL)            /*!< CTREXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29734 #define CRYPTO_HOSTBOOT_AESXEXEXISTSLOCAL_Pos (24UL)                /*!< AESXEXEXISTSLOCAL (Bit 24)                            */
29735 #define CRYPTO_HOSTBOOT_AESXEXEXISTSLOCAL_Msk (0x1000000UL)         /*!< AESXEXEXISTSLOCAL (Bitfield-Mask: 0x01)               */
29736 #define CRYPTO_HOSTBOOT_AESXEXHWTCALCLOCAL_Pos (23UL)               /*!< AESXEXHWTCALCLOCAL (Bit 23)                           */
29737 #define CRYPTO_HOSTBOOT_AESXEXHWTCALCLOCAL_Msk (0x800000UL)         /*!< AESXEXHWTCALCLOCAL (Bitfield-Mask: 0x01)              */
29738 #define CRYPTO_HOSTBOOT_AESCCMEXISTSLOCAL_Pos (22UL)                /*!< AESCCMEXISTSLOCAL (Bit 22)                            */
29739 #define CRYPTO_HOSTBOOT_AESCCMEXISTSLOCAL_Msk (0x400000UL)          /*!< AESCCMEXISTSLOCAL (Bitfield-Mask: 0x01)               */
29740 #define CRYPTO_HOSTBOOT_AESCMACEXISTSLOCAL_Pos (21UL)               /*!< AESCMACEXISTSLOCAL (Bit 21)                           */
29741 #define CRYPTO_HOSTBOOT_AESCMACEXISTSLOCAL_Msk (0x200000UL)         /*!< AESCMACEXISTSLOCAL (Bitfield-Mask: 0x01)              */
29742 #define CRYPTO_HOSTBOOT_AESXCBCMACEXISTSLOCAL_Pos (20UL)            /*!< AESXCBCMACEXISTSLOCAL (Bit 20)                        */
29743 #define CRYPTO_HOSTBOOT_AESXCBCMACEXISTSLOCAL_Msk (0x100000UL)      /*!< AESXCBCMACEXISTSLOCAL (Bitfield-Mask: 0x01)           */
29744 #define CRYPTO_HOSTBOOT_DESEXISTSLOCAL_Pos (19UL)                   /*!< DESEXISTSLOCAL (Bit 19)                               */
29745 #define CRYPTO_HOSTBOOT_DESEXISTSLOCAL_Msk (0x80000UL)              /*!< DESEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29746 #define CRYPTO_HOSTBOOT_C2EXISTSLOCAL_Pos (18UL)                    /*!< C2EXISTSLOCAL (Bit 18)                                */
29747 #define CRYPTO_HOSTBOOT_C2EXISTSLOCAL_Msk (0x40000UL)               /*!< C2EXISTSLOCAL (Bitfield-Mask: 0x01)                   */
29748 #define CRYPTO_HOSTBOOT_HASHEXISTSLOCAL_Pos (17UL)                  /*!< HASHEXISTSLOCAL (Bit 17)                              */
29749 #define CRYPTO_HOSTBOOT_HASHEXISTSLOCAL_Msk (0x20000UL)             /*!< HASHEXISTSLOCAL (Bitfield-Mask: 0x01)                 */
29750 #define CRYPTO_HOSTBOOT_MD5PRSNTLOCAL_Pos (16UL)                    /*!< MD5PRSNTLOCAL (Bit 16)                                */
29751 #define CRYPTO_HOSTBOOT_MD5PRSNTLOCAL_Msk (0x10000UL)               /*!< MD5PRSNTLOCAL (Bitfield-Mask: 0x01)                   */
29752 #define CRYPTO_HOSTBOOT_SHA256PRSNTLOCAL_Pos (15UL)                 /*!< SHA256PRSNTLOCAL (Bit 15)                             */
29753 #define CRYPTO_HOSTBOOT_SHA256PRSNTLOCAL_Msk (0x8000UL)             /*!< SHA256PRSNTLOCAL (Bitfield-Mask: 0x01)                */
29754 #define CRYPTO_HOSTBOOT_SHA512PRSNTLOCAL_Pos (14UL)                 /*!< SHA512PRSNTLOCAL (Bit 14)                             */
29755 #define CRYPTO_HOSTBOOT_SHA512PRSNTLOCAL_Msk (0x4000UL)             /*!< SHA512PRSNTLOCAL (Bitfield-Mask: 0x01)                */
29756 #define CRYPTO_HOSTBOOT_RC4EXISTSLOCAL_Pos (13UL)                   /*!< RC4EXISTSLOCAL (Bit 13)                               */
29757 #define CRYPTO_HOSTBOOT_RC4EXISTSLOCAL_Msk (0x2000UL)               /*!< RC4EXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29758 #define CRYPTO_HOSTBOOT_PKAEXISTSLOCAL_Pos (12UL)                   /*!< PKAEXISTSLOCAL (Bit 12)                               */
29759 #define CRYPTO_HOSTBOOT_PKAEXISTSLOCAL_Msk (0x1000UL)               /*!< PKAEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29760 #define CRYPTO_HOSTBOOT_RNGEXISTSLOCAL_Pos (11UL)                   /*!< RNGEXISTSLOCAL (Bit 11)                               */
29761 #define CRYPTO_HOSTBOOT_RNGEXISTSLOCAL_Msk (0x800UL)                /*!< RNGEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29762 #define CRYPTO_HOSTBOOT_PAUEXISTSLOCAL_Pos (10UL)                   /*!< PAUEXISTSLOCAL (Bit 10)                               */
29763 #define CRYPTO_HOSTBOOT_PAUEXISTSLOCAL_Msk (0x400UL)                /*!< PAUEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
29764 #define CRYPTO_HOSTBOOT_DSCRPTREXISTSLOCAL_Pos (9UL)                /*!< DSCRPTREXISTSLOCAL (Bit 9)                            */
29765 #define CRYPTO_HOSTBOOT_DSCRPTREXISTSLOCAL_Msk (0x200UL)            /*!< DSCRPTREXISTSLOCAL (Bitfield-Mask: 0x01)              */
29766 #define CRYPTO_HOSTBOOT_SRAMSIZELOCAL_Pos (6UL)                     /*!< SRAMSIZELOCAL (Bit 6)                                 */
29767 #define CRYPTO_HOSTBOOT_SRAMSIZELOCAL_Msk (0x1c0UL)                 /*!< SRAMSIZELOCAL (Bitfield-Mask: 0x07)                   */
29768 #define CRYPTO_HOSTBOOT_RKEKECCEXISTSLOCALN_Pos (5UL)               /*!< RKEKECCEXISTSLOCALN (Bit 5)                           */
29769 #define CRYPTO_HOSTBOOT_RKEKECCEXISTSLOCALN_Msk (0x20UL)            /*!< RKEKECCEXISTSLOCALN (Bitfield-Mask: 0x01)             */
29770 #define CRYPTO_HOSTBOOT_EXTMEMSECUREDLOCAL_Pos (3UL)                /*!< EXTMEMSECUREDLOCAL (Bit 3)                            */
29771 #define CRYPTO_HOSTBOOT_EXTMEMSECUREDLOCAL_Msk (0x8UL)              /*!< EXTMEMSECUREDLOCAL (Bitfield-Mask: 0x01)              */
29772 #define CRYPTO_HOSTBOOT_HASHINFUSESLOCAL_Pos (2UL)                  /*!< HASHINFUSESLOCAL (Bit 2)                              */
29773 #define CRYPTO_HOSTBOOT_HASHINFUSESLOCAL_Msk (0x4UL)                /*!< HASHINFUSESLOCAL (Bitfield-Mask: 0x01)                */
29774 #define CRYPTO_HOSTBOOT_LARGERKEKLOCAL_Pos (1UL)                    /*!< LARGERKEKLOCAL (Bit 1)                                */
29775 #define CRYPTO_HOSTBOOT_LARGERKEKLOCAL_Msk (0x2UL)                  /*!< LARGERKEKLOCAL (Bitfield-Mask: 0x01)                  */
29776 #define CRYPTO_HOSTBOOT_SYNTHESISCONFIG_Pos (0UL)                   /*!< SYNTHESISCONFIG (Bit 0)                               */
29777 #define CRYPTO_HOSTBOOT_SYNTHESISCONFIG_Msk (0x1UL)                 /*!< SYNTHESISCONFIG (Bitfield-Mask: 0x01)                 */
29778 /* ===================================================  HOSTCRYPTOKEYSEL  ==================================================== */
29779 #define CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Pos (0UL)              /*!< SELCRYPTOKEY (Bit 0)                                  */
29780 #define CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Msk (0x7UL)            /*!< SELCRYPTOKEY (Bitfield-Mask: 0x07)                    */
29781 /* ================================================  HOSTCORECLKGATINGENABLE  ================================================ */
29782 #define CRYPTO_HOSTCORECLKGATINGENABLE_HOSTCORECLKGATINGENABLE_Pos (0UL) /*!< HOSTCORECLKGATINGENABLE (Bit 0)                  */
29783 #define CRYPTO_HOSTCORECLKGATINGENABLE_HOSTCORECLKGATINGENABLE_Msk (0x1UL) /*!< HOSTCORECLKGATINGENABLE (Bitfield-Mask: 0x01)  */
29784 /* =====================================================  HOSTCCISIDLE  ====================================================== */
29785 #define CRYPTO_HOSTCCISIDLE_CRYPTOISIDLE_Pos (9UL)                  /*!< CRYPTOISIDLE (Bit 9)                                  */
29786 #define CRYPTO_HOSTCCISIDLE_CRYPTOISIDLE_Msk (0x200UL)              /*!< CRYPTOISIDLE (Bitfield-Mask: 0x01)                    */
29787 #define CRYPTO_HOSTCCISIDLE_PKAISIDLE_Pos (8UL)                     /*!< PKAISIDLE (Bit 8)                                     */
29788 #define CRYPTO_HOSTCCISIDLE_PKAISIDLE_Msk (0x100UL)                 /*!< PKAISIDLE (Bitfield-Mask: 0x01)                       */
29789 #define CRYPTO_HOSTCCISIDLE_RNGISIDLE_Pos (7UL)                     /*!< RNGISIDLE (Bit 7)                                     */
29790 #define CRYPTO_HOSTCCISIDLE_RNGISIDLE_Msk (0x80UL)                  /*!< RNGISIDLE (Bitfield-Mask: 0x01)                       */
29791 #define CRYPTO_HOSTCCISIDLE_FATALWR_Pos   (6UL)                     /*!< FATALWR (Bit 6)                                       */
29792 #define CRYPTO_HOSTCCISIDLE_FATALWR_Msk   (0x40UL)                  /*!< FATALWR (Bitfield-Mask: 0x01)                         */
29793 #define CRYPTO_HOSTCCISIDLE_NVMISIDLE_Pos (5UL)                     /*!< NVMISIDLE (Bit 5)                                     */
29794 #define CRYPTO_HOSTCCISIDLE_NVMISIDLE_Msk (0x20UL)                  /*!< NVMISIDLE (Bitfield-Mask: 0x01)                       */
29795 #define CRYPTO_HOSTCCISIDLE_NVMARBISIDLE_Pos (4UL)                  /*!< NVMARBISIDLE (Bit 4)                                  */
29796 #define CRYPTO_HOSTCCISIDLE_NVMARBISIDLE_Msk (0x10UL)               /*!< NVMARBISIDLE (Bitfield-Mask: 0x01)                    */
29797 #define CRYPTO_HOSTCCISIDLE_AHBISIDLE_Pos (3UL)                     /*!< AHBISIDLE (Bit 3)                                     */
29798 #define CRYPTO_HOSTCCISIDLE_AHBISIDLE_Msk (0x8UL)                   /*!< AHBISIDLE (Bitfield-Mask: 0x01)                       */
29799 #define CRYPTO_HOSTCCISIDLE_SYMISBUSY_Pos (2UL)                     /*!< SYMISBUSY (Bit 2)                                     */
29800 #define CRYPTO_HOSTCCISIDLE_SYMISBUSY_Msk (0x4UL)                   /*!< SYMISBUSY (Bitfield-Mask: 0x01)                       */
29801 #define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLEEVENT_Pos (1UL)             /*!< HOSTCCISIDLEEVENT (Bit 1)                             */
29802 #define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLEEVENT_Msk (0x2UL)           /*!< HOSTCCISIDLEEVENT (Bitfield-Mask: 0x01)               */
29803 #define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLE_Pos (0UL)                  /*!< HOSTCCISIDLE (Bit 0)                                  */
29804 #define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLE_Msk (0x1UL)                /*!< HOSTCCISIDLE (Bitfield-Mask: 0x01)                    */
29805 /* =====================================================  HOSTPOWERDOWN  ===================================================== */
29806 #define CRYPTO_HOSTPOWERDOWN_HOSTPOWERDOWN_Pos (0UL)                /*!< HOSTPOWERDOWN (Bit 0)                                 */
29807 #define CRYPTO_HOSTPOWERDOWN_HOSTPOWERDOWN_Msk (0x1UL)              /*!< HOSTPOWERDOWN (Bitfield-Mask: 0x01)                   */
29808 /* =================================================  HOSTREMOVEGHASHENGINE  ================================================= */
29809 #define CRYPTO_HOSTREMOVEGHASHENGINE_HOSTREMOVEGHASHENGINE_Pos (0UL) /*!< HOSTREMOVEGHASHENGINE (Bit 0)                        */
29810 #define CRYPTO_HOSTREMOVEGHASHENGINE_HOSTREMOVEGHASHENGINE_Msk (0x1UL) /*!< HOSTREMOVEGHASHENGINE (Bitfield-Mask: 0x01)        */
29811 /* ================================================  HOSTREMOVECHACHAENGINE  ================================================= */
29812 #define CRYPTO_HOSTREMOVECHACHAENGINE_HOSTREMOVECHACHAENGINE_Pos (0UL) /*!< HOSTREMOVECHACHAENGINE (Bit 0)                     */
29813 #define CRYPTO_HOSTREMOVECHACHAENGINE_HOSTREMOVECHACHAENGINE_Msk (0x1UL) /*!< HOSTREMOVECHACHAENGINE (Bitfield-Mask: 0x01)     */
29814 /* ======================================================  AHBMSINGLES  ====================================================== */
29815 #define CRYPTO_AHBMSINGLES_AHBSINGLES_Pos (0UL)                     /*!< AHBSINGLES (Bit 0)                                    */
29816 #define CRYPTO_AHBMSINGLES_AHBSINGLES_Msk (0x1UL)                   /*!< AHBSINGLES (Bitfield-Mask: 0x01)                      */
29817 /* =======================================================  AHBMHPROT  ======================================================= */
29818 #define CRYPTO_AHBMHPROT_AHBPROT_Pos      (0UL)                     /*!< AHBPROT (Bit 0)                                       */
29819 #define CRYPTO_AHBMHPROT_AHBPROT_Msk      (0xfUL)                   /*!< AHBPROT (Bitfield-Mask: 0x0f)                         */
29820 /* =====================================================  AHBMHMASTLOCK  ===================================================== */
29821 #define CRYPTO_AHBMHMASTLOCK_AHBHMASTLOCK_Pos (0UL)                 /*!< AHBHMASTLOCK (Bit 0)                                  */
29822 #define CRYPTO_AHBMHMASTLOCK_AHBHMASTLOCK_Msk (0x1UL)               /*!< AHBHMASTLOCK (Bitfield-Mask: 0x01)                    */
29823 /* ======================================================  AHBMHNONSEC  ====================================================== */
29824 #define CRYPTO_AHBMHNONSEC_AHBREADHNONSEC_Pos (1UL)                 /*!< AHBREADHNONSEC (Bit 1)                                */
29825 #define CRYPTO_AHBMHNONSEC_AHBREADHNONSEC_Msk (0x2UL)               /*!< AHBREADHNONSEC (Bitfield-Mask: 0x01)                  */
29826 #define CRYPTO_AHBMHNONSEC_AHBWRITEHNONSEC_Pos (0UL)                /*!< AHBWRITEHNONSEC (Bit 0)                               */
29827 #define CRYPTO_AHBMHNONSEC_AHBWRITEHNONSEC_Msk (0x1UL)              /*!< AHBWRITEHNONSEC (Bitfield-Mask: 0x01)                 */
29828 /* =======================================================  DINBUFFER  ======================================================= */
29829 #define CRYPTO_DINBUFFER_DINBUFFERDATA_Pos (0UL)                    /*!< DINBUFFERDATA (Bit 0)                                 */
29830 #define CRYPTO_DINBUFFER_DINBUFFERDATA_Msk (0xffffffffUL)           /*!< DINBUFFERDATA (Bitfield-Mask: 0xffffffff)             */
29831 /* =====================================================  DINMEMDMABUSY  ===================================================== */
29832 #define CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Pos (0UL)                /*!< DINMEMDMABUSY (Bit 0)                                 */
29833 #define CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Msk (0x1UL)              /*!< DINMEMDMABUSY (Bitfield-Mask: 0x01)                   */
29834 /* ======================================================  SRCLLIWORD0  ====================================================== */
29835 #define CRYPTO_SRCLLIWORD0_SRCLLIWORD0_Pos (0UL)                    /*!< SRCLLIWORD0 (Bit 0)                                   */
29836 #define CRYPTO_SRCLLIWORD0_SRCLLIWORD0_Msk (0xffffffffUL)           /*!< SRCLLIWORD0 (Bitfield-Mask: 0xffffffff)               */
29837 /* ======================================================  SRCLLIWORD1  ====================================================== */
29838 #define CRYPTO_SRCLLIWORD1_LAST_Pos       (31UL)                    /*!< LAST (Bit 31)                                         */
29839 #define CRYPTO_SRCLLIWORD1_LAST_Msk       (0x80000000UL)            /*!< LAST (Bitfield-Mask: 0x01)                            */
29840 #define CRYPTO_SRCLLIWORD1_FIRST_Pos      (30UL)                    /*!< FIRST (Bit 30)                                        */
29841 #define CRYPTO_SRCLLIWORD1_FIRST_Msk      (0x40000000UL)            /*!< FIRST (Bitfield-Mask: 0x01)                           */
29842 #define CRYPTO_SRCLLIWORD1_BYTESNUM_Pos   (0UL)                     /*!< BYTESNUM (Bit 0)                                      */
29843 #define CRYPTO_SRCLLIWORD1_BYTESNUM_Msk   (0x3fffffffUL)            /*!< BYTESNUM (Bitfield-Mask: 0x3fffffff)                  */
29844 /* ======================================================  SRAMSRCADDR  ====================================================== */
29845 #define CRYPTO_SRAMSRCADDR_SRAMSOURCE_Pos (0UL)                     /*!< SRAMSOURCE (Bit 0)                                    */
29846 #define CRYPTO_SRAMSRCADDR_SRAMSOURCE_Msk (0xffffffffUL)            /*!< SRAMSOURCE (Bitfield-Mask: 0xffffffff)                */
29847 /* ====================================================  DINSRAMBYTESLEN  ==================================================== */
29848 #define CRYPTO_DINSRAMBYTESLEN_BYTESLEN_Pos (0UL)                   /*!< BYTESLEN (Bit 0)                                      */
29849 #define CRYPTO_DINSRAMBYTESLEN_BYTESLEN_Msk (0xffffffffUL)          /*!< BYTESLEN (Bitfield-Mask: 0xffffffff)                  */
29850 /* ====================================================  DINSRAMDMABUSY  ===================================================== */
29851 #define CRYPTO_DINSRAMDMABUSY_BUSY_Pos    (0UL)                     /*!< BUSY (Bit 0)                                          */
29852 #define CRYPTO_DINSRAMDMABUSY_BUSY_Msk    (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
29853 /* ===================================================  DINSRAMENDIANNESS  =================================================== */
29854 #define CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Pos (0UL)        /*!< SRAMDINENDIANNESS (Bit 0)                             */
29855 #define CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Msk (0x1UL)      /*!< SRAMDINENDIANNESS (Bitfield-Mask: 0x01)               */
29856 /* ====================================================  DINCPUDATASIZE  ===================================================== */
29857 #define CRYPTO_DINCPUDATASIZE_CPUDINSIZE_Pos (0UL)                  /*!< CPUDINSIZE (Bit 0)                                    */
29858 #define CRYPTO_DINCPUDATASIZE_CPUDINSIZE_Msk (0xffffUL)             /*!< CPUDINSIZE (Bitfield-Mask: 0xffff)                    */
29859 /* ======================================================  FIFOINEMPTY  ====================================================== */
29860 #define CRYPTO_FIFOINEMPTY_EMPTY_Pos      (0UL)                     /*!< EMPTY (Bit 0)                                         */
29861 #define CRYPTO_FIFOINEMPTY_EMPTY_Msk      (0x1UL)                   /*!< EMPTY (Bitfield-Mask: 0x01)                           */
29862 /* ====================================================  DINFIFORSTPNTR  ===================================================== */
29863 #define CRYPTO_DINFIFORSTPNTR_RST_Pos     (0UL)                     /*!< RST (Bit 0)                                           */
29864 #define CRYPTO_DINFIFORSTPNTR_RST_Msk     (0x1UL)                   /*!< RST (Bitfield-Mask: 0x01)                             */
29865 /* ======================================================  DOUTBUFFER  ======================================================= */
29866 #define CRYPTO_DOUTBUFFER_DATA_Pos        (0UL)                     /*!< DATA (Bit 0)                                          */
29867 #define CRYPTO_DOUTBUFFER_DATA_Msk        (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
29868 /* ====================================================  DOUTMEMDMABUSY  ===================================================== */
29869 #define CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Pos (0UL)              /*!< DOUTMEMDMABUSY (Bit 0)                                */
29870 #define CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Msk (0x1UL)            /*!< DOUTMEMDMABUSY (Bitfield-Mask: 0x01)                  */
29871 /* ======================================================  DSTLLIWORD0  ====================================================== */
29872 #define CRYPTO_DSTLLIWORD0_DSTLLIWORD0_Pos (0UL)                    /*!< DSTLLIWORD0 (Bit 0)                                   */
29873 #define CRYPTO_DSTLLIWORD0_DSTLLIWORD0_Msk (0xffffffffUL)           /*!< DSTLLIWORD0 (Bitfield-Mask: 0xffffffff)               */
29874 /* ======================================================  DSTLLIWORD1  ====================================================== */
29875 #define CRYPTO_DSTLLIWORD1_LAST_Pos       (31UL)                    /*!< LAST (Bit 31)                                         */
29876 #define CRYPTO_DSTLLIWORD1_LAST_Msk       (0x80000000UL)            /*!< LAST (Bitfield-Mask: 0x01)                            */
29877 #define CRYPTO_DSTLLIWORD1_FIRST_Pos      (30UL)                    /*!< FIRST (Bit 30)                                        */
29878 #define CRYPTO_DSTLLIWORD1_FIRST_Msk      (0x40000000UL)            /*!< FIRST (Bitfield-Mask: 0x01)                           */
29879 #define CRYPTO_DSTLLIWORD1_BYTESNUM_Pos   (0UL)                     /*!< BYTESNUM (Bit 0)                                      */
29880 #define CRYPTO_DSTLLIWORD1_BYTESNUM_Msk   (0x3fffffffUL)            /*!< BYTESNUM (Bitfield-Mask: 0x3fffffff)                  */
29881 /* =====================================================  SRAMDESTADDR  ====================================================== */
29882 #define CRYPTO_SRAMDESTADDR_SRAMDEST_Pos  (0UL)                     /*!< SRAMDEST (Bit 0)                                      */
29883 #define CRYPTO_SRAMDESTADDR_SRAMDEST_Msk  (0xffffffffUL)            /*!< SRAMDEST (Bitfield-Mask: 0xffffffff)                  */
29884 /* ===================================================  DOUTSRAMBYTESLEN  ==================================================== */
29885 #define CRYPTO_DOUTSRAMBYTESLEN_BYTESLEN_Pos (0UL)                  /*!< BYTESLEN (Bit 0)                                      */
29886 #define CRYPTO_DOUTSRAMBYTESLEN_BYTESLEN_Msk (0xffffffffUL)         /*!< BYTESLEN (Bitfield-Mask: 0xffffffff)                  */
29887 /* ====================================================  DOUTSRAMDMABUSY  ==================================================== */
29888 #define CRYPTO_DOUTSRAMDMABUSY_BUSY_Pos   (0UL)                     /*!< BUSY (Bit 0)                                          */
29889 #define CRYPTO_DOUTSRAMDMABUSY_BUSY_Msk   (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
29890 /* ==================================================  DOUTSRAMENDIANNESS  =================================================== */
29891 #define CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Pos (0UL)      /*!< DOUTSRAMENDIANNESS (Bit 0)                            */
29892 #define CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Msk (0x1UL)    /*!< DOUTSRAMENDIANNESS (Bitfield-Mask: 0x01)              */
29893 /* =====================================================  READALIGNLAST  ===================================================== */
29894 #define CRYPTO_READALIGNLAST_LAST_Pos     (0UL)                     /*!< LAST (Bit 0)                                          */
29895 #define CRYPTO_READALIGNLAST_LAST_Msk     (0x1UL)                   /*!< LAST (Bitfield-Mask: 0x01)                            */
29896 /* =====================================================  DOUTFIFOEMPTY  ===================================================== */
29897 #define CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Pos (0UL)                /*!< DOUTFIFOEMPTY (Bit 0)                                 */
29898 #define CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Msk (0x1UL)              /*!< DOUTFIFOEMPTY (Bitfield-Mask: 0x01)                   */
29899 /* =======================================================  SRAMDATA  ======================================================== */
29900 #define CRYPTO_SRAMDATA_SRAMDATA_Pos      (0UL)                     /*!< SRAMDATA (Bit 0)                                      */
29901 #define CRYPTO_SRAMDATA_SRAMDATA_Msk      (0xffffffffUL)            /*!< SRAMDATA (Bitfield-Mask: 0xffffffff)                  */
29902 /* =======================================================  SRAMADDR  ======================================================== */
29903 #define CRYPTO_SRAMADDR_SRAMADDR_Pos      (0UL)                     /*!< SRAMADDR (Bit 0)                                      */
29904 #define CRYPTO_SRAMADDR_SRAMADDR_Msk      (0x7fffUL)                /*!< SRAMADDR (Bitfield-Mask: 0x7fff)                      */
29905 /* =====================================================  SRAMDATAREADY  ===================================================== */
29906 #define CRYPTO_SRAMDATAREADY_SRAMREADY_Pos (0UL)                    /*!< SRAMREADY (Bit 0)                                     */
29907 #define CRYPTO_SRAMDATAREADY_SRAMREADY_Msk (0x1UL)                  /*!< SRAMREADY (Bitfield-Mask: 0x01)                       */
29908 /* =====================================================  PERIPHERALID4  ===================================================== */
29909 #define CRYPTO_PERIPHERALID4_DES2JEP106_Pos (0UL)                   /*!< DES2JEP106 (Bit 0)                                    */
29910 #define CRYPTO_PERIPHERALID4_DES2JEP106_Msk (0xfUL)                 /*!< DES2JEP106 (Bitfield-Mask: 0x0f)                      */
29911 /* =====================================================  PERIPHERALID0  ===================================================== */
29912 #define CRYPTO_PERIPHERALID0_PART0_Pos    (0UL)                     /*!< PART0 (Bit 0)                                         */
29913 #define CRYPTO_PERIPHERALID0_PART0_Msk    (0xffUL)                  /*!< PART0 (Bitfield-Mask: 0xff)                           */
29914 /* =====================================================  PERIPHERALID1  ===================================================== */
29915 #define CRYPTO_PERIPHERALID1_DES0JEP106_Pos (4UL)                   /*!< DES0JEP106 (Bit 4)                                    */
29916 #define CRYPTO_PERIPHERALID1_DES0JEP106_Msk (0xf0UL)                /*!< DES0JEP106 (Bitfield-Mask: 0x0f)                      */
29917 #define CRYPTO_PERIPHERALID1_PART1_Pos    (0UL)                     /*!< PART1 (Bit 0)                                         */
29918 #define CRYPTO_PERIPHERALID1_PART1_Msk    (0xfUL)                   /*!< PART1 (Bitfield-Mask: 0x0f)                           */
29919 /* =====================================================  PERIPHERALID2  ===================================================== */
29920 #define CRYPTO_PERIPHERALID2_REVISION_Pos (4UL)                     /*!< REVISION (Bit 4)                                      */
29921 #define CRYPTO_PERIPHERALID2_REVISION_Msk (0xf0UL)                  /*!< REVISION (Bitfield-Mask: 0x0f)                        */
29922 #define CRYPTO_PERIPHERALID2_JEDEC_Pos    (3UL)                     /*!< JEDEC (Bit 3)                                         */
29923 #define CRYPTO_PERIPHERALID2_JEDEC_Msk    (0x8UL)                   /*!< JEDEC (Bitfield-Mask: 0x01)                           */
29924 #define CRYPTO_PERIPHERALID2_DES1JEP106_Pos (0UL)                   /*!< DES1JEP106 (Bit 0)                                    */
29925 #define CRYPTO_PERIPHERALID2_DES1JEP106_Msk (0x7UL)                 /*!< DES1JEP106 (Bitfield-Mask: 0x07)                      */
29926 /* =====================================================  PERIPHERALID3  ===================================================== */
29927 #define CRYPTO_PERIPHERALID3_REVAND_Pos   (4UL)                     /*!< REVAND (Bit 4)                                        */
29928 #define CRYPTO_PERIPHERALID3_REVAND_Msk   (0xf0UL)                  /*!< REVAND (Bitfield-Mask: 0x0f)                          */
29929 #define CRYPTO_PERIPHERALID3_CMOD_Pos     (0UL)                     /*!< CMOD (Bit 0)                                          */
29930 #define CRYPTO_PERIPHERALID3_CMOD_Msk     (0xfUL)                   /*!< CMOD (Bitfield-Mask: 0x0f)                            */
29931 /* =====================================================  COMPONENTID0  ====================================================== */
29932 #define CRYPTO_COMPONENTID0_PRMBL0_Pos    (0UL)                     /*!< PRMBL0 (Bit 0)                                        */
29933 #define CRYPTO_COMPONENTID0_PRMBL0_Msk    (0xffUL)                  /*!< PRMBL0 (Bitfield-Mask: 0xff)                          */
29934 /* =====================================================  COMPONENTID1  ====================================================== */
29935 #define CRYPTO_COMPONENTID1_CLASS_Pos     (4UL)                     /*!< CLASS (Bit 4)                                         */
29936 #define CRYPTO_COMPONENTID1_CLASS_Msk     (0xf0UL)                  /*!< CLASS (Bitfield-Mask: 0x0f)                           */
29937 #define CRYPTO_COMPONENTID1_PRMBL1_Pos    (0UL)                     /*!< PRMBL1 (Bit 0)                                        */
29938 #define CRYPTO_COMPONENTID1_PRMBL1_Msk    (0xfUL)                   /*!< PRMBL1 (Bitfield-Mask: 0x0f)                          */
29939 /* =====================================================  COMPONENTID2  ====================================================== */
29940 #define CRYPTO_COMPONENTID2_PRMBL2_Pos    (0UL)                     /*!< PRMBL2 (Bit 0)                                        */
29941 #define CRYPTO_COMPONENTID2_PRMBL2_Msk    (0xffUL)                  /*!< PRMBL2 (Bitfield-Mask: 0xff)                          */
29942 /* =====================================================  COMPONENTID3  ====================================================== */
29943 #define CRYPTO_COMPONENTID3_PRMBL3_Pos    (0UL)                     /*!< PRMBL3 (Bit 0)                                        */
29944 #define CRYPTO_COMPONENTID3_PRMBL3_Msk    (0xffUL)                  /*!< PRMBL3 (Bitfield-Mask: 0xff)                          */
29945 /* ======================================================  HOSTDCUEN0  ======================================================= */
29946 #define CRYPTO_HOSTDCUEN0_HOSTDCUEN0_Pos  (0UL)                     /*!< HOSTDCUEN0 (Bit 0)                                    */
29947 #define CRYPTO_HOSTDCUEN0_HOSTDCUEN0_Msk  (0xffffffffUL)            /*!< HOSTDCUEN0 (Bitfield-Mask: 0xffffffff)                */
29948 /* ======================================================  HOSTDCUEN1  ======================================================= */
29949 #define CRYPTO_HOSTDCUEN1_HOSTDCUEN1_Pos  (0UL)                     /*!< HOSTDCUEN1 (Bit 0)                                    */
29950 #define CRYPTO_HOSTDCUEN1_HOSTDCUEN1_Msk  (0xffffffffUL)            /*!< HOSTDCUEN1 (Bitfield-Mask: 0xffffffff)                */
29951 /* ======================================================  HOSTDCUEN2  ======================================================= */
29952 #define CRYPTO_HOSTDCUEN2_HOSTDCUEN2_Pos  (0UL)                     /*!< HOSTDCUEN2 (Bit 0)                                    */
29953 #define CRYPTO_HOSTDCUEN2_HOSTDCUEN2_Msk  (0xffffffffUL)            /*!< HOSTDCUEN2 (Bitfield-Mask: 0xffffffff)                */
29954 /* ======================================================  HOSTDCUEN3  ======================================================= */
29955 #define CRYPTO_HOSTDCUEN3_HOSTDCUEN3_Pos  (0UL)                     /*!< HOSTDCUEN3 (Bit 0)                                    */
29956 #define CRYPTO_HOSTDCUEN3_HOSTDCUEN3_Msk  (0xffffffffUL)            /*!< HOSTDCUEN3 (Bitfield-Mask: 0xffffffff)                */
29957 /* =====================================================  HOSTDCULOCK0  ====================================================== */
29958 #define CRYPTO_HOSTDCULOCK0_HOSTDCULOCK0_Pos (0UL)                  /*!< HOSTDCULOCK0 (Bit 0)                                  */
29959 #define CRYPTO_HOSTDCULOCK0_HOSTDCULOCK0_Msk (0xffffffffUL)         /*!< HOSTDCULOCK0 (Bitfield-Mask: 0xffffffff)              */
29960 /* =====================================================  HOSTDCULOCK1  ====================================================== */
29961 #define CRYPTO_HOSTDCULOCK1_HOSTDCULOCK1_Pos (0UL)                  /*!< HOSTDCULOCK1 (Bit 0)                                  */
29962 #define CRYPTO_HOSTDCULOCK1_HOSTDCULOCK1_Msk (0xffffffffUL)         /*!< HOSTDCULOCK1 (Bitfield-Mask: 0xffffffff)              */
29963 /* =====================================================  HOSTDCULOCK2  ====================================================== */
29964 #define CRYPTO_HOSTDCULOCK2_HOSTDCULOCK2_Pos (0UL)                  /*!< HOSTDCULOCK2 (Bit 0)                                  */
29965 #define CRYPTO_HOSTDCULOCK2_HOSTDCULOCK2_Msk (0xffffffffUL)         /*!< HOSTDCULOCK2 (Bitfield-Mask: 0xffffffff)              */
29966 /* =====================================================  HOSTDCULOCK3  ====================================================== */
29967 #define CRYPTO_HOSTDCULOCK3_HOSTDCULOCK3_Pos (0UL)                  /*!< HOSTDCULOCK3 (Bit 0)                                  */
29968 #define CRYPTO_HOSTDCULOCK3_HOSTDCULOCK3_Msk (0xffffffffUL)         /*!< HOSTDCULOCK3 (Bitfield-Mask: 0xffffffff)              */
29969 /* ===============================================  AOICVDCURESTRICTIONMASK0  ================================================ */
29970 #define CRYPTO_AOICVDCURESTRICTIONMASK0_AOICVDCURESTRICTIONMASK0_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK0 (Bit 0)               */
29971 #define CRYPTO_AOICVDCURESTRICTIONMASK0_AOICVDCURESTRICTIONMASK0_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK0 (Bitfield-Mask: 0xffffffff) */
29972 /* ===============================================  AOICVDCURESTRICTIONMASK1  ================================================ */
29973 #define CRYPTO_AOICVDCURESTRICTIONMASK1_AOICVDCURESTRICTIONMASK1_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK1 (Bit 0)               */
29974 #define CRYPTO_AOICVDCURESTRICTIONMASK1_AOICVDCURESTRICTIONMASK1_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK1 (Bitfield-Mask: 0xffffffff) */
29975 /* ===============================================  AOICVDCURESTRICTIONMASK2  ================================================ */
29976 #define CRYPTO_AOICVDCURESTRICTIONMASK2_AOICVDCURESTRICTIONMASK2_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK2 (Bit 0)               */
29977 #define CRYPTO_AOICVDCURESTRICTIONMASK2_AOICVDCURESTRICTIONMASK2_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK2 (Bitfield-Mask: 0xffffffff) */
29978 /* ===============================================  AOICVDCURESTRICTIONMASK3  ================================================ */
29979 #define CRYPTO_AOICVDCURESTRICTIONMASK3_AOICVDCURESTRICTIONMASK3_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK3 (Bit 0)               */
29980 #define CRYPTO_AOICVDCURESTRICTIONMASK3_AOICVDCURESTRICTIONMASK3_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK3 (Bitfield-Mask: 0xffffffff) */
29981 /* ===================================================  AOCCSECDEBUGRESET  =================================================== */
29982 #define CRYPTO_AOCCSECDEBUGRESET_AOCCSECDEBUGRESET_Pos (0UL)        /*!< AOCCSECDEBUGRESET (Bit 0)                             */
29983 #define CRYPTO_AOCCSECDEBUGRESET_AOCCSECDEBUGRESET_Msk (0x1UL)      /*!< AOCCSECDEBUGRESET (Bitfield-Mask: 0x01)               */
29984 /* ====================================================  HOSTAOLOCKBITS  ===================================================== */
29985 #define CRYPTO_HOSTAOLOCKBITS_HOSTDFAENABLELOCK_Pos (8UL)           /*!< HOSTDFAENABLELOCK (Bit 8)                             */
29986 #define CRYPTO_HOSTAOLOCKBITS_HOSTDFAENABLELOCK_Msk (0x100UL)       /*!< HOSTDFAENABLELOCK (Bitfield-Mask: 0x01)               */
29987 #define CRYPTO_HOSTAOLOCKBITS_HOSTFORCEDFAENABLE_Pos (7UL)          /*!< HOSTFORCEDFAENABLE (Bit 7)                            */
29988 #define CRYPTO_HOSTAOLOCKBITS_HOSTFORCEDFAENABLE_Msk (0x80UL)       /*!< HOSTFORCEDFAENABLE (Bitfield-Mask: 0x01)              */
29989 #define CRYPTO_HOSTAOLOCKBITS_RESETUPONDEBUGDISABLE_Pos (6UL)       /*!< RESETUPONDEBUGDISABLE (Bit 6)                         */
29990 #define CRYPTO_HOSTAOLOCKBITS_RESETUPONDEBUGDISABLE_Msk (0x40UL)    /*!< RESETUPONDEBUGDISABLE (Bitfield-Mask: 0x01)           */
29991 #define CRYPTO_HOSTAOLOCKBITS_HOSTICVRMALOCK_Pos (5UL)              /*!< HOSTICVRMALOCK (Bit 5)                                */
29992 #define CRYPTO_HOSTAOLOCKBITS_HOSTICVRMALOCK_Msk (0x20UL)           /*!< HOSTICVRMALOCK (Bitfield-Mask: 0x01)                  */
29993 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCELOCK_Pos (4UL)                 /*!< HOSTKCELOCK (Bit 4)                                   */
29994 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCELOCK_Msk (0x10UL)              /*!< HOSTKCELOCK (Bitfield-Mask: 0x01)                     */
29995 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCPLOCK_Pos (3UL)                 /*!< HOSTKCPLOCK (Bit 3)                                   */
29996 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCPLOCK_Msk (0x8UL)               /*!< HOSTKCPLOCK (Bitfield-Mask: 0x01)                     */
29997 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCEICVLOCK_Pos (2UL)              /*!< HOSTKCEICVLOCK (Bit 2)                                */
29998 #define CRYPTO_HOSTAOLOCKBITS_HOSTKCEICVLOCK_Msk (0x4UL)            /*!< HOSTKCEICVLOCK (Bitfield-Mask: 0x01)                  */
29999 #define CRYPTO_HOSTAOLOCKBITS_HOSTKPICVLOCK_Pos (1UL)               /*!< HOSTKPICVLOCK (Bit 1)                                 */
30000 #define CRYPTO_HOSTAOLOCKBITS_HOSTKPICVLOCK_Msk (0x2UL)             /*!< HOSTKPICVLOCK (Bitfield-Mask: 0x01)                   */
30001 #define CRYPTO_HOSTAOLOCKBITS_HOSTFATALERR_Pos (0UL)                /*!< HOSTFATALERR (Bit 0)                                  */
30002 #define CRYPTO_HOSTAOLOCKBITS_HOSTFATALERR_Msk (0x1UL)              /*!< HOSTFATALERR (Bitfield-Mask: 0x01)                    */
30003 /* ====================================================  AOAPBFILTERING  ===================================================== */
30004 #define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOWLOCK_Pos (9UL) /*!< APBCONLYINSTACCESSALLOWLOCK (Bit 9)                   */
30005 #define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOWLOCK_Msk (0x200UL) /*!< APBCONLYINSTACCESSALLOWLOCK (Bitfield-Mask: 0x01) */
30006 #define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOW_Pos (8UL)     /*!< APBCONLYINSTACCESSALLOW (Bit 8)                       */
30007 #define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOW_Msk (0x100UL) /*!< APBCONLYINSTACCESSALLOW (Bitfield-Mask: 0x01)         */
30008 #define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOWLOCK_Pos (7UL) /*!< APBCONLYPRIVACCESSALLOWLOCK (Bit 7)                   */
30009 #define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOWLOCK_Msk (0x80UL) /*!< APBCONLYPRIVACCESSALLOWLOCK (Bitfield-Mask: 0x01)  */
30010 #define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOW_Pos (6UL)     /*!< APBCONLYPRIVACCESSALLOW (Bit 6)                       */
30011 #define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOW_Msk (0x40UL)  /*!< APBCONLYPRIVACCESSALLOW (Bitfield-Mask: 0x01)         */
30012 #define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOWLOCK_Pos (5UL)  /*!< APBCONLYSECACCESSALLOWLOCK (Bit 5)                    */
30013 #define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOWLOCK_Msk (0x20UL) /*!< APBCONLYSECACCESSALLOWLOCK (Bitfield-Mask: 0x01)    */
30014 #define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOW_Pos (4UL)      /*!< APBCONLYSECACCESSALLOW (Bit 4)                        */
30015 #define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOW_Msk (0x10UL)   /*!< APBCONLYSECACCESSALLOW (Bitfield-Mask: 0x01)          */
30016 #define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOWLOCK_Pos (3UL)     /*!< ONLYPRIVACCESSALLOWLOCK (Bit 3)                       */
30017 #define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOWLOCK_Msk (0x8UL)   /*!< ONLYPRIVACCESSALLOWLOCK (Bitfield-Mask: 0x01)         */
30018 #define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOW_Pos (2UL)         /*!< ONLYPRIVACCESSALLOW (Bit 2)                           */
30019 #define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOW_Msk (0x4UL)       /*!< ONLYPRIVACCESSALLOW (Bitfield-Mask: 0x01)             */
30020 #define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOWLOCK_Pos (1UL)      /*!< ONLYSECACCESSALLOWLOCK (Bit 1)                        */
30021 #define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOWLOCK_Msk (0x2UL)    /*!< ONLYSECACCESSALLOWLOCK (Bitfield-Mask: 0x01)          */
30022 #define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOW_Pos (0UL)          /*!< ONLYSECACCESSALLOW (Bit 0)                            */
30023 #define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOW_Msk (0x1UL)        /*!< ONLYSECACCESSALLOW (Bitfield-Mask: 0x01)              */
30024 /* =======================================================  AOCCGPPC  ======================================================== */
30025 #define CRYPTO_AOCCGPPC_AOCCGPPC_Pos      (0UL)                     /*!< AOCCGPPC (Bit 0)                                      */
30026 #define CRYPTO_AOCCGPPC_AOCCGPPC_Msk      (0xffUL)                  /*!< AOCCGPPC (Bitfield-Mask: 0xff)                        */
30027 /* ====================================================  HOSTRGFCCSWRST  ===================================================== */
30028 #define CRYPTO_HOSTRGFCCSWRST_HOSTRGFCCSWRST_Pos (0UL)              /*!< HOSTRGFCCSWRST (Bit 0)                                */
30029 #define CRYPTO_HOSTRGFCCSWRST_HOSTRGFCCSWRST_Msk (0x1UL)            /*!< HOSTRGFCCSWRST (Bitfield-Mask: 0x01)                  */
30030 /* =================================================  AIBFUSEPROGCOMPLETED  ================================================== */
30031 #define CRYPTO_AIBFUSEPROGCOMPLETED_AIBFUSEPROGCOMPLETED_Pos (0UL)  /*!< AIBFUSEPROGCOMPLETED (Bit 0)                          */
30032 #define CRYPTO_AIBFUSEPROGCOMPLETED_AIBFUSEPROGCOMPLETED_Msk (0x1UL) /*!< AIBFUSEPROGCOMPLETED (Bitfield-Mask: 0x01)           */
30033 /* ====================================================  NVMDEBUGSTATUS  ===================================================== */
30034 #define CRYPTO_NVMDEBUGSTATUS_NVMSM_Pos   (1UL)                     /*!< NVMSM (Bit 1)                                         */
30035 #define CRYPTO_NVMDEBUGSTATUS_NVMSM_Msk   (0xeUL)                   /*!< NVMSM (Bitfield-Mask: 0x07)                           */
30036 /* ======================================================  LCSISVALID  ======================================================= */
30037 #define CRYPTO_LCSISVALID_LCSISVALIDREG_Pos (0UL)                   /*!< LCSISVALIDREG (Bit 0)                                 */
30038 #define CRYPTO_LCSISVALID_LCSISVALIDREG_Msk (0x1UL)                 /*!< LCSISVALIDREG (Bitfield-Mask: 0x01)                   */
30039 /* =======================================================  NVMISIDLE  ======================================================= */
30040 #define CRYPTO_NVMISIDLE_NVMISIDLEREG_Pos (0UL)                     /*!< NVMISIDLEREG (Bit 0)                                  */
30041 #define CRYPTO_NVMISIDLE_NVMISIDLEREG_Msk (0x1UL)                   /*!< NVMISIDLEREG (Bitfield-Mask: 0x01)                    */
30042 /* ========================================================  LCSREG  ========================================================= */
30043 #define CRYPTO_LCSREG_ERRORKCEICVZEROCNT_Pos (12UL)                 /*!< ERRORKCEICVZEROCNT (Bit 12)                           */
30044 #define CRYPTO_LCSREG_ERRORKCEICVZEROCNT_Msk (0x1000UL)             /*!< ERRORKCEICVZEROCNT (Bitfield-Mask: 0x01)              */
30045 #define CRYPTO_LCSREG_ERRORKPICVZEROCNT_Pos (11UL)                  /*!< ERRORKPICVZEROCNT (Bit 11)                            */
30046 #define CRYPTO_LCSREG_ERRORKPICVZEROCNT_Msk (0x800UL)               /*!< ERRORKPICVZEROCNT (Bitfield-Mask: 0x01)               */
30047 #define CRYPTO_LCSREG_ERRORKCEZEROCNT_Pos (10UL)                    /*!< ERRORKCEZEROCNT (Bit 10)                              */
30048 #define CRYPTO_LCSREG_ERRORKCEZEROCNT_Msk (0x400UL)                 /*!< ERRORKCEZEROCNT (Bitfield-Mask: 0x01)                 */
30049 #define CRYPTO_LCSREG_ERRORPROVZEROCNT_Pos (9UL)                    /*!< ERRORPROVZEROCNT (Bit 9)                              */
30050 #define CRYPTO_LCSREG_ERRORPROVZEROCNT_Msk (0x200UL)                /*!< ERRORPROVZEROCNT (Bitfield-Mask: 0x01)                */
30051 #define CRYPTO_LCSREG_ERRORKDRZEROCNT_Pos (8UL)                     /*!< ERRORKDRZEROCNT (Bit 8)                               */
30052 #define CRYPTO_LCSREG_ERRORKDRZEROCNT_Msk (0x100UL)                 /*!< ERRORKDRZEROCNT (Bitfield-Mask: 0x01)                 */
30053 #define CRYPTO_LCSREG_LCSREG_Pos          (0UL)                     /*!< LCSREG (Bit 0)                                        */
30054 #define CRYPTO_LCSREG_LCSREG_Msk          (0x7UL)                   /*!< LCSREG (Bitfield-Mask: 0x07)                          */
30055 /* ===================================================  HOSTSHADOWKDRREG  ==================================================== */
30056 #define CRYPTO_HOSTSHADOWKDRREG_HOSTSHADOWKDRREG_Pos (0UL)          /*!< HOSTSHADOWKDRREG (Bit 0)                              */
30057 #define CRYPTO_HOSTSHADOWKDRREG_HOSTSHADOWKDRREG_Msk (0x1UL)        /*!< HOSTSHADOWKDRREG (Bitfield-Mask: 0x01)                */
30058 /* ===================================================  HOSTSHADOWKCPREG  ==================================================== */
30059 #define CRYPTO_HOSTSHADOWKCPREG_HOSTSHADOWKCPREG_Pos (0UL)          /*!< HOSTSHADOWKCPREG (Bit 0)                              */
30060 #define CRYPTO_HOSTSHADOWKCPREG_HOSTSHADOWKCPREG_Msk (0x1UL)        /*!< HOSTSHADOWKCPREG (Bitfield-Mask: 0x01)                */
30061 /* ===================================================  HOSTSHADOWKCEREG  ==================================================== */
30062 #define CRYPTO_HOSTSHADOWKCEREG_HOSTSHADOWKCEREG_Pos (0UL)          /*!< HOSTSHADOWKCEREG (Bit 0)                              */
30063 #define CRYPTO_HOSTSHADOWKCEREG_HOSTSHADOWKCEREG_Msk (0x1UL)        /*!< HOSTSHADOWKCEREG (Bitfield-Mask: 0x01)                */
30064 /* ==================================================  HOSTSHADOWKPICVREG  =================================================== */
30065 #define CRYPTO_HOSTSHADOWKPICVREG_HOSTSHADOWKPICVREG_Pos (0UL)      /*!< HOSTSHADOWKPICVREG (Bit 0)                            */
30066 #define CRYPTO_HOSTSHADOWKPICVREG_HOSTSHADOWKPICVREG_Msk (0x1UL)    /*!< HOSTSHADOWKPICVREG (Bitfield-Mask: 0x01)              */
30067 /* ==================================================  HOSTSHADOWKCEICVREG  ================================================== */
30068 #define CRYPTO_HOSTSHADOWKCEICVREG_HOSTSHADOWKCEICVREG_Pos (0UL)    /*!< HOSTSHADOWKCEICVREG (Bit 0)                           */
30069 #define CRYPTO_HOSTSHADOWKCEICVREG_HOSTSHADOWKCEICVREG_Msk (0x1UL)  /*!< HOSTSHADOWKCEICVREG (Bitfield-Mask: 0x01)             */
30070 /* ====================================================  OTPADDRWIDTHDEF  ==================================================== */
30071 #define CRYPTO_OTPADDRWIDTHDEF_OTPADDRWIDTHDEF_Pos (0UL)            /*!< OTPADDRWIDTHDEF (Bit 0)                               */
30072 #define CRYPTO_OTPADDRWIDTHDEF_OTPADDRWIDTHDEF_Msk (0xfUL)          /*!< OTPADDRWIDTHDEF (Bitfield-Mask: 0x0f)                 */
30073 
30074 
30075 /* =========================================================================================================================== */
30076 /* ================                                            DC                                             ================ */
30077 /* =========================================================================================================================== */
30078 
30079 /* =========================================================  MODE  ========================================================== */
30080 #define DC_MODE_DC400ACT_Pos              (31UL)                    /*!< DC400ACT (Bit 31)                                     */
30081 #define DC_MODE_DC400ACT_Msk              (0x80000000UL)            /*!< DC400ACT (Bitfield-Mask: 0x01)                        */
30082 #define DC_MODE_CUSOREN_Pos               (30UL)                    /*!< CUSOREN (Bit 30)                                      */
30083 #define DC_MODE_CUSOREN_Msk               (0x40000000UL)            /*!< CUSOREN (Bitfield-Mask: 0x01)                         */
30084 #define DC_MODE_RSVD4_Pos                 (29UL)                    /*!< RSVD4 (Bit 29)                                        */
30085 #define DC_MODE_RSVD4_Msk                 (0x20000000UL)            /*!< RSVD4 (Bitfield-Mask: 0x01)                           */
30086 #define DC_MODE_VSYNCPOL_Pos              (28UL)                    /*!< VSYNCPOL (Bit 28)                                     */
30087 #define DC_MODE_VSYNCPOL_Msk              (0x10000000UL)            /*!< VSYNCPOL (Bitfield-Mask: 0x01)                        */
30088 #define DC_MODE_HSYNCPOL_Pos              (27UL)                    /*!< HSYNCPOL (Bit 27)                                     */
30089 #define DC_MODE_HSYNCPOL_Msk              (0x8000000UL)             /*!< HSYNCPOL (Bitfield-Mask: 0x01)                        */
30090 #define DC_MODE_DEPOL_Pos                 (26UL)                    /*!< DEPOL (Bit 26)                                        */
30091 #define DC_MODE_DEPOL_Msk                 (0x4000000UL)             /*!< DEPOL (Bitfield-Mask: 0x01)                           */
30092 #define DC_MODE_RSVD3_Pos                 (25UL)                    /*!< RSVD3 (Bit 25)                                        */
30093 #define DC_MODE_RSVD3_Msk                 (0x2000000UL)             /*!< RSVD3 (Bitfield-Mask: 0x01)                           */
30094 #define DC_MODE_DITHEREN_Pos              (24UL)                    /*!< DITHEREN (Bit 24)                                     */
30095 #define DC_MODE_DITHEREN_Msk              (0x1000000UL)             /*!< DITHEREN (Bitfield-Mask: 0x01)                        */
30096 #define DC_MODE_VSYNCEN_Pos               (23UL)                    /*!< VSYNCEN (Bit 23)                                      */
30097 #define DC_MODE_VSYNCEN_Msk               (0x800000UL)              /*!< VSYNCEN (Bitfield-Mask: 0x01)                         */
30098 #define DC_MODE_PIXCLKPOL_Pos             (22UL)                    /*!< PIXCLKPOL (Bit 22)                                    */
30099 #define DC_MODE_PIXCLKPOL_Msk             (0x400000UL)              /*!< PIXCLKPOL (Bitfield-Mask: 0x01)                       */
30100 #define DC_MODE_RSVD2_Pos                 (21UL)                    /*!< RSVD2 (Bit 21)                                        */
30101 #define DC_MODE_RSVD2_Msk                 (0x200000UL)              /*!< RSVD2 (Bitfield-Mask: 0x01)                           */
30102 #define DC_MODE_GAMARAMPEN_Pos            (20UL)                    /*!< GAMARAMPEN (Bit 20)                                   */
30103 #define DC_MODE_GAMARAMPEN_Msk            (0x100000UL)              /*!< GAMARAMPEN (Bitfield-Mask: 0x01)                      */
30104 #define DC_MODE_BLANKFRC_Pos              (19UL)                    /*!< BLANKFRC (Bit 19)                                     */
30105 #define DC_MODE_BLANKFRC_Msk              (0x80000UL)               /*!< BLANKFRC (Bitfield-Mask: 0x01)                        */
30106 #define DC_MODE_RSVD1_Pos                 (18UL)                    /*!< RSVD1 (Bit 18)                                        */
30107 #define DC_MODE_RSVD1_Msk                 (0x40000UL)               /*!< RSVD1 (Bitfield-Mask: 0x01)                           */
30108 #define DC_MODE_FRAMEUPDTEN_Pos           (17UL)                    /*!< FRAMEUPDTEN (Bit 17)                                  */
30109 #define DC_MODE_FRAMEUPDTEN_Msk           (0x20000UL)               /*!< FRAMEUPDTEN (Bitfield-Mask: 0x01)                     */
30110 #define DC_MODE_RSVD0_Pos                 (12UL)                    /*!< RSVD0 (Bit 12)                                        */
30111 #define DC_MODE_RSVD0_Msk                 (0x1f000UL)               /*!< RSVD0 (Bitfield-Mask: 0x1f)                           */
30112 #define DC_MODE_PLLCLKNDIV_Pos            (11UL)                    /*!< PLLCLKNDIV (Bit 11)                                   */
30113 #define DC_MODE_PLLCLKNDIV_Msk            (0x800UL)                 /*!< PLLCLKNDIV (Bitfield-Mask: 0x01)                      */
30114 #define DC_MODE_LVDSPADSEN_Pos            (10UL)                    /*!< LVDSPADSEN (Bit 10)                                   */
30115 #define DC_MODE_LVDSPADSEN_Msk            (0x400UL)                 /*!< LVDSPADSEN (Bitfield-Mask: 0x01)                      */
30116 #define DC_MODE_COLFMT_Pos                (9UL)                     /*!< COLFMT (Bit 9)                                        */
30117 #define DC_MODE_COLFMT_Msk                (0x200UL)                 /*!< COLFMT (Bitfield-Mask: 0x01)                          */
30118 #define DC_MODE_DISPFMT_Pos               (5UL)                     /*!< DISPFMT (Bit 5)                                       */
30119 #define DC_MODE_DISPFMT_Msk               (0x1e0UL)                 /*!< DISPFMT (Bitfield-Mask: 0x0f)                         */
30120 #define DC_MODE_DBITYPEBEN_Pos            (4UL)                     /*!< DBITYPEBEN (Bit 4)                                    */
30121 #define DC_MODE_DBITYPEBEN_Msk            (0x10UL)                  /*!< DBITYPEBEN (Bitfield-Mask: 0x01)                      */
30122 #define DC_MODE_YUYVEN_Pos                (3UL)                     /*!< YUYVEN (Bit 3)                                        */
30123 #define DC_MODE_YUYVEN_Msk                (0x8UL)                   /*!< YUYVEN (Bitfield-Mask: 0x01)                          */
30124 #define DC_MODE_LVDSINTEN_Pos             (2UL)                     /*!< LVDSINTEN (Bit 2)                                     */
30125 #define DC_MODE_LVDSINTEN_Msk             (0x4UL)                   /*!< LVDSINTEN (Bitfield-Mask: 0x01)                       */
30126 #define DC_MODE_DBLHORSCANEN_Pos          (1UL)                     /*!< DBLHORSCANEN (Bit 1)                                  */
30127 #define DC_MODE_DBLHORSCANEN_Msk          (0x2UL)                   /*!< DBLHORSCANEN (Bitfield-Mask: 0x01)                    */
30128 #define DC_MODE_TSTMODEN_Pos              (0UL)                     /*!< TSTMODEN (Bit 0)                                      */
30129 #define DC_MODE_TSTMODEN_Msk              (0x1UL)                   /*!< TSTMODEN (Bitfield-Mask: 0x01)                        */
30130 /* ========================================================  CLKCTRL  ======================================================== */
30131 #define DC_CLKCTRL_SECCLKDIV_Pos          (27UL)                    /*!< SECCLKDIV (Bit 27)                                    */
30132 #define DC_CLKCTRL_SECCLKDIV_Msk          (0xf8000000UL)            /*!< SECCLKDIV (Bitfield-Mask: 0x1f)                       */
30133 #define DC_CLKCTRL_LVDS_Pos               (24UL)                    /*!< LVDS (Bit 24)                                         */
30134 #define DC_CLKCTRL_LVDS_Msk               (0x7000000UL)             /*!< LVDS (Bitfield-Mask: 0x07)                            */
30135 #define DC_CLKCTRL_PLL_Pos                (16UL)                    /*!< PLL (Bit 16)                                          */
30136 #define DC_CLKCTRL_PLL_Msk                (0xff0000UL)              /*!< PLL (Bitfield-Mask: 0xff)                             */
30137 #define DC_CLKCTRL_RSVD1_Pos              (14UL)                    /*!< RSVD1 (Bit 14)                                        */
30138 #define DC_CLKCTRL_RSVD1_Msk              (0xc000UL)                /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
30139 #define DC_CLKCTRL_LINENUM_Pos            (8UL)                     /*!< LINENUM (Bit 8)                                       */
30140 #define DC_CLKCTRL_LINENUM_Msk            (0x3f00UL)                /*!< LINENUM (Bitfield-Mask: 0x3f)                         */
30141 #define DC_CLKCTRL_RSVD0_Pos              (6UL)                     /*!< RSVD0 (Bit 6)                                         */
30142 #define DC_CLKCTRL_RSVD0_Msk              (0xc0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x03)                           */
30143 #define DC_CLKCTRL_DIVIDEVALUE_Pos        (0UL)                     /*!< DIVIDEVALUE (Bit 0)                                   */
30144 #define DC_CLKCTRL_DIVIDEVALUE_Msk        (0x3fUL)                  /*!< DIVIDEVALUE (Bitfield-Mask: 0x3f)                     */
30145 /* ========================================================  BGCOLOR  ======================================================== */
30146 #define DC_BGCOLOR_REDCOLOR_Pos           (24UL)                    /*!< REDCOLOR (Bit 24)                                     */
30147 #define DC_BGCOLOR_REDCOLOR_Msk           (0xff000000UL)            /*!< REDCOLOR (Bitfield-Mask: 0xff)                        */
30148 #define DC_BGCOLOR_GREENCOLOR_Pos         (16UL)                    /*!< GREENCOLOR (Bit 16)                                   */
30149 #define DC_BGCOLOR_GREENCOLOR_Msk         (0xff0000UL)              /*!< GREENCOLOR (Bitfield-Mask: 0xff)                      */
30150 #define DC_BGCOLOR_BLUECOLOR_Pos          (8UL)                     /*!< BLUECOLOR (Bit 8)                                     */
30151 #define DC_BGCOLOR_BLUECOLOR_Msk          (0xff00UL)                /*!< BLUECOLOR (Bitfield-Mask: 0xff)                       */
30152 #define DC_BGCOLOR_ALPHACOLOR_Pos         (0UL)                     /*!< ALPHACOLOR (Bit 0)                                    */
30153 #define DC_BGCOLOR_ALPHACOLOR_Msk         (0xffUL)                  /*!< ALPHACOLOR (Bitfield-Mask: 0xff)                      */
30154 /* =========================================================  RESXY  ========================================================= */
30155 #define DC_RESXY_XRES_Pos                 (16UL)                    /*!< XRES (Bit 16)                                         */
30156 #define DC_RESXY_XRES_Msk                 (0xffff0000UL)            /*!< XRES (Bitfield-Mask: 0xffff)                          */
30157 #define DC_RESXY_YRES_Pos                 (0UL)                     /*!< YRES (Bit 0)                                          */
30158 #define DC_RESXY_YRES_Msk                 (0xffffUL)                /*!< YRES (Bitfield-Mask: 0xffff)                          */
30159 /* =====================================================  FRONTPORCHXY  ====================================================== */
30160 #define DC_FRONTPORCHXY_FPCLKCYCLES_Pos   (16UL)                    /*!< FPCLKCYCLES (Bit 16)                                  */
30161 #define DC_FRONTPORCHXY_FPCLKCYCLES_Msk   (0xffff0000UL)            /*!< FPCLKCYCLES (Bitfield-Mask: 0xffff)                   */
30162 #define DC_FRONTPORCHXY_FLINES_Pos        (0UL)                     /*!< FLINES (Bit 0)                                        */
30163 #define DC_FRONTPORCHXY_FLINES_Msk        (0xffffUL)                /*!< FLINES (Bitfield-Mask: 0xffff)                        */
30164 /* ======================================================  BLANKINGXY  ======================================================= */
30165 #define DC_BLANKINGXY_HSYNCPULSE_Pos      (16UL)                    /*!< HSYNCPULSE (Bit 16)                                   */
30166 #define DC_BLANKINGXY_HSYNCPULSE_Msk      (0xffff0000UL)            /*!< HSYNCPULSE (Bitfield-Mask: 0xffff)                    */
30167 #define DC_BLANKINGXY_VSYNCLINES_Pos      (0UL)                     /*!< VSYNCLINES (Bit 0)                                    */
30168 #define DC_BLANKINGXY_VSYNCLINES_Msk      (0xffffUL)                /*!< VSYNCLINES (Bitfield-Mask: 0xffff)                    */
30169 /* ======================================================  BACKPORCHXY  ====================================================== */
30170 #define DC_BACKPORCHXY_BPCLKCYCLES_Pos    (16UL)                    /*!< BPCLKCYCLES (Bit 16)                                  */
30171 #define DC_BACKPORCHXY_BPCLKCYCLES_Msk    (0xffff0000UL)            /*!< BPCLKCYCLES (Bitfield-Mask: 0xffff)                   */
30172 #define DC_BACKPORCHXY_BLINES_Pos         (0UL)                     /*!< BLINES (Bit 0)                                        */
30173 #define DC_BACKPORCHXY_BLINES_Msk         (0xffffUL)                /*!< BLINES (Bitfield-Mask: 0xffff)                        */
30174 /* =======================================================  CURSORXY  ======================================================== */
30175 #define DC_CURSORXY_CURSORX_Pos           (16UL)                    /*!< CURSORX (Bit 16)                                      */
30176 #define DC_CURSORXY_CURSORX_Msk           (0xffff0000UL)            /*!< CURSORX (Bitfield-Mask: 0xffff)                       */
30177 #define DC_CURSORXY_CURSORY_Pos           (0UL)                     /*!< CURSORY (Bit 0)                                       */
30178 #define DC_CURSORXY_CURSORY_Msk           (0xffffUL)                /*!< CURSORY (Bitfield-Mask: 0xffff)                       */
30179 /* ========================================================  DBICFG  ========================================================= */
30180 #define DC_DBICFG_DBIINTACT_Pos           (31UL)                    /*!< DBIINTACT (Bit 31)                                    */
30181 #define DC_DBICFG_DBIINTACT_Msk           (0x80000000UL)            /*!< DBIINTACT (Bitfield-Mask: 0x01)                       */
30182 #define DC_DBICFG_CSXCFG_Pos              (30UL)                    /*!< CSXCFG (Bit 30)                                       */
30183 #define DC_DBICFG_CSXCFG_Msk              (0x40000000UL)            /*!< CSXCFG (Bitfield-Mask: 0x01)                          */
30184 #define DC_DBICFG_CSXSET_Pos              (29UL)                    /*!< CSXSET (Bit 29)                                       */
30185 #define DC_DBICFG_CSXSET_Msk              (0x20000000UL)            /*!< CSXSET (Bitfield-Mask: 0x01)                          */
30186 #define DC_DBICFG_DBIBTEDIS_Pos           (28UL)                    /*!< DBIBTEDIS (Bit 28)                                    */
30187 #define DC_DBICFG_DBIBTEDIS_Msk           (0x10000000UL)            /*!< DBIBTEDIS (Bitfield-Mask: 0x01)                       */
30188 #define DC_DBICFG_RSVD4_Pos               (26UL)                    /*!< RSVD4 (Bit 26)                                        */
30189 #define DC_DBICFG_RSVD4_Msk               (0xc000000UL)             /*!< RSVD4 (Bitfield-Mask: 0x03)                           */
30190 #define DC_DBICFG_RESXLOW_Pos             (25UL)                    /*!< RESXLOW (Bit 25)                                      */
30191 #define DC_DBICFG_RESXLOW_Msk             (0x2000000UL)             /*!< RESXLOW (Bitfield-Mask: 0x01)                         */
30192 #define DC_DBICFG_RSVD3_Pos               (24UL)                    /*!< RSVD3 (Bit 24)                                        */
30193 #define DC_DBICFG_RSVD3_Msk               (0x1000000UL)             /*!< RSVD3 (Bitfield-Mask: 0x01)                           */
30194 #define DC_DBICFG_SPI3_Pos                (23UL)                    /*!< SPI3 (Bit 23)                                         */
30195 #define DC_DBICFG_SPI3_Msk                (0x800000UL)              /*!< SPI3 (Bitfield-Mask: 0x01)                            */
30196 #define DC_DBICFG_SPI4_Pos                (22UL)                    /*!< SPI4 (Bit 22)                                         */
30197 #define DC_DBICFG_SPI4_Msk                (0x400000UL)              /*!< SPI4 (Bitfield-Mask: 0x01)                            */
30198 #define DC_DBICFG_RSVD2_Pos               (18UL)                    /*!< RSVD2 (Bit 18)                                        */
30199 #define DC_DBICFG_RSVD2_Msk               (0x3c0000UL)              /*!< RSVD2 (Bitfield-Mask: 0x0f)                           */
30200 #define DC_DBICFG_BINDCMDS_Pos            (17UL)                    /*!< BINDCMDS (Bit 17)                                     */
30201 #define DC_DBICFG_BINDCMDS_Msk            (0x20000UL)               /*!< BINDCMDS (Bitfield-Mask: 0x01)                        */
30202 #define DC_DBICFG_INVHRZLINE_Pos          (16UL)                    /*!< INVHRZLINE (Bit 16)                                   */
30203 #define DC_DBICFG_INVHRZLINE_Msk          (0x10000UL)               /*!< INVHRZLINE (Bitfield-Mask: 0x01)                      */
30204 #define DC_DBICFG_RSVD1_Pos               (12UL)                    /*!< RSVD1 (Bit 12)                                        */
30205 #define DC_DBICFG_RSVD1_Msk               (0xf000UL)                /*!< RSVD1 (Bitfield-Mask: 0x0f)                           */
30206 #define DC_DBICFG_BACKPRESSUREEN_Pos      (11UL)                    /*!< BACKPRESSUREEN (Bit 11)                               */
30207 #define DC_DBICFG_BACKPRESSUREEN_Msk      (0x800UL)                 /*!< BACKPRESSUREEN (Bitfield-Mask: 0x01)                  */
30208 #define DC_DBICFG_RSVD0_Pos               (8UL)                     /*!< RSVD0 (Bit 8)                                         */
30209 #define DC_DBICFG_RSVD0_Msk               (0x700UL)                 /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
30210 #define DC_DBICFG_TYPEBWIDTH_Pos          (6UL)                     /*!< TYPEBWIDTH (Bit 6)                                    */
30211 #define DC_DBICFG_TYPEBWIDTH_Msk          (0xc0UL)                  /*!< TYPEBWIDTH (Bitfield-Mask: 0x03)                      */
30212 #define DC_DBICFG_DATAWDORDER_Pos         (3UL)                     /*!< DATAWDORDER (Bit 3)                                   */
30213 #define DC_DBICFG_DATAWDORDER_Msk         (0x38UL)                  /*!< DATAWDORDER (Bitfield-Mask: 0x07)                     */
30214 #define DC_DBICFG_DBICOLORFMT_Pos         (0UL)                     /*!< DBICOLORFMT (Bit 0)                                   */
30215 #define DC_DBICFG_DBICOLORFMT_Msk         (0x7UL)                   /*!< DBICOLORFMT (Bitfield-Mask: 0x07)                     */
30216 /* ========================================================  DCGPIO  ========================================================= */
30217 #define DC_DCGPIO_CGBYPASS_Pos            (22UL)                    /*!< CGBYPASS (Bit 22)                                     */
30218 #define DC_DCGPIO_CGBYPASS_Msk            (0xffc00000UL)            /*!< CGBYPASS (Bitfield-Mask: 0x3ff)                       */
30219 #define DC_DCGPIO_RSVD1_Pos               (9UL)                     /*!< RSVD1 (Bit 9)                                         */
30220 #define DC_DCGPIO_RSVD1_Msk               (0x3ffe00UL)              /*!< RSVD1 (Bitfield-Mask: 0x1fff)                         */
30221 #define DC_DCGPIO_ADVANCEANYWAY_Pos       (7UL)                     /*!< ADVANCEANYWAY (Bit 7)                                 */
30222 #define DC_DCGPIO_ADVANCEANYWAY_Msk       (0x180UL)                 /*!< ADVANCEANYWAY (Bitfield-Mask: 0x03)                   */
30223 #define DC_DCGPIO_RSVD0_Pos               (2UL)                     /*!< RSVD0 (Bit 2)                                         */
30224 #define DC_DCGPIO_RSVD0_Msk               (0x7cUL)                  /*!< RSVD0 (Bitfield-Mask: 0x1f)                           */
30225 #define DC_DCGPIO_RWPINS_Pos              (0UL)                     /*!< RWPINS (Bit 0)                                        */
30226 #define DC_DCGPIO_RWPINS_Msk              (0x3UL)                   /*!< RWPINS (Bitfield-Mask: 0x03)                          */
30227 /* ======================================================  LAYER0MODE  ======================================================= */
30228 #define DC_LAYER0MODE_LAYER0EN_Pos        (31UL)                    /*!< LAYER0EN (Bit 31)                                     */
30229 #define DC_LAYER0MODE_LAYER0EN_Msk        (0x80000000UL)            /*!< LAYER0EN (Bitfield-Mask: 0x01)                        */
30230 #define DC_LAYER0MODE_LAYER0FORCE_Pos     (30UL)                    /*!< LAYER0FORCE (Bit 30)                                  */
30231 #define DC_LAYER0MODE_LAYER0FORCE_Msk     (0x40000000UL)            /*!< LAYER0FORCE (Bitfield-Mask: 0x01)                     */
30232 #define DC_LAYER0MODE_LAYER0BFILTER_Pos   (29UL)                    /*!< LAYER0BFILTER (Bit 29)                                */
30233 #define DC_LAYER0MODE_LAYER0BFILTER_Msk   (0x20000000UL)            /*!< LAYER0BFILTER (Bitfield-Mask: 0x01)                   */
30234 #define DC_LAYER0MODE_LAYER0PREMULT_Pos   (28UL)                    /*!< LAYER0PREMULT (Bit 28)                                */
30235 #define DC_LAYER0MODE_LAYER0PREMULT_Msk   (0x10000000UL)            /*!< LAYER0PREMULT (Bitfield-Mask: 0x01)                   */
30236 #define DC_LAYER0MODE_LAYER0HLOCK_Pos     (27UL)                    /*!< LAYER0HLOCK (Bit 27)                                  */
30237 #define DC_LAYER0MODE_LAYER0HLOCK_Msk     (0x8000000UL)             /*!< LAYER0HLOCK (Bitfield-Mask: 0x01)                     */
30238 #define DC_LAYER0MODE_LAYER0GAMMA_Pos     (26UL)                    /*!< LAYER0GAMMA (Bit 26)                                  */
30239 #define DC_LAYER0MODE_LAYER0GAMMA_Msk     (0x4000000UL)             /*!< LAYER0GAMMA (Bitfield-Mask: 0x01)                     */
30240 #define DC_LAYER0MODE_RSVD1_Pos           (24UL)                    /*!< RSVD1 (Bit 24)                                        */
30241 #define DC_LAYER0MODE_RSVD1_Msk           (0x3000000UL)             /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
30242 #define DC_LAYER0MODE_LAYER0ALPHA_Pos     (16UL)                    /*!< LAYER0ALPHA (Bit 16)                                  */
30243 #define DC_LAYER0MODE_LAYER0ALPHA_Msk     (0xff0000UL)              /*!< LAYER0ALPHA (Bitfield-Mask: 0xff)                     */
30244 #define DC_LAYER0MODE_LAYER0DBLEND_Pos    (12UL)                    /*!< LAYER0DBLEND (Bit 12)                                 */
30245 #define DC_LAYER0MODE_LAYER0DBLEND_Msk    (0xf000UL)                /*!< LAYER0DBLEND (Bitfield-Mask: 0x0f)                    */
30246 #define DC_LAYER0MODE_LAYER0SBLEND_Pos    (8UL)                     /*!< LAYER0SBLEND (Bit 8)                                  */
30247 #define DC_LAYER0MODE_LAYER0SBLEND_Msk    (0xf00UL)                 /*!< LAYER0SBLEND (Bitfield-Mask: 0x0f)                    */
30248 #define DC_LAYER0MODE_RSVD0_Pos           (5UL)                     /*!< RSVD0 (Bit 5)                                         */
30249 #define DC_LAYER0MODE_RSVD0_Msk           (0xe0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
30250 #define DC_LAYER0MODE_LAYER0COLMODE_Pos   (0UL)                     /*!< LAYER0COLMODE (Bit 0)                                 */
30251 #define DC_LAYER0MODE_LAYER0COLMODE_Msk   (0x1fUL)                  /*!< LAYER0COLMODE (Bitfield-Mask: 0x1f)                   */
30252 /* =====================================================  LAYER0STARTXY  ===================================================== */
30253 #define DC_LAYER0STARTXY_LAYER0XOFF_Pos   (16UL)                    /*!< LAYER0XOFF (Bit 16)                                   */
30254 #define DC_LAYER0STARTXY_LAYER0XOFF_Msk   (0xffff0000UL)            /*!< LAYER0XOFF (Bitfield-Mask: 0xffff)                    */
30255 #define DC_LAYER0STARTXY_LAYER0YOFF_Pos   (0UL)                     /*!< LAYER0YOFF (Bit 0)                                    */
30256 #define DC_LAYER0STARTXY_LAYER0YOFF_Msk   (0xffffUL)                /*!< LAYER0YOFF (Bitfield-Mask: 0xffff)                    */
30257 /* =====================================================  LAYER0SIZEXY  ====================================================== */
30258 #define DC_LAYER0SIZEXY_LAYER0PIXSZEX_Pos (16UL)                    /*!< LAYER0PIXSZEX (Bit 16)                                */
30259 #define DC_LAYER0SIZEXY_LAYER0PIXSZEX_Msk (0xffff0000UL)            /*!< LAYER0PIXSZEX (Bitfield-Mask: 0xffff)                 */
30260 #define DC_LAYER0SIZEXY_LAYER0PIXSZEY_Pos (0UL)                     /*!< LAYER0PIXSZEY (Bit 0)                                 */
30261 #define DC_LAYER0SIZEXY_LAYER0PIXSZEY_Msk (0xffffUL)                /*!< LAYER0PIXSZEY (Bitfield-Mask: 0xffff)                 */
30262 /* ======================================================  LAYER0ADDR  ======================================================= */
30263 #define DC_LAYER0ADDR_LAYER0STARTADDRFBUF_Pos (0UL)                 /*!< LAYER0STARTADDRFBUF (Bit 0)                           */
30264 #define DC_LAYER0ADDR_LAYER0STARTADDRFBUF_Msk (0xffffffffUL)        /*!< LAYER0STARTADDRFBUF (Bitfield-Mask: 0xffffffff)       */
30265 /* =====================================================  LAYER0STRIDE  ====================================================== */
30266 #define DC_LAYER0STRIDE_RSVD_Pos          (21UL)                    /*!< RSVD (Bit 21)                                         */
30267 #define DC_LAYER0STRIDE_RSVD_Msk          (0xffe00000UL)            /*!< RSVD (Bitfield-Mask: 0x7ff)                           */
30268 #define DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_Pos (19UL)                /*!< LAYER0AXIFIFOTHLD (Bit 19)                            */
30269 #define DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_Msk (0x180000UL)          /*!< LAYER0AXIFIFOTHLD (Bitfield-Mask: 0x03)               */
30270 #define DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_Pos (16UL)               /*!< LAYER0AXIBURSTBITS (Bit 16)                           */
30271 #define DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_Msk (0x70000UL)          /*!< LAYER0AXIBURSTBITS (Bitfield-Mask: 0x07)              */
30272 #define DC_LAYER0STRIDE_LAYER0STRIDEDIST_Pos (0UL)                  /*!< LAYER0STRIDEDIST (Bit 0)                              */
30273 #define DC_LAYER0STRIDE_LAYER0STRIDEDIST_Msk (0xffffUL)             /*!< LAYER0STRIDEDIST (Bitfield-Mask: 0xffff)              */
30274 /* ======================================================  LAYER0RESXY  ====================================================== */
30275 #define DC_LAYER0RESXY_LAYER0PIXRESX_Pos  (16UL)                    /*!< LAYER0PIXRESX (Bit 16)                                */
30276 #define DC_LAYER0RESXY_LAYER0PIXRESX_Msk  (0xffff0000UL)            /*!< LAYER0PIXRESX (Bitfield-Mask: 0xffff)                 */
30277 #define DC_LAYER0RESXY_LAYER0PIXRESY_Pos  (0UL)                     /*!< LAYER0PIXRESY (Bit 0)                                 */
30278 #define DC_LAYER0RESXY_LAYER0PIXRESY_Msk  (0xffffUL)                /*!< LAYER0PIXRESY (Bitfield-Mask: 0xffff)                 */
30279 /* =====================================================  LAYER0SCALEX  ====================================================== */
30280 #define DC_LAYER0SCALEX_LAYER0XFACTOR_Pos (0UL)                     /*!< LAYER0XFACTOR (Bit 0)                                 */
30281 #define DC_LAYER0SCALEX_LAYER0XFACTOR_Msk (0xffffffffUL)            /*!< LAYER0XFACTOR (Bitfield-Mask: 0xffffffff)             */
30282 /* =====================================================  LAYER0SCALEY  ====================================================== */
30283 #define DC_LAYER0SCALEY_LAYER0YFACTOR_Pos (0UL)                     /*!< LAYER0YFACTOR (Bit 0)                                 */
30284 #define DC_LAYER0SCALEY_LAYER0YFACTOR_Msk (0xffffffffUL)            /*!< LAYER0YFACTOR (Bitfield-Mask: 0xffffffff)             */
30285 /* ======================================================  LAYER1MODE  ======================================================= */
30286 #define DC_LAYER1MODE_LAYER1EN_Pos        (31UL)                    /*!< LAYER1EN (Bit 31)                                     */
30287 #define DC_LAYER1MODE_LAYER1EN_Msk        (0x80000000UL)            /*!< LAYER1EN (Bitfield-Mask: 0x01)                        */
30288 #define DC_LAYER1MODE_LAYER1FORCE_Pos     (30UL)                    /*!< LAYER1FORCE (Bit 30)                                  */
30289 #define DC_LAYER1MODE_LAYER1FORCE_Msk     (0x40000000UL)            /*!< LAYER1FORCE (Bitfield-Mask: 0x01)                     */
30290 #define DC_LAYER1MODE_LAYER1BFILTER_Pos   (29UL)                    /*!< LAYER1BFILTER (Bit 29)                                */
30291 #define DC_LAYER1MODE_LAYER1BFILTER_Msk   (0x20000000UL)            /*!< LAYER1BFILTER (Bitfield-Mask: 0x01)                   */
30292 #define DC_LAYER1MODE_LAYER1PREMULT_Pos   (28UL)                    /*!< LAYER1PREMULT (Bit 28)                                */
30293 #define DC_LAYER1MODE_LAYER1PREMULT_Msk   (0x10000000UL)            /*!< LAYER1PREMULT (Bitfield-Mask: 0x01)                   */
30294 #define DC_LAYER1MODE_LAYER1HLOCK_Pos     (27UL)                    /*!< LAYER1HLOCK (Bit 27)                                  */
30295 #define DC_LAYER1MODE_LAYER1HLOCK_Msk     (0x8000000UL)             /*!< LAYER1HLOCK (Bitfield-Mask: 0x01)                     */
30296 #define DC_LAYER1MODE_LAYER1GAMMA_Pos     (26UL)                    /*!< LAYER1GAMMA (Bit 26)                                  */
30297 #define DC_LAYER1MODE_LAYER1GAMMA_Msk     (0x4000000UL)             /*!< LAYER1GAMMA (Bitfield-Mask: 0x01)                     */
30298 #define DC_LAYER1MODE_RSVD1_Pos           (24UL)                    /*!< RSVD1 (Bit 24)                                        */
30299 #define DC_LAYER1MODE_RSVD1_Msk           (0x3000000UL)             /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
30300 #define DC_LAYER1MODE_LAYER1ALPHA_Pos     (16UL)                    /*!< LAYER1ALPHA (Bit 16)                                  */
30301 #define DC_LAYER1MODE_LAYER1ALPHA_Msk     (0xff0000UL)              /*!< LAYER1ALPHA (Bitfield-Mask: 0xff)                     */
30302 #define DC_LAYER1MODE_LAYER1DBLEND_Pos    (12UL)                    /*!< LAYER1DBLEND (Bit 12)                                 */
30303 #define DC_LAYER1MODE_LAYER1DBLEND_Msk    (0xf000UL)                /*!< LAYER1DBLEND (Bitfield-Mask: 0x0f)                    */
30304 #define DC_LAYER1MODE_LAYER1SBLEND_Pos    (8UL)                     /*!< LAYER1SBLEND (Bit 8)                                  */
30305 #define DC_LAYER1MODE_LAYER1SBLEND_Msk    (0xf00UL)                 /*!< LAYER1SBLEND (Bitfield-Mask: 0x0f)                    */
30306 #define DC_LAYER1MODE_RSVD0_Pos           (5UL)                     /*!< RSVD0 (Bit 5)                                         */
30307 #define DC_LAYER1MODE_RSVD0_Msk           (0xe0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
30308 #define DC_LAYER1MODE_LAYER1COLORMODE_Pos (0UL)                     /*!< LAYER1COLORMODE (Bit 0)                               */
30309 #define DC_LAYER1MODE_LAYER1COLORMODE_Msk (0x1fUL)                  /*!< LAYER1COLORMODE (Bitfield-Mask: 0x1f)                 */
30310 /* =====================================================  LAYER1STARTXY  ===================================================== */
30311 #define DC_LAYER1STARTXY_LAYER1XOFF_Pos   (16UL)                    /*!< LAYER1XOFF (Bit 16)                                   */
30312 #define DC_LAYER1STARTXY_LAYER1XOFF_Msk   (0xffff0000UL)            /*!< LAYER1XOFF (Bitfield-Mask: 0xffff)                    */
30313 #define DC_LAYER1STARTXY_LAYER1YOFF_Pos   (0UL)                     /*!< LAYER1YOFF (Bit 0)                                    */
30314 #define DC_LAYER1STARTXY_LAYER1YOFF_Msk   (0xffffUL)                /*!< LAYER1YOFF (Bitfield-Mask: 0xffff)                    */
30315 /* =====================================================  LAYER1SIZEXY  ====================================================== */
30316 #define DC_LAYER1SIZEXY_LAYER1PIXSZEX_Pos (16UL)                    /*!< LAYER1PIXSZEX (Bit 16)                                */
30317 #define DC_LAYER1SIZEXY_LAYER1PIXSZEX_Msk (0xffff0000UL)            /*!< LAYER1PIXSZEX (Bitfield-Mask: 0xffff)                 */
30318 #define DC_LAYER1SIZEXY_LAYER1PIXSZEY_Pos (0UL)                     /*!< LAYER1PIXSZEY (Bit 0)                                 */
30319 #define DC_LAYER1SIZEXY_LAYER1PIXSZEY_Msk (0xffffUL)                /*!< LAYER1PIXSZEY (Bitfield-Mask: 0xffff)                 */
30320 /* ======================================================  LAYER1ADDR  ======================================================= */
30321 #define DC_LAYER1ADDR_LAYER1STARTADDRFBUF_Pos (0UL)                 /*!< LAYER1STARTADDRFBUF (Bit 0)                           */
30322 #define DC_LAYER1ADDR_LAYER1STARTADDRFBUF_Msk (0xffffffffUL)        /*!< LAYER1STARTADDRFBUF (Bitfield-Mask: 0xffffffff)       */
30323 /* =====================================================  LAYER1STRIDE  ====================================================== */
30324 #define DC_LAYER1STRIDE_RSVD_Pos          (21UL)                    /*!< RSVD (Bit 21)                                         */
30325 #define DC_LAYER1STRIDE_RSVD_Msk          (0xffe00000UL)            /*!< RSVD (Bitfield-Mask: 0x7ff)                           */
30326 #define DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_Pos (19UL)                /*!< LAYER1AXIFIFOTHLD (Bit 19)                            */
30327 #define DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_Msk (0x180000UL)          /*!< LAYER1AXIFIFOTHLD (Bitfield-Mask: 0x03)               */
30328 #define DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_Pos (16UL)               /*!< LAYER1AXIBURSTBITS (Bit 16)                           */
30329 #define DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_Msk (0x70000UL)          /*!< LAYER1AXIBURSTBITS (Bitfield-Mask: 0x07)              */
30330 #define DC_LAYER1STRIDE_LAYER1STRIDEDIST_Pos (0UL)                  /*!< LAYER1STRIDEDIST (Bit 0)                              */
30331 #define DC_LAYER1STRIDE_LAYER1STRIDEDIST_Msk (0xffffUL)             /*!< LAYER1STRIDEDIST (Bitfield-Mask: 0xffff)              */
30332 /* ======================================================  LAYER1RESXY  ====================================================== */
30333 #define DC_LAYER1RESXY_LAYER1PIXRESX_Pos  (16UL)                    /*!< LAYER1PIXRESX (Bit 16)                                */
30334 #define DC_LAYER1RESXY_LAYER1PIXRESX_Msk  (0xffff0000UL)            /*!< LAYER1PIXRESX (Bitfield-Mask: 0xffff)                 */
30335 #define DC_LAYER1RESXY_LAYER1PIXRESY_Pos  (0UL)                     /*!< LAYER1PIXRESY (Bit 0)                                 */
30336 #define DC_LAYER1RESXY_LAYER1PIXRESY_Msk  (0xffffUL)                /*!< LAYER1PIXRESY (Bitfield-Mask: 0xffff)                 */
30337 /* =====================================================  LAYER1SCALEX  ====================================================== */
30338 #define DC_LAYER1SCALEX_LAYER1XFACTOR_Pos (0UL)                     /*!< LAYER1XFACTOR (Bit 0)                                 */
30339 #define DC_LAYER1SCALEX_LAYER1XFACTOR_Msk (0xffffffffUL)            /*!< LAYER1XFACTOR (Bitfield-Mask: 0xffffffff)             */
30340 /* =====================================================  LAYER1SCALEY  ====================================================== */
30341 #define DC_LAYER1SCALEY_LAYER1YFACTOR_Pos (0UL)                     /*!< LAYER1YFACTOR (Bit 0)                                 */
30342 #define DC_LAYER1SCALEY_LAYER1YFACTOR_Msk (0xffffffffUL)            /*!< LAYER1YFACTOR (Bitfield-Mask: 0xffffffff)             */
30343 /* ======================================================  LAYER2MODE  ======================================================= */
30344 #define DC_LAYER2MODE_LAYER2EN_Pos        (31UL)                    /*!< LAYER2EN (Bit 31)                                     */
30345 #define DC_LAYER2MODE_LAYER2EN_Msk        (0x80000000UL)            /*!< LAYER2EN (Bitfield-Mask: 0x01)                        */
30346 #define DC_LAYER2MODE_LAYER2FORCE_Pos     (30UL)                    /*!< LAYER2FORCE (Bit 30)                                  */
30347 #define DC_LAYER2MODE_LAYER2FORCE_Msk     (0x40000000UL)            /*!< LAYER2FORCE (Bitfield-Mask: 0x01)                     */
30348 #define DC_LAYER2MODE_LAYER2BFILTER_Pos   (29UL)                    /*!< LAYER2BFILTER (Bit 29)                                */
30349 #define DC_LAYER2MODE_LAYER2BFILTER_Msk   (0x20000000UL)            /*!< LAYER2BFILTER (Bitfield-Mask: 0x01)                   */
30350 #define DC_LAYER2MODE_LAYER2PREMULT_Pos   (28UL)                    /*!< LAYER2PREMULT (Bit 28)                                */
30351 #define DC_LAYER2MODE_LAYER2PREMULT_Msk   (0x10000000UL)            /*!< LAYER2PREMULT (Bitfield-Mask: 0x01)                   */
30352 #define DC_LAYER2MODE_LAYER2HLOCK_Pos     (27UL)                    /*!< LAYER2HLOCK (Bit 27)                                  */
30353 #define DC_LAYER2MODE_LAYER2HLOCK_Msk     (0x8000000UL)             /*!< LAYER2HLOCK (Bitfield-Mask: 0x01)                     */
30354 #define DC_LAYER2MODE_LAYER2GAMMA_Pos     (26UL)                    /*!< LAYER2GAMMA (Bit 26)                                  */
30355 #define DC_LAYER2MODE_LAYER2GAMMA_Msk     (0x4000000UL)             /*!< LAYER2GAMMA (Bitfield-Mask: 0x01)                     */
30356 #define DC_LAYER2MODE_RSVD1_Pos           (24UL)                    /*!< RSVD1 (Bit 24)                                        */
30357 #define DC_LAYER2MODE_RSVD1_Msk           (0x3000000UL)             /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
30358 #define DC_LAYER2MODE_LAYER2ALPHA_Pos     (16UL)                    /*!< LAYER2ALPHA (Bit 16)                                  */
30359 #define DC_LAYER2MODE_LAYER2ALPHA_Msk     (0xff0000UL)              /*!< LAYER2ALPHA (Bitfield-Mask: 0xff)                     */
30360 #define DC_LAYER2MODE_LAYER2DBLEND_Pos    (12UL)                    /*!< LAYER2DBLEND (Bit 12)                                 */
30361 #define DC_LAYER2MODE_LAYER2DBLEND_Msk    (0xf000UL)                /*!< LAYER2DBLEND (Bitfield-Mask: 0x0f)                    */
30362 #define DC_LAYER2MODE_LAYER2SBLEND_Pos    (8UL)                     /*!< LAYER2SBLEND (Bit 8)                                  */
30363 #define DC_LAYER2MODE_LAYER2SBLEND_Msk    (0xf00UL)                 /*!< LAYER2SBLEND (Bitfield-Mask: 0x0f)                    */
30364 #define DC_LAYER2MODE_RSVD0_Pos           (5UL)                     /*!< RSVD0 (Bit 5)                                         */
30365 #define DC_LAYER2MODE_RSVD0_Msk           (0xe0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
30366 #define DC_LAYER2MODE_LAYER2COLORMODE_Pos (0UL)                     /*!< LAYER2COLORMODE (Bit 0)                               */
30367 #define DC_LAYER2MODE_LAYER2COLORMODE_Msk (0x1fUL)                  /*!< LAYER2COLORMODE (Bitfield-Mask: 0x1f)                 */
30368 /* =====================================================  LAYER2STARTXY  ===================================================== */
30369 #define DC_LAYER2STARTXY_LAYER2XOFF_Pos   (16UL)                    /*!< LAYER2XOFF (Bit 16)                                   */
30370 #define DC_LAYER2STARTXY_LAYER2XOFF_Msk   (0xffff0000UL)            /*!< LAYER2XOFF (Bitfield-Mask: 0xffff)                    */
30371 #define DC_LAYER2STARTXY_LAYER2YOFF_Pos   (0UL)                     /*!< LAYER2YOFF (Bit 0)                                    */
30372 #define DC_LAYER2STARTXY_LAYER2YOFF_Msk   (0xffffUL)                /*!< LAYER2YOFF (Bitfield-Mask: 0xffff)                    */
30373 /* =====================================================  LAYER2SIZEXY  ====================================================== */
30374 #define DC_LAYER2SIZEXY_LAYER2PIXSZEX_Pos (16UL)                    /*!< LAYER2PIXSZEX (Bit 16)                                */
30375 #define DC_LAYER2SIZEXY_LAYER2PIXSZEX_Msk (0xffff0000UL)            /*!< LAYER2PIXSZEX (Bitfield-Mask: 0xffff)                 */
30376 #define DC_LAYER2SIZEXY_LAYER2PIXSZEY_Pos (0UL)                     /*!< LAYER2PIXSZEY (Bit 0)                                 */
30377 #define DC_LAYER2SIZEXY_LAYER2PIXSZEY_Msk (0xffffUL)                /*!< LAYER2PIXSZEY (Bitfield-Mask: 0xffff)                 */
30378 /* ======================================================  LAYER2ADDR  ======================================================= */
30379 #define DC_LAYER2ADDR_LAYER2STARTADDRFBUF_Pos (0UL)                 /*!< LAYER2STARTADDRFBUF (Bit 0)                           */
30380 #define DC_LAYER2ADDR_LAYER2STARTADDRFBUF_Msk (0xffffffffUL)        /*!< LAYER2STARTADDRFBUF (Bitfield-Mask: 0xffffffff)       */
30381 /* =====================================================  LAYER2STRIDE  ====================================================== */
30382 #define DC_LAYER2STRIDE_RSVD_Pos          (21UL)                    /*!< RSVD (Bit 21)                                         */
30383 #define DC_LAYER2STRIDE_RSVD_Msk          (0xffe00000UL)            /*!< RSVD (Bitfield-Mask: 0x7ff)                           */
30384 #define DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_Pos (19UL)                /*!< LAYER2AXIFIFOTHLD (Bit 19)                            */
30385 #define DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_Msk (0x180000UL)          /*!< LAYER2AXIFIFOTHLD (Bitfield-Mask: 0x03)               */
30386 #define DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_Pos (16UL)               /*!< LAYER2AXIBURSTBITS (Bit 16)                           */
30387 #define DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_Msk (0x70000UL)          /*!< LAYER2AXIBURSTBITS (Bitfield-Mask: 0x07)              */
30388 #define DC_LAYER2STRIDE_LAYER2STRIDEDIST_Pos (0UL)                  /*!< LAYER2STRIDEDIST (Bit 0)                              */
30389 #define DC_LAYER2STRIDE_LAYER2STRIDEDIST_Msk (0xffffUL)             /*!< LAYER2STRIDEDIST (Bitfield-Mask: 0xffff)              */
30390 /* ======================================================  LAYER2RESXY  ====================================================== */
30391 #define DC_LAYER2RESXY_LAYER2PIXRESX_Pos  (16UL)                    /*!< LAYER2PIXRESX (Bit 16)                                */
30392 #define DC_LAYER2RESXY_LAYER2PIXRESX_Msk  (0xffff0000UL)            /*!< LAYER2PIXRESX (Bitfield-Mask: 0xffff)                 */
30393 #define DC_LAYER2RESXY_LAYER2PIXRESY_Pos  (0UL)                     /*!< LAYER2PIXRESY (Bit 0)                                 */
30394 #define DC_LAYER2RESXY_LAYER2PIXRESY_Msk  (0xffffUL)                /*!< LAYER2PIXRESY (Bitfield-Mask: 0xffff)                 */
30395 /* =====================================================  LAYER2SCALEX  ====================================================== */
30396 #define DC_LAYER2SCALEX_LAYER2XFACTOR_Pos (0UL)                     /*!< LAYER2XFACTOR (Bit 0)                                 */
30397 #define DC_LAYER2SCALEX_LAYER2XFACTOR_Msk (0xffffffffUL)            /*!< LAYER2XFACTOR (Bitfield-Mask: 0xffffffff)             */
30398 /* =====================================================  LAYER2SCALEY  ====================================================== */
30399 #define DC_LAYER2SCALEY_LAYER2YFACTOR_Pos (0UL)                     /*!< LAYER2YFACTOR (Bit 0)                                 */
30400 #define DC_LAYER2SCALEY_LAYER2YFACTOR_Msk (0xffffffffUL)            /*!< LAYER2YFACTOR (Bitfield-Mask: 0xffffffff)             */
30401 /* ======================================================  LAYER3MODE  ======================================================= */
30402 #define DC_LAYER3MODE_LAYER3EN_Pos        (31UL)                    /*!< LAYER3EN (Bit 31)                                     */
30403 #define DC_LAYER3MODE_LAYER3EN_Msk        (0x80000000UL)            /*!< LAYER3EN (Bitfield-Mask: 0x01)                        */
30404 #define DC_LAYER3MODE_LAYER3FORCE_Pos     (30UL)                    /*!< LAYER3FORCE (Bit 30)                                  */
30405 #define DC_LAYER3MODE_LAYER3FORCE_Msk     (0x40000000UL)            /*!< LAYER3FORCE (Bitfield-Mask: 0x01)                     */
30406 #define DC_LAYER3MODE_LAYER3BFILTER_Pos   (29UL)                    /*!< LAYER3BFILTER (Bit 29)                                */
30407 #define DC_LAYER3MODE_LAYER3BFILTER_Msk   (0x20000000UL)            /*!< LAYER3BFILTER (Bitfield-Mask: 0x01)                   */
30408 #define DC_LAYER3MODE_LAYER3PREMULT_Pos   (28UL)                    /*!< LAYER3PREMULT (Bit 28)                                */
30409 #define DC_LAYER3MODE_LAYER3PREMULT_Msk   (0x10000000UL)            /*!< LAYER3PREMULT (Bitfield-Mask: 0x01)                   */
30410 #define DC_LAYER3MODE_LAYER3HLOCK_Pos     (27UL)                    /*!< LAYER3HLOCK (Bit 27)                                  */
30411 #define DC_LAYER3MODE_LAYER3HLOCK_Msk     (0x8000000UL)             /*!< LAYER3HLOCK (Bitfield-Mask: 0x01)                     */
30412 #define DC_LAYER3MODE_LAYER3GAMMA_Pos     (26UL)                    /*!< LAYER3GAMMA (Bit 26)                                  */
30413 #define DC_LAYER3MODE_LAYER3GAMMA_Msk     (0x4000000UL)             /*!< LAYER3GAMMA (Bitfield-Mask: 0x01)                     */
30414 #define DC_LAYER3MODE_RSVD1_Pos           (24UL)                    /*!< RSVD1 (Bit 24)                                        */
30415 #define DC_LAYER3MODE_RSVD1_Msk           (0x3000000UL)             /*!< RSVD1 (Bitfield-Mask: 0x03)                           */
30416 #define DC_LAYER3MODE_LAYER3ALPHA_Pos     (16UL)                    /*!< LAYER3ALPHA (Bit 16)                                  */
30417 #define DC_LAYER3MODE_LAYER3ALPHA_Msk     (0xff0000UL)              /*!< LAYER3ALPHA (Bitfield-Mask: 0xff)                     */
30418 #define DC_LAYER3MODE_LAYER3DBLEND_Pos    (12UL)                    /*!< LAYER3DBLEND (Bit 12)                                 */
30419 #define DC_LAYER3MODE_LAYER3DBLEND_Msk    (0xf000UL)                /*!< LAYER3DBLEND (Bitfield-Mask: 0x0f)                    */
30420 #define DC_LAYER3MODE_LAYER3SBLEND_Pos    (8UL)                     /*!< LAYER3SBLEND (Bit 8)                                  */
30421 #define DC_LAYER3MODE_LAYER3SBLEND_Msk    (0xf00UL)                 /*!< LAYER3SBLEND (Bitfield-Mask: 0x0f)                    */
30422 #define DC_LAYER3MODE_RSVD0_Pos           (5UL)                     /*!< RSVD0 (Bit 5)                                         */
30423 #define DC_LAYER3MODE_RSVD0_Msk           (0xe0UL)                  /*!< RSVD0 (Bitfield-Mask: 0x07)                           */
30424 #define DC_LAYER3MODE_LAYER3COLORMODE_Pos (0UL)                     /*!< LAYER3COLORMODE (Bit 0)                               */
30425 #define DC_LAYER3MODE_LAYER3COLORMODE_Msk (0x1fUL)                  /*!< LAYER3COLORMODE (Bitfield-Mask: 0x1f)                 */
30426 /* =====================================================  LAYER3STARTXY  ===================================================== */
30427 #define DC_LAYER3STARTXY_LAYER3XOFF_Pos   (16UL)                    /*!< LAYER3XOFF (Bit 16)                                   */
30428 #define DC_LAYER3STARTXY_LAYER3XOFF_Msk   (0xffff0000UL)            /*!< LAYER3XOFF (Bitfield-Mask: 0xffff)                    */
30429 #define DC_LAYER3STARTXY_LAYER3YOFF_Pos   (0UL)                     /*!< LAYER3YOFF (Bit 0)                                    */
30430 #define DC_LAYER3STARTXY_LAYER3YOFF_Msk   (0xffffUL)                /*!< LAYER3YOFF (Bitfield-Mask: 0xffff)                    */
30431 /* =====================================================  LAYER3SIZEXY  ====================================================== */
30432 #define DC_LAYER3SIZEXY_LAYER3PIXSZEX_Pos (16UL)                    /*!< LAYER3PIXSZEX (Bit 16)                                */
30433 #define DC_LAYER3SIZEXY_LAYER3PIXSZEX_Msk (0xffff0000UL)            /*!< LAYER3PIXSZEX (Bitfield-Mask: 0xffff)                 */
30434 #define DC_LAYER3SIZEXY_LAYER3PIXSZEY_Pos (0UL)                     /*!< LAYER3PIXSZEY (Bit 0)                                 */
30435 #define DC_LAYER3SIZEXY_LAYER3PIXSZEY_Msk (0xffffUL)                /*!< LAYER3PIXSZEY (Bitfield-Mask: 0xffff)                 */
30436 /* ======================================================  LAYER3ADDR  ======================================================= */
30437 #define DC_LAYER3ADDR_LAYER3STARTADDRFBUF_Pos (0UL)                 /*!< LAYER3STARTADDRFBUF (Bit 0)                           */
30438 #define DC_LAYER3ADDR_LAYER3STARTADDRFBUF_Msk (0xffffffffUL)        /*!< LAYER3STARTADDRFBUF (Bitfield-Mask: 0xffffffff)       */
30439 /* =====================================================  LAYER3STRIDE  ====================================================== */
30440 #define DC_LAYER3STRIDE_RSVD_Pos          (21UL)                    /*!< RSVD (Bit 21)                                         */
30441 #define DC_LAYER3STRIDE_RSVD_Msk          (0xffe00000UL)            /*!< RSVD (Bitfield-Mask: 0x7ff)                           */
30442 #define DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_Pos (19UL)                /*!< LAYER3AXIFIFOTHLD (Bit 19)                            */
30443 #define DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_Msk (0x180000UL)          /*!< LAYER3AXIFIFOTHLD (Bitfield-Mask: 0x03)               */
30444 #define DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_Pos (16UL)               /*!< LAYER3AXIBURSTBITS (Bit 16)                           */
30445 #define DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_Msk (0x70000UL)          /*!< LAYER3AXIBURSTBITS (Bitfield-Mask: 0x07)              */
30446 #define DC_LAYER3STRIDE_LAYER3STRIDEDIST_Pos (0UL)                  /*!< LAYER3STRIDEDIST (Bit 0)                              */
30447 #define DC_LAYER3STRIDE_LAYER3STRIDEDIST_Msk (0xffffUL)             /*!< LAYER3STRIDEDIST (Bitfield-Mask: 0xffff)              */
30448 /* ======================================================  LAYER3RESXY  ====================================================== */
30449 #define DC_LAYER3RESXY_LAYER3PIXRESX_Pos  (16UL)                    /*!< LAYER3PIXRESX (Bit 16)                                */
30450 #define DC_LAYER3RESXY_LAYER3PIXRESX_Msk  (0xffff0000UL)            /*!< LAYER3PIXRESX (Bitfield-Mask: 0xffff)                 */
30451 #define DC_LAYER3RESXY_LAYER3PIXRESY_Pos  (0UL)                     /*!< LAYER3PIXRESY (Bit 0)                                 */
30452 #define DC_LAYER3RESXY_LAYER3PIXRESY_Msk  (0xffffUL)                /*!< LAYER3PIXRESY (Bitfield-Mask: 0xffff)                 */
30453 /* =====================================================  LAYER3SCALEX  ====================================================== */
30454 #define DC_LAYER3SCALEX_LAYER3XFACTOR_Pos (0UL)                     /*!< LAYER3XFACTOR (Bit 0)                                 */
30455 #define DC_LAYER3SCALEX_LAYER3XFACTOR_Msk (0xffffffffUL)            /*!< LAYER3XFACTOR (Bitfield-Mask: 0xffffffff)             */
30456 /* =====================================================  LAYER3SCALEY  ====================================================== */
30457 #define DC_LAYER3SCALEY_LAYER3YFACTOR_Pos (0UL)                     /*!< LAYER3YFACTOR (Bit 0)                                 */
30458 #define DC_LAYER3SCALEY_LAYER3YFACTOR_Msk (0xffffffffUL)            /*!< LAYER3YFACTOR (Bitfield-Mask: 0xffffffff)             */
30459 /* ========================================================  DBICMD  ========================================================= */
30460 #define DC_DBICMD_RSVD2_Pos               (31UL)                    /*!< RSVD2 (Bit 31)                                        */
30461 #define DC_DBICMD_RSVD2_Msk               (0x80000000UL)            /*!< RSVD2 (Bitfield-Mask: 0x01)                           */
30462 #define DC_DBICMD_DIRECTDATA_Pos          (30UL)                    /*!< DIRECTDATA (Bit 30)                                   */
30463 #define DC_DBICMD_DIRECTDATA_Msk          (0x40000000UL)            /*!< DIRECTDATA (Bitfield-Mask: 0x01)                      */
30464 #define DC_DBICMD_RSVD1_Pos               (29UL)                    /*!< RSVD1 (Bit 29)                                        */
30465 #define DC_DBICMD_RSVD1_Msk               (0x20000000UL)            /*!< RSVD1 (Bitfield-Mask: 0x01)                           */
30466 #define DC_DBICMD_READDBI_Pos             (28UL)                    /*!< READDBI (Bit 28)                                      */
30467 #define DC_DBICMD_READDBI_Msk             (0x10000000UL)            /*!< READDBI (Bitfield-Mask: 0x01)                         */
30468 #define DC_DBICMD_LOCALSTORE_Pos          (27UL)                    /*!< LOCALSTORE (Bit 27)                                   */
30469 #define DC_DBICMD_LOCALSTORE_Msk          (0x8000000UL)             /*!< LOCALSTORE (Bitfield-Mask: 0x01)                      */
30470 #define DC_DBICMD_RSVD0_Pos               (16UL)                    /*!< RSVD0 (Bit 16)                                        */
30471 #define DC_DBICMD_RSVD0_Msk               (0x7ff0000UL)             /*!< RSVD0 (Bitfield-Mask: 0x7ff)                          */
30472 #define DC_DBICMD_DATA2DBI_Pos            (0UL)                     /*!< DATA2DBI (Bit 0)                                      */
30473 #define DC_DBICMD_DATA2DBI_Msk            (0xffffUL)                /*!< DATA2DBI (Bitfield-Mask: 0xffff)                      */
30474 /* ========================================================  DBIRDAT  ======================================================== */
30475 #define DC_DBIRDAT_READTYPEB_Pos          (0UL)                     /*!< READTYPEB (Bit 0)                                     */
30476 #define DC_DBIRDAT_READTYPEB_Msk          (0xffffffffUL)            /*!< READTYPEB (Bitfield-Mask: 0xffffffff)                 */
30477 /* =========================================================  CONFG  ========================================================= */
30478 #define DC_CONFG_RSVD_Pos                 (24UL)                    /*!< RSVD (Bit 24)                                         */
30479 #define DC_CONFG_RSVD_Msk                 (0xff000000UL)            /*!< RSVD (Bitfield-Mask: 0xff)                            */
30480 #define DC_CONFG_CFGLAYER3GAMMALUT_Pos    (23UL)                    /*!< CFGLAYER3GAMMALUT (Bit 23)                            */
30481 #define DC_CONFG_CFGLAYER3GAMMALUT_Msk    (0x800000UL)              /*!< CFGLAYER3GAMMALUT (Bitfield-Mask: 0x01)               */
30482 #define DC_CONFG_CFGLAYER3SCALAR_Pos      (22UL)                    /*!< CFGLAYER3SCALAR (Bit 22)                              */
30483 #define DC_CONFG_CFGLAYER3SCALAR_Msk      (0x400000UL)              /*!< CFGLAYER3SCALAR (Bitfield-Mask: 0x01)                 */
30484 #define DC_CONFG_CFGLAYER3BLENDER_Pos     (21UL)                    /*!< CFGLAYER3BLENDER (Bit 21)                             */
30485 #define DC_CONFG_CFGLAYER3BLENDER_Msk     (0x200000UL)              /*!< CFGLAYER3BLENDER (Bitfield-Mask: 0x01)                */
30486 #define DC_CONFG_CFGLAYER3EN_Pos          (20UL)                    /*!< CFGLAYER3EN (Bit 20)                                  */
30487 #define DC_CONFG_CFGLAYER3EN_Msk          (0x100000UL)              /*!< CFGLAYER3EN (Bitfield-Mask: 0x01)                     */
30488 #define DC_CONFG_CFGLAYER2GAMMALUT_Pos    (19UL)                    /*!< CFGLAYER2GAMMALUT (Bit 19)                            */
30489 #define DC_CONFG_CFGLAYER2GAMMALUT_Msk    (0x80000UL)               /*!< CFGLAYER2GAMMALUT (Bitfield-Mask: 0x01)               */
30490 #define DC_CONFG_CFGLAYER2SCALAR_Pos      (18UL)                    /*!< CFGLAYER2SCALAR (Bit 18)                              */
30491 #define DC_CONFG_CFGLAYER2SCALAR_Msk      (0x40000UL)               /*!< CFGLAYER2SCALAR (Bitfield-Mask: 0x01)                 */
30492 #define DC_CONFG_CFGLAYER2BLENDER_Pos     (17UL)                    /*!< CFGLAYER2BLENDER (Bit 17)                             */
30493 #define DC_CONFG_CFGLAYER2BLENDER_Msk     (0x20000UL)               /*!< CFGLAYER2BLENDER (Bitfield-Mask: 0x01)                */
30494 #define DC_CONFG_CFGLAYER2EN_Pos          (16UL)                    /*!< CFGLAYER2EN (Bit 16)                                  */
30495 #define DC_CONFG_CFGLAYER2EN_Msk          (0x10000UL)               /*!< CFGLAYER2EN (Bitfield-Mask: 0x01)                     */
30496 #define DC_CONFG_CFGLAYER1GAMMALUT_Pos    (15UL)                    /*!< CFGLAYER1GAMMALUT (Bit 15)                            */
30497 #define DC_CONFG_CFGLAYER1GAMMALUT_Msk    (0x8000UL)                /*!< CFGLAYER1GAMMALUT (Bitfield-Mask: 0x01)               */
30498 #define DC_CONFG_CFGLAYER1SCALAR_Pos      (14UL)                    /*!< CFGLAYER1SCALAR (Bit 14)                              */
30499 #define DC_CONFG_CFGLAYER1SCALAR_Msk      (0x4000UL)                /*!< CFGLAYER1SCALAR (Bitfield-Mask: 0x01)                 */
30500 #define DC_CONFG_CFGLAYER1BLENDER_Pos     (13UL)                    /*!< CFGLAYER1BLENDER (Bit 13)                             */
30501 #define DC_CONFG_CFGLAYER1BLENDER_Msk     (0x2000UL)                /*!< CFGLAYER1BLENDER (Bitfield-Mask: 0x01)                */
30502 #define DC_CONFG_CFGLAYER1EN_Pos          (12UL)                    /*!< CFGLAYER1EN (Bit 12)                                  */
30503 #define DC_CONFG_CFGLAYER1EN_Msk          (0x1000UL)                /*!< CFGLAYER1EN (Bitfield-Mask: 0x01)                     */
30504 #define DC_CONFG_CFGLAYER0GAMMALUT_Pos    (11UL)                    /*!< CFGLAYER0GAMMALUT (Bit 11)                            */
30505 #define DC_CONFG_CFGLAYER0GAMMALUT_Msk    (0x800UL)                 /*!< CFGLAYER0GAMMALUT (Bitfield-Mask: 0x01)               */
30506 #define DC_CONFG_CFGLAYER0SCALAR_Pos      (10UL)                    /*!< CFGLAYER0SCALAR (Bit 10)                              */
30507 #define DC_CONFG_CFGLAYER0SCALAR_Msk      (0x400UL)                 /*!< CFGLAYER0SCALAR (Bitfield-Mask: 0x01)                 */
30508 #define DC_CONFG_CFGLAYER0BLENDER_Pos     (9UL)                     /*!< CFGLAYER0BLENDER (Bit 9)                              */
30509 #define DC_CONFG_CFGLAYER0BLENDER_Msk     (0x200UL)                 /*!< CFGLAYER0BLENDER (Bitfield-Mask: 0x01)                */
30510 #define DC_CONFG_CFGLAYER0EN_Pos          (8UL)                     /*!< CFGLAYER0EN (Bit 8)                                   */
30511 #define DC_CONFG_CFGLAYER0EN_Msk          (0x100UL)                 /*!< CFGLAYER0EN (Bitfield-Mask: 0x01)                     */
30512 #define DC_CONFG_CFGRGB2YUVEN_Pos         (7UL)                     /*!< CFGRGB2YUVEN (Bit 7)                                  */
30513 #define DC_CONFG_CFGRGB2YUVEN_Msk         (0x80UL)                  /*!< CFGRGB2YUVEN (Bitfield-Mask: 0x01)                    */
30514 #define DC_CONFG_CFGDBITYPEBEN_Pos        (6UL)                     /*!< CFGDBITYPEBEN (Bit 6)                                 */
30515 #define DC_CONFG_CFGDBITYPEBEN_Msk        (0x40UL)                  /*!< CFGDBITYPEBEN (Bitfield-Mask: 0x01)                   */
30516 #define DC_CONFG_CFGYUVCNVTEN_Pos         (5UL)                     /*!< CFGYUVCNVTEN (Bit 5)                                  */
30517 #define DC_CONFG_CFGYUVCNVTEN_Msk         (0x20UL)                  /*!< CFGYUVCNVTEN (Bitfield-Mask: 0x01)                    */
30518 #define DC_CONFG_CFGFORMATTEN_Pos         (4UL)                     /*!< CFGFORMATTEN (Bit 4)                                  */
30519 #define DC_CONFG_CFGFORMATTEN_Msk         (0x10UL)                  /*!< CFGFORMATTEN (Bitfield-Mask: 0x01)                    */
30520 #define DC_CONFG_CFGDITHEREN_Pos          (3UL)                     /*!< CFGDITHEREN (Bit 3)                                   */
30521 #define DC_CONFG_CFGDITHEREN_Msk          (0x8UL)                   /*!< CFGDITHEREN (Bitfield-Mask: 0x01)                     */
30522 #define DC_CONFG_CFGPCURSOREN_Pos         (2UL)                     /*!< CFGPCURSOREN (Bit 2)                                  */
30523 #define DC_CONFG_CFGPCURSOREN_Msk         (0x4UL)                   /*!< CFGPCURSOREN (Bitfield-Mask: 0x01)                    */
30524 #define DC_CONFG_CFGFCURSOREN_Pos         (1UL)                     /*!< CFGFCURSOREN (Bit 1)                                  */
30525 #define DC_CONFG_CFGFCURSOREN_Msk         (0x2UL)                   /*!< CFGFCURSOREN (Bitfield-Mask: 0x01)                    */
30526 #define DC_CONFG_CFGGLBGAMMAEN_Pos        (0UL)                     /*!< CFGGLBGAMMAEN (Bit 0)                                 */
30527 #define DC_CONFG_CFGGLBGAMMAEN_Msk        (0x1UL)                   /*!< CFGGLBGAMMAEN (Bitfield-Mask: 0x01)                   */
30528 /* =========================================================  IDREG  ========================================================= */
30529 #define DC_IDREG_DCID_Pos                 (0UL)                     /*!< DCID (Bit 0)                                          */
30530 #define DC_IDREG_DCID_Msk                 (0xffffffffUL)            /*!< DCID (Bitfield-Mask: 0xffffffff)                      */
30531 /* =======================================================  INTERRUPT  ======================================================= */
30532 #define DC_INTERRUPT_INTTRIGGER_Pos       (31UL)                    /*!< INTTRIGGER (Bit 31)                                   */
30533 #define DC_INTERRUPT_INTTRIGGER_Msk       (0x80000000UL)            /*!< INTTRIGGER (Bitfield-Mask: 0x01)                      */
30534 #define DC_INTERRUPT_INTTEEN_Pos          (3UL)                     /*!< INTTEEN (Bit 3)                                       */
30535 #define DC_INTERRUPT_INTTEEN_Msk          (0x8UL)                   /*!< INTTEEN (Bitfield-Mask: 0x01)                         */
30536 #define DC_INTERRUPT_INTMMUERR_Pos        (2UL)                     /*!< INTMMUERR (Bit 2)                                     */
30537 #define DC_INTERRUPT_INTMMUERR_Msk        (0x4UL)                   /*!< INTMMUERR (Bitfield-Mask: 0x01)                       */
30538 #define DC_INTERRUPT_INTHSYNCEN_Pos       (1UL)                     /*!< INTHSYNCEN (Bit 1)                                    */
30539 #define DC_INTERRUPT_INTHSYNCEN_Msk       (0x2UL)                   /*!< INTHSYNCEN (Bitfield-Mask: 0x01)                      */
30540 #define DC_INTERRUPT_INTVSYNCEN_Pos       (0UL)                     /*!< INTVSYNCEN (Bit 0)                                    */
30541 #define DC_INTERRUPT_INTVSYNCEN_Msk       (0x1UL)                   /*!< INTVSYNCEN (Bitfield-Mask: 0x01)                      */
30542 /* ========================================================  STATUS  ========================================================= */
30543 #define DC_STATUS_STATDBIPENDTRANS_Pos    (12UL)                    /*!< STATDBIPENDTRANS (Bit 12)                             */
30544 #define DC_STATUS_STATDBIPENDTRANS_Msk    (0x1000UL)                /*!< STATDBIPENDTRANS (Bitfield-Mask: 0x01)                */
30545 #define DC_STATUS_STATDBIPENDCOM_Pos      (11UL)                    /*!< STATDBIPENDCOM (Bit 11)                               */
30546 #define DC_STATUS_STATDBIPENDCOM_Msk      (0x800UL)                 /*!< STATDBIPENDCOM (Bitfield-Mask: 0x01)                  */
30547 #define DC_STATUS_STATDBIRGB_Pos          (10UL)                    /*!< STATDBIRGB (Bit 10)                                   */
30548 #define DC_STATUS_STATDBIRGB_Msk          (0x400UL)                 /*!< STATDBIRGB (Bitfield-Mask: 0x01)                      */
30549 #define DC_STATUS_STATTEAR_Pos            (8UL)                     /*!< STATTEAR (Bit 8)                                      */
30550 #define DC_STATUS_STATTEAR_Msk            (0x100UL)                 /*!< STATTEAR (Bitfield-Mask: 0x01)                        */
30551 #define DC_STATUS_STATSTICKY_Pos          (7UL)                     /*!< STATSTICKY (Bit 7)                                    */
30552 #define DC_STATUS_STATSTICKY_Msk          (0x80UL)                  /*!< STATSTICKY (Bitfield-Mask: 0x01)                      */
30553 #define DC_STATUS_STATUF_Pos              (6UL)                     /*!< STATUF (Bit 6)                                        */
30554 #define DC_STATUS_STATUF_Msk              (0x40UL)                  /*!< STATUF (Bitfield-Mask: 0x01)                          */
30555 #define DC_STATUS_STATLAST_Pos            (5UL)                     /*!< STATLAST (Bit 5)                                      */
30556 #define DC_STATUS_STATLAST_Msk            (0x20UL)                  /*!< STATLAST (Bitfield-Mask: 0x01)                        */
30557 #define DC_STATUS_STATCSYNC_Pos           (4UL)                     /*!< STATCSYNC (Bit 4)                                     */
30558 #define DC_STATUS_STATCSYNC_Msk           (0x10UL)                  /*!< STATCSYNC (Bitfield-Mask: 0x01)                       */
30559 #define DC_STATUS_STATVSYNC_Pos           (3UL)                     /*!< STATVSYNC (Bit 3)                                     */
30560 #define DC_STATUS_STATVSYNC_Msk           (0x8UL)                   /*!< STATVSYNC (Bitfield-Mask: 0x01)                       */
30561 #define DC_STATUS_STATHSYNC_Pos           (2UL)                     /*!< STATHSYNC (Bit 2)                                     */
30562 #define DC_STATUS_STATHSYNC_Msk           (0x4UL)                   /*!< STATHSYNC (Bitfield-Mask: 0x01)                       */
30563 #define DC_STATUS_STATDE_Pos              (1UL)                     /*!< STATDE (Bit 1)                                        */
30564 #define DC_STATUS_STATDE_Msk              (0x2UL)                   /*!< STATDE (Bitfield-Mask: 0x01)                          */
30565 #define DC_STATUS_STATNOTBLANK_Pos        (0UL)                     /*!< STATNOTBLANK (Bit 0)                                  */
30566 #define DC_STATUS_STATNOTBLANK_Msk        (0x1UL)                   /*!< STATNOTBLANK (Bitfield-Mask: 0x01)                    */
30567 /* ========================================================  COLMOD  ========================================================= */
30568 #define DC_COLMOD_CLMDBKPRESSURE_Pos      (31UL)                    /*!< CLMDBKPRESSURE (Bit 31)                               */
30569 #define DC_COLMOD_CLMDBKPRESSURE_Msk      (0x80000000UL)            /*!< CLMDBKPRESSURE (Bitfield-Mask: 0x01)                  */
30570 #define DC_COLMOD_CLMDLVDS_Pos            (30UL)                    /*!< CLMDLVDS (Bit 30)                                     */
30571 #define DC_COLMOD_CLMDLVDS_Msk            (0x40000000UL)            /*!< CLMDLVDS (Bitfield-Mask: 0x01)                        */
30572 #define DC_COLMOD_CLMDJDI_Pos             (29UL)                    /*!< CLMDJDI (Bit 29)                                      */
30573 #define DC_COLMOD_CLMDJDI_Msk             (0x20000000UL)            /*!< CLMDJDI (Bitfield-Mask: 0x01)                         */
30574 #define DC_COLMOD_CLMDARGB4444_Pos        (22UL)                    /*!< CLMDARGB4444 (Bit 22)                                 */
30575 #define DC_COLMOD_CLMDARGB4444_Msk        (0x400000UL)              /*!< CLMDARGB4444 (Bitfield-Mask: 0x01)                    */
30576 #define DC_COLMOD_CLMDRGBA4444_Pos        (21UL)                    /*!< CLMDRGBA4444 (Bit 21)                                 */
30577 #define DC_COLMOD_CLMDRGBA4444_Msk        (0x200000UL)              /*!< CLMDRGBA4444 (Bitfield-Mask: 0x01)                    */
30578 #define DC_COLMOD_CLMDQPI_Pos             (20UL)                    /*!< CLMDQPI (Bit 20)                                      */
30579 #define DC_COLMOD_CLMDQPI_Msk             (0x100000UL)              /*!< CLMDQPI (Bitfield-Mask: 0x01)                         */
30580 #define DC_COLMOD_CLMDDBIBEXTCTRL_Pos     (19UL)                    /*!< CLMDDBIBEXTCTRL (Bit 19)                              */
30581 #define DC_COLMOD_CLMDDBIBEXTCTRL_Msk     (0x80000UL)               /*!< CLMDDBIBEXTCTRL (Bitfield-Mask: 0x01)                 */
30582 #define DC_COLMOD_CLMDTSC6_Pos            (18UL)                    /*!< CLMDTSC6 (Bit 18)                                     */
30583 #define DC_COLMOD_CLMDTSC6_Msk            (0x40000UL)               /*!< CLMDTSC6 (Bitfield-Mask: 0x01)                        */
30584 #define DC_COLMOD_CLMDTSC_Pos             (17UL)                    /*!< CLMDTSC (Bit 17)                                      */
30585 #define DC_COLMOD_CLMDTSC_Msk             (0x20000UL)               /*!< CLMDTSC (Bitfield-Mask: 0x01)                         */
30586 #define DC_COLMOD_CLMDLUT8_Pos            (16UL)                    /*!< CLMDLUT8 (Bit 16)                                     */
30587 #define DC_COLMOD_CLMDLUT8_Msk            (0x10000UL)               /*!< CLMDLUT8 (Bitfield-Mask: 0x01)                        */
30588 #define DC_COLMOD_CLMDRGBA5551_Pos        (15UL)                    /*!< CLMDRGBA5551 (Bit 15)                                 */
30589 #define DC_COLMOD_CLMDRGBA5551_Msk        (0x8000UL)                /*!< CLMDRGBA5551 (Bitfield-Mask: 0x01)                    */
30590 #define DC_COLMOD_CLMDRGBA8888_Pos        (14UL)                    /*!< CLMDRGBA8888 (Bit 14)                                 */
30591 #define DC_COLMOD_CLMDRGBA8888_Msk        (0x4000UL)                /*!< CLMDRGBA8888 (Bitfield-Mask: 0x01)                    */
30592 #define DC_COLMOD_CLMDRGB332_Pos          (13UL)                    /*!< CLMDRGB332 (Bit 13)                                   */
30593 #define DC_COLMOD_CLMDRGB332_Msk          (0x2000UL)                /*!< CLMDRGB332 (Bitfield-Mask: 0x01)                      */
30594 #define DC_COLMOD_CLMDRGB565_Pos          (12UL)                    /*!< CLMDRGB565 (Bit 12)                                   */
30595 #define DC_COLMOD_CLMDRGB565_Msk          (0x1000UL)                /*!< CLMDRGB565 (Bitfield-Mask: 0x01)                      */
30596 #define DC_COLMOD_CLMDARGB8888_Pos        (11UL)                    /*!< CLMDARGB8888 (Bit 11)                                 */
30597 #define DC_COLMOD_CLMDARGB8888_Msk        (0x800UL)                 /*!< CLMDARGB8888 (Bitfield-Mask: 0x01)                    */
30598 #define DC_COLMOD_CLMDL8_Pos              (10UL)                    /*!< CLMDL8 (Bit 10)                                       */
30599 #define DC_COLMOD_CLMDL8_Msk              (0x400UL)                 /*!< CLMDL8 (Bitfield-Mask: 0x01)                          */
30600 #define DC_COLMOD_CLMDL1_Pos              (9UL)                     /*!< CLMDL1 (Bit 9)                                        */
30601 #define DC_COLMOD_CLMDL1_Msk              (0x200UL)                 /*!< CLMDL1 (Bitfield-Mask: 0x01)                          */
30602 #define DC_COLMOD_CLMDL4_Pos              (8UL)                     /*!< CLMDL4 (Bit 8)                                        */
30603 #define DC_COLMOD_CLMDL4_Msk              (0x100UL)                 /*!< CLMDL4 (Bitfield-Mask: 0x01)                          */
30604 #define DC_COLMOD_CLMDYUYV_Pos            (7UL)                     /*!< CLMDYUYV (Bit 7)                                      */
30605 #define DC_COLMOD_CLMDYUYV_Msk            (0x80UL)                  /*!< CLMDYUYV (Bitfield-Mask: 0x01)                        */
30606 #define DC_COLMOD_CLMDRGB888_Pos          (6UL)                     /*!< CLMDRGB888 (Bit 6)                                    */
30607 #define DC_COLMOD_CLMDRGB888_Msk          (0x40UL)                  /*!< CLMDRGB888 (Bitfield-Mask: 0x01)                      */
30608 #define DC_COLMOD_CLMDYUY2_Pos            (5UL)                     /*!< CLMDYUY2 (Bit 5)                                      */
30609 #define DC_COLMOD_CLMDYUY2_Msk            (0x20UL)                  /*!< CLMDYUY2 (Bitfield-Mask: 0x01)                        */
30610 #define DC_COLMOD_CLMDABGR8888_Pos        (4UL)                     /*!< CLMDABGR8888 (Bit 4)                                  */
30611 #define DC_COLMOD_CLMDABGR8888_Msk        (0x10UL)                  /*!< CLMDABGR8888 (Bitfield-Mask: 0x01)                    */
30612 #define DC_COLMOD_CLMDBGRA8888_Pos        (3UL)                     /*!< CLMDBGRA8888 (Bit 3)                                  */
30613 #define DC_COLMOD_CLMDBGRA8888_Msk        (0x8UL)                   /*!< CLMDBGRA8888 (Bitfield-Mask: 0x01)                    */
30614 #define DC_COLMOD_CLMDVYUV420_Pos         (2UL)                     /*!< CLMDVYUV420 (Bit 2)                                   */
30615 #define DC_COLMOD_CLMDVYUV420_Msk         (0x4UL)                   /*!< CLMDVYUV420 (Bitfield-Mask: 0x01)                     */
30616 #define DC_COLMOD_CLMDTLYUV420_Pos        (1UL)                     /*!< CLMDTLYUV420 (Bit 1)                                  */
30617 #define DC_COLMOD_CLMDTLYUV420_Msk        (0x2UL)                   /*!< CLMDTLYUV420 (Bitfield-Mask: 0x01)                    */
30618 #define DC_COLMOD_CLMDTSC4TSC6_Pos        (0UL)                     /*!< CLMDTSC4TSC6 (Bit 0)                                  */
30619 #define DC_COLMOD_CLMDTSC4TSC6_Msk        (0x1UL)                   /*!< CLMDTSC4TSC6 (Bitfield-Mask: 0x01)                    */
30620 /* ==========================================================  CRC  ========================================================== */
30621 #define DC_CRC_CRCREG_Pos                 (0UL)                     /*!< CRCREG (Bit 0)                                        */
30622 #define DC_CRC_CRCREG_Msk                 (0xffffffffUL)            /*!< CRCREG (Bitfield-Mask: 0xffffffff)                    */
30623 /* =========================================================  GLLUT  ========================================================= */
30624 #define DC_GLLUT_GLLUT0GAMRAMPR_Pos       (16UL)                    /*!< GLLUT0GAMRAMPR (Bit 16)                               */
30625 #define DC_GLLUT_GLLUT0GAMRAMPR_Msk       (0xff0000UL)              /*!< GLLUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30626 #define DC_GLLUT_GLLUT0GAMRAMPG_Pos       (8UL)                     /*!< GLLUT0GAMRAMPG (Bit 8)                                */
30627 #define DC_GLLUT_GLLUT0GAMRAMPG_Msk       (0xff00UL)                /*!< GLLUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30628 #define DC_GLLUT_GLLUT0GAMRAMPB_Pos       (0UL)                     /*!< GLLUT0GAMRAMPB (Bit 0)                                */
30629 #define DC_GLLUT_GLLUT0GAMRAMPB_Msk       (0xffUL)                  /*!< GLLUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30630 /* ======================================================  CURSORDATA  ======================================================= */
30631 #define DC_CURSORDATA_CURDATA3112_Pos     (12UL)                    /*!< CURDATA3112 (Bit 12)                                  */
30632 #define DC_CURSORDATA_CURDATA3112_Msk     (0xfffff000UL)            /*!< CURDATA3112 (Bitfield-Mask: 0xfffff)                  */
30633 #define DC_CURSORDATA_CURDATA70_Pos       (0UL)                     /*!< CURDATA70 (Bit 0)                                     */
30634 #define DC_CURSORDATA_CURDATA70_Msk       (0xffUL)                  /*!< CURDATA70 (Bitfield-Mask: 0xff)                       */
30635 /* =======================================================  CURSORLUT  ======================================================= */
30636 #define DC_CURSORLUT_CURLUT0R_Pos         (16UL)                    /*!< CURLUT0R (Bit 16)                                     */
30637 #define DC_CURSORLUT_CURLUT0R_Msk         (0xff0000UL)              /*!< CURLUT0R (Bitfield-Mask: 0xff)                        */
30638 #define DC_CURSORLUT_CURLUT0G_Pos         (8UL)                     /*!< CURLUT0G (Bit 8)                                      */
30639 #define DC_CURSORLUT_CURLUT0G_Msk         (0xff00UL)                /*!< CURLUT0G (Bitfield-Mask: 0xff)                        */
30640 #define DC_CURSORLUT_CURLUT0B_Pos         (0UL)                     /*!< CURLUT0B (Bit 0)                                      */
30641 #define DC_CURSORLUT_CURLUT0B_Msk         (0xffUL)                  /*!< CURLUT0B (Bitfield-Mask: 0xff)                        */
30642 /* =========================================================  L0LUT  ========================================================= */
30643 #define DC_L0LUT_L0LUT0GAMRAMPA_Pos       (24UL)                    /*!< L0LUT0GAMRAMPA (Bit 24)                               */
30644 #define DC_L0LUT_L0LUT0GAMRAMPA_Msk       (0xff000000UL)            /*!< L0LUT0GAMRAMPA (Bitfield-Mask: 0xff)                  */
30645 #define DC_L0LUT_L0LUT0GAMRAMPR_Pos       (16UL)                    /*!< L0LUT0GAMRAMPR (Bit 16)                               */
30646 #define DC_L0LUT_L0LUT0GAMRAMPR_Msk       (0xff0000UL)              /*!< L0LUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30647 #define DC_L0LUT_L0LUT0GAMRAMPG_Pos       (8UL)                     /*!< L0LUT0GAMRAMPG (Bit 8)                                */
30648 #define DC_L0LUT_L0LUT0GAMRAMPG_Msk       (0xff00UL)                /*!< L0LUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30649 #define DC_L0LUT_L0LUT0GAMRAMPB_Pos       (0UL)                     /*!< L0LUT0GAMRAMPB (Bit 0)                                */
30650 #define DC_L0LUT_L0LUT0GAMRAMPB_Msk       (0xffUL)                  /*!< L0LUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30651 /* =========================================================  L1LUT  ========================================================= */
30652 #define DC_L1LUT_L1LUT0GAMRAMPA_Pos       (24UL)                    /*!< L1LUT0GAMRAMPA (Bit 24)                               */
30653 #define DC_L1LUT_L1LUT0GAMRAMPA_Msk       (0xff000000UL)            /*!< L1LUT0GAMRAMPA (Bitfield-Mask: 0xff)                  */
30654 #define DC_L1LUT_L1LUT0GAMRAMPR_Pos       (16UL)                    /*!< L1LUT0GAMRAMPR (Bit 16)                               */
30655 #define DC_L1LUT_L1LUT0GAMRAMPR_Msk       (0xff0000UL)              /*!< L1LUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30656 #define DC_L1LUT_L1LUT0GAMRAMPG_Pos       (8UL)                     /*!< L1LUT0GAMRAMPG (Bit 8)                                */
30657 #define DC_L1LUT_L1LUT0GAMRAMPG_Msk       (0xff00UL)                /*!< L1LUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30658 #define DC_L1LUT_L1LUT0GAMRAMPB_Pos       (0UL)                     /*!< L1LUT0GAMRAMPB (Bit 0)                                */
30659 #define DC_L1LUT_L1LUT0GAMRAMPB_Msk       (0xffUL)                  /*!< L1LUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30660 /* ========================================================  L2LUT0  ========================================================= */
30661 #define DC_L2LUT0_L2LUT0GAMRAMPA_Pos      (24UL)                    /*!< L2LUT0GAMRAMPA (Bit 24)                               */
30662 #define DC_L2LUT0_L2LUT0GAMRAMPA_Msk      (0xff000000UL)            /*!< L2LUT0GAMRAMPA (Bitfield-Mask: 0xff)                  */
30663 #define DC_L2LUT0_L2LUT0GAMRAMPR_Pos      (16UL)                    /*!< L2LUT0GAMRAMPR (Bit 16)                               */
30664 #define DC_L2LUT0_L2LUT0GAMRAMPR_Msk      (0xff0000UL)              /*!< L2LUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30665 #define DC_L2LUT0_L2LUT0GAMRAMPG_Pos      (8UL)                     /*!< L2LUT0GAMRAMPG (Bit 8)                                */
30666 #define DC_L2LUT0_L2LUT0GAMRAMPG_Msk      (0xff00UL)                /*!< L2LUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30667 #define DC_L2LUT0_L2LUT0GAMRAMPB_Pos      (0UL)                     /*!< L2LUT0GAMRAMPB (Bit 0)                                */
30668 #define DC_L2LUT0_L2LUT0GAMRAMPB_Msk      (0xffUL)                  /*!< L2LUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30669 /* =========================================================  L3LUT  ========================================================= */
30670 #define DC_L3LUT_L3LUT0GAMRAMPA_Pos       (24UL)                    /*!< L3LUT0GAMRAMPA (Bit 24)                               */
30671 #define DC_L3LUT_L3LUT0GAMRAMPA_Msk       (0xff000000UL)            /*!< L3LUT0GAMRAMPA (Bitfield-Mask: 0xff)                  */
30672 #define DC_L3LUT_L3LUT0GAMRAMPR_Pos       (16UL)                    /*!< L3LUT0GAMRAMPR (Bit 16)                               */
30673 #define DC_L3LUT_L3LUT0GAMRAMPR_Msk       (0xff0000UL)              /*!< L3LUT0GAMRAMPR (Bitfield-Mask: 0xff)                  */
30674 #define DC_L3LUT_L3LUT0GAMRAMPG_Pos       (8UL)                     /*!< L3LUT0GAMRAMPG (Bit 8)                                */
30675 #define DC_L3LUT_L3LUT0GAMRAMPG_Msk       (0xff00UL)                /*!< L3LUT0GAMRAMPG (Bitfield-Mask: 0xff)                  */
30676 #define DC_L3LUT_L3LUT0GAMRAMPB_Pos       (0UL)                     /*!< L3LUT0GAMRAMPB (Bit 0)                                */
30677 #define DC_L3LUT_L3LUT0GAMRAMPB_Msk       (0xffUL)                  /*!< L3LUT0GAMRAMPB (Bitfield-Mask: 0xff)                  */
30678 
30679 
30680 /* =========================================================================================================================== */
30681 /* ================                                            DSI                                            ================ */
30682 /* =========================================================================================================================== */
30683 
30684 /* ======================================================  DEVICEREADY  ====================================================== */
30685 #define DSI_DEVICEREADY_DISPLAYBUSPOSSESSEN_Pos (3UL)               /*!< DISPLAYBUSPOSSESSEN (Bit 3)                           */
30686 #define DSI_DEVICEREADY_DISPLAYBUSPOSSESSEN_Msk (0x8UL)             /*!< DISPLAYBUSPOSSESSEN (Bitfield-Mask: 0x01)             */
30687 #define DSI_DEVICEREADY_ULPS_Pos          (1UL)                     /*!< ULPS (Bit 1)                                          */
30688 #define DSI_DEVICEREADY_ULPS_Msk          (0x6UL)                   /*!< ULPS (Bitfield-Mask: 0x03)                            */
30689 #define DSI_DEVICEREADY_READY_Pos         (0UL)                     /*!< READY (Bit 0)                                         */
30690 #define DSI_DEVICEREADY_READY_Msk         (0x1UL)                   /*!< READY (Bitfield-Mask: 0x01)                           */
30691 /* =======================================================  INTRSTAT  ======================================================== */
30692 #define DSI_INTRSTAT_DPIPRGERR_Pos        (31UL)                    /*!< DPIPRGERR (Bit 31)                                    */
30693 #define DSI_INTRSTAT_DPIPRGERR_Msk        (0x80000000UL)            /*!< DPIPRGERR (Bitfield-Mask: 0x01)                       */
30694 #define DSI_INTRSTAT_DPILINETO_Pos        (30UL)                    /*!< DPILINETO (Bit 30)                                    */
30695 #define DSI_INTRSTAT_DPILINETO_Msk        (0x40000000UL)            /*!< DPILINETO (Bitfield-Mask: 0x01)                       */
30696 #define DSI_INTRSTAT_RXCNT_Pos            (29UL)                    /*!< RXCNT (Bit 29)                                        */
30697 #define DSI_INTRSTAT_RXCNT_Msk            (0x20000000UL)            /*!< RXCNT (Bitfield-Mask: 0x01)                           */
30698 #define DSI_INTRSTAT_INITDONE_Pos         (28UL)                    /*!< INITDONE (Bit 28)                                     */
30699 #define DSI_INTRSTAT_INITDONE_Msk         (0x10000000UL)            /*!< INITDONE (Bitfield-Mask: 0x01)                        */
30700 #define DSI_INTRSTAT_SPECIALPACK_Pos      (27UL)                    /*!< SPECIALPACK (Bit 27)                                  */
30701 #define DSI_INTRSTAT_SPECIALPACK_Msk      (0x8000000UL)             /*!< SPECIALPACK (Bitfield-Mask: 0x01)                     */
30702 #define DSI_INTRSTAT_RXDSIPROT_Pos        (26UL)                    /*!< RXDSIPROT (Bit 26)                                    */
30703 #define DSI_INTRSTAT_RXDSIPROT_Msk        (0x4000000UL)             /*!< RXDSIPROT (Bitfield-Mask: 0x01)                       */
30704 #define DSI_INTRSTAT_RXINVALID_Pos        (25UL)                    /*!< RXINVALID (Bit 25)                                    */
30705 #define DSI_INTRSTAT_RXINVALID_Msk        (0x2000000UL)             /*!< RXINVALID (Bitfield-Mask: 0x01)                       */
30706 #define DSI_INTRSTAT_ACKWNOERR_Pos        (24UL)                    /*!< ACKWNOERR (Bit 24)                                    */
30707 #define DSI_INTRSTAT_ACKWNOERR_Msk        (0x1000000UL)             /*!< ACKWNOERR (Bitfield-Mask: 0x01)                       */
30708 #define DSI_INTRSTAT_TURNARNDACK_Pos      (23UL)                    /*!< TURNARNDACK (Bit 23)                                  */
30709 #define DSI_INTRSTAT_TURNARNDACK_Msk      (0x800000UL)              /*!< TURNARNDACK (Bitfield-Mask: 0x01)                     */
30710 #define DSI_INTRSTAT_LPRXTIMEOUT_Pos      (22UL)                    /*!< LPRXTIMEOUT (Bit 22)                                  */
30711 #define DSI_INTRSTAT_LPRXTIMEOUT_Msk      (0x400000UL)              /*!< LPRXTIMEOUT (Bitfield-Mask: 0x01)                     */
30712 #define DSI_INTRSTAT_HSTXTIMEOUT_Pos      (21UL)                    /*!< HSTXTIMEOUT (Bit 21)                                  */
30713 #define DSI_INTRSTAT_HSTXTIMEOUT_Msk      (0x200000UL)              /*!< HSTXTIMEOUT (Bitfield-Mask: 0x01)                     */
30714 #define DSI_INTRSTAT_FIFOEMPTY_Pos        (20UL)                    /*!< FIFOEMPTY (Bit 20)                                    */
30715 #define DSI_INTRSTAT_FIFOEMPTY_Msk        (0x100000UL)              /*!< FIFOEMPTY (Bitfield-Mask: 0x01)                       */
30716 #define DSI_INTRSTAT_LOWC_Pos             (19UL)                    /*!< LOWC (Bit 19)                                         */
30717 #define DSI_INTRSTAT_LOWC_Msk             (0x80000UL)               /*!< LOWC (Bitfield-Mask: 0x01)                            */
30718 #define DSI_INTRSTAT_HIGHC_Pos            (18UL)                    /*!< HIGHC (Bit 18)                                        */
30719 #define DSI_INTRSTAT_HIGHC_Msk            (0x40000UL)               /*!< HIGHC (Bitfield-Mask: 0x01)                           */
30720 #define DSI_INTRSTAT_TxDSII_Pos           (17UL)                    /*!< TxDSII (Bit 17)                                       */
30721 #define DSI_INTRSTAT_TxDSII_Msk           (0x20000UL)               /*!< TxDSII (Bitfield-Mask: 0x01)                          */
30722 #define DSI_INTRSTAT_TxDSIN_Pos           (16UL)                    /*!< TxDSIN (Bit 16)                                       */
30723 #define DSI_INTRSTAT_TxDSIN_Msk           (0x10000UL)               /*!< TxDSIN (Bitfield-Mask: 0x01)                          */
30724 #define DSI_INTRSTAT_TXCHECKSUM_Pos       (15UL)                    /*!< TXCHECKSUM (Bit 15)                                   */
30725 #define DSI_INTRSTAT_TXCHECKSUM_Msk       (0x8000UL)                /*!< TXCHECKSUM (Bitfield-Mask: 0x01)                      */
30726 #define DSI_INTRSTAT_TXECCM_Pos           (14UL)                    /*!< TXECCM (Bit 14)                                       */
30727 #define DSI_INTRSTAT_TXECCM_Msk           (0x4000UL)                /*!< TXECCM (Bitfield-Mask: 0x01)                          */
30728 #define DSI_INTRSTAT_TXECCS_Pos           (13UL)                    /*!< TXECCS (Bit 13)                                       */
30729 #define DSI_INTRSTAT_TXECCS_Msk           (0x2000UL)                /*!< TXECCS (Bitfield-Mask: 0x01)                          */
30730 #define DSI_INTRSTAT_TXFALSECNTRL_Pos     (12UL)                    /*!< TXFALSECNTRL (Bit 12)                                 */
30731 #define DSI_INTRSTAT_TXFALSECNTRL_Msk     (0x1000UL)                /*!< TXFALSECNTRL (Bitfield-Mask: 0x01)                    */
30732 #define DSI_INTRSTAT_RxDSIDI_Pos          (11UL)                    /*!< RxDSIDI (Bit 11)                                      */
30733 #define DSI_INTRSTAT_RxDSIDI_Msk          (0x800UL)                 /*!< RxDSIDI (Bitfield-Mask: 0x01)                         */
30734 #define DSI_INTRSTAT_RxDSINR_Pos          (10UL)                    /*!< RxDSINR (Bit 10)                                      */
30735 #define DSI_INTRSTAT_RxDSINR_Msk          (0x400UL)                 /*!< RxDSINR (Bitfield-Mask: 0x01)                         */
30736 #define DSI_INTRSTAT_RXCHECKSUM_Pos       (9UL)                     /*!< RXCHECKSUM (Bit 9)                                    */
30737 #define DSI_INTRSTAT_RXCHECKSUM_Msk       (0x200UL)                 /*!< RXCHECKSUM (Bitfield-Mask: 0x01)                      */
30738 #define DSI_INTRSTAT_RxECCM_Pos           (8UL)                     /*!< RxECCM (Bit 8)                                        */
30739 #define DSI_INTRSTAT_RxECCM_Msk           (0x100UL)                 /*!< RxECCM (Bitfield-Mask: 0x01)                          */
30740 #define DSI_INTRSTAT_RxECCS_Pos           (7UL)                     /*!< RxECCS (Bit 7)                                        */
30741 #define DSI_INTRSTAT_RxECCS_Msk           (0x80UL)                  /*!< RxECCS (Bitfield-Mask: 0x01)                          */
30742 #define DSI_INTRSTAT_RXFALSECNTRL_Pos     (6UL)                     /*!< RXFALSECNTRL (Bit 6)                                  */
30743 #define DSI_INTRSTAT_RXFALSECNTRL_Msk     (0x40UL)                  /*!< RXFALSECNTRL (Bitfield-Mask: 0x01)                    */
30744 #define DSI_INTRSTAT_RXPERIPHERAL_Pos     (5UL)                     /*!< RXPERIPHERAL (Bit 5)                                  */
30745 #define DSI_INTRSTAT_RXPERIPHERAL_Msk     (0x20UL)                  /*!< RXPERIPHERAL (Bitfield-Mask: 0x01)                    */
30746 #define DSI_INTRSTAT_RXLPTXSYNCERR_Pos    (4UL)                     /*!< RXLPTXSYNCERR (Bit 4)                                 */
30747 #define DSI_INTRSTAT_RXLPTXSYNCERR_Msk    (0x10UL)                  /*!< RXLPTXSYNCERR (Bitfield-Mask: 0x01)                   */
30748 #define DSI_INTRSTAT_RXESCAPEMODE_Pos     (3UL)                     /*!< RXESCAPEMODE (Bit 3)                                  */
30749 #define DSI_INTRSTAT_RXESCAPEMODE_Msk     (0x8UL)                   /*!< RXESCAPEMODE (Bitfield-Mask: 0x01)                    */
30750 #define DSI_INTRSTAT_RXEOTSYNCERROR_Pos   (2UL)                     /*!< RXEOTSYNCERROR (Bit 2)                                */
30751 #define DSI_INTRSTAT_RXEOTSYNCERROR_Msk   (0x4UL)                   /*!< RXEOTSYNCERROR (Bitfield-Mask: 0x01)                  */
30752 #define DSI_INTRSTAT_RXSOTSYNCERROR_Pos   (1UL)                     /*!< RXSOTSYNCERROR (Bit 1)                                */
30753 #define DSI_INTRSTAT_RXSOTSYNCERROR_Msk   (0x2UL)                   /*!< RXSOTSYNCERROR (Bitfield-Mask: 0x01)                  */
30754 #define DSI_INTRSTAT_RXSOTERROR_Pos       (0UL)                     /*!< RXSOTERROR (Bit 0)                                    */
30755 #define DSI_INTRSTAT_RXSOTERROR_Msk       (0x1UL)                   /*!< RXSOTERROR (Bitfield-Mask: 0x01)                      */
30756 /* ========================================================  INTREN  ========================================================= */
30757 #define DSI_INTREN_DPI_Pos                (31UL)                    /*!< DPI (Bit 31)                                          */
30758 #define DSI_INTREN_DPI_Msk                (0x80000000UL)            /*!< DPI (Bitfield-Mask: 0x01)                             */
30759 #define DSI_INTREN_DPILINETO_Pos          (30UL)                    /*!< DPILINETO (Bit 30)                                    */
30760 #define DSI_INTREN_DPILINETO_Msk          (0x40000000UL)            /*!< DPILINETO (Bitfield-Mask: 0x01)                       */
30761 #define DSI_INTREN_RXCONTENT_Pos          (29UL)                    /*!< RXCONTENT (Bit 29)                                    */
30762 #define DSI_INTREN_RXCONTENT_Msk          (0x20000000UL)            /*!< RXCONTENT (Bitfield-Mask: 0x01)                       */
30763 #define DSI_INTREN_INITDONE_Pos           (28UL)                    /*!< INITDONE (Bit 28)                                     */
30764 #define DSI_INTREN_INITDONE_Msk           (0x10000000UL)            /*!< INITDONE (Bitfield-Mask: 0x01)                        */
30765 #define DSI_INTREN_SPECIALPACK_Pos        (27UL)                    /*!< SPECIALPACK (Bit 27)                                  */
30766 #define DSI_INTREN_SPECIALPACK_Msk        (0x8000000UL)             /*!< SPECIALPACK (Bitfield-Mask: 0x01)                     */
30767 #define DSI_INTREN_RXDSI_Pos              (26UL)                    /*!< RXDSI (Bit 26)                                        */
30768 #define DSI_INTREN_RXDSI_Msk              (0x4000000UL)             /*!< RXDSI (Bitfield-Mask: 0x01)                           */
30769 #define DSI_INTREN_RXINV_Pos              (25UL)                    /*!< RXINV (Bit 25)                                        */
30770 #define DSI_INTREN_RXINV_Msk              (0x2000000UL)             /*!< RXINV (Bitfield-Mask: 0x01)                           */
30771 #define DSI_INTREN_ACKWITHNOERR_Pos       (24UL)                    /*!< ACKWITHNOERR (Bit 24)                                 */
30772 #define DSI_INTREN_ACKWITHNOERR_Msk       (0x1000000UL)             /*!< ACKWITHNOERR (Bitfield-Mask: 0x01)                    */
30773 #define DSI_INTREN_TURNARNDACK_Pos        (23UL)                    /*!< TURNARNDACK (Bit 23)                                  */
30774 #define DSI_INTREN_TURNARNDACK_Msk        (0x800000UL)              /*!< TURNARNDACK (Bitfield-Mask: 0x01)                     */
30775 #define DSI_INTREN_LPRXTIMEOUT_Pos        (22UL)                    /*!< LPRXTIMEOUT (Bit 22)                                  */
30776 #define DSI_INTREN_LPRXTIMEOUT_Msk        (0x400000UL)              /*!< LPRXTIMEOUT (Bitfield-Mask: 0x01)                     */
30777 #define DSI_INTREN_HSTXTIMEOUT_Pos        (21UL)                    /*!< HSTXTIMEOUT (Bit 21)                                  */
30778 #define DSI_INTREN_HSTXTIMEOUT_Msk        (0x200000UL)              /*!< HSTXTIMEOUT (Bitfield-Mask: 0x01)                     */
30779 #define DSI_INTREN_FIFOEMPTY_Pos          (20UL)                    /*!< FIFOEMPTY (Bit 20)                                    */
30780 #define DSI_INTREN_FIFOEMPTY_Msk          (0x100000UL)              /*!< FIFOEMPTY (Bitfield-Mask: 0x01)                       */
30781 #define DSI_INTREN_LOWC_Pos               (19UL)                    /*!< LOWC (Bit 19)                                         */
30782 #define DSI_INTREN_LOWC_Msk               (0x80000UL)               /*!< LOWC (Bitfield-Mask: 0x01)                            */
30783 #define DSI_INTREN_HIGHC_Pos              (18UL)                    /*!< HIGHC (Bit 18)                                        */
30784 #define DSI_INTREN_HIGHC_Msk              (0x40000UL)               /*!< HIGHC (Bitfield-Mask: 0x01)                           */
30785 #define DSI_INTREN_TxDSIV_Pos             (17UL)                    /*!< TxDSIV (Bit 17)                                       */
30786 #define DSI_INTREN_TxDSIV_Msk             (0x20000UL)               /*!< TxDSIV (Bitfield-Mask: 0x01)                          */
30787 #define DSI_INTREN_TxDSID_Pos             (16UL)                    /*!< TxDSID (Bit 16)                                       */
30788 #define DSI_INTREN_TxDSID_Msk             (0x10000UL)               /*!< TxDSID (Bitfield-Mask: 0x01)                          */
30789 #define DSI_INTREN_TXCHCKSUM_Pos          (15UL)                    /*!< TXCHCKSUM (Bit 15)                                    */
30790 #define DSI_INTREN_TXCHCKSUM_Msk          (0x8000UL)                /*!< TXCHCKSUM (Bitfield-Mask: 0x01)                       */
30791 #define DSI_INTREN_TxECCM_Pos             (14UL)                    /*!< TxECCM (Bit 14)                                       */
30792 #define DSI_INTREN_TxECCM_Msk             (0x4000UL)                /*!< TxECCM (Bitfield-Mask: 0x01)                          */
30793 #define DSI_INTREN_TxECCS_Pos             (13UL)                    /*!< TxECCS (Bit 13)                                       */
30794 #define DSI_INTREN_TxECCS_Msk             (0x2000UL)                /*!< TxECCS (Bitfield-Mask: 0x01)                          */
30795 #define DSI_INTREN_TxFalseCntrl_Pos       (12UL)                    /*!< TxFalseCntrl (Bit 12)                                 */
30796 #define DSI_INTREN_TxFalseCntrl_Msk       (0x1000UL)                /*!< TxFalseCntrl (Bitfield-Mask: 0x01)                    */
30797 #define DSI_INTREN_RxDSIV_Pos             (11UL)                    /*!< RxDSIV (Bit 11)                                       */
30798 #define DSI_INTREN_RxDSIV_Msk             (0x800UL)                 /*!< RxDSIV (Bitfield-Mask: 0x01)                          */
30799 #define DSI_INTREN_RxDSIData_Pos          (10UL)                    /*!< RxDSIData (Bit 10)                                    */
30800 #define DSI_INTREN_RxDSIData_Msk          (0x400UL)                 /*!< RxDSIData (Bitfield-Mask: 0x01)                       */
30801 #define DSI_INTREN_RXCHECKSUM_Pos         (9UL)                     /*!< RXCHECKSUM (Bit 9)                                    */
30802 #define DSI_INTREN_RXCHECKSUM_Msk         (0x200UL)                 /*!< RXCHECKSUM (Bitfield-Mask: 0x01)                      */
30803 #define DSI_INTREN_RXECCM_Pos             (8UL)                     /*!< RXECCM (Bit 8)                                        */
30804 #define DSI_INTREN_RXECCM_Msk             (0x100UL)                 /*!< RXECCM (Bitfield-Mask: 0x01)                          */
30805 #define DSI_INTREN_RXECCS_Pos             (7UL)                     /*!< RXECCS (Bit 7)                                        */
30806 #define DSI_INTREN_RXECCS_Msk             (0x80UL)                  /*!< RXECCS (Bitfield-Mask: 0x01)                          */
30807 #define DSI_INTREN_RXFALSE_Pos            (6UL)                     /*!< RXFALSE (Bit 6)                                       */
30808 #define DSI_INTREN_RXFALSE_Msk            (0x40UL)                  /*!< RXFALSE (Bitfield-Mask: 0x01)                         */
30809 #define DSI_INTREN_RXPERIPHRCVTOE_Pos     (5UL)                     /*!< RXPERIPHRCVTOE (Bit 5)                                */
30810 #define DSI_INTREN_RXPERIPHRCVTOE_Msk     (0x20UL)                  /*!< RXPERIPHRCVTOE (Bitfield-Mask: 0x01)                  */
30811 #define DSI_INTREN_RXLPTXSYNCERR_Pos      (4UL)                     /*!< RXLPTXSYNCERR (Bit 4)                                 */
30812 #define DSI_INTREN_RXLPTXSYNCERR_Msk      (0x10UL)                  /*!< RXLPTXSYNCERR (Bitfield-Mask: 0x01)                   */
30813 #define DSI_INTREN_RXESCPMDETRYERR_Pos    (3UL)                     /*!< RXESCPMDETRYERR (Bit 3)                               */
30814 #define DSI_INTREN_RXESCPMDETRYERR_Msk    (0x8UL)                   /*!< RXESCPMDETRYERR (Bitfield-Mask: 0x01)                 */
30815 #define DSI_INTREN_RXEOTSYNCRR_Pos        (2UL)                     /*!< RXEOTSYNCRR (Bit 2)                                   */
30816 #define DSI_INTREN_RXEOTSYNCRR_Msk        (0x4UL)                   /*!< RXEOTSYNCRR (Bitfield-Mask: 0x01)                     */
30817 #define DSI_INTREN_RXSOTSYNCERROR_Pos     (1UL)                     /*!< RXSOTSYNCERROR (Bit 1)                                */
30818 #define DSI_INTREN_RXSOTSYNCERROR_Msk     (0x2UL)                   /*!< RXSOTSYNCERROR (Bitfield-Mask: 0x01)                  */
30819 #define DSI_INTREN_RXSOTERROR_Pos         (0UL)                     /*!< RXSOTERROR (Bit 0)                                    */
30820 #define DSI_INTREN_RXSOTERROR_Msk         (0x1UL)                   /*!< RXSOTERROR (Bitfield-Mask: 0x01)                      */
30821 /* ======================================================  DSIFUNCPRG  ======================================================= */
30822 #define DSI_DSIFUNCPRG_REGNAME_Pos        (13UL)                    /*!< REGNAME (Bit 13)                                      */
30823 #define DSI_DSIFUNCPRG_REGNAME_Msk        (0xe000UL)                /*!< REGNAME (Bitfield-Mask: 0x07)                         */
30824 #define DSI_DSIFUNCPRG_SUPCOLVIDMODE_Pos  (7UL)                     /*!< SUPCOLVIDMODE (Bit 7)                                 */
30825 #define DSI_DSIFUNCPRG_SUPCOLVIDMODE_Msk  (0x380UL)                 /*!< SUPCOLVIDMODE (Bitfield-Mask: 0x07)                   */
30826 #define DSI_DSIFUNCPRG_CHNUMCMODE_Pos     (5UL)                     /*!< CHNUMCMODE (Bit 5)                                    */
30827 #define DSI_DSIFUNCPRG_CHNUMCMODE_Msk     (0x60UL)                  /*!< CHNUMCMODE (Bitfield-Mask: 0x03)                      */
30828 #define DSI_DSIFUNCPRG_CHNUMVM_Pos        (3UL)                     /*!< CHNUMVM (Bit 3)                                       */
30829 #define DSI_DSIFUNCPRG_CHNUMVM_Msk        (0x18UL)                  /*!< CHNUMVM (Bitfield-Mask: 0x03)                         */
30830 #define DSI_DSIFUNCPRG_DATALANES_Pos      (0UL)                     /*!< DATALANES (Bit 0)                                     */
30831 #define DSI_DSIFUNCPRG_DATALANES_Msk      (0x7UL)                   /*!< DATALANES (Bitfield-Mask: 0x07)                       */
30832 /* ======================================================  HSTXTIMEOUT  ====================================================== */
30833 #define DSI_HSTXTIMEOUT_MAXDURTOCNT_Pos   (0UL)                     /*!< MAXDURTOCNT (Bit 0)                                   */
30834 #define DSI_HSTXTIMEOUT_MAXDURTOCNT_Msk   (0xffffffUL)              /*!< MAXDURTOCNT (Bitfield-Mask: 0xffffff)                 */
30835 /* ========================================================  LPRXTO  ========================================================= */
30836 #define DSI_LPRXTO_TOCHKRVS_Pos           (0UL)                     /*!< TOCHKRVS (Bit 0)                                      */
30837 #define DSI_LPRXTO_TOCHKRVS_Msk           (0xffffffUL)              /*!< TOCHKRVS (Bitfield-Mask: 0xffffff)                    */
30838 /* ======================================================  TURNARNDTO  ======================================================= */
30839 #define DSI_TURNARNDTO_TIMOUT_Pos         (0UL)                     /*!< TIMOUT (Bit 0)                                        */
30840 #define DSI_TURNARNDTO_TIMOUT_Msk         (0x3fUL)                  /*!< TIMOUT (Bitfield-Mask: 0x3f)                          */
30841 /* ===================================================  DEVICERESETTIMER  ==================================================== */
30842 #define DSI_DEVICERESETTIMER_TIMOUT_Pos   (0UL)                     /*!< TIMOUT (Bit 0)                                        */
30843 #define DSI_DEVICERESETTIMER_TIMOUT_Msk   (0xffffUL)                /*!< TIMOUT (Bitfield-Mask: 0xffff)                        */
30844 /* =====================================================  DPIRESOLUTION  ===================================================== */
30845 #define DSI_DPIRESOLUTION_DPIRESOLUTION_Pos (0UL)                   /*!< DPIRESOLUTION (Bit 0)                                 */
30846 #define DSI_DPIRESOLUTION_DPIRESOLUTION_Msk (0xffffffffUL)          /*!< DPIRESOLUTION (Bitfield-Mask: 0xffffffff)             */
30847 /* =======================================================  HSYNCCNT  ======================================================== */
30848 #define DSI_HSYNCCNT_HORZCNT_Pos          (0UL)                     /*!< HORZCNT (Bit 0)                                       */
30849 #define DSI_HSYNCCNT_HORZCNT_Msk          (0xffffUL)                /*!< HORZCNT (Bitfield-Mask: 0xffff)                       */
30850 /* ====================================================  HORIZBKPORCHCNT  ==================================================== */
30851 #define DSI_HORIZBKPORCHCNT_HORZBKPCNT_Pos (0UL)                    /*!< HORZBKPCNT (Bit 0)                                    */
30852 #define DSI_HORIZBKPORCHCNT_HORZBKPCNT_Msk (0xffffUL)               /*!< HORZBKPCNT (Bitfield-Mask: 0xffff)                    */
30853 /* ====================================================  HORIZFPORCHCNT  ===================================================== */
30854 #define DSI_HORIZFPORCHCNT_HORZFTPCNT_Pos (0UL)                     /*!< HORZFTPCNT (Bit 0)                                    */
30855 #define DSI_HORIZFPORCHCNT_HORZFTPCNT_Msk (0xffffUL)                /*!< HORZFTPCNT (Bitfield-Mask: 0xffff)                    */
30856 /* ===================================================  HORZACTIVEAREACNT  =================================================== */
30857 #define DSI_HORZACTIVEAREACNT_HORACTCNT_Pos (0UL)                   /*!< HORACTCNT (Bit 0)                                     */
30858 #define DSI_HORZACTIVEAREACNT_HORACTCNT_Msk (0xffffUL)              /*!< HORACTCNT (Bitfield-Mask: 0xffff)                     */
30859 /* =======================================================  VSYNCCNT  ======================================================== */
30860 #define DSI_VSYNCCNT_VSC_Pos              (0UL)                     /*!< VSC (Bit 0)                                           */
30861 #define DSI_VSYNCCNT_VSC_Msk              (0xffffUL)                /*!< VSC (Bitfield-Mask: 0xffff)                           */
30862 /* ====================================================  VERTBKPORCHCNT  ===================================================== */
30863 #define DSI_VERTBKPORCHCNT_VBPSC_Pos      (0UL)                     /*!< VBPSC (Bit 0)                                         */
30864 #define DSI_VERTBKPORCHCNT_VBPSC_Msk      (0xffffUL)                /*!< VBPSC (Bitfield-Mask: 0xffff)                         */
30865 /* =====================================================  VERTFPORCHCNT  ===================================================== */
30866 #define DSI_VERTFPORCHCNT_VFPSC_Pos       (0UL)                     /*!< VFPSC (Bit 0)                                         */
30867 #define DSI_VERTFPORCHCNT_VFPSC_Msk       (0xffffUL)                /*!< VFPSC (Bitfield-Mask: 0xffff)                         */
30868 /* ===================================================  DATALANEHILOSWCNT  =================================================== */
30869 #define DSI_DATALANEHILOSWCNT_DATALHLSWCNT_Pos (0UL)                /*!< DATALHLSWCNT (Bit 0)                                  */
30870 #define DSI_DATALANEHILOSWCNT_DATALHLSWCNT_Msk (0xffffUL)           /*!< DATALHLSWCNT (Bitfield-Mask: 0xffff)                  */
30871 /* ==========================================================  DPI  ========================================================== */
30872 #define DSI_DPI_COLORMODEOFF_Pos          (3UL)                     /*!< COLORMODEOFF (Bit 3)                                  */
30873 #define DSI_DPI_COLORMODEOFF_Msk          (0x8UL)                   /*!< COLORMODEOFF (Bitfield-Mask: 0x01)                    */
30874 #define DSI_DPI_COLOR_Pos                 (2UL)                     /*!< COLOR (Bit 2)                                         */
30875 #define DSI_DPI_COLOR_Msk                 (0x4UL)                   /*!< COLOR (Bitfield-Mask: 0x01)                           */
30876 #define DSI_DPI_TURNON1_Pos               (1UL)                     /*!< TURNON1 (Bit 1)                                       */
30877 #define DSI_DPI_TURNON1_Msk               (0x2UL)                   /*!< TURNON1 (Bitfield-Mask: 0x01)                         */
30878 #define DSI_DPI_SHUTDOWN_Pos              (0UL)                     /*!< SHUTDOWN (Bit 0)                                      */
30879 #define DSI_DPI_SHUTDOWN_Msk              (0x1UL)                   /*!< SHUTDOWN (Bitfield-Mask: 0x01)                        */
30880 /* ======================================================  PLLLOCKCNT  ======================================================= */
30881 #define DSI_PLLLOCKCNT_PLLCNTVAL_Pos      (0UL)                     /*!< PLLCNTVAL (Bit 0)                                     */
30882 #define DSI_PLLLOCKCNT_PLLCNTVAL_Msk      (0xffffUL)                /*!< PLLCNTVAL (Bitfield-Mask: 0xffff)                     */
30883 /* ========================================================  INITCNT  ======================================================== */
30884 #define DSI_INITCNT_MSTR_Pos              (0UL)                     /*!< MSTR (Bit 0)                                          */
30885 #define DSI_INITCNT_MSTR_Msk              (0xffffUL)                /*!< MSTR (Bitfield-Mask: 0xffff)                          */
30886 /* =====================================================  MAXRETPACSZE  ====================================================== */
30887 #define DSI_MAXRETPACSZE_HSLP_Pos         (15UL)                    /*!< HSLP (Bit 15)                                         */
30888 #define DSI_MAXRETPACSZE_HSLP_Msk         (0x8000UL)                /*!< HSLP (Bitfield-Mask: 0x01)                            */
30889 #define DSI_MAXRETPACSZE_COUNTVAL_Pos     (0UL)                     /*!< COUNTVAL (Bit 0)                                      */
30890 #define DSI_MAXRETPACSZE_COUNTVAL_Msk     (0x7ffUL)                 /*!< COUNTVAL (Bitfield-Mask: 0x7ff)                       */
30891 /* =====================================================  VIDEOMODEFMT  ====================================================== */
30892 #define DSI_VIDEOMODEFMT_VIDEMDFMT_Pos    (0UL)                     /*!< VIDEMDFMT (Bit 0)                                     */
30893 #define DSI_VIDEOMODEFMT_VIDEMDFMT_Msk    (0x3UL)                   /*!< VIDEMDFMT (Bitfield-Mask: 0x03)                       */
30894 /* ========================================================  CLKEOT  ========================================================= */
30895 #define DSI_CLKEOT_BTA_Pos                (2UL)                     /*!< BTA (Bit 2)                                           */
30896 #define DSI_CLKEOT_BTA_Msk                (0x4UL)                   /*!< BTA (Bitfield-Mask: 0x01)                             */
30897 #define DSI_CLKEOT_CLOCK_Pos              (1UL)                     /*!< CLOCK (Bit 1)                                         */
30898 #define DSI_CLKEOT_CLOCK_Msk              (0x2UL)                   /*!< CLOCK (Bitfield-Mask: 0x01)                           */
30899 #define DSI_CLKEOT_EOT_Pos                (0UL)                     /*!< EOT (Bit 0)                                           */
30900 #define DSI_CLKEOT_EOT_Msk                (0x1UL)                   /*!< EOT (Bitfield-Mask: 0x01)                             */
30901 /* =======================================================  POLARITY  ======================================================== */
30902 #define DSI_POLARITY_PBITS_Pos            (0UL)                     /*!< PBITS (Bit 0)                                         */
30903 #define DSI_POLARITY_PBITS_Msk            (0xfUL)                   /*!< PBITS (Bitfield-Mask: 0x0f)                           */
30904 /* ======================================================  CLKLANESWT  ======================================================= */
30905 #define DSI_CLKLANESWT_LOWPWR2HI_Pos      (16UL)                    /*!< LOWPWR2HI (Bit 16)                                    */
30906 #define DSI_CLKLANESWT_LOWPWR2HI_Msk      (0xffff0000UL)            /*!< LOWPWR2HI (Bitfield-Mask: 0xffff)                     */
30907 #define DSI_CLKLANESWT_HISPLPSW_Pos       (0UL)                     /*!< HISPLPSW (Bit 0)                                      */
30908 #define DSI_CLKLANESWT_HISPLPSW_Msk       (0xffffUL)                /*!< HISPLPSW (Bitfield-Mask: 0xffff)                      */
30909 /* =======================================================  LPBYTECLK  ======================================================= */
30910 #define DSI_LPBYTECLK_VALBYTECLK_Pos      (0UL)                     /*!< VALBYTECLK (Bit 0)                                    */
30911 #define DSI_LPBYTECLK_VALBYTECLK_Msk      (0xffffUL)                /*!< VALBYTECLK (Bitfield-Mask: 0xffff)                    */
30912 /* =======================================================  DPHYPARAM  ======================================================= */
30913 #define DSI_DPHYPARAM_HSEXIT_Pos          (24UL)                    /*!< HSEXIT (Bit 24)                                       */
30914 #define DSI_DPHYPARAM_HSEXIT_Msk          (0xff000000UL)            /*!< HSEXIT (Bitfield-Mask: 0xff)                          */
30915 #define DSI_DPHYPARAM_HSTRAIL_Pos         (16UL)                    /*!< HSTRAIL (Bit 16)                                      */
30916 #define DSI_DPHYPARAM_HSTRAIL_Msk         (0xff0000UL)              /*!< HSTRAIL (Bitfield-Mask: 0xff)                         */
30917 #define DSI_DPHYPARAM_HSZERO_Pos          (8UL)                     /*!< HSZERO (Bit 8)                                        */
30918 #define DSI_DPHYPARAM_HSZERO_Msk          (0xff00UL)                /*!< HSZERO (Bitfield-Mask: 0xff)                          */
30919 #define DSI_DPHYPARAM_HSPREP_Pos          (0UL)                     /*!< HSPREP (Bit 0)                                        */
30920 #define DSI_DPHYPARAM_HSPREP_Msk          (0xffUL)                  /*!< HSPREP (Bitfield-Mask: 0xff)                          */
30921 /* ====================================================  CLKLANETIMPARM  ===================================================== */
30922 #define DSI_CLKLANETIMPARM_HSEXIT_Pos     (24UL)                    /*!< HSEXIT (Bit 24)                                       */
30923 #define DSI_CLKLANETIMPARM_HSEXIT_Msk     (0xff000000UL)            /*!< HSEXIT (Bitfield-Mask: 0xff)                          */
30924 #define DSI_CLKLANETIMPARM_HSTRAIL_Pos    (16UL)                    /*!< HSTRAIL (Bit 16)                                      */
30925 #define DSI_CLKLANETIMPARM_HSTRAIL_Msk    (0xff0000UL)              /*!< HSTRAIL (Bitfield-Mask: 0xff)                         */
30926 #define DSI_CLKLANETIMPARM_HSZERO_Pos     (8UL)                     /*!< HSZERO (Bit 8)                                        */
30927 #define DSI_CLKLANETIMPARM_HSZERO_Msk     (0xff00UL)                /*!< HSZERO (Bitfield-Mask: 0xff)                          */
30928 #define DSI_CLKLANETIMPARM_HSPREP_Pos     (0UL)                     /*!< HSPREP (Bit 0)                                        */
30929 #define DSI_CLKLANETIMPARM_HSPREP_Msk     (0xffUL)                  /*!< HSPREP (Bitfield-Mask: 0xff)                          */
30930 /* =======================================================  RSTENBDFE  ======================================================= */
30931 #define DSI_RSTENBDFE_ENABLE_Pos          (0UL)                     /*!< ENABLE (Bit 0)                                        */
30932 #define DSI_RSTENBDFE_ENABLE_Msk          (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
30933 /* =======================================================  AFETRIM0  ======================================================== */
30934 #define DSI_AFETRIM0_AFETRIM0_Pos         (0UL)                     /*!< AFETRIM0 (Bit 0)                                      */
30935 #define DSI_AFETRIM0_AFETRIM0_Msk         (0xffffffffUL)            /*!< AFETRIM0 (Bitfield-Mask: 0xffffffff)                  */
30936 /* =======================================================  AFETRIM1  ======================================================== */
30937 #define DSI_AFETRIM1_AFETRIM1_Pos         (0UL)                     /*!< AFETRIM1 (Bit 0)                                      */
30938 #define DSI_AFETRIM1_AFETRIM1_Msk         (0xffffffffUL)            /*!< AFETRIM1 (Bitfield-Mask: 0xffffffff)                  */
30939 /* =======================================================  AFETRIM2  ======================================================== */
30940 #define DSI_AFETRIM2_AFETRIM2_Pos         (0UL)                     /*!< AFETRIM2 (Bit 0)                                      */
30941 #define DSI_AFETRIM2_AFETRIM2_Msk         (0xffffffffUL)            /*!< AFETRIM2 (Bitfield-Mask: 0xffffffff)                  */
30942 /* =======================================================  AFETRIM3  ======================================================== */
30943 #define DSI_AFETRIM3_AFETRIM3_Pos         (0UL)                     /*!< AFETRIM3 (Bit 0)                                      */
30944 #define DSI_AFETRIM3_AFETRIM3_Msk         (0xffffffffUL)            /*!< AFETRIM3 (Bitfield-Mask: 0xffffffff)                  */
30945 /* =====================================================  ERRORAUTORCOV  ===================================================== */
30946 #define DSI_ERRORAUTORCOV_LPRXTIMEOUTCLR_Pos (5UL)                  /*!< LPRXTIMEOUTCLR (Bit 5)                                */
30947 #define DSI_ERRORAUTORCOV_LPRXTIMEOUTCLR_Msk (0x20UL)               /*!< LPRXTIMEOUTCLR (Bitfield-Mask: 0x01)                  */
30948 #define DSI_ERRORAUTORCOV_HSRXTIMEOUTCLR_Pos (4UL)                  /*!< HSRXTIMEOUTCLR (Bit 4)                                */
30949 #define DSI_ERRORAUTORCOV_HSRXTIMEOUTCLR_Msk (0x10UL)               /*!< HSRXTIMEOUTCLR (Bitfield-Mask: 0x01)                  */
30950 #define DSI_ERRORAUTORCOV_LOCONTCLR_Pos   (3UL)                     /*!< LOCONTCLR (Bit 3)                                     */
30951 #define DSI_ERRORAUTORCOV_LOCONTCLR_Msk   (0x8UL)                   /*!< LOCONTCLR (Bitfield-Mask: 0x01)                       */
30952 #define DSI_ERRORAUTORCOV_HICONTCLR_Pos   (2UL)                     /*!< HICONTCLR (Bit 2)                                     */
30953 #define DSI_ERRORAUTORCOV_HICONTCLR_Msk   (0x4UL)                   /*!< HICONTCLR (Bitfield-Mask: 0x01)                       */
30954 #define DSI_ERRORAUTORCOV_INVLDDTCLR_Pos  (1UL)                     /*!< INVLDDTCLR (Bit 1)                                    */
30955 #define DSI_ERRORAUTORCOV_INVLDDTCLR_Msk  (0x2UL)                   /*!< INVLDDTCLR (Bitfield-Mask: 0x01)                      */
30956 #define DSI_ERRORAUTORCOV_ECCMULERRCLR_Pos (0UL)                    /*!< ECCMULERRCLR (Bit 0)                                  */
30957 #define DSI_ERRORAUTORCOV_ECCMULERRCLR_Msk (0x1UL)                  /*!< ECCMULERRCLR (Bitfield-Mask: 0x01)                    */
30958 /* ====================================================  MIPIDIRDPIDIFF  ===================================================== */
30959 #define DSI_MIPIDIRDPIDIFF_DPIDIFF_Pos    (16UL)                    /*!< DPIDIFF (Bit 16)                                      */
30960 #define DSI_MIPIDIRDPIDIFF_DPIDIFF_Msk    (0xffff0000UL)            /*!< DPIDIFF (Bitfield-Mask: 0xffff)                       */
30961 #define DSI_MIPIDIRDPIDIFF_DPIHIGH_Pos    (15UL)                    /*!< DPIHIGH (Bit 15)                                      */
30962 #define DSI_MIPIDIRDPIDIFF_DPIHIGH_Msk    (0x8000UL)                /*!< DPIHIGH (Bitfield-Mask: 0x01)                         */
30963 #define DSI_MIPIDIRDPIDIFF_MIPIDIR_Pos    (0UL)                     /*!< MIPIDIR (Bit 0)                                       */
30964 #define DSI_MIPIDIRDPIDIFF_MIPIDIR_Msk    (0x1UL)                   /*!< MIPIDIR (Bitfield-Mask: 0x01)                         */
30965 /* ====================================================  DATALANEPOLSWAP  ==================================================== */
30966 #define DSI_DATALANEPOLSWAP_DATALNPOLSWAP_Pos (0UL)                 /*!< DATALNPOLSWAP (Bit 0)                                 */
30967 #define DSI_DATALANEPOLSWAP_DATALNPOLSWAP_Msk (0xfUL)               /*!< DATALNPOLSWAP (Bitfield-Mask: 0x0f)                   */
30968 
30969 
30970 /* =========================================================================================================================== */
30971 /* ================                                            DSP                                            ================ */
30972 /* =========================================================================================================================== */
30973 
30974 /* ========================================================  MUTEX0  ========================================================= */
30975 #define DSP_MUTEX0_MUTEX0_Pos             (0UL)                     /*!< MUTEX0 (Bit 0)                                        */
30976 #define DSP_MUTEX0_MUTEX0_Msk             (0x7UL)                   /*!< MUTEX0 (Bitfield-Mask: 0x07)                          */
30977 /* ========================================================  MUTEX1  ========================================================= */
30978 #define DSP_MUTEX1_MUTEX1_Pos             (0UL)                     /*!< MUTEX1 (Bit 0)                                        */
30979 #define DSP_MUTEX1_MUTEX1_Msk             (0x7UL)                   /*!< MUTEX1 (Bitfield-Mask: 0x07)                          */
30980 /* ========================================================  MUTEX2  ========================================================= */
30981 #define DSP_MUTEX2_MUTEX2_Pos             (0UL)                     /*!< MUTEX2 (Bit 0)                                        */
30982 #define DSP_MUTEX2_MUTEX2_Msk             (0x7UL)                   /*!< MUTEX2 (Bitfield-Mask: 0x07)                          */
30983 /* ========================================================  MUTEX3  ========================================================= */
30984 #define DSP_MUTEX3_MUTEX3_Pos             (0UL)                     /*!< MUTEX3 (Bit 0)                                        */
30985 #define DSP_MUTEX3_MUTEX3_Msk             (0x7UL)                   /*!< MUTEX3 (Bitfield-Mask: 0x07)                          */
30986 /* ========================================================  MUTEX4  ========================================================= */
30987 #define DSP_MUTEX4_MUTEX4_Pos             (0UL)                     /*!< MUTEX4 (Bit 0)                                        */
30988 #define DSP_MUTEX4_MUTEX4_Msk             (0x7UL)                   /*!< MUTEX4 (Bitfield-Mask: 0x07)                          */
30989 /* ========================================================  MUTEX5  ========================================================= */
30990 #define DSP_MUTEX5_MUTEX5_Pos             (0UL)                     /*!< MUTEX5 (Bit 0)                                        */
30991 #define DSP_MUTEX5_MUTEX5_Msk             (0x7UL)                   /*!< MUTEX5 (Bitfield-Mask: 0x07)                          */
30992 /* ========================================================  MUTEX6  ========================================================= */
30993 #define DSP_MUTEX6_MUTEX6_Pos             (0UL)                     /*!< MUTEX6 (Bit 0)                                        */
30994 #define DSP_MUTEX6_MUTEX6_Msk             (0x7UL)                   /*!< MUTEX6 (Bitfield-Mask: 0x07)                          */
30995 /* ========================================================  MUTEX7  ========================================================= */
30996 #define DSP_MUTEX7_MUTEX7_Pos             (0UL)                     /*!< MUTEX7 (Bit 0)                                        */
30997 #define DSP_MUTEX7_MUTEX7_Msk             (0x7UL)                   /*!< MUTEX7 (Bitfield-Mask: 0x07)                          */
30998 /* ======================================================  CPUMBINTSET  ====================================================== */
30999 #define DSP_CPUMBINTSET_CPUMBINTSET_Pos   (0UL)                     /*!< CPUMBINTSET (Bit 0)                                   */
31000 #define DSP_CPUMBINTSET_CPUMBINTSET_Msk   (0xffffffffUL)            /*!< CPUMBINTSET (Bitfield-Mask: 0xffffffff)               */
31001 /* ======================================================  CPUMBINTCLR  ====================================================== */
31002 #define DSP_CPUMBINTCLR_CPUMBINTCLR_Pos   (0UL)                     /*!< CPUMBINTCLR (Bit 0)                                   */
31003 #define DSP_CPUMBINTCLR_CPUMBINTCLR_Msk   (0xffffffffUL)            /*!< CPUMBINTCLR (Bitfield-Mask: 0xffffffff)               */
31004 /* =====================================================  CPUMBINTSTAT  ====================================================== */
31005 #define DSP_CPUMBINTSTAT_CPUMBINTSTAT_Pos (0UL)                     /*!< CPUMBINTSTAT (Bit 0)                                  */
31006 #define DSP_CPUMBINTSTAT_CPUMBINTSTAT_Msk (0xffffffffUL)            /*!< CPUMBINTSTAT (Bitfield-Mask: 0xffffffff)              */
31007 /* =====================================================  CPUCPUMBDATA  ====================================================== */
31008 #define DSP_CPUCPUMBDATA_CPUCPUMBDATA_Pos (0UL)                     /*!< CPUCPUMBDATA (Bit 0)                                  */
31009 #define DSP_CPUCPUMBDATA_CPUCPUMBDATA_Msk (0xffffffffUL)            /*!< CPUCPUMBDATA (Bitfield-Mask: 0xffffffff)              */
31010 /* =====================================================  DSP0CPUMBDATA  ===================================================== */
31011 #define DSP_DSP0CPUMBDATA_DSP0CPUMBDATA_Pos (0UL)                   /*!< DSP0CPUMBDATA (Bit 0)                                 */
31012 #define DSP_DSP0CPUMBDATA_DSP0CPUMBDATA_Msk (0xffffffffUL)          /*!< DSP0CPUMBDATA (Bitfield-Mask: 0xffffffff)             */
31013 /* =====================================================  DSP1CPUMBDATA  ===================================================== */
31014 #define DSP_DSP1CPUMBDATA_DSP1CPUMBDATA_Pos (0UL)                   /*!< DSP1CPUMBDATA (Bit 0)                                 */
31015 #define DSP_DSP1CPUMBDATA_DSP1CPUMBDATA_Msk (0xffffffffUL)          /*!< DSP1CPUMBDATA (Bitfield-Mask: 0xffffffff)             */
31016 /* =====================================================  DSP0MBINTSET  ====================================================== */
31017 #define DSP_DSP0MBINTSET_DSP0MBINTSET_Pos (0UL)                     /*!< DSP0MBINTSET (Bit 0)                                  */
31018 #define DSP_DSP0MBINTSET_DSP0MBINTSET_Msk (0xffffffffUL)            /*!< DSP0MBINTSET (Bitfield-Mask: 0xffffffff)              */
31019 /* =====================================================  DSP0MBINTCLR  ====================================================== */
31020 #define DSP_DSP0MBINTCLR_DSP0MBINTCLR_Pos (0UL)                     /*!< DSP0MBINTCLR (Bit 0)                                  */
31021 #define DSP_DSP0MBINTCLR_DSP0MBINTCLR_Msk (0xffffffffUL)            /*!< DSP0MBINTCLR (Bitfield-Mask: 0xffffffff)              */
31022 /* =====================================================  DSP0MBINTSTAT  ===================================================== */
31023 #define DSP_DSP0MBINTSTAT_DSP0MBINTSTAT_Pos (0UL)                   /*!< DSP0MBINTSTAT (Bit 0)                                 */
31024 #define DSP_DSP0MBINTSTAT_DSP0MBINTSTAT_Msk (0xffffffffUL)          /*!< DSP0MBINTSTAT (Bitfield-Mask: 0xffffffff)             */
31025 /* =====================================================  CPUDSP0MBDATA  ===================================================== */
31026 #define DSP_CPUDSP0MBDATA_CPUDSP0MBDATA_Pos (0UL)                   /*!< CPUDSP0MBDATA (Bit 0)                                 */
31027 #define DSP_CPUDSP0MBDATA_CPUDSP0MBDATA_Msk (0xffffffffUL)          /*!< CPUDSP0MBDATA (Bitfield-Mask: 0xffffffff)             */
31028 /* ====================================================  DSP0DSP0MBDATA  ===================================================== */
31029 #define DSP_DSP0DSP0MBDATA_DSP0DSP0MBDATA_Pos (0UL)                 /*!< DSP0DSP0MBDATA (Bit 0)                                */
31030 #define DSP_DSP0DSP0MBDATA_DSP0DSP0MBDATA_Msk (0xffffffffUL)        /*!< DSP0DSP0MBDATA (Bitfield-Mask: 0xffffffff)            */
31031 /* ====================================================  DSP1DSP0MBDATA  ===================================================== */
31032 #define DSP_DSP1DSP0MBDATA_DSP1DSP0MBDATA_Pos (0UL)                 /*!< DSP1DSP0MBDATA (Bit 0)                                */
31033 #define DSP_DSP1DSP0MBDATA_DSP1DSP0MBDATA_Msk (0xffffffffUL)        /*!< DSP1DSP0MBDATA (Bitfield-Mask: 0xffffffff)            */
31034 /* =====================================================  DSP1MBINTSET  ====================================================== */
31035 #define DSP_DSP1MBINTSET_DSP1MBINTSET_Pos (0UL)                     /*!< DSP1MBINTSET (Bit 0)                                  */
31036 #define DSP_DSP1MBINTSET_DSP1MBINTSET_Msk (0xffffffffUL)            /*!< DSP1MBINTSET (Bitfield-Mask: 0xffffffff)              */
31037 /* =====================================================  DSP1MBINTCLR  ====================================================== */
31038 #define DSP_DSP1MBINTCLR_DSP1MBINTCLR_Pos (0UL)                     /*!< DSP1MBINTCLR (Bit 0)                                  */
31039 #define DSP_DSP1MBINTCLR_DSP1MBINTCLR_Msk (0xffffffffUL)            /*!< DSP1MBINTCLR (Bitfield-Mask: 0xffffffff)              */
31040 /* =====================================================  DSP1MBINTSTAT  ===================================================== */
31041 #define DSP_DSP1MBINTSTAT_DSP1MBINTSTAT_Pos (0UL)                   /*!< DSP1MBINTSTAT (Bit 0)                                 */
31042 #define DSP_DSP1MBINTSTAT_DSP1MBINTSTAT_Msk (0xffffffffUL)          /*!< DSP1MBINTSTAT (Bitfield-Mask: 0xffffffff)             */
31043 /* =====================================================  CPUDSP1MBDATA  ===================================================== */
31044 #define DSP_CPUDSP1MBDATA_CPUDSP1MBDATA_Pos (0UL)                   /*!< CPUDSP1MBDATA (Bit 0)                                 */
31045 #define DSP_CPUDSP1MBDATA_CPUDSP1MBDATA_Msk (0xffffffffUL)          /*!< CPUDSP1MBDATA (Bitfield-Mask: 0xffffffff)             */
31046 /* ====================================================  DSP0DSP1MBDATA  ===================================================== */
31047 #define DSP_DSP0DSP1MBDATA_DSP0DSP1MBDATA_Pos (0UL)                 /*!< DSP0DSP1MBDATA (Bit 0)                                */
31048 #define DSP_DSP0DSP1MBDATA_DSP0DSP1MBDATA_Msk (0xffffffffUL)        /*!< DSP0DSP1MBDATA (Bitfield-Mask: 0xffffffff)            */
31049 /* ====================================================  DSP1DSP1MBDATA  ===================================================== */
31050 #define DSP_DSP1DSP1MBDATA_DSP1DSP1MBDATA_Pos (0UL)                 /*!< DSP1DSP1MBDATA (Bit 0)                                */
31051 #define DSP_DSP1DSP1MBDATA_DSP1DSP1MBDATA_Msk (0xffffffffUL)        /*!< DSP1DSP1MBDATA (Bitfield-Mask: 0xffffffff)            */
31052 /* ======================================================  DSP0CONTROL  ====================================================== */
31053 #define DSP_DSP0CONTROL_DSP0IDMAXTRIGSRC_Pos (8UL)                  /*!< DSP0IDMAXTRIGSRC (Bit 8)                              */
31054 #define DSP_DSP0CONTROL_DSP0IDMAXTRIGSRC_Msk (0x7fffff00UL)         /*!< DSP0IDMAXTRIGSRC (Bitfield-Mask: 0x7fffff)            */
31055 #define DSP_DSP0CONTROL_DSP0IDMATRIG_Pos  (4UL)                     /*!< DSP0IDMATRIG (Bit 4)                                  */
31056 #define DSP_DSP0CONTROL_DSP0IDMATRIG_Msk  (0x30UL)                  /*!< DSP0IDMATRIG (Bitfield-Mask: 0x03)                    */
31057 #define DSP_DSP0CONTROL_DSP0RUNSTALL_Pos  (3UL)                     /*!< DSP0RUNSTALL (Bit 3)                                  */
31058 #define DSP_DSP0CONTROL_DSP0RUNSTALL_Msk  (0x8UL)                   /*!< DSP0RUNSTALL (Bitfield-Mask: 0x01)                    */
31059 #define DSP_DSP0CONTROL_DSP0DRESET_Pos    (2UL)                     /*!< DSP0DRESET (Bit 2)                                    */
31060 #define DSP_DSP0CONTROL_DSP0DRESET_Msk    (0x4UL)                   /*!< DSP0DRESET (Bitfield-Mask: 0x01)                      */
31061 #define DSP_DSP0CONTROL_DSP0BRESET_Pos    (1UL)                     /*!< DSP0BRESET (Bit 1)                                    */
31062 #define DSP_DSP0CONTROL_DSP0BRESET_Msk    (0x2UL)                   /*!< DSP0BRESET (Bitfield-Mask: 0x01)                      */
31063 #define DSP_DSP0CONTROL_DSP0STATVECSEL_Pos (0UL)                    /*!< DSP0STATVECSEL (Bit 0)                                */
31064 #define DSP_DSP0CONTROL_DSP0STATVECSEL_Msk (0x1UL)                  /*!< DSP0STATVECSEL (Bitfield-Mask: 0x01)                  */
31065 /* =====================================================  DSP0RESETVEC  ====================================================== */
31066 #define DSP_DSP0RESETVEC_DSP0RESETVEC_Pos (0UL)                     /*!< DSP0RESETVEC (Bit 0)                                  */
31067 #define DSP_DSP0RESETVEC_DSP0RESETVEC_Msk (0xffffffffUL)            /*!< DSP0RESETVEC (Bitfield-Mask: 0xffffffff)              */
31068 /* ======================================================  DSP0IRQMASK  ====================================================== */
31069 #define DSP_DSP0IRQMASK_DSP0IRQMASK_Pos   (0UL)                     /*!< DSP0IRQMASK (Bit 0)                                   */
31070 #define DSP_DSP0IRQMASK_DSP0IRQMASK_Msk   (0x7fffffUL)              /*!< DSP0IRQMASK (Bitfield-Mask: 0x7fffff)                 */
31071 /* =====================================================  DSP0WAKEMASK  ====================================================== */
31072 #define DSP_DSP0WAKEMASK_DSP0WAKEMASK_Pos (0UL)                     /*!< DSP0WAKEMASK (Bit 0)                                  */
31073 #define DSP_DSP0WAKEMASK_DSP0WAKEMASK_Msk (0x7fffffUL)              /*!< DSP0WAKEMASK (Bitfield-Mask: 0x7fffff)                */
31074 /* ==================================================  DSP0RAWIRQSTAT31to0  ================================================== */
31075 #define DSP_DSP0RAWIRQSTAT31to0_DSP0RAWIRQSTAT31to0_Pos (0UL)       /*!< DSP0RAWIRQSTAT31to0 (Bit 0)                           */
31076 #define DSP_DSP0RAWIRQSTAT31to0_DSP0RAWIRQSTAT31to0_Msk (0xffffffffUL) /*!< DSP0RAWIRQSTAT31to0 (Bitfield-Mask: 0xffffffff)    */
31077 /* =================================================  DSP0RAWIRQSTAT63to32  ================================================== */
31078 #define DSP_DSP0RAWIRQSTAT63to32_DSP0RAWIRQSTAT63to32_Pos (0UL)     /*!< DSP0RAWIRQSTAT63to32 (Bit 0)                          */
31079 #define DSP_DSP0RAWIRQSTAT63to32_DSP0RAWIRQSTAT63to32_Msk (0xffffffffUL) /*!< DSP0RAWIRQSTAT63to32 (Bitfield-Mask: 0xffffffff) */
31080 /* =================================================  DSP0RAWIRQSTAT95to64  ================================================== */
31081 #define DSP_DSP0RAWIRQSTAT95to64_DSP0RAWIRQSTAT95to64_Pos (0UL)     /*!< DSP0RAWIRQSTAT95to64 (Bit 0)                          */
31082 #define DSP_DSP0RAWIRQSTAT95to64_DSP0RAWIRQSTAT95to64_Msk (0xffffffffUL) /*!< DSP0RAWIRQSTAT95to64 (Bitfield-Mask: 0xffffffff) */
31083 /* =====================================================  DSP0L2LVLINT  ====================================================== */
31084 #define DSP_DSP0L2LVLINT_DSP0L2LVLINT_Pos (0UL)                     /*!< DSP0L2LVLINT (Bit 0)                                  */
31085 #define DSP_DSP0L2LVLINT_DSP0L2LVLINT_Msk (0x7ffffUL)               /*!< DSP0L2LVLINT (Bitfield-Mask: 0x7ffff)                 */
31086 /* =====================================================  DSP0L3LVLINT  ====================================================== */
31087 #define DSP_DSP0L3LVLINT_DSP0L3LVLINT_Pos (0UL)                     /*!< DSP0L3LVLINT (Bit 0)                                  */
31088 #define DSP_DSP0L3LVLINT_DSP0L3LVLINT_Msk (0x7ffffUL)               /*!< DSP0L3LVLINT (Bitfield-Mask: 0x7ffff)                 */
31089 /* =====================================================  DSP0L4LVLINT  ====================================================== */
31090 #define DSP_DSP0L4LVLINT_DSP0L4LVLINT_Pos (0UL)                     /*!< DSP0L4LVLINT (Bit 0)                                  */
31091 #define DSP_DSP0L4LVLINT_DSP0L4LVLINT_Msk (0x7ffffUL)               /*!< DSP0L4LVLINT (Bitfield-Mask: 0x7ffff)                 */
31092 /* =====================================================  DSP0L5LVLINT  ====================================================== */
31093 #define DSP_DSP0L5LVLINT_DSP0L5LVLINT_Pos (0UL)                     /*!< DSP0L5LVLINT (Bit 0)                                  */
31094 #define DSP_DSP0L5LVLINT_DSP0L5LVLINT_Msk (0x7ffffUL)               /*!< DSP0L5LVLINT (Bitfield-Mask: 0x7ffff)                 */
31095 /* ====================================================  DSP0IDMATRIGCTL  ==================================================== */
31096 #define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGPULSE_Pos (4UL)             /*!< DSP0IDMATRIGPULSE (Bit 4)                             */
31097 #define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGPULSE_Msk (0x10UL)          /*!< DSP0IDMATRIGPULSE (Bitfield-Mask: 0x01)               */
31098 #define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGSTAT_Pos (0UL)              /*!< DSP0IDMATRIGSTAT (Bit 0)                              */
31099 #define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGSTAT_Msk (0x1UL)            /*!< DSP0IDMATRIGSTAT (Bitfield-Mask: 0x01)                */
31100 /* ==================================================  DSP0INTORMASK31TO0A  ================================================== */
31101 #define DSP_DSP0INTORMASK31TO0A_DSP0INTMCUIOORMASKA_Pos (0UL)       /*!< DSP0INTMCUIOORMASKA (Bit 0)                           */
31102 #define DSP_DSP0INTORMASK31TO0A_DSP0INTMCUIOORMASKA_Msk (0xffffffffUL) /*!< DSP0INTMCUIOORMASKA (Bitfield-Mask: 0xffffffff)    */
31103 /* =================================================  DSP0INTORMASK63TO32A  ================================================== */
31104 #define DSP_DSP0INTORMASK63TO32A_DSP0GPIOORMASKA_Pos (24UL)         /*!< DSP0GPIOORMASKA (Bit 24)                              */
31105 #define DSP_DSP0INTORMASK63TO32A_DSP0GPIOORMASKA_Msk (0x3f000000UL) /*!< DSP0GPIOORMASKA (Bitfield-Mask: 0x3f)                 */
31106 #define DSP_DSP0INTORMASK63TO32A_DSP0PDMORMASKA_Pos (16UL)          /*!< DSP0PDMORMASKA (Bit 16)                               */
31107 #define DSP_DSP0INTORMASK63TO32A_DSP0PDMORMASKA_Msk (0xf0000UL)     /*!< DSP0PDMORMASKA (Bitfield-Mask: 0x0f)                  */
31108 #define DSP_DSP0INTORMASK63TO32A_DSP0I2SORMASKA_Pos (12UL)          /*!< DSP0I2SORMASKA (Bit 12)                               */
31109 #define DSP_DSP0INTORMASK63TO32A_DSP0I2SORMASKA_Msk (0xf000UL)      /*!< DSP0I2SORMASKA (Bitfield-Mask: 0x0f)                  */
31110 #define DSP_DSP0INTORMASK63TO32A_DSP0TMRORMASKA_Pos (0UL)           /*!< DSP0TMRORMASKA (Bit 0)                                */
31111 #define DSP_DSP0INTORMASK63TO32A_DSP0TMRORMASKA_Msk (0x3ffUL)       /*!< DSP0TMRORMASKA (Bitfield-Mask: 0x3ff)                 */
31112 /* =================================================  DSP0INTORMASK95TO64A  ================================================== */
31113 #define DSP_DSP0INTORMASK95TO64A_DSP0MBINTORMASKA_Pos (0UL)         /*!< DSP0MBINTORMASKA (Bit 0)                              */
31114 #define DSP_DSP0INTORMASK95TO64A_DSP0MBINTORMASKA_Msk (0xffffffffUL) /*!< DSP0MBINTORMASKA (Bitfield-Mask: 0xffffffff)         */
31115 /* ==================================================  DSP0INTORMASK31to0B  ================================================== */
31116 #define DSP_DSP0INTORMASK31to0B_DSP0INTMCUIOORMASKB_Pos (0UL)       /*!< DSP0INTMCUIOORMASKB (Bit 0)                           */
31117 #define DSP_DSP0INTORMASK31to0B_DSP0INTMCUIOORMASKB_Msk (0xffffffffUL) /*!< DSP0INTMCUIOORMASKB (Bitfield-Mask: 0xffffffff)    */
31118 /* =================================================  DSP0INTORMASK63TO32B  ================================================== */
31119 #define DSP_DSP0INTORMASK63TO32B_DSP0GPIOORMASKB_Pos (24UL)         /*!< DSP0GPIOORMASKB (Bit 24)                              */
31120 #define DSP_DSP0INTORMASK63TO32B_DSP0GPIOORMASKB_Msk (0x3f000000UL) /*!< DSP0GPIOORMASKB (Bitfield-Mask: 0x3f)                 */
31121 #define DSP_DSP0INTORMASK63TO32B_DSP0PDMORMASKB_Pos (16UL)          /*!< DSP0PDMORMASKB (Bit 16)                               */
31122 #define DSP_DSP0INTORMASK63TO32B_DSP0PDMORMASKB_Msk (0xf0000UL)     /*!< DSP0PDMORMASKB (Bitfield-Mask: 0x0f)                  */
31123 #define DSP_DSP0INTORMASK63TO32B_DSP0I2SORMASKB_Pos (12UL)          /*!< DSP0I2SORMASKB (Bit 12)                               */
31124 #define DSP_DSP0INTORMASK63TO32B_DSP0I2SORMASKB_Msk (0xf000UL)      /*!< DSP0I2SORMASKB (Bitfield-Mask: 0x0f)                  */
31125 #define DSP_DSP0INTORMASK63TO32B_DSP0TMRORMASKB_Pos (0UL)           /*!< DSP0TMRORMASKB (Bit 0)                                */
31126 #define DSP_DSP0INTORMASK63TO32B_DSP0TMRORMASKB_Msk (0x3ffUL)       /*!< DSP0TMRORMASKB (Bitfield-Mask: 0x3ff)                 */
31127 /* =================================================  DSP0INTORMASK95TO64B  ================================================== */
31128 #define DSP_DSP0INTORMASK95TO64B_DSP0MBINTORMASKB_Pos (0UL)         /*!< DSP0MBINTORMASKB (Bit 0)                              */
31129 #define DSP_DSP0INTORMASK95TO64B_DSP0MBINTORMASKB_Msk (0xffffffffUL) /*!< DSP0MBINTORMASKB (Bitfield-Mask: 0xffffffff)         */
31130 /* ===================================================  DSP0INTENIRQ31TO0  =================================================== */
31131 #define DSP_DSP0INTENIRQ31TO0_DSP0INTENIRQ31TO0_Pos (0UL)           /*!< DSP0INTENIRQ31TO0 (Bit 0)                             */
31132 #define DSP_DSP0INTENIRQ31TO0_DSP0INTENIRQ31TO0_Msk (0xffffffffUL)  /*!< DSP0INTENIRQ31TO0 (Bitfield-Mask: 0xffffffff)         */
31133 /* ==================================================  DSP0INTENIRQ63TO32  =================================================== */
31134 #define DSP_DSP0INTENIRQ63TO32_DSP0INTENIRQ63TO32_Pos (0UL)         /*!< DSP0INTENIRQ63TO32 (Bit 0)                            */
31135 #define DSP_DSP0INTENIRQ63TO32_DSP0INTENIRQ63TO32_Msk (0xffffffffUL) /*!< DSP0INTENIRQ63TO32 (Bitfield-Mask: 0xffffffff)       */
31136 /* ==================================================  DSP0INTENIRQ95TO64  =================================================== */
31137 #define DSP_DSP0INTENIRQ95TO64_DSP0INTENIRQ95TO64_Pos (0UL)         /*!< DSP0INTENIRQ95TO64 (Bit 0)                            */
31138 #define DSP_DSP0INTENIRQ95TO64_DSP0INTENIRQ95TO64_Msk (0xffffffffUL) /*!< DSP0INTENIRQ95TO64 (Bitfield-Mask: 0xffffffff)       */
31139 /* ======================================================  DSP1CONTROL  ====================================================== */
31140 #define DSP_DSP1CONTROL_DSP1IDMAXTRIGSRC_Pos (8UL)                  /*!< DSP1IDMAXTRIGSRC (Bit 8)                              */
31141 #define DSP_DSP1CONTROL_DSP1IDMAXTRIGSRC_Msk (0x7fffff00UL)         /*!< DSP1IDMAXTRIGSRC (Bitfield-Mask: 0x7fffff)            */
31142 #define DSP_DSP1CONTROL_DSP1IDMATRIG_Pos  (4UL)                     /*!< DSP1IDMATRIG (Bit 4)                                  */
31143 #define DSP_DSP1CONTROL_DSP1IDMATRIG_Msk  (0x30UL)                  /*!< DSP1IDMATRIG (Bitfield-Mask: 0x03)                    */
31144 #define DSP_DSP1CONTROL_DSP1RUNSTALL_Pos  (3UL)                     /*!< DSP1RUNSTALL (Bit 3)                                  */
31145 #define DSP_DSP1CONTROL_DSP1RUNSTALL_Msk  (0x8UL)                   /*!< DSP1RUNSTALL (Bitfield-Mask: 0x01)                    */
31146 #define DSP_DSP1CONTROL_DSP1DRESET_Pos    (2UL)                     /*!< DSP1DRESET (Bit 2)                                    */
31147 #define DSP_DSP1CONTROL_DSP1DRESET_Msk    (0x4UL)                   /*!< DSP1DRESET (Bitfield-Mask: 0x01)                      */
31148 #define DSP_DSP1CONTROL_DSP1BRESET_Pos    (1UL)                     /*!< DSP1BRESET (Bit 1)                                    */
31149 #define DSP_DSP1CONTROL_DSP1BRESET_Msk    (0x2UL)                   /*!< DSP1BRESET (Bitfield-Mask: 0x01)                      */
31150 #define DSP_DSP1CONTROL_DSP1STATVECSEL_Pos (0UL)                    /*!< DSP1STATVECSEL (Bit 0)                                */
31151 #define DSP_DSP1CONTROL_DSP1STATVECSEL_Msk (0x1UL)                  /*!< DSP1STATVECSEL (Bitfield-Mask: 0x01)                  */
31152 /* =====================================================  DSP1RESETVEC  ====================================================== */
31153 #define DSP_DSP1RESETVEC_DSP1RESETVEC_Pos (0UL)                     /*!< DSP1RESETVEC (Bit 0)                                  */
31154 #define DSP_DSP1RESETVEC_DSP1RESETVEC_Msk (0xffffffffUL)            /*!< DSP1RESETVEC (Bitfield-Mask: 0xffffffff)              */
31155 /* ======================================================  DSP1IRQMASK  ====================================================== */
31156 #define DSP_DSP1IRQMASK_DSP1IRQMASK_Pos   (0UL)                     /*!< DSP1IRQMASK (Bit 0)                                   */
31157 #define DSP_DSP1IRQMASK_DSP1IRQMASK_Msk   (0x7fffffUL)              /*!< DSP1IRQMASK (Bitfield-Mask: 0x7fffff)                 */
31158 /* =====================================================  DSP1WAKEMASK  ====================================================== */
31159 #define DSP_DSP1WAKEMASK_DSP1WAKEMASK_Pos (0UL)                     /*!< DSP1WAKEMASK (Bit 0)                                  */
31160 #define DSP_DSP1WAKEMASK_DSP1WAKEMASK_Msk (0x7fffffUL)              /*!< DSP1WAKEMASK (Bitfield-Mask: 0x7fffff)                */
31161 /* ==================================================  DSP1RAWIRQSTAT31to0  ================================================== */
31162 #define DSP_DSP1RAWIRQSTAT31to0_DSP1RAWIRQSTAT31to0_Pos (0UL)       /*!< DSP1RAWIRQSTAT31to0 (Bit 0)                           */
31163 #define DSP_DSP1RAWIRQSTAT31to0_DSP1RAWIRQSTAT31to0_Msk (0xffffffffUL) /*!< DSP1RAWIRQSTAT31to0 (Bitfield-Mask: 0xffffffff)    */
31164 /* =================================================  DSP1RAWIRQSTAT63to32  ================================================== */
31165 #define DSP_DSP1RAWIRQSTAT63to32_DSP1RAWIRQSTAT63to32_Pos (0UL)     /*!< DSP1RAWIRQSTAT63to32 (Bit 0)                          */
31166 #define DSP_DSP1RAWIRQSTAT63to32_DSP1RAWIRQSTAT63to32_Msk (0xffffffffUL) /*!< DSP1RAWIRQSTAT63to32 (Bitfield-Mask: 0xffffffff) */
31167 /* =================================================  DSP1RAWIRQSTAT95to64  ================================================== */
31168 #define DSP_DSP1RAWIRQSTAT95to64_DSP1RAWIRQSTAT95to64_Pos (0UL)     /*!< DSP1RAWIRQSTAT95to64 (Bit 0)                          */
31169 #define DSP_DSP1RAWIRQSTAT95to64_DSP1RAWIRQSTAT95to64_Msk (0xffffffffUL) /*!< DSP1RAWIRQSTAT95to64 (Bitfield-Mask: 0xffffffff) */
31170 /* =====================================================  DSP1L2LVLINT  ====================================================== */
31171 #define DSP_DSP1L2LVLINT_DSP1L2LVLINT_Pos (0UL)                     /*!< DSP1L2LVLINT (Bit 0)                                  */
31172 #define DSP_DSP1L2LVLINT_DSP1L2LVLINT_Msk (0x7ffffUL)               /*!< DSP1L2LVLINT (Bitfield-Mask: 0x7ffff)                 */
31173 /* =====================================================  DSP1L3LVLINT  ====================================================== */
31174 #define DSP_DSP1L3LVLINT_DSP1L3LVLINT_Pos (0UL)                     /*!< DSP1L3LVLINT (Bit 0)                                  */
31175 #define DSP_DSP1L3LVLINT_DSP1L3LVLINT_Msk (0x7ffffUL)               /*!< DSP1L3LVLINT (Bitfield-Mask: 0x7ffff)                 */
31176 /* =====================================================  DSP1L4LVLINT  ====================================================== */
31177 #define DSP_DSP1L4LVLINT_DSP1L4LVLINT_Pos (0UL)                     /*!< DSP1L4LVLINT (Bit 0)                                  */
31178 #define DSP_DSP1L4LVLINT_DSP1L4LVLINT_Msk (0x7ffffUL)               /*!< DSP1L4LVLINT (Bitfield-Mask: 0x7ffff)                 */
31179 /* =====================================================  DSP1L5LVLINT  ====================================================== */
31180 #define DSP_DSP1L5LVLINT_DSP1L5LVLINT_Pos (0UL)                     /*!< DSP1L5LVLINT (Bit 0)                                  */
31181 #define DSP_DSP1L5LVLINT_DSP1L5LVLINT_Msk (0x7ffffUL)               /*!< DSP1L5LVLINT (Bitfield-Mask: 0x7ffff)                 */
31182 /* ====================================================  DSP1IDMATRIGCTL  ==================================================== */
31183 #define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGPULSE_Pos (4UL)             /*!< DSP1IDMATRIGPULSE (Bit 4)                             */
31184 #define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGPULSE_Msk (0x10UL)          /*!< DSP1IDMATRIGPULSE (Bitfield-Mask: 0x01)               */
31185 #define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGSTAT_Pos (0UL)              /*!< DSP1IDMATRIGSTAT (Bit 0)                              */
31186 #define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGSTAT_Msk (0x1UL)            /*!< DSP1IDMATRIGSTAT (Bitfield-Mask: 0x01)                */
31187 /* ==================================================  DSP1INTORMASK31TO0A  ================================================== */
31188 #define DSP_DSP1INTORMASK31TO0A_DSP1INTMCUIOORMASKA_Pos (0UL)       /*!< DSP1INTMCUIOORMASKA (Bit 0)                           */
31189 #define DSP_DSP1INTORMASK31TO0A_DSP1INTMCUIOORMASKA_Msk (0xffffffffUL) /*!< DSP1INTMCUIOORMASKA (Bitfield-Mask: 0xffffffff)    */
31190 /* =================================================  DSP1INTORMASK63TO32A  ================================================== */
31191 #define DSP_DSP1INTORMASK63TO32A_DSP1GPIOORMASKA_Pos (24UL)         /*!< DSP1GPIOORMASKA (Bit 24)                              */
31192 #define DSP_DSP1INTORMASK63TO32A_DSP1GPIOORMASKA_Msk (0x3f000000UL) /*!< DSP1GPIOORMASKA (Bitfield-Mask: 0x3f)                 */
31193 #define DSP_DSP1INTORMASK63TO32A_DSP1PDMORMASKA_Pos (16UL)          /*!< DSP1PDMORMASKA (Bit 16)                               */
31194 #define DSP_DSP1INTORMASK63TO32A_DSP1PDMORMASKA_Msk (0xf0000UL)     /*!< DSP1PDMORMASKA (Bitfield-Mask: 0x0f)                  */
31195 #define DSP_DSP1INTORMASK63TO32A_DSP1I2SORMASKA_Pos (12UL)          /*!< DSP1I2SORMASKA (Bit 12)                               */
31196 #define DSP_DSP1INTORMASK63TO32A_DSP1I2SORMASKA_Msk (0xf000UL)      /*!< DSP1I2SORMASKA (Bitfield-Mask: 0x0f)                  */
31197 #define DSP_DSP1INTORMASK63TO32A_DSP1TMRORMASKA_Pos (0UL)           /*!< DSP1TMRORMASKA (Bit 0)                                */
31198 #define DSP_DSP1INTORMASK63TO32A_DSP1TMRORMASKA_Msk (0x3ffUL)       /*!< DSP1TMRORMASKA (Bitfield-Mask: 0x3ff)                 */
31199 /* =================================================  DSP1INTORMASK95TO64A  ================================================== */
31200 #define DSP_DSP1INTORMASK95TO64A_DSP1MBINTORMASKA_Pos (0UL)         /*!< DSP1MBINTORMASKA (Bit 0)                              */
31201 #define DSP_DSP1INTORMASK95TO64A_DSP1MBINTORMASKA_Msk (0xffffffffUL) /*!< DSP1MBINTORMASKA (Bitfield-Mask: 0xffffffff)         */
31202 /* ==================================================  DSP1INTORMASK31to0B  ================================================== */
31203 #define DSP_DSP1INTORMASK31to0B_DSP1INTMCUIOORMASKB_Pos (0UL)       /*!< DSP1INTMCUIOORMASKB (Bit 0)                           */
31204 #define DSP_DSP1INTORMASK31to0B_DSP1INTMCUIOORMASKB_Msk (0xffffffffUL) /*!< DSP1INTMCUIOORMASKB (Bitfield-Mask: 0xffffffff)    */
31205 /* =================================================  DSP1INTORMASK63TO32B  ================================================== */
31206 #define DSP_DSP1INTORMASK63TO32B_DSP1GPIOORMASKB_Pos (24UL)         /*!< DSP1GPIOORMASKB (Bit 24)                              */
31207 #define DSP_DSP1INTORMASK63TO32B_DSP1GPIOORMASKB_Msk (0x3f000000UL) /*!< DSP1GPIOORMASKB (Bitfield-Mask: 0x3f)                 */
31208 #define DSP_DSP1INTORMASK63TO32B_DSP1PDMORMASKB_Pos (16UL)          /*!< DSP1PDMORMASKB (Bit 16)                               */
31209 #define DSP_DSP1INTORMASK63TO32B_DSP1PDMORMASKB_Msk (0xf0000UL)     /*!< DSP1PDMORMASKB (Bitfield-Mask: 0x0f)                  */
31210 #define DSP_DSP1INTORMASK63TO32B_DSP1I2SORMASKB_Pos (12UL)          /*!< DSP1I2SORMASKB (Bit 12)                               */
31211 #define DSP_DSP1INTORMASK63TO32B_DSP1I2SORMASKB_Msk (0xf000UL)      /*!< DSP1I2SORMASKB (Bitfield-Mask: 0x0f)                  */
31212 #define DSP_DSP1INTORMASK63TO32B_DSP1TMRORMASKB_Pos (0UL)           /*!< DSP1TMRORMASKB (Bit 0)                                */
31213 #define DSP_DSP1INTORMASK63TO32B_DSP1TMRORMASKB_Msk (0x3ffUL)       /*!< DSP1TMRORMASKB (Bitfield-Mask: 0x3ff)                 */
31214 /* =================================================  DSP1INTORMASK95TO64B  ================================================== */
31215 #define DSP_DSP1INTORMASK95TO64B_DSP1MBINTORMASKB_Pos (0UL)         /*!< DSP1MBINTORMASKB (Bit 0)                              */
31216 #define DSP_DSP1INTORMASK95TO64B_DSP1MBINTORMASKB_Msk (0xffffffffUL) /*!< DSP1MBINTORMASKB (Bitfield-Mask: 0xffffffff)         */
31217 /* ===================================================  DSP1INTENIRQ31TO0  =================================================== */
31218 #define DSP_DSP1INTENIRQ31TO0_DSP1INTENIRQ31TO0_Pos (0UL)           /*!< DSP1INTENIRQ31TO0 (Bit 0)                             */
31219 #define DSP_DSP1INTENIRQ31TO0_DSP1INTENIRQ31TO0_Msk (0xffffffffUL)  /*!< DSP1INTENIRQ31TO0 (Bitfield-Mask: 0xffffffff)         */
31220 /* ==================================================  DSP1INTENIRQ63TO32  =================================================== */
31221 #define DSP_DSP1INTENIRQ63TO32_DSP1INTENIRQ63TO32_Pos (0UL)         /*!< DSP1INTENIRQ63TO32 (Bit 0)                            */
31222 #define DSP_DSP1INTENIRQ63TO32_DSP1INTENIRQ63TO32_Msk (0xffffffffUL) /*!< DSP1INTENIRQ63TO32 (Bitfield-Mask: 0xffffffff)       */
31223 /* ==================================================  DSP1INTENIRQ95TO64  =================================================== */
31224 #define DSP_DSP1INTENIRQ95TO64_DSP1INTENIRQ95TO64_Pos (0UL)         /*!< DSP1INTENIRQ95TO64 (Bit 0)                            */
31225 #define DSP_DSP1INTENIRQ95TO64_DSP1INTENIRQ95TO64_Msk (0xffffffffUL) /*!< DSP1INTENIRQ95TO64 (Bitfield-Mask: 0xffffffff)       */
31226 
31227 
31228 /* =========================================================================================================================== */
31229 /* ================                                           FPIO                                            ================ */
31230 /* =========================================================================================================================== */
31231 
31232 /* ==========================================================  RD0  ========================================================== */
31233 #define FPIO_RD0_RD0_Pos                  (0UL)                     /*!< RD0 (Bit 0)                                           */
31234 #define FPIO_RD0_RD0_Msk                  (0xffffffffUL)            /*!< RD0 (Bitfield-Mask: 0xffffffff)                       */
31235 /* ==========================================================  RD1  ========================================================== */
31236 #define FPIO_RD1_RD1_Pos                  (0UL)                     /*!< RD1 (Bit 0)                                           */
31237 #define FPIO_RD1_RD1_Msk                  (0xffffffffUL)            /*!< RD1 (Bitfield-Mask: 0xffffffff)                       */
31238 /* ==========================================================  RD2  ========================================================== */
31239 #define FPIO_RD2_RD2_Pos                  (0UL)                     /*!< RD2 (Bit 0)                                           */
31240 #define FPIO_RD2_RD2_Msk                  (0xffffffffUL)            /*!< RD2 (Bitfield-Mask: 0xffffffff)                       */
31241 /* ==========================================================  RD3  ========================================================== */
31242 #define FPIO_RD3_RD3_Pos                  (0UL)                     /*!< RD3 (Bit 0)                                           */
31243 #define FPIO_RD3_RD3_Msk                  (0xffffffffUL)            /*!< RD3 (Bitfield-Mask: 0xffffffff)                       */
31244 /* ==========================================================  WT0  ========================================================== */
31245 #define FPIO_WT0_WT0_Pos                  (0UL)                     /*!< WT0 (Bit 0)                                           */
31246 #define FPIO_WT0_WT0_Msk                  (0xffffffffUL)            /*!< WT0 (Bitfield-Mask: 0xffffffff)                       */
31247 /* ==========================================================  WT1  ========================================================== */
31248 #define FPIO_WT1_WT1_Pos                  (0UL)                     /*!< WT1 (Bit 0)                                           */
31249 #define FPIO_WT1_WT1_Msk                  (0xffffffffUL)            /*!< WT1 (Bitfield-Mask: 0xffffffff)                       */
31250 /* ==========================================================  WT2  ========================================================== */
31251 #define FPIO_WT2_WT2_Pos                  (0UL)                     /*!< WT2 (Bit 0)                                           */
31252 #define FPIO_WT2_WT2_Msk                  (0xffffffffUL)            /*!< WT2 (Bitfield-Mask: 0xffffffff)                       */
31253 /* ==========================================================  WT3  ========================================================== */
31254 #define FPIO_WT3_WT3_Pos                  (0UL)                     /*!< WT3 (Bit 0)                                           */
31255 #define FPIO_WT3_WT3_Msk                  (0xffffffffUL)            /*!< WT3 (Bitfield-Mask: 0xffffffff)                       */
31256 /* =========================================================  WTS0  ========================================================== */
31257 #define FPIO_WTS0_WTS0_Pos                (0UL)                     /*!< WTS0 (Bit 0)                                          */
31258 #define FPIO_WTS0_WTS0_Msk                (0xffffffffUL)            /*!< WTS0 (Bitfield-Mask: 0xffffffff)                      */
31259 /* =========================================================  WTS1  ========================================================== */
31260 #define FPIO_WTS1_WTS1_Pos                (0UL)                     /*!< WTS1 (Bit 0)                                          */
31261 #define FPIO_WTS1_WTS1_Msk                (0xffffffffUL)            /*!< WTS1 (Bitfield-Mask: 0xffffffff)                      */
31262 /* =========================================================  WTS2  ========================================================== */
31263 #define FPIO_WTS2_WTS2_Pos                (0UL)                     /*!< WTS2 (Bit 0)                                          */
31264 #define FPIO_WTS2_WTS2_Msk                (0xffffffffUL)            /*!< WTS2 (Bitfield-Mask: 0xffffffff)                      */
31265 /* =========================================================  WTS3  ========================================================== */
31266 #define FPIO_WTS3_WTS3_Pos                (0UL)                     /*!< WTS3 (Bit 0)                                          */
31267 #define FPIO_WTS3_WTS3_Msk                (0xffffffffUL)            /*!< WTS3 (Bitfield-Mask: 0xffffffff)                      */
31268 /* =========================================================  WTC0  ========================================================== */
31269 #define FPIO_WTC0_WTC0_Pos                (0UL)                     /*!< WTC0 (Bit 0)                                          */
31270 #define FPIO_WTC0_WTC0_Msk                (0xffffffffUL)            /*!< WTC0 (Bitfield-Mask: 0xffffffff)                      */
31271 /* =========================================================  WTC1  ========================================================== */
31272 #define FPIO_WTC1_WTC1_Pos                (0UL)                     /*!< WTC1 (Bit 0)                                          */
31273 #define FPIO_WTC1_WTC1_Msk                (0xffffffffUL)            /*!< WTC1 (Bitfield-Mask: 0xffffffff)                      */
31274 /* =========================================================  WTC2  ========================================================== */
31275 #define FPIO_WTC2_WTC2_Pos                (0UL)                     /*!< WTC2 (Bit 0)                                          */
31276 #define FPIO_WTC2_WTC2_Msk                (0xffffffffUL)            /*!< WTC2 (Bitfield-Mask: 0xffffffff)                      */
31277 /* =========================================================  WTC3  ========================================================== */
31278 #define FPIO_WTC3_WTC3_Pos                (0UL)                     /*!< WTC3 (Bit 0)                                          */
31279 #define FPIO_WTC3_WTC3_Msk                (0xffffffffUL)            /*!< WTC3 (Bitfield-Mask: 0xffffffff)                      */
31280 /* ==========================================================  EN0  ========================================================== */
31281 #define FPIO_EN0_EN0_Pos                  (0UL)                     /*!< EN0 (Bit 0)                                           */
31282 #define FPIO_EN0_EN0_Msk                  (0xffffffffUL)            /*!< EN0 (Bitfield-Mask: 0xffffffff)                       */
31283 /* ==========================================================  EN1  ========================================================== */
31284 #define FPIO_EN1_EN1_Pos                  (0UL)                     /*!< EN1 (Bit 0)                                           */
31285 #define FPIO_EN1_EN1_Msk                  (0xffffffffUL)            /*!< EN1 (Bitfield-Mask: 0xffffffff)                       */
31286 /* ==========================================================  EN2  ========================================================== */
31287 #define FPIO_EN2_EN2_Pos                  (0UL)                     /*!< EN2 (Bit 0)                                           */
31288 #define FPIO_EN2_EN2_Msk                  (0xffffffffUL)            /*!< EN2 (Bitfield-Mask: 0xffffffff)                       */
31289 /* ==========================================================  EN3  ========================================================== */
31290 #define FPIO_EN3_EN3_Pos                  (0UL)                     /*!< EN3 (Bit 0)                                           */
31291 #define FPIO_EN3_EN3_Msk                  (0xffffffffUL)            /*!< EN3 (Bitfield-Mask: 0xffffffff)                       */
31292 /* =========================================================  ENS0  ========================================================== */
31293 #define FPIO_ENS0_ENS0_Pos                (0UL)                     /*!< ENS0 (Bit 0)                                          */
31294 #define FPIO_ENS0_ENS0_Msk                (0xffffffffUL)            /*!< ENS0 (Bitfield-Mask: 0xffffffff)                      */
31295 /* =========================================================  ENS1  ========================================================== */
31296 #define FPIO_ENS1_ENS1_Pos                (0UL)                     /*!< ENS1 (Bit 0)                                          */
31297 #define FPIO_ENS1_ENS1_Msk                (0xffffffffUL)            /*!< ENS1 (Bitfield-Mask: 0xffffffff)                      */
31298 /* =========================================================  ENS2  ========================================================== */
31299 #define FPIO_ENS2_ENS2_Pos                (0UL)                     /*!< ENS2 (Bit 0)                                          */
31300 #define FPIO_ENS2_ENS2_Msk                (0xffffffffUL)            /*!< ENS2 (Bitfield-Mask: 0xffffffff)                      */
31301 /* =========================================================  ENS3  ========================================================== */
31302 #define FPIO_ENS3_ENS3_Pos                (0UL)                     /*!< ENS3 (Bit 0)                                          */
31303 #define FPIO_ENS3_ENS3_Msk                (0xffffffffUL)            /*!< ENS3 (Bitfield-Mask: 0xffffffff)                      */
31304 /* =========================================================  ENC0  ========================================================== */
31305 #define FPIO_ENC0_ENC0_Pos                (0UL)                     /*!< ENC0 (Bit 0)                                          */
31306 #define FPIO_ENC0_ENC0_Msk                (0xffffffffUL)            /*!< ENC0 (Bitfield-Mask: 0xffffffff)                      */
31307 /* =========================================================  ENC1  ========================================================== */
31308 #define FPIO_ENC1_ENC1_Pos                (0UL)                     /*!< ENC1 (Bit 0)                                          */
31309 #define FPIO_ENC1_ENC1_Msk                (0xffffffffUL)            /*!< ENC1 (Bitfield-Mask: 0xffffffff)                      */
31310 /* =========================================================  ENC2  ========================================================== */
31311 #define FPIO_ENC2_ENC2_Pos                (0UL)                     /*!< ENC2 (Bit 0)                                          */
31312 #define FPIO_ENC2_ENC2_Msk                (0xffffffffUL)            /*!< ENC2 (Bitfield-Mask: 0xffffffff)                      */
31313 /* =========================================================  ENC3  ========================================================== */
31314 #define FPIO_ENC3_ENC3_Pos                (0UL)                     /*!< ENC3 (Bit 0)                                          */
31315 #define FPIO_ENC3_ENC3_Msk                (0xffffffffUL)            /*!< ENC3 (Bitfield-Mask: 0xffffffff)                      */
31316 
31317 
31318 /* =========================================================================================================================== */
31319 /* ================                                           GPIO                                            ================ */
31320 /* =========================================================================================================================== */
31321 
31322 /* ========================================================  PINCFG0  ======================================================== */
31323 #define GPIO_PINCFG0_FOEN0_Pos            (27UL)                    /*!< FOEN0 (Bit 27)                                        */
31324 #define GPIO_PINCFG0_FOEN0_Msk            (0x8000000UL)             /*!< FOEN0 (Bitfield-Mask: 0x01)                           */
31325 #define GPIO_PINCFG0_FIEN0_Pos            (26UL)                    /*!< FIEN0 (Bit 26)                                        */
31326 #define GPIO_PINCFG0_FIEN0_Msk            (0x4000000UL)             /*!< FIEN0 (Bitfield-Mask: 0x01)                           */
31327 #define GPIO_PINCFG0_NCEPOL0_Pos          (22UL)                    /*!< NCEPOL0 (Bit 22)                                      */
31328 #define GPIO_PINCFG0_NCEPOL0_Msk          (0x400000UL)              /*!< NCEPOL0 (Bitfield-Mask: 0x01)                         */
31329 #define GPIO_PINCFG0_NCESRC0_Pos          (16UL)                    /*!< NCESRC0 (Bit 16)                                      */
31330 #define GPIO_PINCFG0_NCESRC0_Msk          (0x3f0000UL)              /*!< NCESRC0 (Bitfield-Mask: 0x3f)                         */
31331 #define GPIO_PINCFG0_PULLCFG0_Pos         (13UL)                    /*!< PULLCFG0 (Bit 13)                                     */
31332 #define GPIO_PINCFG0_PULLCFG0_Msk         (0xe000UL)                /*!< PULLCFG0 (Bitfield-Mask: 0x07)                        */
31333 #define GPIO_PINCFG0_SR0_Pos              (12UL)                    /*!< SR0 (Bit 12)                                          */
31334 #define GPIO_PINCFG0_SR0_Msk              (0x1000UL)                /*!< SR0 (Bitfield-Mask: 0x01)                             */
31335 #define GPIO_PINCFG0_DS0_Pos              (10UL)                    /*!< DS0 (Bit 10)                                          */
31336 #define GPIO_PINCFG0_DS0_Msk              (0xc00UL)                 /*!< DS0 (Bitfield-Mask: 0x03)                             */
31337 #define GPIO_PINCFG0_OUTCFG0_Pos          (8UL)                     /*!< OUTCFG0 (Bit 8)                                       */
31338 #define GPIO_PINCFG0_OUTCFG0_Msk          (0x300UL)                 /*!< OUTCFG0 (Bitfield-Mask: 0x03)                         */
31339 #define GPIO_PINCFG0_IRPTEN0_Pos          (6UL)                     /*!< IRPTEN0 (Bit 6)                                       */
31340 #define GPIO_PINCFG0_IRPTEN0_Msk          (0xc0UL)                  /*!< IRPTEN0 (Bitfield-Mask: 0x03)                         */
31341 #define GPIO_PINCFG0_RDZERO0_Pos          (5UL)                     /*!< RDZERO0 (Bit 5)                                       */
31342 #define GPIO_PINCFG0_RDZERO0_Msk          (0x20UL)                  /*!< RDZERO0 (Bitfield-Mask: 0x01)                         */
31343 #define GPIO_PINCFG0_INPEN0_Pos           (4UL)                     /*!< INPEN0 (Bit 4)                                        */
31344 #define GPIO_PINCFG0_INPEN0_Msk           (0x10UL)                  /*!< INPEN0 (Bitfield-Mask: 0x01)                          */
31345 #define GPIO_PINCFG0_FNCSEL0_Pos          (0UL)                     /*!< FNCSEL0 (Bit 0)                                       */
31346 #define GPIO_PINCFG0_FNCSEL0_Msk          (0xfUL)                   /*!< FNCSEL0 (Bitfield-Mask: 0x0f)                         */
31347 /* ========================================================  PINCFG1  ======================================================== */
31348 #define GPIO_PINCFG1_FOEN1_Pos            (27UL)                    /*!< FOEN1 (Bit 27)                                        */
31349 #define GPIO_PINCFG1_FOEN1_Msk            (0x8000000UL)             /*!< FOEN1 (Bitfield-Mask: 0x01)                           */
31350 #define GPIO_PINCFG1_FIEN1_Pos            (26UL)                    /*!< FIEN1 (Bit 26)                                        */
31351 #define GPIO_PINCFG1_FIEN1_Msk            (0x4000000UL)             /*!< FIEN1 (Bitfield-Mask: 0x01)                           */
31352 #define GPIO_PINCFG1_NCEPOL1_Pos          (22UL)                    /*!< NCEPOL1 (Bit 22)                                      */
31353 #define GPIO_PINCFG1_NCEPOL1_Msk          (0x400000UL)              /*!< NCEPOL1 (Bitfield-Mask: 0x01)                         */
31354 #define GPIO_PINCFG1_NCESRC1_Pos          (16UL)                    /*!< NCESRC1 (Bit 16)                                      */
31355 #define GPIO_PINCFG1_NCESRC1_Msk          (0x3f0000UL)              /*!< NCESRC1 (Bitfield-Mask: 0x3f)                         */
31356 #define GPIO_PINCFG1_PULLCFG1_Pos         (13UL)                    /*!< PULLCFG1 (Bit 13)                                     */
31357 #define GPIO_PINCFG1_PULLCFG1_Msk         (0xe000UL)                /*!< PULLCFG1 (Bitfield-Mask: 0x07)                        */
31358 #define GPIO_PINCFG1_SR1_Pos              (12UL)                    /*!< SR1 (Bit 12)                                          */
31359 #define GPIO_PINCFG1_SR1_Msk              (0x1000UL)                /*!< SR1 (Bitfield-Mask: 0x01)                             */
31360 #define GPIO_PINCFG1_DS1_Pos              (10UL)                    /*!< DS1 (Bit 10)                                          */
31361 #define GPIO_PINCFG1_DS1_Msk              (0xc00UL)                 /*!< DS1 (Bitfield-Mask: 0x03)                             */
31362 #define GPIO_PINCFG1_OUTCFG1_Pos          (8UL)                     /*!< OUTCFG1 (Bit 8)                                       */
31363 #define GPIO_PINCFG1_OUTCFG1_Msk          (0x300UL)                 /*!< OUTCFG1 (Bitfield-Mask: 0x03)                         */
31364 #define GPIO_PINCFG1_IRPTEN1_Pos          (6UL)                     /*!< IRPTEN1 (Bit 6)                                       */
31365 #define GPIO_PINCFG1_IRPTEN1_Msk          (0xc0UL)                  /*!< IRPTEN1 (Bitfield-Mask: 0x03)                         */
31366 #define GPIO_PINCFG1_RDZERO1_Pos          (5UL)                     /*!< RDZERO1 (Bit 5)                                       */
31367 #define GPIO_PINCFG1_RDZERO1_Msk          (0x20UL)                  /*!< RDZERO1 (Bitfield-Mask: 0x01)                         */
31368 #define GPIO_PINCFG1_INPEN1_Pos           (4UL)                     /*!< INPEN1 (Bit 4)                                        */
31369 #define GPIO_PINCFG1_INPEN1_Msk           (0x10UL)                  /*!< INPEN1 (Bitfield-Mask: 0x01)                          */
31370 #define GPIO_PINCFG1_FNCSEL1_Pos          (0UL)                     /*!< FNCSEL1 (Bit 0)                                       */
31371 #define GPIO_PINCFG1_FNCSEL1_Msk          (0xfUL)                   /*!< FNCSEL1 (Bitfield-Mask: 0x0f)                         */
31372 /* ========================================================  PINCFG2  ======================================================== */
31373 #define GPIO_PINCFG2_FOEN2_Pos            (27UL)                    /*!< FOEN2 (Bit 27)                                        */
31374 #define GPIO_PINCFG2_FOEN2_Msk            (0x8000000UL)             /*!< FOEN2 (Bitfield-Mask: 0x01)                           */
31375 #define GPIO_PINCFG2_FIEN2_Pos            (26UL)                    /*!< FIEN2 (Bit 26)                                        */
31376 #define GPIO_PINCFG2_FIEN2_Msk            (0x4000000UL)             /*!< FIEN2 (Bitfield-Mask: 0x01)                           */
31377 #define GPIO_PINCFG2_NCEPOL2_Pos          (22UL)                    /*!< NCEPOL2 (Bit 22)                                      */
31378 #define GPIO_PINCFG2_NCEPOL2_Msk          (0x400000UL)              /*!< NCEPOL2 (Bitfield-Mask: 0x01)                         */
31379 #define GPIO_PINCFG2_NCESRC2_Pos          (16UL)                    /*!< NCESRC2 (Bit 16)                                      */
31380 #define GPIO_PINCFG2_NCESRC2_Msk          (0x3f0000UL)              /*!< NCESRC2 (Bitfield-Mask: 0x3f)                         */
31381 #define GPIO_PINCFG2_PULLCFG2_Pos         (13UL)                    /*!< PULLCFG2 (Bit 13)                                     */
31382 #define GPIO_PINCFG2_PULLCFG2_Msk         (0xe000UL)                /*!< PULLCFG2 (Bitfield-Mask: 0x07)                        */
31383 #define GPIO_PINCFG2_SR2_Pos              (12UL)                    /*!< SR2 (Bit 12)                                          */
31384 #define GPIO_PINCFG2_SR2_Msk              (0x1000UL)                /*!< SR2 (Bitfield-Mask: 0x01)                             */
31385 #define GPIO_PINCFG2_DS2_Pos              (10UL)                    /*!< DS2 (Bit 10)                                          */
31386 #define GPIO_PINCFG2_DS2_Msk              (0xc00UL)                 /*!< DS2 (Bitfield-Mask: 0x03)                             */
31387 #define GPIO_PINCFG2_OUTCFG2_Pos          (8UL)                     /*!< OUTCFG2 (Bit 8)                                       */
31388 #define GPIO_PINCFG2_OUTCFG2_Msk          (0x300UL)                 /*!< OUTCFG2 (Bitfield-Mask: 0x03)                         */
31389 #define GPIO_PINCFG2_IRPTEN2_Pos          (6UL)                     /*!< IRPTEN2 (Bit 6)                                       */
31390 #define GPIO_PINCFG2_IRPTEN2_Msk          (0xc0UL)                  /*!< IRPTEN2 (Bitfield-Mask: 0x03)                         */
31391 #define GPIO_PINCFG2_RDZERO2_Pos          (5UL)                     /*!< RDZERO2 (Bit 5)                                       */
31392 #define GPIO_PINCFG2_RDZERO2_Msk          (0x20UL)                  /*!< RDZERO2 (Bitfield-Mask: 0x01)                         */
31393 #define GPIO_PINCFG2_INPEN2_Pos           (4UL)                     /*!< INPEN2 (Bit 4)                                        */
31394 #define GPIO_PINCFG2_INPEN2_Msk           (0x10UL)                  /*!< INPEN2 (Bitfield-Mask: 0x01)                          */
31395 #define GPIO_PINCFG2_FNCSEL2_Pos          (0UL)                     /*!< FNCSEL2 (Bit 0)                                       */
31396 #define GPIO_PINCFG2_FNCSEL2_Msk          (0xfUL)                   /*!< FNCSEL2 (Bitfield-Mask: 0x0f)                         */
31397 /* ========================================================  PINCFG3  ======================================================== */
31398 #define GPIO_PINCFG3_FOEN3_Pos            (27UL)                    /*!< FOEN3 (Bit 27)                                        */
31399 #define GPIO_PINCFG3_FOEN3_Msk            (0x8000000UL)             /*!< FOEN3 (Bitfield-Mask: 0x01)                           */
31400 #define GPIO_PINCFG3_FIEN3_Pos            (26UL)                    /*!< FIEN3 (Bit 26)                                        */
31401 #define GPIO_PINCFG3_FIEN3_Msk            (0x4000000UL)             /*!< FIEN3 (Bitfield-Mask: 0x01)                           */
31402 #define GPIO_PINCFG3_NCEPOL3_Pos          (22UL)                    /*!< NCEPOL3 (Bit 22)                                      */
31403 #define GPIO_PINCFG3_NCEPOL3_Msk          (0x400000UL)              /*!< NCEPOL3 (Bitfield-Mask: 0x01)                         */
31404 #define GPIO_PINCFG3_NCESRC3_Pos          (16UL)                    /*!< NCESRC3 (Bit 16)                                      */
31405 #define GPIO_PINCFG3_NCESRC3_Msk          (0x3f0000UL)              /*!< NCESRC3 (Bitfield-Mask: 0x3f)                         */
31406 #define GPIO_PINCFG3_PULLCFG3_Pos         (13UL)                    /*!< PULLCFG3 (Bit 13)                                     */
31407 #define GPIO_PINCFG3_PULLCFG3_Msk         (0xe000UL)                /*!< PULLCFG3 (Bitfield-Mask: 0x07)                        */
31408 #define GPIO_PINCFG3_SR3_Pos              (12UL)                    /*!< SR3 (Bit 12)                                          */
31409 #define GPIO_PINCFG3_SR3_Msk              (0x1000UL)                /*!< SR3 (Bitfield-Mask: 0x01)                             */
31410 #define GPIO_PINCFG3_DS3_Pos              (10UL)                    /*!< DS3 (Bit 10)                                          */
31411 #define GPIO_PINCFG3_DS3_Msk              (0xc00UL)                 /*!< DS3 (Bitfield-Mask: 0x03)                             */
31412 #define GPIO_PINCFG3_OUTCFG3_Pos          (8UL)                     /*!< OUTCFG3 (Bit 8)                                       */
31413 #define GPIO_PINCFG3_OUTCFG3_Msk          (0x300UL)                 /*!< OUTCFG3 (Bitfield-Mask: 0x03)                         */
31414 #define GPIO_PINCFG3_IRPTEN3_Pos          (6UL)                     /*!< IRPTEN3 (Bit 6)                                       */
31415 #define GPIO_PINCFG3_IRPTEN3_Msk          (0xc0UL)                  /*!< IRPTEN3 (Bitfield-Mask: 0x03)                         */
31416 #define GPIO_PINCFG3_RDZERO3_Pos          (5UL)                     /*!< RDZERO3 (Bit 5)                                       */
31417 #define GPIO_PINCFG3_RDZERO3_Msk          (0x20UL)                  /*!< RDZERO3 (Bitfield-Mask: 0x01)                         */
31418 #define GPIO_PINCFG3_INPEN3_Pos           (4UL)                     /*!< INPEN3 (Bit 4)                                        */
31419 #define GPIO_PINCFG3_INPEN3_Msk           (0x10UL)                  /*!< INPEN3 (Bitfield-Mask: 0x01)                          */
31420 #define GPIO_PINCFG3_FNCSEL3_Pos          (0UL)                     /*!< FNCSEL3 (Bit 0)                                       */
31421 #define GPIO_PINCFG3_FNCSEL3_Msk          (0xfUL)                   /*!< FNCSEL3 (Bitfield-Mask: 0x0f)                         */
31422 /* ========================================================  PINCFG4  ======================================================== */
31423 #define GPIO_PINCFG4_FOEN4_Pos            (27UL)                    /*!< FOEN4 (Bit 27)                                        */
31424 #define GPIO_PINCFG4_FOEN4_Msk            (0x8000000UL)             /*!< FOEN4 (Bitfield-Mask: 0x01)                           */
31425 #define GPIO_PINCFG4_FIEN4_Pos            (26UL)                    /*!< FIEN4 (Bit 26)                                        */
31426 #define GPIO_PINCFG4_FIEN4_Msk            (0x4000000UL)             /*!< FIEN4 (Bitfield-Mask: 0x01)                           */
31427 #define GPIO_PINCFG4_NCEPOL4_Pos          (22UL)                    /*!< NCEPOL4 (Bit 22)                                      */
31428 #define GPIO_PINCFG4_NCEPOL4_Msk          (0x400000UL)              /*!< NCEPOL4 (Bitfield-Mask: 0x01)                         */
31429 #define GPIO_PINCFG4_NCESRC4_Pos          (16UL)                    /*!< NCESRC4 (Bit 16)                                      */
31430 #define GPIO_PINCFG4_NCESRC4_Msk          (0x3f0000UL)              /*!< NCESRC4 (Bitfield-Mask: 0x3f)                         */
31431 #define GPIO_PINCFG4_PULLCFG4_Pos         (13UL)                    /*!< PULLCFG4 (Bit 13)                                     */
31432 #define GPIO_PINCFG4_PULLCFG4_Msk         (0xe000UL)                /*!< PULLCFG4 (Bitfield-Mask: 0x07)                        */
31433 #define GPIO_PINCFG4_SR4_Pos              (12UL)                    /*!< SR4 (Bit 12)                                          */
31434 #define GPIO_PINCFG4_SR4_Msk              (0x1000UL)                /*!< SR4 (Bitfield-Mask: 0x01)                             */
31435 #define GPIO_PINCFG4_DS4_Pos              (10UL)                    /*!< DS4 (Bit 10)                                          */
31436 #define GPIO_PINCFG4_DS4_Msk              (0xc00UL)                 /*!< DS4 (Bitfield-Mask: 0x03)                             */
31437 #define GPIO_PINCFG4_OUTCFG4_Pos          (8UL)                     /*!< OUTCFG4 (Bit 8)                                       */
31438 #define GPIO_PINCFG4_OUTCFG4_Msk          (0x300UL)                 /*!< OUTCFG4 (Bitfield-Mask: 0x03)                         */
31439 #define GPIO_PINCFG4_IRPTEN4_Pos          (6UL)                     /*!< IRPTEN4 (Bit 6)                                       */
31440 #define GPIO_PINCFG4_IRPTEN4_Msk          (0xc0UL)                  /*!< IRPTEN4 (Bitfield-Mask: 0x03)                         */
31441 #define GPIO_PINCFG4_RDZERO4_Pos          (5UL)                     /*!< RDZERO4 (Bit 5)                                       */
31442 #define GPIO_PINCFG4_RDZERO4_Msk          (0x20UL)                  /*!< RDZERO4 (Bitfield-Mask: 0x01)                         */
31443 #define GPIO_PINCFG4_INPEN4_Pos           (4UL)                     /*!< INPEN4 (Bit 4)                                        */
31444 #define GPIO_PINCFG4_INPEN4_Msk           (0x10UL)                  /*!< INPEN4 (Bitfield-Mask: 0x01)                          */
31445 #define GPIO_PINCFG4_FNCSEL4_Pos          (0UL)                     /*!< FNCSEL4 (Bit 0)                                       */
31446 #define GPIO_PINCFG4_FNCSEL4_Msk          (0xfUL)                   /*!< FNCSEL4 (Bitfield-Mask: 0x0f)                         */
31447 /* ========================================================  PINCFG5  ======================================================== */
31448 #define GPIO_PINCFG5_FOEN5_Pos            (27UL)                    /*!< FOEN5 (Bit 27)                                        */
31449 #define GPIO_PINCFG5_FOEN5_Msk            (0x8000000UL)             /*!< FOEN5 (Bitfield-Mask: 0x01)                           */
31450 #define GPIO_PINCFG5_FIEN5_Pos            (26UL)                    /*!< FIEN5 (Bit 26)                                        */
31451 #define GPIO_PINCFG5_FIEN5_Msk            (0x4000000UL)             /*!< FIEN5 (Bitfield-Mask: 0x01)                           */
31452 #define GPIO_PINCFG5_NCEPOL5_Pos          (22UL)                    /*!< NCEPOL5 (Bit 22)                                      */
31453 #define GPIO_PINCFG5_NCEPOL5_Msk          (0x400000UL)              /*!< NCEPOL5 (Bitfield-Mask: 0x01)                         */
31454 #define GPIO_PINCFG5_NCESRC5_Pos          (16UL)                    /*!< NCESRC5 (Bit 16)                                      */
31455 #define GPIO_PINCFG5_NCESRC5_Msk          (0x3f0000UL)              /*!< NCESRC5 (Bitfield-Mask: 0x3f)                         */
31456 #define GPIO_PINCFG5_PULLCFG5_Pos         (13UL)                    /*!< PULLCFG5 (Bit 13)                                     */
31457 #define GPIO_PINCFG5_PULLCFG5_Msk         (0xe000UL)                /*!< PULLCFG5 (Bitfield-Mask: 0x07)                        */
31458 #define GPIO_PINCFG5_SR5_Pos              (12UL)                    /*!< SR5 (Bit 12)                                          */
31459 #define GPIO_PINCFG5_SR5_Msk              (0x1000UL)                /*!< SR5 (Bitfield-Mask: 0x01)                             */
31460 #define GPIO_PINCFG5_DS5_Pos              (10UL)                    /*!< DS5 (Bit 10)                                          */
31461 #define GPIO_PINCFG5_DS5_Msk              (0xc00UL)                 /*!< DS5 (Bitfield-Mask: 0x03)                             */
31462 #define GPIO_PINCFG5_OUTCFG5_Pos          (8UL)                     /*!< OUTCFG5 (Bit 8)                                       */
31463 #define GPIO_PINCFG5_OUTCFG5_Msk          (0x300UL)                 /*!< OUTCFG5 (Bitfield-Mask: 0x03)                         */
31464 #define GPIO_PINCFG5_IRPTEN5_Pos          (6UL)                     /*!< IRPTEN5 (Bit 6)                                       */
31465 #define GPIO_PINCFG5_IRPTEN5_Msk          (0xc0UL)                  /*!< IRPTEN5 (Bitfield-Mask: 0x03)                         */
31466 #define GPIO_PINCFG5_RDZERO5_Pos          (5UL)                     /*!< RDZERO5 (Bit 5)                                       */
31467 #define GPIO_PINCFG5_RDZERO5_Msk          (0x20UL)                  /*!< RDZERO5 (Bitfield-Mask: 0x01)                         */
31468 #define GPIO_PINCFG5_INPEN5_Pos           (4UL)                     /*!< INPEN5 (Bit 4)                                        */
31469 #define GPIO_PINCFG5_INPEN5_Msk           (0x10UL)                  /*!< INPEN5 (Bitfield-Mask: 0x01)                          */
31470 #define GPIO_PINCFG5_FNCSEL5_Pos          (0UL)                     /*!< FNCSEL5 (Bit 0)                                       */
31471 #define GPIO_PINCFG5_FNCSEL5_Msk          (0xfUL)                   /*!< FNCSEL5 (Bitfield-Mask: 0x0f)                         */
31472 /* ========================================================  PINCFG6  ======================================================== */
31473 #define GPIO_PINCFG6_FOEN6_Pos            (27UL)                    /*!< FOEN6 (Bit 27)                                        */
31474 #define GPIO_PINCFG6_FOEN6_Msk            (0x8000000UL)             /*!< FOEN6 (Bitfield-Mask: 0x01)                           */
31475 #define GPIO_PINCFG6_FIEN6_Pos            (26UL)                    /*!< FIEN6 (Bit 26)                                        */
31476 #define GPIO_PINCFG6_FIEN6_Msk            (0x4000000UL)             /*!< FIEN6 (Bitfield-Mask: 0x01)                           */
31477 #define GPIO_PINCFG6_NCEPOL6_Pos          (22UL)                    /*!< NCEPOL6 (Bit 22)                                      */
31478 #define GPIO_PINCFG6_NCEPOL6_Msk          (0x400000UL)              /*!< NCEPOL6 (Bitfield-Mask: 0x01)                         */
31479 #define GPIO_PINCFG6_NCESRC6_Pos          (16UL)                    /*!< NCESRC6 (Bit 16)                                      */
31480 #define GPIO_PINCFG6_NCESRC6_Msk          (0x3f0000UL)              /*!< NCESRC6 (Bitfield-Mask: 0x3f)                         */
31481 #define GPIO_PINCFG6_PULLCFG6_Pos         (13UL)                    /*!< PULLCFG6 (Bit 13)                                     */
31482 #define GPIO_PINCFG6_PULLCFG6_Msk         (0xe000UL)                /*!< PULLCFG6 (Bitfield-Mask: 0x07)                        */
31483 #define GPIO_PINCFG6_SR6_Pos              (12UL)                    /*!< SR6 (Bit 12)                                          */
31484 #define GPIO_PINCFG6_SR6_Msk              (0x1000UL)                /*!< SR6 (Bitfield-Mask: 0x01)                             */
31485 #define GPIO_PINCFG6_DS6_Pos              (10UL)                    /*!< DS6 (Bit 10)                                          */
31486 #define GPIO_PINCFG6_DS6_Msk              (0xc00UL)                 /*!< DS6 (Bitfield-Mask: 0x03)                             */
31487 #define GPIO_PINCFG6_OUTCFG6_Pos          (8UL)                     /*!< OUTCFG6 (Bit 8)                                       */
31488 #define GPIO_PINCFG6_OUTCFG6_Msk          (0x300UL)                 /*!< OUTCFG6 (Bitfield-Mask: 0x03)                         */
31489 #define GPIO_PINCFG6_IRPTEN6_Pos          (6UL)                     /*!< IRPTEN6 (Bit 6)                                       */
31490 #define GPIO_PINCFG6_IRPTEN6_Msk          (0xc0UL)                  /*!< IRPTEN6 (Bitfield-Mask: 0x03)                         */
31491 #define GPIO_PINCFG6_RDZERO6_Pos          (5UL)                     /*!< RDZERO6 (Bit 5)                                       */
31492 #define GPIO_PINCFG6_RDZERO6_Msk          (0x20UL)                  /*!< RDZERO6 (Bitfield-Mask: 0x01)                         */
31493 #define GPIO_PINCFG6_INPEN6_Pos           (4UL)                     /*!< INPEN6 (Bit 4)                                        */
31494 #define GPIO_PINCFG6_INPEN6_Msk           (0x10UL)                  /*!< INPEN6 (Bitfield-Mask: 0x01)                          */
31495 #define GPIO_PINCFG6_FNCSEL6_Pos          (0UL)                     /*!< FNCSEL6 (Bit 0)                                       */
31496 #define GPIO_PINCFG6_FNCSEL6_Msk          (0xfUL)                   /*!< FNCSEL6 (Bitfield-Mask: 0x0f)                         */
31497 /* ========================================================  PINCFG7  ======================================================== */
31498 #define GPIO_PINCFG7_FOEN7_Pos            (27UL)                    /*!< FOEN7 (Bit 27)                                        */
31499 #define GPIO_PINCFG7_FOEN7_Msk            (0x8000000UL)             /*!< FOEN7 (Bitfield-Mask: 0x01)                           */
31500 #define GPIO_PINCFG7_FIEN7_Pos            (26UL)                    /*!< FIEN7 (Bit 26)                                        */
31501 #define GPIO_PINCFG7_FIEN7_Msk            (0x4000000UL)             /*!< FIEN7 (Bitfield-Mask: 0x01)                           */
31502 #define GPIO_PINCFG7_NCEPOL7_Pos          (22UL)                    /*!< NCEPOL7 (Bit 22)                                      */
31503 #define GPIO_PINCFG7_NCEPOL7_Msk          (0x400000UL)              /*!< NCEPOL7 (Bitfield-Mask: 0x01)                         */
31504 #define GPIO_PINCFG7_NCESRC7_Pos          (16UL)                    /*!< NCESRC7 (Bit 16)                                      */
31505 #define GPIO_PINCFG7_NCESRC7_Msk          (0x3f0000UL)              /*!< NCESRC7 (Bitfield-Mask: 0x3f)                         */
31506 #define GPIO_PINCFG7_PULLCFG7_Pos         (13UL)                    /*!< PULLCFG7 (Bit 13)                                     */
31507 #define GPIO_PINCFG7_PULLCFG7_Msk         (0xe000UL)                /*!< PULLCFG7 (Bitfield-Mask: 0x07)                        */
31508 #define GPIO_PINCFG7_SR7_Pos              (12UL)                    /*!< SR7 (Bit 12)                                          */
31509 #define GPIO_PINCFG7_SR7_Msk              (0x1000UL)                /*!< SR7 (Bitfield-Mask: 0x01)                             */
31510 #define GPIO_PINCFG7_DS7_Pos              (10UL)                    /*!< DS7 (Bit 10)                                          */
31511 #define GPIO_PINCFG7_DS7_Msk              (0xc00UL)                 /*!< DS7 (Bitfield-Mask: 0x03)                             */
31512 #define GPIO_PINCFG7_OUTCFG7_Pos          (8UL)                     /*!< OUTCFG7 (Bit 8)                                       */
31513 #define GPIO_PINCFG7_OUTCFG7_Msk          (0x300UL)                 /*!< OUTCFG7 (Bitfield-Mask: 0x03)                         */
31514 #define GPIO_PINCFG7_IRPTEN7_Pos          (6UL)                     /*!< IRPTEN7 (Bit 6)                                       */
31515 #define GPIO_PINCFG7_IRPTEN7_Msk          (0xc0UL)                  /*!< IRPTEN7 (Bitfield-Mask: 0x03)                         */
31516 #define GPIO_PINCFG7_RDZERO7_Pos          (5UL)                     /*!< RDZERO7 (Bit 5)                                       */
31517 #define GPIO_PINCFG7_RDZERO7_Msk          (0x20UL)                  /*!< RDZERO7 (Bitfield-Mask: 0x01)                         */
31518 #define GPIO_PINCFG7_INPEN7_Pos           (4UL)                     /*!< INPEN7 (Bit 4)                                        */
31519 #define GPIO_PINCFG7_INPEN7_Msk           (0x10UL)                  /*!< INPEN7 (Bitfield-Mask: 0x01)                          */
31520 #define GPIO_PINCFG7_FNCSEL7_Pos          (0UL)                     /*!< FNCSEL7 (Bit 0)                                       */
31521 #define GPIO_PINCFG7_FNCSEL7_Msk          (0xfUL)                   /*!< FNCSEL7 (Bitfield-Mask: 0x0f)                         */
31522 /* ========================================================  PINCFG8  ======================================================== */
31523 #define GPIO_PINCFG8_FOEN8_Pos            (27UL)                    /*!< FOEN8 (Bit 27)                                        */
31524 #define GPIO_PINCFG8_FOEN8_Msk            (0x8000000UL)             /*!< FOEN8 (Bitfield-Mask: 0x01)                           */
31525 #define GPIO_PINCFG8_FIEN8_Pos            (26UL)                    /*!< FIEN8 (Bit 26)                                        */
31526 #define GPIO_PINCFG8_FIEN8_Msk            (0x4000000UL)             /*!< FIEN8 (Bitfield-Mask: 0x01)                           */
31527 #define GPIO_PINCFG8_NCEPOL8_Pos          (22UL)                    /*!< NCEPOL8 (Bit 22)                                      */
31528 #define GPIO_PINCFG8_NCEPOL8_Msk          (0x400000UL)              /*!< NCEPOL8 (Bitfield-Mask: 0x01)                         */
31529 #define GPIO_PINCFG8_NCESRC8_Pos          (16UL)                    /*!< NCESRC8 (Bit 16)                                      */
31530 #define GPIO_PINCFG8_NCESRC8_Msk          (0x3f0000UL)              /*!< NCESRC8 (Bitfield-Mask: 0x3f)                         */
31531 #define GPIO_PINCFG8_PULLCFG8_Pos         (13UL)                    /*!< PULLCFG8 (Bit 13)                                     */
31532 #define GPIO_PINCFG8_PULLCFG8_Msk         (0xe000UL)                /*!< PULLCFG8 (Bitfield-Mask: 0x07)                        */
31533 #define GPIO_PINCFG8_SR8_Pos              (12UL)                    /*!< SR8 (Bit 12)                                          */
31534 #define GPIO_PINCFG8_SR8_Msk              (0x1000UL)                /*!< SR8 (Bitfield-Mask: 0x01)                             */
31535 #define GPIO_PINCFG8_DS8_Pos              (10UL)                    /*!< DS8 (Bit 10)                                          */
31536 #define GPIO_PINCFG8_DS8_Msk              (0xc00UL)                 /*!< DS8 (Bitfield-Mask: 0x03)                             */
31537 #define GPIO_PINCFG8_OUTCFG8_Pos          (8UL)                     /*!< OUTCFG8 (Bit 8)                                       */
31538 #define GPIO_PINCFG8_OUTCFG8_Msk          (0x300UL)                 /*!< OUTCFG8 (Bitfield-Mask: 0x03)                         */
31539 #define GPIO_PINCFG8_IRPTEN8_Pos          (6UL)                     /*!< IRPTEN8 (Bit 6)                                       */
31540 #define GPIO_PINCFG8_IRPTEN8_Msk          (0xc0UL)                  /*!< IRPTEN8 (Bitfield-Mask: 0x03)                         */
31541 #define GPIO_PINCFG8_RDZERO8_Pos          (5UL)                     /*!< RDZERO8 (Bit 5)                                       */
31542 #define GPIO_PINCFG8_RDZERO8_Msk          (0x20UL)                  /*!< RDZERO8 (Bitfield-Mask: 0x01)                         */
31543 #define GPIO_PINCFG8_INPEN8_Pos           (4UL)                     /*!< INPEN8 (Bit 4)                                        */
31544 #define GPIO_PINCFG8_INPEN8_Msk           (0x10UL)                  /*!< INPEN8 (Bitfield-Mask: 0x01)                          */
31545 #define GPIO_PINCFG8_FNCSEL8_Pos          (0UL)                     /*!< FNCSEL8 (Bit 0)                                       */
31546 #define GPIO_PINCFG8_FNCSEL8_Msk          (0xfUL)                   /*!< FNCSEL8 (Bitfield-Mask: 0x0f)                         */
31547 /* ========================================================  PINCFG9  ======================================================== */
31548 #define GPIO_PINCFG9_FOEN9_Pos            (27UL)                    /*!< FOEN9 (Bit 27)                                        */
31549 #define GPIO_PINCFG9_FOEN9_Msk            (0x8000000UL)             /*!< FOEN9 (Bitfield-Mask: 0x01)                           */
31550 #define GPIO_PINCFG9_FIEN9_Pos            (26UL)                    /*!< FIEN9 (Bit 26)                                        */
31551 #define GPIO_PINCFG9_FIEN9_Msk            (0x4000000UL)             /*!< FIEN9 (Bitfield-Mask: 0x01)                           */
31552 #define GPIO_PINCFG9_NCEPOL9_Pos          (22UL)                    /*!< NCEPOL9 (Bit 22)                                      */
31553 #define GPIO_PINCFG9_NCEPOL9_Msk          (0x400000UL)              /*!< NCEPOL9 (Bitfield-Mask: 0x01)                         */
31554 #define GPIO_PINCFG9_NCESRC9_Pos          (16UL)                    /*!< NCESRC9 (Bit 16)                                      */
31555 #define GPIO_PINCFG9_NCESRC9_Msk          (0x3f0000UL)              /*!< NCESRC9 (Bitfield-Mask: 0x3f)                         */
31556 #define GPIO_PINCFG9_PULLCFG9_Pos         (13UL)                    /*!< PULLCFG9 (Bit 13)                                     */
31557 #define GPIO_PINCFG9_PULLCFG9_Msk         (0xe000UL)                /*!< PULLCFG9 (Bitfield-Mask: 0x07)                        */
31558 #define GPIO_PINCFG9_SR9_Pos              (12UL)                    /*!< SR9 (Bit 12)                                          */
31559 #define GPIO_PINCFG9_SR9_Msk              (0x1000UL)                /*!< SR9 (Bitfield-Mask: 0x01)                             */
31560 #define GPIO_PINCFG9_DS9_Pos              (10UL)                    /*!< DS9 (Bit 10)                                          */
31561 #define GPIO_PINCFG9_DS9_Msk              (0xc00UL)                 /*!< DS9 (Bitfield-Mask: 0x03)                             */
31562 #define GPIO_PINCFG9_OUTCFG9_Pos          (8UL)                     /*!< OUTCFG9 (Bit 8)                                       */
31563 #define GPIO_PINCFG9_OUTCFG9_Msk          (0x300UL)                 /*!< OUTCFG9 (Bitfield-Mask: 0x03)                         */
31564 #define GPIO_PINCFG9_IRPTEN9_Pos          (6UL)                     /*!< IRPTEN9 (Bit 6)                                       */
31565 #define GPIO_PINCFG9_IRPTEN9_Msk          (0xc0UL)                  /*!< IRPTEN9 (Bitfield-Mask: 0x03)                         */
31566 #define GPIO_PINCFG9_RDZERO9_Pos          (5UL)                     /*!< RDZERO9 (Bit 5)                                       */
31567 #define GPIO_PINCFG9_RDZERO9_Msk          (0x20UL)                  /*!< RDZERO9 (Bitfield-Mask: 0x01)                         */
31568 #define GPIO_PINCFG9_INPEN9_Pos           (4UL)                     /*!< INPEN9 (Bit 4)                                        */
31569 #define GPIO_PINCFG9_INPEN9_Msk           (0x10UL)                  /*!< INPEN9 (Bitfield-Mask: 0x01)                          */
31570 #define GPIO_PINCFG9_FNCSEL9_Pos          (0UL)                     /*!< FNCSEL9 (Bit 0)                                       */
31571 #define GPIO_PINCFG9_FNCSEL9_Msk          (0xfUL)                   /*!< FNCSEL9 (Bitfield-Mask: 0x0f)                         */
31572 /* =======================================================  PINCFG10  ======================================================== */
31573 #define GPIO_PINCFG10_FOEN10_Pos          (27UL)                    /*!< FOEN10 (Bit 27)                                       */
31574 #define GPIO_PINCFG10_FOEN10_Msk          (0x8000000UL)             /*!< FOEN10 (Bitfield-Mask: 0x01)                          */
31575 #define GPIO_PINCFG10_FIEN10_Pos          (26UL)                    /*!< FIEN10 (Bit 26)                                       */
31576 #define GPIO_PINCFG10_FIEN10_Msk          (0x4000000UL)             /*!< FIEN10 (Bitfield-Mask: 0x01)                          */
31577 #define GPIO_PINCFG10_NCEPOL10_Pos        (22UL)                    /*!< NCEPOL10 (Bit 22)                                     */
31578 #define GPIO_PINCFG10_NCEPOL10_Msk        (0x400000UL)              /*!< NCEPOL10 (Bitfield-Mask: 0x01)                        */
31579 #define GPIO_PINCFG10_NCESRC10_Pos        (16UL)                    /*!< NCESRC10 (Bit 16)                                     */
31580 #define GPIO_PINCFG10_NCESRC10_Msk        (0x3f0000UL)              /*!< NCESRC10 (Bitfield-Mask: 0x3f)                        */
31581 #define GPIO_PINCFG10_PULLCFG10_Pos       (13UL)                    /*!< PULLCFG10 (Bit 13)                                    */
31582 #define GPIO_PINCFG10_PULLCFG10_Msk       (0xe000UL)                /*!< PULLCFG10 (Bitfield-Mask: 0x07)                       */
31583 #define GPIO_PINCFG10_SR10_Pos            (12UL)                    /*!< SR10 (Bit 12)                                         */
31584 #define GPIO_PINCFG10_SR10_Msk            (0x1000UL)                /*!< SR10 (Bitfield-Mask: 0x01)                            */
31585 #define GPIO_PINCFG10_DS10_Pos            (10UL)                    /*!< DS10 (Bit 10)                                         */
31586 #define GPIO_PINCFG10_DS10_Msk            (0xc00UL)                 /*!< DS10 (Bitfield-Mask: 0x03)                            */
31587 #define GPIO_PINCFG10_OUTCFG10_Pos        (8UL)                     /*!< OUTCFG10 (Bit 8)                                      */
31588 #define GPIO_PINCFG10_OUTCFG10_Msk        (0x300UL)                 /*!< OUTCFG10 (Bitfield-Mask: 0x03)                        */
31589 #define GPIO_PINCFG10_IRPTEN10_Pos        (6UL)                     /*!< IRPTEN10 (Bit 6)                                      */
31590 #define GPIO_PINCFG10_IRPTEN10_Msk        (0xc0UL)                  /*!< IRPTEN10 (Bitfield-Mask: 0x03)                        */
31591 #define GPIO_PINCFG10_RDZERO10_Pos        (5UL)                     /*!< RDZERO10 (Bit 5)                                      */
31592 #define GPIO_PINCFG10_RDZERO10_Msk        (0x20UL)                  /*!< RDZERO10 (Bitfield-Mask: 0x01)                        */
31593 #define GPIO_PINCFG10_INPEN10_Pos         (4UL)                     /*!< INPEN10 (Bit 4)                                       */
31594 #define GPIO_PINCFG10_INPEN10_Msk         (0x10UL)                  /*!< INPEN10 (Bitfield-Mask: 0x01)                         */
31595 #define GPIO_PINCFG10_FNCSEL10_Pos        (0UL)                     /*!< FNCSEL10 (Bit 0)                                      */
31596 #define GPIO_PINCFG10_FNCSEL10_Msk        (0xfUL)                   /*!< FNCSEL10 (Bitfield-Mask: 0x0f)                        */
31597 /* =======================================================  PINCFG11  ======================================================== */
31598 #define GPIO_PINCFG11_FOEN11_Pos          (27UL)                    /*!< FOEN11 (Bit 27)                                       */
31599 #define GPIO_PINCFG11_FOEN11_Msk          (0x8000000UL)             /*!< FOEN11 (Bitfield-Mask: 0x01)                          */
31600 #define GPIO_PINCFG11_FIEN11_Pos          (26UL)                    /*!< FIEN11 (Bit 26)                                       */
31601 #define GPIO_PINCFG11_FIEN11_Msk          (0x4000000UL)             /*!< FIEN11 (Bitfield-Mask: 0x01)                          */
31602 #define GPIO_PINCFG11_NCEPOL11_Pos        (22UL)                    /*!< NCEPOL11 (Bit 22)                                     */
31603 #define GPIO_PINCFG11_NCEPOL11_Msk        (0x400000UL)              /*!< NCEPOL11 (Bitfield-Mask: 0x01)                        */
31604 #define GPIO_PINCFG11_NCESRC11_Pos        (16UL)                    /*!< NCESRC11 (Bit 16)                                     */
31605 #define GPIO_PINCFG11_NCESRC11_Msk        (0x3f0000UL)              /*!< NCESRC11 (Bitfield-Mask: 0x3f)                        */
31606 #define GPIO_PINCFG11_PULLCFG11_Pos       (13UL)                    /*!< PULLCFG11 (Bit 13)                                    */
31607 #define GPIO_PINCFG11_PULLCFG11_Msk       (0xe000UL)                /*!< PULLCFG11 (Bitfield-Mask: 0x07)                       */
31608 #define GPIO_PINCFG11_SR11_Pos            (12UL)                    /*!< SR11 (Bit 12)                                         */
31609 #define GPIO_PINCFG11_SR11_Msk            (0x1000UL)                /*!< SR11 (Bitfield-Mask: 0x01)                            */
31610 #define GPIO_PINCFG11_DS11_Pos            (10UL)                    /*!< DS11 (Bit 10)                                         */
31611 #define GPIO_PINCFG11_DS11_Msk            (0xc00UL)                 /*!< DS11 (Bitfield-Mask: 0x03)                            */
31612 #define GPIO_PINCFG11_OUTCFG11_Pos        (8UL)                     /*!< OUTCFG11 (Bit 8)                                      */
31613 #define GPIO_PINCFG11_OUTCFG11_Msk        (0x300UL)                 /*!< OUTCFG11 (Bitfield-Mask: 0x03)                        */
31614 #define GPIO_PINCFG11_IRPTEN11_Pos        (6UL)                     /*!< IRPTEN11 (Bit 6)                                      */
31615 #define GPIO_PINCFG11_IRPTEN11_Msk        (0xc0UL)                  /*!< IRPTEN11 (Bitfield-Mask: 0x03)                        */
31616 #define GPIO_PINCFG11_RDZERO11_Pos        (5UL)                     /*!< RDZERO11 (Bit 5)                                      */
31617 #define GPIO_PINCFG11_RDZERO11_Msk        (0x20UL)                  /*!< RDZERO11 (Bitfield-Mask: 0x01)                        */
31618 #define GPIO_PINCFG11_INPEN11_Pos         (4UL)                     /*!< INPEN11 (Bit 4)                                       */
31619 #define GPIO_PINCFG11_INPEN11_Msk         (0x10UL)                  /*!< INPEN11 (Bitfield-Mask: 0x01)                         */
31620 #define GPIO_PINCFG11_FNCSEL11_Pos        (0UL)                     /*!< FNCSEL11 (Bit 0)                                      */
31621 #define GPIO_PINCFG11_FNCSEL11_Msk        (0xfUL)                   /*!< FNCSEL11 (Bitfield-Mask: 0x0f)                        */
31622 /* =======================================================  PINCFG12  ======================================================== */
31623 #define GPIO_PINCFG12_FOEN12_Pos          (27UL)                    /*!< FOEN12 (Bit 27)                                       */
31624 #define GPIO_PINCFG12_FOEN12_Msk          (0x8000000UL)             /*!< FOEN12 (Bitfield-Mask: 0x01)                          */
31625 #define GPIO_PINCFG12_FIEN12_Pos          (26UL)                    /*!< FIEN12 (Bit 26)                                       */
31626 #define GPIO_PINCFG12_FIEN12_Msk          (0x4000000UL)             /*!< FIEN12 (Bitfield-Mask: 0x01)                          */
31627 #define GPIO_PINCFG12_NCEPOL12_Pos        (22UL)                    /*!< NCEPOL12 (Bit 22)                                     */
31628 #define GPIO_PINCFG12_NCEPOL12_Msk        (0x400000UL)              /*!< NCEPOL12 (Bitfield-Mask: 0x01)                        */
31629 #define GPIO_PINCFG12_NCESRC12_Pos        (16UL)                    /*!< NCESRC12 (Bit 16)                                     */
31630 #define GPIO_PINCFG12_NCESRC12_Msk        (0x3f0000UL)              /*!< NCESRC12 (Bitfield-Mask: 0x3f)                        */
31631 #define GPIO_PINCFG12_PULLCFG12_Pos       (13UL)                    /*!< PULLCFG12 (Bit 13)                                    */
31632 #define GPIO_PINCFG12_PULLCFG12_Msk       (0xe000UL)                /*!< PULLCFG12 (Bitfield-Mask: 0x07)                       */
31633 #define GPIO_PINCFG12_SR12_Pos            (12UL)                    /*!< SR12 (Bit 12)                                         */
31634 #define GPIO_PINCFG12_SR12_Msk            (0x1000UL)                /*!< SR12 (Bitfield-Mask: 0x01)                            */
31635 #define GPIO_PINCFG12_DS12_Pos            (10UL)                    /*!< DS12 (Bit 10)                                         */
31636 #define GPIO_PINCFG12_DS12_Msk            (0xc00UL)                 /*!< DS12 (Bitfield-Mask: 0x03)                            */
31637 #define GPIO_PINCFG12_OUTCFG12_Pos        (8UL)                     /*!< OUTCFG12 (Bit 8)                                      */
31638 #define GPIO_PINCFG12_OUTCFG12_Msk        (0x300UL)                 /*!< OUTCFG12 (Bitfield-Mask: 0x03)                        */
31639 #define GPIO_PINCFG12_IRPTEN12_Pos        (6UL)                     /*!< IRPTEN12 (Bit 6)                                      */
31640 #define GPIO_PINCFG12_IRPTEN12_Msk        (0xc0UL)                  /*!< IRPTEN12 (Bitfield-Mask: 0x03)                        */
31641 #define GPIO_PINCFG12_RDZERO12_Pos        (5UL)                     /*!< RDZERO12 (Bit 5)                                      */
31642 #define GPIO_PINCFG12_RDZERO12_Msk        (0x20UL)                  /*!< RDZERO12 (Bitfield-Mask: 0x01)                        */
31643 #define GPIO_PINCFG12_INPEN12_Pos         (4UL)                     /*!< INPEN12 (Bit 4)                                       */
31644 #define GPIO_PINCFG12_INPEN12_Msk         (0x10UL)                  /*!< INPEN12 (Bitfield-Mask: 0x01)                         */
31645 #define GPIO_PINCFG12_FNCSEL12_Pos        (0UL)                     /*!< FNCSEL12 (Bit 0)                                      */
31646 #define GPIO_PINCFG12_FNCSEL12_Msk        (0xfUL)                   /*!< FNCSEL12 (Bitfield-Mask: 0x0f)                        */
31647 /* =======================================================  PINCFG13  ======================================================== */
31648 #define GPIO_PINCFG13_FOEN13_Pos          (27UL)                    /*!< FOEN13 (Bit 27)                                       */
31649 #define GPIO_PINCFG13_FOEN13_Msk          (0x8000000UL)             /*!< FOEN13 (Bitfield-Mask: 0x01)                          */
31650 #define GPIO_PINCFG13_FIEN13_Pos          (26UL)                    /*!< FIEN13 (Bit 26)                                       */
31651 #define GPIO_PINCFG13_FIEN13_Msk          (0x4000000UL)             /*!< FIEN13 (Bitfield-Mask: 0x01)                          */
31652 #define GPIO_PINCFG13_NCEPOL13_Pos        (22UL)                    /*!< NCEPOL13 (Bit 22)                                     */
31653 #define GPIO_PINCFG13_NCEPOL13_Msk        (0x400000UL)              /*!< NCEPOL13 (Bitfield-Mask: 0x01)                        */
31654 #define GPIO_PINCFG13_NCESRC13_Pos        (16UL)                    /*!< NCESRC13 (Bit 16)                                     */
31655 #define GPIO_PINCFG13_NCESRC13_Msk        (0x3f0000UL)              /*!< NCESRC13 (Bitfield-Mask: 0x3f)                        */
31656 #define GPIO_PINCFG13_PULLCFG13_Pos       (13UL)                    /*!< PULLCFG13 (Bit 13)                                    */
31657 #define GPIO_PINCFG13_PULLCFG13_Msk       (0xe000UL)                /*!< PULLCFG13 (Bitfield-Mask: 0x07)                       */
31658 #define GPIO_PINCFG13_SR13_Pos            (12UL)                    /*!< SR13 (Bit 12)                                         */
31659 #define GPIO_PINCFG13_SR13_Msk            (0x1000UL)                /*!< SR13 (Bitfield-Mask: 0x01)                            */
31660 #define GPIO_PINCFG13_DS13_Pos            (10UL)                    /*!< DS13 (Bit 10)                                         */
31661 #define GPIO_PINCFG13_DS13_Msk            (0xc00UL)                 /*!< DS13 (Bitfield-Mask: 0x03)                            */
31662 #define GPIO_PINCFG13_OUTCFG13_Pos        (8UL)                     /*!< OUTCFG13 (Bit 8)                                      */
31663 #define GPIO_PINCFG13_OUTCFG13_Msk        (0x300UL)                 /*!< OUTCFG13 (Bitfield-Mask: 0x03)                        */
31664 #define GPIO_PINCFG13_IRPTEN13_Pos        (6UL)                     /*!< IRPTEN13 (Bit 6)                                      */
31665 #define GPIO_PINCFG13_IRPTEN13_Msk        (0xc0UL)                  /*!< IRPTEN13 (Bitfield-Mask: 0x03)                        */
31666 #define GPIO_PINCFG13_RDZERO13_Pos        (5UL)                     /*!< RDZERO13 (Bit 5)                                      */
31667 #define GPIO_PINCFG13_RDZERO13_Msk        (0x20UL)                  /*!< RDZERO13 (Bitfield-Mask: 0x01)                        */
31668 #define GPIO_PINCFG13_INPEN13_Pos         (4UL)                     /*!< INPEN13 (Bit 4)                                       */
31669 #define GPIO_PINCFG13_INPEN13_Msk         (0x10UL)                  /*!< INPEN13 (Bitfield-Mask: 0x01)                         */
31670 #define GPIO_PINCFG13_FNCSEL13_Pos        (0UL)                     /*!< FNCSEL13 (Bit 0)                                      */
31671 #define GPIO_PINCFG13_FNCSEL13_Msk        (0xfUL)                   /*!< FNCSEL13 (Bitfield-Mask: 0x0f)                        */
31672 /* =======================================================  PINCFG14  ======================================================== */
31673 #define GPIO_PINCFG14_FOEN14_Pos          (27UL)                    /*!< FOEN14 (Bit 27)                                       */
31674 #define GPIO_PINCFG14_FOEN14_Msk          (0x8000000UL)             /*!< FOEN14 (Bitfield-Mask: 0x01)                          */
31675 #define GPIO_PINCFG14_FIEN14_Pos          (26UL)                    /*!< FIEN14 (Bit 26)                                       */
31676 #define GPIO_PINCFG14_FIEN14_Msk          (0x4000000UL)             /*!< FIEN14 (Bitfield-Mask: 0x01)                          */
31677 #define GPIO_PINCFG14_NCEPOL14_Pos        (22UL)                    /*!< NCEPOL14 (Bit 22)                                     */
31678 #define GPIO_PINCFG14_NCEPOL14_Msk        (0x400000UL)              /*!< NCEPOL14 (Bitfield-Mask: 0x01)                        */
31679 #define GPIO_PINCFG14_NCESRC14_Pos        (16UL)                    /*!< NCESRC14 (Bit 16)                                     */
31680 #define GPIO_PINCFG14_NCESRC14_Msk        (0x3f0000UL)              /*!< NCESRC14 (Bitfield-Mask: 0x3f)                        */
31681 #define GPIO_PINCFG14_PULLCFG14_Pos       (13UL)                    /*!< PULLCFG14 (Bit 13)                                    */
31682 #define GPIO_PINCFG14_PULLCFG14_Msk       (0xe000UL)                /*!< PULLCFG14 (Bitfield-Mask: 0x07)                       */
31683 #define GPIO_PINCFG14_SR14_Pos            (12UL)                    /*!< SR14 (Bit 12)                                         */
31684 #define GPIO_PINCFG14_SR14_Msk            (0x1000UL)                /*!< SR14 (Bitfield-Mask: 0x01)                            */
31685 #define GPIO_PINCFG14_DS14_Pos            (10UL)                    /*!< DS14 (Bit 10)                                         */
31686 #define GPIO_PINCFG14_DS14_Msk            (0xc00UL)                 /*!< DS14 (Bitfield-Mask: 0x03)                            */
31687 #define GPIO_PINCFG14_OUTCFG14_Pos        (8UL)                     /*!< OUTCFG14 (Bit 8)                                      */
31688 #define GPIO_PINCFG14_OUTCFG14_Msk        (0x300UL)                 /*!< OUTCFG14 (Bitfield-Mask: 0x03)                        */
31689 #define GPIO_PINCFG14_IRPTEN14_Pos        (6UL)                     /*!< IRPTEN14 (Bit 6)                                      */
31690 #define GPIO_PINCFG14_IRPTEN14_Msk        (0xc0UL)                  /*!< IRPTEN14 (Bitfield-Mask: 0x03)                        */
31691 #define GPIO_PINCFG14_RDZERO14_Pos        (5UL)                     /*!< RDZERO14 (Bit 5)                                      */
31692 #define GPIO_PINCFG14_RDZERO14_Msk        (0x20UL)                  /*!< RDZERO14 (Bitfield-Mask: 0x01)                        */
31693 #define GPIO_PINCFG14_INPEN14_Pos         (4UL)                     /*!< INPEN14 (Bit 4)                                       */
31694 #define GPIO_PINCFG14_INPEN14_Msk         (0x10UL)                  /*!< INPEN14 (Bitfield-Mask: 0x01)                         */
31695 #define GPIO_PINCFG14_FNCSEL14_Pos        (0UL)                     /*!< FNCSEL14 (Bit 0)                                      */
31696 #define GPIO_PINCFG14_FNCSEL14_Msk        (0xfUL)                   /*!< FNCSEL14 (Bitfield-Mask: 0x0f)                        */
31697 /* =======================================================  PINCFG15  ======================================================== */
31698 #define GPIO_PINCFG15_FOEN15_Pos          (27UL)                    /*!< FOEN15 (Bit 27)                                       */
31699 #define GPIO_PINCFG15_FOEN15_Msk          (0x8000000UL)             /*!< FOEN15 (Bitfield-Mask: 0x01)                          */
31700 #define GPIO_PINCFG15_FIEN15_Pos          (26UL)                    /*!< FIEN15 (Bit 26)                                       */
31701 #define GPIO_PINCFG15_FIEN15_Msk          (0x4000000UL)             /*!< FIEN15 (Bitfield-Mask: 0x01)                          */
31702 #define GPIO_PINCFG15_NCEPOL15_Pos        (22UL)                    /*!< NCEPOL15 (Bit 22)                                     */
31703 #define GPIO_PINCFG15_NCEPOL15_Msk        (0x400000UL)              /*!< NCEPOL15 (Bitfield-Mask: 0x01)                        */
31704 #define GPIO_PINCFG15_NCESRC15_Pos        (16UL)                    /*!< NCESRC15 (Bit 16)                                     */
31705 #define GPIO_PINCFG15_NCESRC15_Msk        (0x3f0000UL)              /*!< NCESRC15 (Bitfield-Mask: 0x3f)                        */
31706 #define GPIO_PINCFG15_PULLCFG15_Pos       (13UL)                    /*!< PULLCFG15 (Bit 13)                                    */
31707 #define GPIO_PINCFG15_PULLCFG15_Msk       (0xe000UL)                /*!< PULLCFG15 (Bitfield-Mask: 0x07)                       */
31708 #define GPIO_PINCFG15_SR15_Pos            (12UL)                    /*!< SR15 (Bit 12)                                         */
31709 #define GPIO_PINCFG15_SR15_Msk            (0x1000UL)                /*!< SR15 (Bitfield-Mask: 0x01)                            */
31710 #define GPIO_PINCFG15_DS15_Pos            (10UL)                    /*!< DS15 (Bit 10)                                         */
31711 #define GPIO_PINCFG15_DS15_Msk            (0xc00UL)                 /*!< DS15 (Bitfield-Mask: 0x03)                            */
31712 #define GPIO_PINCFG15_OUTCFG15_Pos        (8UL)                     /*!< OUTCFG15 (Bit 8)                                      */
31713 #define GPIO_PINCFG15_OUTCFG15_Msk        (0x300UL)                 /*!< OUTCFG15 (Bitfield-Mask: 0x03)                        */
31714 #define GPIO_PINCFG15_IRPTEN15_Pos        (6UL)                     /*!< IRPTEN15 (Bit 6)                                      */
31715 #define GPIO_PINCFG15_IRPTEN15_Msk        (0xc0UL)                  /*!< IRPTEN15 (Bitfield-Mask: 0x03)                        */
31716 #define GPIO_PINCFG15_RDZERO15_Pos        (5UL)                     /*!< RDZERO15 (Bit 5)                                      */
31717 #define GPIO_PINCFG15_RDZERO15_Msk        (0x20UL)                  /*!< RDZERO15 (Bitfield-Mask: 0x01)                        */
31718 #define GPIO_PINCFG15_INPEN15_Pos         (4UL)                     /*!< INPEN15 (Bit 4)                                       */
31719 #define GPIO_PINCFG15_INPEN15_Msk         (0x10UL)                  /*!< INPEN15 (Bitfield-Mask: 0x01)                         */
31720 #define GPIO_PINCFG15_FNCSEL15_Pos        (0UL)                     /*!< FNCSEL15 (Bit 0)                                      */
31721 #define GPIO_PINCFG15_FNCSEL15_Msk        (0xfUL)                   /*!< FNCSEL15 (Bitfield-Mask: 0x0f)                        */
31722 /* =======================================================  PINCFG16  ======================================================== */
31723 #define GPIO_PINCFG16_FOEN16_Pos          (27UL)                    /*!< FOEN16 (Bit 27)                                       */
31724 #define GPIO_PINCFG16_FOEN16_Msk          (0x8000000UL)             /*!< FOEN16 (Bitfield-Mask: 0x01)                          */
31725 #define GPIO_PINCFG16_FIEN16_Pos          (26UL)                    /*!< FIEN16 (Bit 26)                                       */
31726 #define GPIO_PINCFG16_FIEN16_Msk          (0x4000000UL)             /*!< FIEN16 (Bitfield-Mask: 0x01)                          */
31727 #define GPIO_PINCFG16_NCEPOL16_Pos        (22UL)                    /*!< NCEPOL16 (Bit 22)                                     */
31728 #define GPIO_PINCFG16_NCEPOL16_Msk        (0x400000UL)              /*!< NCEPOL16 (Bitfield-Mask: 0x01)                        */
31729 #define GPIO_PINCFG16_NCESRC16_Pos        (16UL)                    /*!< NCESRC16 (Bit 16)                                     */
31730 #define GPIO_PINCFG16_NCESRC16_Msk        (0x3f0000UL)              /*!< NCESRC16 (Bitfield-Mask: 0x3f)                        */
31731 #define GPIO_PINCFG16_PULLCFG16_Pos       (13UL)                    /*!< PULLCFG16 (Bit 13)                                    */
31732 #define GPIO_PINCFG16_PULLCFG16_Msk       (0xe000UL)                /*!< PULLCFG16 (Bitfield-Mask: 0x07)                       */
31733 #define GPIO_PINCFG16_SR16_Pos            (12UL)                    /*!< SR16 (Bit 12)                                         */
31734 #define GPIO_PINCFG16_SR16_Msk            (0x1000UL)                /*!< SR16 (Bitfield-Mask: 0x01)                            */
31735 #define GPIO_PINCFG16_DS16_Pos            (10UL)                    /*!< DS16 (Bit 10)                                         */
31736 #define GPIO_PINCFG16_DS16_Msk            (0xc00UL)                 /*!< DS16 (Bitfield-Mask: 0x03)                            */
31737 #define GPIO_PINCFG16_OUTCFG16_Pos        (8UL)                     /*!< OUTCFG16 (Bit 8)                                      */
31738 #define GPIO_PINCFG16_OUTCFG16_Msk        (0x300UL)                 /*!< OUTCFG16 (Bitfield-Mask: 0x03)                        */
31739 #define GPIO_PINCFG16_IRPTEN16_Pos        (6UL)                     /*!< IRPTEN16 (Bit 6)                                      */
31740 #define GPIO_PINCFG16_IRPTEN16_Msk        (0xc0UL)                  /*!< IRPTEN16 (Bitfield-Mask: 0x03)                        */
31741 #define GPIO_PINCFG16_RDZERO16_Pos        (5UL)                     /*!< RDZERO16 (Bit 5)                                      */
31742 #define GPIO_PINCFG16_RDZERO16_Msk        (0x20UL)                  /*!< RDZERO16 (Bitfield-Mask: 0x01)                        */
31743 #define GPIO_PINCFG16_INPEN16_Pos         (4UL)                     /*!< INPEN16 (Bit 4)                                       */
31744 #define GPIO_PINCFG16_INPEN16_Msk         (0x10UL)                  /*!< INPEN16 (Bitfield-Mask: 0x01)                         */
31745 #define GPIO_PINCFG16_FNCSEL16_Pos        (0UL)                     /*!< FNCSEL16 (Bit 0)                                      */
31746 #define GPIO_PINCFG16_FNCSEL16_Msk        (0xfUL)                   /*!< FNCSEL16 (Bitfield-Mask: 0x0f)                        */
31747 /* =======================================================  PINCFG17  ======================================================== */
31748 #define GPIO_PINCFG17_FOEN17_Pos          (27UL)                    /*!< FOEN17 (Bit 27)                                       */
31749 #define GPIO_PINCFG17_FOEN17_Msk          (0x8000000UL)             /*!< FOEN17 (Bitfield-Mask: 0x01)                          */
31750 #define GPIO_PINCFG17_FIEN17_Pos          (26UL)                    /*!< FIEN17 (Bit 26)                                       */
31751 #define GPIO_PINCFG17_FIEN17_Msk          (0x4000000UL)             /*!< FIEN17 (Bitfield-Mask: 0x01)                          */
31752 #define GPIO_PINCFG17_NCEPOL17_Pos        (22UL)                    /*!< NCEPOL17 (Bit 22)                                     */
31753 #define GPIO_PINCFG17_NCEPOL17_Msk        (0x400000UL)              /*!< NCEPOL17 (Bitfield-Mask: 0x01)                        */
31754 #define GPIO_PINCFG17_NCESRC17_Pos        (16UL)                    /*!< NCESRC17 (Bit 16)                                     */
31755 #define GPIO_PINCFG17_NCESRC17_Msk        (0x3f0000UL)              /*!< NCESRC17 (Bitfield-Mask: 0x3f)                        */
31756 #define GPIO_PINCFG17_PULLCFG17_Pos       (13UL)                    /*!< PULLCFG17 (Bit 13)                                    */
31757 #define GPIO_PINCFG17_PULLCFG17_Msk       (0xe000UL)                /*!< PULLCFG17 (Bitfield-Mask: 0x07)                       */
31758 #define GPIO_PINCFG17_SR17_Pos            (12UL)                    /*!< SR17 (Bit 12)                                         */
31759 #define GPIO_PINCFG17_SR17_Msk            (0x1000UL)                /*!< SR17 (Bitfield-Mask: 0x01)                            */
31760 #define GPIO_PINCFG17_DS17_Pos            (10UL)                    /*!< DS17 (Bit 10)                                         */
31761 #define GPIO_PINCFG17_DS17_Msk            (0xc00UL)                 /*!< DS17 (Bitfield-Mask: 0x03)                            */
31762 #define GPIO_PINCFG17_OUTCFG17_Pos        (8UL)                     /*!< OUTCFG17 (Bit 8)                                      */
31763 #define GPIO_PINCFG17_OUTCFG17_Msk        (0x300UL)                 /*!< OUTCFG17 (Bitfield-Mask: 0x03)                        */
31764 #define GPIO_PINCFG17_IRPTEN17_Pos        (6UL)                     /*!< IRPTEN17 (Bit 6)                                      */
31765 #define GPIO_PINCFG17_IRPTEN17_Msk        (0xc0UL)                  /*!< IRPTEN17 (Bitfield-Mask: 0x03)                        */
31766 #define GPIO_PINCFG17_RDZERO17_Pos        (5UL)                     /*!< RDZERO17 (Bit 5)                                      */
31767 #define GPIO_PINCFG17_RDZERO17_Msk        (0x20UL)                  /*!< RDZERO17 (Bitfield-Mask: 0x01)                        */
31768 #define GPIO_PINCFG17_INPEN17_Pos         (4UL)                     /*!< INPEN17 (Bit 4)                                       */
31769 #define GPIO_PINCFG17_INPEN17_Msk         (0x10UL)                  /*!< INPEN17 (Bitfield-Mask: 0x01)                         */
31770 #define GPIO_PINCFG17_FNCSEL17_Pos        (0UL)                     /*!< FNCSEL17 (Bit 0)                                      */
31771 #define GPIO_PINCFG17_FNCSEL17_Msk        (0xfUL)                   /*!< FNCSEL17 (Bitfield-Mask: 0x0f)                        */
31772 /* =======================================================  PINCFG18  ======================================================== */
31773 #define GPIO_PINCFG18_FOEN18_Pos          (27UL)                    /*!< FOEN18 (Bit 27)                                       */
31774 #define GPIO_PINCFG18_FOEN18_Msk          (0x8000000UL)             /*!< FOEN18 (Bitfield-Mask: 0x01)                          */
31775 #define GPIO_PINCFG18_FIEN18_Pos          (26UL)                    /*!< FIEN18 (Bit 26)                                       */
31776 #define GPIO_PINCFG18_FIEN18_Msk          (0x4000000UL)             /*!< FIEN18 (Bitfield-Mask: 0x01)                          */
31777 #define GPIO_PINCFG18_NCEPOL18_Pos        (22UL)                    /*!< NCEPOL18 (Bit 22)                                     */
31778 #define GPIO_PINCFG18_NCEPOL18_Msk        (0x400000UL)              /*!< NCEPOL18 (Bitfield-Mask: 0x01)                        */
31779 #define GPIO_PINCFG18_NCESRC18_Pos        (16UL)                    /*!< NCESRC18 (Bit 16)                                     */
31780 #define GPIO_PINCFG18_NCESRC18_Msk        (0x3f0000UL)              /*!< NCESRC18 (Bitfield-Mask: 0x3f)                        */
31781 #define GPIO_PINCFG18_PULLCFG18_Pos       (13UL)                    /*!< PULLCFG18 (Bit 13)                                    */
31782 #define GPIO_PINCFG18_PULLCFG18_Msk       (0xe000UL)                /*!< PULLCFG18 (Bitfield-Mask: 0x07)                       */
31783 #define GPIO_PINCFG18_SR18_Pos            (12UL)                    /*!< SR18 (Bit 12)                                         */
31784 #define GPIO_PINCFG18_SR18_Msk            (0x1000UL)                /*!< SR18 (Bitfield-Mask: 0x01)                            */
31785 #define GPIO_PINCFG18_DS18_Pos            (10UL)                    /*!< DS18 (Bit 10)                                         */
31786 #define GPIO_PINCFG18_DS18_Msk            (0xc00UL)                 /*!< DS18 (Bitfield-Mask: 0x03)                            */
31787 #define GPIO_PINCFG18_OUTCFG18_Pos        (8UL)                     /*!< OUTCFG18 (Bit 8)                                      */
31788 #define GPIO_PINCFG18_OUTCFG18_Msk        (0x300UL)                 /*!< OUTCFG18 (Bitfield-Mask: 0x03)                        */
31789 #define GPIO_PINCFG18_IRPTEN18_Pos        (6UL)                     /*!< IRPTEN18 (Bit 6)                                      */
31790 #define GPIO_PINCFG18_IRPTEN18_Msk        (0xc0UL)                  /*!< IRPTEN18 (Bitfield-Mask: 0x03)                        */
31791 #define GPIO_PINCFG18_RDZERO18_Pos        (5UL)                     /*!< RDZERO18 (Bit 5)                                      */
31792 #define GPIO_PINCFG18_RDZERO18_Msk        (0x20UL)                  /*!< RDZERO18 (Bitfield-Mask: 0x01)                        */
31793 #define GPIO_PINCFG18_INPEN18_Pos         (4UL)                     /*!< INPEN18 (Bit 4)                                       */
31794 #define GPIO_PINCFG18_INPEN18_Msk         (0x10UL)                  /*!< INPEN18 (Bitfield-Mask: 0x01)                         */
31795 #define GPIO_PINCFG18_FNCSEL18_Pos        (0UL)                     /*!< FNCSEL18 (Bit 0)                                      */
31796 #define GPIO_PINCFG18_FNCSEL18_Msk        (0xfUL)                   /*!< FNCSEL18 (Bitfield-Mask: 0x0f)                        */
31797 /* =======================================================  PINCFG19  ======================================================== */
31798 #define GPIO_PINCFG19_FOEN19_Pos          (27UL)                    /*!< FOEN19 (Bit 27)                                       */
31799 #define GPIO_PINCFG19_FOEN19_Msk          (0x8000000UL)             /*!< FOEN19 (Bitfield-Mask: 0x01)                          */
31800 #define GPIO_PINCFG19_FIEN19_Pos          (26UL)                    /*!< FIEN19 (Bit 26)                                       */
31801 #define GPIO_PINCFG19_FIEN19_Msk          (0x4000000UL)             /*!< FIEN19 (Bitfield-Mask: 0x01)                          */
31802 #define GPIO_PINCFG19_NCEPOL19_Pos        (22UL)                    /*!< NCEPOL19 (Bit 22)                                     */
31803 #define GPIO_PINCFG19_NCEPOL19_Msk        (0x400000UL)              /*!< NCEPOL19 (Bitfield-Mask: 0x01)                        */
31804 #define GPIO_PINCFG19_NCESRC19_Pos        (16UL)                    /*!< NCESRC19 (Bit 16)                                     */
31805 #define GPIO_PINCFG19_NCESRC19_Msk        (0x3f0000UL)              /*!< NCESRC19 (Bitfield-Mask: 0x3f)                        */
31806 #define GPIO_PINCFG19_PULLCFG19_Pos       (13UL)                    /*!< PULLCFG19 (Bit 13)                                    */
31807 #define GPIO_PINCFG19_PULLCFG19_Msk       (0xe000UL)                /*!< PULLCFG19 (Bitfield-Mask: 0x07)                       */
31808 #define GPIO_PINCFG19_SR19_Pos            (12UL)                    /*!< SR19 (Bit 12)                                         */
31809 #define GPIO_PINCFG19_SR19_Msk            (0x1000UL)                /*!< SR19 (Bitfield-Mask: 0x01)                            */
31810 #define GPIO_PINCFG19_DS19_Pos            (10UL)                    /*!< DS19 (Bit 10)                                         */
31811 #define GPIO_PINCFG19_DS19_Msk            (0xc00UL)                 /*!< DS19 (Bitfield-Mask: 0x03)                            */
31812 #define GPIO_PINCFG19_OUTCFG19_Pos        (8UL)                     /*!< OUTCFG19 (Bit 8)                                      */
31813 #define GPIO_PINCFG19_OUTCFG19_Msk        (0x300UL)                 /*!< OUTCFG19 (Bitfield-Mask: 0x03)                        */
31814 #define GPIO_PINCFG19_IRPTEN19_Pos        (6UL)                     /*!< IRPTEN19 (Bit 6)                                      */
31815 #define GPIO_PINCFG19_IRPTEN19_Msk        (0xc0UL)                  /*!< IRPTEN19 (Bitfield-Mask: 0x03)                        */
31816 #define GPIO_PINCFG19_RDZERO19_Pos        (5UL)                     /*!< RDZERO19 (Bit 5)                                      */
31817 #define GPIO_PINCFG19_RDZERO19_Msk        (0x20UL)                  /*!< RDZERO19 (Bitfield-Mask: 0x01)                        */
31818 #define GPIO_PINCFG19_INPEN19_Pos         (4UL)                     /*!< INPEN19 (Bit 4)                                       */
31819 #define GPIO_PINCFG19_INPEN19_Msk         (0x10UL)                  /*!< INPEN19 (Bitfield-Mask: 0x01)                         */
31820 #define GPIO_PINCFG19_FNCSEL19_Pos        (0UL)                     /*!< FNCSEL19 (Bit 0)                                      */
31821 #define GPIO_PINCFG19_FNCSEL19_Msk        (0xfUL)                   /*!< FNCSEL19 (Bitfield-Mask: 0x0f)                        */
31822 /* =======================================================  PINCFG20  ======================================================== */
31823 #define GPIO_PINCFG20_FOEN20_Pos          (27UL)                    /*!< FOEN20 (Bit 27)                                       */
31824 #define GPIO_PINCFG20_FOEN20_Msk          (0x8000000UL)             /*!< FOEN20 (Bitfield-Mask: 0x01)                          */
31825 #define GPIO_PINCFG20_FIEN20_Pos          (26UL)                    /*!< FIEN20 (Bit 26)                                       */
31826 #define GPIO_PINCFG20_FIEN20_Msk          (0x4000000UL)             /*!< FIEN20 (Bitfield-Mask: 0x01)                          */
31827 #define GPIO_PINCFG20_NCEPOL20_Pos        (22UL)                    /*!< NCEPOL20 (Bit 22)                                     */
31828 #define GPIO_PINCFG20_NCEPOL20_Msk        (0x400000UL)              /*!< NCEPOL20 (Bitfield-Mask: 0x01)                        */
31829 #define GPIO_PINCFG20_NCESRC20_Pos        (16UL)                    /*!< NCESRC20 (Bit 16)                                     */
31830 #define GPIO_PINCFG20_NCESRC20_Msk        (0x3f0000UL)              /*!< NCESRC20 (Bitfield-Mask: 0x3f)                        */
31831 #define GPIO_PINCFG20_PULLCFG20_Pos       (13UL)                    /*!< PULLCFG20 (Bit 13)                                    */
31832 #define GPIO_PINCFG20_PULLCFG20_Msk       (0xe000UL)                /*!< PULLCFG20 (Bitfield-Mask: 0x07)                       */
31833 #define GPIO_PINCFG20_SR20_Pos            (12UL)                    /*!< SR20 (Bit 12)                                         */
31834 #define GPIO_PINCFG20_SR20_Msk            (0x1000UL)                /*!< SR20 (Bitfield-Mask: 0x01)                            */
31835 #define GPIO_PINCFG20_DS20_Pos            (10UL)                    /*!< DS20 (Bit 10)                                         */
31836 #define GPIO_PINCFG20_DS20_Msk            (0xc00UL)                 /*!< DS20 (Bitfield-Mask: 0x03)                            */
31837 #define GPIO_PINCFG20_OUTCFG20_Pos        (8UL)                     /*!< OUTCFG20 (Bit 8)                                      */
31838 #define GPIO_PINCFG20_OUTCFG20_Msk        (0x300UL)                 /*!< OUTCFG20 (Bitfield-Mask: 0x03)                        */
31839 #define GPIO_PINCFG20_IRPTEN20_Pos        (6UL)                     /*!< IRPTEN20 (Bit 6)                                      */
31840 #define GPIO_PINCFG20_IRPTEN20_Msk        (0xc0UL)                  /*!< IRPTEN20 (Bitfield-Mask: 0x03)                        */
31841 #define GPIO_PINCFG20_RDZERO20_Pos        (5UL)                     /*!< RDZERO20 (Bit 5)                                      */
31842 #define GPIO_PINCFG20_RDZERO20_Msk        (0x20UL)                  /*!< RDZERO20 (Bitfield-Mask: 0x01)                        */
31843 #define GPIO_PINCFG20_INPEN20_Pos         (4UL)                     /*!< INPEN20 (Bit 4)                                       */
31844 #define GPIO_PINCFG20_INPEN20_Msk         (0x10UL)                  /*!< INPEN20 (Bitfield-Mask: 0x01)                         */
31845 #define GPIO_PINCFG20_FNCSEL20_Pos        (0UL)                     /*!< FNCSEL20 (Bit 0)                                      */
31846 #define GPIO_PINCFG20_FNCSEL20_Msk        (0xfUL)                   /*!< FNCSEL20 (Bitfield-Mask: 0x0f)                        */
31847 /* =======================================================  PINCFG21  ======================================================== */
31848 #define GPIO_PINCFG21_FOEN21_Pos          (27UL)                    /*!< FOEN21 (Bit 27)                                       */
31849 #define GPIO_PINCFG21_FOEN21_Msk          (0x8000000UL)             /*!< FOEN21 (Bitfield-Mask: 0x01)                          */
31850 #define GPIO_PINCFG21_FIEN21_Pos          (26UL)                    /*!< FIEN21 (Bit 26)                                       */
31851 #define GPIO_PINCFG21_FIEN21_Msk          (0x4000000UL)             /*!< FIEN21 (Bitfield-Mask: 0x01)                          */
31852 #define GPIO_PINCFG21_NCEPOL21_Pos        (22UL)                    /*!< NCEPOL21 (Bit 22)                                     */
31853 #define GPIO_PINCFG21_NCEPOL21_Msk        (0x400000UL)              /*!< NCEPOL21 (Bitfield-Mask: 0x01)                        */
31854 #define GPIO_PINCFG21_NCESRC21_Pos        (16UL)                    /*!< NCESRC21 (Bit 16)                                     */
31855 #define GPIO_PINCFG21_NCESRC21_Msk        (0x3f0000UL)              /*!< NCESRC21 (Bitfield-Mask: 0x3f)                        */
31856 #define GPIO_PINCFG21_PULLCFG21_Pos       (13UL)                    /*!< PULLCFG21 (Bit 13)                                    */
31857 #define GPIO_PINCFG21_PULLCFG21_Msk       (0xe000UL)                /*!< PULLCFG21 (Bitfield-Mask: 0x07)                       */
31858 #define GPIO_PINCFG21_SR21_Pos            (12UL)                    /*!< SR21 (Bit 12)                                         */
31859 #define GPIO_PINCFG21_SR21_Msk            (0x1000UL)                /*!< SR21 (Bitfield-Mask: 0x01)                            */
31860 #define GPIO_PINCFG21_DS21_Pos            (10UL)                    /*!< DS21 (Bit 10)                                         */
31861 #define GPIO_PINCFG21_DS21_Msk            (0xc00UL)                 /*!< DS21 (Bitfield-Mask: 0x03)                            */
31862 #define GPIO_PINCFG21_OUTCFG21_Pos        (8UL)                     /*!< OUTCFG21 (Bit 8)                                      */
31863 #define GPIO_PINCFG21_OUTCFG21_Msk        (0x300UL)                 /*!< OUTCFG21 (Bitfield-Mask: 0x03)                        */
31864 #define GPIO_PINCFG21_IRPTEN21_Pos        (6UL)                     /*!< IRPTEN21 (Bit 6)                                      */
31865 #define GPIO_PINCFG21_IRPTEN21_Msk        (0xc0UL)                  /*!< IRPTEN21 (Bitfield-Mask: 0x03)                        */
31866 #define GPIO_PINCFG21_RDZERO21_Pos        (5UL)                     /*!< RDZERO21 (Bit 5)                                      */
31867 #define GPIO_PINCFG21_RDZERO21_Msk        (0x20UL)                  /*!< RDZERO21 (Bitfield-Mask: 0x01)                        */
31868 #define GPIO_PINCFG21_INPEN21_Pos         (4UL)                     /*!< INPEN21 (Bit 4)                                       */
31869 #define GPIO_PINCFG21_INPEN21_Msk         (0x10UL)                  /*!< INPEN21 (Bitfield-Mask: 0x01)                         */
31870 #define GPIO_PINCFG21_FNCSEL21_Pos        (0UL)                     /*!< FNCSEL21 (Bit 0)                                      */
31871 #define GPIO_PINCFG21_FNCSEL21_Msk        (0xfUL)                   /*!< FNCSEL21 (Bitfield-Mask: 0x0f)                        */
31872 /* =======================================================  PINCFG22  ======================================================== */
31873 #define GPIO_PINCFG22_FOEN22_Pos          (27UL)                    /*!< FOEN22 (Bit 27)                                       */
31874 #define GPIO_PINCFG22_FOEN22_Msk          (0x8000000UL)             /*!< FOEN22 (Bitfield-Mask: 0x01)                          */
31875 #define GPIO_PINCFG22_FIEN22_Pos          (26UL)                    /*!< FIEN22 (Bit 26)                                       */
31876 #define GPIO_PINCFG22_FIEN22_Msk          (0x4000000UL)             /*!< FIEN22 (Bitfield-Mask: 0x01)                          */
31877 #define GPIO_PINCFG22_NCEPOL22_Pos        (22UL)                    /*!< NCEPOL22 (Bit 22)                                     */
31878 #define GPIO_PINCFG22_NCEPOL22_Msk        (0x400000UL)              /*!< NCEPOL22 (Bitfield-Mask: 0x01)                        */
31879 #define GPIO_PINCFG22_NCESRC22_Pos        (16UL)                    /*!< NCESRC22 (Bit 16)                                     */
31880 #define GPIO_PINCFG22_NCESRC22_Msk        (0x3f0000UL)              /*!< NCESRC22 (Bitfield-Mask: 0x3f)                        */
31881 #define GPIO_PINCFG22_PULLCFG22_Pos       (13UL)                    /*!< PULLCFG22 (Bit 13)                                    */
31882 #define GPIO_PINCFG22_PULLCFG22_Msk       (0xe000UL)                /*!< PULLCFG22 (Bitfield-Mask: 0x07)                       */
31883 #define GPIO_PINCFG22_SR22_Pos            (12UL)                    /*!< SR22 (Bit 12)                                         */
31884 #define GPIO_PINCFG22_SR22_Msk            (0x1000UL)                /*!< SR22 (Bitfield-Mask: 0x01)                            */
31885 #define GPIO_PINCFG22_DS22_Pos            (10UL)                    /*!< DS22 (Bit 10)                                         */
31886 #define GPIO_PINCFG22_DS22_Msk            (0xc00UL)                 /*!< DS22 (Bitfield-Mask: 0x03)                            */
31887 #define GPIO_PINCFG22_OUTCFG22_Pos        (8UL)                     /*!< OUTCFG22 (Bit 8)                                      */
31888 #define GPIO_PINCFG22_OUTCFG22_Msk        (0x300UL)                 /*!< OUTCFG22 (Bitfield-Mask: 0x03)                        */
31889 #define GPIO_PINCFG22_IRPTEN22_Pos        (6UL)                     /*!< IRPTEN22 (Bit 6)                                      */
31890 #define GPIO_PINCFG22_IRPTEN22_Msk        (0xc0UL)                  /*!< IRPTEN22 (Bitfield-Mask: 0x03)                        */
31891 #define GPIO_PINCFG22_RDZERO22_Pos        (5UL)                     /*!< RDZERO22 (Bit 5)                                      */
31892 #define GPIO_PINCFG22_RDZERO22_Msk        (0x20UL)                  /*!< RDZERO22 (Bitfield-Mask: 0x01)                        */
31893 #define GPIO_PINCFG22_INPEN22_Pos         (4UL)                     /*!< INPEN22 (Bit 4)                                       */
31894 #define GPIO_PINCFG22_INPEN22_Msk         (0x10UL)                  /*!< INPEN22 (Bitfield-Mask: 0x01)                         */
31895 #define GPIO_PINCFG22_FNCSEL22_Pos        (0UL)                     /*!< FNCSEL22 (Bit 0)                                      */
31896 #define GPIO_PINCFG22_FNCSEL22_Msk        (0xfUL)                   /*!< FNCSEL22 (Bitfield-Mask: 0x0f)                        */
31897 /* =======================================================  PINCFG23  ======================================================== */
31898 #define GPIO_PINCFG23_FOEN23_Pos          (27UL)                    /*!< FOEN23 (Bit 27)                                       */
31899 #define GPIO_PINCFG23_FOEN23_Msk          (0x8000000UL)             /*!< FOEN23 (Bitfield-Mask: 0x01)                          */
31900 #define GPIO_PINCFG23_FIEN23_Pos          (26UL)                    /*!< FIEN23 (Bit 26)                                       */
31901 #define GPIO_PINCFG23_FIEN23_Msk          (0x4000000UL)             /*!< FIEN23 (Bitfield-Mask: 0x01)                          */
31902 #define GPIO_PINCFG23_NCEPOL23_Pos        (22UL)                    /*!< NCEPOL23 (Bit 22)                                     */
31903 #define GPIO_PINCFG23_NCEPOL23_Msk        (0x400000UL)              /*!< NCEPOL23 (Bitfield-Mask: 0x01)                        */
31904 #define GPIO_PINCFG23_NCESRC23_Pos        (16UL)                    /*!< NCESRC23 (Bit 16)                                     */
31905 #define GPIO_PINCFG23_NCESRC23_Msk        (0x3f0000UL)              /*!< NCESRC23 (Bitfield-Mask: 0x3f)                        */
31906 #define GPIO_PINCFG23_PULLCFG23_Pos       (13UL)                    /*!< PULLCFG23 (Bit 13)                                    */
31907 #define GPIO_PINCFG23_PULLCFG23_Msk       (0xe000UL)                /*!< PULLCFG23 (Bitfield-Mask: 0x07)                       */
31908 #define GPIO_PINCFG23_SR23_Pos            (12UL)                    /*!< SR23 (Bit 12)                                         */
31909 #define GPIO_PINCFG23_SR23_Msk            (0x1000UL)                /*!< SR23 (Bitfield-Mask: 0x01)                            */
31910 #define GPIO_PINCFG23_DS23_Pos            (10UL)                    /*!< DS23 (Bit 10)                                         */
31911 #define GPIO_PINCFG23_DS23_Msk            (0xc00UL)                 /*!< DS23 (Bitfield-Mask: 0x03)                            */
31912 #define GPIO_PINCFG23_OUTCFG23_Pos        (8UL)                     /*!< OUTCFG23 (Bit 8)                                      */
31913 #define GPIO_PINCFG23_OUTCFG23_Msk        (0x300UL)                 /*!< OUTCFG23 (Bitfield-Mask: 0x03)                        */
31914 #define GPIO_PINCFG23_IRPTEN23_Pos        (6UL)                     /*!< IRPTEN23 (Bit 6)                                      */
31915 #define GPIO_PINCFG23_IRPTEN23_Msk        (0xc0UL)                  /*!< IRPTEN23 (Bitfield-Mask: 0x03)                        */
31916 #define GPIO_PINCFG23_RDZERO23_Pos        (5UL)                     /*!< RDZERO23 (Bit 5)                                      */
31917 #define GPIO_PINCFG23_RDZERO23_Msk        (0x20UL)                  /*!< RDZERO23 (Bitfield-Mask: 0x01)                        */
31918 #define GPIO_PINCFG23_INPEN23_Pos         (4UL)                     /*!< INPEN23 (Bit 4)                                       */
31919 #define GPIO_PINCFG23_INPEN23_Msk         (0x10UL)                  /*!< INPEN23 (Bitfield-Mask: 0x01)                         */
31920 #define GPIO_PINCFG23_FNCSEL23_Pos        (0UL)                     /*!< FNCSEL23 (Bit 0)                                      */
31921 #define GPIO_PINCFG23_FNCSEL23_Msk        (0xfUL)                   /*!< FNCSEL23 (Bitfield-Mask: 0x0f)                        */
31922 /* =======================================================  PINCFG24  ======================================================== */
31923 #define GPIO_PINCFG24_FOEN24_Pos          (27UL)                    /*!< FOEN24 (Bit 27)                                       */
31924 #define GPIO_PINCFG24_FOEN24_Msk          (0x8000000UL)             /*!< FOEN24 (Bitfield-Mask: 0x01)                          */
31925 #define GPIO_PINCFG24_FIEN24_Pos          (26UL)                    /*!< FIEN24 (Bit 26)                                       */
31926 #define GPIO_PINCFG24_FIEN24_Msk          (0x4000000UL)             /*!< FIEN24 (Bitfield-Mask: 0x01)                          */
31927 #define GPIO_PINCFG24_NCEPOL24_Pos        (22UL)                    /*!< NCEPOL24 (Bit 22)                                     */
31928 #define GPIO_PINCFG24_NCEPOL24_Msk        (0x400000UL)              /*!< NCEPOL24 (Bitfield-Mask: 0x01)                        */
31929 #define GPIO_PINCFG24_NCESRC24_Pos        (16UL)                    /*!< NCESRC24 (Bit 16)                                     */
31930 #define GPIO_PINCFG24_NCESRC24_Msk        (0x3f0000UL)              /*!< NCESRC24 (Bitfield-Mask: 0x3f)                        */
31931 #define GPIO_PINCFG24_PULLCFG24_Pos       (13UL)                    /*!< PULLCFG24 (Bit 13)                                    */
31932 #define GPIO_PINCFG24_PULLCFG24_Msk       (0xe000UL)                /*!< PULLCFG24 (Bitfield-Mask: 0x07)                       */
31933 #define GPIO_PINCFG24_SR24_Pos            (12UL)                    /*!< SR24 (Bit 12)                                         */
31934 #define GPIO_PINCFG24_SR24_Msk            (0x1000UL)                /*!< SR24 (Bitfield-Mask: 0x01)                            */
31935 #define GPIO_PINCFG24_DS24_Pos            (10UL)                    /*!< DS24 (Bit 10)                                         */
31936 #define GPIO_PINCFG24_DS24_Msk            (0xc00UL)                 /*!< DS24 (Bitfield-Mask: 0x03)                            */
31937 #define GPIO_PINCFG24_OUTCFG24_Pos        (8UL)                     /*!< OUTCFG24 (Bit 8)                                      */
31938 #define GPIO_PINCFG24_OUTCFG24_Msk        (0x300UL)                 /*!< OUTCFG24 (Bitfield-Mask: 0x03)                        */
31939 #define GPIO_PINCFG24_IRPTEN24_Pos        (6UL)                     /*!< IRPTEN24 (Bit 6)                                      */
31940 #define GPIO_PINCFG24_IRPTEN24_Msk        (0xc0UL)                  /*!< IRPTEN24 (Bitfield-Mask: 0x03)                        */
31941 #define GPIO_PINCFG24_RDZERO24_Pos        (5UL)                     /*!< RDZERO24 (Bit 5)                                      */
31942 #define GPIO_PINCFG24_RDZERO24_Msk        (0x20UL)                  /*!< RDZERO24 (Bitfield-Mask: 0x01)                        */
31943 #define GPIO_PINCFG24_INPEN24_Pos         (4UL)                     /*!< INPEN24 (Bit 4)                                       */
31944 #define GPIO_PINCFG24_INPEN24_Msk         (0x10UL)                  /*!< INPEN24 (Bitfield-Mask: 0x01)                         */
31945 #define GPIO_PINCFG24_FNCSEL24_Pos        (0UL)                     /*!< FNCSEL24 (Bit 0)                                      */
31946 #define GPIO_PINCFG24_FNCSEL24_Msk        (0xfUL)                   /*!< FNCSEL24 (Bitfield-Mask: 0x0f)                        */
31947 /* =======================================================  PINCFG25  ======================================================== */
31948 #define GPIO_PINCFG25_FOEN25_Pos          (27UL)                    /*!< FOEN25 (Bit 27)                                       */
31949 #define GPIO_PINCFG25_FOEN25_Msk          (0x8000000UL)             /*!< FOEN25 (Bitfield-Mask: 0x01)                          */
31950 #define GPIO_PINCFG25_FIEN25_Pos          (26UL)                    /*!< FIEN25 (Bit 26)                                       */
31951 #define GPIO_PINCFG25_FIEN25_Msk          (0x4000000UL)             /*!< FIEN25 (Bitfield-Mask: 0x01)                          */
31952 #define GPIO_PINCFG25_NCEPOL25_Pos        (22UL)                    /*!< NCEPOL25 (Bit 22)                                     */
31953 #define GPIO_PINCFG25_NCEPOL25_Msk        (0x400000UL)              /*!< NCEPOL25 (Bitfield-Mask: 0x01)                        */
31954 #define GPIO_PINCFG25_NCESRC25_Pos        (16UL)                    /*!< NCESRC25 (Bit 16)                                     */
31955 #define GPIO_PINCFG25_NCESRC25_Msk        (0x3f0000UL)              /*!< NCESRC25 (Bitfield-Mask: 0x3f)                        */
31956 #define GPIO_PINCFG25_PULLCFG25_Pos       (13UL)                    /*!< PULLCFG25 (Bit 13)                                    */
31957 #define GPIO_PINCFG25_PULLCFG25_Msk       (0xe000UL)                /*!< PULLCFG25 (Bitfield-Mask: 0x07)                       */
31958 #define GPIO_PINCFG25_SR25_Pos            (12UL)                    /*!< SR25 (Bit 12)                                         */
31959 #define GPIO_PINCFG25_SR25_Msk            (0x1000UL)                /*!< SR25 (Bitfield-Mask: 0x01)                            */
31960 #define GPIO_PINCFG25_DS25_Pos            (10UL)                    /*!< DS25 (Bit 10)                                         */
31961 #define GPIO_PINCFG25_DS25_Msk            (0xc00UL)                 /*!< DS25 (Bitfield-Mask: 0x03)                            */
31962 #define GPIO_PINCFG25_OUTCFG25_Pos        (8UL)                     /*!< OUTCFG25 (Bit 8)                                      */
31963 #define GPIO_PINCFG25_OUTCFG25_Msk        (0x300UL)                 /*!< OUTCFG25 (Bitfield-Mask: 0x03)                        */
31964 #define GPIO_PINCFG25_IRPTEN25_Pos        (6UL)                     /*!< IRPTEN25 (Bit 6)                                      */
31965 #define GPIO_PINCFG25_IRPTEN25_Msk        (0xc0UL)                  /*!< IRPTEN25 (Bitfield-Mask: 0x03)                        */
31966 #define GPIO_PINCFG25_RDZERO25_Pos        (5UL)                     /*!< RDZERO25 (Bit 5)                                      */
31967 #define GPIO_PINCFG25_RDZERO25_Msk        (0x20UL)                  /*!< RDZERO25 (Bitfield-Mask: 0x01)                        */
31968 #define GPIO_PINCFG25_INPEN25_Pos         (4UL)                     /*!< INPEN25 (Bit 4)                                       */
31969 #define GPIO_PINCFG25_INPEN25_Msk         (0x10UL)                  /*!< INPEN25 (Bitfield-Mask: 0x01)                         */
31970 #define GPIO_PINCFG25_FNCSEL25_Pos        (0UL)                     /*!< FNCSEL25 (Bit 0)                                      */
31971 #define GPIO_PINCFG25_FNCSEL25_Msk        (0xfUL)                   /*!< FNCSEL25 (Bitfield-Mask: 0x0f)                        */
31972 /* =======================================================  PINCFG26  ======================================================== */
31973 #define GPIO_PINCFG26_FOEN26_Pos          (27UL)                    /*!< FOEN26 (Bit 27)                                       */
31974 #define GPIO_PINCFG26_FOEN26_Msk          (0x8000000UL)             /*!< FOEN26 (Bitfield-Mask: 0x01)                          */
31975 #define GPIO_PINCFG26_FIEN26_Pos          (26UL)                    /*!< FIEN26 (Bit 26)                                       */
31976 #define GPIO_PINCFG26_FIEN26_Msk          (0x4000000UL)             /*!< FIEN26 (Bitfield-Mask: 0x01)                          */
31977 #define GPIO_PINCFG26_NCEPOL26_Pos        (22UL)                    /*!< NCEPOL26 (Bit 22)                                     */
31978 #define GPIO_PINCFG26_NCEPOL26_Msk        (0x400000UL)              /*!< NCEPOL26 (Bitfield-Mask: 0x01)                        */
31979 #define GPIO_PINCFG26_NCESRC26_Pos        (16UL)                    /*!< NCESRC26 (Bit 16)                                     */
31980 #define GPIO_PINCFG26_NCESRC26_Msk        (0x3f0000UL)              /*!< NCESRC26 (Bitfield-Mask: 0x3f)                        */
31981 #define GPIO_PINCFG26_PULLCFG26_Pos       (13UL)                    /*!< PULLCFG26 (Bit 13)                                    */
31982 #define GPIO_PINCFG26_PULLCFG26_Msk       (0xe000UL)                /*!< PULLCFG26 (Bitfield-Mask: 0x07)                       */
31983 #define GPIO_PINCFG26_SR26_Pos            (12UL)                    /*!< SR26 (Bit 12)                                         */
31984 #define GPIO_PINCFG26_SR26_Msk            (0x1000UL)                /*!< SR26 (Bitfield-Mask: 0x01)                            */
31985 #define GPIO_PINCFG26_DS26_Pos            (10UL)                    /*!< DS26 (Bit 10)                                         */
31986 #define GPIO_PINCFG26_DS26_Msk            (0xc00UL)                 /*!< DS26 (Bitfield-Mask: 0x03)                            */
31987 #define GPIO_PINCFG26_OUTCFG26_Pos        (8UL)                     /*!< OUTCFG26 (Bit 8)                                      */
31988 #define GPIO_PINCFG26_OUTCFG26_Msk        (0x300UL)                 /*!< OUTCFG26 (Bitfield-Mask: 0x03)                        */
31989 #define GPIO_PINCFG26_IRPTEN26_Pos        (6UL)                     /*!< IRPTEN26 (Bit 6)                                      */
31990 #define GPIO_PINCFG26_IRPTEN26_Msk        (0xc0UL)                  /*!< IRPTEN26 (Bitfield-Mask: 0x03)                        */
31991 #define GPIO_PINCFG26_RDZERO26_Pos        (5UL)                     /*!< RDZERO26 (Bit 5)                                      */
31992 #define GPIO_PINCFG26_RDZERO26_Msk        (0x20UL)                  /*!< RDZERO26 (Bitfield-Mask: 0x01)                        */
31993 #define GPIO_PINCFG26_INPEN26_Pos         (4UL)                     /*!< INPEN26 (Bit 4)                                       */
31994 #define GPIO_PINCFG26_INPEN26_Msk         (0x10UL)                  /*!< INPEN26 (Bitfield-Mask: 0x01)                         */
31995 #define GPIO_PINCFG26_FNCSEL26_Pos        (0UL)                     /*!< FNCSEL26 (Bit 0)                                      */
31996 #define GPIO_PINCFG26_FNCSEL26_Msk        (0xfUL)                   /*!< FNCSEL26 (Bitfield-Mask: 0x0f)                        */
31997 /* =======================================================  PINCFG27  ======================================================== */
31998 #define GPIO_PINCFG27_FOEN27_Pos          (27UL)                    /*!< FOEN27 (Bit 27)                                       */
31999 #define GPIO_PINCFG27_FOEN27_Msk          (0x8000000UL)             /*!< FOEN27 (Bitfield-Mask: 0x01)                          */
32000 #define GPIO_PINCFG27_FIEN27_Pos          (26UL)                    /*!< FIEN27 (Bit 26)                                       */
32001 #define GPIO_PINCFG27_FIEN27_Msk          (0x4000000UL)             /*!< FIEN27 (Bitfield-Mask: 0x01)                          */
32002 #define GPIO_PINCFG27_NCEPOL27_Pos        (22UL)                    /*!< NCEPOL27 (Bit 22)                                     */
32003 #define GPIO_PINCFG27_NCEPOL27_Msk        (0x400000UL)              /*!< NCEPOL27 (Bitfield-Mask: 0x01)                        */
32004 #define GPIO_PINCFG27_NCESRC27_Pos        (16UL)                    /*!< NCESRC27 (Bit 16)                                     */
32005 #define GPIO_PINCFG27_NCESRC27_Msk        (0x3f0000UL)              /*!< NCESRC27 (Bitfield-Mask: 0x3f)                        */
32006 #define GPIO_PINCFG27_PULLCFG27_Pos       (13UL)                    /*!< PULLCFG27 (Bit 13)                                    */
32007 #define GPIO_PINCFG27_PULLCFG27_Msk       (0xe000UL)                /*!< PULLCFG27 (Bitfield-Mask: 0x07)                       */
32008 #define GPIO_PINCFG27_SR27_Pos            (12UL)                    /*!< SR27 (Bit 12)                                         */
32009 #define GPIO_PINCFG27_SR27_Msk            (0x1000UL)                /*!< SR27 (Bitfield-Mask: 0x01)                            */
32010 #define GPIO_PINCFG27_DS27_Pos            (10UL)                    /*!< DS27 (Bit 10)                                         */
32011 #define GPIO_PINCFG27_DS27_Msk            (0xc00UL)                 /*!< DS27 (Bitfield-Mask: 0x03)                            */
32012 #define GPIO_PINCFG27_OUTCFG27_Pos        (8UL)                     /*!< OUTCFG27 (Bit 8)                                      */
32013 #define GPIO_PINCFG27_OUTCFG27_Msk        (0x300UL)                 /*!< OUTCFG27 (Bitfield-Mask: 0x03)                        */
32014 #define GPIO_PINCFG27_IRPTEN27_Pos        (6UL)                     /*!< IRPTEN27 (Bit 6)                                      */
32015 #define GPIO_PINCFG27_IRPTEN27_Msk        (0xc0UL)                  /*!< IRPTEN27 (Bitfield-Mask: 0x03)                        */
32016 #define GPIO_PINCFG27_RDZERO27_Pos        (5UL)                     /*!< RDZERO27 (Bit 5)                                      */
32017 #define GPIO_PINCFG27_RDZERO27_Msk        (0x20UL)                  /*!< RDZERO27 (Bitfield-Mask: 0x01)                        */
32018 #define GPIO_PINCFG27_INPEN27_Pos         (4UL)                     /*!< INPEN27 (Bit 4)                                       */
32019 #define GPIO_PINCFG27_INPEN27_Msk         (0x10UL)                  /*!< INPEN27 (Bitfield-Mask: 0x01)                         */
32020 #define GPIO_PINCFG27_FNCSEL27_Pos        (0UL)                     /*!< FNCSEL27 (Bit 0)                                      */
32021 #define GPIO_PINCFG27_FNCSEL27_Msk        (0xfUL)                   /*!< FNCSEL27 (Bitfield-Mask: 0x0f)                        */
32022 /* =======================================================  PINCFG28  ======================================================== */
32023 #define GPIO_PINCFG28_FOEN28_Pos          (27UL)                    /*!< FOEN28 (Bit 27)                                       */
32024 #define GPIO_PINCFG28_FOEN28_Msk          (0x8000000UL)             /*!< FOEN28 (Bitfield-Mask: 0x01)                          */
32025 #define GPIO_PINCFG28_FIEN28_Pos          (26UL)                    /*!< FIEN28 (Bit 26)                                       */
32026 #define GPIO_PINCFG28_FIEN28_Msk          (0x4000000UL)             /*!< FIEN28 (Bitfield-Mask: 0x01)                          */
32027 #define GPIO_PINCFG28_NCEPOL28_Pos        (22UL)                    /*!< NCEPOL28 (Bit 22)                                     */
32028 #define GPIO_PINCFG28_NCEPOL28_Msk        (0x400000UL)              /*!< NCEPOL28 (Bitfield-Mask: 0x01)                        */
32029 #define GPIO_PINCFG28_NCESRC28_Pos        (16UL)                    /*!< NCESRC28 (Bit 16)                                     */
32030 #define GPIO_PINCFG28_NCESRC28_Msk        (0x3f0000UL)              /*!< NCESRC28 (Bitfield-Mask: 0x3f)                        */
32031 #define GPIO_PINCFG28_PULLCFG28_Pos       (13UL)                    /*!< PULLCFG28 (Bit 13)                                    */
32032 #define GPIO_PINCFG28_PULLCFG28_Msk       (0xe000UL)                /*!< PULLCFG28 (Bitfield-Mask: 0x07)                       */
32033 #define GPIO_PINCFG28_SR28_Pos            (12UL)                    /*!< SR28 (Bit 12)                                         */
32034 #define GPIO_PINCFG28_SR28_Msk            (0x1000UL)                /*!< SR28 (Bitfield-Mask: 0x01)                            */
32035 #define GPIO_PINCFG28_DS28_Pos            (10UL)                    /*!< DS28 (Bit 10)                                         */
32036 #define GPIO_PINCFG28_DS28_Msk            (0xc00UL)                 /*!< DS28 (Bitfield-Mask: 0x03)                            */
32037 #define GPIO_PINCFG28_OUTCFG28_Pos        (8UL)                     /*!< OUTCFG28 (Bit 8)                                      */
32038 #define GPIO_PINCFG28_OUTCFG28_Msk        (0x300UL)                 /*!< OUTCFG28 (Bitfield-Mask: 0x03)                        */
32039 #define GPIO_PINCFG28_IRPTEN28_Pos        (6UL)                     /*!< IRPTEN28 (Bit 6)                                      */
32040 #define GPIO_PINCFG28_IRPTEN28_Msk        (0xc0UL)                  /*!< IRPTEN28 (Bitfield-Mask: 0x03)                        */
32041 #define GPIO_PINCFG28_RDZERO28_Pos        (5UL)                     /*!< RDZERO28 (Bit 5)                                      */
32042 #define GPIO_PINCFG28_RDZERO28_Msk        (0x20UL)                  /*!< RDZERO28 (Bitfield-Mask: 0x01)                        */
32043 #define GPIO_PINCFG28_INPEN28_Pos         (4UL)                     /*!< INPEN28 (Bit 4)                                       */
32044 #define GPIO_PINCFG28_INPEN28_Msk         (0x10UL)                  /*!< INPEN28 (Bitfield-Mask: 0x01)                         */
32045 #define GPIO_PINCFG28_FNCSEL28_Pos        (0UL)                     /*!< FNCSEL28 (Bit 0)                                      */
32046 #define GPIO_PINCFG28_FNCSEL28_Msk        (0xfUL)                   /*!< FNCSEL28 (Bitfield-Mask: 0x0f)                        */
32047 /* =======================================================  PINCFG29  ======================================================== */
32048 #define GPIO_PINCFG29_FOEN29_Pos          (27UL)                    /*!< FOEN29 (Bit 27)                                       */
32049 #define GPIO_PINCFG29_FOEN29_Msk          (0x8000000UL)             /*!< FOEN29 (Bitfield-Mask: 0x01)                          */
32050 #define GPIO_PINCFG29_FIEN29_Pos          (26UL)                    /*!< FIEN29 (Bit 26)                                       */
32051 #define GPIO_PINCFG29_FIEN29_Msk          (0x4000000UL)             /*!< FIEN29 (Bitfield-Mask: 0x01)                          */
32052 #define GPIO_PINCFG29_NCEPOL29_Pos        (22UL)                    /*!< NCEPOL29 (Bit 22)                                     */
32053 #define GPIO_PINCFG29_NCEPOL29_Msk        (0x400000UL)              /*!< NCEPOL29 (Bitfield-Mask: 0x01)                        */
32054 #define GPIO_PINCFG29_NCESRC29_Pos        (16UL)                    /*!< NCESRC29 (Bit 16)                                     */
32055 #define GPIO_PINCFG29_NCESRC29_Msk        (0x3f0000UL)              /*!< NCESRC29 (Bitfield-Mask: 0x3f)                        */
32056 #define GPIO_PINCFG29_PULLCFG29_Pos       (13UL)                    /*!< PULLCFG29 (Bit 13)                                    */
32057 #define GPIO_PINCFG29_PULLCFG29_Msk       (0xe000UL)                /*!< PULLCFG29 (Bitfield-Mask: 0x07)                       */
32058 #define GPIO_PINCFG29_SR29_Pos            (12UL)                    /*!< SR29 (Bit 12)                                         */
32059 #define GPIO_PINCFG29_SR29_Msk            (0x1000UL)                /*!< SR29 (Bitfield-Mask: 0x01)                            */
32060 #define GPIO_PINCFG29_DS29_Pos            (10UL)                    /*!< DS29 (Bit 10)                                         */
32061 #define GPIO_PINCFG29_DS29_Msk            (0xc00UL)                 /*!< DS29 (Bitfield-Mask: 0x03)                            */
32062 #define GPIO_PINCFG29_OUTCFG29_Pos        (8UL)                     /*!< OUTCFG29 (Bit 8)                                      */
32063 #define GPIO_PINCFG29_OUTCFG29_Msk        (0x300UL)                 /*!< OUTCFG29 (Bitfield-Mask: 0x03)                        */
32064 #define GPIO_PINCFG29_IRPTEN29_Pos        (6UL)                     /*!< IRPTEN29 (Bit 6)                                      */
32065 #define GPIO_PINCFG29_IRPTEN29_Msk        (0xc0UL)                  /*!< IRPTEN29 (Bitfield-Mask: 0x03)                        */
32066 #define GPIO_PINCFG29_RDZERO29_Pos        (5UL)                     /*!< RDZERO29 (Bit 5)                                      */
32067 #define GPIO_PINCFG29_RDZERO29_Msk        (0x20UL)                  /*!< RDZERO29 (Bitfield-Mask: 0x01)                        */
32068 #define GPIO_PINCFG29_INPEN29_Pos         (4UL)                     /*!< INPEN29 (Bit 4)                                       */
32069 #define GPIO_PINCFG29_INPEN29_Msk         (0x10UL)                  /*!< INPEN29 (Bitfield-Mask: 0x01)                         */
32070 #define GPIO_PINCFG29_FNCSEL29_Pos        (0UL)                     /*!< FNCSEL29 (Bit 0)                                      */
32071 #define GPIO_PINCFG29_FNCSEL29_Msk        (0xfUL)                   /*!< FNCSEL29 (Bitfield-Mask: 0x0f)                        */
32072 /* =======================================================  PINCFG30  ======================================================== */
32073 #define GPIO_PINCFG30_FOEN30_Pos          (27UL)                    /*!< FOEN30 (Bit 27)                                       */
32074 #define GPIO_PINCFG30_FOEN30_Msk          (0x8000000UL)             /*!< FOEN30 (Bitfield-Mask: 0x01)                          */
32075 #define GPIO_PINCFG30_FIEN30_Pos          (26UL)                    /*!< FIEN30 (Bit 26)                                       */
32076 #define GPIO_PINCFG30_FIEN30_Msk          (0x4000000UL)             /*!< FIEN30 (Bitfield-Mask: 0x01)                          */
32077 #define GPIO_PINCFG30_NCEPOL30_Pos        (22UL)                    /*!< NCEPOL30 (Bit 22)                                     */
32078 #define GPIO_PINCFG30_NCEPOL30_Msk        (0x400000UL)              /*!< NCEPOL30 (Bitfield-Mask: 0x01)                        */
32079 #define GPIO_PINCFG30_NCESRC30_Pos        (16UL)                    /*!< NCESRC30 (Bit 16)                                     */
32080 #define GPIO_PINCFG30_NCESRC30_Msk        (0x3f0000UL)              /*!< NCESRC30 (Bitfield-Mask: 0x3f)                        */
32081 #define GPIO_PINCFG30_PULLCFG30_Pos       (13UL)                    /*!< PULLCFG30 (Bit 13)                                    */
32082 #define GPIO_PINCFG30_PULLCFG30_Msk       (0xe000UL)                /*!< PULLCFG30 (Bitfield-Mask: 0x07)                       */
32083 #define GPIO_PINCFG30_SR30_Pos            (12UL)                    /*!< SR30 (Bit 12)                                         */
32084 #define GPIO_PINCFG30_SR30_Msk            (0x1000UL)                /*!< SR30 (Bitfield-Mask: 0x01)                            */
32085 #define GPIO_PINCFG30_DS30_Pos            (10UL)                    /*!< DS30 (Bit 10)                                         */
32086 #define GPIO_PINCFG30_DS30_Msk            (0xc00UL)                 /*!< DS30 (Bitfield-Mask: 0x03)                            */
32087 #define GPIO_PINCFG30_OUTCFG30_Pos        (8UL)                     /*!< OUTCFG30 (Bit 8)                                      */
32088 #define GPIO_PINCFG30_OUTCFG30_Msk        (0x300UL)                 /*!< OUTCFG30 (Bitfield-Mask: 0x03)                        */
32089 #define GPIO_PINCFG30_IRPTEN30_Pos        (6UL)                     /*!< IRPTEN30 (Bit 6)                                      */
32090 #define GPIO_PINCFG30_IRPTEN30_Msk        (0xc0UL)                  /*!< IRPTEN30 (Bitfield-Mask: 0x03)                        */
32091 #define GPIO_PINCFG30_RDZERO30_Pos        (5UL)                     /*!< RDZERO30 (Bit 5)                                      */
32092 #define GPIO_PINCFG30_RDZERO30_Msk        (0x20UL)                  /*!< RDZERO30 (Bitfield-Mask: 0x01)                        */
32093 #define GPIO_PINCFG30_INPEN30_Pos         (4UL)                     /*!< INPEN30 (Bit 4)                                       */
32094 #define GPIO_PINCFG30_INPEN30_Msk         (0x10UL)                  /*!< INPEN30 (Bitfield-Mask: 0x01)                         */
32095 #define GPIO_PINCFG30_FNCSEL30_Pos        (0UL)                     /*!< FNCSEL30 (Bit 0)                                      */
32096 #define GPIO_PINCFG30_FNCSEL30_Msk        (0xfUL)                   /*!< FNCSEL30 (Bitfield-Mask: 0x0f)                        */
32097 /* =======================================================  PINCFG31  ======================================================== */
32098 #define GPIO_PINCFG31_FOEN31_Pos          (27UL)                    /*!< FOEN31 (Bit 27)                                       */
32099 #define GPIO_PINCFG31_FOEN31_Msk          (0x8000000UL)             /*!< FOEN31 (Bitfield-Mask: 0x01)                          */
32100 #define GPIO_PINCFG31_FIEN31_Pos          (26UL)                    /*!< FIEN31 (Bit 26)                                       */
32101 #define GPIO_PINCFG31_FIEN31_Msk          (0x4000000UL)             /*!< FIEN31 (Bitfield-Mask: 0x01)                          */
32102 #define GPIO_PINCFG31_NCEPOL31_Pos        (22UL)                    /*!< NCEPOL31 (Bit 22)                                     */
32103 #define GPIO_PINCFG31_NCEPOL31_Msk        (0x400000UL)              /*!< NCEPOL31 (Bitfield-Mask: 0x01)                        */
32104 #define GPIO_PINCFG31_NCESRC31_Pos        (16UL)                    /*!< NCESRC31 (Bit 16)                                     */
32105 #define GPIO_PINCFG31_NCESRC31_Msk        (0x3f0000UL)              /*!< NCESRC31 (Bitfield-Mask: 0x3f)                        */
32106 #define GPIO_PINCFG31_PULLCFG31_Pos       (13UL)                    /*!< PULLCFG31 (Bit 13)                                    */
32107 #define GPIO_PINCFG31_PULLCFG31_Msk       (0xe000UL)                /*!< PULLCFG31 (Bitfield-Mask: 0x07)                       */
32108 #define GPIO_PINCFG31_SR31_Pos            (12UL)                    /*!< SR31 (Bit 12)                                         */
32109 #define GPIO_PINCFG31_SR31_Msk            (0x1000UL)                /*!< SR31 (Bitfield-Mask: 0x01)                            */
32110 #define GPIO_PINCFG31_DS31_Pos            (10UL)                    /*!< DS31 (Bit 10)                                         */
32111 #define GPIO_PINCFG31_DS31_Msk            (0xc00UL)                 /*!< DS31 (Bitfield-Mask: 0x03)                            */
32112 #define GPIO_PINCFG31_OUTCFG31_Pos        (8UL)                     /*!< OUTCFG31 (Bit 8)                                      */
32113 #define GPIO_PINCFG31_OUTCFG31_Msk        (0x300UL)                 /*!< OUTCFG31 (Bitfield-Mask: 0x03)                        */
32114 #define GPIO_PINCFG31_IRPTEN31_Pos        (6UL)                     /*!< IRPTEN31 (Bit 6)                                      */
32115 #define GPIO_PINCFG31_IRPTEN31_Msk        (0xc0UL)                  /*!< IRPTEN31 (Bitfield-Mask: 0x03)                        */
32116 #define GPIO_PINCFG31_RDZERO31_Pos        (5UL)                     /*!< RDZERO31 (Bit 5)                                      */
32117 #define GPIO_PINCFG31_RDZERO31_Msk        (0x20UL)                  /*!< RDZERO31 (Bitfield-Mask: 0x01)                        */
32118 #define GPIO_PINCFG31_INPEN31_Pos         (4UL)                     /*!< INPEN31 (Bit 4)                                       */
32119 #define GPIO_PINCFG31_INPEN31_Msk         (0x10UL)                  /*!< INPEN31 (Bitfield-Mask: 0x01)                         */
32120 #define GPIO_PINCFG31_FNCSEL31_Pos        (0UL)                     /*!< FNCSEL31 (Bit 0)                                      */
32121 #define GPIO_PINCFG31_FNCSEL31_Msk        (0xfUL)                   /*!< FNCSEL31 (Bitfield-Mask: 0x0f)                        */
32122 /* =======================================================  PINCFG32  ======================================================== */
32123 #define GPIO_PINCFG32_FOEN32_Pos          (27UL)                    /*!< FOEN32 (Bit 27)                                       */
32124 #define GPIO_PINCFG32_FOEN32_Msk          (0x8000000UL)             /*!< FOEN32 (Bitfield-Mask: 0x01)                          */
32125 #define GPIO_PINCFG32_FIEN32_Pos          (26UL)                    /*!< FIEN32 (Bit 26)                                       */
32126 #define GPIO_PINCFG32_FIEN32_Msk          (0x4000000UL)             /*!< FIEN32 (Bitfield-Mask: 0x01)                          */
32127 #define GPIO_PINCFG32_NCEPOL32_Pos        (22UL)                    /*!< NCEPOL32 (Bit 22)                                     */
32128 #define GPIO_PINCFG32_NCEPOL32_Msk        (0x400000UL)              /*!< NCEPOL32 (Bitfield-Mask: 0x01)                        */
32129 #define GPIO_PINCFG32_NCESRC32_Pos        (16UL)                    /*!< NCESRC32 (Bit 16)                                     */
32130 #define GPIO_PINCFG32_NCESRC32_Msk        (0x3f0000UL)              /*!< NCESRC32 (Bitfield-Mask: 0x3f)                        */
32131 #define GPIO_PINCFG32_PULLCFG32_Pos       (13UL)                    /*!< PULLCFG32 (Bit 13)                                    */
32132 #define GPIO_PINCFG32_PULLCFG32_Msk       (0xe000UL)                /*!< PULLCFG32 (Bitfield-Mask: 0x07)                       */
32133 #define GPIO_PINCFG32_SR32_Pos            (12UL)                    /*!< SR32 (Bit 12)                                         */
32134 #define GPIO_PINCFG32_SR32_Msk            (0x1000UL)                /*!< SR32 (Bitfield-Mask: 0x01)                            */
32135 #define GPIO_PINCFG32_DS32_Pos            (10UL)                    /*!< DS32 (Bit 10)                                         */
32136 #define GPIO_PINCFG32_DS32_Msk            (0xc00UL)                 /*!< DS32 (Bitfield-Mask: 0x03)                            */
32137 #define GPIO_PINCFG32_OUTCFG32_Pos        (8UL)                     /*!< OUTCFG32 (Bit 8)                                      */
32138 #define GPIO_PINCFG32_OUTCFG32_Msk        (0x300UL)                 /*!< OUTCFG32 (Bitfield-Mask: 0x03)                        */
32139 #define GPIO_PINCFG32_IRPTEN32_Pos        (6UL)                     /*!< IRPTEN32 (Bit 6)                                      */
32140 #define GPIO_PINCFG32_IRPTEN32_Msk        (0xc0UL)                  /*!< IRPTEN32 (Bitfield-Mask: 0x03)                        */
32141 #define GPIO_PINCFG32_RDZERO32_Pos        (5UL)                     /*!< RDZERO32 (Bit 5)                                      */
32142 #define GPIO_PINCFG32_RDZERO32_Msk        (0x20UL)                  /*!< RDZERO32 (Bitfield-Mask: 0x01)                        */
32143 #define GPIO_PINCFG32_INPEN32_Pos         (4UL)                     /*!< INPEN32 (Bit 4)                                       */
32144 #define GPIO_PINCFG32_INPEN32_Msk         (0x10UL)                  /*!< INPEN32 (Bitfield-Mask: 0x01)                         */
32145 #define GPIO_PINCFG32_FNCSEL32_Pos        (0UL)                     /*!< FNCSEL32 (Bit 0)                                      */
32146 #define GPIO_PINCFG32_FNCSEL32_Msk        (0xfUL)                   /*!< FNCSEL32 (Bitfield-Mask: 0x0f)                        */
32147 /* =======================================================  PINCFG33  ======================================================== */
32148 #define GPIO_PINCFG33_FOEN33_Pos          (27UL)                    /*!< FOEN33 (Bit 27)                                       */
32149 #define GPIO_PINCFG33_FOEN33_Msk          (0x8000000UL)             /*!< FOEN33 (Bitfield-Mask: 0x01)                          */
32150 #define GPIO_PINCFG33_FIEN33_Pos          (26UL)                    /*!< FIEN33 (Bit 26)                                       */
32151 #define GPIO_PINCFG33_FIEN33_Msk          (0x4000000UL)             /*!< FIEN33 (Bitfield-Mask: 0x01)                          */
32152 #define GPIO_PINCFG33_NCEPOL33_Pos        (22UL)                    /*!< NCEPOL33 (Bit 22)                                     */
32153 #define GPIO_PINCFG33_NCEPOL33_Msk        (0x400000UL)              /*!< NCEPOL33 (Bitfield-Mask: 0x01)                        */
32154 #define GPIO_PINCFG33_NCESRC33_Pos        (16UL)                    /*!< NCESRC33 (Bit 16)                                     */
32155 #define GPIO_PINCFG33_NCESRC33_Msk        (0x3f0000UL)              /*!< NCESRC33 (Bitfield-Mask: 0x3f)                        */
32156 #define GPIO_PINCFG33_PULLCFG33_Pos       (13UL)                    /*!< PULLCFG33 (Bit 13)                                    */
32157 #define GPIO_PINCFG33_PULLCFG33_Msk       (0xe000UL)                /*!< PULLCFG33 (Bitfield-Mask: 0x07)                       */
32158 #define GPIO_PINCFG33_SR33_Pos            (12UL)                    /*!< SR33 (Bit 12)                                         */
32159 #define GPIO_PINCFG33_SR33_Msk            (0x1000UL)                /*!< SR33 (Bitfield-Mask: 0x01)                            */
32160 #define GPIO_PINCFG33_DS33_Pos            (10UL)                    /*!< DS33 (Bit 10)                                         */
32161 #define GPIO_PINCFG33_DS33_Msk            (0xc00UL)                 /*!< DS33 (Bitfield-Mask: 0x03)                            */
32162 #define GPIO_PINCFG33_OUTCFG33_Pos        (8UL)                     /*!< OUTCFG33 (Bit 8)                                      */
32163 #define GPIO_PINCFG33_OUTCFG33_Msk        (0x300UL)                 /*!< OUTCFG33 (Bitfield-Mask: 0x03)                        */
32164 #define GPIO_PINCFG33_IRPTEN33_Pos        (6UL)                     /*!< IRPTEN33 (Bit 6)                                      */
32165 #define GPIO_PINCFG33_IRPTEN33_Msk        (0xc0UL)                  /*!< IRPTEN33 (Bitfield-Mask: 0x03)                        */
32166 #define GPIO_PINCFG33_RDZERO33_Pos        (5UL)                     /*!< RDZERO33 (Bit 5)                                      */
32167 #define GPIO_PINCFG33_RDZERO33_Msk        (0x20UL)                  /*!< RDZERO33 (Bitfield-Mask: 0x01)                        */
32168 #define GPIO_PINCFG33_INPEN33_Pos         (4UL)                     /*!< INPEN33 (Bit 4)                                       */
32169 #define GPIO_PINCFG33_INPEN33_Msk         (0x10UL)                  /*!< INPEN33 (Bitfield-Mask: 0x01)                         */
32170 #define GPIO_PINCFG33_FNCSEL33_Pos        (0UL)                     /*!< FNCSEL33 (Bit 0)                                      */
32171 #define GPIO_PINCFG33_FNCSEL33_Msk        (0xfUL)                   /*!< FNCSEL33 (Bitfield-Mask: 0x0f)                        */
32172 /* =======================================================  PINCFG34  ======================================================== */
32173 #define GPIO_PINCFG34_FOEN34_Pos          (27UL)                    /*!< FOEN34 (Bit 27)                                       */
32174 #define GPIO_PINCFG34_FOEN34_Msk          (0x8000000UL)             /*!< FOEN34 (Bitfield-Mask: 0x01)                          */
32175 #define GPIO_PINCFG34_FIEN34_Pos          (26UL)                    /*!< FIEN34 (Bit 26)                                       */
32176 #define GPIO_PINCFG34_FIEN34_Msk          (0x4000000UL)             /*!< FIEN34 (Bitfield-Mask: 0x01)                          */
32177 #define GPIO_PINCFG34_NCEPOL34_Pos        (22UL)                    /*!< NCEPOL34 (Bit 22)                                     */
32178 #define GPIO_PINCFG34_NCEPOL34_Msk        (0x400000UL)              /*!< NCEPOL34 (Bitfield-Mask: 0x01)                        */
32179 #define GPIO_PINCFG34_NCESRC34_Pos        (16UL)                    /*!< NCESRC34 (Bit 16)                                     */
32180 #define GPIO_PINCFG34_NCESRC34_Msk        (0x3f0000UL)              /*!< NCESRC34 (Bitfield-Mask: 0x3f)                        */
32181 #define GPIO_PINCFG34_PULLCFG34_Pos       (13UL)                    /*!< PULLCFG34 (Bit 13)                                    */
32182 #define GPIO_PINCFG34_PULLCFG34_Msk       (0xe000UL)                /*!< PULLCFG34 (Bitfield-Mask: 0x07)                       */
32183 #define GPIO_PINCFG34_SR34_Pos            (12UL)                    /*!< SR34 (Bit 12)                                         */
32184 #define GPIO_PINCFG34_SR34_Msk            (0x1000UL)                /*!< SR34 (Bitfield-Mask: 0x01)                            */
32185 #define GPIO_PINCFG34_DS34_Pos            (10UL)                    /*!< DS34 (Bit 10)                                         */
32186 #define GPIO_PINCFG34_DS34_Msk            (0xc00UL)                 /*!< DS34 (Bitfield-Mask: 0x03)                            */
32187 #define GPIO_PINCFG34_OUTCFG34_Pos        (8UL)                     /*!< OUTCFG34 (Bit 8)                                      */
32188 #define GPIO_PINCFG34_OUTCFG34_Msk        (0x300UL)                 /*!< OUTCFG34 (Bitfield-Mask: 0x03)                        */
32189 #define GPIO_PINCFG34_IRPTEN34_Pos        (6UL)                     /*!< IRPTEN34 (Bit 6)                                      */
32190 #define GPIO_PINCFG34_IRPTEN34_Msk        (0xc0UL)                  /*!< IRPTEN34 (Bitfield-Mask: 0x03)                        */
32191 #define GPIO_PINCFG34_RDZERO34_Pos        (5UL)                     /*!< RDZERO34 (Bit 5)                                      */
32192 #define GPIO_PINCFG34_RDZERO34_Msk        (0x20UL)                  /*!< RDZERO34 (Bitfield-Mask: 0x01)                        */
32193 #define GPIO_PINCFG34_INPEN34_Pos         (4UL)                     /*!< INPEN34 (Bit 4)                                       */
32194 #define GPIO_PINCFG34_INPEN34_Msk         (0x10UL)                  /*!< INPEN34 (Bitfield-Mask: 0x01)                         */
32195 #define GPIO_PINCFG34_FNCSEL34_Pos        (0UL)                     /*!< FNCSEL34 (Bit 0)                                      */
32196 #define GPIO_PINCFG34_FNCSEL34_Msk        (0xfUL)                   /*!< FNCSEL34 (Bitfield-Mask: 0x0f)                        */
32197 /* =======================================================  PINCFG35  ======================================================== */
32198 #define GPIO_PINCFG35_FOEN35_Pos          (27UL)                    /*!< FOEN35 (Bit 27)                                       */
32199 #define GPIO_PINCFG35_FOEN35_Msk          (0x8000000UL)             /*!< FOEN35 (Bitfield-Mask: 0x01)                          */
32200 #define GPIO_PINCFG35_FIEN35_Pos          (26UL)                    /*!< FIEN35 (Bit 26)                                       */
32201 #define GPIO_PINCFG35_FIEN35_Msk          (0x4000000UL)             /*!< FIEN35 (Bitfield-Mask: 0x01)                          */
32202 #define GPIO_PINCFG35_NCEPOL35_Pos        (22UL)                    /*!< NCEPOL35 (Bit 22)                                     */
32203 #define GPIO_PINCFG35_NCEPOL35_Msk        (0x400000UL)              /*!< NCEPOL35 (Bitfield-Mask: 0x01)                        */
32204 #define GPIO_PINCFG35_NCESRC35_Pos        (16UL)                    /*!< NCESRC35 (Bit 16)                                     */
32205 #define GPIO_PINCFG35_NCESRC35_Msk        (0x3f0000UL)              /*!< NCESRC35 (Bitfield-Mask: 0x3f)                        */
32206 #define GPIO_PINCFG35_PULLCFG35_Pos       (13UL)                    /*!< PULLCFG35 (Bit 13)                                    */
32207 #define GPIO_PINCFG35_PULLCFG35_Msk       (0xe000UL)                /*!< PULLCFG35 (Bitfield-Mask: 0x07)                       */
32208 #define GPIO_PINCFG35_SR35_Pos            (12UL)                    /*!< SR35 (Bit 12)                                         */
32209 #define GPIO_PINCFG35_SR35_Msk            (0x1000UL)                /*!< SR35 (Bitfield-Mask: 0x01)                            */
32210 #define GPIO_PINCFG35_DS35_Pos            (10UL)                    /*!< DS35 (Bit 10)                                         */
32211 #define GPIO_PINCFG35_DS35_Msk            (0xc00UL)                 /*!< DS35 (Bitfield-Mask: 0x03)                            */
32212 #define GPIO_PINCFG35_OUTCFG35_Pos        (8UL)                     /*!< OUTCFG35 (Bit 8)                                      */
32213 #define GPIO_PINCFG35_OUTCFG35_Msk        (0x300UL)                 /*!< OUTCFG35 (Bitfield-Mask: 0x03)                        */
32214 #define GPIO_PINCFG35_IRPTEN35_Pos        (6UL)                     /*!< IRPTEN35 (Bit 6)                                      */
32215 #define GPIO_PINCFG35_IRPTEN35_Msk        (0xc0UL)                  /*!< IRPTEN35 (Bitfield-Mask: 0x03)                        */
32216 #define GPIO_PINCFG35_RDZERO35_Pos        (5UL)                     /*!< RDZERO35 (Bit 5)                                      */
32217 #define GPIO_PINCFG35_RDZERO35_Msk        (0x20UL)                  /*!< RDZERO35 (Bitfield-Mask: 0x01)                        */
32218 #define GPIO_PINCFG35_INPEN35_Pos         (4UL)                     /*!< INPEN35 (Bit 4)                                       */
32219 #define GPIO_PINCFG35_INPEN35_Msk         (0x10UL)                  /*!< INPEN35 (Bitfield-Mask: 0x01)                         */
32220 #define GPIO_PINCFG35_FNCSEL35_Pos        (0UL)                     /*!< FNCSEL35 (Bit 0)                                      */
32221 #define GPIO_PINCFG35_FNCSEL35_Msk        (0xfUL)                   /*!< FNCSEL35 (Bitfield-Mask: 0x0f)                        */
32222 /* =======================================================  PINCFG36  ======================================================== */
32223 #define GPIO_PINCFG36_FOEN36_Pos          (27UL)                    /*!< FOEN36 (Bit 27)                                       */
32224 #define GPIO_PINCFG36_FOEN36_Msk          (0x8000000UL)             /*!< FOEN36 (Bitfield-Mask: 0x01)                          */
32225 #define GPIO_PINCFG36_FIEN36_Pos          (26UL)                    /*!< FIEN36 (Bit 26)                                       */
32226 #define GPIO_PINCFG36_FIEN36_Msk          (0x4000000UL)             /*!< FIEN36 (Bitfield-Mask: 0x01)                          */
32227 #define GPIO_PINCFG36_NCEPOL36_Pos        (22UL)                    /*!< NCEPOL36 (Bit 22)                                     */
32228 #define GPIO_PINCFG36_NCEPOL36_Msk        (0x400000UL)              /*!< NCEPOL36 (Bitfield-Mask: 0x01)                        */
32229 #define GPIO_PINCFG36_NCESRC36_Pos        (16UL)                    /*!< NCESRC36 (Bit 16)                                     */
32230 #define GPIO_PINCFG36_NCESRC36_Msk        (0x3f0000UL)              /*!< NCESRC36 (Bitfield-Mask: 0x3f)                        */
32231 #define GPIO_PINCFG36_PULLCFG36_Pos       (13UL)                    /*!< PULLCFG36 (Bit 13)                                    */
32232 #define GPIO_PINCFG36_PULLCFG36_Msk       (0xe000UL)                /*!< PULLCFG36 (Bitfield-Mask: 0x07)                       */
32233 #define GPIO_PINCFG36_SR36_Pos            (12UL)                    /*!< SR36 (Bit 12)                                         */
32234 #define GPIO_PINCFG36_SR36_Msk            (0x1000UL)                /*!< SR36 (Bitfield-Mask: 0x01)                            */
32235 #define GPIO_PINCFG36_DS36_Pos            (10UL)                    /*!< DS36 (Bit 10)                                         */
32236 #define GPIO_PINCFG36_DS36_Msk            (0xc00UL)                 /*!< DS36 (Bitfield-Mask: 0x03)                            */
32237 #define GPIO_PINCFG36_OUTCFG36_Pos        (8UL)                     /*!< OUTCFG36 (Bit 8)                                      */
32238 #define GPIO_PINCFG36_OUTCFG36_Msk        (0x300UL)                 /*!< OUTCFG36 (Bitfield-Mask: 0x03)                        */
32239 #define GPIO_PINCFG36_IRPTEN36_Pos        (6UL)                     /*!< IRPTEN36 (Bit 6)                                      */
32240 #define GPIO_PINCFG36_IRPTEN36_Msk        (0xc0UL)                  /*!< IRPTEN36 (Bitfield-Mask: 0x03)                        */
32241 #define GPIO_PINCFG36_RDZERO36_Pos        (5UL)                     /*!< RDZERO36 (Bit 5)                                      */
32242 #define GPIO_PINCFG36_RDZERO36_Msk        (0x20UL)                  /*!< RDZERO36 (Bitfield-Mask: 0x01)                        */
32243 #define GPIO_PINCFG36_INPEN36_Pos         (4UL)                     /*!< INPEN36 (Bit 4)                                       */
32244 #define GPIO_PINCFG36_INPEN36_Msk         (0x10UL)                  /*!< INPEN36 (Bitfield-Mask: 0x01)                         */
32245 #define GPIO_PINCFG36_FNCSEL36_Pos        (0UL)                     /*!< FNCSEL36 (Bit 0)                                      */
32246 #define GPIO_PINCFG36_FNCSEL36_Msk        (0xfUL)                   /*!< FNCSEL36 (Bitfield-Mask: 0x0f)                        */
32247 /* =======================================================  PINCFG37  ======================================================== */
32248 #define GPIO_PINCFG37_FOEN37_Pos          (27UL)                    /*!< FOEN37 (Bit 27)                                       */
32249 #define GPIO_PINCFG37_FOEN37_Msk          (0x8000000UL)             /*!< FOEN37 (Bitfield-Mask: 0x01)                          */
32250 #define GPIO_PINCFG37_FIEN37_Pos          (26UL)                    /*!< FIEN37 (Bit 26)                                       */
32251 #define GPIO_PINCFG37_FIEN37_Msk          (0x4000000UL)             /*!< FIEN37 (Bitfield-Mask: 0x01)                          */
32252 #define GPIO_PINCFG37_NCEPOL37_Pos        (22UL)                    /*!< NCEPOL37 (Bit 22)                                     */
32253 #define GPIO_PINCFG37_NCEPOL37_Msk        (0x400000UL)              /*!< NCEPOL37 (Bitfield-Mask: 0x01)                        */
32254 #define GPIO_PINCFG37_NCESRC37_Pos        (16UL)                    /*!< NCESRC37 (Bit 16)                                     */
32255 #define GPIO_PINCFG37_NCESRC37_Msk        (0x3f0000UL)              /*!< NCESRC37 (Bitfield-Mask: 0x3f)                        */
32256 #define GPIO_PINCFG37_PULLCFG37_Pos       (13UL)                    /*!< PULLCFG37 (Bit 13)                                    */
32257 #define GPIO_PINCFG37_PULLCFG37_Msk       (0xe000UL)                /*!< PULLCFG37 (Bitfield-Mask: 0x07)                       */
32258 #define GPIO_PINCFG37_SR37_Pos            (12UL)                    /*!< SR37 (Bit 12)                                         */
32259 #define GPIO_PINCFG37_SR37_Msk            (0x1000UL)                /*!< SR37 (Bitfield-Mask: 0x01)                            */
32260 #define GPIO_PINCFG37_DS37_Pos            (10UL)                    /*!< DS37 (Bit 10)                                         */
32261 #define GPIO_PINCFG37_DS37_Msk            (0xc00UL)                 /*!< DS37 (Bitfield-Mask: 0x03)                            */
32262 #define GPIO_PINCFG37_OUTCFG37_Pos        (8UL)                     /*!< OUTCFG37 (Bit 8)                                      */
32263 #define GPIO_PINCFG37_OUTCFG37_Msk        (0x300UL)                 /*!< OUTCFG37 (Bitfield-Mask: 0x03)                        */
32264 #define GPIO_PINCFG37_IRPTEN37_Pos        (6UL)                     /*!< IRPTEN37 (Bit 6)                                      */
32265 #define GPIO_PINCFG37_IRPTEN37_Msk        (0xc0UL)                  /*!< IRPTEN37 (Bitfield-Mask: 0x03)                        */
32266 #define GPIO_PINCFG37_RDZERO37_Pos        (5UL)                     /*!< RDZERO37 (Bit 5)                                      */
32267 #define GPIO_PINCFG37_RDZERO37_Msk        (0x20UL)                  /*!< RDZERO37 (Bitfield-Mask: 0x01)                        */
32268 #define GPIO_PINCFG37_INPEN37_Pos         (4UL)                     /*!< INPEN37 (Bit 4)                                       */
32269 #define GPIO_PINCFG37_INPEN37_Msk         (0x10UL)                  /*!< INPEN37 (Bitfield-Mask: 0x01)                         */
32270 #define GPIO_PINCFG37_FNCSEL37_Pos        (0UL)                     /*!< FNCSEL37 (Bit 0)                                      */
32271 #define GPIO_PINCFG37_FNCSEL37_Msk        (0xfUL)                   /*!< FNCSEL37 (Bitfield-Mask: 0x0f)                        */
32272 /* =======================================================  PINCFG38  ======================================================== */
32273 #define GPIO_PINCFG38_FOEN38_Pos          (27UL)                    /*!< FOEN38 (Bit 27)                                       */
32274 #define GPIO_PINCFG38_FOEN38_Msk          (0x8000000UL)             /*!< FOEN38 (Bitfield-Mask: 0x01)                          */
32275 #define GPIO_PINCFG38_FIEN38_Pos          (26UL)                    /*!< FIEN38 (Bit 26)                                       */
32276 #define GPIO_PINCFG38_FIEN38_Msk          (0x4000000UL)             /*!< FIEN38 (Bitfield-Mask: 0x01)                          */
32277 #define GPIO_PINCFG38_NCEPOL38_Pos        (22UL)                    /*!< NCEPOL38 (Bit 22)                                     */
32278 #define GPIO_PINCFG38_NCEPOL38_Msk        (0x400000UL)              /*!< NCEPOL38 (Bitfield-Mask: 0x01)                        */
32279 #define GPIO_PINCFG38_NCESRC38_Pos        (16UL)                    /*!< NCESRC38 (Bit 16)                                     */
32280 #define GPIO_PINCFG38_NCESRC38_Msk        (0x3f0000UL)              /*!< NCESRC38 (Bitfield-Mask: 0x3f)                        */
32281 #define GPIO_PINCFG38_PULLCFG38_Pos       (13UL)                    /*!< PULLCFG38 (Bit 13)                                    */
32282 #define GPIO_PINCFG38_PULLCFG38_Msk       (0xe000UL)                /*!< PULLCFG38 (Bitfield-Mask: 0x07)                       */
32283 #define GPIO_PINCFG38_SR38_Pos            (12UL)                    /*!< SR38 (Bit 12)                                         */
32284 #define GPIO_PINCFG38_SR38_Msk            (0x1000UL)                /*!< SR38 (Bitfield-Mask: 0x01)                            */
32285 #define GPIO_PINCFG38_DS38_Pos            (10UL)                    /*!< DS38 (Bit 10)                                         */
32286 #define GPIO_PINCFG38_DS38_Msk            (0xc00UL)                 /*!< DS38 (Bitfield-Mask: 0x03)                            */
32287 #define GPIO_PINCFG38_OUTCFG38_Pos        (8UL)                     /*!< OUTCFG38 (Bit 8)                                      */
32288 #define GPIO_PINCFG38_OUTCFG38_Msk        (0x300UL)                 /*!< OUTCFG38 (Bitfield-Mask: 0x03)                        */
32289 #define GPIO_PINCFG38_IRPTEN38_Pos        (6UL)                     /*!< IRPTEN38 (Bit 6)                                      */
32290 #define GPIO_PINCFG38_IRPTEN38_Msk        (0xc0UL)                  /*!< IRPTEN38 (Bitfield-Mask: 0x03)                        */
32291 #define GPIO_PINCFG38_RDZERO38_Pos        (5UL)                     /*!< RDZERO38 (Bit 5)                                      */
32292 #define GPIO_PINCFG38_RDZERO38_Msk        (0x20UL)                  /*!< RDZERO38 (Bitfield-Mask: 0x01)                        */
32293 #define GPIO_PINCFG38_INPEN38_Pos         (4UL)                     /*!< INPEN38 (Bit 4)                                       */
32294 #define GPIO_PINCFG38_INPEN38_Msk         (0x10UL)                  /*!< INPEN38 (Bitfield-Mask: 0x01)                         */
32295 #define GPIO_PINCFG38_FNCSEL38_Pos        (0UL)                     /*!< FNCSEL38 (Bit 0)                                      */
32296 #define GPIO_PINCFG38_FNCSEL38_Msk        (0xfUL)                   /*!< FNCSEL38 (Bitfield-Mask: 0x0f)                        */
32297 /* =======================================================  PINCFG39  ======================================================== */
32298 #define GPIO_PINCFG39_FOEN39_Pos          (27UL)                    /*!< FOEN39 (Bit 27)                                       */
32299 #define GPIO_PINCFG39_FOEN39_Msk          (0x8000000UL)             /*!< FOEN39 (Bitfield-Mask: 0x01)                          */
32300 #define GPIO_PINCFG39_FIEN39_Pos          (26UL)                    /*!< FIEN39 (Bit 26)                                       */
32301 #define GPIO_PINCFG39_FIEN39_Msk          (0x4000000UL)             /*!< FIEN39 (Bitfield-Mask: 0x01)                          */
32302 #define GPIO_PINCFG39_NCEPOL39_Pos        (22UL)                    /*!< NCEPOL39 (Bit 22)                                     */
32303 #define GPIO_PINCFG39_NCEPOL39_Msk        (0x400000UL)              /*!< NCEPOL39 (Bitfield-Mask: 0x01)                        */
32304 #define GPIO_PINCFG39_NCESRC39_Pos        (16UL)                    /*!< NCESRC39 (Bit 16)                                     */
32305 #define GPIO_PINCFG39_NCESRC39_Msk        (0x3f0000UL)              /*!< NCESRC39 (Bitfield-Mask: 0x3f)                        */
32306 #define GPIO_PINCFG39_PULLCFG39_Pos       (13UL)                    /*!< PULLCFG39 (Bit 13)                                    */
32307 #define GPIO_PINCFG39_PULLCFG39_Msk       (0xe000UL)                /*!< PULLCFG39 (Bitfield-Mask: 0x07)                       */
32308 #define GPIO_PINCFG39_SR39_Pos            (12UL)                    /*!< SR39 (Bit 12)                                         */
32309 #define GPIO_PINCFG39_SR39_Msk            (0x1000UL)                /*!< SR39 (Bitfield-Mask: 0x01)                            */
32310 #define GPIO_PINCFG39_DS39_Pos            (10UL)                    /*!< DS39 (Bit 10)                                         */
32311 #define GPIO_PINCFG39_DS39_Msk            (0xc00UL)                 /*!< DS39 (Bitfield-Mask: 0x03)                            */
32312 #define GPIO_PINCFG39_OUTCFG39_Pos        (8UL)                     /*!< OUTCFG39 (Bit 8)                                      */
32313 #define GPIO_PINCFG39_OUTCFG39_Msk        (0x300UL)                 /*!< OUTCFG39 (Bitfield-Mask: 0x03)                        */
32314 #define GPIO_PINCFG39_IRPTEN39_Pos        (6UL)                     /*!< IRPTEN39 (Bit 6)                                      */
32315 #define GPIO_PINCFG39_IRPTEN39_Msk        (0xc0UL)                  /*!< IRPTEN39 (Bitfield-Mask: 0x03)                        */
32316 #define GPIO_PINCFG39_RDZERO39_Pos        (5UL)                     /*!< RDZERO39 (Bit 5)                                      */
32317 #define GPIO_PINCFG39_RDZERO39_Msk        (0x20UL)                  /*!< RDZERO39 (Bitfield-Mask: 0x01)                        */
32318 #define GPIO_PINCFG39_INPEN39_Pos         (4UL)                     /*!< INPEN39 (Bit 4)                                       */
32319 #define GPIO_PINCFG39_INPEN39_Msk         (0x10UL)                  /*!< INPEN39 (Bitfield-Mask: 0x01)                         */
32320 #define GPIO_PINCFG39_FNCSEL39_Pos        (0UL)                     /*!< FNCSEL39 (Bit 0)                                      */
32321 #define GPIO_PINCFG39_FNCSEL39_Msk        (0xfUL)                   /*!< FNCSEL39 (Bitfield-Mask: 0x0f)                        */
32322 /* =======================================================  PINCFG40  ======================================================== */
32323 #define GPIO_PINCFG40_FOEN40_Pos          (27UL)                    /*!< FOEN40 (Bit 27)                                       */
32324 #define GPIO_PINCFG40_FOEN40_Msk          (0x8000000UL)             /*!< FOEN40 (Bitfield-Mask: 0x01)                          */
32325 #define GPIO_PINCFG40_FIEN40_Pos          (26UL)                    /*!< FIEN40 (Bit 26)                                       */
32326 #define GPIO_PINCFG40_FIEN40_Msk          (0x4000000UL)             /*!< FIEN40 (Bitfield-Mask: 0x01)                          */
32327 #define GPIO_PINCFG40_NCEPOL40_Pos        (22UL)                    /*!< NCEPOL40 (Bit 22)                                     */
32328 #define GPIO_PINCFG40_NCEPOL40_Msk        (0x400000UL)              /*!< NCEPOL40 (Bitfield-Mask: 0x01)                        */
32329 #define GPIO_PINCFG40_NCESRC40_Pos        (16UL)                    /*!< NCESRC40 (Bit 16)                                     */
32330 #define GPIO_PINCFG40_NCESRC40_Msk        (0x3f0000UL)              /*!< NCESRC40 (Bitfield-Mask: 0x3f)                        */
32331 #define GPIO_PINCFG40_PULLCFG40_Pos       (13UL)                    /*!< PULLCFG40 (Bit 13)                                    */
32332 #define GPIO_PINCFG40_PULLCFG40_Msk       (0xe000UL)                /*!< PULLCFG40 (Bitfield-Mask: 0x07)                       */
32333 #define GPIO_PINCFG40_SR40_Pos            (12UL)                    /*!< SR40 (Bit 12)                                         */
32334 #define GPIO_PINCFG40_SR40_Msk            (0x1000UL)                /*!< SR40 (Bitfield-Mask: 0x01)                            */
32335 #define GPIO_PINCFG40_DS40_Pos            (10UL)                    /*!< DS40 (Bit 10)                                         */
32336 #define GPIO_PINCFG40_DS40_Msk            (0xc00UL)                 /*!< DS40 (Bitfield-Mask: 0x03)                            */
32337 #define GPIO_PINCFG40_OUTCFG40_Pos        (8UL)                     /*!< OUTCFG40 (Bit 8)                                      */
32338 #define GPIO_PINCFG40_OUTCFG40_Msk        (0x300UL)                 /*!< OUTCFG40 (Bitfield-Mask: 0x03)                        */
32339 #define GPIO_PINCFG40_IRPTEN40_Pos        (6UL)                     /*!< IRPTEN40 (Bit 6)                                      */
32340 #define GPIO_PINCFG40_IRPTEN40_Msk        (0xc0UL)                  /*!< IRPTEN40 (Bitfield-Mask: 0x03)                        */
32341 #define GPIO_PINCFG40_RDZERO40_Pos        (5UL)                     /*!< RDZERO40 (Bit 5)                                      */
32342 #define GPIO_PINCFG40_RDZERO40_Msk        (0x20UL)                  /*!< RDZERO40 (Bitfield-Mask: 0x01)                        */
32343 #define GPIO_PINCFG40_INPEN40_Pos         (4UL)                     /*!< INPEN40 (Bit 4)                                       */
32344 #define GPIO_PINCFG40_INPEN40_Msk         (0x10UL)                  /*!< INPEN40 (Bitfield-Mask: 0x01)                         */
32345 #define GPIO_PINCFG40_FNCSEL40_Pos        (0UL)                     /*!< FNCSEL40 (Bit 0)                                      */
32346 #define GPIO_PINCFG40_FNCSEL40_Msk        (0xfUL)                   /*!< FNCSEL40 (Bitfield-Mask: 0x0f)                        */
32347 /* =======================================================  PINCFG41  ======================================================== */
32348 #define GPIO_PINCFG41_FOEN41_Pos          (27UL)                    /*!< FOEN41 (Bit 27)                                       */
32349 #define GPIO_PINCFG41_FOEN41_Msk          (0x8000000UL)             /*!< FOEN41 (Bitfield-Mask: 0x01)                          */
32350 #define GPIO_PINCFG41_FIEN41_Pos          (26UL)                    /*!< FIEN41 (Bit 26)                                       */
32351 #define GPIO_PINCFG41_FIEN41_Msk          (0x4000000UL)             /*!< FIEN41 (Bitfield-Mask: 0x01)                          */
32352 #define GPIO_PINCFG41_NCEPOL41_Pos        (22UL)                    /*!< NCEPOL41 (Bit 22)                                     */
32353 #define GPIO_PINCFG41_NCEPOL41_Msk        (0x400000UL)              /*!< NCEPOL41 (Bitfield-Mask: 0x01)                        */
32354 #define GPIO_PINCFG41_NCESRC41_Pos        (16UL)                    /*!< NCESRC41 (Bit 16)                                     */
32355 #define GPIO_PINCFG41_NCESRC41_Msk        (0x3f0000UL)              /*!< NCESRC41 (Bitfield-Mask: 0x3f)                        */
32356 #define GPIO_PINCFG41_PULLCFG41_Pos       (13UL)                    /*!< PULLCFG41 (Bit 13)                                    */
32357 #define GPIO_PINCFG41_PULLCFG41_Msk       (0xe000UL)                /*!< PULLCFG41 (Bitfield-Mask: 0x07)                       */
32358 #define GPIO_PINCFG41_SR41_Pos            (12UL)                    /*!< SR41 (Bit 12)                                         */
32359 #define GPIO_PINCFG41_SR41_Msk            (0x1000UL)                /*!< SR41 (Bitfield-Mask: 0x01)                            */
32360 #define GPIO_PINCFG41_DS41_Pos            (10UL)                    /*!< DS41 (Bit 10)                                         */
32361 #define GPIO_PINCFG41_DS41_Msk            (0xc00UL)                 /*!< DS41 (Bitfield-Mask: 0x03)                            */
32362 #define GPIO_PINCFG41_OUTCFG41_Pos        (8UL)                     /*!< OUTCFG41 (Bit 8)                                      */
32363 #define GPIO_PINCFG41_OUTCFG41_Msk        (0x300UL)                 /*!< OUTCFG41 (Bitfield-Mask: 0x03)                        */
32364 #define GPIO_PINCFG41_IRPTEN41_Pos        (6UL)                     /*!< IRPTEN41 (Bit 6)                                      */
32365 #define GPIO_PINCFG41_IRPTEN41_Msk        (0xc0UL)                  /*!< IRPTEN41 (Bitfield-Mask: 0x03)                        */
32366 #define GPIO_PINCFG41_RDZERO41_Pos        (5UL)                     /*!< RDZERO41 (Bit 5)                                      */
32367 #define GPIO_PINCFG41_RDZERO41_Msk        (0x20UL)                  /*!< RDZERO41 (Bitfield-Mask: 0x01)                        */
32368 #define GPIO_PINCFG41_INPEN41_Pos         (4UL)                     /*!< INPEN41 (Bit 4)                                       */
32369 #define GPIO_PINCFG41_INPEN41_Msk         (0x10UL)                  /*!< INPEN41 (Bitfield-Mask: 0x01)                         */
32370 #define GPIO_PINCFG41_FNCSEL41_Pos        (0UL)                     /*!< FNCSEL41 (Bit 0)                                      */
32371 #define GPIO_PINCFG41_FNCSEL41_Msk        (0xfUL)                   /*!< FNCSEL41 (Bitfield-Mask: 0x0f)                        */
32372 /* =======================================================  PINCFG42  ======================================================== */
32373 #define GPIO_PINCFG42_FOEN42_Pos          (27UL)                    /*!< FOEN42 (Bit 27)                                       */
32374 #define GPIO_PINCFG42_FOEN42_Msk          (0x8000000UL)             /*!< FOEN42 (Bitfield-Mask: 0x01)                          */
32375 #define GPIO_PINCFG42_FIEN42_Pos          (26UL)                    /*!< FIEN42 (Bit 26)                                       */
32376 #define GPIO_PINCFG42_FIEN42_Msk          (0x4000000UL)             /*!< FIEN42 (Bitfield-Mask: 0x01)                          */
32377 #define GPIO_PINCFG42_NCEPOL42_Pos        (22UL)                    /*!< NCEPOL42 (Bit 22)                                     */
32378 #define GPIO_PINCFG42_NCEPOL42_Msk        (0x400000UL)              /*!< NCEPOL42 (Bitfield-Mask: 0x01)                        */
32379 #define GPIO_PINCFG42_NCESRC42_Pos        (16UL)                    /*!< NCESRC42 (Bit 16)                                     */
32380 #define GPIO_PINCFG42_NCESRC42_Msk        (0x3f0000UL)              /*!< NCESRC42 (Bitfield-Mask: 0x3f)                        */
32381 #define GPIO_PINCFG42_PULLCFG42_Pos       (13UL)                    /*!< PULLCFG42 (Bit 13)                                    */
32382 #define GPIO_PINCFG42_PULLCFG42_Msk       (0xe000UL)                /*!< PULLCFG42 (Bitfield-Mask: 0x07)                       */
32383 #define GPIO_PINCFG42_SR42_Pos            (12UL)                    /*!< SR42 (Bit 12)                                         */
32384 #define GPIO_PINCFG42_SR42_Msk            (0x1000UL)                /*!< SR42 (Bitfield-Mask: 0x01)                            */
32385 #define GPIO_PINCFG42_DS42_Pos            (10UL)                    /*!< DS42 (Bit 10)                                         */
32386 #define GPIO_PINCFG42_DS42_Msk            (0xc00UL)                 /*!< DS42 (Bitfield-Mask: 0x03)                            */
32387 #define GPIO_PINCFG42_OUTCFG42_Pos        (8UL)                     /*!< OUTCFG42 (Bit 8)                                      */
32388 #define GPIO_PINCFG42_OUTCFG42_Msk        (0x300UL)                 /*!< OUTCFG42 (Bitfield-Mask: 0x03)                        */
32389 #define GPIO_PINCFG42_IRPTEN42_Pos        (6UL)                     /*!< IRPTEN42 (Bit 6)                                      */
32390 #define GPIO_PINCFG42_IRPTEN42_Msk        (0xc0UL)                  /*!< IRPTEN42 (Bitfield-Mask: 0x03)                        */
32391 #define GPIO_PINCFG42_RDZERO42_Pos        (5UL)                     /*!< RDZERO42 (Bit 5)                                      */
32392 #define GPIO_PINCFG42_RDZERO42_Msk        (0x20UL)                  /*!< RDZERO42 (Bitfield-Mask: 0x01)                        */
32393 #define GPIO_PINCFG42_INPEN42_Pos         (4UL)                     /*!< INPEN42 (Bit 4)                                       */
32394 #define GPIO_PINCFG42_INPEN42_Msk         (0x10UL)                  /*!< INPEN42 (Bitfield-Mask: 0x01)                         */
32395 #define GPIO_PINCFG42_FNCSEL42_Pos        (0UL)                     /*!< FNCSEL42 (Bit 0)                                      */
32396 #define GPIO_PINCFG42_FNCSEL42_Msk        (0xfUL)                   /*!< FNCSEL42 (Bitfield-Mask: 0x0f)                        */
32397 /* =======================================================  PINCFG43  ======================================================== */
32398 #define GPIO_PINCFG43_FOEN43_Pos          (27UL)                    /*!< FOEN43 (Bit 27)                                       */
32399 #define GPIO_PINCFG43_FOEN43_Msk          (0x8000000UL)             /*!< FOEN43 (Bitfield-Mask: 0x01)                          */
32400 #define GPIO_PINCFG43_FIEN43_Pos          (26UL)                    /*!< FIEN43 (Bit 26)                                       */
32401 #define GPIO_PINCFG43_FIEN43_Msk          (0x4000000UL)             /*!< FIEN43 (Bitfield-Mask: 0x01)                          */
32402 #define GPIO_PINCFG43_NCEPOL43_Pos        (22UL)                    /*!< NCEPOL43 (Bit 22)                                     */
32403 #define GPIO_PINCFG43_NCEPOL43_Msk        (0x400000UL)              /*!< NCEPOL43 (Bitfield-Mask: 0x01)                        */
32404 #define GPIO_PINCFG43_NCESRC43_Pos        (16UL)                    /*!< NCESRC43 (Bit 16)                                     */
32405 #define GPIO_PINCFG43_NCESRC43_Msk        (0x3f0000UL)              /*!< NCESRC43 (Bitfield-Mask: 0x3f)                        */
32406 #define GPIO_PINCFG43_PULLCFG43_Pos       (13UL)                    /*!< PULLCFG43 (Bit 13)                                    */
32407 #define GPIO_PINCFG43_PULLCFG43_Msk       (0xe000UL)                /*!< PULLCFG43 (Bitfield-Mask: 0x07)                       */
32408 #define GPIO_PINCFG43_SR43_Pos            (12UL)                    /*!< SR43 (Bit 12)                                         */
32409 #define GPIO_PINCFG43_SR43_Msk            (0x1000UL)                /*!< SR43 (Bitfield-Mask: 0x01)                            */
32410 #define GPIO_PINCFG43_DS43_Pos            (10UL)                    /*!< DS43 (Bit 10)                                         */
32411 #define GPIO_PINCFG43_DS43_Msk            (0xc00UL)                 /*!< DS43 (Bitfield-Mask: 0x03)                            */
32412 #define GPIO_PINCFG43_OUTCFG43_Pos        (8UL)                     /*!< OUTCFG43 (Bit 8)                                      */
32413 #define GPIO_PINCFG43_OUTCFG43_Msk        (0x300UL)                 /*!< OUTCFG43 (Bitfield-Mask: 0x03)                        */
32414 #define GPIO_PINCFG43_IRPTEN43_Pos        (6UL)                     /*!< IRPTEN43 (Bit 6)                                      */
32415 #define GPIO_PINCFG43_IRPTEN43_Msk        (0xc0UL)                  /*!< IRPTEN43 (Bitfield-Mask: 0x03)                        */
32416 #define GPIO_PINCFG43_RDZERO43_Pos        (5UL)                     /*!< RDZERO43 (Bit 5)                                      */
32417 #define GPIO_PINCFG43_RDZERO43_Msk        (0x20UL)                  /*!< RDZERO43 (Bitfield-Mask: 0x01)                        */
32418 #define GPIO_PINCFG43_INPEN43_Pos         (4UL)                     /*!< INPEN43 (Bit 4)                                       */
32419 #define GPIO_PINCFG43_INPEN43_Msk         (0x10UL)                  /*!< INPEN43 (Bitfield-Mask: 0x01)                         */
32420 #define GPIO_PINCFG43_FNCSEL43_Pos        (0UL)                     /*!< FNCSEL43 (Bit 0)                                      */
32421 #define GPIO_PINCFG43_FNCSEL43_Msk        (0xfUL)                   /*!< FNCSEL43 (Bitfield-Mask: 0x0f)                        */
32422 /* =======================================================  PINCFG44  ======================================================== */
32423 #define GPIO_PINCFG44_FOEN44_Pos          (27UL)                    /*!< FOEN44 (Bit 27)                                       */
32424 #define GPIO_PINCFG44_FOEN44_Msk          (0x8000000UL)             /*!< FOEN44 (Bitfield-Mask: 0x01)                          */
32425 #define GPIO_PINCFG44_FIEN44_Pos          (26UL)                    /*!< FIEN44 (Bit 26)                                       */
32426 #define GPIO_PINCFG44_FIEN44_Msk          (0x4000000UL)             /*!< FIEN44 (Bitfield-Mask: 0x01)                          */
32427 #define GPIO_PINCFG44_NCEPOL44_Pos        (22UL)                    /*!< NCEPOL44 (Bit 22)                                     */
32428 #define GPIO_PINCFG44_NCEPOL44_Msk        (0x400000UL)              /*!< NCEPOL44 (Bitfield-Mask: 0x01)                        */
32429 #define GPIO_PINCFG44_NCESRC44_Pos        (16UL)                    /*!< NCESRC44 (Bit 16)                                     */
32430 #define GPIO_PINCFG44_NCESRC44_Msk        (0x3f0000UL)              /*!< NCESRC44 (Bitfield-Mask: 0x3f)                        */
32431 #define GPIO_PINCFG44_PULLCFG44_Pos       (13UL)                    /*!< PULLCFG44 (Bit 13)                                    */
32432 #define GPIO_PINCFG44_PULLCFG44_Msk       (0xe000UL)                /*!< PULLCFG44 (Bitfield-Mask: 0x07)                       */
32433 #define GPIO_PINCFG44_SR44_Pos            (12UL)                    /*!< SR44 (Bit 12)                                         */
32434 #define GPIO_PINCFG44_SR44_Msk            (0x1000UL)                /*!< SR44 (Bitfield-Mask: 0x01)                            */
32435 #define GPIO_PINCFG44_DS44_Pos            (10UL)                    /*!< DS44 (Bit 10)                                         */
32436 #define GPIO_PINCFG44_DS44_Msk            (0xc00UL)                 /*!< DS44 (Bitfield-Mask: 0x03)                            */
32437 #define GPIO_PINCFG44_OUTCFG44_Pos        (8UL)                     /*!< OUTCFG44 (Bit 8)                                      */
32438 #define GPIO_PINCFG44_OUTCFG44_Msk        (0x300UL)                 /*!< OUTCFG44 (Bitfield-Mask: 0x03)                        */
32439 #define GPIO_PINCFG44_IRPTEN44_Pos        (6UL)                     /*!< IRPTEN44 (Bit 6)                                      */
32440 #define GPIO_PINCFG44_IRPTEN44_Msk        (0xc0UL)                  /*!< IRPTEN44 (Bitfield-Mask: 0x03)                        */
32441 #define GPIO_PINCFG44_RDZERO44_Pos        (5UL)                     /*!< RDZERO44 (Bit 5)                                      */
32442 #define GPIO_PINCFG44_RDZERO44_Msk        (0x20UL)                  /*!< RDZERO44 (Bitfield-Mask: 0x01)                        */
32443 #define GPIO_PINCFG44_INPEN44_Pos         (4UL)                     /*!< INPEN44 (Bit 4)                                       */
32444 #define GPIO_PINCFG44_INPEN44_Msk         (0x10UL)                  /*!< INPEN44 (Bitfield-Mask: 0x01)                         */
32445 #define GPIO_PINCFG44_FNCSEL44_Pos        (0UL)                     /*!< FNCSEL44 (Bit 0)                                      */
32446 #define GPIO_PINCFG44_FNCSEL44_Msk        (0xfUL)                   /*!< FNCSEL44 (Bitfield-Mask: 0x0f)                        */
32447 /* =======================================================  PINCFG45  ======================================================== */
32448 #define GPIO_PINCFG45_FOEN45_Pos          (27UL)                    /*!< FOEN45 (Bit 27)                                       */
32449 #define GPIO_PINCFG45_FOEN45_Msk          (0x8000000UL)             /*!< FOEN45 (Bitfield-Mask: 0x01)                          */
32450 #define GPIO_PINCFG45_FIEN45_Pos          (26UL)                    /*!< FIEN45 (Bit 26)                                       */
32451 #define GPIO_PINCFG45_FIEN45_Msk          (0x4000000UL)             /*!< FIEN45 (Bitfield-Mask: 0x01)                          */
32452 #define GPIO_PINCFG45_NCEPOL45_Pos        (22UL)                    /*!< NCEPOL45 (Bit 22)                                     */
32453 #define GPIO_PINCFG45_NCEPOL45_Msk        (0x400000UL)              /*!< NCEPOL45 (Bitfield-Mask: 0x01)                        */
32454 #define GPIO_PINCFG45_NCESRC45_Pos        (16UL)                    /*!< NCESRC45 (Bit 16)                                     */
32455 #define GPIO_PINCFG45_NCESRC45_Msk        (0x3f0000UL)              /*!< NCESRC45 (Bitfield-Mask: 0x3f)                        */
32456 #define GPIO_PINCFG45_PULLCFG45_Pos       (13UL)                    /*!< PULLCFG45 (Bit 13)                                    */
32457 #define GPIO_PINCFG45_PULLCFG45_Msk       (0xe000UL)                /*!< PULLCFG45 (Bitfield-Mask: 0x07)                       */
32458 #define GPIO_PINCFG45_SR45_Pos            (12UL)                    /*!< SR45 (Bit 12)                                         */
32459 #define GPIO_PINCFG45_SR45_Msk            (0x1000UL)                /*!< SR45 (Bitfield-Mask: 0x01)                            */
32460 #define GPIO_PINCFG45_DS45_Pos            (10UL)                    /*!< DS45 (Bit 10)                                         */
32461 #define GPIO_PINCFG45_DS45_Msk            (0xc00UL)                 /*!< DS45 (Bitfield-Mask: 0x03)                            */
32462 #define GPIO_PINCFG45_OUTCFG45_Pos        (8UL)                     /*!< OUTCFG45 (Bit 8)                                      */
32463 #define GPIO_PINCFG45_OUTCFG45_Msk        (0x300UL)                 /*!< OUTCFG45 (Bitfield-Mask: 0x03)                        */
32464 #define GPIO_PINCFG45_IRPTEN45_Pos        (6UL)                     /*!< IRPTEN45 (Bit 6)                                      */
32465 #define GPIO_PINCFG45_IRPTEN45_Msk        (0xc0UL)                  /*!< IRPTEN45 (Bitfield-Mask: 0x03)                        */
32466 #define GPIO_PINCFG45_RDZERO45_Pos        (5UL)                     /*!< RDZERO45 (Bit 5)                                      */
32467 #define GPIO_PINCFG45_RDZERO45_Msk        (0x20UL)                  /*!< RDZERO45 (Bitfield-Mask: 0x01)                        */
32468 #define GPIO_PINCFG45_INPEN45_Pos         (4UL)                     /*!< INPEN45 (Bit 4)                                       */
32469 #define GPIO_PINCFG45_INPEN45_Msk         (0x10UL)                  /*!< INPEN45 (Bitfield-Mask: 0x01)                         */
32470 #define GPIO_PINCFG45_FNCSEL45_Pos        (0UL)                     /*!< FNCSEL45 (Bit 0)                                      */
32471 #define GPIO_PINCFG45_FNCSEL45_Msk        (0xfUL)                   /*!< FNCSEL45 (Bitfield-Mask: 0x0f)                        */
32472 /* =======================================================  PINCFG46  ======================================================== */
32473 #define GPIO_PINCFG46_FOEN46_Pos          (27UL)                    /*!< FOEN46 (Bit 27)                                       */
32474 #define GPIO_PINCFG46_FOEN46_Msk          (0x8000000UL)             /*!< FOEN46 (Bitfield-Mask: 0x01)                          */
32475 #define GPIO_PINCFG46_FIEN46_Pos          (26UL)                    /*!< FIEN46 (Bit 26)                                       */
32476 #define GPIO_PINCFG46_FIEN46_Msk          (0x4000000UL)             /*!< FIEN46 (Bitfield-Mask: 0x01)                          */
32477 #define GPIO_PINCFG46_NCEPOL46_Pos        (22UL)                    /*!< NCEPOL46 (Bit 22)                                     */
32478 #define GPIO_PINCFG46_NCEPOL46_Msk        (0x400000UL)              /*!< NCEPOL46 (Bitfield-Mask: 0x01)                        */
32479 #define GPIO_PINCFG46_NCESRC46_Pos        (16UL)                    /*!< NCESRC46 (Bit 16)                                     */
32480 #define GPIO_PINCFG46_NCESRC46_Msk        (0x3f0000UL)              /*!< NCESRC46 (Bitfield-Mask: 0x3f)                        */
32481 #define GPIO_PINCFG46_PULLCFG46_Pos       (13UL)                    /*!< PULLCFG46 (Bit 13)                                    */
32482 #define GPIO_PINCFG46_PULLCFG46_Msk       (0xe000UL)                /*!< PULLCFG46 (Bitfield-Mask: 0x07)                       */
32483 #define GPIO_PINCFG46_SR46_Pos            (12UL)                    /*!< SR46 (Bit 12)                                         */
32484 #define GPIO_PINCFG46_SR46_Msk            (0x1000UL)                /*!< SR46 (Bitfield-Mask: 0x01)                            */
32485 #define GPIO_PINCFG46_DS46_Pos            (10UL)                    /*!< DS46 (Bit 10)                                         */
32486 #define GPIO_PINCFG46_DS46_Msk            (0xc00UL)                 /*!< DS46 (Bitfield-Mask: 0x03)                            */
32487 #define GPIO_PINCFG46_OUTCFG46_Pos        (8UL)                     /*!< OUTCFG46 (Bit 8)                                      */
32488 #define GPIO_PINCFG46_OUTCFG46_Msk        (0x300UL)                 /*!< OUTCFG46 (Bitfield-Mask: 0x03)                        */
32489 #define GPIO_PINCFG46_IRPTEN46_Pos        (6UL)                     /*!< IRPTEN46 (Bit 6)                                      */
32490 #define GPIO_PINCFG46_IRPTEN46_Msk        (0xc0UL)                  /*!< IRPTEN46 (Bitfield-Mask: 0x03)                        */
32491 #define GPIO_PINCFG46_RDZERO46_Pos        (5UL)                     /*!< RDZERO46 (Bit 5)                                      */
32492 #define GPIO_PINCFG46_RDZERO46_Msk        (0x20UL)                  /*!< RDZERO46 (Bitfield-Mask: 0x01)                        */
32493 #define GPIO_PINCFG46_INPEN46_Pos         (4UL)                     /*!< INPEN46 (Bit 4)                                       */
32494 #define GPIO_PINCFG46_INPEN46_Msk         (0x10UL)                  /*!< INPEN46 (Bitfield-Mask: 0x01)                         */
32495 #define GPIO_PINCFG46_FNCSEL46_Pos        (0UL)                     /*!< FNCSEL46 (Bit 0)                                      */
32496 #define GPIO_PINCFG46_FNCSEL46_Msk        (0xfUL)                   /*!< FNCSEL46 (Bitfield-Mask: 0x0f)                        */
32497 /* =======================================================  PINCFG47  ======================================================== */
32498 #define GPIO_PINCFG47_FOEN47_Pos          (27UL)                    /*!< FOEN47 (Bit 27)                                       */
32499 #define GPIO_PINCFG47_FOEN47_Msk          (0x8000000UL)             /*!< FOEN47 (Bitfield-Mask: 0x01)                          */
32500 #define GPIO_PINCFG47_FIEN47_Pos          (26UL)                    /*!< FIEN47 (Bit 26)                                       */
32501 #define GPIO_PINCFG47_FIEN47_Msk          (0x4000000UL)             /*!< FIEN47 (Bitfield-Mask: 0x01)                          */
32502 #define GPIO_PINCFG47_NCEPOL47_Pos        (22UL)                    /*!< NCEPOL47 (Bit 22)                                     */
32503 #define GPIO_PINCFG47_NCEPOL47_Msk        (0x400000UL)              /*!< NCEPOL47 (Bitfield-Mask: 0x01)                        */
32504 #define GPIO_PINCFG47_NCESRC47_Pos        (16UL)                    /*!< NCESRC47 (Bit 16)                                     */
32505 #define GPIO_PINCFG47_NCESRC47_Msk        (0x3f0000UL)              /*!< NCESRC47 (Bitfield-Mask: 0x3f)                        */
32506 #define GPIO_PINCFG47_PULLCFG47_Pos       (13UL)                    /*!< PULLCFG47 (Bit 13)                                    */
32507 #define GPIO_PINCFG47_PULLCFG47_Msk       (0xe000UL)                /*!< PULLCFG47 (Bitfield-Mask: 0x07)                       */
32508 #define GPIO_PINCFG47_SR47_Pos            (12UL)                    /*!< SR47 (Bit 12)                                         */
32509 #define GPIO_PINCFG47_SR47_Msk            (0x1000UL)                /*!< SR47 (Bitfield-Mask: 0x01)                            */
32510 #define GPIO_PINCFG47_DS47_Pos            (10UL)                    /*!< DS47 (Bit 10)                                         */
32511 #define GPIO_PINCFG47_DS47_Msk            (0xc00UL)                 /*!< DS47 (Bitfield-Mask: 0x03)                            */
32512 #define GPIO_PINCFG47_OUTCFG47_Pos        (8UL)                     /*!< OUTCFG47 (Bit 8)                                      */
32513 #define GPIO_PINCFG47_OUTCFG47_Msk        (0x300UL)                 /*!< OUTCFG47 (Bitfield-Mask: 0x03)                        */
32514 #define GPIO_PINCFG47_IRPTEN47_Pos        (6UL)                     /*!< IRPTEN47 (Bit 6)                                      */
32515 #define GPIO_PINCFG47_IRPTEN47_Msk        (0xc0UL)                  /*!< IRPTEN47 (Bitfield-Mask: 0x03)                        */
32516 #define GPIO_PINCFG47_RDZERO47_Pos        (5UL)                     /*!< RDZERO47 (Bit 5)                                      */
32517 #define GPIO_PINCFG47_RDZERO47_Msk        (0x20UL)                  /*!< RDZERO47 (Bitfield-Mask: 0x01)                        */
32518 #define GPIO_PINCFG47_INPEN47_Pos         (4UL)                     /*!< INPEN47 (Bit 4)                                       */
32519 #define GPIO_PINCFG47_INPEN47_Msk         (0x10UL)                  /*!< INPEN47 (Bitfield-Mask: 0x01)                         */
32520 #define GPIO_PINCFG47_FNCSEL47_Pos        (0UL)                     /*!< FNCSEL47 (Bit 0)                                      */
32521 #define GPIO_PINCFG47_FNCSEL47_Msk        (0xfUL)                   /*!< FNCSEL47 (Bitfield-Mask: 0x0f)                        */
32522 /* =======================================================  PINCFG48  ======================================================== */
32523 #define GPIO_PINCFG48_FOEN48_Pos          (27UL)                    /*!< FOEN48 (Bit 27)                                       */
32524 #define GPIO_PINCFG48_FOEN48_Msk          (0x8000000UL)             /*!< FOEN48 (Bitfield-Mask: 0x01)                          */
32525 #define GPIO_PINCFG48_FIEN48_Pos          (26UL)                    /*!< FIEN48 (Bit 26)                                       */
32526 #define GPIO_PINCFG48_FIEN48_Msk          (0x4000000UL)             /*!< FIEN48 (Bitfield-Mask: 0x01)                          */
32527 #define GPIO_PINCFG48_NCEPOL48_Pos        (22UL)                    /*!< NCEPOL48 (Bit 22)                                     */
32528 #define GPIO_PINCFG48_NCEPOL48_Msk        (0x400000UL)              /*!< NCEPOL48 (Bitfield-Mask: 0x01)                        */
32529 #define GPIO_PINCFG48_NCESRC48_Pos        (16UL)                    /*!< NCESRC48 (Bit 16)                                     */
32530 #define GPIO_PINCFG48_NCESRC48_Msk        (0x3f0000UL)              /*!< NCESRC48 (Bitfield-Mask: 0x3f)                        */
32531 #define GPIO_PINCFG48_PULLCFG48_Pos       (13UL)                    /*!< PULLCFG48 (Bit 13)                                    */
32532 #define GPIO_PINCFG48_PULLCFG48_Msk       (0xe000UL)                /*!< PULLCFG48 (Bitfield-Mask: 0x07)                       */
32533 #define GPIO_PINCFG48_SR48_Pos            (12UL)                    /*!< SR48 (Bit 12)                                         */
32534 #define GPIO_PINCFG48_SR48_Msk            (0x1000UL)                /*!< SR48 (Bitfield-Mask: 0x01)                            */
32535 #define GPIO_PINCFG48_DS48_Pos            (10UL)                    /*!< DS48 (Bit 10)                                         */
32536 #define GPIO_PINCFG48_DS48_Msk            (0xc00UL)                 /*!< DS48 (Bitfield-Mask: 0x03)                            */
32537 #define GPIO_PINCFG48_OUTCFG48_Pos        (8UL)                     /*!< OUTCFG48 (Bit 8)                                      */
32538 #define GPIO_PINCFG48_OUTCFG48_Msk        (0x300UL)                 /*!< OUTCFG48 (Bitfield-Mask: 0x03)                        */
32539 #define GPIO_PINCFG48_IRPTEN48_Pos        (6UL)                     /*!< IRPTEN48 (Bit 6)                                      */
32540 #define GPIO_PINCFG48_IRPTEN48_Msk        (0xc0UL)                  /*!< IRPTEN48 (Bitfield-Mask: 0x03)                        */
32541 #define GPIO_PINCFG48_RDZERO48_Pos        (5UL)                     /*!< RDZERO48 (Bit 5)                                      */
32542 #define GPIO_PINCFG48_RDZERO48_Msk        (0x20UL)                  /*!< RDZERO48 (Bitfield-Mask: 0x01)                        */
32543 #define GPIO_PINCFG48_INPEN48_Pos         (4UL)                     /*!< INPEN48 (Bit 4)                                       */
32544 #define GPIO_PINCFG48_INPEN48_Msk         (0x10UL)                  /*!< INPEN48 (Bitfield-Mask: 0x01)                         */
32545 #define GPIO_PINCFG48_FNCSEL48_Pos        (0UL)                     /*!< FNCSEL48 (Bit 0)                                      */
32546 #define GPIO_PINCFG48_FNCSEL48_Msk        (0xfUL)                   /*!< FNCSEL48 (Bitfield-Mask: 0x0f)                        */
32547 /* =======================================================  PINCFG49  ======================================================== */
32548 #define GPIO_PINCFG49_FOEN49_Pos          (27UL)                    /*!< FOEN49 (Bit 27)                                       */
32549 #define GPIO_PINCFG49_FOEN49_Msk          (0x8000000UL)             /*!< FOEN49 (Bitfield-Mask: 0x01)                          */
32550 #define GPIO_PINCFG49_FIEN49_Pos          (26UL)                    /*!< FIEN49 (Bit 26)                                       */
32551 #define GPIO_PINCFG49_FIEN49_Msk          (0x4000000UL)             /*!< FIEN49 (Bitfield-Mask: 0x01)                          */
32552 #define GPIO_PINCFG49_NCEPOL49_Pos        (22UL)                    /*!< NCEPOL49 (Bit 22)                                     */
32553 #define GPIO_PINCFG49_NCEPOL49_Msk        (0x400000UL)              /*!< NCEPOL49 (Bitfield-Mask: 0x01)                        */
32554 #define GPIO_PINCFG49_NCESRC49_Pos        (16UL)                    /*!< NCESRC49 (Bit 16)                                     */
32555 #define GPIO_PINCFG49_NCESRC49_Msk        (0x3f0000UL)              /*!< NCESRC49 (Bitfield-Mask: 0x3f)                        */
32556 #define GPIO_PINCFG49_PULLCFG49_Pos       (13UL)                    /*!< PULLCFG49 (Bit 13)                                    */
32557 #define GPIO_PINCFG49_PULLCFG49_Msk       (0xe000UL)                /*!< PULLCFG49 (Bitfield-Mask: 0x07)                       */
32558 #define GPIO_PINCFG49_SR49_Pos            (12UL)                    /*!< SR49 (Bit 12)                                         */
32559 #define GPIO_PINCFG49_SR49_Msk            (0x1000UL)                /*!< SR49 (Bitfield-Mask: 0x01)                            */
32560 #define GPIO_PINCFG49_DS49_Pos            (10UL)                    /*!< DS49 (Bit 10)                                         */
32561 #define GPIO_PINCFG49_DS49_Msk            (0xc00UL)                 /*!< DS49 (Bitfield-Mask: 0x03)                            */
32562 #define GPIO_PINCFG49_OUTCFG49_Pos        (8UL)                     /*!< OUTCFG49 (Bit 8)                                      */
32563 #define GPIO_PINCFG49_OUTCFG49_Msk        (0x300UL)                 /*!< OUTCFG49 (Bitfield-Mask: 0x03)                        */
32564 #define GPIO_PINCFG49_IRPTEN49_Pos        (6UL)                     /*!< IRPTEN49 (Bit 6)                                      */
32565 #define GPIO_PINCFG49_IRPTEN49_Msk        (0xc0UL)                  /*!< IRPTEN49 (Bitfield-Mask: 0x03)                        */
32566 #define GPIO_PINCFG49_RDZERO49_Pos        (5UL)                     /*!< RDZERO49 (Bit 5)                                      */
32567 #define GPIO_PINCFG49_RDZERO49_Msk        (0x20UL)                  /*!< RDZERO49 (Bitfield-Mask: 0x01)                        */
32568 #define GPIO_PINCFG49_INPEN49_Pos         (4UL)                     /*!< INPEN49 (Bit 4)                                       */
32569 #define GPIO_PINCFG49_INPEN49_Msk         (0x10UL)                  /*!< INPEN49 (Bitfield-Mask: 0x01)                         */
32570 #define GPIO_PINCFG49_FNCSEL49_Pos        (0UL)                     /*!< FNCSEL49 (Bit 0)                                      */
32571 #define GPIO_PINCFG49_FNCSEL49_Msk        (0xfUL)                   /*!< FNCSEL49 (Bitfield-Mask: 0x0f)                        */
32572 /* =======================================================  PINCFG50  ======================================================== */
32573 #define GPIO_PINCFG50_FOEN50_Pos          (27UL)                    /*!< FOEN50 (Bit 27)                                       */
32574 #define GPIO_PINCFG50_FOEN50_Msk          (0x8000000UL)             /*!< FOEN50 (Bitfield-Mask: 0x01)                          */
32575 #define GPIO_PINCFG50_FIEN50_Pos          (26UL)                    /*!< FIEN50 (Bit 26)                                       */
32576 #define GPIO_PINCFG50_FIEN50_Msk          (0x4000000UL)             /*!< FIEN50 (Bitfield-Mask: 0x01)                          */
32577 #define GPIO_PINCFG50_NCEPOL50_Pos        (22UL)                    /*!< NCEPOL50 (Bit 22)                                     */
32578 #define GPIO_PINCFG50_NCEPOL50_Msk        (0x400000UL)              /*!< NCEPOL50 (Bitfield-Mask: 0x01)                        */
32579 #define GPIO_PINCFG50_NCESRC50_Pos        (16UL)                    /*!< NCESRC50 (Bit 16)                                     */
32580 #define GPIO_PINCFG50_NCESRC50_Msk        (0x3f0000UL)              /*!< NCESRC50 (Bitfield-Mask: 0x3f)                        */
32581 #define GPIO_PINCFG50_PULLCFG50_Pos       (13UL)                    /*!< PULLCFG50 (Bit 13)                                    */
32582 #define GPIO_PINCFG50_PULLCFG50_Msk       (0xe000UL)                /*!< PULLCFG50 (Bitfield-Mask: 0x07)                       */
32583 #define GPIO_PINCFG50_SR50_Pos            (12UL)                    /*!< SR50 (Bit 12)                                         */
32584 #define GPIO_PINCFG50_SR50_Msk            (0x1000UL)                /*!< SR50 (Bitfield-Mask: 0x01)                            */
32585 #define GPIO_PINCFG50_DS50_Pos            (10UL)                    /*!< DS50 (Bit 10)                                         */
32586 #define GPIO_PINCFG50_DS50_Msk            (0xc00UL)                 /*!< DS50 (Bitfield-Mask: 0x03)                            */
32587 #define GPIO_PINCFG50_OUTCFG50_Pos        (8UL)                     /*!< OUTCFG50 (Bit 8)                                      */
32588 #define GPIO_PINCFG50_OUTCFG50_Msk        (0x300UL)                 /*!< OUTCFG50 (Bitfield-Mask: 0x03)                        */
32589 #define GPIO_PINCFG50_IRPTEN50_Pos        (6UL)                     /*!< IRPTEN50 (Bit 6)                                      */
32590 #define GPIO_PINCFG50_IRPTEN50_Msk        (0xc0UL)                  /*!< IRPTEN50 (Bitfield-Mask: 0x03)                        */
32591 #define GPIO_PINCFG50_RDZERO50_Pos        (5UL)                     /*!< RDZERO50 (Bit 5)                                      */
32592 #define GPIO_PINCFG50_RDZERO50_Msk        (0x20UL)                  /*!< RDZERO50 (Bitfield-Mask: 0x01)                        */
32593 #define GPIO_PINCFG50_INPEN50_Pos         (4UL)                     /*!< INPEN50 (Bit 4)                                       */
32594 #define GPIO_PINCFG50_INPEN50_Msk         (0x10UL)                  /*!< INPEN50 (Bitfield-Mask: 0x01)                         */
32595 #define GPIO_PINCFG50_FNCSEL50_Pos        (0UL)                     /*!< FNCSEL50 (Bit 0)                                      */
32596 #define GPIO_PINCFG50_FNCSEL50_Msk        (0xfUL)                   /*!< FNCSEL50 (Bitfield-Mask: 0x0f)                        */
32597 /* =======================================================  PINCFG51  ======================================================== */
32598 #define GPIO_PINCFG51_FOEN51_Pos          (27UL)                    /*!< FOEN51 (Bit 27)                                       */
32599 #define GPIO_PINCFG51_FOEN51_Msk          (0x8000000UL)             /*!< FOEN51 (Bitfield-Mask: 0x01)                          */
32600 #define GPIO_PINCFG51_FIEN51_Pos          (26UL)                    /*!< FIEN51 (Bit 26)                                       */
32601 #define GPIO_PINCFG51_FIEN51_Msk          (0x4000000UL)             /*!< FIEN51 (Bitfield-Mask: 0x01)                          */
32602 #define GPIO_PINCFG51_NCEPOL51_Pos        (22UL)                    /*!< NCEPOL51 (Bit 22)                                     */
32603 #define GPIO_PINCFG51_NCEPOL51_Msk        (0x400000UL)              /*!< NCEPOL51 (Bitfield-Mask: 0x01)                        */
32604 #define GPIO_PINCFG51_NCESRC51_Pos        (16UL)                    /*!< NCESRC51 (Bit 16)                                     */
32605 #define GPIO_PINCFG51_NCESRC51_Msk        (0x3f0000UL)              /*!< NCESRC51 (Bitfield-Mask: 0x3f)                        */
32606 #define GPIO_PINCFG51_PULLCFG51_Pos       (13UL)                    /*!< PULLCFG51 (Bit 13)                                    */
32607 #define GPIO_PINCFG51_PULLCFG51_Msk       (0xe000UL)                /*!< PULLCFG51 (Bitfield-Mask: 0x07)                       */
32608 #define GPIO_PINCFG51_SR51_Pos            (12UL)                    /*!< SR51 (Bit 12)                                         */
32609 #define GPIO_PINCFG51_SR51_Msk            (0x1000UL)                /*!< SR51 (Bitfield-Mask: 0x01)                            */
32610 #define GPIO_PINCFG51_DS51_Pos            (10UL)                    /*!< DS51 (Bit 10)                                         */
32611 #define GPIO_PINCFG51_DS51_Msk            (0xc00UL)                 /*!< DS51 (Bitfield-Mask: 0x03)                            */
32612 #define GPIO_PINCFG51_OUTCFG51_Pos        (8UL)                     /*!< OUTCFG51 (Bit 8)                                      */
32613 #define GPIO_PINCFG51_OUTCFG51_Msk        (0x300UL)                 /*!< OUTCFG51 (Bitfield-Mask: 0x03)                        */
32614 #define GPIO_PINCFG51_IRPTEN51_Pos        (6UL)                     /*!< IRPTEN51 (Bit 6)                                      */
32615 #define GPIO_PINCFG51_IRPTEN51_Msk        (0xc0UL)                  /*!< IRPTEN51 (Bitfield-Mask: 0x03)                        */
32616 #define GPIO_PINCFG51_RDZERO51_Pos        (5UL)                     /*!< RDZERO51 (Bit 5)                                      */
32617 #define GPIO_PINCFG51_RDZERO51_Msk        (0x20UL)                  /*!< RDZERO51 (Bitfield-Mask: 0x01)                        */
32618 #define GPIO_PINCFG51_INPEN51_Pos         (4UL)                     /*!< INPEN51 (Bit 4)                                       */
32619 #define GPIO_PINCFG51_INPEN51_Msk         (0x10UL)                  /*!< INPEN51 (Bitfield-Mask: 0x01)                         */
32620 #define GPIO_PINCFG51_FNCSEL51_Pos        (0UL)                     /*!< FNCSEL51 (Bit 0)                                      */
32621 #define GPIO_PINCFG51_FNCSEL51_Msk        (0xfUL)                   /*!< FNCSEL51 (Bitfield-Mask: 0x0f)                        */
32622 /* =======================================================  PINCFG52  ======================================================== */
32623 #define GPIO_PINCFG52_FOEN52_Pos          (27UL)                    /*!< FOEN52 (Bit 27)                                       */
32624 #define GPIO_PINCFG52_FOEN52_Msk          (0x8000000UL)             /*!< FOEN52 (Bitfield-Mask: 0x01)                          */
32625 #define GPIO_PINCFG52_FIEN52_Pos          (26UL)                    /*!< FIEN52 (Bit 26)                                       */
32626 #define GPIO_PINCFG52_FIEN52_Msk          (0x4000000UL)             /*!< FIEN52 (Bitfield-Mask: 0x01)                          */
32627 #define GPIO_PINCFG52_NCEPOL52_Pos        (22UL)                    /*!< NCEPOL52 (Bit 22)                                     */
32628 #define GPIO_PINCFG52_NCEPOL52_Msk        (0x400000UL)              /*!< NCEPOL52 (Bitfield-Mask: 0x01)                        */
32629 #define GPIO_PINCFG52_NCESRC52_Pos        (16UL)                    /*!< NCESRC52 (Bit 16)                                     */
32630 #define GPIO_PINCFG52_NCESRC52_Msk        (0x3f0000UL)              /*!< NCESRC52 (Bitfield-Mask: 0x3f)                        */
32631 #define GPIO_PINCFG52_PULLCFG52_Pos       (13UL)                    /*!< PULLCFG52 (Bit 13)                                    */
32632 #define GPIO_PINCFG52_PULLCFG52_Msk       (0xe000UL)                /*!< PULLCFG52 (Bitfield-Mask: 0x07)                       */
32633 #define GPIO_PINCFG52_SR52_Pos            (12UL)                    /*!< SR52 (Bit 12)                                         */
32634 #define GPIO_PINCFG52_SR52_Msk            (0x1000UL)                /*!< SR52 (Bitfield-Mask: 0x01)                            */
32635 #define GPIO_PINCFG52_DS52_Pos            (10UL)                    /*!< DS52 (Bit 10)                                         */
32636 #define GPIO_PINCFG52_DS52_Msk            (0xc00UL)                 /*!< DS52 (Bitfield-Mask: 0x03)                            */
32637 #define GPIO_PINCFG52_OUTCFG52_Pos        (8UL)                     /*!< OUTCFG52 (Bit 8)                                      */
32638 #define GPIO_PINCFG52_OUTCFG52_Msk        (0x300UL)                 /*!< OUTCFG52 (Bitfield-Mask: 0x03)                        */
32639 #define GPIO_PINCFG52_IRPTEN52_Pos        (6UL)                     /*!< IRPTEN52 (Bit 6)                                      */
32640 #define GPIO_PINCFG52_IRPTEN52_Msk        (0xc0UL)                  /*!< IRPTEN52 (Bitfield-Mask: 0x03)                        */
32641 #define GPIO_PINCFG52_RDZERO52_Pos        (5UL)                     /*!< RDZERO52 (Bit 5)                                      */
32642 #define GPIO_PINCFG52_RDZERO52_Msk        (0x20UL)                  /*!< RDZERO52 (Bitfield-Mask: 0x01)                        */
32643 #define GPIO_PINCFG52_INPEN52_Pos         (4UL)                     /*!< INPEN52 (Bit 4)                                       */
32644 #define GPIO_PINCFG52_INPEN52_Msk         (0x10UL)                  /*!< INPEN52 (Bitfield-Mask: 0x01)                         */
32645 #define GPIO_PINCFG52_FNCSEL52_Pos        (0UL)                     /*!< FNCSEL52 (Bit 0)                                      */
32646 #define GPIO_PINCFG52_FNCSEL52_Msk        (0xfUL)                   /*!< FNCSEL52 (Bitfield-Mask: 0x0f)                        */
32647 /* =======================================================  PINCFG53  ======================================================== */
32648 #define GPIO_PINCFG53_FOEN53_Pos          (27UL)                    /*!< FOEN53 (Bit 27)                                       */
32649 #define GPIO_PINCFG53_FOEN53_Msk          (0x8000000UL)             /*!< FOEN53 (Bitfield-Mask: 0x01)                          */
32650 #define GPIO_PINCFG53_FIEN53_Pos          (26UL)                    /*!< FIEN53 (Bit 26)                                       */
32651 #define GPIO_PINCFG53_FIEN53_Msk          (0x4000000UL)             /*!< FIEN53 (Bitfield-Mask: 0x01)                          */
32652 #define GPIO_PINCFG53_NCEPOL53_Pos        (22UL)                    /*!< NCEPOL53 (Bit 22)                                     */
32653 #define GPIO_PINCFG53_NCEPOL53_Msk        (0x400000UL)              /*!< NCEPOL53 (Bitfield-Mask: 0x01)                        */
32654 #define GPIO_PINCFG53_NCESRC53_Pos        (16UL)                    /*!< NCESRC53 (Bit 16)                                     */
32655 #define GPIO_PINCFG53_NCESRC53_Msk        (0x3f0000UL)              /*!< NCESRC53 (Bitfield-Mask: 0x3f)                        */
32656 #define GPIO_PINCFG53_PULLCFG53_Pos       (13UL)                    /*!< PULLCFG53 (Bit 13)                                    */
32657 #define GPIO_PINCFG53_PULLCFG53_Msk       (0xe000UL)                /*!< PULLCFG53 (Bitfield-Mask: 0x07)                       */
32658 #define GPIO_PINCFG53_SR53_Pos            (12UL)                    /*!< SR53 (Bit 12)                                         */
32659 #define GPIO_PINCFG53_SR53_Msk            (0x1000UL)                /*!< SR53 (Bitfield-Mask: 0x01)                            */
32660 #define GPIO_PINCFG53_DS53_Pos            (10UL)                    /*!< DS53 (Bit 10)                                         */
32661 #define GPIO_PINCFG53_DS53_Msk            (0xc00UL)                 /*!< DS53 (Bitfield-Mask: 0x03)                            */
32662 #define GPIO_PINCFG53_OUTCFG53_Pos        (8UL)                     /*!< OUTCFG53 (Bit 8)                                      */
32663 #define GPIO_PINCFG53_OUTCFG53_Msk        (0x300UL)                 /*!< OUTCFG53 (Bitfield-Mask: 0x03)                        */
32664 #define GPIO_PINCFG53_IRPTEN53_Pos        (6UL)                     /*!< IRPTEN53 (Bit 6)                                      */
32665 #define GPIO_PINCFG53_IRPTEN53_Msk        (0xc0UL)                  /*!< IRPTEN53 (Bitfield-Mask: 0x03)                        */
32666 #define GPIO_PINCFG53_RDZERO53_Pos        (5UL)                     /*!< RDZERO53 (Bit 5)                                      */
32667 #define GPIO_PINCFG53_RDZERO53_Msk        (0x20UL)                  /*!< RDZERO53 (Bitfield-Mask: 0x01)                        */
32668 #define GPIO_PINCFG53_INPEN53_Pos         (4UL)                     /*!< INPEN53 (Bit 4)                                       */
32669 #define GPIO_PINCFG53_INPEN53_Msk         (0x10UL)                  /*!< INPEN53 (Bitfield-Mask: 0x01)                         */
32670 #define GPIO_PINCFG53_FNCSEL53_Pos        (0UL)                     /*!< FNCSEL53 (Bit 0)                                      */
32671 #define GPIO_PINCFG53_FNCSEL53_Msk        (0xfUL)                   /*!< FNCSEL53 (Bitfield-Mask: 0x0f)                        */
32672 /* =======================================================  PINCFG54  ======================================================== */
32673 #define GPIO_PINCFG54_FOEN54_Pos          (27UL)                    /*!< FOEN54 (Bit 27)                                       */
32674 #define GPIO_PINCFG54_FOEN54_Msk          (0x8000000UL)             /*!< FOEN54 (Bitfield-Mask: 0x01)                          */
32675 #define GPIO_PINCFG54_FIEN54_Pos          (26UL)                    /*!< FIEN54 (Bit 26)                                       */
32676 #define GPIO_PINCFG54_FIEN54_Msk          (0x4000000UL)             /*!< FIEN54 (Bitfield-Mask: 0x01)                          */
32677 #define GPIO_PINCFG54_NCEPOL54_Pos        (22UL)                    /*!< NCEPOL54 (Bit 22)                                     */
32678 #define GPIO_PINCFG54_NCEPOL54_Msk        (0x400000UL)              /*!< NCEPOL54 (Bitfield-Mask: 0x01)                        */
32679 #define GPIO_PINCFG54_NCESRC54_Pos        (16UL)                    /*!< NCESRC54 (Bit 16)                                     */
32680 #define GPIO_PINCFG54_NCESRC54_Msk        (0x3f0000UL)              /*!< NCESRC54 (Bitfield-Mask: 0x3f)                        */
32681 #define GPIO_PINCFG54_PULLCFG54_Pos       (13UL)                    /*!< PULLCFG54 (Bit 13)                                    */
32682 #define GPIO_PINCFG54_PULLCFG54_Msk       (0xe000UL)                /*!< PULLCFG54 (Bitfield-Mask: 0x07)                       */
32683 #define GPIO_PINCFG54_SR54_Pos            (12UL)                    /*!< SR54 (Bit 12)                                         */
32684 #define GPIO_PINCFG54_SR54_Msk            (0x1000UL)                /*!< SR54 (Bitfield-Mask: 0x01)                            */
32685 #define GPIO_PINCFG54_DS54_Pos            (10UL)                    /*!< DS54 (Bit 10)                                         */
32686 #define GPIO_PINCFG54_DS54_Msk            (0xc00UL)                 /*!< DS54 (Bitfield-Mask: 0x03)                            */
32687 #define GPIO_PINCFG54_OUTCFG54_Pos        (8UL)                     /*!< OUTCFG54 (Bit 8)                                      */
32688 #define GPIO_PINCFG54_OUTCFG54_Msk        (0x300UL)                 /*!< OUTCFG54 (Bitfield-Mask: 0x03)                        */
32689 #define GPIO_PINCFG54_IRPTEN54_Pos        (6UL)                     /*!< IRPTEN54 (Bit 6)                                      */
32690 #define GPIO_PINCFG54_IRPTEN54_Msk        (0xc0UL)                  /*!< IRPTEN54 (Bitfield-Mask: 0x03)                        */
32691 #define GPIO_PINCFG54_RDZERO54_Pos        (5UL)                     /*!< RDZERO54 (Bit 5)                                      */
32692 #define GPIO_PINCFG54_RDZERO54_Msk        (0x20UL)                  /*!< RDZERO54 (Bitfield-Mask: 0x01)                        */
32693 #define GPIO_PINCFG54_INPEN54_Pos         (4UL)                     /*!< INPEN54 (Bit 4)                                       */
32694 #define GPIO_PINCFG54_INPEN54_Msk         (0x10UL)                  /*!< INPEN54 (Bitfield-Mask: 0x01)                         */
32695 #define GPIO_PINCFG54_FNCSEL54_Pos        (0UL)                     /*!< FNCSEL54 (Bit 0)                                      */
32696 #define GPIO_PINCFG54_FNCSEL54_Msk        (0xfUL)                   /*!< FNCSEL54 (Bitfield-Mask: 0x0f)                        */
32697 /* =======================================================  PINCFG55  ======================================================== */
32698 #define GPIO_PINCFG55_FOEN55_Pos          (27UL)                    /*!< FOEN55 (Bit 27)                                       */
32699 #define GPIO_PINCFG55_FOEN55_Msk          (0x8000000UL)             /*!< FOEN55 (Bitfield-Mask: 0x01)                          */
32700 #define GPIO_PINCFG55_FIEN55_Pos          (26UL)                    /*!< FIEN55 (Bit 26)                                       */
32701 #define GPIO_PINCFG55_FIEN55_Msk          (0x4000000UL)             /*!< FIEN55 (Bitfield-Mask: 0x01)                          */
32702 #define GPIO_PINCFG55_NCEPOL55_Pos        (22UL)                    /*!< NCEPOL55 (Bit 22)                                     */
32703 #define GPIO_PINCFG55_NCEPOL55_Msk        (0x400000UL)              /*!< NCEPOL55 (Bitfield-Mask: 0x01)                        */
32704 #define GPIO_PINCFG55_NCESRC55_Pos        (16UL)                    /*!< NCESRC55 (Bit 16)                                     */
32705 #define GPIO_PINCFG55_NCESRC55_Msk        (0x3f0000UL)              /*!< NCESRC55 (Bitfield-Mask: 0x3f)                        */
32706 #define GPIO_PINCFG55_PULLCFG55_Pos       (13UL)                    /*!< PULLCFG55 (Bit 13)                                    */
32707 #define GPIO_PINCFG55_PULLCFG55_Msk       (0xe000UL)                /*!< PULLCFG55 (Bitfield-Mask: 0x07)                       */
32708 #define GPIO_PINCFG55_SR55_Pos            (12UL)                    /*!< SR55 (Bit 12)                                         */
32709 #define GPIO_PINCFG55_SR55_Msk            (0x1000UL)                /*!< SR55 (Bitfield-Mask: 0x01)                            */
32710 #define GPIO_PINCFG55_DS55_Pos            (10UL)                    /*!< DS55 (Bit 10)                                         */
32711 #define GPIO_PINCFG55_DS55_Msk            (0xc00UL)                 /*!< DS55 (Bitfield-Mask: 0x03)                            */
32712 #define GPIO_PINCFG55_OUTCFG55_Pos        (8UL)                     /*!< OUTCFG55 (Bit 8)                                      */
32713 #define GPIO_PINCFG55_OUTCFG55_Msk        (0x300UL)                 /*!< OUTCFG55 (Bitfield-Mask: 0x03)                        */
32714 #define GPIO_PINCFG55_IRPTEN55_Pos        (6UL)                     /*!< IRPTEN55 (Bit 6)                                      */
32715 #define GPIO_PINCFG55_IRPTEN55_Msk        (0xc0UL)                  /*!< IRPTEN55 (Bitfield-Mask: 0x03)                        */
32716 #define GPIO_PINCFG55_RDZERO55_Pos        (5UL)                     /*!< RDZERO55 (Bit 5)                                      */
32717 #define GPIO_PINCFG55_RDZERO55_Msk        (0x20UL)                  /*!< RDZERO55 (Bitfield-Mask: 0x01)                        */
32718 #define GPIO_PINCFG55_INPEN55_Pos         (4UL)                     /*!< INPEN55 (Bit 4)                                       */
32719 #define GPIO_PINCFG55_INPEN55_Msk         (0x10UL)                  /*!< INPEN55 (Bitfield-Mask: 0x01)                         */
32720 #define GPIO_PINCFG55_FNCSEL55_Pos        (0UL)                     /*!< FNCSEL55 (Bit 0)                                      */
32721 #define GPIO_PINCFG55_FNCSEL55_Msk        (0xfUL)                   /*!< FNCSEL55 (Bitfield-Mask: 0x0f)                        */
32722 /* =======================================================  PINCFG56  ======================================================== */
32723 #define GPIO_PINCFG56_FOEN56_Pos          (27UL)                    /*!< FOEN56 (Bit 27)                                       */
32724 #define GPIO_PINCFG56_FOEN56_Msk          (0x8000000UL)             /*!< FOEN56 (Bitfield-Mask: 0x01)                          */
32725 #define GPIO_PINCFG56_FIEN56_Pos          (26UL)                    /*!< FIEN56 (Bit 26)                                       */
32726 #define GPIO_PINCFG56_FIEN56_Msk          (0x4000000UL)             /*!< FIEN56 (Bitfield-Mask: 0x01)                          */
32727 #define GPIO_PINCFG56_NCEPOL56_Pos        (22UL)                    /*!< NCEPOL56 (Bit 22)                                     */
32728 #define GPIO_PINCFG56_NCEPOL56_Msk        (0x400000UL)              /*!< NCEPOL56 (Bitfield-Mask: 0x01)                        */
32729 #define GPIO_PINCFG56_NCESRC56_Pos        (16UL)                    /*!< NCESRC56 (Bit 16)                                     */
32730 #define GPIO_PINCFG56_NCESRC56_Msk        (0x3f0000UL)              /*!< NCESRC56 (Bitfield-Mask: 0x3f)                        */
32731 #define GPIO_PINCFG56_PULLCFG56_Pos       (13UL)                    /*!< PULLCFG56 (Bit 13)                                    */
32732 #define GPIO_PINCFG56_PULLCFG56_Msk       (0xe000UL)                /*!< PULLCFG56 (Bitfield-Mask: 0x07)                       */
32733 #define GPIO_PINCFG56_SR56_Pos            (12UL)                    /*!< SR56 (Bit 12)                                         */
32734 #define GPIO_PINCFG56_SR56_Msk            (0x1000UL)                /*!< SR56 (Bitfield-Mask: 0x01)                            */
32735 #define GPIO_PINCFG56_DS56_Pos            (10UL)                    /*!< DS56 (Bit 10)                                         */
32736 #define GPIO_PINCFG56_DS56_Msk            (0xc00UL)                 /*!< DS56 (Bitfield-Mask: 0x03)                            */
32737 #define GPIO_PINCFG56_OUTCFG56_Pos        (8UL)                     /*!< OUTCFG56 (Bit 8)                                      */
32738 #define GPIO_PINCFG56_OUTCFG56_Msk        (0x300UL)                 /*!< OUTCFG56 (Bitfield-Mask: 0x03)                        */
32739 #define GPIO_PINCFG56_IRPTEN56_Pos        (6UL)                     /*!< IRPTEN56 (Bit 6)                                      */
32740 #define GPIO_PINCFG56_IRPTEN56_Msk        (0xc0UL)                  /*!< IRPTEN56 (Bitfield-Mask: 0x03)                        */
32741 #define GPIO_PINCFG56_RDZERO56_Pos        (5UL)                     /*!< RDZERO56 (Bit 5)                                      */
32742 #define GPIO_PINCFG56_RDZERO56_Msk        (0x20UL)                  /*!< RDZERO56 (Bitfield-Mask: 0x01)                        */
32743 #define GPIO_PINCFG56_INPEN56_Pos         (4UL)                     /*!< INPEN56 (Bit 4)                                       */
32744 #define GPIO_PINCFG56_INPEN56_Msk         (0x10UL)                  /*!< INPEN56 (Bitfield-Mask: 0x01)                         */
32745 #define GPIO_PINCFG56_FNCSEL56_Pos        (0UL)                     /*!< FNCSEL56 (Bit 0)                                      */
32746 #define GPIO_PINCFG56_FNCSEL56_Msk        (0xfUL)                   /*!< FNCSEL56 (Bitfield-Mask: 0x0f)                        */
32747 /* =======================================================  PINCFG57  ======================================================== */
32748 #define GPIO_PINCFG57_FOEN57_Pos          (27UL)                    /*!< FOEN57 (Bit 27)                                       */
32749 #define GPIO_PINCFG57_FOEN57_Msk          (0x8000000UL)             /*!< FOEN57 (Bitfield-Mask: 0x01)                          */
32750 #define GPIO_PINCFG57_FIEN57_Pos          (26UL)                    /*!< FIEN57 (Bit 26)                                       */
32751 #define GPIO_PINCFG57_FIEN57_Msk          (0x4000000UL)             /*!< FIEN57 (Bitfield-Mask: 0x01)                          */
32752 #define GPIO_PINCFG57_NCEPOL57_Pos        (22UL)                    /*!< NCEPOL57 (Bit 22)                                     */
32753 #define GPIO_PINCFG57_NCEPOL57_Msk        (0x400000UL)              /*!< NCEPOL57 (Bitfield-Mask: 0x01)                        */
32754 #define GPIO_PINCFG57_NCESRC57_Pos        (16UL)                    /*!< NCESRC57 (Bit 16)                                     */
32755 #define GPIO_PINCFG57_NCESRC57_Msk        (0x3f0000UL)              /*!< NCESRC57 (Bitfield-Mask: 0x3f)                        */
32756 #define GPIO_PINCFG57_PULLCFG57_Pos       (13UL)                    /*!< PULLCFG57 (Bit 13)                                    */
32757 #define GPIO_PINCFG57_PULLCFG57_Msk       (0xe000UL)                /*!< PULLCFG57 (Bitfield-Mask: 0x07)                       */
32758 #define GPIO_PINCFG57_SR57_Pos            (12UL)                    /*!< SR57 (Bit 12)                                         */
32759 #define GPIO_PINCFG57_SR57_Msk            (0x1000UL)                /*!< SR57 (Bitfield-Mask: 0x01)                            */
32760 #define GPIO_PINCFG57_DS57_Pos            (10UL)                    /*!< DS57 (Bit 10)                                         */
32761 #define GPIO_PINCFG57_DS57_Msk            (0xc00UL)                 /*!< DS57 (Bitfield-Mask: 0x03)                            */
32762 #define GPIO_PINCFG57_OUTCFG57_Pos        (8UL)                     /*!< OUTCFG57 (Bit 8)                                      */
32763 #define GPIO_PINCFG57_OUTCFG57_Msk        (0x300UL)                 /*!< OUTCFG57 (Bitfield-Mask: 0x03)                        */
32764 #define GPIO_PINCFG57_IRPTEN57_Pos        (6UL)                     /*!< IRPTEN57 (Bit 6)                                      */
32765 #define GPIO_PINCFG57_IRPTEN57_Msk        (0xc0UL)                  /*!< IRPTEN57 (Bitfield-Mask: 0x03)                        */
32766 #define GPIO_PINCFG57_RDZERO57_Pos        (5UL)                     /*!< RDZERO57 (Bit 5)                                      */
32767 #define GPIO_PINCFG57_RDZERO57_Msk        (0x20UL)                  /*!< RDZERO57 (Bitfield-Mask: 0x01)                        */
32768 #define GPIO_PINCFG57_INPEN57_Pos         (4UL)                     /*!< INPEN57 (Bit 4)                                       */
32769 #define GPIO_PINCFG57_INPEN57_Msk         (0x10UL)                  /*!< INPEN57 (Bitfield-Mask: 0x01)                         */
32770 #define GPIO_PINCFG57_FNCSEL57_Pos        (0UL)                     /*!< FNCSEL57 (Bit 0)                                      */
32771 #define GPIO_PINCFG57_FNCSEL57_Msk        (0xfUL)                   /*!< FNCSEL57 (Bitfield-Mask: 0x0f)                        */
32772 /* =======================================================  PINCFG58  ======================================================== */
32773 #define GPIO_PINCFG58_FOEN58_Pos          (27UL)                    /*!< FOEN58 (Bit 27)                                       */
32774 #define GPIO_PINCFG58_FOEN58_Msk          (0x8000000UL)             /*!< FOEN58 (Bitfield-Mask: 0x01)                          */
32775 #define GPIO_PINCFG58_FIEN58_Pos          (26UL)                    /*!< FIEN58 (Bit 26)                                       */
32776 #define GPIO_PINCFG58_FIEN58_Msk          (0x4000000UL)             /*!< FIEN58 (Bitfield-Mask: 0x01)                          */
32777 #define GPIO_PINCFG58_NCEPOL58_Pos        (22UL)                    /*!< NCEPOL58 (Bit 22)                                     */
32778 #define GPIO_PINCFG58_NCEPOL58_Msk        (0x400000UL)              /*!< NCEPOL58 (Bitfield-Mask: 0x01)                        */
32779 #define GPIO_PINCFG58_NCESRC58_Pos        (16UL)                    /*!< NCESRC58 (Bit 16)                                     */
32780 #define GPIO_PINCFG58_NCESRC58_Msk        (0x3f0000UL)              /*!< NCESRC58 (Bitfield-Mask: 0x3f)                        */
32781 #define GPIO_PINCFG58_PULLCFG58_Pos       (13UL)                    /*!< PULLCFG58 (Bit 13)                                    */
32782 #define GPIO_PINCFG58_PULLCFG58_Msk       (0xe000UL)                /*!< PULLCFG58 (Bitfield-Mask: 0x07)                       */
32783 #define GPIO_PINCFG58_SR58_Pos            (12UL)                    /*!< SR58 (Bit 12)                                         */
32784 #define GPIO_PINCFG58_SR58_Msk            (0x1000UL)                /*!< SR58 (Bitfield-Mask: 0x01)                            */
32785 #define GPIO_PINCFG58_DS58_Pos            (10UL)                    /*!< DS58 (Bit 10)                                         */
32786 #define GPIO_PINCFG58_DS58_Msk            (0xc00UL)                 /*!< DS58 (Bitfield-Mask: 0x03)                            */
32787 #define GPIO_PINCFG58_OUTCFG58_Pos        (8UL)                     /*!< OUTCFG58 (Bit 8)                                      */
32788 #define GPIO_PINCFG58_OUTCFG58_Msk        (0x300UL)                 /*!< OUTCFG58 (Bitfield-Mask: 0x03)                        */
32789 #define GPIO_PINCFG58_IRPTEN58_Pos        (6UL)                     /*!< IRPTEN58 (Bit 6)                                      */
32790 #define GPIO_PINCFG58_IRPTEN58_Msk        (0xc0UL)                  /*!< IRPTEN58 (Bitfield-Mask: 0x03)                        */
32791 #define GPIO_PINCFG58_RDZERO58_Pos        (5UL)                     /*!< RDZERO58 (Bit 5)                                      */
32792 #define GPIO_PINCFG58_RDZERO58_Msk        (0x20UL)                  /*!< RDZERO58 (Bitfield-Mask: 0x01)                        */
32793 #define GPIO_PINCFG58_INPEN58_Pos         (4UL)                     /*!< INPEN58 (Bit 4)                                       */
32794 #define GPIO_PINCFG58_INPEN58_Msk         (0x10UL)                  /*!< INPEN58 (Bitfield-Mask: 0x01)                         */
32795 #define GPIO_PINCFG58_FNCSEL58_Pos        (0UL)                     /*!< FNCSEL58 (Bit 0)                                      */
32796 #define GPIO_PINCFG58_FNCSEL58_Msk        (0xfUL)                   /*!< FNCSEL58 (Bitfield-Mask: 0x0f)                        */
32797 /* =======================================================  PINCFG59  ======================================================== */
32798 #define GPIO_PINCFG59_FOEN59_Pos          (27UL)                    /*!< FOEN59 (Bit 27)                                       */
32799 #define GPIO_PINCFG59_FOEN59_Msk          (0x8000000UL)             /*!< FOEN59 (Bitfield-Mask: 0x01)                          */
32800 #define GPIO_PINCFG59_FIEN59_Pos          (26UL)                    /*!< FIEN59 (Bit 26)                                       */
32801 #define GPIO_PINCFG59_FIEN59_Msk          (0x4000000UL)             /*!< FIEN59 (Bitfield-Mask: 0x01)                          */
32802 #define GPIO_PINCFG59_NCEPOL59_Pos        (22UL)                    /*!< NCEPOL59 (Bit 22)                                     */
32803 #define GPIO_PINCFG59_NCEPOL59_Msk        (0x400000UL)              /*!< NCEPOL59 (Bitfield-Mask: 0x01)                        */
32804 #define GPIO_PINCFG59_NCESRC59_Pos        (16UL)                    /*!< NCESRC59 (Bit 16)                                     */
32805 #define GPIO_PINCFG59_NCESRC59_Msk        (0x3f0000UL)              /*!< NCESRC59 (Bitfield-Mask: 0x3f)                        */
32806 #define GPIO_PINCFG59_PULLCFG59_Pos       (13UL)                    /*!< PULLCFG59 (Bit 13)                                    */
32807 #define GPIO_PINCFG59_PULLCFG59_Msk       (0xe000UL)                /*!< PULLCFG59 (Bitfield-Mask: 0x07)                       */
32808 #define GPIO_PINCFG59_SR59_Pos            (12UL)                    /*!< SR59 (Bit 12)                                         */
32809 #define GPIO_PINCFG59_SR59_Msk            (0x1000UL)                /*!< SR59 (Bitfield-Mask: 0x01)                            */
32810 #define GPIO_PINCFG59_DS59_Pos            (10UL)                    /*!< DS59 (Bit 10)                                         */
32811 #define GPIO_PINCFG59_DS59_Msk            (0xc00UL)                 /*!< DS59 (Bitfield-Mask: 0x03)                            */
32812 #define GPIO_PINCFG59_OUTCFG59_Pos        (8UL)                     /*!< OUTCFG59 (Bit 8)                                      */
32813 #define GPIO_PINCFG59_OUTCFG59_Msk        (0x300UL)                 /*!< OUTCFG59 (Bitfield-Mask: 0x03)                        */
32814 #define GPIO_PINCFG59_IRPTEN59_Pos        (6UL)                     /*!< IRPTEN59 (Bit 6)                                      */
32815 #define GPIO_PINCFG59_IRPTEN59_Msk        (0xc0UL)                  /*!< IRPTEN59 (Bitfield-Mask: 0x03)                        */
32816 #define GPIO_PINCFG59_RDZERO59_Pos        (5UL)                     /*!< RDZERO59 (Bit 5)                                      */
32817 #define GPIO_PINCFG59_RDZERO59_Msk        (0x20UL)                  /*!< RDZERO59 (Bitfield-Mask: 0x01)                        */
32818 #define GPIO_PINCFG59_INPEN59_Pos         (4UL)                     /*!< INPEN59 (Bit 4)                                       */
32819 #define GPIO_PINCFG59_INPEN59_Msk         (0x10UL)                  /*!< INPEN59 (Bitfield-Mask: 0x01)                         */
32820 #define GPIO_PINCFG59_FNCSEL59_Pos        (0UL)                     /*!< FNCSEL59 (Bit 0)                                      */
32821 #define GPIO_PINCFG59_FNCSEL59_Msk        (0xfUL)                   /*!< FNCSEL59 (Bitfield-Mask: 0x0f)                        */
32822 /* =======================================================  PINCFG60  ======================================================== */
32823 #define GPIO_PINCFG60_FOEN60_Pos          (27UL)                    /*!< FOEN60 (Bit 27)                                       */
32824 #define GPIO_PINCFG60_FOEN60_Msk          (0x8000000UL)             /*!< FOEN60 (Bitfield-Mask: 0x01)                          */
32825 #define GPIO_PINCFG60_FIEN60_Pos          (26UL)                    /*!< FIEN60 (Bit 26)                                       */
32826 #define GPIO_PINCFG60_FIEN60_Msk          (0x4000000UL)             /*!< FIEN60 (Bitfield-Mask: 0x01)                          */
32827 #define GPIO_PINCFG60_NCEPOL60_Pos        (22UL)                    /*!< NCEPOL60 (Bit 22)                                     */
32828 #define GPIO_PINCFG60_NCEPOL60_Msk        (0x400000UL)              /*!< NCEPOL60 (Bitfield-Mask: 0x01)                        */
32829 #define GPIO_PINCFG60_NCESRC60_Pos        (16UL)                    /*!< NCESRC60 (Bit 16)                                     */
32830 #define GPIO_PINCFG60_NCESRC60_Msk        (0x3f0000UL)              /*!< NCESRC60 (Bitfield-Mask: 0x3f)                        */
32831 #define GPIO_PINCFG60_PULLCFG60_Pos       (13UL)                    /*!< PULLCFG60 (Bit 13)                                    */
32832 #define GPIO_PINCFG60_PULLCFG60_Msk       (0xe000UL)                /*!< PULLCFG60 (Bitfield-Mask: 0x07)                       */
32833 #define GPIO_PINCFG60_SR60_Pos            (12UL)                    /*!< SR60 (Bit 12)                                         */
32834 #define GPIO_PINCFG60_SR60_Msk            (0x1000UL)                /*!< SR60 (Bitfield-Mask: 0x01)                            */
32835 #define GPIO_PINCFG60_DS60_Pos            (10UL)                    /*!< DS60 (Bit 10)                                         */
32836 #define GPIO_PINCFG60_DS60_Msk            (0xc00UL)                 /*!< DS60 (Bitfield-Mask: 0x03)                            */
32837 #define GPIO_PINCFG60_OUTCFG60_Pos        (8UL)                     /*!< OUTCFG60 (Bit 8)                                      */
32838 #define GPIO_PINCFG60_OUTCFG60_Msk        (0x300UL)                 /*!< OUTCFG60 (Bitfield-Mask: 0x03)                        */
32839 #define GPIO_PINCFG60_IRPTEN60_Pos        (6UL)                     /*!< IRPTEN60 (Bit 6)                                      */
32840 #define GPIO_PINCFG60_IRPTEN60_Msk        (0xc0UL)                  /*!< IRPTEN60 (Bitfield-Mask: 0x03)                        */
32841 #define GPIO_PINCFG60_RDZERO60_Pos        (5UL)                     /*!< RDZERO60 (Bit 5)                                      */
32842 #define GPIO_PINCFG60_RDZERO60_Msk        (0x20UL)                  /*!< RDZERO60 (Bitfield-Mask: 0x01)                        */
32843 #define GPIO_PINCFG60_INPEN60_Pos         (4UL)                     /*!< INPEN60 (Bit 4)                                       */
32844 #define GPIO_PINCFG60_INPEN60_Msk         (0x10UL)                  /*!< INPEN60 (Bitfield-Mask: 0x01)                         */
32845 #define GPIO_PINCFG60_FNCSEL60_Pos        (0UL)                     /*!< FNCSEL60 (Bit 0)                                      */
32846 #define GPIO_PINCFG60_FNCSEL60_Msk        (0xfUL)                   /*!< FNCSEL60 (Bitfield-Mask: 0x0f)                        */
32847 /* =======================================================  PINCFG61  ======================================================== */
32848 #define GPIO_PINCFG61_FOEN61_Pos          (27UL)                    /*!< FOEN61 (Bit 27)                                       */
32849 #define GPIO_PINCFG61_FOEN61_Msk          (0x8000000UL)             /*!< FOEN61 (Bitfield-Mask: 0x01)                          */
32850 #define GPIO_PINCFG61_FIEN61_Pos          (26UL)                    /*!< FIEN61 (Bit 26)                                       */
32851 #define GPIO_PINCFG61_FIEN61_Msk          (0x4000000UL)             /*!< FIEN61 (Bitfield-Mask: 0x01)                          */
32852 #define GPIO_PINCFG61_NCEPOL61_Pos        (22UL)                    /*!< NCEPOL61 (Bit 22)                                     */
32853 #define GPIO_PINCFG61_NCEPOL61_Msk        (0x400000UL)              /*!< NCEPOL61 (Bitfield-Mask: 0x01)                        */
32854 #define GPIO_PINCFG61_NCESRC61_Pos        (16UL)                    /*!< NCESRC61 (Bit 16)                                     */
32855 #define GPIO_PINCFG61_NCESRC61_Msk        (0x3f0000UL)              /*!< NCESRC61 (Bitfield-Mask: 0x3f)                        */
32856 #define GPIO_PINCFG61_PULLCFG61_Pos       (13UL)                    /*!< PULLCFG61 (Bit 13)                                    */
32857 #define GPIO_PINCFG61_PULLCFG61_Msk       (0xe000UL)                /*!< PULLCFG61 (Bitfield-Mask: 0x07)                       */
32858 #define GPIO_PINCFG61_SR61_Pos            (12UL)                    /*!< SR61 (Bit 12)                                         */
32859 #define GPIO_PINCFG61_SR61_Msk            (0x1000UL)                /*!< SR61 (Bitfield-Mask: 0x01)                            */
32860 #define GPIO_PINCFG61_DS61_Pos            (10UL)                    /*!< DS61 (Bit 10)                                         */
32861 #define GPIO_PINCFG61_DS61_Msk            (0xc00UL)                 /*!< DS61 (Bitfield-Mask: 0x03)                            */
32862 #define GPIO_PINCFG61_OUTCFG61_Pos        (8UL)                     /*!< OUTCFG61 (Bit 8)                                      */
32863 #define GPIO_PINCFG61_OUTCFG61_Msk        (0x300UL)                 /*!< OUTCFG61 (Bitfield-Mask: 0x03)                        */
32864 #define GPIO_PINCFG61_IRPTEN61_Pos        (6UL)                     /*!< IRPTEN61 (Bit 6)                                      */
32865 #define GPIO_PINCFG61_IRPTEN61_Msk        (0xc0UL)                  /*!< IRPTEN61 (Bitfield-Mask: 0x03)                        */
32866 #define GPIO_PINCFG61_RDZERO61_Pos        (5UL)                     /*!< RDZERO61 (Bit 5)                                      */
32867 #define GPIO_PINCFG61_RDZERO61_Msk        (0x20UL)                  /*!< RDZERO61 (Bitfield-Mask: 0x01)                        */
32868 #define GPIO_PINCFG61_INPEN61_Pos         (4UL)                     /*!< INPEN61 (Bit 4)                                       */
32869 #define GPIO_PINCFG61_INPEN61_Msk         (0x10UL)                  /*!< INPEN61 (Bitfield-Mask: 0x01)                         */
32870 #define GPIO_PINCFG61_FNCSEL61_Pos        (0UL)                     /*!< FNCSEL61 (Bit 0)                                      */
32871 #define GPIO_PINCFG61_FNCSEL61_Msk        (0xfUL)                   /*!< FNCSEL61 (Bitfield-Mask: 0x0f)                        */
32872 /* =======================================================  PINCFG62  ======================================================== */
32873 #define GPIO_PINCFG62_FOEN62_Pos          (27UL)                    /*!< FOEN62 (Bit 27)                                       */
32874 #define GPIO_PINCFG62_FOEN62_Msk          (0x8000000UL)             /*!< FOEN62 (Bitfield-Mask: 0x01)                          */
32875 #define GPIO_PINCFG62_FIEN62_Pos          (26UL)                    /*!< FIEN62 (Bit 26)                                       */
32876 #define GPIO_PINCFG62_FIEN62_Msk          (0x4000000UL)             /*!< FIEN62 (Bitfield-Mask: 0x01)                          */
32877 #define GPIO_PINCFG62_NCEPOL62_Pos        (22UL)                    /*!< NCEPOL62 (Bit 22)                                     */
32878 #define GPIO_PINCFG62_NCEPOL62_Msk        (0x400000UL)              /*!< NCEPOL62 (Bitfield-Mask: 0x01)                        */
32879 #define GPIO_PINCFG62_NCESRC62_Pos        (16UL)                    /*!< NCESRC62 (Bit 16)                                     */
32880 #define GPIO_PINCFG62_NCESRC62_Msk        (0x3f0000UL)              /*!< NCESRC62 (Bitfield-Mask: 0x3f)                        */
32881 #define GPIO_PINCFG62_PULLCFG62_Pos       (13UL)                    /*!< PULLCFG62 (Bit 13)                                    */
32882 #define GPIO_PINCFG62_PULLCFG62_Msk       (0xe000UL)                /*!< PULLCFG62 (Bitfield-Mask: 0x07)                       */
32883 #define GPIO_PINCFG62_SR62_Pos            (12UL)                    /*!< SR62 (Bit 12)                                         */
32884 #define GPIO_PINCFG62_SR62_Msk            (0x1000UL)                /*!< SR62 (Bitfield-Mask: 0x01)                            */
32885 #define GPIO_PINCFG62_DS62_Pos            (10UL)                    /*!< DS62 (Bit 10)                                         */
32886 #define GPIO_PINCFG62_DS62_Msk            (0xc00UL)                 /*!< DS62 (Bitfield-Mask: 0x03)                            */
32887 #define GPIO_PINCFG62_OUTCFG62_Pos        (8UL)                     /*!< OUTCFG62 (Bit 8)                                      */
32888 #define GPIO_PINCFG62_OUTCFG62_Msk        (0x300UL)                 /*!< OUTCFG62 (Bitfield-Mask: 0x03)                        */
32889 #define GPIO_PINCFG62_IRPTEN62_Pos        (6UL)                     /*!< IRPTEN62 (Bit 6)                                      */
32890 #define GPIO_PINCFG62_IRPTEN62_Msk        (0xc0UL)                  /*!< IRPTEN62 (Bitfield-Mask: 0x03)                        */
32891 #define GPIO_PINCFG62_RDZERO62_Pos        (5UL)                     /*!< RDZERO62 (Bit 5)                                      */
32892 #define GPIO_PINCFG62_RDZERO62_Msk        (0x20UL)                  /*!< RDZERO62 (Bitfield-Mask: 0x01)                        */
32893 #define GPIO_PINCFG62_INPEN62_Pos         (4UL)                     /*!< INPEN62 (Bit 4)                                       */
32894 #define GPIO_PINCFG62_INPEN62_Msk         (0x10UL)                  /*!< INPEN62 (Bitfield-Mask: 0x01)                         */
32895 #define GPIO_PINCFG62_FNCSEL62_Pos        (0UL)                     /*!< FNCSEL62 (Bit 0)                                      */
32896 #define GPIO_PINCFG62_FNCSEL62_Msk        (0xfUL)                   /*!< FNCSEL62 (Bitfield-Mask: 0x0f)                        */
32897 /* =======================================================  PINCFG63  ======================================================== */
32898 #define GPIO_PINCFG63_FOEN63_Pos          (27UL)                    /*!< FOEN63 (Bit 27)                                       */
32899 #define GPIO_PINCFG63_FOEN63_Msk          (0x8000000UL)             /*!< FOEN63 (Bitfield-Mask: 0x01)                          */
32900 #define GPIO_PINCFG63_FIEN63_Pos          (26UL)                    /*!< FIEN63 (Bit 26)                                       */
32901 #define GPIO_PINCFG63_FIEN63_Msk          (0x4000000UL)             /*!< FIEN63 (Bitfield-Mask: 0x01)                          */
32902 #define GPIO_PINCFG63_NCEPOL63_Pos        (22UL)                    /*!< NCEPOL63 (Bit 22)                                     */
32903 #define GPIO_PINCFG63_NCEPOL63_Msk        (0x400000UL)              /*!< NCEPOL63 (Bitfield-Mask: 0x01)                        */
32904 #define GPIO_PINCFG63_NCESRC63_Pos        (16UL)                    /*!< NCESRC63 (Bit 16)                                     */
32905 #define GPIO_PINCFG63_NCESRC63_Msk        (0x3f0000UL)              /*!< NCESRC63 (Bitfield-Mask: 0x3f)                        */
32906 #define GPIO_PINCFG63_PULLCFG63_Pos       (13UL)                    /*!< PULLCFG63 (Bit 13)                                    */
32907 #define GPIO_PINCFG63_PULLCFG63_Msk       (0xe000UL)                /*!< PULLCFG63 (Bitfield-Mask: 0x07)                       */
32908 #define GPIO_PINCFG63_SR63_Pos            (12UL)                    /*!< SR63 (Bit 12)                                         */
32909 #define GPIO_PINCFG63_SR63_Msk            (0x1000UL)                /*!< SR63 (Bitfield-Mask: 0x01)                            */
32910 #define GPIO_PINCFG63_DS63_Pos            (10UL)                    /*!< DS63 (Bit 10)                                         */
32911 #define GPIO_PINCFG63_DS63_Msk            (0xc00UL)                 /*!< DS63 (Bitfield-Mask: 0x03)                            */
32912 #define GPIO_PINCFG63_OUTCFG63_Pos        (8UL)                     /*!< OUTCFG63 (Bit 8)                                      */
32913 #define GPIO_PINCFG63_OUTCFG63_Msk        (0x300UL)                 /*!< OUTCFG63 (Bitfield-Mask: 0x03)                        */
32914 #define GPIO_PINCFG63_IRPTEN63_Pos        (6UL)                     /*!< IRPTEN63 (Bit 6)                                      */
32915 #define GPIO_PINCFG63_IRPTEN63_Msk        (0xc0UL)                  /*!< IRPTEN63 (Bitfield-Mask: 0x03)                        */
32916 #define GPIO_PINCFG63_RDZERO63_Pos        (5UL)                     /*!< RDZERO63 (Bit 5)                                      */
32917 #define GPIO_PINCFG63_RDZERO63_Msk        (0x20UL)                  /*!< RDZERO63 (Bitfield-Mask: 0x01)                        */
32918 #define GPIO_PINCFG63_INPEN63_Pos         (4UL)                     /*!< INPEN63 (Bit 4)                                       */
32919 #define GPIO_PINCFG63_INPEN63_Msk         (0x10UL)                  /*!< INPEN63 (Bitfield-Mask: 0x01)                         */
32920 #define GPIO_PINCFG63_FNCSEL63_Pos        (0UL)                     /*!< FNCSEL63 (Bit 0)                                      */
32921 #define GPIO_PINCFG63_FNCSEL63_Msk        (0xfUL)                   /*!< FNCSEL63 (Bitfield-Mask: 0x0f)                        */
32922 /* =======================================================  PINCFG64  ======================================================== */
32923 #define GPIO_PINCFG64_FOEN64_Pos          (27UL)                    /*!< FOEN64 (Bit 27)                                       */
32924 #define GPIO_PINCFG64_FOEN64_Msk          (0x8000000UL)             /*!< FOEN64 (Bitfield-Mask: 0x01)                          */
32925 #define GPIO_PINCFG64_FIEN64_Pos          (26UL)                    /*!< FIEN64 (Bit 26)                                       */
32926 #define GPIO_PINCFG64_FIEN64_Msk          (0x4000000UL)             /*!< FIEN64 (Bitfield-Mask: 0x01)                          */
32927 #define GPIO_PINCFG64_NCEPOL64_Pos        (22UL)                    /*!< NCEPOL64 (Bit 22)                                     */
32928 #define GPIO_PINCFG64_NCEPOL64_Msk        (0x400000UL)              /*!< NCEPOL64 (Bitfield-Mask: 0x01)                        */
32929 #define GPIO_PINCFG64_NCESRC64_Pos        (16UL)                    /*!< NCESRC64 (Bit 16)                                     */
32930 #define GPIO_PINCFG64_NCESRC64_Msk        (0x3f0000UL)              /*!< NCESRC64 (Bitfield-Mask: 0x3f)                        */
32931 #define GPIO_PINCFG64_PULLCFG64_Pos       (13UL)                    /*!< PULLCFG64 (Bit 13)                                    */
32932 #define GPIO_PINCFG64_PULLCFG64_Msk       (0xe000UL)                /*!< PULLCFG64 (Bitfield-Mask: 0x07)                       */
32933 #define GPIO_PINCFG64_SR64_Pos            (12UL)                    /*!< SR64 (Bit 12)                                         */
32934 #define GPIO_PINCFG64_SR64_Msk            (0x1000UL)                /*!< SR64 (Bitfield-Mask: 0x01)                            */
32935 #define GPIO_PINCFG64_DS64_Pos            (10UL)                    /*!< DS64 (Bit 10)                                         */
32936 #define GPIO_PINCFG64_DS64_Msk            (0xc00UL)                 /*!< DS64 (Bitfield-Mask: 0x03)                            */
32937 #define GPIO_PINCFG64_OUTCFG64_Pos        (8UL)                     /*!< OUTCFG64 (Bit 8)                                      */
32938 #define GPIO_PINCFG64_OUTCFG64_Msk        (0x300UL)                 /*!< OUTCFG64 (Bitfield-Mask: 0x03)                        */
32939 #define GPIO_PINCFG64_IRPTEN64_Pos        (6UL)                     /*!< IRPTEN64 (Bit 6)                                      */
32940 #define GPIO_PINCFG64_IRPTEN64_Msk        (0xc0UL)                  /*!< IRPTEN64 (Bitfield-Mask: 0x03)                        */
32941 #define GPIO_PINCFG64_RDZERO64_Pos        (5UL)                     /*!< RDZERO64 (Bit 5)                                      */
32942 #define GPIO_PINCFG64_RDZERO64_Msk        (0x20UL)                  /*!< RDZERO64 (Bitfield-Mask: 0x01)                        */
32943 #define GPIO_PINCFG64_INPEN64_Pos         (4UL)                     /*!< INPEN64 (Bit 4)                                       */
32944 #define GPIO_PINCFG64_INPEN64_Msk         (0x10UL)                  /*!< INPEN64 (Bitfield-Mask: 0x01)                         */
32945 #define GPIO_PINCFG64_FNCSEL64_Pos        (0UL)                     /*!< FNCSEL64 (Bit 0)                                      */
32946 #define GPIO_PINCFG64_FNCSEL64_Msk        (0xfUL)                   /*!< FNCSEL64 (Bitfield-Mask: 0x0f)                        */
32947 /* =======================================================  PINCFG65  ======================================================== */
32948 #define GPIO_PINCFG65_FOEN65_Pos          (27UL)                    /*!< FOEN65 (Bit 27)                                       */
32949 #define GPIO_PINCFG65_FOEN65_Msk          (0x8000000UL)             /*!< FOEN65 (Bitfield-Mask: 0x01)                          */
32950 #define GPIO_PINCFG65_FIEN65_Pos          (26UL)                    /*!< FIEN65 (Bit 26)                                       */
32951 #define GPIO_PINCFG65_FIEN65_Msk          (0x4000000UL)             /*!< FIEN65 (Bitfield-Mask: 0x01)                          */
32952 #define GPIO_PINCFG65_NCEPOL65_Pos        (22UL)                    /*!< NCEPOL65 (Bit 22)                                     */
32953 #define GPIO_PINCFG65_NCEPOL65_Msk        (0x400000UL)              /*!< NCEPOL65 (Bitfield-Mask: 0x01)                        */
32954 #define GPIO_PINCFG65_NCESRC65_Pos        (16UL)                    /*!< NCESRC65 (Bit 16)                                     */
32955 #define GPIO_PINCFG65_NCESRC65_Msk        (0x3f0000UL)              /*!< NCESRC65 (Bitfield-Mask: 0x3f)                        */
32956 #define GPIO_PINCFG65_PULLCFG65_Pos       (13UL)                    /*!< PULLCFG65 (Bit 13)                                    */
32957 #define GPIO_PINCFG65_PULLCFG65_Msk       (0xe000UL)                /*!< PULLCFG65 (Bitfield-Mask: 0x07)                       */
32958 #define GPIO_PINCFG65_SR65_Pos            (12UL)                    /*!< SR65 (Bit 12)                                         */
32959 #define GPIO_PINCFG65_SR65_Msk            (0x1000UL)                /*!< SR65 (Bitfield-Mask: 0x01)                            */
32960 #define GPIO_PINCFG65_DS65_Pos            (10UL)                    /*!< DS65 (Bit 10)                                         */
32961 #define GPIO_PINCFG65_DS65_Msk            (0xc00UL)                 /*!< DS65 (Bitfield-Mask: 0x03)                            */
32962 #define GPIO_PINCFG65_OUTCFG65_Pos        (8UL)                     /*!< OUTCFG65 (Bit 8)                                      */
32963 #define GPIO_PINCFG65_OUTCFG65_Msk        (0x300UL)                 /*!< OUTCFG65 (Bitfield-Mask: 0x03)                        */
32964 #define GPIO_PINCFG65_IRPTEN65_Pos        (6UL)                     /*!< IRPTEN65 (Bit 6)                                      */
32965 #define GPIO_PINCFG65_IRPTEN65_Msk        (0xc0UL)                  /*!< IRPTEN65 (Bitfield-Mask: 0x03)                        */
32966 #define GPIO_PINCFG65_RDZERO65_Pos        (5UL)                     /*!< RDZERO65 (Bit 5)                                      */
32967 #define GPIO_PINCFG65_RDZERO65_Msk        (0x20UL)                  /*!< RDZERO65 (Bitfield-Mask: 0x01)                        */
32968 #define GPIO_PINCFG65_INPEN65_Pos         (4UL)                     /*!< INPEN65 (Bit 4)                                       */
32969 #define GPIO_PINCFG65_INPEN65_Msk         (0x10UL)                  /*!< INPEN65 (Bitfield-Mask: 0x01)                         */
32970 #define GPIO_PINCFG65_FNCSEL65_Pos        (0UL)                     /*!< FNCSEL65 (Bit 0)                                      */
32971 #define GPIO_PINCFG65_FNCSEL65_Msk        (0xfUL)                   /*!< FNCSEL65 (Bitfield-Mask: 0x0f)                        */
32972 /* =======================================================  PINCFG66  ======================================================== */
32973 #define GPIO_PINCFG66_FOEN66_Pos          (27UL)                    /*!< FOEN66 (Bit 27)                                       */
32974 #define GPIO_PINCFG66_FOEN66_Msk          (0x8000000UL)             /*!< FOEN66 (Bitfield-Mask: 0x01)                          */
32975 #define GPIO_PINCFG66_FIEN66_Pos          (26UL)                    /*!< FIEN66 (Bit 26)                                       */
32976 #define GPIO_PINCFG66_FIEN66_Msk          (0x4000000UL)             /*!< FIEN66 (Bitfield-Mask: 0x01)                          */
32977 #define GPIO_PINCFG66_NCEPOL66_Pos        (22UL)                    /*!< NCEPOL66 (Bit 22)                                     */
32978 #define GPIO_PINCFG66_NCEPOL66_Msk        (0x400000UL)              /*!< NCEPOL66 (Bitfield-Mask: 0x01)                        */
32979 #define GPIO_PINCFG66_NCESRC66_Pos        (16UL)                    /*!< NCESRC66 (Bit 16)                                     */
32980 #define GPIO_PINCFG66_NCESRC66_Msk        (0x3f0000UL)              /*!< NCESRC66 (Bitfield-Mask: 0x3f)                        */
32981 #define GPIO_PINCFG66_PULLCFG66_Pos       (13UL)                    /*!< PULLCFG66 (Bit 13)                                    */
32982 #define GPIO_PINCFG66_PULLCFG66_Msk       (0xe000UL)                /*!< PULLCFG66 (Bitfield-Mask: 0x07)                       */
32983 #define GPIO_PINCFG66_SR66_Pos            (12UL)                    /*!< SR66 (Bit 12)                                         */
32984 #define GPIO_PINCFG66_SR66_Msk            (0x1000UL)                /*!< SR66 (Bitfield-Mask: 0x01)                            */
32985 #define GPIO_PINCFG66_DS66_Pos            (10UL)                    /*!< DS66 (Bit 10)                                         */
32986 #define GPIO_PINCFG66_DS66_Msk            (0xc00UL)                 /*!< DS66 (Bitfield-Mask: 0x03)                            */
32987 #define GPIO_PINCFG66_OUTCFG66_Pos        (8UL)                     /*!< OUTCFG66 (Bit 8)                                      */
32988 #define GPIO_PINCFG66_OUTCFG66_Msk        (0x300UL)                 /*!< OUTCFG66 (Bitfield-Mask: 0x03)                        */
32989 #define GPIO_PINCFG66_IRPTEN66_Pos        (6UL)                     /*!< IRPTEN66 (Bit 6)                                      */
32990 #define GPIO_PINCFG66_IRPTEN66_Msk        (0xc0UL)                  /*!< IRPTEN66 (Bitfield-Mask: 0x03)                        */
32991 #define GPIO_PINCFG66_RDZERO66_Pos        (5UL)                     /*!< RDZERO66 (Bit 5)                                      */
32992 #define GPIO_PINCFG66_RDZERO66_Msk        (0x20UL)                  /*!< RDZERO66 (Bitfield-Mask: 0x01)                        */
32993 #define GPIO_PINCFG66_INPEN66_Pos         (4UL)                     /*!< INPEN66 (Bit 4)                                       */
32994 #define GPIO_PINCFG66_INPEN66_Msk         (0x10UL)                  /*!< INPEN66 (Bitfield-Mask: 0x01)                         */
32995 #define GPIO_PINCFG66_FNCSEL66_Pos        (0UL)                     /*!< FNCSEL66 (Bit 0)                                      */
32996 #define GPIO_PINCFG66_FNCSEL66_Msk        (0xfUL)                   /*!< FNCSEL66 (Bitfield-Mask: 0x0f)                        */
32997 /* =======================================================  PINCFG67  ======================================================== */
32998 #define GPIO_PINCFG67_FOEN67_Pos          (27UL)                    /*!< FOEN67 (Bit 27)                                       */
32999 #define GPIO_PINCFG67_FOEN67_Msk          (0x8000000UL)             /*!< FOEN67 (Bitfield-Mask: 0x01)                          */
33000 #define GPIO_PINCFG67_FIEN67_Pos          (26UL)                    /*!< FIEN67 (Bit 26)                                       */
33001 #define GPIO_PINCFG67_FIEN67_Msk          (0x4000000UL)             /*!< FIEN67 (Bitfield-Mask: 0x01)                          */
33002 #define GPIO_PINCFG67_NCEPOL67_Pos        (22UL)                    /*!< NCEPOL67 (Bit 22)                                     */
33003 #define GPIO_PINCFG67_NCEPOL67_Msk        (0x400000UL)              /*!< NCEPOL67 (Bitfield-Mask: 0x01)                        */
33004 #define GPIO_PINCFG67_NCESRC67_Pos        (16UL)                    /*!< NCESRC67 (Bit 16)                                     */
33005 #define GPIO_PINCFG67_NCESRC67_Msk        (0x3f0000UL)              /*!< NCESRC67 (Bitfield-Mask: 0x3f)                        */
33006 #define GPIO_PINCFG67_PULLCFG67_Pos       (13UL)                    /*!< PULLCFG67 (Bit 13)                                    */
33007 #define GPIO_PINCFG67_PULLCFG67_Msk       (0xe000UL)                /*!< PULLCFG67 (Bitfield-Mask: 0x07)                       */
33008 #define GPIO_PINCFG67_SR67_Pos            (12UL)                    /*!< SR67 (Bit 12)                                         */
33009 #define GPIO_PINCFG67_SR67_Msk            (0x1000UL)                /*!< SR67 (Bitfield-Mask: 0x01)                            */
33010 #define GPIO_PINCFG67_DS67_Pos            (10UL)                    /*!< DS67 (Bit 10)                                         */
33011 #define GPIO_PINCFG67_DS67_Msk            (0xc00UL)                 /*!< DS67 (Bitfield-Mask: 0x03)                            */
33012 #define GPIO_PINCFG67_OUTCFG67_Pos        (8UL)                     /*!< OUTCFG67 (Bit 8)                                      */
33013 #define GPIO_PINCFG67_OUTCFG67_Msk        (0x300UL)                 /*!< OUTCFG67 (Bitfield-Mask: 0x03)                        */
33014 #define GPIO_PINCFG67_IRPTEN67_Pos        (6UL)                     /*!< IRPTEN67 (Bit 6)                                      */
33015 #define GPIO_PINCFG67_IRPTEN67_Msk        (0xc0UL)                  /*!< IRPTEN67 (Bitfield-Mask: 0x03)                        */
33016 #define GPIO_PINCFG67_RDZERO67_Pos        (5UL)                     /*!< RDZERO67 (Bit 5)                                      */
33017 #define GPIO_PINCFG67_RDZERO67_Msk        (0x20UL)                  /*!< RDZERO67 (Bitfield-Mask: 0x01)                        */
33018 #define GPIO_PINCFG67_INPEN67_Pos         (4UL)                     /*!< INPEN67 (Bit 4)                                       */
33019 #define GPIO_PINCFG67_INPEN67_Msk         (0x10UL)                  /*!< INPEN67 (Bitfield-Mask: 0x01)                         */
33020 #define GPIO_PINCFG67_FNCSEL67_Pos        (0UL)                     /*!< FNCSEL67 (Bit 0)                                      */
33021 #define GPIO_PINCFG67_FNCSEL67_Msk        (0xfUL)                   /*!< FNCSEL67 (Bitfield-Mask: 0x0f)                        */
33022 /* =======================================================  PINCFG68  ======================================================== */
33023 #define GPIO_PINCFG68_FOEN68_Pos          (27UL)                    /*!< FOEN68 (Bit 27)                                       */
33024 #define GPIO_PINCFG68_FOEN68_Msk          (0x8000000UL)             /*!< FOEN68 (Bitfield-Mask: 0x01)                          */
33025 #define GPIO_PINCFG68_FIEN68_Pos          (26UL)                    /*!< FIEN68 (Bit 26)                                       */
33026 #define GPIO_PINCFG68_FIEN68_Msk          (0x4000000UL)             /*!< FIEN68 (Bitfield-Mask: 0x01)                          */
33027 #define GPIO_PINCFG68_NCEPOL68_Pos        (22UL)                    /*!< NCEPOL68 (Bit 22)                                     */
33028 #define GPIO_PINCFG68_NCEPOL68_Msk        (0x400000UL)              /*!< NCEPOL68 (Bitfield-Mask: 0x01)                        */
33029 #define GPIO_PINCFG68_NCESRC68_Pos        (16UL)                    /*!< NCESRC68 (Bit 16)                                     */
33030 #define GPIO_PINCFG68_NCESRC68_Msk        (0x3f0000UL)              /*!< NCESRC68 (Bitfield-Mask: 0x3f)                        */
33031 #define GPIO_PINCFG68_PULLCFG68_Pos       (13UL)                    /*!< PULLCFG68 (Bit 13)                                    */
33032 #define GPIO_PINCFG68_PULLCFG68_Msk       (0xe000UL)                /*!< PULLCFG68 (Bitfield-Mask: 0x07)                       */
33033 #define GPIO_PINCFG68_SR68_Pos            (12UL)                    /*!< SR68 (Bit 12)                                         */
33034 #define GPIO_PINCFG68_SR68_Msk            (0x1000UL)                /*!< SR68 (Bitfield-Mask: 0x01)                            */
33035 #define GPIO_PINCFG68_DS68_Pos            (10UL)                    /*!< DS68 (Bit 10)                                         */
33036 #define GPIO_PINCFG68_DS68_Msk            (0xc00UL)                 /*!< DS68 (Bitfield-Mask: 0x03)                            */
33037 #define GPIO_PINCFG68_OUTCFG68_Pos        (8UL)                     /*!< OUTCFG68 (Bit 8)                                      */
33038 #define GPIO_PINCFG68_OUTCFG68_Msk        (0x300UL)                 /*!< OUTCFG68 (Bitfield-Mask: 0x03)                        */
33039 #define GPIO_PINCFG68_IRPTEN68_Pos        (6UL)                     /*!< IRPTEN68 (Bit 6)                                      */
33040 #define GPIO_PINCFG68_IRPTEN68_Msk        (0xc0UL)                  /*!< IRPTEN68 (Bitfield-Mask: 0x03)                        */
33041 #define GPIO_PINCFG68_RDZERO68_Pos        (5UL)                     /*!< RDZERO68 (Bit 5)                                      */
33042 #define GPIO_PINCFG68_RDZERO68_Msk        (0x20UL)                  /*!< RDZERO68 (Bitfield-Mask: 0x01)                        */
33043 #define GPIO_PINCFG68_INPEN68_Pos         (4UL)                     /*!< INPEN68 (Bit 4)                                       */
33044 #define GPIO_PINCFG68_INPEN68_Msk         (0x10UL)                  /*!< INPEN68 (Bitfield-Mask: 0x01)                         */
33045 #define GPIO_PINCFG68_FNCSEL68_Pos        (0UL)                     /*!< FNCSEL68 (Bit 0)                                      */
33046 #define GPIO_PINCFG68_FNCSEL68_Msk        (0xfUL)                   /*!< FNCSEL68 (Bitfield-Mask: 0x0f)                        */
33047 /* =======================================================  PINCFG69  ======================================================== */
33048 #define GPIO_PINCFG69_FOEN69_Pos          (27UL)                    /*!< FOEN69 (Bit 27)                                       */
33049 #define GPIO_PINCFG69_FOEN69_Msk          (0x8000000UL)             /*!< FOEN69 (Bitfield-Mask: 0x01)                          */
33050 #define GPIO_PINCFG69_FIEN69_Pos          (26UL)                    /*!< FIEN69 (Bit 26)                                       */
33051 #define GPIO_PINCFG69_FIEN69_Msk          (0x4000000UL)             /*!< FIEN69 (Bitfield-Mask: 0x01)                          */
33052 #define GPIO_PINCFG69_NCEPOL69_Pos        (22UL)                    /*!< NCEPOL69 (Bit 22)                                     */
33053 #define GPIO_PINCFG69_NCEPOL69_Msk        (0x400000UL)              /*!< NCEPOL69 (Bitfield-Mask: 0x01)                        */
33054 #define GPIO_PINCFG69_NCESRC69_Pos        (16UL)                    /*!< NCESRC69 (Bit 16)                                     */
33055 #define GPIO_PINCFG69_NCESRC69_Msk        (0x3f0000UL)              /*!< NCESRC69 (Bitfield-Mask: 0x3f)                        */
33056 #define GPIO_PINCFG69_PULLCFG69_Pos       (13UL)                    /*!< PULLCFG69 (Bit 13)                                    */
33057 #define GPIO_PINCFG69_PULLCFG69_Msk       (0xe000UL)                /*!< PULLCFG69 (Bitfield-Mask: 0x07)                       */
33058 #define GPIO_PINCFG69_SR69_Pos            (12UL)                    /*!< SR69 (Bit 12)                                         */
33059 #define GPIO_PINCFG69_SR69_Msk            (0x1000UL)                /*!< SR69 (Bitfield-Mask: 0x01)                            */
33060 #define GPIO_PINCFG69_DS69_Pos            (10UL)                    /*!< DS69 (Bit 10)                                         */
33061 #define GPIO_PINCFG69_DS69_Msk            (0xc00UL)                 /*!< DS69 (Bitfield-Mask: 0x03)                            */
33062 #define GPIO_PINCFG69_OUTCFG69_Pos        (8UL)                     /*!< OUTCFG69 (Bit 8)                                      */
33063 #define GPIO_PINCFG69_OUTCFG69_Msk        (0x300UL)                 /*!< OUTCFG69 (Bitfield-Mask: 0x03)                        */
33064 #define GPIO_PINCFG69_IRPTEN69_Pos        (6UL)                     /*!< IRPTEN69 (Bit 6)                                      */
33065 #define GPIO_PINCFG69_IRPTEN69_Msk        (0xc0UL)                  /*!< IRPTEN69 (Bitfield-Mask: 0x03)                        */
33066 #define GPIO_PINCFG69_RDZERO69_Pos        (5UL)                     /*!< RDZERO69 (Bit 5)                                      */
33067 #define GPIO_PINCFG69_RDZERO69_Msk        (0x20UL)                  /*!< RDZERO69 (Bitfield-Mask: 0x01)                        */
33068 #define GPIO_PINCFG69_INPEN69_Pos         (4UL)                     /*!< INPEN69 (Bit 4)                                       */
33069 #define GPIO_PINCFG69_INPEN69_Msk         (0x10UL)                  /*!< INPEN69 (Bitfield-Mask: 0x01)                         */
33070 #define GPIO_PINCFG69_FNCSEL69_Pos        (0UL)                     /*!< FNCSEL69 (Bit 0)                                      */
33071 #define GPIO_PINCFG69_FNCSEL69_Msk        (0xfUL)                   /*!< FNCSEL69 (Bitfield-Mask: 0x0f)                        */
33072 /* =======================================================  PINCFG70  ======================================================== */
33073 #define GPIO_PINCFG70_FOEN70_Pos          (27UL)                    /*!< FOEN70 (Bit 27)                                       */
33074 #define GPIO_PINCFG70_FOEN70_Msk          (0x8000000UL)             /*!< FOEN70 (Bitfield-Mask: 0x01)                          */
33075 #define GPIO_PINCFG70_FIEN70_Pos          (26UL)                    /*!< FIEN70 (Bit 26)                                       */
33076 #define GPIO_PINCFG70_FIEN70_Msk          (0x4000000UL)             /*!< FIEN70 (Bitfield-Mask: 0x01)                          */
33077 #define GPIO_PINCFG70_NCEPOL70_Pos        (22UL)                    /*!< NCEPOL70 (Bit 22)                                     */
33078 #define GPIO_PINCFG70_NCEPOL70_Msk        (0x400000UL)              /*!< NCEPOL70 (Bitfield-Mask: 0x01)                        */
33079 #define GPIO_PINCFG70_NCESRC70_Pos        (16UL)                    /*!< NCESRC70 (Bit 16)                                     */
33080 #define GPIO_PINCFG70_NCESRC70_Msk        (0x3f0000UL)              /*!< NCESRC70 (Bitfield-Mask: 0x3f)                        */
33081 #define GPIO_PINCFG70_PULLCFG70_Pos       (13UL)                    /*!< PULLCFG70 (Bit 13)                                    */
33082 #define GPIO_PINCFG70_PULLCFG70_Msk       (0xe000UL)                /*!< PULLCFG70 (Bitfield-Mask: 0x07)                       */
33083 #define GPIO_PINCFG70_SR70_Pos            (12UL)                    /*!< SR70 (Bit 12)                                         */
33084 #define GPIO_PINCFG70_SR70_Msk            (0x1000UL)                /*!< SR70 (Bitfield-Mask: 0x01)                            */
33085 #define GPIO_PINCFG70_DS70_Pos            (10UL)                    /*!< DS70 (Bit 10)                                         */
33086 #define GPIO_PINCFG70_DS70_Msk            (0xc00UL)                 /*!< DS70 (Bitfield-Mask: 0x03)                            */
33087 #define GPIO_PINCFG70_OUTCFG70_Pos        (8UL)                     /*!< OUTCFG70 (Bit 8)                                      */
33088 #define GPIO_PINCFG70_OUTCFG70_Msk        (0x300UL)                 /*!< OUTCFG70 (Bitfield-Mask: 0x03)                        */
33089 #define GPIO_PINCFG70_IRPTEN70_Pos        (6UL)                     /*!< IRPTEN70 (Bit 6)                                      */
33090 #define GPIO_PINCFG70_IRPTEN70_Msk        (0xc0UL)                  /*!< IRPTEN70 (Bitfield-Mask: 0x03)                        */
33091 #define GPIO_PINCFG70_RDZERO70_Pos        (5UL)                     /*!< RDZERO70 (Bit 5)                                      */
33092 #define GPIO_PINCFG70_RDZERO70_Msk        (0x20UL)                  /*!< RDZERO70 (Bitfield-Mask: 0x01)                        */
33093 #define GPIO_PINCFG70_INPEN70_Pos         (4UL)                     /*!< INPEN70 (Bit 4)                                       */
33094 #define GPIO_PINCFG70_INPEN70_Msk         (0x10UL)                  /*!< INPEN70 (Bitfield-Mask: 0x01)                         */
33095 #define GPIO_PINCFG70_FNCSEL70_Pos        (0UL)                     /*!< FNCSEL70 (Bit 0)                                      */
33096 #define GPIO_PINCFG70_FNCSEL70_Msk        (0xfUL)                   /*!< FNCSEL70 (Bitfield-Mask: 0x0f)                        */
33097 /* =======================================================  PINCFG71  ======================================================== */
33098 #define GPIO_PINCFG71_FOEN71_Pos          (27UL)                    /*!< FOEN71 (Bit 27)                                       */
33099 #define GPIO_PINCFG71_FOEN71_Msk          (0x8000000UL)             /*!< FOEN71 (Bitfield-Mask: 0x01)                          */
33100 #define GPIO_PINCFG71_FIEN71_Pos          (26UL)                    /*!< FIEN71 (Bit 26)                                       */
33101 #define GPIO_PINCFG71_FIEN71_Msk          (0x4000000UL)             /*!< FIEN71 (Bitfield-Mask: 0x01)                          */
33102 #define GPIO_PINCFG71_NCEPOL71_Pos        (22UL)                    /*!< NCEPOL71 (Bit 22)                                     */
33103 #define GPIO_PINCFG71_NCEPOL71_Msk        (0x400000UL)              /*!< NCEPOL71 (Bitfield-Mask: 0x01)                        */
33104 #define GPIO_PINCFG71_NCESRC71_Pos        (16UL)                    /*!< NCESRC71 (Bit 16)                                     */
33105 #define GPIO_PINCFG71_NCESRC71_Msk        (0x3f0000UL)              /*!< NCESRC71 (Bitfield-Mask: 0x3f)                        */
33106 #define GPIO_PINCFG71_PULLCFG71_Pos       (13UL)                    /*!< PULLCFG71 (Bit 13)                                    */
33107 #define GPIO_PINCFG71_PULLCFG71_Msk       (0xe000UL)                /*!< PULLCFG71 (Bitfield-Mask: 0x07)                       */
33108 #define GPIO_PINCFG71_SR71_Pos            (12UL)                    /*!< SR71 (Bit 12)                                         */
33109 #define GPIO_PINCFG71_SR71_Msk            (0x1000UL)                /*!< SR71 (Bitfield-Mask: 0x01)                            */
33110 #define GPIO_PINCFG71_DS71_Pos            (10UL)                    /*!< DS71 (Bit 10)                                         */
33111 #define GPIO_PINCFG71_DS71_Msk            (0xc00UL)                 /*!< DS71 (Bitfield-Mask: 0x03)                            */
33112 #define GPIO_PINCFG71_OUTCFG71_Pos        (8UL)                     /*!< OUTCFG71 (Bit 8)                                      */
33113 #define GPIO_PINCFG71_OUTCFG71_Msk        (0x300UL)                 /*!< OUTCFG71 (Bitfield-Mask: 0x03)                        */
33114 #define GPIO_PINCFG71_IRPTEN71_Pos        (6UL)                     /*!< IRPTEN71 (Bit 6)                                      */
33115 #define GPIO_PINCFG71_IRPTEN71_Msk        (0xc0UL)                  /*!< IRPTEN71 (Bitfield-Mask: 0x03)                        */
33116 #define GPIO_PINCFG71_RDZERO71_Pos        (5UL)                     /*!< RDZERO71 (Bit 5)                                      */
33117 #define GPIO_PINCFG71_RDZERO71_Msk        (0x20UL)                  /*!< RDZERO71 (Bitfield-Mask: 0x01)                        */
33118 #define GPIO_PINCFG71_INPEN71_Pos         (4UL)                     /*!< INPEN71 (Bit 4)                                       */
33119 #define GPIO_PINCFG71_INPEN71_Msk         (0x10UL)                  /*!< INPEN71 (Bitfield-Mask: 0x01)                         */
33120 #define GPIO_PINCFG71_FNCSEL71_Pos        (0UL)                     /*!< FNCSEL71 (Bit 0)                                      */
33121 #define GPIO_PINCFG71_FNCSEL71_Msk        (0xfUL)                   /*!< FNCSEL71 (Bitfield-Mask: 0x0f)                        */
33122 /* =======================================================  PINCFG72  ======================================================== */
33123 #define GPIO_PINCFG72_FOEN72_Pos          (27UL)                    /*!< FOEN72 (Bit 27)                                       */
33124 #define GPIO_PINCFG72_FOEN72_Msk          (0x8000000UL)             /*!< FOEN72 (Bitfield-Mask: 0x01)                          */
33125 #define GPIO_PINCFG72_FIEN72_Pos          (26UL)                    /*!< FIEN72 (Bit 26)                                       */
33126 #define GPIO_PINCFG72_FIEN72_Msk          (0x4000000UL)             /*!< FIEN72 (Bitfield-Mask: 0x01)                          */
33127 #define GPIO_PINCFG72_NCEPOL72_Pos        (22UL)                    /*!< NCEPOL72 (Bit 22)                                     */
33128 #define GPIO_PINCFG72_NCEPOL72_Msk        (0x400000UL)              /*!< NCEPOL72 (Bitfield-Mask: 0x01)                        */
33129 #define GPIO_PINCFG72_NCESRC72_Pos        (16UL)                    /*!< NCESRC72 (Bit 16)                                     */
33130 #define GPIO_PINCFG72_NCESRC72_Msk        (0x3f0000UL)              /*!< NCESRC72 (Bitfield-Mask: 0x3f)                        */
33131 #define GPIO_PINCFG72_PULLCFG72_Pos       (13UL)                    /*!< PULLCFG72 (Bit 13)                                    */
33132 #define GPIO_PINCFG72_PULLCFG72_Msk       (0xe000UL)                /*!< PULLCFG72 (Bitfield-Mask: 0x07)                       */
33133 #define GPIO_PINCFG72_SR72_Pos            (12UL)                    /*!< SR72 (Bit 12)                                         */
33134 #define GPIO_PINCFG72_SR72_Msk            (0x1000UL)                /*!< SR72 (Bitfield-Mask: 0x01)                            */
33135 #define GPIO_PINCFG72_DS72_Pos            (10UL)                    /*!< DS72 (Bit 10)                                         */
33136 #define GPIO_PINCFG72_DS72_Msk            (0xc00UL)                 /*!< DS72 (Bitfield-Mask: 0x03)                            */
33137 #define GPIO_PINCFG72_OUTCFG72_Pos        (8UL)                     /*!< OUTCFG72 (Bit 8)                                      */
33138 #define GPIO_PINCFG72_OUTCFG72_Msk        (0x300UL)                 /*!< OUTCFG72 (Bitfield-Mask: 0x03)                        */
33139 #define GPIO_PINCFG72_IRPTEN72_Pos        (6UL)                     /*!< IRPTEN72 (Bit 6)                                      */
33140 #define GPIO_PINCFG72_IRPTEN72_Msk        (0xc0UL)                  /*!< IRPTEN72 (Bitfield-Mask: 0x03)                        */
33141 #define GPIO_PINCFG72_RDZERO72_Pos        (5UL)                     /*!< RDZERO72 (Bit 5)                                      */
33142 #define GPIO_PINCFG72_RDZERO72_Msk        (0x20UL)                  /*!< RDZERO72 (Bitfield-Mask: 0x01)                        */
33143 #define GPIO_PINCFG72_INPEN72_Pos         (4UL)                     /*!< INPEN72 (Bit 4)                                       */
33144 #define GPIO_PINCFG72_INPEN72_Msk         (0x10UL)                  /*!< INPEN72 (Bitfield-Mask: 0x01)                         */
33145 #define GPIO_PINCFG72_FNCSEL72_Pos        (0UL)                     /*!< FNCSEL72 (Bit 0)                                      */
33146 #define GPIO_PINCFG72_FNCSEL72_Msk        (0xfUL)                   /*!< FNCSEL72 (Bitfield-Mask: 0x0f)                        */
33147 /* =======================================================  PINCFG73  ======================================================== */
33148 #define GPIO_PINCFG73_FOEN73_Pos          (27UL)                    /*!< FOEN73 (Bit 27)                                       */
33149 #define GPIO_PINCFG73_FOEN73_Msk          (0x8000000UL)             /*!< FOEN73 (Bitfield-Mask: 0x01)                          */
33150 #define GPIO_PINCFG73_FIEN73_Pos          (26UL)                    /*!< FIEN73 (Bit 26)                                       */
33151 #define GPIO_PINCFG73_FIEN73_Msk          (0x4000000UL)             /*!< FIEN73 (Bitfield-Mask: 0x01)                          */
33152 #define GPIO_PINCFG73_NCEPOL73_Pos        (22UL)                    /*!< NCEPOL73 (Bit 22)                                     */
33153 #define GPIO_PINCFG73_NCEPOL73_Msk        (0x400000UL)              /*!< NCEPOL73 (Bitfield-Mask: 0x01)                        */
33154 #define GPIO_PINCFG73_NCESRC73_Pos        (16UL)                    /*!< NCESRC73 (Bit 16)                                     */
33155 #define GPIO_PINCFG73_NCESRC73_Msk        (0x3f0000UL)              /*!< NCESRC73 (Bitfield-Mask: 0x3f)                        */
33156 #define GPIO_PINCFG73_PULLCFG73_Pos       (13UL)                    /*!< PULLCFG73 (Bit 13)                                    */
33157 #define GPIO_PINCFG73_PULLCFG73_Msk       (0xe000UL)                /*!< PULLCFG73 (Bitfield-Mask: 0x07)                       */
33158 #define GPIO_PINCFG73_SR73_Pos            (12UL)                    /*!< SR73 (Bit 12)                                         */
33159 #define GPIO_PINCFG73_SR73_Msk            (0x1000UL)                /*!< SR73 (Bitfield-Mask: 0x01)                            */
33160 #define GPIO_PINCFG73_DS73_Pos            (10UL)                    /*!< DS73 (Bit 10)                                         */
33161 #define GPIO_PINCFG73_DS73_Msk            (0xc00UL)                 /*!< DS73 (Bitfield-Mask: 0x03)                            */
33162 #define GPIO_PINCFG73_OUTCFG73_Pos        (8UL)                     /*!< OUTCFG73 (Bit 8)                                      */
33163 #define GPIO_PINCFG73_OUTCFG73_Msk        (0x300UL)                 /*!< OUTCFG73 (Bitfield-Mask: 0x03)                        */
33164 #define GPIO_PINCFG73_IRPTEN73_Pos        (6UL)                     /*!< IRPTEN73 (Bit 6)                                      */
33165 #define GPIO_PINCFG73_IRPTEN73_Msk        (0xc0UL)                  /*!< IRPTEN73 (Bitfield-Mask: 0x03)                        */
33166 #define GPIO_PINCFG73_RDZERO73_Pos        (5UL)                     /*!< RDZERO73 (Bit 5)                                      */
33167 #define GPIO_PINCFG73_RDZERO73_Msk        (0x20UL)                  /*!< RDZERO73 (Bitfield-Mask: 0x01)                        */
33168 #define GPIO_PINCFG73_INPEN73_Pos         (4UL)                     /*!< INPEN73 (Bit 4)                                       */
33169 #define GPIO_PINCFG73_INPEN73_Msk         (0x10UL)                  /*!< INPEN73 (Bitfield-Mask: 0x01)                         */
33170 #define GPIO_PINCFG73_FNCSEL73_Pos        (0UL)                     /*!< FNCSEL73 (Bit 0)                                      */
33171 #define GPIO_PINCFG73_FNCSEL73_Msk        (0xfUL)                   /*!< FNCSEL73 (Bitfield-Mask: 0x0f)                        */
33172 /* =======================================================  PINCFG74  ======================================================== */
33173 #define GPIO_PINCFG74_FOEN74_Pos          (27UL)                    /*!< FOEN74 (Bit 27)                                       */
33174 #define GPIO_PINCFG74_FOEN74_Msk          (0x8000000UL)             /*!< FOEN74 (Bitfield-Mask: 0x01)                          */
33175 #define GPIO_PINCFG74_FIEN74_Pos          (26UL)                    /*!< FIEN74 (Bit 26)                                       */
33176 #define GPIO_PINCFG74_FIEN74_Msk          (0x4000000UL)             /*!< FIEN74 (Bitfield-Mask: 0x01)                          */
33177 #define GPIO_PINCFG74_NCEPOL74_Pos        (22UL)                    /*!< NCEPOL74 (Bit 22)                                     */
33178 #define GPIO_PINCFG74_NCEPOL74_Msk        (0x400000UL)              /*!< NCEPOL74 (Bitfield-Mask: 0x01)                        */
33179 #define GPIO_PINCFG74_NCESRC74_Pos        (16UL)                    /*!< NCESRC74 (Bit 16)                                     */
33180 #define GPIO_PINCFG74_NCESRC74_Msk        (0x3f0000UL)              /*!< NCESRC74 (Bitfield-Mask: 0x3f)                        */
33181 #define GPIO_PINCFG74_PULLCFG74_Pos       (13UL)                    /*!< PULLCFG74 (Bit 13)                                    */
33182 #define GPIO_PINCFG74_PULLCFG74_Msk       (0xe000UL)                /*!< PULLCFG74 (Bitfield-Mask: 0x07)                       */
33183 #define GPIO_PINCFG74_SR74_Pos            (12UL)                    /*!< SR74 (Bit 12)                                         */
33184 #define GPIO_PINCFG74_SR74_Msk            (0x1000UL)                /*!< SR74 (Bitfield-Mask: 0x01)                            */
33185 #define GPIO_PINCFG74_DS74_Pos            (10UL)                    /*!< DS74 (Bit 10)                                         */
33186 #define GPIO_PINCFG74_DS74_Msk            (0xc00UL)                 /*!< DS74 (Bitfield-Mask: 0x03)                            */
33187 #define GPIO_PINCFG74_OUTCFG74_Pos        (8UL)                     /*!< OUTCFG74 (Bit 8)                                      */
33188 #define GPIO_PINCFG74_OUTCFG74_Msk        (0x300UL)                 /*!< OUTCFG74 (Bitfield-Mask: 0x03)                        */
33189 #define GPIO_PINCFG74_IRPTEN74_Pos        (6UL)                     /*!< IRPTEN74 (Bit 6)                                      */
33190 #define GPIO_PINCFG74_IRPTEN74_Msk        (0xc0UL)                  /*!< IRPTEN74 (Bitfield-Mask: 0x03)                        */
33191 #define GPIO_PINCFG74_RDZERO74_Pos        (5UL)                     /*!< RDZERO74 (Bit 5)                                      */
33192 #define GPIO_PINCFG74_RDZERO74_Msk        (0x20UL)                  /*!< RDZERO74 (Bitfield-Mask: 0x01)                        */
33193 #define GPIO_PINCFG74_INPEN74_Pos         (4UL)                     /*!< INPEN74 (Bit 4)                                       */
33194 #define GPIO_PINCFG74_INPEN74_Msk         (0x10UL)                  /*!< INPEN74 (Bitfield-Mask: 0x01)                         */
33195 #define GPIO_PINCFG74_FNCSEL74_Pos        (0UL)                     /*!< FNCSEL74 (Bit 0)                                      */
33196 #define GPIO_PINCFG74_FNCSEL74_Msk        (0xfUL)                   /*!< FNCSEL74 (Bitfield-Mask: 0x0f)                        */
33197 /* =======================================================  PINCFG75  ======================================================== */
33198 #define GPIO_PINCFG75_FOEN75_Pos          (27UL)                    /*!< FOEN75 (Bit 27)                                       */
33199 #define GPIO_PINCFG75_FOEN75_Msk          (0x8000000UL)             /*!< FOEN75 (Bitfield-Mask: 0x01)                          */
33200 #define GPIO_PINCFG75_FIEN75_Pos          (26UL)                    /*!< FIEN75 (Bit 26)                                       */
33201 #define GPIO_PINCFG75_FIEN75_Msk          (0x4000000UL)             /*!< FIEN75 (Bitfield-Mask: 0x01)                          */
33202 #define GPIO_PINCFG75_NCEPOL75_Pos        (22UL)                    /*!< NCEPOL75 (Bit 22)                                     */
33203 #define GPIO_PINCFG75_NCEPOL75_Msk        (0x400000UL)              /*!< NCEPOL75 (Bitfield-Mask: 0x01)                        */
33204 #define GPIO_PINCFG75_NCESRC75_Pos        (16UL)                    /*!< NCESRC75 (Bit 16)                                     */
33205 #define GPIO_PINCFG75_NCESRC75_Msk        (0x3f0000UL)              /*!< NCESRC75 (Bitfield-Mask: 0x3f)                        */
33206 #define GPIO_PINCFG75_PULLCFG75_Pos       (13UL)                    /*!< PULLCFG75 (Bit 13)                                    */
33207 #define GPIO_PINCFG75_PULLCFG75_Msk       (0xe000UL)                /*!< PULLCFG75 (Bitfield-Mask: 0x07)                       */
33208 #define GPIO_PINCFG75_SR75_Pos            (12UL)                    /*!< SR75 (Bit 12)                                         */
33209 #define GPIO_PINCFG75_SR75_Msk            (0x1000UL)                /*!< SR75 (Bitfield-Mask: 0x01)                            */
33210 #define GPIO_PINCFG75_DS75_Pos            (10UL)                    /*!< DS75 (Bit 10)                                         */
33211 #define GPIO_PINCFG75_DS75_Msk            (0xc00UL)                 /*!< DS75 (Bitfield-Mask: 0x03)                            */
33212 #define GPIO_PINCFG75_OUTCFG75_Pos        (8UL)                     /*!< OUTCFG75 (Bit 8)                                      */
33213 #define GPIO_PINCFG75_OUTCFG75_Msk        (0x300UL)                 /*!< OUTCFG75 (Bitfield-Mask: 0x03)                        */
33214 #define GPIO_PINCFG75_IRPTEN75_Pos        (6UL)                     /*!< IRPTEN75 (Bit 6)                                      */
33215 #define GPIO_PINCFG75_IRPTEN75_Msk        (0xc0UL)                  /*!< IRPTEN75 (Bitfield-Mask: 0x03)                        */
33216 #define GPIO_PINCFG75_RDZERO75_Pos        (5UL)                     /*!< RDZERO75 (Bit 5)                                      */
33217 #define GPIO_PINCFG75_RDZERO75_Msk        (0x20UL)                  /*!< RDZERO75 (Bitfield-Mask: 0x01)                        */
33218 #define GPIO_PINCFG75_INPEN75_Pos         (4UL)                     /*!< INPEN75 (Bit 4)                                       */
33219 #define GPIO_PINCFG75_INPEN75_Msk         (0x10UL)                  /*!< INPEN75 (Bitfield-Mask: 0x01)                         */
33220 #define GPIO_PINCFG75_FNCSEL75_Pos        (0UL)                     /*!< FNCSEL75 (Bit 0)                                      */
33221 #define GPIO_PINCFG75_FNCSEL75_Msk        (0xfUL)                   /*!< FNCSEL75 (Bitfield-Mask: 0x0f)                        */
33222 /* =======================================================  PINCFG76  ======================================================== */
33223 #define GPIO_PINCFG76_FOEN76_Pos          (27UL)                    /*!< FOEN76 (Bit 27)                                       */
33224 #define GPIO_PINCFG76_FOEN76_Msk          (0x8000000UL)             /*!< FOEN76 (Bitfield-Mask: 0x01)                          */
33225 #define GPIO_PINCFG76_FIEN76_Pos          (26UL)                    /*!< FIEN76 (Bit 26)                                       */
33226 #define GPIO_PINCFG76_FIEN76_Msk          (0x4000000UL)             /*!< FIEN76 (Bitfield-Mask: 0x01)                          */
33227 #define GPIO_PINCFG76_NCEPOL76_Pos        (22UL)                    /*!< NCEPOL76 (Bit 22)                                     */
33228 #define GPIO_PINCFG76_NCEPOL76_Msk        (0x400000UL)              /*!< NCEPOL76 (Bitfield-Mask: 0x01)                        */
33229 #define GPIO_PINCFG76_NCESRC76_Pos        (16UL)                    /*!< NCESRC76 (Bit 16)                                     */
33230 #define GPIO_PINCFG76_NCESRC76_Msk        (0x3f0000UL)              /*!< NCESRC76 (Bitfield-Mask: 0x3f)                        */
33231 #define GPIO_PINCFG76_PULLCFG76_Pos       (13UL)                    /*!< PULLCFG76 (Bit 13)                                    */
33232 #define GPIO_PINCFG76_PULLCFG76_Msk       (0xe000UL)                /*!< PULLCFG76 (Bitfield-Mask: 0x07)                       */
33233 #define GPIO_PINCFG76_SR76_Pos            (12UL)                    /*!< SR76 (Bit 12)                                         */
33234 #define GPIO_PINCFG76_SR76_Msk            (0x1000UL)                /*!< SR76 (Bitfield-Mask: 0x01)                            */
33235 #define GPIO_PINCFG76_DS76_Pos            (10UL)                    /*!< DS76 (Bit 10)                                         */
33236 #define GPIO_PINCFG76_DS76_Msk            (0xc00UL)                 /*!< DS76 (Bitfield-Mask: 0x03)                            */
33237 #define GPIO_PINCFG76_OUTCFG76_Pos        (8UL)                     /*!< OUTCFG76 (Bit 8)                                      */
33238 #define GPIO_PINCFG76_OUTCFG76_Msk        (0x300UL)                 /*!< OUTCFG76 (Bitfield-Mask: 0x03)                        */
33239 #define GPIO_PINCFG76_IRPTEN76_Pos        (6UL)                     /*!< IRPTEN76 (Bit 6)                                      */
33240 #define GPIO_PINCFG76_IRPTEN76_Msk        (0xc0UL)                  /*!< IRPTEN76 (Bitfield-Mask: 0x03)                        */
33241 #define GPIO_PINCFG76_RDZERO76_Pos        (5UL)                     /*!< RDZERO76 (Bit 5)                                      */
33242 #define GPIO_PINCFG76_RDZERO76_Msk        (0x20UL)                  /*!< RDZERO76 (Bitfield-Mask: 0x01)                        */
33243 #define GPIO_PINCFG76_INPEN76_Pos         (4UL)                     /*!< INPEN76 (Bit 4)                                       */
33244 #define GPIO_PINCFG76_INPEN76_Msk         (0x10UL)                  /*!< INPEN76 (Bitfield-Mask: 0x01)                         */
33245 #define GPIO_PINCFG76_FNCSEL76_Pos        (0UL)                     /*!< FNCSEL76 (Bit 0)                                      */
33246 #define GPIO_PINCFG76_FNCSEL76_Msk        (0xfUL)                   /*!< FNCSEL76 (Bitfield-Mask: 0x0f)                        */
33247 /* =======================================================  PINCFG77  ======================================================== */
33248 #define GPIO_PINCFG77_FOEN77_Pos          (27UL)                    /*!< FOEN77 (Bit 27)                                       */
33249 #define GPIO_PINCFG77_FOEN77_Msk          (0x8000000UL)             /*!< FOEN77 (Bitfield-Mask: 0x01)                          */
33250 #define GPIO_PINCFG77_FIEN77_Pos          (26UL)                    /*!< FIEN77 (Bit 26)                                       */
33251 #define GPIO_PINCFG77_FIEN77_Msk          (0x4000000UL)             /*!< FIEN77 (Bitfield-Mask: 0x01)                          */
33252 #define GPIO_PINCFG77_NCEPOL77_Pos        (22UL)                    /*!< NCEPOL77 (Bit 22)                                     */
33253 #define GPIO_PINCFG77_NCEPOL77_Msk        (0x400000UL)              /*!< NCEPOL77 (Bitfield-Mask: 0x01)                        */
33254 #define GPIO_PINCFG77_NCESRC77_Pos        (16UL)                    /*!< NCESRC77 (Bit 16)                                     */
33255 #define GPIO_PINCFG77_NCESRC77_Msk        (0x3f0000UL)              /*!< NCESRC77 (Bitfield-Mask: 0x3f)                        */
33256 #define GPIO_PINCFG77_PULLCFG77_Pos       (13UL)                    /*!< PULLCFG77 (Bit 13)                                    */
33257 #define GPIO_PINCFG77_PULLCFG77_Msk       (0xe000UL)                /*!< PULLCFG77 (Bitfield-Mask: 0x07)                       */
33258 #define GPIO_PINCFG77_SR77_Pos            (12UL)                    /*!< SR77 (Bit 12)                                         */
33259 #define GPIO_PINCFG77_SR77_Msk            (0x1000UL)                /*!< SR77 (Bitfield-Mask: 0x01)                            */
33260 #define GPIO_PINCFG77_DS77_Pos            (10UL)                    /*!< DS77 (Bit 10)                                         */
33261 #define GPIO_PINCFG77_DS77_Msk            (0xc00UL)                 /*!< DS77 (Bitfield-Mask: 0x03)                            */
33262 #define GPIO_PINCFG77_OUTCFG77_Pos        (8UL)                     /*!< OUTCFG77 (Bit 8)                                      */
33263 #define GPIO_PINCFG77_OUTCFG77_Msk        (0x300UL)                 /*!< OUTCFG77 (Bitfield-Mask: 0x03)                        */
33264 #define GPIO_PINCFG77_IRPTEN77_Pos        (6UL)                     /*!< IRPTEN77 (Bit 6)                                      */
33265 #define GPIO_PINCFG77_IRPTEN77_Msk        (0xc0UL)                  /*!< IRPTEN77 (Bitfield-Mask: 0x03)                        */
33266 #define GPIO_PINCFG77_RDZERO77_Pos        (5UL)                     /*!< RDZERO77 (Bit 5)                                      */
33267 #define GPIO_PINCFG77_RDZERO77_Msk        (0x20UL)                  /*!< RDZERO77 (Bitfield-Mask: 0x01)                        */
33268 #define GPIO_PINCFG77_INPEN77_Pos         (4UL)                     /*!< INPEN77 (Bit 4)                                       */
33269 #define GPIO_PINCFG77_INPEN77_Msk         (0x10UL)                  /*!< INPEN77 (Bitfield-Mask: 0x01)                         */
33270 #define GPIO_PINCFG77_FNCSEL77_Pos        (0UL)                     /*!< FNCSEL77 (Bit 0)                                      */
33271 #define GPIO_PINCFG77_FNCSEL77_Msk        (0xfUL)                   /*!< FNCSEL77 (Bitfield-Mask: 0x0f)                        */
33272 /* =======================================================  PINCFG78  ======================================================== */
33273 #define GPIO_PINCFG78_FOEN78_Pos          (27UL)                    /*!< FOEN78 (Bit 27)                                       */
33274 #define GPIO_PINCFG78_FOEN78_Msk          (0x8000000UL)             /*!< FOEN78 (Bitfield-Mask: 0x01)                          */
33275 #define GPIO_PINCFG78_FIEN78_Pos          (26UL)                    /*!< FIEN78 (Bit 26)                                       */
33276 #define GPIO_PINCFG78_FIEN78_Msk          (0x4000000UL)             /*!< FIEN78 (Bitfield-Mask: 0x01)                          */
33277 #define GPIO_PINCFG78_NCEPOL78_Pos        (22UL)                    /*!< NCEPOL78 (Bit 22)                                     */
33278 #define GPIO_PINCFG78_NCEPOL78_Msk        (0x400000UL)              /*!< NCEPOL78 (Bitfield-Mask: 0x01)                        */
33279 #define GPIO_PINCFG78_NCESRC78_Pos        (16UL)                    /*!< NCESRC78 (Bit 16)                                     */
33280 #define GPIO_PINCFG78_NCESRC78_Msk        (0x3f0000UL)              /*!< NCESRC78 (Bitfield-Mask: 0x3f)                        */
33281 #define GPIO_PINCFG78_PULLCFG78_Pos       (13UL)                    /*!< PULLCFG78 (Bit 13)                                    */
33282 #define GPIO_PINCFG78_PULLCFG78_Msk       (0xe000UL)                /*!< PULLCFG78 (Bitfield-Mask: 0x07)                       */
33283 #define GPIO_PINCFG78_SR78_Pos            (12UL)                    /*!< SR78 (Bit 12)                                         */
33284 #define GPIO_PINCFG78_SR78_Msk            (0x1000UL)                /*!< SR78 (Bitfield-Mask: 0x01)                            */
33285 #define GPIO_PINCFG78_DS78_Pos            (10UL)                    /*!< DS78 (Bit 10)                                         */
33286 #define GPIO_PINCFG78_DS78_Msk            (0xc00UL)                 /*!< DS78 (Bitfield-Mask: 0x03)                            */
33287 #define GPIO_PINCFG78_OUTCFG78_Pos        (8UL)                     /*!< OUTCFG78 (Bit 8)                                      */
33288 #define GPIO_PINCFG78_OUTCFG78_Msk        (0x300UL)                 /*!< OUTCFG78 (Bitfield-Mask: 0x03)                        */
33289 #define GPIO_PINCFG78_IRPTEN78_Pos        (6UL)                     /*!< IRPTEN78 (Bit 6)                                      */
33290 #define GPIO_PINCFG78_IRPTEN78_Msk        (0xc0UL)                  /*!< IRPTEN78 (Bitfield-Mask: 0x03)                        */
33291 #define GPIO_PINCFG78_RDZERO78_Pos        (5UL)                     /*!< RDZERO78 (Bit 5)                                      */
33292 #define GPIO_PINCFG78_RDZERO78_Msk        (0x20UL)                  /*!< RDZERO78 (Bitfield-Mask: 0x01)                        */
33293 #define GPIO_PINCFG78_INPEN78_Pos         (4UL)                     /*!< INPEN78 (Bit 4)                                       */
33294 #define GPIO_PINCFG78_INPEN78_Msk         (0x10UL)                  /*!< INPEN78 (Bitfield-Mask: 0x01)                         */
33295 #define GPIO_PINCFG78_FNCSEL78_Pos        (0UL)                     /*!< FNCSEL78 (Bit 0)                                      */
33296 #define GPIO_PINCFG78_FNCSEL78_Msk        (0xfUL)                   /*!< FNCSEL78 (Bitfield-Mask: 0x0f)                        */
33297 /* =======================================================  PINCFG79  ======================================================== */
33298 #define GPIO_PINCFG79_FOEN79_Pos          (27UL)                    /*!< FOEN79 (Bit 27)                                       */
33299 #define GPIO_PINCFG79_FOEN79_Msk          (0x8000000UL)             /*!< FOEN79 (Bitfield-Mask: 0x01)                          */
33300 #define GPIO_PINCFG79_FIEN79_Pos          (26UL)                    /*!< FIEN79 (Bit 26)                                       */
33301 #define GPIO_PINCFG79_FIEN79_Msk          (0x4000000UL)             /*!< FIEN79 (Bitfield-Mask: 0x01)                          */
33302 #define GPIO_PINCFG79_NCEPOL79_Pos        (22UL)                    /*!< NCEPOL79 (Bit 22)                                     */
33303 #define GPIO_PINCFG79_NCEPOL79_Msk        (0x400000UL)              /*!< NCEPOL79 (Bitfield-Mask: 0x01)                        */
33304 #define GPIO_PINCFG79_NCESRC79_Pos        (16UL)                    /*!< NCESRC79 (Bit 16)                                     */
33305 #define GPIO_PINCFG79_NCESRC79_Msk        (0x3f0000UL)              /*!< NCESRC79 (Bitfield-Mask: 0x3f)                        */
33306 #define GPIO_PINCFG79_PULLCFG79_Pos       (13UL)                    /*!< PULLCFG79 (Bit 13)                                    */
33307 #define GPIO_PINCFG79_PULLCFG79_Msk       (0xe000UL)                /*!< PULLCFG79 (Bitfield-Mask: 0x07)                       */
33308 #define GPIO_PINCFG79_SR79_Pos            (12UL)                    /*!< SR79 (Bit 12)                                         */
33309 #define GPIO_PINCFG79_SR79_Msk            (0x1000UL)                /*!< SR79 (Bitfield-Mask: 0x01)                            */
33310 #define GPIO_PINCFG79_DS79_Pos            (10UL)                    /*!< DS79 (Bit 10)                                         */
33311 #define GPIO_PINCFG79_DS79_Msk            (0xc00UL)                 /*!< DS79 (Bitfield-Mask: 0x03)                            */
33312 #define GPIO_PINCFG79_OUTCFG79_Pos        (8UL)                     /*!< OUTCFG79 (Bit 8)                                      */
33313 #define GPIO_PINCFG79_OUTCFG79_Msk        (0x300UL)                 /*!< OUTCFG79 (Bitfield-Mask: 0x03)                        */
33314 #define GPIO_PINCFG79_IRPTEN79_Pos        (6UL)                     /*!< IRPTEN79 (Bit 6)                                      */
33315 #define GPIO_PINCFG79_IRPTEN79_Msk        (0xc0UL)                  /*!< IRPTEN79 (Bitfield-Mask: 0x03)                        */
33316 #define GPIO_PINCFG79_RDZERO79_Pos        (5UL)                     /*!< RDZERO79 (Bit 5)                                      */
33317 #define GPIO_PINCFG79_RDZERO79_Msk        (0x20UL)                  /*!< RDZERO79 (Bitfield-Mask: 0x01)                        */
33318 #define GPIO_PINCFG79_INPEN79_Pos         (4UL)                     /*!< INPEN79 (Bit 4)                                       */
33319 #define GPIO_PINCFG79_INPEN79_Msk         (0x10UL)                  /*!< INPEN79 (Bitfield-Mask: 0x01)                         */
33320 #define GPIO_PINCFG79_FNCSEL79_Pos        (0UL)                     /*!< FNCSEL79 (Bit 0)                                      */
33321 #define GPIO_PINCFG79_FNCSEL79_Msk        (0xfUL)                   /*!< FNCSEL79 (Bitfield-Mask: 0x0f)                        */
33322 /* =======================================================  PINCFG80  ======================================================== */
33323 #define GPIO_PINCFG80_FOEN80_Pos          (27UL)                    /*!< FOEN80 (Bit 27)                                       */
33324 #define GPIO_PINCFG80_FOEN80_Msk          (0x8000000UL)             /*!< FOEN80 (Bitfield-Mask: 0x01)                          */
33325 #define GPIO_PINCFG80_FIEN80_Pos          (26UL)                    /*!< FIEN80 (Bit 26)                                       */
33326 #define GPIO_PINCFG80_FIEN80_Msk          (0x4000000UL)             /*!< FIEN80 (Bitfield-Mask: 0x01)                          */
33327 #define GPIO_PINCFG80_NCEPOL80_Pos        (22UL)                    /*!< NCEPOL80 (Bit 22)                                     */
33328 #define GPIO_PINCFG80_NCEPOL80_Msk        (0x400000UL)              /*!< NCEPOL80 (Bitfield-Mask: 0x01)                        */
33329 #define GPIO_PINCFG80_NCESRC80_Pos        (16UL)                    /*!< NCESRC80 (Bit 16)                                     */
33330 #define GPIO_PINCFG80_NCESRC80_Msk        (0x3f0000UL)              /*!< NCESRC80 (Bitfield-Mask: 0x3f)                        */
33331 #define GPIO_PINCFG80_PULLCFG80_Pos       (13UL)                    /*!< PULLCFG80 (Bit 13)                                    */
33332 #define GPIO_PINCFG80_PULLCFG80_Msk       (0xe000UL)                /*!< PULLCFG80 (Bitfield-Mask: 0x07)                       */
33333 #define GPIO_PINCFG80_SR80_Pos            (12UL)                    /*!< SR80 (Bit 12)                                         */
33334 #define GPIO_PINCFG80_SR80_Msk            (0x1000UL)                /*!< SR80 (Bitfield-Mask: 0x01)                            */
33335 #define GPIO_PINCFG80_DS80_Pos            (10UL)                    /*!< DS80 (Bit 10)                                         */
33336 #define GPIO_PINCFG80_DS80_Msk            (0xc00UL)                 /*!< DS80 (Bitfield-Mask: 0x03)                            */
33337 #define GPIO_PINCFG80_OUTCFG80_Pos        (8UL)                     /*!< OUTCFG80 (Bit 8)                                      */
33338 #define GPIO_PINCFG80_OUTCFG80_Msk        (0x300UL)                 /*!< OUTCFG80 (Bitfield-Mask: 0x03)                        */
33339 #define GPIO_PINCFG80_IRPTEN80_Pos        (6UL)                     /*!< IRPTEN80 (Bit 6)                                      */
33340 #define GPIO_PINCFG80_IRPTEN80_Msk        (0xc0UL)                  /*!< IRPTEN80 (Bitfield-Mask: 0x03)                        */
33341 #define GPIO_PINCFG80_RDZERO80_Pos        (5UL)                     /*!< RDZERO80 (Bit 5)                                      */
33342 #define GPIO_PINCFG80_RDZERO80_Msk        (0x20UL)                  /*!< RDZERO80 (Bitfield-Mask: 0x01)                        */
33343 #define GPIO_PINCFG80_INPEN80_Pos         (4UL)                     /*!< INPEN80 (Bit 4)                                       */
33344 #define GPIO_PINCFG80_INPEN80_Msk         (0x10UL)                  /*!< INPEN80 (Bitfield-Mask: 0x01)                         */
33345 #define GPIO_PINCFG80_FNCSEL80_Pos        (0UL)                     /*!< FNCSEL80 (Bit 0)                                      */
33346 #define GPIO_PINCFG80_FNCSEL80_Msk        (0xfUL)                   /*!< FNCSEL80 (Bitfield-Mask: 0x0f)                        */
33347 /* =======================================================  PINCFG81  ======================================================== */
33348 #define GPIO_PINCFG81_FOEN81_Pos          (27UL)                    /*!< FOEN81 (Bit 27)                                       */
33349 #define GPIO_PINCFG81_FOEN81_Msk          (0x8000000UL)             /*!< FOEN81 (Bitfield-Mask: 0x01)                          */
33350 #define GPIO_PINCFG81_FIEN81_Pos          (26UL)                    /*!< FIEN81 (Bit 26)                                       */
33351 #define GPIO_PINCFG81_FIEN81_Msk          (0x4000000UL)             /*!< FIEN81 (Bitfield-Mask: 0x01)                          */
33352 #define GPIO_PINCFG81_NCEPOL81_Pos        (22UL)                    /*!< NCEPOL81 (Bit 22)                                     */
33353 #define GPIO_PINCFG81_NCEPOL81_Msk        (0x400000UL)              /*!< NCEPOL81 (Bitfield-Mask: 0x01)                        */
33354 #define GPIO_PINCFG81_NCESRC81_Pos        (16UL)                    /*!< NCESRC81 (Bit 16)                                     */
33355 #define GPIO_PINCFG81_NCESRC81_Msk        (0x3f0000UL)              /*!< NCESRC81 (Bitfield-Mask: 0x3f)                        */
33356 #define GPIO_PINCFG81_PULLCFG81_Pos       (13UL)                    /*!< PULLCFG81 (Bit 13)                                    */
33357 #define GPIO_PINCFG81_PULLCFG81_Msk       (0xe000UL)                /*!< PULLCFG81 (Bitfield-Mask: 0x07)                       */
33358 #define GPIO_PINCFG81_SR81_Pos            (12UL)                    /*!< SR81 (Bit 12)                                         */
33359 #define GPIO_PINCFG81_SR81_Msk            (0x1000UL)                /*!< SR81 (Bitfield-Mask: 0x01)                            */
33360 #define GPIO_PINCFG81_DS81_Pos            (10UL)                    /*!< DS81 (Bit 10)                                         */
33361 #define GPIO_PINCFG81_DS81_Msk            (0xc00UL)                 /*!< DS81 (Bitfield-Mask: 0x03)                            */
33362 #define GPIO_PINCFG81_OUTCFG81_Pos        (8UL)                     /*!< OUTCFG81 (Bit 8)                                      */
33363 #define GPIO_PINCFG81_OUTCFG81_Msk        (0x300UL)                 /*!< OUTCFG81 (Bitfield-Mask: 0x03)                        */
33364 #define GPIO_PINCFG81_IRPTEN81_Pos        (6UL)                     /*!< IRPTEN81 (Bit 6)                                      */
33365 #define GPIO_PINCFG81_IRPTEN81_Msk        (0xc0UL)                  /*!< IRPTEN81 (Bitfield-Mask: 0x03)                        */
33366 #define GPIO_PINCFG81_RDZERO81_Pos        (5UL)                     /*!< RDZERO81 (Bit 5)                                      */
33367 #define GPIO_PINCFG81_RDZERO81_Msk        (0x20UL)                  /*!< RDZERO81 (Bitfield-Mask: 0x01)                        */
33368 #define GPIO_PINCFG81_INPEN81_Pos         (4UL)                     /*!< INPEN81 (Bit 4)                                       */
33369 #define GPIO_PINCFG81_INPEN81_Msk         (0x10UL)                  /*!< INPEN81 (Bitfield-Mask: 0x01)                         */
33370 #define GPIO_PINCFG81_FNCSEL81_Pos        (0UL)                     /*!< FNCSEL81 (Bit 0)                                      */
33371 #define GPIO_PINCFG81_FNCSEL81_Msk        (0xfUL)                   /*!< FNCSEL81 (Bitfield-Mask: 0x0f)                        */
33372 /* =======================================================  PINCFG82  ======================================================== */
33373 #define GPIO_PINCFG82_FOEN82_Pos          (27UL)                    /*!< FOEN82 (Bit 27)                                       */
33374 #define GPIO_PINCFG82_FOEN82_Msk          (0x8000000UL)             /*!< FOEN82 (Bitfield-Mask: 0x01)                          */
33375 #define GPIO_PINCFG82_FIEN82_Pos          (26UL)                    /*!< FIEN82 (Bit 26)                                       */
33376 #define GPIO_PINCFG82_FIEN82_Msk          (0x4000000UL)             /*!< FIEN82 (Bitfield-Mask: 0x01)                          */
33377 #define GPIO_PINCFG82_NCEPOL82_Pos        (22UL)                    /*!< NCEPOL82 (Bit 22)                                     */
33378 #define GPIO_PINCFG82_NCEPOL82_Msk        (0x400000UL)              /*!< NCEPOL82 (Bitfield-Mask: 0x01)                        */
33379 #define GPIO_PINCFG82_NCESRC82_Pos        (16UL)                    /*!< NCESRC82 (Bit 16)                                     */
33380 #define GPIO_PINCFG82_NCESRC82_Msk        (0x3f0000UL)              /*!< NCESRC82 (Bitfield-Mask: 0x3f)                        */
33381 #define GPIO_PINCFG82_PULLCFG82_Pos       (13UL)                    /*!< PULLCFG82 (Bit 13)                                    */
33382 #define GPIO_PINCFG82_PULLCFG82_Msk       (0xe000UL)                /*!< PULLCFG82 (Bitfield-Mask: 0x07)                       */
33383 #define GPIO_PINCFG82_SR82_Pos            (12UL)                    /*!< SR82 (Bit 12)                                         */
33384 #define GPIO_PINCFG82_SR82_Msk            (0x1000UL)                /*!< SR82 (Bitfield-Mask: 0x01)                            */
33385 #define GPIO_PINCFG82_DS82_Pos            (10UL)                    /*!< DS82 (Bit 10)                                         */
33386 #define GPIO_PINCFG82_DS82_Msk            (0xc00UL)                 /*!< DS82 (Bitfield-Mask: 0x03)                            */
33387 #define GPIO_PINCFG82_OUTCFG82_Pos        (8UL)                     /*!< OUTCFG82 (Bit 8)                                      */
33388 #define GPIO_PINCFG82_OUTCFG82_Msk        (0x300UL)                 /*!< OUTCFG82 (Bitfield-Mask: 0x03)                        */
33389 #define GPIO_PINCFG82_IRPTEN82_Pos        (6UL)                     /*!< IRPTEN82 (Bit 6)                                      */
33390 #define GPIO_PINCFG82_IRPTEN82_Msk        (0xc0UL)                  /*!< IRPTEN82 (Bitfield-Mask: 0x03)                        */
33391 #define GPIO_PINCFG82_RDZERO82_Pos        (5UL)                     /*!< RDZERO82 (Bit 5)                                      */
33392 #define GPIO_PINCFG82_RDZERO82_Msk        (0x20UL)                  /*!< RDZERO82 (Bitfield-Mask: 0x01)                        */
33393 #define GPIO_PINCFG82_INPEN82_Pos         (4UL)                     /*!< INPEN82 (Bit 4)                                       */
33394 #define GPIO_PINCFG82_INPEN82_Msk         (0x10UL)                  /*!< INPEN82 (Bitfield-Mask: 0x01)                         */
33395 #define GPIO_PINCFG82_FNCSEL82_Pos        (0UL)                     /*!< FNCSEL82 (Bit 0)                                      */
33396 #define GPIO_PINCFG82_FNCSEL82_Msk        (0xfUL)                   /*!< FNCSEL82 (Bitfield-Mask: 0x0f)                        */
33397 /* =======================================================  PINCFG83  ======================================================== */
33398 #define GPIO_PINCFG83_FOEN83_Pos          (27UL)                    /*!< FOEN83 (Bit 27)                                       */
33399 #define GPIO_PINCFG83_FOEN83_Msk          (0x8000000UL)             /*!< FOEN83 (Bitfield-Mask: 0x01)                          */
33400 #define GPIO_PINCFG83_FIEN83_Pos          (26UL)                    /*!< FIEN83 (Bit 26)                                       */
33401 #define GPIO_PINCFG83_FIEN83_Msk          (0x4000000UL)             /*!< FIEN83 (Bitfield-Mask: 0x01)                          */
33402 #define GPIO_PINCFG83_NCEPOL83_Pos        (22UL)                    /*!< NCEPOL83 (Bit 22)                                     */
33403 #define GPIO_PINCFG83_NCEPOL83_Msk        (0x400000UL)              /*!< NCEPOL83 (Bitfield-Mask: 0x01)                        */
33404 #define GPIO_PINCFG83_NCESRC83_Pos        (16UL)                    /*!< NCESRC83 (Bit 16)                                     */
33405 #define GPIO_PINCFG83_NCESRC83_Msk        (0x3f0000UL)              /*!< NCESRC83 (Bitfield-Mask: 0x3f)                        */
33406 #define GPIO_PINCFG83_PULLCFG83_Pos       (13UL)                    /*!< PULLCFG83 (Bit 13)                                    */
33407 #define GPIO_PINCFG83_PULLCFG83_Msk       (0xe000UL)                /*!< PULLCFG83 (Bitfield-Mask: 0x07)                       */
33408 #define GPIO_PINCFG83_SR83_Pos            (12UL)                    /*!< SR83 (Bit 12)                                         */
33409 #define GPIO_PINCFG83_SR83_Msk            (0x1000UL)                /*!< SR83 (Bitfield-Mask: 0x01)                            */
33410 #define GPIO_PINCFG83_DS83_Pos            (10UL)                    /*!< DS83 (Bit 10)                                         */
33411 #define GPIO_PINCFG83_DS83_Msk            (0xc00UL)                 /*!< DS83 (Bitfield-Mask: 0x03)                            */
33412 #define GPIO_PINCFG83_OUTCFG83_Pos        (8UL)                     /*!< OUTCFG83 (Bit 8)                                      */
33413 #define GPIO_PINCFG83_OUTCFG83_Msk        (0x300UL)                 /*!< OUTCFG83 (Bitfield-Mask: 0x03)                        */
33414 #define GPIO_PINCFG83_IRPTEN83_Pos        (6UL)                     /*!< IRPTEN83 (Bit 6)                                      */
33415 #define GPIO_PINCFG83_IRPTEN83_Msk        (0xc0UL)                  /*!< IRPTEN83 (Bitfield-Mask: 0x03)                        */
33416 #define GPIO_PINCFG83_RDZERO83_Pos        (5UL)                     /*!< RDZERO83 (Bit 5)                                      */
33417 #define GPIO_PINCFG83_RDZERO83_Msk        (0x20UL)                  /*!< RDZERO83 (Bitfield-Mask: 0x01)                        */
33418 #define GPIO_PINCFG83_INPEN83_Pos         (4UL)                     /*!< INPEN83 (Bit 4)                                       */
33419 #define GPIO_PINCFG83_INPEN83_Msk         (0x10UL)                  /*!< INPEN83 (Bitfield-Mask: 0x01)                         */
33420 #define GPIO_PINCFG83_FNCSEL83_Pos        (0UL)                     /*!< FNCSEL83 (Bit 0)                                      */
33421 #define GPIO_PINCFG83_FNCSEL83_Msk        (0xfUL)                   /*!< FNCSEL83 (Bitfield-Mask: 0x0f)                        */
33422 /* =======================================================  PINCFG84  ======================================================== */
33423 #define GPIO_PINCFG84_FOEN84_Pos          (27UL)                    /*!< FOEN84 (Bit 27)                                       */
33424 #define GPIO_PINCFG84_FOEN84_Msk          (0x8000000UL)             /*!< FOEN84 (Bitfield-Mask: 0x01)                          */
33425 #define GPIO_PINCFG84_FIEN84_Pos          (26UL)                    /*!< FIEN84 (Bit 26)                                       */
33426 #define GPIO_PINCFG84_FIEN84_Msk          (0x4000000UL)             /*!< FIEN84 (Bitfield-Mask: 0x01)                          */
33427 #define GPIO_PINCFG84_NCEPOL84_Pos        (22UL)                    /*!< NCEPOL84 (Bit 22)                                     */
33428 #define GPIO_PINCFG84_NCEPOL84_Msk        (0x400000UL)              /*!< NCEPOL84 (Bitfield-Mask: 0x01)                        */
33429 #define GPIO_PINCFG84_NCESRC84_Pos        (16UL)                    /*!< NCESRC84 (Bit 16)                                     */
33430 #define GPIO_PINCFG84_NCESRC84_Msk        (0x3f0000UL)              /*!< NCESRC84 (Bitfield-Mask: 0x3f)                        */
33431 #define GPIO_PINCFG84_PULLCFG84_Pos       (13UL)                    /*!< PULLCFG84 (Bit 13)                                    */
33432 #define GPIO_PINCFG84_PULLCFG84_Msk       (0xe000UL)                /*!< PULLCFG84 (Bitfield-Mask: 0x07)                       */
33433 #define GPIO_PINCFG84_SR84_Pos            (12UL)                    /*!< SR84 (Bit 12)                                         */
33434 #define GPIO_PINCFG84_SR84_Msk            (0x1000UL)                /*!< SR84 (Bitfield-Mask: 0x01)                            */
33435 #define GPIO_PINCFG84_DS84_Pos            (10UL)                    /*!< DS84 (Bit 10)                                         */
33436 #define GPIO_PINCFG84_DS84_Msk            (0xc00UL)                 /*!< DS84 (Bitfield-Mask: 0x03)                            */
33437 #define GPIO_PINCFG84_OUTCFG84_Pos        (8UL)                     /*!< OUTCFG84 (Bit 8)                                      */
33438 #define GPIO_PINCFG84_OUTCFG84_Msk        (0x300UL)                 /*!< OUTCFG84 (Bitfield-Mask: 0x03)                        */
33439 #define GPIO_PINCFG84_IRPTEN84_Pos        (6UL)                     /*!< IRPTEN84 (Bit 6)                                      */
33440 #define GPIO_PINCFG84_IRPTEN84_Msk        (0xc0UL)                  /*!< IRPTEN84 (Bitfield-Mask: 0x03)                        */
33441 #define GPIO_PINCFG84_RDZERO84_Pos        (5UL)                     /*!< RDZERO84 (Bit 5)                                      */
33442 #define GPIO_PINCFG84_RDZERO84_Msk        (0x20UL)                  /*!< RDZERO84 (Bitfield-Mask: 0x01)                        */
33443 #define GPIO_PINCFG84_INPEN84_Pos         (4UL)                     /*!< INPEN84 (Bit 4)                                       */
33444 #define GPIO_PINCFG84_INPEN84_Msk         (0x10UL)                  /*!< INPEN84 (Bitfield-Mask: 0x01)                         */
33445 #define GPIO_PINCFG84_FNCSEL84_Pos        (0UL)                     /*!< FNCSEL84 (Bit 0)                                      */
33446 #define GPIO_PINCFG84_FNCSEL84_Msk        (0xfUL)                   /*!< FNCSEL84 (Bitfield-Mask: 0x0f)                        */
33447 /* =======================================================  PINCFG85  ======================================================== */
33448 #define GPIO_PINCFG85_FOEN85_Pos          (27UL)                    /*!< FOEN85 (Bit 27)                                       */
33449 #define GPIO_PINCFG85_FOEN85_Msk          (0x8000000UL)             /*!< FOEN85 (Bitfield-Mask: 0x01)                          */
33450 #define GPIO_PINCFG85_FIEN85_Pos          (26UL)                    /*!< FIEN85 (Bit 26)                                       */
33451 #define GPIO_PINCFG85_FIEN85_Msk          (0x4000000UL)             /*!< FIEN85 (Bitfield-Mask: 0x01)                          */
33452 #define GPIO_PINCFG85_NCEPOL85_Pos        (22UL)                    /*!< NCEPOL85 (Bit 22)                                     */
33453 #define GPIO_PINCFG85_NCEPOL85_Msk        (0x400000UL)              /*!< NCEPOL85 (Bitfield-Mask: 0x01)                        */
33454 #define GPIO_PINCFG85_NCESRC85_Pos        (16UL)                    /*!< NCESRC85 (Bit 16)                                     */
33455 #define GPIO_PINCFG85_NCESRC85_Msk        (0x3f0000UL)              /*!< NCESRC85 (Bitfield-Mask: 0x3f)                        */
33456 #define GPIO_PINCFG85_PULLCFG85_Pos       (13UL)                    /*!< PULLCFG85 (Bit 13)                                    */
33457 #define GPIO_PINCFG85_PULLCFG85_Msk       (0xe000UL)                /*!< PULLCFG85 (Bitfield-Mask: 0x07)                       */
33458 #define GPIO_PINCFG85_SR85_Pos            (12UL)                    /*!< SR85 (Bit 12)                                         */
33459 #define GPIO_PINCFG85_SR85_Msk            (0x1000UL)                /*!< SR85 (Bitfield-Mask: 0x01)                            */
33460 #define GPIO_PINCFG85_DS85_Pos            (10UL)                    /*!< DS85 (Bit 10)                                         */
33461 #define GPIO_PINCFG85_DS85_Msk            (0xc00UL)                 /*!< DS85 (Bitfield-Mask: 0x03)                            */
33462 #define GPIO_PINCFG85_OUTCFG85_Pos        (8UL)                     /*!< OUTCFG85 (Bit 8)                                      */
33463 #define GPIO_PINCFG85_OUTCFG85_Msk        (0x300UL)                 /*!< OUTCFG85 (Bitfield-Mask: 0x03)                        */
33464 #define GPIO_PINCFG85_IRPTEN85_Pos        (6UL)                     /*!< IRPTEN85 (Bit 6)                                      */
33465 #define GPIO_PINCFG85_IRPTEN85_Msk        (0xc0UL)                  /*!< IRPTEN85 (Bitfield-Mask: 0x03)                        */
33466 #define GPIO_PINCFG85_RDZERO85_Pos        (5UL)                     /*!< RDZERO85 (Bit 5)                                      */
33467 #define GPIO_PINCFG85_RDZERO85_Msk        (0x20UL)                  /*!< RDZERO85 (Bitfield-Mask: 0x01)                        */
33468 #define GPIO_PINCFG85_INPEN85_Pos         (4UL)                     /*!< INPEN85 (Bit 4)                                       */
33469 #define GPIO_PINCFG85_INPEN85_Msk         (0x10UL)                  /*!< INPEN85 (Bitfield-Mask: 0x01)                         */
33470 #define GPIO_PINCFG85_FNCSEL85_Pos        (0UL)                     /*!< FNCSEL85 (Bit 0)                                      */
33471 #define GPIO_PINCFG85_FNCSEL85_Msk        (0xfUL)                   /*!< FNCSEL85 (Bitfield-Mask: 0x0f)                        */
33472 /* =======================================================  PINCFG86  ======================================================== */
33473 #define GPIO_PINCFG86_FOEN86_Pos          (27UL)                    /*!< FOEN86 (Bit 27)                                       */
33474 #define GPIO_PINCFG86_FOEN86_Msk          (0x8000000UL)             /*!< FOEN86 (Bitfield-Mask: 0x01)                          */
33475 #define GPIO_PINCFG86_FIEN86_Pos          (26UL)                    /*!< FIEN86 (Bit 26)                                       */
33476 #define GPIO_PINCFG86_FIEN86_Msk          (0x4000000UL)             /*!< FIEN86 (Bitfield-Mask: 0x01)                          */
33477 #define GPIO_PINCFG86_NCEPOL86_Pos        (22UL)                    /*!< NCEPOL86 (Bit 22)                                     */
33478 #define GPIO_PINCFG86_NCEPOL86_Msk        (0x400000UL)              /*!< NCEPOL86 (Bitfield-Mask: 0x01)                        */
33479 #define GPIO_PINCFG86_NCESRC86_Pos        (16UL)                    /*!< NCESRC86 (Bit 16)                                     */
33480 #define GPIO_PINCFG86_NCESRC86_Msk        (0x3f0000UL)              /*!< NCESRC86 (Bitfield-Mask: 0x3f)                        */
33481 #define GPIO_PINCFG86_PULLCFG86_Pos       (13UL)                    /*!< PULLCFG86 (Bit 13)                                    */
33482 #define GPIO_PINCFG86_PULLCFG86_Msk       (0xe000UL)                /*!< PULLCFG86 (Bitfield-Mask: 0x07)                       */
33483 #define GPIO_PINCFG86_SR86_Pos            (12UL)                    /*!< SR86 (Bit 12)                                         */
33484 #define GPIO_PINCFG86_SR86_Msk            (0x1000UL)                /*!< SR86 (Bitfield-Mask: 0x01)                            */
33485 #define GPIO_PINCFG86_DS86_Pos            (10UL)                    /*!< DS86 (Bit 10)                                         */
33486 #define GPIO_PINCFG86_DS86_Msk            (0xc00UL)                 /*!< DS86 (Bitfield-Mask: 0x03)                            */
33487 #define GPIO_PINCFG86_OUTCFG86_Pos        (8UL)                     /*!< OUTCFG86 (Bit 8)                                      */
33488 #define GPIO_PINCFG86_OUTCFG86_Msk        (0x300UL)                 /*!< OUTCFG86 (Bitfield-Mask: 0x03)                        */
33489 #define GPIO_PINCFG86_IRPTEN86_Pos        (6UL)                     /*!< IRPTEN86 (Bit 6)                                      */
33490 #define GPIO_PINCFG86_IRPTEN86_Msk        (0xc0UL)                  /*!< IRPTEN86 (Bitfield-Mask: 0x03)                        */
33491 #define GPIO_PINCFG86_RDZERO86_Pos        (5UL)                     /*!< RDZERO86 (Bit 5)                                      */
33492 #define GPIO_PINCFG86_RDZERO86_Msk        (0x20UL)                  /*!< RDZERO86 (Bitfield-Mask: 0x01)                        */
33493 #define GPIO_PINCFG86_INPEN86_Pos         (4UL)                     /*!< INPEN86 (Bit 4)                                       */
33494 #define GPIO_PINCFG86_INPEN86_Msk         (0x10UL)                  /*!< INPEN86 (Bitfield-Mask: 0x01)                         */
33495 #define GPIO_PINCFG86_FNCSEL86_Pos        (0UL)                     /*!< FNCSEL86 (Bit 0)                                      */
33496 #define GPIO_PINCFG86_FNCSEL86_Msk        (0xfUL)                   /*!< FNCSEL86 (Bitfield-Mask: 0x0f)                        */
33497 /* =======================================================  PINCFG87  ======================================================== */
33498 #define GPIO_PINCFG87_FOEN87_Pos          (27UL)                    /*!< FOEN87 (Bit 27)                                       */
33499 #define GPIO_PINCFG87_FOEN87_Msk          (0x8000000UL)             /*!< FOEN87 (Bitfield-Mask: 0x01)                          */
33500 #define GPIO_PINCFG87_FIEN87_Pos          (26UL)                    /*!< FIEN87 (Bit 26)                                       */
33501 #define GPIO_PINCFG87_FIEN87_Msk          (0x4000000UL)             /*!< FIEN87 (Bitfield-Mask: 0x01)                          */
33502 #define GPIO_PINCFG87_NCEPOL87_Pos        (22UL)                    /*!< NCEPOL87 (Bit 22)                                     */
33503 #define GPIO_PINCFG87_NCEPOL87_Msk        (0x400000UL)              /*!< NCEPOL87 (Bitfield-Mask: 0x01)                        */
33504 #define GPIO_PINCFG87_NCESRC87_Pos        (16UL)                    /*!< NCESRC87 (Bit 16)                                     */
33505 #define GPIO_PINCFG87_NCESRC87_Msk        (0x3f0000UL)              /*!< NCESRC87 (Bitfield-Mask: 0x3f)                        */
33506 #define GPIO_PINCFG87_PULLCFG87_Pos       (13UL)                    /*!< PULLCFG87 (Bit 13)                                    */
33507 #define GPIO_PINCFG87_PULLCFG87_Msk       (0xe000UL)                /*!< PULLCFG87 (Bitfield-Mask: 0x07)                       */
33508 #define GPIO_PINCFG87_SR87_Pos            (12UL)                    /*!< SR87 (Bit 12)                                         */
33509 #define GPIO_PINCFG87_SR87_Msk            (0x1000UL)                /*!< SR87 (Bitfield-Mask: 0x01)                            */
33510 #define GPIO_PINCFG87_DS87_Pos            (10UL)                    /*!< DS87 (Bit 10)                                         */
33511 #define GPIO_PINCFG87_DS87_Msk            (0xc00UL)                 /*!< DS87 (Bitfield-Mask: 0x03)                            */
33512 #define GPIO_PINCFG87_OUTCFG87_Pos        (8UL)                     /*!< OUTCFG87 (Bit 8)                                      */
33513 #define GPIO_PINCFG87_OUTCFG87_Msk        (0x300UL)                 /*!< OUTCFG87 (Bitfield-Mask: 0x03)                        */
33514 #define GPIO_PINCFG87_IRPTEN87_Pos        (6UL)                     /*!< IRPTEN87 (Bit 6)                                      */
33515 #define GPIO_PINCFG87_IRPTEN87_Msk        (0xc0UL)                  /*!< IRPTEN87 (Bitfield-Mask: 0x03)                        */
33516 #define GPIO_PINCFG87_RDZERO87_Pos        (5UL)                     /*!< RDZERO87 (Bit 5)                                      */
33517 #define GPIO_PINCFG87_RDZERO87_Msk        (0x20UL)                  /*!< RDZERO87 (Bitfield-Mask: 0x01)                        */
33518 #define GPIO_PINCFG87_INPEN87_Pos         (4UL)                     /*!< INPEN87 (Bit 4)                                       */
33519 #define GPIO_PINCFG87_INPEN87_Msk         (0x10UL)                  /*!< INPEN87 (Bitfield-Mask: 0x01)                         */
33520 #define GPIO_PINCFG87_FNCSEL87_Pos        (0UL)                     /*!< FNCSEL87 (Bit 0)                                      */
33521 #define GPIO_PINCFG87_FNCSEL87_Msk        (0xfUL)                   /*!< FNCSEL87 (Bitfield-Mask: 0x0f)                        */
33522 /* =======================================================  PINCFG88  ======================================================== */
33523 #define GPIO_PINCFG88_FOEN88_Pos          (27UL)                    /*!< FOEN88 (Bit 27)                                       */
33524 #define GPIO_PINCFG88_FOEN88_Msk          (0x8000000UL)             /*!< FOEN88 (Bitfield-Mask: 0x01)                          */
33525 #define GPIO_PINCFG88_FIEN88_Pos          (26UL)                    /*!< FIEN88 (Bit 26)                                       */
33526 #define GPIO_PINCFG88_FIEN88_Msk          (0x4000000UL)             /*!< FIEN88 (Bitfield-Mask: 0x01)                          */
33527 #define GPIO_PINCFG88_NCEPOL88_Pos        (22UL)                    /*!< NCEPOL88 (Bit 22)                                     */
33528 #define GPIO_PINCFG88_NCEPOL88_Msk        (0x400000UL)              /*!< NCEPOL88 (Bitfield-Mask: 0x01)                        */
33529 #define GPIO_PINCFG88_NCESRC88_Pos        (16UL)                    /*!< NCESRC88 (Bit 16)                                     */
33530 #define GPIO_PINCFG88_NCESRC88_Msk        (0x3f0000UL)              /*!< NCESRC88 (Bitfield-Mask: 0x3f)                        */
33531 #define GPIO_PINCFG88_PULLCFG88_Pos       (13UL)                    /*!< PULLCFG88 (Bit 13)                                    */
33532 #define GPIO_PINCFG88_PULLCFG88_Msk       (0xe000UL)                /*!< PULLCFG88 (Bitfield-Mask: 0x07)                       */
33533 #define GPIO_PINCFG88_SR88_Pos            (12UL)                    /*!< SR88 (Bit 12)                                         */
33534 #define GPIO_PINCFG88_SR88_Msk            (0x1000UL)                /*!< SR88 (Bitfield-Mask: 0x01)                            */
33535 #define GPIO_PINCFG88_DS88_Pos            (10UL)                    /*!< DS88 (Bit 10)                                         */
33536 #define GPIO_PINCFG88_DS88_Msk            (0xc00UL)                 /*!< DS88 (Bitfield-Mask: 0x03)                            */
33537 #define GPIO_PINCFG88_OUTCFG88_Pos        (8UL)                     /*!< OUTCFG88 (Bit 8)                                      */
33538 #define GPIO_PINCFG88_OUTCFG88_Msk        (0x300UL)                 /*!< OUTCFG88 (Bitfield-Mask: 0x03)                        */
33539 #define GPIO_PINCFG88_IRPTEN88_Pos        (6UL)                     /*!< IRPTEN88 (Bit 6)                                      */
33540 #define GPIO_PINCFG88_IRPTEN88_Msk        (0xc0UL)                  /*!< IRPTEN88 (Bitfield-Mask: 0x03)                        */
33541 #define GPIO_PINCFG88_RDZERO88_Pos        (5UL)                     /*!< RDZERO88 (Bit 5)                                      */
33542 #define GPIO_PINCFG88_RDZERO88_Msk        (0x20UL)                  /*!< RDZERO88 (Bitfield-Mask: 0x01)                        */
33543 #define GPIO_PINCFG88_INPEN88_Pos         (4UL)                     /*!< INPEN88 (Bit 4)                                       */
33544 #define GPIO_PINCFG88_INPEN88_Msk         (0x10UL)                  /*!< INPEN88 (Bitfield-Mask: 0x01)                         */
33545 #define GPIO_PINCFG88_FNCSEL88_Pos        (0UL)                     /*!< FNCSEL88 (Bit 0)                                      */
33546 #define GPIO_PINCFG88_FNCSEL88_Msk        (0xfUL)                   /*!< FNCSEL88 (Bitfield-Mask: 0x0f)                        */
33547 /* =======================================================  PINCFG89  ======================================================== */
33548 #define GPIO_PINCFG89_FOEN89_Pos          (27UL)                    /*!< FOEN89 (Bit 27)                                       */
33549 #define GPIO_PINCFG89_FOEN89_Msk          (0x8000000UL)             /*!< FOEN89 (Bitfield-Mask: 0x01)                          */
33550 #define GPIO_PINCFG89_FIEN89_Pos          (26UL)                    /*!< FIEN89 (Bit 26)                                       */
33551 #define GPIO_PINCFG89_FIEN89_Msk          (0x4000000UL)             /*!< FIEN89 (Bitfield-Mask: 0x01)                          */
33552 #define GPIO_PINCFG89_NCEPOL89_Pos        (22UL)                    /*!< NCEPOL89 (Bit 22)                                     */
33553 #define GPIO_PINCFG89_NCEPOL89_Msk        (0x400000UL)              /*!< NCEPOL89 (Bitfield-Mask: 0x01)                        */
33554 #define GPIO_PINCFG89_NCESRC89_Pos        (16UL)                    /*!< NCESRC89 (Bit 16)                                     */
33555 #define GPIO_PINCFG89_NCESRC89_Msk        (0x3f0000UL)              /*!< NCESRC89 (Bitfield-Mask: 0x3f)                        */
33556 #define GPIO_PINCFG89_PULLCFG89_Pos       (13UL)                    /*!< PULLCFG89 (Bit 13)                                    */
33557 #define GPIO_PINCFG89_PULLCFG89_Msk       (0xe000UL)                /*!< PULLCFG89 (Bitfield-Mask: 0x07)                       */
33558 #define GPIO_PINCFG89_SR89_Pos            (12UL)                    /*!< SR89 (Bit 12)                                         */
33559 #define GPIO_PINCFG89_SR89_Msk            (0x1000UL)                /*!< SR89 (Bitfield-Mask: 0x01)                            */
33560 #define GPIO_PINCFG89_DS89_Pos            (10UL)                    /*!< DS89 (Bit 10)                                         */
33561 #define GPIO_PINCFG89_DS89_Msk            (0xc00UL)                 /*!< DS89 (Bitfield-Mask: 0x03)                            */
33562 #define GPIO_PINCFG89_OUTCFG89_Pos        (8UL)                     /*!< OUTCFG89 (Bit 8)                                      */
33563 #define GPIO_PINCFG89_OUTCFG89_Msk        (0x300UL)                 /*!< OUTCFG89 (Bitfield-Mask: 0x03)                        */
33564 #define GPIO_PINCFG89_IRPTEN89_Pos        (6UL)                     /*!< IRPTEN89 (Bit 6)                                      */
33565 #define GPIO_PINCFG89_IRPTEN89_Msk        (0xc0UL)                  /*!< IRPTEN89 (Bitfield-Mask: 0x03)                        */
33566 #define GPIO_PINCFG89_RDZERO89_Pos        (5UL)                     /*!< RDZERO89 (Bit 5)                                      */
33567 #define GPIO_PINCFG89_RDZERO89_Msk        (0x20UL)                  /*!< RDZERO89 (Bitfield-Mask: 0x01)                        */
33568 #define GPIO_PINCFG89_INPEN89_Pos         (4UL)                     /*!< INPEN89 (Bit 4)                                       */
33569 #define GPIO_PINCFG89_INPEN89_Msk         (0x10UL)                  /*!< INPEN89 (Bitfield-Mask: 0x01)                         */
33570 #define GPIO_PINCFG89_FNCSEL89_Pos        (0UL)                     /*!< FNCSEL89 (Bit 0)                                      */
33571 #define GPIO_PINCFG89_FNCSEL89_Msk        (0xfUL)                   /*!< FNCSEL89 (Bitfield-Mask: 0x0f)                        */
33572 /* =======================================================  PINCFG90  ======================================================== */
33573 #define GPIO_PINCFG90_FOEN90_Pos          (27UL)                    /*!< FOEN90 (Bit 27)                                       */
33574 #define GPIO_PINCFG90_FOEN90_Msk          (0x8000000UL)             /*!< FOEN90 (Bitfield-Mask: 0x01)                          */
33575 #define GPIO_PINCFG90_FIEN90_Pos          (26UL)                    /*!< FIEN90 (Bit 26)                                       */
33576 #define GPIO_PINCFG90_FIEN90_Msk          (0x4000000UL)             /*!< FIEN90 (Bitfield-Mask: 0x01)                          */
33577 #define GPIO_PINCFG90_NCEPOL90_Pos        (22UL)                    /*!< NCEPOL90 (Bit 22)                                     */
33578 #define GPIO_PINCFG90_NCEPOL90_Msk        (0x400000UL)              /*!< NCEPOL90 (Bitfield-Mask: 0x01)                        */
33579 #define GPIO_PINCFG90_NCESRC90_Pos        (16UL)                    /*!< NCESRC90 (Bit 16)                                     */
33580 #define GPIO_PINCFG90_NCESRC90_Msk        (0x3f0000UL)              /*!< NCESRC90 (Bitfield-Mask: 0x3f)                        */
33581 #define GPIO_PINCFG90_PULLCFG90_Pos       (13UL)                    /*!< PULLCFG90 (Bit 13)                                    */
33582 #define GPIO_PINCFG90_PULLCFG90_Msk       (0xe000UL)                /*!< PULLCFG90 (Bitfield-Mask: 0x07)                       */
33583 #define GPIO_PINCFG90_SR90_Pos            (12UL)                    /*!< SR90 (Bit 12)                                         */
33584 #define GPIO_PINCFG90_SR90_Msk            (0x1000UL)                /*!< SR90 (Bitfield-Mask: 0x01)                            */
33585 #define GPIO_PINCFG90_DS90_Pos            (10UL)                    /*!< DS90 (Bit 10)                                         */
33586 #define GPIO_PINCFG90_DS90_Msk            (0xc00UL)                 /*!< DS90 (Bitfield-Mask: 0x03)                            */
33587 #define GPIO_PINCFG90_OUTCFG90_Pos        (8UL)                     /*!< OUTCFG90 (Bit 8)                                      */
33588 #define GPIO_PINCFG90_OUTCFG90_Msk        (0x300UL)                 /*!< OUTCFG90 (Bitfield-Mask: 0x03)                        */
33589 #define GPIO_PINCFG90_IRPTEN90_Pos        (6UL)                     /*!< IRPTEN90 (Bit 6)                                      */
33590 #define GPIO_PINCFG90_IRPTEN90_Msk        (0xc0UL)                  /*!< IRPTEN90 (Bitfield-Mask: 0x03)                        */
33591 #define GPIO_PINCFG90_RDZERO90_Pos        (5UL)                     /*!< RDZERO90 (Bit 5)                                      */
33592 #define GPIO_PINCFG90_RDZERO90_Msk        (0x20UL)                  /*!< RDZERO90 (Bitfield-Mask: 0x01)                        */
33593 #define GPIO_PINCFG90_INPEN90_Pos         (4UL)                     /*!< INPEN90 (Bit 4)                                       */
33594 #define GPIO_PINCFG90_INPEN90_Msk         (0x10UL)                  /*!< INPEN90 (Bitfield-Mask: 0x01)                         */
33595 #define GPIO_PINCFG90_FNCSEL90_Pos        (0UL)                     /*!< FNCSEL90 (Bit 0)                                      */
33596 #define GPIO_PINCFG90_FNCSEL90_Msk        (0xfUL)                   /*!< FNCSEL90 (Bitfield-Mask: 0x0f)                        */
33597 /* =======================================================  PINCFG91  ======================================================== */
33598 #define GPIO_PINCFG91_FOEN91_Pos          (27UL)                    /*!< FOEN91 (Bit 27)                                       */
33599 #define GPIO_PINCFG91_FOEN91_Msk          (0x8000000UL)             /*!< FOEN91 (Bitfield-Mask: 0x01)                          */
33600 #define GPIO_PINCFG91_FIEN91_Pos          (26UL)                    /*!< FIEN91 (Bit 26)                                       */
33601 #define GPIO_PINCFG91_FIEN91_Msk          (0x4000000UL)             /*!< FIEN91 (Bitfield-Mask: 0x01)                          */
33602 #define GPIO_PINCFG91_NCEPOL91_Pos        (22UL)                    /*!< NCEPOL91 (Bit 22)                                     */
33603 #define GPIO_PINCFG91_NCEPOL91_Msk        (0x400000UL)              /*!< NCEPOL91 (Bitfield-Mask: 0x01)                        */
33604 #define GPIO_PINCFG91_NCESRC91_Pos        (16UL)                    /*!< NCESRC91 (Bit 16)                                     */
33605 #define GPIO_PINCFG91_NCESRC91_Msk        (0x3f0000UL)              /*!< NCESRC91 (Bitfield-Mask: 0x3f)                        */
33606 #define GPIO_PINCFG91_PULLCFG91_Pos       (13UL)                    /*!< PULLCFG91 (Bit 13)                                    */
33607 #define GPIO_PINCFG91_PULLCFG91_Msk       (0xe000UL)                /*!< PULLCFG91 (Bitfield-Mask: 0x07)                       */
33608 #define GPIO_PINCFG91_SR91_Pos            (12UL)                    /*!< SR91 (Bit 12)                                         */
33609 #define GPIO_PINCFG91_SR91_Msk            (0x1000UL)                /*!< SR91 (Bitfield-Mask: 0x01)                            */
33610 #define GPIO_PINCFG91_DS91_Pos            (10UL)                    /*!< DS91 (Bit 10)                                         */
33611 #define GPIO_PINCFG91_DS91_Msk            (0xc00UL)                 /*!< DS91 (Bitfield-Mask: 0x03)                            */
33612 #define GPIO_PINCFG91_OUTCFG91_Pos        (8UL)                     /*!< OUTCFG91 (Bit 8)                                      */
33613 #define GPIO_PINCFG91_OUTCFG91_Msk        (0x300UL)                 /*!< OUTCFG91 (Bitfield-Mask: 0x03)                        */
33614 #define GPIO_PINCFG91_IRPTEN91_Pos        (6UL)                     /*!< IRPTEN91 (Bit 6)                                      */
33615 #define GPIO_PINCFG91_IRPTEN91_Msk        (0xc0UL)                  /*!< IRPTEN91 (Bitfield-Mask: 0x03)                        */
33616 #define GPIO_PINCFG91_RDZERO91_Pos        (5UL)                     /*!< RDZERO91 (Bit 5)                                      */
33617 #define GPIO_PINCFG91_RDZERO91_Msk        (0x20UL)                  /*!< RDZERO91 (Bitfield-Mask: 0x01)                        */
33618 #define GPIO_PINCFG91_INPEN91_Pos         (4UL)                     /*!< INPEN91 (Bit 4)                                       */
33619 #define GPIO_PINCFG91_INPEN91_Msk         (0x10UL)                  /*!< INPEN91 (Bitfield-Mask: 0x01)                         */
33620 #define GPIO_PINCFG91_FNCSEL91_Pos        (0UL)                     /*!< FNCSEL91 (Bit 0)                                      */
33621 #define GPIO_PINCFG91_FNCSEL91_Msk        (0xfUL)                   /*!< FNCSEL91 (Bitfield-Mask: 0x0f)                        */
33622 /* =======================================================  PINCFG92  ======================================================== */
33623 #define GPIO_PINCFG92_FOEN92_Pos          (27UL)                    /*!< FOEN92 (Bit 27)                                       */
33624 #define GPIO_PINCFG92_FOEN92_Msk          (0x8000000UL)             /*!< FOEN92 (Bitfield-Mask: 0x01)                          */
33625 #define GPIO_PINCFG92_FIEN92_Pos          (26UL)                    /*!< FIEN92 (Bit 26)                                       */
33626 #define GPIO_PINCFG92_FIEN92_Msk          (0x4000000UL)             /*!< FIEN92 (Bitfield-Mask: 0x01)                          */
33627 #define GPIO_PINCFG92_NCEPOL92_Pos        (22UL)                    /*!< NCEPOL92 (Bit 22)                                     */
33628 #define GPIO_PINCFG92_NCEPOL92_Msk        (0x400000UL)              /*!< NCEPOL92 (Bitfield-Mask: 0x01)                        */
33629 #define GPIO_PINCFG92_NCESRC92_Pos        (16UL)                    /*!< NCESRC92 (Bit 16)                                     */
33630 #define GPIO_PINCFG92_NCESRC92_Msk        (0x3f0000UL)              /*!< NCESRC92 (Bitfield-Mask: 0x3f)                        */
33631 #define GPIO_PINCFG92_PULLCFG92_Pos       (13UL)                    /*!< PULLCFG92 (Bit 13)                                    */
33632 #define GPIO_PINCFG92_PULLCFG92_Msk       (0xe000UL)                /*!< PULLCFG92 (Bitfield-Mask: 0x07)                       */
33633 #define GPIO_PINCFG92_SR92_Pos            (12UL)                    /*!< SR92 (Bit 12)                                         */
33634 #define GPIO_PINCFG92_SR92_Msk            (0x1000UL)                /*!< SR92 (Bitfield-Mask: 0x01)                            */
33635 #define GPIO_PINCFG92_DS92_Pos            (10UL)                    /*!< DS92 (Bit 10)                                         */
33636 #define GPIO_PINCFG92_DS92_Msk            (0xc00UL)                 /*!< DS92 (Bitfield-Mask: 0x03)                            */
33637 #define GPIO_PINCFG92_OUTCFG92_Pos        (8UL)                     /*!< OUTCFG92 (Bit 8)                                      */
33638 #define GPIO_PINCFG92_OUTCFG92_Msk        (0x300UL)                 /*!< OUTCFG92 (Bitfield-Mask: 0x03)                        */
33639 #define GPIO_PINCFG92_IRPTEN92_Pos        (6UL)                     /*!< IRPTEN92 (Bit 6)                                      */
33640 #define GPIO_PINCFG92_IRPTEN92_Msk        (0xc0UL)                  /*!< IRPTEN92 (Bitfield-Mask: 0x03)                        */
33641 #define GPIO_PINCFG92_RDZERO92_Pos        (5UL)                     /*!< RDZERO92 (Bit 5)                                      */
33642 #define GPIO_PINCFG92_RDZERO92_Msk        (0x20UL)                  /*!< RDZERO92 (Bitfield-Mask: 0x01)                        */
33643 #define GPIO_PINCFG92_INPEN92_Pos         (4UL)                     /*!< INPEN92 (Bit 4)                                       */
33644 #define GPIO_PINCFG92_INPEN92_Msk         (0x10UL)                  /*!< INPEN92 (Bitfield-Mask: 0x01)                         */
33645 #define GPIO_PINCFG92_FNCSEL92_Pos        (0UL)                     /*!< FNCSEL92 (Bit 0)                                      */
33646 #define GPIO_PINCFG92_FNCSEL92_Msk        (0xfUL)                   /*!< FNCSEL92 (Bitfield-Mask: 0x0f)                        */
33647 /* =======================================================  PINCFG93  ======================================================== */
33648 #define GPIO_PINCFG93_FOEN93_Pos          (27UL)                    /*!< FOEN93 (Bit 27)                                       */
33649 #define GPIO_PINCFG93_FOEN93_Msk          (0x8000000UL)             /*!< FOEN93 (Bitfield-Mask: 0x01)                          */
33650 #define GPIO_PINCFG93_FIEN93_Pos          (26UL)                    /*!< FIEN93 (Bit 26)                                       */
33651 #define GPIO_PINCFG93_FIEN93_Msk          (0x4000000UL)             /*!< FIEN93 (Bitfield-Mask: 0x01)                          */
33652 #define GPIO_PINCFG93_NCEPOL93_Pos        (22UL)                    /*!< NCEPOL93 (Bit 22)                                     */
33653 #define GPIO_PINCFG93_NCEPOL93_Msk        (0x400000UL)              /*!< NCEPOL93 (Bitfield-Mask: 0x01)                        */
33654 #define GPIO_PINCFG93_NCESRC93_Pos        (16UL)                    /*!< NCESRC93 (Bit 16)                                     */
33655 #define GPIO_PINCFG93_NCESRC93_Msk        (0x3f0000UL)              /*!< NCESRC93 (Bitfield-Mask: 0x3f)                        */
33656 #define GPIO_PINCFG93_PULLCFG93_Pos       (13UL)                    /*!< PULLCFG93 (Bit 13)                                    */
33657 #define GPIO_PINCFG93_PULLCFG93_Msk       (0xe000UL)                /*!< PULLCFG93 (Bitfield-Mask: 0x07)                       */
33658 #define GPIO_PINCFG93_SR93_Pos            (12UL)                    /*!< SR93 (Bit 12)                                         */
33659 #define GPIO_PINCFG93_SR93_Msk            (0x1000UL)                /*!< SR93 (Bitfield-Mask: 0x01)                            */
33660 #define GPIO_PINCFG93_DS93_Pos            (10UL)                    /*!< DS93 (Bit 10)                                         */
33661 #define GPIO_PINCFG93_DS93_Msk            (0xc00UL)                 /*!< DS93 (Bitfield-Mask: 0x03)                            */
33662 #define GPIO_PINCFG93_OUTCFG93_Pos        (8UL)                     /*!< OUTCFG93 (Bit 8)                                      */
33663 #define GPIO_PINCFG93_OUTCFG93_Msk        (0x300UL)                 /*!< OUTCFG93 (Bitfield-Mask: 0x03)                        */
33664 #define GPIO_PINCFG93_IRPTEN93_Pos        (6UL)                     /*!< IRPTEN93 (Bit 6)                                      */
33665 #define GPIO_PINCFG93_IRPTEN93_Msk        (0xc0UL)                  /*!< IRPTEN93 (Bitfield-Mask: 0x03)                        */
33666 #define GPIO_PINCFG93_RDZERO93_Pos        (5UL)                     /*!< RDZERO93 (Bit 5)                                      */
33667 #define GPIO_PINCFG93_RDZERO93_Msk        (0x20UL)                  /*!< RDZERO93 (Bitfield-Mask: 0x01)                        */
33668 #define GPIO_PINCFG93_INPEN93_Pos         (4UL)                     /*!< INPEN93 (Bit 4)                                       */
33669 #define GPIO_PINCFG93_INPEN93_Msk         (0x10UL)                  /*!< INPEN93 (Bitfield-Mask: 0x01)                         */
33670 #define GPIO_PINCFG93_FNCSEL93_Pos        (0UL)                     /*!< FNCSEL93 (Bit 0)                                      */
33671 #define GPIO_PINCFG93_FNCSEL93_Msk        (0xfUL)                   /*!< FNCSEL93 (Bitfield-Mask: 0x0f)                        */
33672 /* =======================================================  PINCFG94  ======================================================== */
33673 #define GPIO_PINCFG94_FOEN94_Pos          (27UL)                    /*!< FOEN94 (Bit 27)                                       */
33674 #define GPIO_PINCFG94_FOEN94_Msk          (0x8000000UL)             /*!< FOEN94 (Bitfield-Mask: 0x01)                          */
33675 #define GPIO_PINCFG94_FIEN94_Pos          (26UL)                    /*!< FIEN94 (Bit 26)                                       */
33676 #define GPIO_PINCFG94_FIEN94_Msk          (0x4000000UL)             /*!< FIEN94 (Bitfield-Mask: 0x01)                          */
33677 #define GPIO_PINCFG94_NCEPOL94_Pos        (22UL)                    /*!< NCEPOL94 (Bit 22)                                     */
33678 #define GPIO_PINCFG94_NCEPOL94_Msk        (0x400000UL)              /*!< NCEPOL94 (Bitfield-Mask: 0x01)                        */
33679 #define GPIO_PINCFG94_NCESRC94_Pos        (16UL)                    /*!< NCESRC94 (Bit 16)                                     */
33680 #define GPIO_PINCFG94_NCESRC94_Msk        (0x3f0000UL)              /*!< NCESRC94 (Bitfield-Mask: 0x3f)                        */
33681 #define GPIO_PINCFG94_PULLCFG94_Pos       (13UL)                    /*!< PULLCFG94 (Bit 13)                                    */
33682 #define GPIO_PINCFG94_PULLCFG94_Msk       (0xe000UL)                /*!< PULLCFG94 (Bitfield-Mask: 0x07)                       */
33683 #define GPIO_PINCFG94_SR94_Pos            (12UL)                    /*!< SR94 (Bit 12)                                         */
33684 #define GPIO_PINCFG94_SR94_Msk            (0x1000UL)                /*!< SR94 (Bitfield-Mask: 0x01)                            */
33685 #define GPIO_PINCFG94_DS94_Pos            (10UL)                    /*!< DS94 (Bit 10)                                         */
33686 #define GPIO_PINCFG94_DS94_Msk            (0xc00UL)                 /*!< DS94 (Bitfield-Mask: 0x03)                            */
33687 #define GPIO_PINCFG94_OUTCFG94_Pos        (8UL)                     /*!< OUTCFG94 (Bit 8)                                      */
33688 #define GPIO_PINCFG94_OUTCFG94_Msk        (0x300UL)                 /*!< OUTCFG94 (Bitfield-Mask: 0x03)                        */
33689 #define GPIO_PINCFG94_IRPTEN94_Pos        (6UL)                     /*!< IRPTEN94 (Bit 6)                                      */
33690 #define GPIO_PINCFG94_IRPTEN94_Msk        (0xc0UL)                  /*!< IRPTEN94 (Bitfield-Mask: 0x03)                        */
33691 #define GPIO_PINCFG94_RDZERO94_Pos        (5UL)                     /*!< RDZERO94 (Bit 5)                                      */
33692 #define GPIO_PINCFG94_RDZERO94_Msk        (0x20UL)                  /*!< RDZERO94 (Bitfield-Mask: 0x01)                        */
33693 #define GPIO_PINCFG94_INPEN94_Pos         (4UL)                     /*!< INPEN94 (Bit 4)                                       */
33694 #define GPIO_PINCFG94_INPEN94_Msk         (0x10UL)                  /*!< INPEN94 (Bitfield-Mask: 0x01)                         */
33695 #define GPIO_PINCFG94_FNCSEL94_Pos        (0UL)                     /*!< FNCSEL94 (Bit 0)                                      */
33696 #define GPIO_PINCFG94_FNCSEL94_Msk        (0xfUL)                   /*!< FNCSEL94 (Bitfield-Mask: 0x0f)                        */
33697 /* =======================================================  PINCFG95  ======================================================== */
33698 #define GPIO_PINCFG95_FOEN95_Pos          (27UL)                    /*!< FOEN95 (Bit 27)                                       */
33699 #define GPIO_PINCFG95_FOEN95_Msk          (0x8000000UL)             /*!< FOEN95 (Bitfield-Mask: 0x01)                          */
33700 #define GPIO_PINCFG95_FIEN95_Pos          (26UL)                    /*!< FIEN95 (Bit 26)                                       */
33701 #define GPIO_PINCFG95_FIEN95_Msk          (0x4000000UL)             /*!< FIEN95 (Bitfield-Mask: 0x01)                          */
33702 #define GPIO_PINCFG95_NCEPOL95_Pos        (22UL)                    /*!< NCEPOL95 (Bit 22)                                     */
33703 #define GPIO_PINCFG95_NCEPOL95_Msk        (0x400000UL)              /*!< NCEPOL95 (Bitfield-Mask: 0x01)                        */
33704 #define GPIO_PINCFG95_NCESRC95_Pos        (16UL)                    /*!< NCESRC95 (Bit 16)                                     */
33705 #define GPIO_PINCFG95_NCESRC95_Msk        (0x3f0000UL)              /*!< NCESRC95 (Bitfield-Mask: 0x3f)                        */
33706 #define GPIO_PINCFG95_PULLCFG95_Pos       (13UL)                    /*!< PULLCFG95 (Bit 13)                                    */
33707 #define GPIO_PINCFG95_PULLCFG95_Msk       (0xe000UL)                /*!< PULLCFG95 (Bitfield-Mask: 0x07)                       */
33708 #define GPIO_PINCFG95_SR95_Pos            (12UL)                    /*!< SR95 (Bit 12)                                         */
33709 #define GPIO_PINCFG95_SR95_Msk            (0x1000UL)                /*!< SR95 (Bitfield-Mask: 0x01)                            */
33710 #define GPIO_PINCFG95_DS95_Pos            (10UL)                    /*!< DS95 (Bit 10)                                         */
33711 #define GPIO_PINCFG95_DS95_Msk            (0xc00UL)                 /*!< DS95 (Bitfield-Mask: 0x03)                            */
33712 #define GPIO_PINCFG95_OUTCFG95_Pos        (8UL)                     /*!< OUTCFG95 (Bit 8)                                      */
33713 #define GPIO_PINCFG95_OUTCFG95_Msk        (0x300UL)                 /*!< OUTCFG95 (Bitfield-Mask: 0x03)                        */
33714 #define GPIO_PINCFG95_IRPTEN95_Pos        (6UL)                     /*!< IRPTEN95 (Bit 6)                                      */
33715 #define GPIO_PINCFG95_IRPTEN95_Msk        (0xc0UL)                  /*!< IRPTEN95 (Bitfield-Mask: 0x03)                        */
33716 #define GPIO_PINCFG95_RDZERO95_Pos        (5UL)                     /*!< RDZERO95 (Bit 5)                                      */
33717 #define GPIO_PINCFG95_RDZERO95_Msk        (0x20UL)                  /*!< RDZERO95 (Bitfield-Mask: 0x01)                        */
33718 #define GPIO_PINCFG95_INPEN95_Pos         (4UL)                     /*!< INPEN95 (Bit 4)                                       */
33719 #define GPIO_PINCFG95_INPEN95_Msk         (0x10UL)                  /*!< INPEN95 (Bitfield-Mask: 0x01)                         */
33720 #define GPIO_PINCFG95_FNCSEL95_Pos        (0UL)                     /*!< FNCSEL95 (Bit 0)                                      */
33721 #define GPIO_PINCFG95_FNCSEL95_Msk        (0xfUL)                   /*!< FNCSEL95 (Bitfield-Mask: 0x0f)                        */
33722 /* =======================================================  PINCFG96  ======================================================== */
33723 #define GPIO_PINCFG96_FOEN96_Pos          (27UL)                    /*!< FOEN96 (Bit 27)                                       */
33724 #define GPIO_PINCFG96_FOEN96_Msk          (0x8000000UL)             /*!< FOEN96 (Bitfield-Mask: 0x01)                          */
33725 #define GPIO_PINCFG96_FIEN96_Pos          (26UL)                    /*!< FIEN96 (Bit 26)                                       */
33726 #define GPIO_PINCFG96_FIEN96_Msk          (0x4000000UL)             /*!< FIEN96 (Bitfield-Mask: 0x01)                          */
33727 #define GPIO_PINCFG96_NCEPOL96_Pos        (22UL)                    /*!< NCEPOL96 (Bit 22)                                     */
33728 #define GPIO_PINCFG96_NCEPOL96_Msk        (0x400000UL)              /*!< NCEPOL96 (Bitfield-Mask: 0x01)                        */
33729 #define GPIO_PINCFG96_NCESRC96_Pos        (16UL)                    /*!< NCESRC96 (Bit 16)                                     */
33730 #define GPIO_PINCFG96_NCESRC96_Msk        (0x3f0000UL)              /*!< NCESRC96 (Bitfield-Mask: 0x3f)                        */
33731 #define GPIO_PINCFG96_PULLCFG96_Pos       (13UL)                    /*!< PULLCFG96 (Bit 13)                                    */
33732 #define GPIO_PINCFG96_PULLCFG96_Msk       (0xe000UL)                /*!< PULLCFG96 (Bitfield-Mask: 0x07)                       */
33733 #define GPIO_PINCFG96_SR96_Pos            (12UL)                    /*!< SR96 (Bit 12)                                         */
33734 #define GPIO_PINCFG96_SR96_Msk            (0x1000UL)                /*!< SR96 (Bitfield-Mask: 0x01)                            */
33735 #define GPIO_PINCFG96_DS96_Pos            (10UL)                    /*!< DS96 (Bit 10)                                         */
33736 #define GPIO_PINCFG96_DS96_Msk            (0xc00UL)                 /*!< DS96 (Bitfield-Mask: 0x03)                            */
33737 #define GPIO_PINCFG96_OUTCFG96_Pos        (8UL)                     /*!< OUTCFG96 (Bit 8)                                      */
33738 #define GPIO_PINCFG96_OUTCFG96_Msk        (0x300UL)                 /*!< OUTCFG96 (Bitfield-Mask: 0x03)                        */
33739 #define GPIO_PINCFG96_IRPTEN96_Pos        (6UL)                     /*!< IRPTEN96 (Bit 6)                                      */
33740 #define GPIO_PINCFG96_IRPTEN96_Msk        (0xc0UL)                  /*!< IRPTEN96 (Bitfield-Mask: 0x03)                        */
33741 #define GPIO_PINCFG96_RDZERO96_Pos        (5UL)                     /*!< RDZERO96 (Bit 5)                                      */
33742 #define GPIO_PINCFG96_RDZERO96_Msk        (0x20UL)                  /*!< RDZERO96 (Bitfield-Mask: 0x01)                        */
33743 #define GPIO_PINCFG96_INPEN96_Pos         (4UL)                     /*!< INPEN96 (Bit 4)                                       */
33744 #define GPIO_PINCFG96_INPEN96_Msk         (0x10UL)                  /*!< INPEN96 (Bitfield-Mask: 0x01)                         */
33745 #define GPIO_PINCFG96_FNCSEL96_Pos        (0UL)                     /*!< FNCSEL96 (Bit 0)                                      */
33746 #define GPIO_PINCFG96_FNCSEL96_Msk        (0xfUL)                   /*!< FNCSEL96 (Bitfield-Mask: 0x0f)                        */
33747 /* =======================================================  PINCFG97  ======================================================== */
33748 #define GPIO_PINCFG97_FOEN97_Pos          (27UL)                    /*!< FOEN97 (Bit 27)                                       */
33749 #define GPIO_PINCFG97_FOEN97_Msk          (0x8000000UL)             /*!< FOEN97 (Bitfield-Mask: 0x01)                          */
33750 #define GPIO_PINCFG97_FIEN97_Pos          (26UL)                    /*!< FIEN97 (Bit 26)                                       */
33751 #define GPIO_PINCFG97_FIEN97_Msk          (0x4000000UL)             /*!< FIEN97 (Bitfield-Mask: 0x01)                          */
33752 #define GPIO_PINCFG97_NCEPOL97_Pos        (22UL)                    /*!< NCEPOL97 (Bit 22)                                     */
33753 #define GPIO_PINCFG97_NCEPOL97_Msk        (0x400000UL)              /*!< NCEPOL97 (Bitfield-Mask: 0x01)                        */
33754 #define GPIO_PINCFG97_NCESRC97_Pos        (16UL)                    /*!< NCESRC97 (Bit 16)                                     */
33755 #define GPIO_PINCFG97_NCESRC97_Msk        (0x3f0000UL)              /*!< NCESRC97 (Bitfield-Mask: 0x3f)                        */
33756 #define GPIO_PINCFG97_PULLCFG97_Pos       (13UL)                    /*!< PULLCFG97 (Bit 13)                                    */
33757 #define GPIO_PINCFG97_PULLCFG97_Msk       (0xe000UL)                /*!< PULLCFG97 (Bitfield-Mask: 0x07)                       */
33758 #define GPIO_PINCFG97_SR97_Pos            (12UL)                    /*!< SR97 (Bit 12)                                         */
33759 #define GPIO_PINCFG97_SR97_Msk            (0x1000UL)                /*!< SR97 (Bitfield-Mask: 0x01)                            */
33760 #define GPIO_PINCFG97_DS97_Pos            (10UL)                    /*!< DS97 (Bit 10)                                         */
33761 #define GPIO_PINCFG97_DS97_Msk            (0xc00UL)                 /*!< DS97 (Bitfield-Mask: 0x03)                            */
33762 #define GPIO_PINCFG97_OUTCFG97_Pos        (8UL)                     /*!< OUTCFG97 (Bit 8)                                      */
33763 #define GPIO_PINCFG97_OUTCFG97_Msk        (0x300UL)                 /*!< OUTCFG97 (Bitfield-Mask: 0x03)                        */
33764 #define GPIO_PINCFG97_IRPTEN97_Pos        (6UL)                     /*!< IRPTEN97 (Bit 6)                                      */
33765 #define GPIO_PINCFG97_IRPTEN97_Msk        (0xc0UL)                  /*!< IRPTEN97 (Bitfield-Mask: 0x03)                        */
33766 #define GPIO_PINCFG97_RDZERO97_Pos        (5UL)                     /*!< RDZERO97 (Bit 5)                                      */
33767 #define GPIO_PINCFG97_RDZERO97_Msk        (0x20UL)                  /*!< RDZERO97 (Bitfield-Mask: 0x01)                        */
33768 #define GPIO_PINCFG97_INPEN97_Pos         (4UL)                     /*!< INPEN97 (Bit 4)                                       */
33769 #define GPIO_PINCFG97_INPEN97_Msk         (0x10UL)                  /*!< INPEN97 (Bitfield-Mask: 0x01)                         */
33770 #define GPIO_PINCFG97_FNCSEL97_Pos        (0UL)                     /*!< FNCSEL97 (Bit 0)                                      */
33771 #define GPIO_PINCFG97_FNCSEL97_Msk        (0xfUL)                   /*!< FNCSEL97 (Bitfield-Mask: 0x0f)                        */
33772 /* =======================================================  PINCFG98  ======================================================== */
33773 #define GPIO_PINCFG98_FOEN98_Pos          (27UL)                    /*!< FOEN98 (Bit 27)                                       */
33774 #define GPIO_PINCFG98_FOEN98_Msk          (0x8000000UL)             /*!< FOEN98 (Bitfield-Mask: 0x01)                          */
33775 #define GPIO_PINCFG98_FIEN98_Pos          (26UL)                    /*!< FIEN98 (Bit 26)                                       */
33776 #define GPIO_PINCFG98_FIEN98_Msk          (0x4000000UL)             /*!< FIEN98 (Bitfield-Mask: 0x01)                          */
33777 #define GPIO_PINCFG98_NCEPOL98_Pos        (22UL)                    /*!< NCEPOL98 (Bit 22)                                     */
33778 #define GPIO_PINCFG98_NCEPOL98_Msk        (0x400000UL)              /*!< NCEPOL98 (Bitfield-Mask: 0x01)                        */
33779 #define GPIO_PINCFG98_NCESRC98_Pos        (16UL)                    /*!< NCESRC98 (Bit 16)                                     */
33780 #define GPIO_PINCFG98_NCESRC98_Msk        (0x3f0000UL)              /*!< NCESRC98 (Bitfield-Mask: 0x3f)                        */
33781 #define GPIO_PINCFG98_PULLCFG98_Pos       (13UL)                    /*!< PULLCFG98 (Bit 13)                                    */
33782 #define GPIO_PINCFG98_PULLCFG98_Msk       (0xe000UL)                /*!< PULLCFG98 (Bitfield-Mask: 0x07)                       */
33783 #define GPIO_PINCFG98_SR98_Pos            (12UL)                    /*!< SR98 (Bit 12)                                         */
33784 #define GPIO_PINCFG98_SR98_Msk            (0x1000UL)                /*!< SR98 (Bitfield-Mask: 0x01)                            */
33785 #define GPIO_PINCFG98_DS98_Pos            (10UL)                    /*!< DS98 (Bit 10)                                         */
33786 #define GPIO_PINCFG98_DS98_Msk            (0xc00UL)                 /*!< DS98 (Bitfield-Mask: 0x03)                            */
33787 #define GPIO_PINCFG98_OUTCFG98_Pos        (8UL)                     /*!< OUTCFG98 (Bit 8)                                      */
33788 #define GPIO_PINCFG98_OUTCFG98_Msk        (0x300UL)                 /*!< OUTCFG98 (Bitfield-Mask: 0x03)                        */
33789 #define GPIO_PINCFG98_IRPTEN98_Pos        (6UL)                     /*!< IRPTEN98 (Bit 6)                                      */
33790 #define GPIO_PINCFG98_IRPTEN98_Msk        (0xc0UL)                  /*!< IRPTEN98 (Bitfield-Mask: 0x03)                        */
33791 #define GPIO_PINCFG98_RDZERO98_Pos        (5UL)                     /*!< RDZERO98 (Bit 5)                                      */
33792 #define GPIO_PINCFG98_RDZERO98_Msk        (0x20UL)                  /*!< RDZERO98 (Bitfield-Mask: 0x01)                        */
33793 #define GPIO_PINCFG98_INPEN98_Pos         (4UL)                     /*!< INPEN98 (Bit 4)                                       */
33794 #define GPIO_PINCFG98_INPEN98_Msk         (0x10UL)                  /*!< INPEN98 (Bitfield-Mask: 0x01)                         */
33795 #define GPIO_PINCFG98_FNCSEL98_Pos        (0UL)                     /*!< FNCSEL98 (Bit 0)                                      */
33796 #define GPIO_PINCFG98_FNCSEL98_Msk        (0xfUL)                   /*!< FNCSEL98 (Bitfield-Mask: 0x0f)                        */
33797 /* =======================================================  PINCFG99  ======================================================== */
33798 #define GPIO_PINCFG99_FOEN99_Pos          (27UL)                    /*!< FOEN99 (Bit 27)                                       */
33799 #define GPIO_PINCFG99_FOEN99_Msk          (0x8000000UL)             /*!< FOEN99 (Bitfield-Mask: 0x01)                          */
33800 #define GPIO_PINCFG99_FIEN99_Pos          (26UL)                    /*!< FIEN99 (Bit 26)                                       */
33801 #define GPIO_PINCFG99_FIEN99_Msk          (0x4000000UL)             /*!< FIEN99 (Bitfield-Mask: 0x01)                          */
33802 #define GPIO_PINCFG99_NCEPOL99_Pos        (22UL)                    /*!< NCEPOL99 (Bit 22)                                     */
33803 #define GPIO_PINCFG99_NCEPOL99_Msk        (0x400000UL)              /*!< NCEPOL99 (Bitfield-Mask: 0x01)                        */
33804 #define GPIO_PINCFG99_NCESRC99_Pos        (16UL)                    /*!< NCESRC99 (Bit 16)                                     */
33805 #define GPIO_PINCFG99_NCESRC99_Msk        (0x3f0000UL)              /*!< NCESRC99 (Bitfield-Mask: 0x3f)                        */
33806 #define GPIO_PINCFG99_PULLCFG99_Pos       (13UL)                    /*!< PULLCFG99 (Bit 13)                                    */
33807 #define GPIO_PINCFG99_PULLCFG99_Msk       (0xe000UL)                /*!< PULLCFG99 (Bitfield-Mask: 0x07)                       */
33808 #define GPIO_PINCFG99_SR99_Pos            (12UL)                    /*!< SR99 (Bit 12)                                         */
33809 #define GPIO_PINCFG99_SR99_Msk            (0x1000UL)                /*!< SR99 (Bitfield-Mask: 0x01)                            */
33810 #define GPIO_PINCFG99_DS99_Pos            (10UL)                    /*!< DS99 (Bit 10)                                         */
33811 #define GPIO_PINCFG99_DS99_Msk            (0xc00UL)                 /*!< DS99 (Bitfield-Mask: 0x03)                            */
33812 #define GPIO_PINCFG99_OUTCFG99_Pos        (8UL)                     /*!< OUTCFG99 (Bit 8)                                      */
33813 #define GPIO_PINCFG99_OUTCFG99_Msk        (0x300UL)                 /*!< OUTCFG99 (Bitfield-Mask: 0x03)                        */
33814 #define GPIO_PINCFG99_IRPTEN99_Pos        (6UL)                     /*!< IRPTEN99 (Bit 6)                                      */
33815 #define GPIO_PINCFG99_IRPTEN99_Msk        (0xc0UL)                  /*!< IRPTEN99 (Bitfield-Mask: 0x03)                        */
33816 #define GPIO_PINCFG99_RDZERO99_Pos        (5UL)                     /*!< RDZERO99 (Bit 5)                                      */
33817 #define GPIO_PINCFG99_RDZERO99_Msk        (0x20UL)                  /*!< RDZERO99 (Bitfield-Mask: 0x01)                        */
33818 #define GPIO_PINCFG99_INPEN99_Pos         (4UL)                     /*!< INPEN99 (Bit 4)                                       */
33819 #define GPIO_PINCFG99_INPEN99_Msk         (0x10UL)                  /*!< INPEN99 (Bitfield-Mask: 0x01)                         */
33820 #define GPIO_PINCFG99_FNCSEL99_Pos        (0UL)                     /*!< FNCSEL99 (Bit 0)                                      */
33821 #define GPIO_PINCFG99_FNCSEL99_Msk        (0xfUL)                   /*!< FNCSEL99 (Bitfield-Mask: 0x0f)                        */
33822 /* =======================================================  PINCFG100  ======================================================= */
33823 #define GPIO_PINCFG100_FOEN100_Pos        (27UL)                    /*!< FOEN100 (Bit 27)                                      */
33824 #define GPIO_PINCFG100_FOEN100_Msk        (0x8000000UL)             /*!< FOEN100 (Bitfield-Mask: 0x01)                         */
33825 #define GPIO_PINCFG100_FIEN100_Pos        (26UL)                    /*!< FIEN100 (Bit 26)                                      */
33826 #define GPIO_PINCFG100_FIEN100_Msk        (0x4000000UL)             /*!< FIEN100 (Bitfield-Mask: 0x01)                         */
33827 #define GPIO_PINCFG100_NCEPOL100_Pos      (22UL)                    /*!< NCEPOL100 (Bit 22)                                    */
33828 #define GPIO_PINCFG100_NCEPOL100_Msk      (0x400000UL)              /*!< NCEPOL100 (Bitfield-Mask: 0x01)                       */
33829 #define GPIO_PINCFG100_NCESRC100_Pos      (16UL)                    /*!< NCESRC100 (Bit 16)                                    */
33830 #define GPIO_PINCFG100_NCESRC100_Msk      (0x3f0000UL)              /*!< NCESRC100 (Bitfield-Mask: 0x3f)                       */
33831 #define GPIO_PINCFG100_PULLCFG100_Pos     (13UL)                    /*!< PULLCFG100 (Bit 13)                                   */
33832 #define GPIO_PINCFG100_PULLCFG100_Msk     (0xe000UL)                /*!< PULLCFG100 (Bitfield-Mask: 0x07)                      */
33833 #define GPIO_PINCFG100_SR100_Pos          (12UL)                    /*!< SR100 (Bit 12)                                        */
33834 #define GPIO_PINCFG100_SR100_Msk          (0x1000UL)                /*!< SR100 (Bitfield-Mask: 0x01)                           */
33835 #define GPIO_PINCFG100_DS100_Pos          (10UL)                    /*!< DS100 (Bit 10)                                        */
33836 #define GPIO_PINCFG100_DS100_Msk          (0xc00UL)                 /*!< DS100 (Bitfield-Mask: 0x03)                           */
33837 #define GPIO_PINCFG100_OUTCFG100_Pos      (8UL)                     /*!< OUTCFG100 (Bit 8)                                     */
33838 #define GPIO_PINCFG100_OUTCFG100_Msk      (0x300UL)                 /*!< OUTCFG100 (Bitfield-Mask: 0x03)                       */
33839 #define GPIO_PINCFG100_IRPTEN100_Pos      (6UL)                     /*!< IRPTEN100 (Bit 6)                                     */
33840 #define GPIO_PINCFG100_IRPTEN100_Msk      (0xc0UL)                  /*!< IRPTEN100 (Bitfield-Mask: 0x03)                       */
33841 #define GPIO_PINCFG100_RDZERO100_Pos      (5UL)                     /*!< RDZERO100 (Bit 5)                                     */
33842 #define GPIO_PINCFG100_RDZERO100_Msk      (0x20UL)                  /*!< RDZERO100 (Bitfield-Mask: 0x01)                       */
33843 #define GPIO_PINCFG100_INPEN100_Pos       (4UL)                     /*!< INPEN100 (Bit 4)                                      */
33844 #define GPIO_PINCFG100_INPEN100_Msk       (0x10UL)                  /*!< INPEN100 (Bitfield-Mask: 0x01)                        */
33845 #define GPIO_PINCFG100_FNCSEL100_Pos      (0UL)                     /*!< FNCSEL100 (Bit 0)                                     */
33846 #define GPIO_PINCFG100_FNCSEL100_Msk      (0xfUL)                   /*!< FNCSEL100 (Bitfield-Mask: 0x0f)                       */
33847 /* =======================================================  PINCFG101  ======================================================= */
33848 #define GPIO_PINCFG101_FOEN101_Pos        (27UL)                    /*!< FOEN101 (Bit 27)                                      */
33849 #define GPIO_PINCFG101_FOEN101_Msk        (0x8000000UL)             /*!< FOEN101 (Bitfield-Mask: 0x01)                         */
33850 #define GPIO_PINCFG101_FIEN101_Pos        (26UL)                    /*!< FIEN101 (Bit 26)                                      */
33851 #define GPIO_PINCFG101_FIEN101_Msk        (0x4000000UL)             /*!< FIEN101 (Bitfield-Mask: 0x01)                         */
33852 #define GPIO_PINCFG101_NCEPOL101_Pos      (22UL)                    /*!< NCEPOL101 (Bit 22)                                    */
33853 #define GPIO_PINCFG101_NCEPOL101_Msk      (0x400000UL)              /*!< NCEPOL101 (Bitfield-Mask: 0x01)                       */
33854 #define GPIO_PINCFG101_NCESRC101_Pos      (16UL)                    /*!< NCESRC101 (Bit 16)                                    */
33855 #define GPIO_PINCFG101_NCESRC101_Msk      (0x3f0000UL)              /*!< NCESRC101 (Bitfield-Mask: 0x3f)                       */
33856 #define GPIO_PINCFG101_PULLCFG101_Pos     (13UL)                    /*!< PULLCFG101 (Bit 13)                                   */
33857 #define GPIO_PINCFG101_PULLCFG101_Msk     (0xe000UL)                /*!< PULLCFG101 (Bitfield-Mask: 0x07)                      */
33858 #define GPIO_PINCFG101_SR101_Pos          (12UL)                    /*!< SR101 (Bit 12)                                        */
33859 #define GPIO_PINCFG101_SR101_Msk          (0x1000UL)                /*!< SR101 (Bitfield-Mask: 0x01)                           */
33860 #define GPIO_PINCFG101_DS101_Pos          (10UL)                    /*!< DS101 (Bit 10)                                        */
33861 #define GPIO_PINCFG101_DS101_Msk          (0xc00UL)                 /*!< DS101 (Bitfield-Mask: 0x03)                           */
33862 #define GPIO_PINCFG101_OUTCFG101_Pos      (8UL)                     /*!< OUTCFG101 (Bit 8)                                     */
33863 #define GPIO_PINCFG101_OUTCFG101_Msk      (0x300UL)                 /*!< OUTCFG101 (Bitfield-Mask: 0x03)                       */
33864 #define GPIO_PINCFG101_IRPTEN101_Pos      (6UL)                     /*!< IRPTEN101 (Bit 6)                                     */
33865 #define GPIO_PINCFG101_IRPTEN101_Msk      (0xc0UL)                  /*!< IRPTEN101 (Bitfield-Mask: 0x03)                       */
33866 #define GPIO_PINCFG101_RDZERO101_Pos      (5UL)                     /*!< RDZERO101 (Bit 5)                                     */
33867 #define GPIO_PINCFG101_RDZERO101_Msk      (0x20UL)                  /*!< RDZERO101 (Bitfield-Mask: 0x01)                       */
33868 #define GPIO_PINCFG101_INPEN101_Pos       (4UL)                     /*!< INPEN101 (Bit 4)                                      */
33869 #define GPIO_PINCFG101_INPEN101_Msk       (0x10UL)                  /*!< INPEN101 (Bitfield-Mask: 0x01)                        */
33870 #define GPIO_PINCFG101_FNCSEL101_Pos      (0UL)                     /*!< FNCSEL101 (Bit 0)                                     */
33871 #define GPIO_PINCFG101_FNCSEL101_Msk      (0xfUL)                   /*!< FNCSEL101 (Bitfield-Mask: 0x0f)                       */
33872 /* =======================================================  PINCFG102  ======================================================= */
33873 #define GPIO_PINCFG102_FOEN102_Pos        (27UL)                    /*!< FOEN102 (Bit 27)                                      */
33874 #define GPIO_PINCFG102_FOEN102_Msk        (0x8000000UL)             /*!< FOEN102 (Bitfield-Mask: 0x01)                         */
33875 #define GPIO_PINCFG102_FIEN102_Pos        (26UL)                    /*!< FIEN102 (Bit 26)                                      */
33876 #define GPIO_PINCFG102_FIEN102_Msk        (0x4000000UL)             /*!< FIEN102 (Bitfield-Mask: 0x01)                         */
33877 #define GPIO_PINCFG102_NCEPOL102_Pos      (22UL)                    /*!< NCEPOL102 (Bit 22)                                    */
33878 #define GPIO_PINCFG102_NCEPOL102_Msk      (0x400000UL)              /*!< NCEPOL102 (Bitfield-Mask: 0x01)                       */
33879 #define GPIO_PINCFG102_NCESRC102_Pos      (16UL)                    /*!< NCESRC102 (Bit 16)                                    */
33880 #define GPIO_PINCFG102_NCESRC102_Msk      (0x3f0000UL)              /*!< NCESRC102 (Bitfield-Mask: 0x3f)                       */
33881 #define GPIO_PINCFG102_PULLCFG102_Pos     (13UL)                    /*!< PULLCFG102 (Bit 13)                                   */
33882 #define GPIO_PINCFG102_PULLCFG102_Msk     (0xe000UL)                /*!< PULLCFG102 (Bitfield-Mask: 0x07)                      */
33883 #define GPIO_PINCFG102_SR102_Pos          (12UL)                    /*!< SR102 (Bit 12)                                        */
33884 #define GPIO_PINCFG102_SR102_Msk          (0x1000UL)                /*!< SR102 (Bitfield-Mask: 0x01)                           */
33885 #define GPIO_PINCFG102_DS102_Pos          (10UL)                    /*!< DS102 (Bit 10)                                        */
33886 #define GPIO_PINCFG102_DS102_Msk          (0xc00UL)                 /*!< DS102 (Bitfield-Mask: 0x03)                           */
33887 #define GPIO_PINCFG102_OUTCFG102_Pos      (8UL)                     /*!< OUTCFG102 (Bit 8)                                     */
33888 #define GPIO_PINCFG102_OUTCFG102_Msk      (0x300UL)                 /*!< OUTCFG102 (Bitfield-Mask: 0x03)                       */
33889 #define GPIO_PINCFG102_IRPTEN102_Pos      (6UL)                     /*!< IRPTEN102 (Bit 6)                                     */
33890 #define GPIO_PINCFG102_IRPTEN102_Msk      (0xc0UL)                  /*!< IRPTEN102 (Bitfield-Mask: 0x03)                       */
33891 #define GPIO_PINCFG102_RDZERO102_Pos      (5UL)                     /*!< RDZERO102 (Bit 5)                                     */
33892 #define GPIO_PINCFG102_RDZERO102_Msk      (0x20UL)                  /*!< RDZERO102 (Bitfield-Mask: 0x01)                       */
33893 #define GPIO_PINCFG102_INPEN102_Pos       (4UL)                     /*!< INPEN102 (Bit 4)                                      */
33894 #define GPIO_PINCFG102_INPEN102_Msk       (0x10UL)                  /*!< INPEN102 (Bitfield-Mask: 0x01)                        */
33895 #define GPIO_PINCFG102_FNCSEL102_Pos      (0UL)                     /*!< FNCSEL102 (Bit 0)                                     */
33896 #define GPIO_PINCFG102_FNCSEL102_Msk      (0xfUL)                   /*!< FNCSEL102 (Bitfield-Mask: 0x0f)                       */
33897 /* =======================================================  PINCFG103  ======================================================= */
33898 #define GPIO_PINCFG103_FOEN103_Pos        (27UL)                    /*!< FOEN103 (Bit 27)                                      */
33899 #define GPIO_PINCFG103_FOEN103_Msk        (0x8000000UL)             /*!< FOEN103 (Bitfield-Mask: 0x01)                         */
33900 #define GPIO_PINCFG103_FIEN103_Pos        (26UL)                    /*!< FIEN103 (Bit 26)                                      */
33901 #define GPIO_PINCFG103_FIEN103_Msk        (0x4000000UL)             /*!< FIEN103 (Bitfield-Mask: 0x01)                         */
33902 #define GPIO_PINCFG103_NCEPOL103_Pos      (22UL)                    /*!< NCEPOL103 (Bit 22)                                    */
33903 #define GPIO_PINCFG103_NCEPOL103_Msk      (0x400000UL)              /*!< NCEPOL103 (Bitfield-Mask: 0x01)                       */
33904 #define GPIO_PINCFG103_NCESRC103_Pos      (16UL)                    /*!< NCESRC103 (Bit 16)                                    */
33905 #define GPIO_PINCFG103_NCESRC103_Msk      (0x3f0000UL)              /*!< NCESRC103 (Bitfield-Mask: 0x3f)                       */
33906 #define GPIO_PINCFG103_PULLCFG103_Pos     (13UL)                    /*!< PULLCFG103 (Bit 13)                                   */
33907 #define GPIO_PINCFG103_PULLCFG103_Msk     (0xe000UL)                /*!< PULLCFG103 (Bitfield-Mask: 0x07)                      */
33908 #define GPIO_PINCFG103_SR103_Pos          (12UL)                    /*!< SR103 (Bit 12)                                        */
33909 #define GPIO_PINCFG103_SR103_Msk          (0x1000UL)                /*!< SR103 (Bitfield-Mask: 0x01)                           */
33910 #define GPIO_PINCFG103_DS103_Pos          (10UL)                    /*!< DS103 (Bit 10)                                        */
33911 #define GPIO_PINCFG103_DS103_Msk          (0xc00UL)                 /*!< DS103 (Bitfield-Mask: 0x03)                           */
33912 #define GPIO_PINCFG103_OUTCFG103_Pos      (8UL)                     /*!< OUTCFG103 (Bit 8)                                     */
33913 #define GPIO_PINCFG103_OUTCFG103_Msk      (0x300UL)                 /*!< OUTCFG103 (Bitfield-Mask: 0x03)                       */
33914 #define GPIO_PINCFG103_IRPTEN103_Pos      (6UL)                     /*!< IRPTEN103 (Bit 6)                                     */
33915 #define GPIO_PINCFG103_IRPTEN103_Msk      (0xc0UL)                  /*!< IRPTEN103 (Bitfield-Mask: 0x03)                       */
33916 #define GPIO_PINCFG103_RDZERO103_Pos      (5UL)                     /*!< RDZERO103 (Bit 5)                                     */
33917 #define GPIO_PINCFG103_RDZERO103_Msk      (0x20UL)                  /*!< RDZERO103 (Bitfield-Mask: 0x01)                       */
33918 #define GPIO_PINCFG103_INPEN103_Pos       (4UL)                     /*!< INPEN103 (Bit 4)                                      */
33919 #define GPIO_PINCFG103_INPEN103_Msk       (0x10UL)                  /*!< INPEN103 (Bitfield-Mask: 0x01)                        */
33920 #define GPIO_PINCFG103_FNCSEL103_Pos      (0UL)                     /*!< FNCSEL103 (Bit 0)                                     */
33921 #define GPIO_PINCFG103_FNCSEL103_Msk      (0xfUL)                   /*!< FNCSEL103 (Bitfield-Mask: 0x0f)                       */
33922 /* =======================================================  PINCFG104  ======================================================= */
33923 #define GPIO_PINCFG104_FOEN104_Pos        (27UL)                    /*!< FOEN104 (Bit 27)                                      */
33924 #define GPIO_PINCFG104_FOEN104_Msk        (0x8000000UL)             /*!< FOEN104 (Bitfield-Mask: 0x01)                         */
33925 #define GPIO_PINCFG104_FIEN104_Pos        (26UL)                    /*!< FIEN104 (Bit 26)                                      */
33926 #define GPIO_PINCFG104_FIEN104_Msk        (0x4000000UL)             /*!< FIEN104 (Bitfield-Mask: 0x01)                         */
33927 #define GPIO_PINCFG104_NCEPOL104_Pos      (22UL)                    /*!< NCEPOL104 (Bit 22)                                    */
33928 #define GPIO_PINCFG104_NCEPOL104_Msk      (0x400000UL)              /*!< NCEPOL104 (Bitfield-Mask: 0x01)                       */
33929 #define GPIO_PINCFG104_NCESRC104_Pos      (16UL)                    /*!< NCESRC104 (Bit 16)                                    */
33930 #define GPIO_PINCFG104_NCESRC104_Msk      (0x3f0000UL)              /*!< NCESRC104 (Bitfield-Mask: 0x3f)                       */
33931 #define GPIO_PINCFG104_PULLCFG104_Pos     (13UL)                    /*!< PULLCFG104 (Bit 13)                                   */
33932 #define GPIO_PINCFG104_PULLCFG104_Msk     (0xe000UL)                /*!< PULLCFG104 (Bitfield-Mask: 0x07)                      */
33933 #define GPIO_PINCFG104_SR104_Pos          (12UL)                    /*!< SR104 (Bit 12)                                        */
33934 #define GPIO_PINCFG104_SR104_Msk          (0x1000UL)                /*!< SR104 (Bitfield-Mask: 0x01)                           */
33935 #define GPIO_PINCFG104_DS104_Pos          (10UL)                    /*!< DS104 (Bit 10)                                        */
33936 #define GPIO_PINCFG104_DS104_Msk          (0xc00UL)                 /*!< DS104 (Bitfield-Mask: 0x03)                           */
33937 #define GPIO_PINCFG104_OUTCFG104_Pos      (8UL)                     /*!< OUTCFG104 (Bit 8)                                     */
33938 #define GPIO_PINCFG104_OUTCFG104_Msk      (0x300UL)                 /*!< OUTCFG104 (Bitfield-Mask: 0x03)                       */
33939 #define GPIO_PINCFG104_IRPTEN104_Pos      (6UL)                     /*!< IRPTEN104 (Bit 6)                                     */
33940 #define GPIO_PINCFG104_IRPTEN104_Msk      (0xc0UL)                  /*!< IRPTEN104 (Bitfield-Mask: 0x03)                       */
33941 #define GPIO_PINCFG104_RDZERO104_Pos      (5UL)                     /*!< RDZERO104 (Bit 5)                                     */
33942 #define GPIO_PINCFG104_RDZERO104_Msk      (0x20UL)                  /*!< RDZERO104 (Bitfield-Mask: 0x01)                       */
33943 #define GPIO_PINCFG104_INPEN104_Pos       (4UL)                     /*!< INPEN104 (Bit 4)                                      */
33944 #define GPIO_PINCFG104_INPEN104_Msk       (0x10UL)                  /*!< INPEN104 (Bitfield-Mask: 0x01)                        */
33945 #define GPIO_PINCFG104_FNCSEL104_Pos      (0UL)                     /*!< FNCSEL104 (Bit 0)                                     */
33946 #define GPIO_PINCFG104_FNCSEL104_Msk      (0xfUL)                   /*!< FNCSEL104 (Bitfield-Mask: 0x0f)                       */
33947 /* =======================================================  PINCFG105  ======================================================= */
33948 #define GPIO_PINCFG105_OUTCFG105_Pos      (8UL)                     /*!< OUTCFG105 (Bit 8)                                     */
33949 #define GPIO_PINCFG105_OUTCFG105_Msk      (0x300UL)                 /*!< OUTCFG105 (Bitfield-Mask: 0x03)                       */
33950 #define GPIO_PINCFG105_IRPTEN105_Pos      (6UL)                     /*!< IRPTEN105 (Bit 6)                                     */
33951 #define GPIO_PINCFG105_IRPTEN105_Msk      (0xc0UL)                  /*!< IRPTEN105 (Bitfield-Mask: 0x03)                       */
33952 #define GPIO_PINCFG105_RDZERO105_Pos      (5UL)                     /*!< RDZERO105 (Bit 5)                                     */
33953 #define GPIO_PINCFG105_RDZERO105_Msk      (0x20UL)                  /*!< RDZERO105 (Bitfield-Mask: 0x01)                       */
33954 #define GPIO_PINCFG105_INPEN105_Pos       (4UL)                     /*!< INPEN105 (Bit 4)                                      */
33955 #define GPIO_PINCFG105_INPEN105_Msk       (0x10UL)                  /*!< INPEN105 (Bitfield-Mask: 0x01)                        */
33956 #define GPIO_PINCFG105_FNCSEL105_Pos      (0UL)                     /*!< FNCSEL105 (Bit 0)                                     */
33957 #define GPIO_PINCFG105_FNCSEL105_Msk      (0xfUL)                   /*!< FNCSEL105 (Bitfield-Mask: 0x0f)                       */
33958 /* =======================================================  PINCFG106  ======================================================= */
33959 #define GPIO_PINCFG106_OUTCFG106_Pos      (8UL)                     /*!< OUTCFG106 (Bit 8)                                     */
33960 #define GPIO_PINCFG106_OUTCFG106_Msk      (0x300UL)                 /*!< OUTCFG106 (Bitfield-Mask: 0x03)                       */
33961 #define GPIO_PINCFG106_IRPTEN106_Pos      (6UL)                     /*!< IRPTEN106 (Bit 6)                                     */
33962 #define GPIO_PINCFG106_IRPTEN106_Msk      (0xc0UL)                  /*!< IRPTEN106 (Bitfield-Mask: 0x03)                       */
33963 #define GPIO_PINCFG106_RDZERO106_Pos      (5UL)                     /*!< RDZERO106 (Bit 5)                                     */
33964 #define GPIO_PINCFG106_RDZERO106_Msk      (0x20UL)                  /*!< RDZERO106 (Bitfield-Mask: 0x01)                       */
33965 #define GPIO_PINCFG106_INPEN106_Pos       (4UL)                     /*!< INPEN106 (Bit 4)                                      */
33966 #define GPIO_PINCFG106_INPEN106_Msk       (0x10UL)                  /*!< INPEN106 (Bitfield-Mask: 0x01)                        */
33967 #define GPIO_PINCFG106_FNCSEL106_Pos      (0UL)                     /*!< FNCSEL106 (Bit 0)                                     */
33968 #define GPIO_PINCFG106_FNCSEL106_Msk      (0xfUL)                   /*!< FNCSEL106 (Bitfield-Mask: 0x0f)                       */
33969 /* =======================================================  PINCFG107  ======================================================= */
33970 #define GPIO_PINCFG107_OUTCFG107_Pos      (8UL)                     /*!< OUTCFG107 (Bit 8)                                     */
33971 #define GPIO_PINCFG107_OUTCFG107_Msk      (0x300UL)                 /*!< OUTCFG107 (Bitfield-Mask: 0x03)                       */
33972 #define GPIO_PINCFG107_IRPTEN107_Pos      (6UL)                     /*!< IRPTEN107 (Bit 6)                                     */
33973 #define GPIO_PINCFG107_IRPTEN107_Msk      (0xc0UL)                  /*!< IRPTEN107 (Bitfield-Mask: 0x03)                       */
33974 #define GPIO_PINCFG107_RDZERO107_Pos      (5UL)                     /*!< RDZERO107 (Bit 5)                                     */
33975 #define GPIO_PINCFG107_RDZERO107_Msk      (0x20UL)                  /*!< RDZERO107 (Bitfield-Mask: 0x01)                       */
33976 #define GPIO_PINCFG107_INPEN107_Pos       (4UL)                     /*!< INPEN107 (Bit 4)                                      */
33977 #define GPIO_PINCFG107_INPEN107_Msk       (0x10UL)                  /*!< INPEN107 (Bitfield-Mask: 0x01)                        */
33978 #define GPIO_PINCFG107_FNCSEL107_Pos      (0UL)                     /*!< FNCSEL107 (Bit 0)                                     */
33979 #define GPIO_PINCFG107_FNCSEL107_Msk      (0xfUL)                   /*!< FNCSEL107 (Bitfield-Mask: 0x0f)                       */
33980 /* =======================================================  PINCFG108  ======================================================= */
33981 #define GPIO_PINCFG108_OUTCFG108_Pos      (8UL)                     /*!< OUTCFG108 (Bit 8)                                     */
33982 #define GPIO_PINCFG108_OUTCFG108_Msk      (0x300UL)                 /*!< OUTCFG108 (Bitfield-Mask: 0x03)                       */
33983 #define GPIO_PINCFG108_IRPTEN108_Pos      (6UL)                     /*!< IRPTEN108 (Bit 6)                                     */
33984 #define GPIO_PINCFG108_IRPTEN108_Msk      (0xc0UL)                  /*!< IRPTEN108 (Bitfield-Mask: 0x03)                       */
33985 #define GPIO_PINCFG108_RDZERO108_Pos      (5UL)                     /*!< RDZERO108 (Bit 5)                                     */
33986 #define GPIO_PINCFG108_RDZERO108_Msk      (0x20UL)                  /*!< RDZERO108 (Bitfield-Mask: 0x01)                       */
33987 #define GPIO_PINCFG108_INPEN108_Pos       (4UL)                     /*!< INPEN108 (Bit 4)                                      */
33988 #define GPIO_PINCFG108_INPEN108_Msk       (0x10UL)                  /*!< INPEN108 (Bitfield-Mask: 0x01)                        */
33989 #define GPIO_PINCFG108_FNCSEL108_Pos      (0UL)                     /*!< FNCSEL108 (Bit 0)                                     */
33990 #define GPIO_PINCFG108_FNCSEL108_Msk      (0xfUL)                   /*!< FNCSEL108 (Bitfield-Mask: 0x0f)                       */
33991 /* =======================================================  PINCFG109  ======================================================= */
33992 #define GPIO_PINCFG109_OUTCFG109_Pos      (8UL)                     /*!< OUTCFG109 (Bit 8)                                     */
33993 #define GPIO_PINCFG109_OUTCFG109_Msk      (0x300UL)                 /*!< OUTCFG109 (Bitfield-Mask: 0x03)                       */
33994 #define GPIO_PINCFG109_IRPTEN109_Pos      (6UL)                     /*!< IRPTEN109 (Bit 6)                                     */
33995 #define GPIO_PINCFG109_IRPTEN109_Msk      (0xc0UL)                  /*!< IRPTEN109 (Bitfield-Mask: 0x03)                       */
33996 #define GPIO_PINCFG109_RDZERO109_Pos      (5UL)                     /*!< RDZERO109 (Bit 5)                                     */
33997 #define GPIO_PINCFG109_RDZERO109_Msk      (0x20UL)                  /*!< RDZERO109 (Bitfield-Mask: 0x01)                       */
33998 #define GPIO_PINCFG109_INPEN109_Pos       (4UL)                     /*!< INPEN109 (Bit 4)                                      */
33999 #define GPIO_PINCFG109_INPEN109_Msk       (0x10UL)                  /*!< INPEN109 (Bitfield-Mask: 0x01)                        */
34000 #define GPIO_PINCFG109_FNCSEL109_Pos      (0UL)                     /*!< FNCSEL109 (Bit 0)                                     */
34001 #define GPIO_PINCFG109_FNCSEL109_Msk      (0xfUL)                   /*!< FNCSEL109 (Bitfield-Mask: 0x0f)                       */
34002 /* =======================================================  PINCFG110  ======================================================= */
34003 #define GPIO_PINCFG110_OUTCFG110_Pos      (8UL)                     /*!< OUTCFG110 (Bit 8)                                     */
34004 #define GPIO_PINCFG110_OUTCFG110_Msk      (0x300UL)                 /*!< OUTCFG110 (Bitfield-Mask: 0x03)                       */
34005 #define GPIO_PINCFG110_IRPTEN110_Pos      (6UL)                     /*!< IRPTEN110 (Bit 6)                                     */
34006 #define GPIO_PINCFG110_IRPTEN110_Msk      (0xc0UL)                  /*!< IRPTEN110 (Bitfield-Mask: 0x03)                       */
34007 #define GPIO_PINCFG110_RDZERO110_Pos      (5UL)                     /*!< RDZERO110 (Bit 5)                                     */
34008 #define GPIO_PINCFG110_RDZERO110_Msk      (0x20UL)                  /*!< RDZERO110 (Bitfield-Mask: 0x01)                       */
34009 #define GPIO_PINCFG110_INPEN110_Pos       (4UL)                     /*!< INPEN110 (Bit 4)                                      */
34010 #define GPIO_PINCFG110_INPEN110_Msk       (0x10UL)                  /*!< INPEN110 (Bitfield-Mask: 0x01)                        */
34011 #define GPIO_PINCFG110_FNCSEL110_Pos      (0UL)                     /*!< FNCSEL110 (Bit 0)                                     */
34012 #define GPIO_PINCFG110_FNCSEL110_Msk      (0xfUL)                   /*!< FNCSEL110 (Bitfield-Mask: 0x0f)                       */
34013 /* =======================================================  PINCFG111  ======================================================= */
34014 #define GPIO_PINCFG111_OUTCFG111_Pos      (8UL)                     /*!< OUTCFG111 (Bit 8)                                     */
34015 #define GPIO_PINCFG111_OUTCFG111_Msk      (0x300UL)                 /*!< OUTCFG111 (Bitfield-Mask: 0x03)                       */
34016 #define GPIO_PINCFG111_IRPTEN111_Pos      (6UL)                     /*!< IRPTEN111 (Bit 6)                                     */
34017 #define GPIO_PINCFG111_IRPTEN111_Msk      (0xc0UL)                  /*!< IRPTEN111 (Bitfield-Mask: 0x03)                       */
34018 #define GPIO_PINCFG111_RDZERO111_Pos      (5UL)                     /*!< RDZERO111 (Bit 5)                                     */
34019 #define GPIO_PINCFG111_RDZERO111_Msk      (0x20UL)                  /*!< RDZERO111 (Bitfield-Mask: 0x01)                       */
34020 #define GPIO_PINCFG111_INPEN111_Pos       (4UL)                     /*!< INPEN111 (Bit 4)                                      */
34021 #define GPIO_PINCFG111_INPEN111_Msk       (0x10UL)                  /*!< INPEN111 (Bitfield-Mask: 0x01)                        */
34022 #define GPIO_PINCFG111_FNCSEL111_Pos      (0UL)                     /*!< FNCSEL111 (Bit 0)                                     */
34023 #define GPIO_PINCFG111_FNCSEL111_Msk      (0xfUL)                   /*!< FNCSEL111 (Bitfield-Mask: 0x0f)                       */
34024 /* =======================================================  PINCFG112  ======================================================= */
34025 #define GPIO_PINCFG112_OUTCFG112_Pos      (8UL)                     /*!< OUTCFG112 (Bit 8)                                     */
34026 #define GPIO_PINCFG112_OUTCFG112_Msk      (0x300UL)                 /*!< OUTCFG112 (Bitfield-Mask: 0x03)                       */
34027 #define GPIO_PINCFG112_IRPTEN112_Pos      (6UL)                     /*!< IRPTEN112 (Bit 6)                                     */
34028 #define GPIO_PINCFG112_IRPTEN112_Msk      (0xc0UL)                  /*!< IRPTEN112 (Bitfield-Mask: 0x03)                       */
34029 #define GPIO_PINCFG112_RDZERO112_Pos      (5UL)                     /*!< RDZERO112 (Bit 5)                                     */
34030 #define GPIO_PINCFG112_RDZERO112_Msk      (0x20UL)                  /*!< RDZERO112 (Bitfield-Mask: 0x01)                       */
34031 #define GPIO_PINCFG112_INPEN112_Pos       (4UL)                     /*!< INPEN112 (Bit 4)                                      */
34032 #define GPIO_PINCFG112_INPEN112_Msk       (0x10UL)                  /*!< INPEN112 (Bitfield-Mask: 0x01)                        */
34033 #define GPIO_PINCFG112_FNCSEL112_Pos      (0UL)                     /*!< FNCSEL112 (Bit 0)                                     */
34034 #define GPIO_PINCFG112_FNCSEL112_Msk      (0xfUL)                   /*!< FNCSEL112 (Bitfield-Mask: 0x0f)                       */
34035 /* =======================================================  PINCFG113  ======================================================= */
34036 #define GPIO_PINCFG113_OUTCFG113_Pos      (8UL)                     /*!< OUTCFG113 (Bit 8)                                     */
34037 #define GPIO_PINCFG113_OUTCFG113_Msk      (0x300UL)                 /*!< OUTCFG113 (Bitfield-Mask: 0x03)                       */
34038 #define GPIO_PINCFG113_IRPTEN113_Pos      (6UL)                     /*!< IRPTEN113 (Bit 6)                                     */
34039 #define GPIO_PINCFG113_IRPTEN113_Msk      (0xc0UL)                  /*!< IRPTEN113 (Bitfield-Mask: 0x03)                       */
34040 #define GPIO_PINCFG113_RDZERO113_Pos      (5UL)                     /*!< RDZERO113 (Bit 5)                                     */
34041 #define GPIO_PINCFG113_RDZERO113_Msk      (0x20UL)                  /*!< RDZERO113 (Bitfield-Mask: 0x01)                       */
34042 #define GPIO_PINCFG113_INPEN113_Pos       (4UL)                     /*!< INPEN113 (Bit 4)                                      */
34043 #define GPIO_PINCFG113_INPEN113_Msk       (0x10UL)                  /*!< INPEN113 (Bitfield-Mask: 0x01)                        */
34044 #define GPIO_PINCFG113_FNCSEL113_Pos      (0UL)                     /*!< FNCSEL113 (Bit 0)                                     */
34045 #define GPIO_PINCFG113_FNCSEL113_Msk      (0xfUL)                   /*!< FNCSEL113 (Bitfield-Mask: 0x0f)                       */
34046 /* =======================================================  PINCFG114  ======================================================= */
34047 #define GPIO_PINCFG114_OUTCFG114_Pos      (8UL)                     /*!< OUTCFG114 (Bit 8)                                     */
34048 #define GPIO_PINCFG114_OUTCFG114_Msk      (0x300UL)                 /*!< OUTCFG114 (Bitfield-Mask: 0x03)                       */
34049 #define GPIO_PINCFG114_IRPTEN114_Pos      (6UL)                     /*!< IRPTEN114 (Bit 6)                                     */
34050 #define GPIO_PINCFG114_IRPTEN114_Msk      (0xc0UL)                  /*!< IRPTEN114 (Bitfield-Mask: 0x03)                       */
34051 #define GPIO_PINCFG114_RDZERO114_Pos      (5UL)                     /*!< RDZERO114 (Bit 5)                                     */
34052 #define GPIO_PINCFG114_RDZERO114_Msk      (0x20UL)                  /*!< RDZERO114 (Bitfield-Mask: 0x01)                       */
34053 #define GPIO_PINCFG114_INPEN114_Pos       (4UL)                     /*!< INPEN114 (Bit 4)                                      */
34054 #define GPIO_PINCFG114_INPEN114_Msk       (0x10UL)                  /*!< INPEN114 (Bitfield-Mask: 0x01)                        */
34055 #define GPIO_PINCFG114_FNCSEL114_Pos      (0UL)                     /*!< FNCSEL114 (Bit 0)                                     */
34056 #define GPIO_PINCFG114_FNCSEL114_Msk      (0xfUL)                   /*!< FNCSEL114 (Bitfield-Mask: 0x0f)                       */
34057 /* =======================================================  PINCFG115  ======================================================= */
34058 #define GPIO_PINCFG115_OUTCFG115_Pos      (8UL)                     /*!< OUTCFG115 (Bit 8)                                     */
34059 #define GPIO_PINCFG115_OUTCFG115_Msk      (0x300UL)                 /*!< OUTCFG115 (Bitfield-Mask: 0x03)                       */
34060 #define GPIO_PINCFG115_IRPTEN115_Pos      (6UL)                     /*!< IRPTEN115 (Bit 6)                                     */
34061 #define GPIO_PINCFG115_IRPTEN115_Msk      (0xc0UL)                  /*!< IRPTEN115 (Bitfield-Mask: 0x03)                       */
34062 #define GPIO_PINCFG115_RDZERO115_Pos      (5UL)                     /*!< RDZERO115 (Bit 5)                                     */
34063 #define GPIO_PINCFG115_RDZERO115_Msk      (0x20UL)                  /*!< RDZERO115 (Bitfield-Mask: 0x01)                       */
34064 #define GPIO_PINCFG115_INPEN115_Pos       (4UL)                     /*!< INPEN115 (Bit 4)                                      */
34065 #define GPIO_PINCFG115_INPEN115_Msk       (0x10UL)                  /*!< INPEN115 (Bitfield-Mask: 0x01)                        */
34066 #define GPIO_PINCFG115_FNCSEL115_Pos      (0UL)                     /*!< FNCSEL115 (Bit 0)                                     */
34067 #define GPIO_PINCFG115_FNCSEL115_Msk      (0xfUL)                   /*!< FNCSEL115 (Bitfield-Mask: 0x0f)                       */
34068 /* =======================================================  PINCFG116  ======================================================= */
34069 #define GPIO_PINCFG116_OUTCFG116_Pos      (8UL)                     /*!< OUTCFG116 (Bit 8)                                     */
34070 #define GPIO_PINCFG116_OUTCFG116_Msk      (0x300UL)                 /*!< OUTCFG116 (Bitfield-Mask: 0x03)                       */
34071 #define GPIO_PINCFG116_IRPTEN116_Pos      (6UL)                     /*!< IRPTEN116 (Bit 6)                                     */
34072 #define GPIO_PINCFG116_IRPTEN116_Msk      (0xc0UL)                  /*!< IRPTEN116 (Bitfield-Mask: 0x03)                       */
34073 #define GPIO_PINCFG116_RDZERO116_Pos      (5UL)                     /*!< RDZERO116 (Bit 5)                                     */
34074 #define GPIO_PINCFG116_RDZERO116_Msk      (0x20UL)                  /*!< RDZERO116 (Bitfield-Mask: 0x01)                       */
34075 #define GPIO_PINCFG116_INPEN116_Pos       (4UL)                     /*!< INPEN116 (Bit 4)                                      */
34076 #define GPIO_PINCFG116_INPEN116_Msk       (0x10UL)                  /*!< INPEN116 (Bitfield-Mask: 0x01)                        */
34077 #define GPIO_PINCFG116_FNCSEL116_Pos      (0UL)                     /*!< FNCSEL116 (Bit 0)                                     */
34078 #define GPIO_PINCFG116_FNCSEL116_Msk      (0xfUL)                   /*!< FNCSEL116 (Bitfield-Mask: 0x0f)                       */
34079 /* =======================================================  PINCFG117  ======================================================= */
34080 #define GPIO_PINCFG117_OUTCFG117_Pos      (8UL)                     /*!< OUTCFG117 (Bit 8)                                     */
34081 #define GPIO_PINCFG117_OUTCFG117_Msk      (0x300UL)                 /*!< OUTCFG117 (Bitfield-Mask: 0x03)                       */
34082 #define GPIO_PINCFG117_IRPTEN117_Pos      (6UL)                     /*!< IRPTEN117 (Bit 6)                                     */
34083 #define GPIO_PINCFG117_IRPTEN117_Msk      (0xc0UL)                  /*!< IRPTEN117 (Bitfield-Mask: 0x03)                       */
34084 #define GPIO_PINCFG117_RDZERO117_Pos      (5UL)                     /*!< RDZERO117 (Bit 5)                                     */
34085 #define GPIO_PINCFG117_RDZERO117_Msk      (0x20UL)                  /*!< RDZERO117 (Bitfield-Mask: 0x01)                       */
34086 #define GPIO_PINCFG117_INPEN117_Pos       (4UL)                     /*!< INPEN117 (Bit 4)                                      */
34087 #define GPIO_PINCFG117_INPEN117_Msk       (0x10UL)                  /*!< INPEN117 (Bitfield-Mask: 0x01)                        */
34088 #define GPIO_PINCFG117_FNCSEL117_Pos      (0UL)                     /*!< FNCSEL117 (Bit 0)                                     */
34089 #define GPIO_PINCFG117_FNCSEL117_Msk      (0xfUL)                   /*!< FNCSEL117 (Bitfield-Mask: 0x0f)                       */
34090 /* =======================================================  PINCFG118  ======================================================= */
34091 #define GPIO_PINCFG118_OUTCFG118_Pos      (8UL)                     /*!< OUTCFG118 (Bit 8)                                     */
34092 #define GPIO_PINCFG118_OUTCFG118_Msk      (0x300UL)                 /*!< OUTCFG118 (Bitfield-Mask: 0x03)                       */
34093 #define GPIO_PINCFG118_IRPTEN118_Pos      (6UL)                     /*!< IRPTEN118 (Bit 6)                                     */
34094 #define GPIO_PINCFG118_IRPTEN118_Msk      (0xc0UL)                  /*!< IRPTEN118 (Bitfield-Mask: 0x03)                       */
34095 #define GPIO_PINCFG118_RDZERO118_Pos      (5UL)                     /*!< RDZERO118 (Bit 5)                                     */
34096 #define GPIO_PINCFG118_RDZERO118_Msk      (0x20UL)                  /*!< RDZERO118 (Bitfield-Mask: 0x01)                       */
34097 #define GPIO_PINCFG118_INPEN118_Pos       (4UL)                     /*!< INPEN118 (Bit 4)                                      */
34098 #define GPIO_PINCFG118_INPEN118_Msk       (0x10UL)                  /*!< INPEN118 (Bitfield-Mask: 0x01)                        */
34099 #define GPIO_PINCFG118_FNCSEL118_Pos      (0UL)                     /*!< FNCSEL118 (Bit 0)                                     */
34100 #define GPIO_PINCFG118_FNCSEL118_Msk      (0xfUL)                   /*!< FNCSEL118 (Bitfield-Mask: 0x0f)                       */
34101 /* =======================================================  PINCFG119  ======================================================= */
34102 #define GPIO_PINCFG119_OUTCFG119_Pos      (8UL)                     /*!< OUTCFG119 (Bit 8)                                     */
34103 #define GPIO_PINCFG119_OUTCFG119_Msk      (0x300UL)                 /*!< OUTCFG119 (Bitfield-Mask: 0x03)                       */
34104 #define GPIO_PINCFG119_IRPTEN119_Pos      (6UL)                     /*!< IRPTEN119 (Bit 6)                                     */
34105 #define GPIO_PINCFG119_IRPTEN119_Msk      (0xc0UL)                  /*!< IRPTEN119 (Bitfield-Mask: 0x03)                       */
34106 #define GPIO_PINCFG119_RDZERO119_Pos      (5UL)                     /*!< RDZERO119 (Bit 5)                                     */
34107 #define GPIO_PINCFG119_RDZERO119_Msk      (0x20UL)                  /*!< RDZERO119 (Bitfield-Mask: 0x01)                       */
34108 #define GPIO_PINCFG119_INPEN119_Pos       (4UL)                     /*!< INPEN119 (Bit 4)                                      */
34109 #define GPIO_PINCFG119_INPEN119_Msk       (0x10UL)                  /*!< INPEN119 (Bitfield-Mask: 0x01)                        */
34110 #define GPIO_PINCFG119_FNCSEL119_Pos      (0UL)                     /*!< FNCSEL119 (Bit 0)                                     */
34111 #define GPIO_PINCFG119_FNCSEL119_Msk      (0xfUL)                   /*!< FNCSEL119 (Bitfield-Mask: 0x0f)                       */
34112 /* =======================================================  PINCFG120  ======================================================= */
34113 #define GPIO_PINCFG120_OUTCFG120_Pos      (8UL)                     /*!< OUTCFG120 (Bit 8)                                     */
34114 #define GPIO_PINCFG120_OUTCFG120_Msk      (0x300UL)                 /*!< OUTCFG120 (Bitfield-Mask: 0x03)                       */
34115 #define GPIO_PINCFG120_IRPTEN120_Pos      (6UL)                     /*!< IRPTEN120 (Bit 6)                                     */
34116 #define GPIO_PINCFG120_IRPTEN120_Msk      (0xc0UL)                  /*!< IRPTEN120 (Bitfield-Mask: 0x03)                       */
34117 #define GPIO_PINCFG120_RDZERO120_Pos      (5UL)                     /*!< RDZERO120 (Bit 5)                                     */
34118 #define GPIO_PINCFG120_RDZERO120_Msk      (0x20UL)                  /*!< RDZERO120 (Bitfield-Mask: 0x01)                       */
34119 #define GPIO_PINCFG120_INPEN120_Pos       (4UL)                     /*!< INPEN120 (Bit 4)                                      */
34120 #define GPIO_PINCFG120_INPEN120_Msk       (0x10UL)                  /*!< INPEN120 (Bitfield-Mask: 0x01)                        */
34121 #define GPIO_PINCFG120_FNCSEL120_Pos      (0UL)                     /*!< FNCSEL120 (Bit 0)                                     */
34122 #define GPIO_PINCFG120_FNCSEL120_Msk      (0xfUL)                   /*!< FNCSEL120 (Bitfield-Mask: 0x0f)                       */
34123 /* =======================================================  PINCFG121  ======================================================= */
34124 #define GPIO_PINCFG121_OUTCFG121_Pos      (8UL)                     /*!< OUTCFG121 (Bit 8)                                     */
34125 #define GPIO_PINCFG121_OUTCFG121_Msk      (0x300UL)                 /*!< OUTCFG121 (Bitfield-Mask: 0x03)                       */
34126 #define GPIO_PINCFG121_IRPTEN121_Pos      (6UL)                     /*!< IRPTEN121 (Bit 6)                                     */
34127 #define GPIO_PINCFG121_IRPTEN121_Msk      (0xc0UL)                  /*!< IRPTEN121 (Bitfield-Mask: 0x03)                       */
34128 #define GPIO_PINCFG121_RDZERO121_Pos      (5UL)                     /*!< RDZERO121 (Bit 5)                                     */
34129 #define GPIO_PINCFG121_RDZERO121_Msk      (0x20UL)                  /*!< RDZERO121 (Bitfield-Mask: 0x01)                       */
34130 #define GPIO_PINCFG121_INPEN121_Pos       (4UL)                     /*!< INPEN121 (Bit 4)                                      */
34131 #define GPIO_PINCFG121_INPEN121_Msk       (0x10UL)                  /*!< INPEN121 (Bitfield-Mask: 0x01)                        */
34132 #define GPIO_PINCFG121_FNCSEL121_Pos      (0UL)                     /*!< FNCSEL121 (Bit 0)                                     */
34133 #define GPIO_PINCFG121_FNCSEL121_Msk      (0xfUL)                   /*!< FNCSEL121 (Bitfield-Mask: 0x0f)                       */
34134 /* =======================================================  PINCFG122  ======================================================= */
34135 #define GPIO_PINCFG122_OUTCFG122_Pos      (8UL)                     /*!< OUTCFG122 (Bit 8)                                     */
34136 #define GPIO_PINCFG122_OUTCFG122_Msk      (0x300UL)                 /*!< OUTCFG122 (Bitfield-Mask: 0x03)                       */
34137 #define GPIO_PINCFG122_IRPTEN122_Pos      (6UL)                     /*!< IRPTEN122 (Bit 6)                                     */
34138 #define GPIO_PINCFG122_IRPTEN122_Msk      (0xc0UL)                  /*!< IRPTEN122 (Bitfield-Mask: 0x03)                       */
34139 #define GPIO_PINCFG122_RDZERO122_Pos      (5UL)                     /*!< RDZERO122 (Bit 5)                                     */
34140 #define GPIO_PINCFG122_RDZERO122_Msk      (0x20UL)                  /*!< RDZERO122 (Bitfield-Mask: 0x01)                       */
34141 #define GPIO_PINCFG122_INPEN122_Pos       (4UL)                     /*!< INPEN122 (Bit 4)                                      */
34142 #define GPIO_PINCFG122_INPEN122_Msk       (0x10UL)                  /*!< INPEN122 (Bitfield-Mask: 0x01)                        */
34143 #define GPIO_PINCFG122_FNCSEL122_Pos      (0UL)                     /*!< FNCSEL122 (Bit 0)                                     */
34144 #define GPIO_PINCFG122_FNCSEL122_Msk      (0xfUL)                   /*!< FNCSEL122 (Bitfield-Mask: 0x0f)                       */
34145 /* =======================================================  PINCFG123  ======================================================= */
34146 #define GPIO_PINCFG123_OUTCFG123_Pos      (8UL)                     /*!< OUTCFG123 (Bit 8)                                     */
34147 #define GPIO_PINCFG123_OUTCFG123_Msk      (0x300UL)                 /*!< OUTCFG123 (Bitfield-Mask: 0x03)                       */
34148 #define GPIO_PINCFG123_IRPTEN123_Pos      (6UL)                     /*!< IRPTEN123 (Bit 6)                                     */
34149 #define GPIO_PINCFG123_IRPTEN123_Msk      (0xc0UL)                  /*!< IRPTEN123 (Bitfield-Mask: 0x03)                       */
34150 #define GPIO_PINCFG123_RDZERO123_Pos      (5UL)                     /*!< RDZERO123 (Bit 5)                                     */
34151 #define GPIO_PINCFG123_RDZERO123_Msk      (0x20UL)                  /*!< RDZERO123 (Bitfield-Mask: 0x01)                       */
34152 #define GPIO_PINCFG123_INPEN123_Pos       (4UL)                     /*!< INPEN123 (Bit 4)                                      */
34153 #define GPIO_PINCFG123_INPEN123_Msk       (0x10UL)                  /*!< INPEN123 (Bitfield-Mask: 0x01)                        */
34154 #define GPIO_PINCFG123_FNCSEL123_Pos      (0UL)                     /*!< FNCSEL123 (Bit 0)                                     */
34155 #define GPIO_PINCFG123_FNCSEL123_Msk      (0xfUL)                   /*!< FNCSEL123 (Bitfield-Mask: 0x0f)                       */
34156 /* =======================================================  PINCFG124  ======================================================= */
34157 #define GPIO_PINCFG124_OUTCFG124_Pos      (8UL)                     /*!< OUTCFG124 (Bit 8)                                     */
34158 #define GPIO_PINCFG124_OUTCFG124_Msk      (0x300UL)                 /*!< OUTCFG124 (Bitfield-Mask: 0x03)                       */
34159 #define GPIO_PINCFG124_IRPTEN124_Pos      (6UL)                     /*!< IRPTEN124 (Bit 6)                                     */
34160 #define GPIO_PINCFG124_IRPTEN124_Msk      (0xc0UL)                  /*!< IRPTEN124 (Bitfield-Mask: 0x03)                       */
34161 #define GPIO_PINCFG124_RDZERO124_Pos      (5UL)                     /*!< RDZERO124 (Bit 5)                                     */
34162 #define GPIO_PINCFG124_RDZERO124_Msk      (0x20UL)                  /*!< RDZERO124 (Bitfield-Mask: 0x01)                       */
34163 #define GPIO_PINCFG124_INPEN124_Pos       (4UL)                     /*!< INPEN124 (Bit 4)                                      */
34164 #define GPIO_PINCFG124_INPEN124_Msk       (0x10UL)                  /*!< INPEN124 (Bitfield-Mask: 0x01)                        */
34165 #define GPIO_PINCFG124_FNCSEL124_Pos      (0UL)                     /*!< FNCSEL124 (Bit 0)                                     */
34166 #define GPIO_PINCFG124_FNCSEL124_Msk      (0xfUL)                   /*!< FNCSEL124 (Bitfield-Mask: 0x0f)                       */
34167 /* =======================================================  PINCFG125  ======================================================= */
34168 #define GPIO_PINCFG125_OUTCFG125_Pos      (8UL)                     /*!< OUTCFG125 (Bit 8)                                     */
34169 #define GPIO_PINCFG125_OUTCFG125_Msk      (0x300UL)                 /*!< OUTCFG125 (Bitfield-Mask: 0x03)                       */
34170 #define GPIO_PINCFG125_IRPTEN125_Pos      (6UL)                     /*!< IRPTEN125 (Bit 6)                                     */
34171 #define GPIO_PINCFG125_IRPTEN125_Msk      (0xc0UL)                  /*!< IRPTEN125 (Bitfield-Mask: 0x03)                       */
34172 #define GPIO_PINCFG125_RDZERO125_Pos      (5UL)                     /*!< RDZERO125 (Bit 5)                                     */
34173 #define GPIO_PINCFG125_RDZERO125_Msk      (0x20UL)                  /*!< RDZERO125 (Bitfield-Mask: 0x01)                       */
34174 #define GPIO_PINCFG125_INPEN125_Pos       (4UL)                     /*!< INPEN125 (Bit 4)                                      */
34175 #define GPIO_PINCFG125_INPEN125_Msk       (0x10UL)                  /*!< INPEN125 (Bitfield-Mask: 0x01)                        */
34176 #define GPIO_PINCFG125_FNCSEL125_Pos      (0UL)                     /*!< FNCSEL125 (Bit 0)                                     */
34177 #define GPIO_PINCFG125_FNCSEL125_Msk      (0xfUL)                   /*!< FNCSEL125 (Bitfield-Mask: 0x0f)                       */
34178 /* =======================================================  PINCFG126  ======================================================= */
34179 #define GPIO_PINCFG126_OUTCFG126_Pos      (8UL)                     /*!< OUTCFG126 (Bit 8)                                     */
34180 #define GPIO_PINCFG126_OUTCFG126_Msk      (0x300UL)                 /*!< OUTCFG126 (Bitfield-Mask: 0x03)                       */
34181 #define GPIO_PINCFG126_IRPTEN126_Pos      (6UL)                     /*!< IRPTEN126 (Bit 6)                                     */
34182 #define GPIO_PINCFG126_IRPTEN126_Msk      (0xc0UL)                  /*!< IRPTEN126 (Bitfield-Mask: 0x03)                       */
34183 #define GPIO_PINCFG126_RDZERO126_Pos      (5UL)                     /*!< RDZERO126 (Bit 5)                                     */
34184 #define GPIO_PINCFG126_RDZERO126_Msk      (0x20UL)                  /*!< RDZERO126 (Bitfield-Mask: 0x01)                       */
34185 #define GPIO_PINCFG126_INPEN126_Pos       (4UL)                     /*!< INPEN126 (Bit 4)                                      */
34186 #define GPIO_PINCFG126_INPEN126_Msk       (0x10UL)                  /*!< INPEN126 (Bitfield-Mask: 0x01)                        */
34187 #define GPIO_PINCFG126_FNCSEL126_Pos      (0UL)                     /*!< FNCSEL126 (Bit 0)                                     */
34188 #define GPIO_PINCFG126_FNCSEL126_Msk      (0xfUL)                   /*!< FNCSEL126 (Bitfield-Mask: 0x0f)                       */
34189 /* =======================================================  PINCFG127  ======================================================= */
34190 #define GPIO_PINCFG127_OUTCFG127_Pos      (8UL)                     /*!< OUTCFG127 (Bit 8)                                     */
34191 #define GPIO_PINCFG127_OUTCFG127_Msk      (0x300UL)                 /*!< OUTCFG127 (Bitfield-Mask: 0x03)                       */
34192 #define GPIO_PINCFG127_IRPTEN127_Pos      (6UL)                     /*!< IRPTEN127 (Bit 6)                                     */
34193 #define GPIO_PINCFG127_IRPTEN127_Msk      (0xc0UL)                  /*!< IRPTEN127 (Bitfield-Mask: 0x03)                       */
34194 #define GPIO_PINCFG127_RDZERO127_Pos      (5UL)                     /*!< RDZERO127 (Bit 5)                                     */
34195 #define GPIO_PINCFG127_RDZERO127_Msk      (0x20UL)                  /*!< RDZERO127 (Bitfield-Mask: 0x01)                       */
34196 #define GPIO_PINCFG127_INPEN127_Pos       (4UL)                     /*!< INPEN127 (Bit 4)                                      */
34197 #define GPIO_PINCFG127_INPEN127_Msk       (0x10UL)                  /*!< INPEN127 (Bitfield-Mask: 0x01)                        */
34198 #define GPIO_PINCFG127_FNCSEL127_Pos      (0UL)                     /*!< FNCSEL127 (Bit 0)                                     */
34199 #define GPIO_PINCFG127_FNCSEL127_Msk      (0xfUL)                   /*!< FNCSEL127 (Bitfield-Mask: 0x0f)                       */
34200 /* ========================================================  PADKEY  ========================================================= */
34201 #define GPIO_PADKEY_PADKEY_Pos            (0UL)                     /*!< PADKEY (Bit 0)                                        */
34202 #define GPIO_PADKEY_PADKEY_Msk            (0xffffffffUL)            /*!< PADKEY (Bitfield-Mask: 0xffffffff)                    */
34203 /* ==========================================================  RD0  ========================================================== */
34204 #define GPIO_RD0_RD0_Pos                  (0UL)                     /*!< RD0 (Bit 0)                                           */
34205 #define GPIO_RD0_RD0_Msk                  (0xffffffffUL)            /*!< RD0 (Bitfield-Mask: 0xffffffff)                       */
34206 /* ==========================================================  RD1  ========================================================== */
34207 #define GPIO_RD1_RD1_Pos                  (0UL)                     /*!< RD1 (Bit 0)                                           */
34208 #define GPIO_RD1_RD1_Msk                  (0xffffffffUL)            /*!< RD1 (Bitfield-Mask: 0xffffffff)                       */
34209 /* ==========================================================  RD2  ========================================================== */
34210 #define GPIO_RD2_RD2_Pos                  (0UL)                     /*!< RD2 (Bit 0)                                           */
34211 #define GPIO_RD2_RD2_Msk                  (0xffffffffUL)            /*!< RD2 (Bitfield-Mask: 0xffffffff)                       */
34212 /* ==========================================================  RD3  ========================================================== */
34213 #define GPIO_RD3_RD3_Pos                  (0UL)                     /*!< RD3 (Bit 0)                                           */
34214 #define GPIO_RD3_RD3_Msk                  (0xffffffffUL)            /*!< RD3 (Bitfield-Mask: 0xffffffff)                       */
34215 /* ==========================================================  WT0  ========================================================== */
34216 #define GPIO_WT0_WT0_Pos                  (0UL)                     /*!< WT0 (Bit 0)                                           */
34217 #define GPIO_WT0_WT0_Msk                  (0xffffffffUL)            /*!< WT0 (Bitfield-Mask: 0xffffffff)                       */
34218 /* ==========================================================  WT1  ========================================================== */
34219 #define GPIO_WT1_WT1_Pos                  (0UL)                     /*!< WT1 (Bit 0)                                           */
34220 #define GPIO_WT1_WT1_Msk                  (0xffffffffUL)            /*!< WT1 (Bitfield-Mask: 0xffffffff)                       */
34221 /* ==========================================================  WT2  ========================================================== */
34222 #define GPIO_WT2_WT2_Pos                  (0UL)                     /*!< WT2 (Bit 0)                                           */
34223 #define GPIO_WT2_WT2_Msk                  (0xffffffffUL)            /*!< WT2 (Bitfield-Mask: 0xffffffff)                       */
34224 /* ==========================================================  WT3  ========================================================== */
34225 #define GPIO_WT3_WT3_Pos                  (0UL)                     /*!< WT3 (Bit 0)                                           */
34226 #define GPIO_WT3_WT3_Msk                  (0xffffffffUL)            /*!< WT3 (Bitfield-Mask: 0xffffffff)                       */
34227 /* =========================================================  WTS0  ========================================================== */
34228 #define GPIO_WTS0_WTS0_Pos                (0UL)                     /*!< WTS0 (Bit 0)                                          */
34229 #define GPIO_WTS0_WTS0_Msk                (0xffffffffUL)            /*!< WTS0 (Bitfield-Mask: 0xffffffff)                      */
34230 /* =========================================================  WTS1  ========================================================== */
34231 #define GPIO_WTS1_WTS1_Pos                (0UL)                     /*!< WTS1 (Bit 0)                                          */
34232 #define GPIO_WTS1_WTS1_Msk                (0xffffffffUL)            /*!< WTS1 (Bitfield-Mask: 0xffffffff)                      */
34233 /* =========================================================  WTS2  ========================================================== */
34234 #define GPIO_WTS2_WTS2_Pos                (0UL)                     /*!< WTS2 (Bit 0)                                          */
34235 #define GPIO_WTS2_WTS2_Msk                (0xffffffffUL)            /*!< WTS2 (Bitfield-Mask: 0xffffffff)                      */
34236 /* =========================================================  WTS3  ========================================================== */
34237 #define GPIO_WTS3_WTS3_Pos                (0UL)                     /*!< WTS3 (Bit 0)                                          */
34238 #define GPIO_WTS3_WTS3_Msk                (0xffffffffUL)            /*!< WTS3 (Bitfield-Mask: 0xffffffff)                      */
34239 /* =========================================================  WTC0  ========================================================== */
34240 #define GPIO_WTC0_WTC0_Pos                (0UL)                     /*!< WTC0 (Bit 0)                                          */
34241 #define GPIO_WTC0_WTC0_Msk                (0xffffffffUL)            /*!< WTC0 (Bitfield-Mask: 0xffffffff)                      */
34242 /* =========================================================  WTC1  ========================================================== */
34243 #define GPIO_WTC1_WTC1_Pos                (0UL)                     /*!< WTC1 (Bit 0)                                          */
34244 #define GPIO_WTC1_WTC1_Msk                (0xffffffffUL)            /*!< WTC1 (Bitfield-Mask: 0xffffffff)                      */
34245 /* =========================================================  WTC2  ========================================================== */
34246 #define GPIO_WTC2_WTC2_Pos                (0UL)                     /*!< WTC2 (Bit 0)                                          */
34247 #define GPIO_WTC2_WTC2_Msk                (0xffffffffUL)            /*!< WTC2 (Bitfield-Mask: 0xffffffff)                      */
34248 /* =========================================================  WTC3  ========================================================== */
34249 #define GPIO_WTC3_WTC3_Pos                (0UL)                     /*!< WTC3 (Bit 0)                                          */
34250 #define GPIO_WTC3_WTC3_Msk                (0xffffffffUL)            /*!< WTC3 (Bitfield-Mask: 0xffffffff)                      */
34251 /* ==========================================================  EN0  ========================================================== */
34252 #define GPIO_EN0_EN0_Pos                  (0UL)                     /*!< EN0 (Bit 0)                                           */
34253 #define GPIO_EN0_EN0_Msk                  (0xffffffffUL)            /*!< EN0 (Bitfield-Mask: 0xffffffff)                       */
34254 /* ==========================================================  EN1  ========================================================== */
34255 #define GPIO_EN1_EN1_Pos                  (0UL)                     /*!< EN1 (Bit 0)                                           */
34256 #define GPIO_EN1_EN1_Msk                  (0xffffffffUL)            /*!< EN1 (Bitfield-Mask: 0xffffffff)                       */
34257 /* ==========================================================  EN2  ========================================================== */
34258 #define GPIO_EN2_EN2_Pos                  (0UL)                     /*!< EN2 (Bit 0)                                           */
34259 #define GPIO_EN2_EN2_Msk                  (0xffffffffUL)            /*!< EN2 (Bitfield-Mask: 0xffffffff)                       */
34260 /* ==========================================================  EN3  ========================================================== */
34261 #define GPIO_EN3_EN3_Pos                  (0UL)                     /*!< EN3 (Bit 0)                                           */
34262 #define GPIO_EN3_EN3_Msk                  (0xffffffffUL)            /*!< EN3 (Bitfield-Mask: 0xffffffff)                       */
34263 /* =========================================================  ENS0  ========================================================== */
34264 #define GPIO_ENS0_ENS0_Pos                (0UL)                     /*!< ENS0 (Bit 0)                                          */
34265 #define GPIO_ENS0_ENS0_Msk                (0xffffffffUL)            /*!< ENS0 (Bitfield-Mask: 0xffffffff)                      */
34266 /* =========================================================  ENS1  ========================================================== */
34267 #define GPIO_ENS1_ENS1_Pos                (0UL)                     /*!< ENS1 (Bit 0)                                          */
34268 #define GPIO_ENS1_ENS1_Msk                (0xffffffffUL)            /*!< ENS1 (Bitfield-Mask: 0xffffffff)                      */
34269 /* =========================================================  ENS2  ========================================================== */
34270 #define GPIO_ENS2_ENS2_Pos                (0UL)                     /*!< ENS2 (Bit 0)                                          */
34271 #define GPIO_ENS2_ENS2_Msk                (0xffffffffUL)            /*!< ENS2 (Bitfield-Mask: 0xffffffff)                      */
34272 /* =========================================================  ENS3  ========================================================== */
34273 #define GPIO_ENS3_ENS3_Pos                (0UL)                     /*!< ENS3 (Bit 0)                                          */
34274 #define GPIO_ENS3_ENS3_Msk                (0xffffffffUL)            /*!< ENS3 (Bitfield-Mask: 0xffffffff)                      */
34275 /* =========================================================  ENC0  ========================================================== */
34276 #define GPIO_ENC0_ENC0_Pos                (0UL)                     /*!< ENC0 (Bit 0)                                          */
34277 #define GPIO_ENC0_ENC0_Msk                (0xffffffffUL)            /*!< ENC0 (Bitfield-Mask: 0xffffffff)                      */
34278 /* =========================================================  ENC1  ========================================================== */
34279 #define GPIO_ENC1_ENC1_Pos                (0UL)                     /*!< ENC1 (Bit 0)                                          */
34280 #define GPIO_ENC1_ENC1_Msk                (0xffffffffUL)            /*!< ENC1 (Bitfield-Mask: 0xffffffff)                      */
34281 /* =========================================================  ENC2  ========================================================== */
34282 #define GPIO_ENC2_ENC2_Pos                (0UL)                     /*!< ENC2 (Bit 0)                                          */
34283 #define GPIO_ENC2_ENC2_Msk                (0xffffffffUL)            /*!< ENC2 (Bitfield-Mask: 0xffffffff)                      */
34284 /* =========================================================  ENC3  ========================================================== */
34285 #define GPIO_ENC3_ENC3_Pos                (0UL)                     /*!< ENC3 (Bit 0)                                          */
34286 #define GPIO_ENC3_ENC3_Msk                (0xffffffffUL)            /*!< ENC3 (Bitfield-Mask: 0xffffffff)                      */
34287 /* ========================================================  IOM0IRQ  ======================================================== */
34288 #define GPIO_IOM0IRQ_IOM0IRQ_Pos          (0UL)                     /*!< IOM0IRQ (Bit 0)                                       */
34289 #define GPIO_IOM0IRQ_IOM0IRQ_Msk          (0x7fUL)                  /*!< IOM0IRQ (Bitfield-Mask: 0x7f)                         */
34290 /* ========================================================  IOM1IRQ  ======================================================== */
34291 #define GPIO_IOM1IRQ_IOM1IRQ_Pos          (0UL)                     /*!< IOM1IRQ (Bit 0)                                       */
34292 #define GPIO_IOM1IRQ_IOM1IRQ_Msk          (0x7fUL)                  /*!< IOM1IRQ (Bitfield-Mask: 0x7f)                         */
34293 /* ========================================================  IOM2IRQ  ======================================================== */
34294 #define GPIO_IOM2IRQ_IOM2IRQ_Pos          (0UL)                     /*!< IOM2IRQ (Bit 0)                                       */
34295 #define GPIO_IOM2IRQ_IOM2IRQ_Msk          (0x7fUL)                  /*!< IOM2IRQ (Bitfield-Mask: 0x7f)                         */
34296 /* ========================================================  IOM3IRQ  ======================================================== */
34297 #define GPIO_IOM3IRQ_IOM3IRQ_Pos          (0UL)                     /*!< IOM3IRQ (Bit 0)                                       */
34298 #define GPIO_IOM3IRQ_IOM3IRQ_Msk          (0x7fUL)                  /*!< IOM3IRQ (Bitfield-Mask: 0x7f)                         */
34299 /* ========================================================  IOM4IRQ  ======================================================== */
34300 #define GPIO_IOM4IRQ_IOM4IRQ_Pos          (0UL)                     /*!< IOM4IRQ (Bit 0)                                       */
34301 #define GPIO_IOM4IRQ_IOM4IRQ_Msk          (0x7fUL)                  /*!< IOM4IRQ (Bitfield-Mask: 0x7f)                         */
34302 /* ========================================================  IOM5IRQ  ======================================================== */
34303 #define GPIO_IOM5IRQ_IOM5IRQ_Pos          (0UL)                     /*!< IOM5IRQ (Bit 0)                                       */
34304 #define GPIO_IOM5IRQ_IOM5IRQ_Msk          (0x7fUL)                  /*!< IOM5IRQ (Bitfield-Mask: 0x7f)                         */
34305 /* ========================================================  IOM6IRQ  ======================================================== */
34306 #define GPIO_IOM6IRQ_IOM6IRQ_Pos          (0UL)                     /*!< IOM6IRQ (Bit 0)                                       */
34307 #define GPIO_IOM6IRQ_IOM6IRQ_Msk          (0x7fUL)                  /*!< IOM6IRQ (Bitfield-Mask: 0x7f)                         */
34308 /* ========================================================  IOM7IRQ  ======================================================== */
34309 #define GPIO_IOM7IRQ_IOM7IRQ_Pos          (0UL)                     /*!< IOM7IRQ (Bit 0)                                       */
34310 #define GPIO_IOM7IRQ_IOM7IRQ_Msk          (0x7fUL)                  /*!< IOM7IRQ (Bitfield-Mask: 0x7f)                         */
34311 /* =======================================================  SDIFCDWP  ======================================================== */
34312 #define GPIO_SDIFCDWP_SDIFWP_Pos          (8UL)                     /*!< SDIFWP (Bit 8)                                        */
34313 #define GPIO_SDIFCDWP_SDIFWP_Msk          (0x7f00UL)                /*!< SDIFWP (Bitfield-Mask: 0x7f)                          */
34314 #define GPIO_SDIFCDWP_SDIFCD_Pos          (0UL)                     /*!< SDIFCD (Bit 0)                                        */
34315 #define GPIO_SDIFCDWP_SDIFCD_Msk          (0x7fUL)                  /*!< SDIFCD (Bitfield-Mask: 0x7f)                          */
34316 /* ========================================================  OBSDATA  ======================================================== */
34317 #define GPIO_OBSDATA_OBSDATA_Pos          (0UL)                     /*!< OBSDATA (Bit 0)                                       */
34318 #define GPIO_OBSDATA_OBSDATA_Msk          (0xffffUL)                /*!< OBSDATA (Bitfield-Mask: 0xffff)                       */
34319 /* ========================================================  IEOBS0  ========================================================= */
34320 #define GPIO_IEOBS0_IEDATA0_Pos           (0UL)                     /*!< IEDATA0 (Bit 0)                                       */
34321 #define GPIO_IEOBS0_IEDATA0_Msk           (0xffffffffUL)            /*!< IEDATA0 (Bitfield-Mask: 0xffffffff)                   */
34322 /* ========================================================  IEOBS1  ========================================================= */
34323 #define GPIO_IEOBS1_IEDATA1_Pos           (0UL)                     /*!< IEDATA1 (Bit 0)                                       */
34324 #define GPIO_IEOBS1_IEDATA1_Msk           (0xffffffffUL)            /*!< IEDATA1 (Bitfield-Mask: 0xffffffff)                   */
34325 /* ========================================================  IEOBS2  ========================================================= */
34326 #define GPIO_IEOBS2_IEDATA2_Pos           (0UL)                     /*!< IEDATA2 (Bit 0)                                       */
34327 #define GPIO_IEOBS2_IEDATA2_Msk           (0xffffffffUL)            /*!< IEDATA2 (Bitfield-Mask: 0xffffffff)                   */
34328 /* ========================================================  IEOBS3  ========================================================= */
34329 #define GPIO_IEOBS3_IEDATA3_Pos           (0UL)                     /*!< IEDATA3 (Bit 0)                                       */
34330 #define GPIO_IEOBS3_IEDATA3_Msk           (0xffffffffUL)            /*!< IEDATA3 (Bitfield-Mask: 0xffffffff)                   */
34331 /* ========================================================  OEOBS0  ========================================================= */
34332 #define GPIO_OEOBS0_OEDATA0_Pos           (0UL)                     /*!< OEDATA0 (Bit 0)                                       */
34333 #define GPIO_OEOBS0_OEDATA0_Msk           (0xffffffffUL)            /*!< OEDATA0 (Bitfield-Mask: 0xffffffff)                   */
34334 /* ========================================================  OEOBS1  ========================================================= */
34335 #define GPIO_OEOBS1_OEDATA1_Pos           (0UL)                     /*!< OEDATA1 (Bit 0)                                       */
34336 #define GPIO_OEOBS1_OEDATA1_Msk           (0xffffffffUL)            /*!< OEDATA1 (Bitfield-Mask: 0xffffffff)                   */
34337 /* ========================================================  OEOBS2  ========================================================= */
34338 #define GPIO_OEOBS2_OEDATA2_Pos           (0UL)                     /*!< OEDATA2 (Bit 0)                                       */
34339 #define GPIO_OEOBS2_OEDATA2_Msk           (0xffffffffUL)            /*!< OEDATA2 (Bitfield-Mask: 0xffffffff)                   */
34340 /* ========================================================  OEOBS3  ========================================================= */
34341 #define GPIO_OEOBS3_OEDATA3_Pos           (0UL)                     /*!< OEDATA3 (Bit 0)                                       */
34342 #define GPIO_OEOBS3_OEDATA3_Msk           (0xffffffffUL)            /*!< OEDATA3 (Bitfield-Mask: 0xffffffff)                   */
34343 /* ======================================================  MCUN0INT0EN  ====================================================== */
34344 #define GPIO_MCUN0INT0EN_MCUN0GPIO31_Pos  (31UL)                    /*!< MCUN0GPIO31 (Bit 31)                                  */
34345 #define GPIO_MCUN0INT0EN_MCUN0GPIO31_Msk  (0x80000000UL)            /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
34346 #define GPIO_MCUN0INT0EN_MCUN0GPIO30_Pos  (30UL)                    /*!< MCUN0GPIO30 (Bit 30)                                  */
34347 #define GPIO_MCUN0INT0EN_MCUN0GPIO30_Msk  (0x40000000UL)            /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
34348 #define GPIO_MCUN0INT0EN_MCUN0GPIO29_Pos  (29UL)                    /*!< MCUN0GPIO29 (Bit 29)                                  */
34349 #define GPIO_MCUN0INT0EN_MCUN0GPIO29_Msk  (0x20000000UL)            /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
34350 #define GPIO_MCUN0INT0EN_MCUN0GPIO28_Pos  (28UL)                    /*!< MCUN0GPIO28 (Bit 28)                                  */
34351 #define GPIO_MCUN0INT0EN_MCUN0GPIO28_Msk  (0x10000000UL)            /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
34352 #define GPIO_MCUN0INT0EN_MCUN0GPIO27_Pos  (27UL)                    /*!< MCUN0GPIO27 (Bit 27)                                  */
34353 #define GPIO_MCUN0INT0EN_MCUN0GPIO27_Msk  (0x8000000UL)             /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
34354 #define GPIO_MCUN0INT0EN_MCUN0GPIO26_Pos  (26UL)                    /*!< MCUN0GPIO26 (Bit 26)                                  */
34355 #define GPIO_MCUN0INT0EN_MCUN0GPIO26_Msk  (0x4000000UL)             /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
34356 #define GPIO_MCUN0INT0EN_MCUN0GPIO25_Pos  (25UL)                    /*!< MCUN0GPIO25 (Bit 25)                                  */
34357 #define GPIO_MCUN0INT0EN_MCUN0GPIO25_Msk  (0x2000000UL)             /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
34358 #define GPIO_MCUN0INT0EN_MCUN0GPIO24_Pos  (24UL)                    /*!< MCUN0GPIO24 (Bit 24)                                  */
34359 #define GPIO_MCUN0INT0EN_MCUN0GPIO24_Msk  (0x1000000UL)             /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
34360 #define GPIO_MCUN0INT0EN_MCUN0GPIO23_Pos  (23UL)                    /*!< MCUN0GPIO23 (Bit 23)                                  */
34361 #define GPIO_MCUN0INT0EN_MCUN0GPIO23_Msk  (0x800000UL)              /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
34362 #define GPIO_MCUN0INT0EN_MCUN0GPIO22_Pos  (22UL)                    /*!< MCUN0GPIO22 (Bit 22)                                  */
34363 #define GPIO_MCUN0INT0EN_MCUN0GPIO22_Msk  (0x400000UL)              /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
34364 #define GPIO_MCUN0INT0EN_MCUN0GPIO21_Pos  (21UL)                    /*!< MCUN0GPIO21 (Bit 21)                                  */
34365 #define GPIO_MCUN0INT0EN_MCUN0GPIO21_Msk  (0x200000UL)              /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
34366 #define GPIO_MCUN0INT0EN_MCUN0GPIO20_Pos  (20UL)                    /*!< MCUN0GPIO20 (Bit 20)                                  */
34367 #define GPIO_MCUN0INT0EN_MCUN0GPIO20_Msk  (0x100000UL)              /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
34368 #define GPIO_MCUN0INT0EN_MCUN0GPIO19_Pos  (19UL)                    /*!< MCUN0GPIO19 (Bit 19)                                  */
34369 #define GPIO_MCUN0INT0EN_MCUN0GPIO19_Msk  (0x80000UL)               /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
34370 #define GPIO_MCUN0INT0EN_MCUN0GPIO18_Pos  (18UL)                    /*!< MCUN0GPIO18 (Bit 18)                                  */
34371 #define GPIO_MCUN0INT0EN_MCUN0GPIO18_Msk  (0x40000UL)               /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
34372 #define GPIO_MCUN0INT0EN_MCUN0GPIO17_Pos  (17UL)                    /*!< MCUN0GPIO17 (Bit 17)                                  */
34373 #define GPIO_MCUN0INT0EN_MCUN0GPIO17_Msk  (0x20000UL)               /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
34374 #define GPIO_MCUN0INT0EN_MCUN0GPIO16_Pos  (16UL)                    /*!< MCUN0GPIO16 (Bit 16)                                  */
34375 #define GPIO_MCUN0INT0EN_MCUN0GPIO16_Msk  (0x10000UL)               /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
34376 #define GPIO_MCUN0INT0EN_MCUN0GPIO15_Pos  (15UL)                    /*!< MCUN0GPIO15 (Bit 15)                                  */
34377 #define GPIO_MCUN0INT0EN_MCUN0GPIO15_Msk  (0x8000UL)                /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
34378 #define GPIO_MCUN0INT0EN_MCUN0GPIO14_Pos  (14UL)                    /*!< MCUN0GPIO14 (Bit 14)                                  */
34379 #define GPIO_MCUN0INT0EN_MCUN0GPIO14_Msk  (0x4000UL)                /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
34380 #define GPIO_MCUN0INT0EN_MCUN0GPIO13_Pos  (13UL)                    /*!< MCUN0GPIO13 (Bit 13)                                  */
34381 #define GPIO_MCUN0INT0EN_MCUN0GPIO13_Msk  (0x2000UL)                /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
34382 #define GPIO_MCUN0INT0EN_MCUN0GPIO12_Pos  (12UL)                    /*!< MCUN0GPIO12 (Bit 12)                                  */
34383 #define GPIO_MCUN0INT0EN_MCUN0GPIO12_Msk  (0x1000UL)                /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
34384 #define GPIO_MCUN0INT0EN_MCUN0GPIO11_Pos  (11UL)                    /*!< MCUN0GPIO11 (Bit 11)                                  */
34385 #define GPIO_MCUN0INT0EN_MCUN0GPIO11_Msk  (0x800UL)                 /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
34386 #define GPIO_MCUN0INT0EN_MCUN0GPIO10_Pos  (10UL)                    /*!< MCUN0GPIO10 (Bit 10)                                  */
34387 #define GPIO_MCUN0INT0EN_MCUN0GPIO10_Msk  (0x400UL)                 /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
34388 #define GPIO_MCUN0INT0EN_MCUN0GPIO9_Pos   (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
34389 #define GPIO_MCUN0INT0EN_MCUN0GPIO9_Msk   (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
34390 #define GPIO_MCUN0INT0EN_MCUN0GPIO8_Pos   (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
34391 #define GPIO_MCUN0INT0EN_MCUN0GPIO8_Msk   (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
34392 #define GPIO_MCUN0INT0EN_MCUN0GPIO7_Pos   (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
34393 #define GPIO_MCUN0INT0EN_MCUN0GPIO7_Msk   (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
34394 #define GPIO_MCUN0INT0EN_MCUN0GPIO6_Pos   (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
34395 #define GPIO_MCUN0INT0EN_MCUN0GPIO6_Msk   (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
34396 #define GPIO_MCUN0INT0EN_MCUN0GPIO5_Pos   (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
34397 #define GPIO_MCUN0INT0EN_MCUN0GPIO5_Msk   (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
34398 #define GPIO_MCUN0INT0EN_MCUN0GPIO4_Pos   (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
34399 #define GPIO_MCUN0INT0EN_MCUN0GPIO4_Msk   (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
34400 #define GPIO_MCUN0INT0EN_MCUN0GPIO3_Pos   (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
34401 #define GPIO_MCUN0INT0EN_MCUN0GPIO3_Msk   (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
34402 #define GPIO_MCUN0INT0EN_MCUN0GPIO2_Pos   (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
34403 #define GPIO_MCUN0INT0EN_MCUN0GPIO2_Msk   (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
34404 #define GPIO_MCUN0INT0EN_MCUN0GPIO1_Pos   (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
34405 #define GPIO_MCUN0INT0EN_MCUN0GPIO1_Msk   (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
34406 #define GPIO_MCUN0INT0EN_MCUN0GPIO0_Pos   (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
34407 #define GPIO_MCUN0INT0EN_MCUN0GPIO0_Msk   (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
34408 /* =====================================================  MCUN0INT0STAT  ===================================================== */
34409 #define GPIO_MCUN0INT0STAT_MCUN0GPIO31_Pos (31UL)                   /*!< MCUN0GPIO31 (Bit 31)                                  */
34410 #define GPIO_MCUN0INT0STAT_MCUN0GPIO31_Msk (0x80000000UL)           /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
34411 #define GPIO_MCUN0INT0STAT_MCUN0GPIO30_Pos (30UL)                   /*!< MCUN0GPIO30 (Bit 30)                                  */
34412 #define GPIO_MCUN0INT0STAT_MCUN0GPIO30_Msk (0x40000000UL)           /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
34413 #define GPIO_MCUN0INT0STAT_MCUN0GPIO29_Pos (29UL)                   /*!< MCUN0GPIO29 (Bit 29)                                  */
34414 #define GPIO_MCUN0INT0STAT_MCUN0GPIO29_Msk (0x20000000UL)           /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
34415 #define GPIO_MCUN0INT0STAT_MCUN0GPIO28_Pos (28UL)                   /*!< MCUN0GPIO28 (Bit 28)                                  */
34416 #define GPIO_MCUN0INT0STAT_MCUN0GPIO28_Msk (0x10000000UL)           /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
34417 #define GPIO_MCUN0INT0STAT_MCUN0GPIO27_Pos (27UL)                   /*!< MCUN0GPIO27 (Bit 27)                                  */
34418 #define GPIO_MCUN0INT0STAT_MCUN0GPIO27_Msk (0x8000000UL)            /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
34419 #define GPIO_MCUN0INT0STAT_MCUN0GPIO26_Pos (26UL)                   /*!< MCUN0GPIO26 (Bit 26)                                  */
34420 #define GPIO_MCUN0INT0STAT_MCUN0GPIO26_Msk (0x4000000UL)            /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
34421 #define GPIO_MCUN0INT0STAT_MCUN0GPIO25_Pos (25UL)                   /*!< MCUN0GPIO25 (Bit 25)                                  */
34422 #define GPIO_MCUN0INT0STAT_MCUN0GPIO25_Msk (0x2000000UL)            /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
34423 #define GPIO_MCUN0INT0STAT_MCUN0GPIO24_Pos (24UL)                   /*!< MCUN0GPIO24 (Bit 24)                                  */
34424 #define GPIO_MCUN0INT0STAT_MCUN0GPIO24_Msk (0x1000000UL)            /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
34425 #define GPIO_MCUN0INT0STAT_MCUN0GPIO23_Pos (23UL)                   /*!< MCUN0GPIO23 (Bit 23)                                  */
34426 #define GPIO_MCUN0INT0STAT_MCUN0GPIO23_Msk (0x800000UL)             /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
34427 #define GPIO_MCUN0INT0STAT_MCUN0GPIO22_Pos (22UL)                   /*!< MCUN0GPIO22 (Bit 22)                                  */
34428 #define GPIO_MCUN0INT0STAT_MCUN0GPIO22_Msk (0x400000UL)             /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
34429 #define GPIO_MCUN0INT0STAT_MCUN0GPIO21_Pos (21UL)                   /*!< MCUN0GPIO21 (Bit 21)                                  */
34430 #define GPIO_MCUN0INT0STAT_MCUN0GPIO21_Msk (0x200000UL)             /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
34431 #define GPIO_MCUN0INT0STAT_MCUN0GPIO20_Pos (20UL)                   /*!< MCUN0GPIO20 (Bit 20)                                  */
34432 #define GPIO_MCUN0INT0STAT_MCUN0GPIO20_Msk (0x100000UL)             /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
34433 #define GPIO_MCUN0INT0STAT_MCUN0GPIO19_Pos (19UL)                   /*!< MCUN0GPIO19 (Bit 19)                                  */
34434 #define GPIO_MCUN0INT0STAT_MCUN0GPIO19_Msk (0x80000UL)              /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
34435 #define GPIO_MCUN0INT0STAT_MCUN0GPIO18_Pos (18UL)                   /*!< MCUN0GPIO18 (Bit 18)                                  */
34436 #define GPIO_MCUN0INT0STAT_MCUN0GPIO18_Msk (0x40000UL)              /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
34437 #define GPIO_MCUN0INT0STAT_MCUN0GPIO17_Pos (17UL)                   /*!< MCUN0GPIO17 (Bit 17)                                  */
34438 #define GPIO_MCUN0INT0STAT_MCUN0GPIO17_Msk (0x20000UL)              /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
34439 #define GPIO_MCUN0INT0STAT_MCUN0GPIO16_Pos (16UL)                   /*!< MCUN0GPIO16 (Bit 16)                                  */
34440 #define GPIO_MCUN0INT0STAT_MCUN0GPIO16_Msk (0x10000UL)              /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
34441 #define GPIO_MCUN0INT0STAT_MCUN0GPIO15_Pos (15UL)                   /*!< MCUN0GPIO15 (Bit 15)                                  */
34442 #define GPIO_MCUN0INT0STAT_MCUN0GPIO15_Msk (0x8000UL)               /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
34443 #define GPIO_MCUN0INT0STAT_MCUN0GPIO14_Pos (14UL)                   /*!< MCUN0GPIO14 (Bit 14)                                  */
34444 #define GPIO_MCUN0INT0STAT_MCUN0GPIO14_Msk (0x4000UL)               /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
34445 #define GPIO_MCUN0INT0STAT_MCUN0GPIO13_Pos (13UL)                   /*!< MCUN0GPIO13 (Bit 13)                                  */
34446 #define GPIO_MCUN0INT0STAT_MCUN0GPIO13_Msk (0x2000UL)               /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
34447 #define GPIO_MCUN0INT0STAT_MCUN0GPIO12_Pos (12UL)                   /*!< MCUN0GPIO12 (Bit 12)                                  */
34448 #define GPIO_MCUN0INT0STAT_MCUN0GPIO12_Msk (0x1000UL)               /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
34449 #define GPIO_MCUN0INT0STAT_MCUN0GPIO11_Pos (11UL)                   /*!< MCUN0GPIO11 (Bit 11)                                  */
34450 #define GPIO_MCUN0INT0STAT_MCUN0GPIO11_Msk (0x800UL)                /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
34451 #define GPIO_MCUN0INT0STAT_MCUN0GPIO10_Pos (10UL)                   /*!< MCUN0GPIO10 (Bit 10)                                  */
34452 #define GPIO_MCUN0INT0STAT_MCUN0GPIO10_Msk (0x400UL)                /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
34453 #define GPIO_MCUN0INT0STAT_MCUN0GPIO9_Pos (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
34454 #define GPIO_MCUN0INT0STAT_MCUN0GPIO9_Msk (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
34455 #define GPIO_MCUN0INT0STAT_MCUN0GPIO8_Pos (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
34456 #define GPIO_MCUN0INT0STAT_MCUN0GPIO8_Msk (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
34457 #define GPIO_MCUN0INT0STAT_MCUN0GPIO7_Pos (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
34458 #define GPIO_MCUN0INT0STAT_MCUN0GPIO7_Msk (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
34459 #define GPIO_MCUN0INT0STAT_MCUN0GPIO6_Pos (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
34460 #define GPIO_MCUN0INT0STAT_MCUN0GPIO6_Msk (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
34461 #define GPIO_MCUN0INT0STAT_MCUN0GPIO5_Pos (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
34462 #define GPIO_MCUN0INT0STAT_MCUN0GPIO5_Msk (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
34463 #define GPIO_MCUN0INT0STAT_MCUN0GPIO4_Pos (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
34464 #define GPIO_MCUN0INT0STAT_MCUN0GPIO4_Msk (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
34465 #define GPIO_MCUN0INT0STAT_MCUN0GPIO3_Pos (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
34466 #define GPIO_MCUN0INT0STAT_MCUN0GPIO3_Msk (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
34467 #define GPIO_MCUN0INT0STAT_MCUN0GPIO2_Pos (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
34468 #define GPIO_MCUN0INT0STAT_MCUN0GPIO2_Msk (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
34469 #define GPIO_MCUN0INT0STAT_MCUN0GPIO1_Pos (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
34470 #define GPIO_MCUN0INT0STAT_MCUN0GPIO1_Msk (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
34471 #define GPIO_MCUN0INT0STAT_MCUN0GPIO0_Pos (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
34472 #define GPIO_MCUN0INT0STAT_MCUN0GPIO0_Msk (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
34473 /* =====================================================  MCUN0INT0CLR  ====================================================== */
34474 #define GPIO_MCUN0INT0CLR_MCUN0GPIO31_Pos (31UL)                    /*!< MCUN0GPIO31 (Bit 31)                                  */
34475 #define GPIO_MCUN0INT0CLR_MCUN0GPIO31_Msk (0x80000000UL)            /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
34476 #define GPIO_MCUN0INT0CLR_MCUN0GPIO30_Pos (30UL)                    /*!< MCUN0GPIO30 (Bit 30)                                  */
34477 #define GPIO_MCUN0INT0CLR_MCUN0GPIO30_Msk (0x40000000UL)            /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
34478 #define GPIO_MCUN0INT0CLR_MCUN0GPIO29_Pos (29UL)                    /*!< MCUN0GPIO29 (Bit 29)                                  */
34479 #define GPIO_MCUN0INT0CLR_MCUN0GPIO29_Msk (0x20000000UL)            /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
34480 #define GPIO_MCUN0INT0CLR_MCUN0GPIO28_Pos (28UL)                    /*!< MCUN0GPIO28 (Bit 28)                                  */
34481 #define GPIO_MCUN0INT0CLR_MCUN0GPIO28_Msk (0x10000000UL)            /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
34482 #define GPIO_MCUN0INT0CLR_MCUN0GPIO27_Pos (27UL)                    /*!< MCUN0GPIO27 (Bit 27)                                  */
34483 #define GPIO_MCUN0INT0CLR_MCUN0GPIO27_Msk (0x8000000UL)             /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
34484 #define GPIO_MCUN0INT0CLR_MCUN0GPIO26_Pos (26UL)                    /*!< MCUN0GPIO26 (Bit 26)                                  */
34485 #define GPIO_MCUN0INT0CLR_MCUN0GPIO26_Msk (0x4000000UL)             /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
34486 #define GPIO_MCUN0INT0CLR_MCUN0GPIO25_Pos (25UL)                    /*!< MCUN0GPIO25 (Bit 25)                                  */
34487 #define GPIO_MCUN0INT0CLR_MCUN0GPIO25_Msk (0x2000000UL)             /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
34488 #define GPIO_MCUN0INT0CLR_MCUN0GPIO24_Pos (24UL)                    /*!< MCUN0GPIO24 (Bit 24)                                  */
34489 #define GPIO_MCUN0INT0CLR_MCUN0GPIO24_Msk (0x1000000UL)             /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
34490 #define GPIO_MCUN0INT0CLR_MCUN0GPIO23_Pos (23UL)                    /*!< MCUN0GPIO23 (Bit 23)                                  */
34491 #define GPIO_MCUN0INT0CLR_MCUN0GPIO23_Msk (0x800000UL)              /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
34492 #define GPIO_MCUN0INT0CLR_MCUN0GPIO22_Pos (22UL)                    /*!< MCUN0GPIO22 (Bit 22)                                  */
34493 #define GPIO_MCUN0INT0CLR_MCUN0GPIO22_Msk (0x400000UL)              /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
34494 #define GPIO_MCUN0INT0CLR_MCUN0GPIO21_Pos (21UL)                    /*!< MCUN0GPIO21 (Bit 21)                                  */
34495 #define GPIO_MCUN0INT0CLR_MCUN0GPIO21_Msk (0x200000UL)              /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
34496 #define GPIO_MCUN0INT0CLR_MCUN0GPIO20_Pos (20UL)                    /*!< MCUN0GPIO20 (Bit 20)                                  */
34497 #define GPIO_MCUN0INT0CLR_MCUN0GPIO20_Msk (0x100000UL)              /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
34498 #define GPIO_MCUN0INT0CLR_MCUN0GPIO19_Pos (19UL)                    /*!< MCUN0GPIO19 (Bit 19)                                  */
34499 #define GPIO_MCUN0INT0CLR_MCUN0GPIO19_Msk (0x80000UL)               /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
34500 #define GPIO_MCUN0INT0CLR_MCUN0GPIO18_Pos (18UL)                    /*!< MCUN0GPIO18 (Bit 18)                                  */
34501 #define GPIO_MCUN0INT0CLR_MCUN0GPIO18_Msk (0x40000UL)               /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
34502 #define GPIO_MCUN0INT0CLR_MCUN0GPIO17_Pos (17UL)                    /*!< MCUN0GPIO17 (Bit 17)                                  */
34503 #define GPIO_MCUN0INT0CLR_MCUN0GPIO17_Msk (0x20000UL)               /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
34504 #define GPIO_MCUN0INT0CLR_MCUN0GPIO16_Pos (16UL)                    /*!< MCUN0GPIO16 (Bit 16)                                  */
34505 #define GPIO_MCUN0INT0CLR_MCUN0GPIO16_Msk (0x10000UL)               /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
34506 #define GPIO_MCUN0INT0CLR_MCUN0GPIO15_Pos (15UL)                    /*!< MCUN0GPIO15 (Bit 15)                                  */
34507 #define GPIO_MCUN0INT0CLR_MCUN0GPIO15_Msk (0x8000UL)                /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
34508 #define GPIO_MCUN0INT0CLR_MCUN0GPIO14_Pos (14UL)                    /*!< MCUN0GPIO14 (Bit 14)                                  */
34509 #define GPIO_MCUN0INT0CLR_MCUN0GPIO14_Msk (0x4000UL)                /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
34510 #define GPIO_MCUN0INT0CLR_MCUN0GPIO13_Pos (13UL)                    /*!< MCUN0GPIO13 (Bit 13)                                  */
34511 #define GPIO_MCUN0INT0CLR_MCUN0GPIO13_Msk (0x2000UL)                /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
34512 #define GPIO_MCUN0INT0CLR_MCUN0GPIO12_Pos (12UL)                    /*!< MCUN0GPIO12 (Bit 12)                                  */
34513 #define GPIO_MCUN0INT0CLR_MCUN0GPIO12_Msk (0x1000UL)                /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
34514 #define GPIO_MCUN0INT0CLR_MCUN0GPIO11_Pos (11UL)                    /*!< MCUN0GPIO11 (Bit 11)                                  */
34515 #define GPIO_MCUN0INT0CLR_MCUN0GPIO11_Msk (0x800UL)                 /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
34516 #define GPIO_MCUN0INT0CLR_MCUN0GPIO10_Pos (10UL)                    /*!< MCUN0GPIO10 (Bit 10)                                  */
34517 #define GPIO_MCUN0INT0CLR_MCUN0GPIO10_Msk (0x400UL)                 /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
34518 #define GPIO_MCUN0INT0CLR_MCUN0GPIO9_Pos  (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
34519 #define GPIO_MCUN0INT0CLR_MCUN0GPIO9_Msk  (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
34520 #define GPIO_MCUN0INT0CLR_MCUN0GPIO8_Pos  (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
34521 #define GPIO_MCUN0INT0CLR_MCUN0GPIO8_Msk  (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
34522 #define GPIO_MCUN0INT0CLR_MCUN0GPIO7_Pos  (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
34523 #define GPIO_MCUN0INT0CLR_MCUN0GPIO7_Msk  (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
34524 #define GPIO_MCUN0INT0CLR_MCUN0GPIO6_Pos  (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
34525 #define GPIO_MCUN0INT0CLR_MCUN0GPIO6_Msk  (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
34526 #define GPIO_MCUN0INT0CLR_MCUN0GPIO5_Pos  (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
34527 #define GPIO_MCUN0INT0CLR_MCUN0GPIO5_Msk  (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
34528 #define GPIO_MCUN0INT0CLR_MCUN0GPIO4_Pos  (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
34529 #define GPIO_MCUN0INT0CLR_MCUN0GPIO4_Msk  (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
34530 #define GPIO_MCUN0INT0CLR_MCUN0GPIO3_Pos  (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
34531 #define GPIO_MCUN0INT0CLR_MCUN0GPIO3_Msk  (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
34532 #define GPIO_MCUN0INT0CLR_MCUN0GPIO2_Pos  (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
34533 #define GPIO_MCUN0INT0CLR_MCUN0GPIO2_Msk  (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
34534 #define GPIO_MCUN0INT0CLR_MCUN0GPIO1_Pos  (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
34535 #define GPIO_MCUN0INT0CLR_MCUN0GPIO1_Msk  (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
34536 #define GPIO_MCUN0INT0CLR_MCUN0GPIO0_Pos  (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
34537 #define GPIO_MCUN0INT0CLR_MCUN0GPIO0_Msk  (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
34538 /* =====================================================  MCUN0INT0SET  ====================================================== */
34539 #define GPIO_MCUN0INT0SET_MCUN0GPIO31_Pos (31UL)                    /*!< MCUN0GPIO31 (Bit 31)                                  */
34540 #define GPIO_MCUN0INT0SET_MCUN0GPIO31_Msk (0x80000000UL)            /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
34541 #define GPIO_MCUN0INT0SET_MCUN0GPIO30_Pos (30UL)                    /*!< MCUN0GPIO30 (Bit 30)                                  */
34542 #define GPIO_MCUN0INT0SET_MCUN0GPIO30_Msk (0x40000000UL)            /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
34543 #define GPIO_MCUN0INT0SET_MCUN0GPIO29_Pos (29UL)                    /*!< MCUN0GPIO29 (Bit 29)                                  */
34544 #define GPIO_MCUN0INT0SET_MCUN0GPIO29_Msk (0x20000000UL)            /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
34545 #define GPIO_MCUN0INT0SET_MCUN0GPIO28_Pos (28UL)                    /*!< MCUN0GPIO28 (Bit 28)                                  */
34546 #define GPIO_MCUN0INT0SET_MCUN0GPIO28_Msk (0x10000000UL)            /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
34547 #define GPIO_MCUN0INT0SET_MCUN0GPIO27_Pos (27UL)                    /*!< MCUN0GPIO27 (Bit 27)                                  */
34548 #define GPIO_MCUN0INT0SET_MCUN0GPIO27_Msk (0x8000000UL)             /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
34549 #define GPIO_MCUN0INT0SET_MCUN0GPIO26_Pos (26UL)                    /*!< MCUN0GPIO26 (Bit 26)                                  */
34550 #define GPIO_MCUN0INT0SET_MCUN0GPIO26_Msk (0x4000000UL)             /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
34551 #define GPIO_MCUN0INT0SET_MCUN0GPIO25_Pos (25UL)                    /*!< MCUN0GPIO25 (Bit 25)                                  */
34552 #define GPIO_MCUN0INT0SET_MCUN0GPIO25_Msk (0x2000000UL)             /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
34553 #define GPIO_MCUN0INT0SET_MCUN0GPIO24_Pos (24UL)                    /*!< MCUN0GPIO24 (Bit 24)                                  */
34554 #define GPIO_MCUN0INT0SET_MCUN0GPIO24_Msk (0x1000000UL)             /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
34555 #define GPIO_MCUN0INT0SET_MCUN0GPIO23_Pos (23UL)                    /*!< MCUN0GPIO23 (Bit 23)                                  */
34556 #define GPIO_MCUN0INT0SET_MCUN0GPIO23_Msk (0x800000UL)              /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
34557 #define GPIO_MCUN0INT0SET_MCUN0GPIO22_Pos (22UL)                    /*!< MCUN0GPIO22 (Bit 22)                                  */
34558 #define GPIO_MCUN0INT0SET_MCUN0GPIO22_Msk (0x400000UL)              /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
34559 #define GPIO_MCUN0INT0SET_MCUN0GPIO21_Pos (21UL)                    /*!< MCUN0GPIO21 (Bit 21)                                  */
34560 #define GPIO_MCUN0INT0SET_MCUN0GPIO21_Msk (0x200000UL)              /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
34561 #define GPIO_MCUN0INT0SET_MCUN0GPIO20_Pos (20UL)                    /*!< MCUN0GPIO20 (Bit 20)                                  */
34562 #define GPIO_MCUN0INT0SET_MCUN0GPIO20_Msk (0x100000UL)              /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
34563 #define GPIO_MCUN0INT0SET_MCUN0GPIO19_Pos (19UL)                    /*!< MCUN0GPIO19 (Bit 19)                                  */
34564 #define GPIO_MCUN0INT0SET_MCUN0GPIO19_Msk (0x80000UL)               /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
34565 #define GPIO_MCUN0INT0SET_MCUN0GPIO18_Pos (18UL)                    /*!< MCUN0GPIO18 (Bit 18)                                  */
34566 #define GPIO_MCUN0INT0SET_MCUN0GPIO18_Msk (0x40000UL)               /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
34567 #define GPIO_MCUN0INT0SET_MCUN0GPIO17_Pos (17UL)                    /*!< MCUN0GPIO17 (Bit 17)                                  */
34568 #define GPIO_MCUN0INT0SET_MCUN0GPIO17_Msk (0x20000UL)               /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
34569 #define GPIO_MCUN0INT0SET_MCUN0GPIO16_Pos (16UL)                    /*!< MCUN0GPIO16 (Bit 16)                                  */
34570 #define GPIO_MCUN0INT0SET_MCUN0GPIO16_Msk (0x10000UL)               /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
34571 #define GPIO_MCUN0INT0SET_MCUN0GPIO15_Pos (15UL)                    /*!< MCUN0GPIO15 (Bit 15)                                  */
34572 #define GPIO_MCUN0INT0SET_MCUN0GPIO15_Msk (0x8000UL)                /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
34573 #define GPIO_MCUN0INT0SET_MCUN0GPIO14_Pos (14UL)                    /*!< MCUN0GPIO14 (Bit 14)                                  */
34574 #define GPIO_MCUN0INT0SET_MCUN0GPIO14_Msk (0x4000UL)                /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
34575 #define GPIO_MCUN0INT0SET_MCUN0GPIO13_Pos (13UL)                    /*!< MCUN0GPIO13 (Bit 13)                                  */
34576 #define GPIO_MCUN0INT0SET_MCUN0GPIO13_Msk (0x2000UL)                /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
34577 #define GPIO_MCUN0INT0SET_MCUN0GPIO12_Pos (12UL)                    /*!< MCUN0GPIO12 (Bit 12)                                  */
34578 #define GPIO_MCUN0INT0SET_MCUN0GPIO12_Msk (0x1000UL)                /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
34579 #define GPIO_MCUN0INT0SET_MCUN0GPIO11_Pos (11UL)                    /*!< MCUN0GPIO11 (Bit 11)                                  */
34580 #define GPIO_MCUN0INT0SET_MCUN0GPIO11_Msk (0x800UL)                 /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
34581 #define GPIO_MCUN0INT0SET_MCUN0GPIO10_Pos (10UL)                    /*!< MCUN0GPIO10 (Bit 10)                                  */
34582 #define GPIO_MCUN0INT0SET_MCUN0GPIO10_Msk (0x400UL)                 /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
34583 #define GPIO_MCUN0INT0SET_MCUN0GPIO9_Pos  (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
34584 #define GPIO_MCUN0INT0SET_MCUN0GPIO9_Msk  (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
34585 #define GPIO_MCUN0INT0SET_MCUN0GPIO8_Pos  (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
34586 #define GPIO_MCUN0INT0SET_MCUN0GPIO8_Msk  (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
34587 #define GPIO_MCUN0INT0SET_MCUN0GPIO7_Pos  (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
34588 #define GPIO_MCUN0INT0SET_MCUN0GPIO7_Msk  (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
34589 #define GPIO_MCUN0INT0SET_MCUN0GPIO6_Pos  (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
34590 #define GPIO_MCUN0INT0SET_MCUN0GPIO6_Msk  (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
34591 #define GPIO_MCUN0INT0SET_MCUN0GPIO5_Pos  (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
34592 #define GPIO_MCUN0INT0SET_MCUN0GPIO5_Msk  (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
34593 #define GPIO_MCUN0INT0SET_MCUN0GPIO4_Pos  (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
34594 #define GPIO_MCUN0INT0SET_MCUN0GPIO4_Msk  (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
34595 #define GPIO_MCUN0INT0SET_MCUN0GPIO3_Pos  (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
34596 #define GPIO_MCUN0INT0SET_MCUN0GPIO3_Msk  (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
34597 #define GPIO_MCUN0INT0SET_MCUN0GPIO2_Pos  (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
34598 #define GPIO_MCUN0INT0SET_MCUN0GPIO2_Msk  (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
34599 #define GPIO_MCUN0INT0SET_MCUN0GPIO1_Pos  (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
34600 #define GPIO_MCUN0INT0SET_MCUN0GPIO1_Msk  (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
34601 #define GPIO_MCUN0INT0SET_MCUN0GPIO0_Pos  (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
34602 #define GPIO_MCUN0INT0SET_MCUN0GPIO0_Msk  (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
34603 /* ======================================================  MCUN0INT1EN  ====================================================== */
34604 #define GPIO_MCUN0INT1EN_MCUN0GPIO63_Pos  (31UL)                    /*!< MCUN0GPIO63 (Bit 31)                                  */
34605 #define GPIO_MCUN0INT1EN_MCUN0GPIO63_Msk  (0x80000000UL)            /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
34606 #define GPIO_MCUN0INT1EN_MCUN0GPIO62_Pos  (30UL)                    /*!< MCUN0GPIO62 (Bit 30)                                  */
34607 #define GPIO_MCUN0INT1EN_MCUN0GPIO62_Msk  (0x40000000UL)            /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
34608 #define GPIO_MCUN0INT1EN_MCUN0GPIO61_Pos  (29UL)                    /*!< MCUN0GPIO61 (Bit 29)                                  */
34609 #define GPIO_MCUN0INT1EN_MCUN0GPIO61_Msk  (0x20000000UL)            /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
34610 #define GPIO_MCUN0INT1EN_MCUN0GPIO60_Pos  (28UL)                    /*!< MCUN0GPIO60 (Bit 28)                                  */
34611 #define GPIO_MCUN0INT1EN_MCUN0GPIO60_Msk  (0x10000000UL)            /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
34612 #define GPIO_MCUN0INT1EN_MCUN0GPIO59_Pos  (27UL)                    /*!< MCUN0GPIO59 (Bit 27)                                  */
34613 #define GPIO_MCUN0INT1EN_MCUN0GPIO59_Msk  (0x8000000UL)             /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
34614 #define GPIO_MCUN0INT1EN_MCUN0GPIO58_Pos  (26UL)                    /*!< MCUN0GPIO58 (Bit 26)                                  */
34615 #define GPIO_MCUN0INT1EN_MCUN0GPIO58_Msk  (0x4000000UL)             /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
34616 #define GPIO_MCUN0INT1EN_MCUN0GPIO57_Pos  (25UL)                    /*!< MCUN0GPIO57 (Bit 25)                                  */
34617 #define GPIO_MCUN0INT1EN_MCUN0GPIO57_Msk  (0x2000000UL)             /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
34618 #define GPIO_MCUN0INT1EN_MCUN0GPIO56_Pos  (24UL)                    /*!< MCUN0GPIO56 (Bit 24)                                  */
34619 #define GPIO_MCUN0INT1EN_MCUN0GPIO56_Msk  (0x1000000UL)             /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
34620 #define GPIO_MCUN0INT1EN_MCUN0GPIO55_Pos  (23UL)                    /*!< MCUN0GPIO55 (Bit 23)                                  */
34621 #define GPIO_MCUN0INT1EN_MCUN0GPIO55_Msk  (0x800000UL)              /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
34622 #define GPIO_MCUN0INT1EN_MCUN0GPIO54_Pos  (22UL)                    /*!< MCUN0GPIO54 (Bit 22)                                  */
34623 #define GPIO_MCUN0INT1EN_MCUN0GPIO54_Msk  (0x400000UL)              /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
34624 #define GPIO_MCUN0INT1EN_MCUN0GPIO53_Pos  (21UL)                    /*!< MCUN0GPIO53 (Bit 21)                                  */
34625 #define GPIO_MCUN0INT1EN_MCUN0GPIO53_Msk  (0x200000UL)              /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
34626 #define GPIO_MCUN0INT1EN_MCUN0GPIO52_Pos  (20UL)                    /*!< MCUN0GPIO52 (Bit 20)                                  */
34627 #define GPIO_MCUN0INT1EN_MCUN0GPIO52_Msk  (0x100000UL)              /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
34628 #define GPIO_MCUN0INT1EN_MCUN0GPIO51_Pos  (19UL)                    /*!< MCUN0GPIO51 (Bit 19)                                  */
34629 #define GPIO_MCUN0INT1EN_MCUN0GPIO51_Msk  (0x80000UL)               /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
34630 #define GPIO_MCUN0INT1EN_MCUN0GPIO50_Pos  (18UL)                    /*!< MCUN0GPIO50 (Bit 18)                                  */
34631 #define GPIO_MCUN0INT1EN_MCUN0GPIO50_Msk  (0x40000UL)               /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
34632 #define GPIO_MCUN0INT1EN_MCUN0GPIO49_Pos  (17UL)                    /*!< MCUN0GPIO49 (Bit 17)                                  */
34633 #define GPIO_MCUN0INT1EN_MCUN0GPIO49_Msk  (0x20000UL)               /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
34634 #define GPIO_MCUN0INT1EN_MCUN0GPIO48_Pos  (16UL)                    /*!< MCUN0GPIO48 (Bit 16)                                  */
34635 #define GPIO_MCUN0INT1EN_MCUN0GPIO48_Msk  (0x10000UL)               /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
34636 #define GPIO_MCUN0INT1EN_MCUN0GPIO47_Pos  (15UL)                    /*!< MCUN0GPIO47 (Bit 15)                                  */
34637 #define GPIO_MCUN0INT1EN_MCUN0GPIO47_Msk  (0x8000UL)                /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
34638 #define GPIO_MCUN0INT1EN_MCUN0GPIO46_Pos  (14UL)                    /*!< MCUN0GPIO46 (Bit 14)                                  */
34639 #define GPIO_MCUN0INT1EN_MCUN0GPIO46_Msk  (0x4000UL)                /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
34640 #define GPIO_MCUN0INT1EN_MCUN0GPIO45_Pos  (13UL)                    /*!< MCUN0GPIO45 (Bit 13)                                  */
34641 #define GPIO_MCUN0INT1EN_MCUN0GPIO45_Msk  (0x2000UL)                /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
34642 #define GPIO_MCUN0INT1EN_MCUN0GPIO44_Pos  (12UL)                    /*!< MCUN0GPIO44 (Bit 12)                                  */
34643 #define GPIO_MCUN0INT1EN_MCUN0GPIO44_Msk  (0x1000UL)                /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
34644 #define GPIO_MCUN0INT1EN_MCUN0GPIO43_Pos  (11UL)                    /*!< MCUN0GPIO43 (Bit 11)                                  */
34645 #define GPIO_MCUN0INT1EN_MCUN0GPIO43_Msk  (0x800UL)                 /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
34646 #define GPIO_MCUN0INT1EN_MCUN0GPIO42_Pos  (10UL)                    /*!< MCUN0GPIO42 (Bit 10)                                  */
34647 #define GPIO_MCUN0INT1EN_MCUN0GPIO42_Msk  (0x400UL)                 /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
34648 #define GPIO_MCUN0INT1EN_MCUN0GPIO41_Pos  (9UL)                     /*!< MCUN0GPIO41 (Bit 9)                                   */
34649 #define GPIO_MCUN0INT1EN_MCUN0GPIO41_Msk  (0x200UL)                 /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
34650 #define GPIO_MCUN0INT1EN_MCUN0GPIO40_Pos  (8UL)                     /*!< MCUN0GPIO40 (Bit 8)                                   */
34651 #define GPIO_MCUN0INT1EN_MCUN0GPIO40_Msk  (0x100UL)                 /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
34652 #define GPIO_MCUN0INT1EN_MCUN0GPIO39_Pos  (7UL)                     /*!< MCUN0GPIO39 (Bit 7)                                   */
34653 #define GPIO_MCUN0INT1EN_MCUN0GPIO39_Msk  (0x80UL)                  /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
34654 #define GPIO_MCUN0INT1EN_MCUN0GPIO38_Pos  (6UL)                     /*!< MCUN0GPIO38 (Bit 6)                                   */
34655 #define GPIO_MCUN0INT1EN_MCUN0GPIO38_Msk  (0x40UL)                  /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
34656 #define GPIO_MCUN0INT1EN_MCUN0GPIO37_Pos  (5UL)                     /*!< MCUN0GPIO37 (Bit 5)                                   */
34657 #define GPIO_MCUN0INT1EN_MCUN0GPIO37_Msk  (0x20UL)                  /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
34658 #define GPIO_MCUN0INT1EN_MCUN0GPIO36_Pos  (4UL)                     /*!< MCUN0GPIO36 (Bit 4)                                   */
34659 #define GPIO_MCUN0INT1EN_MCUN0GPIO36_Msk  (0x10UL)                  /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
34660 #define GPIO_MCUN0INT1EN_MCUN0GPIO35_Pos  (3UL)                     /*!< MCUN0GPIO35 (Bit 3)                                   */
34661 #define GPIO_MCUN0INT1EN_MCUN0GPIO35_Msk  (0x8UL)                   /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
34662 #define GPIO_MCUN0INT1EN_MCUN0GPIO34_Pos  (2UL)                     /*!< MCUN0GPIO34 (Bit 2)                                   */
34663 #define GPIO_MCUN0INT1EN_MCUN0GPIO34_Msk  (0x4UL)                   /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
34664 #define GPIO_MCUN0INT1EN_MCUN0GPIO33_Pos  (1UL)                     /*!< MCUN0GPIO33 (Bit 1)                                   */
34665 #define GPIO_MCUN0INT1EN_MCUN0GPIO33_Msk  (0x2UL)                   /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
34666 #define GPIO_MCUN0INT1EN_MCUN0GPIO32_Pos  (0UL)                     /*!< MCUN0GPIO32 (Bit 0)                                   */
34667 #define GPIO_MCUN0INT1EN_MCUN0GPIO32_Msk  (0x1UL)                   /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
34668 /* =====================================================  MCUN0INT1STAT  ===================================================== */
34669 #define GPIO_MCUN0INT1STAT_MCUN0GPIO63_Pos (31UL)                   /*!< MCUN0GPIO63 (Bit 31)                                  */
34670 #define GPIO_MCUN0INT1STAT_MCUN0GPIO63_Msk (0x80000000UL)           /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
34671 #define GPIO_MCUN0INT1STAT_MCUN0GPIO62_Pos (30UL)                   /*!< MCUN0GPIO62 (Bit 30)                                  */
34672 #define GPIO_MCUN0INT1STAT_MCUN0GPIO62_Msk (0x40000000UL)           /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
34673 #define GPIO_MCUN0INT1STAT_MCUN0GPIO61_Pos (29UL)                   /*!< MCUN0GPIO61 (Bit 29)                                  */
34674 #define GPIO_MCUN0INT1STAT_MCUN0GPIO61_Msk (0x20000000UL)           /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
34675 #define GPIO_MCUN0INT1STAT_MCUN0GPIO60_Pos (28UL)                   /*!< MCUN0GPIO60 (Bit 28)                                  */
34676 #define GPIO_MCUN0INT1STAT_MCUN0GPIO60_Msk (0x10000000UL)           /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
34677 #define GPIO_MCUN0INT1STAT_MCUN0GPIO59_Pos (27UL)                   /*!< MCUN0GPIO59 (Bit 27)                                  */
34678 #define GPIO_MCUN0INT1STAT_MCUN0GPIO59_Msk (0x8000000UL)            /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
34679 #define GPIO_MCUN0INT1STAT_MCUN0GPIO58_Pos (26UL)                   /*!< MCUN0GPIO58 (Bit 26)                                  */
34680 #define GPIO_MCUN0INT1STAT_MCUN0GPIO58_Msk (0x4000000UL)            /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
34681 #define GPIO_MCUN0INT1STAT_MCUN0GPIO57_Pos (25UL)                   /*!< MCUN0GPIO57 (Bit 25)                                  */
34682 #define GPIO_MCUN0INT1STAT_MCUN0GPIO57_Msk (0x2000000UL)            /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
34683 #define GPIO_MCUN0INT1STAT_MCUN0GPIO56_Pos (24UL)                   /*!< MCUN0GPIO56 (Bit 24)                                  */
34684 #define GPIO_MCUN0INT1STAT_MCUN0GPIO56_Msk (0x1000000UL)            /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
34685 #define GPIO_MCUN0INT1STAT_MCUN0GPIO55_Pos (23UL)                   /*!< MCUN0GPIO55 (Bit 23)                                  */
34686 #define GPIO_MCUN0INT1STAT_MCUN0GPIO55_Msk (0x800000UL)             /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
34687 #define GPIO_MCUN0INT1STAT_MCUN0GPIO54_Pos (22UL)                   /*!< MCUN0GPIO54 (Bit 22)                                  */
34688 #define GPIO_MCUN0INT1STAT_MCUN0GPIO54_Msk (0x400000UL)             /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
34689 #define GPIO_MCUN0INT1STAT_MCUN0GPIO53_Pos (21UL)                   /*!< MCUN0GPIO53 (Bit 21)                                  */
34690 #define GPIO_MCUN0INT1STAT_MCUN0GPIO53_Msk (0x200000UL)             /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
34691 #define GPIO_MCUN0INT1STAT_MCUN0GPIO52_Pos (20UL)                   /*!< MCUN0GPIO52 (Bit 20)                                  */
34692 #define GPIO_MCUN0INT1STAT_MCUN0GPIO52_Msk (0x100000UL)             /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
34693 #define GPIO_MCUN0INT1STAT_MCUN0GPIO51_Pos (19UL)                   /*!< MCUN0GPIO51 (Bit 19)                                  */
34694 #define GPIO_MCUN0INT1STAT_MCUN0GPIO51_Msk (0x80000UL)              /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
34695 #define GPIO_MCUN0INT1STAT_MCUN0GPIO50_Pos (18UL)                   /*!< MCUN0GPIO50 (Bit 18)                                  */
34696 #define GPIO_MCUN0INT1STAT_MCUN0GPIO50_Msk (0x40000UL)              /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
34697 #define GPIO_MCUN0INT1STAT_MCUN0GPIO49_Pos (17UL)                   /*!< MCUN0GPIO49 (Bit 17)                                  */
34698 #define GPIO_MCUN0INT1STAT_MCUN0GPIO49_Msk (0x20000UL)              /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
34699 #define GPIO_MCUN0INT1STAT_MCUN0GPIO48_Pos (16UL)                   /*!< MCUN0GPIO48 (Bit 16)                                  */
34700 #define GPIO_MCUN0INT1STAT_MCUN0GPIO48_Msk (0x10000UL)              /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
34701 #define GPIO_MCUN0INT1STAT_MCUN0GPIO47_Pos (15UL)                   /*!< MCUN0GPIO47 (Bit 15)                                  */
34702 #define GPIO_MCUN0INT1STAT_MCUN0GPIO47_Msk (0x8000UL)               /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
34703 #define GPIO_MCUN0INT1STAT_MCUN0GPIO46_Pos (14UL)                   /*!< MCUN0GPIO46 (Bit 14)                                  */
34704 #define GPIO_MCUN0INT1STAT_MCUN0GPIO46_Msk (0x4000UL)               /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
34705 #define GPIO_MCUN0INT1STAT_MCUN0GPIO45_Pos (13UL)                   /*!< MCUN0GPIO45 (Bit 13)                                  */
34706 #define GPIO_MCUN0INT1STAT_MCUN0GPIO45_Msk (0x2000UL)               /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
34707 #define GPIO_MCUN0INT1STAT_MCUN0GPIO44_Pos (12UL)                   /*!< MCUN0GPIO44 (Bit 12)                                  */
34708 #define GPIO_MCUN0INT1STAT_MCUN0GPIO44_Msk (0x1000UL)               /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
34709 #define GPIO_MCUN0INT1STAT_MCUN0GPIO43_Pos (11UL)                   /*!< MCUN0GPIO43 (Bit 11)                                  */
34710 #define GPIO_MCUN0INT1STAT_MCUN0GPIO43_Msk (0x800UL)                /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
34711 #define GPIO_MCUN0INT1STAT_MCUN0GPIO42_Pos (10UL)                   /*!< MCUN0GPIO42 (Bit 10)                                  */
34712 #define GPIO_MCUN0INT1STAT_MCUN0GPIO42_Msk (0x400UL)                /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
34713 #define GPIO_MCUN0INT1STAT_MCUN0GPIO41_Pos (9UL)                    /*!< MCUN0GPIO41 (Bit 9)                                   */
34714 #define GPIO_MCUN0INT1STAT_MCUN0GPIO41_Msk (0x200UL)                /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
34715 #define GPIO_MCUN0INT1STAT_MCUN0GPIO40_Pos (8UL)                    /*!< MCUN0GPIO40 (Bit 8)                                   */
34716 #define GPIO_MCUN0INT1STAT_MCUN0GPIO40_Msk (0x100UL)                /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
34717 #define GPIO_MCUN0INT1STAT_MCUN0GPIO39_Pos (7UL)                    /*!< MCUN0GPIO39 (Bit 7)                                   */
34718 #define GPIO_MCUN0INT1STAT_MCUN0GPIO39_Msk (0x80UL)                 /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
34719 #define GPIO_MCUN0INT1STAT_MCUN0GPIO38_Pos (6UL)                    /*!< MCUN0GPIO38 (Bit 6)                                   */
34720 #define GPIO_MCUN0INT1STAT_MCUN0GPIO38_Msk (0x40UL)                 /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
34721 #define GPIO_MCUN0INT1STAT_MCUN0GPIO37_Pos (5UL)                    /*!< MCUN0GPIO37 (Bit 5)                                   */
34722 #define GPIO_MCUN0INT1STAT_MCUN0GPIO37_Msk (0x20UL)                 /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
34723 #define GPIO_MCUN0INT1STAT_MCUN0GPIO36_Pos (4UL)                    /*!< MCUN0GPIO36 (Bit 4)                                   */
34724 #define GPIO_MCUN0INT1STAT_MCUN0GPIO36_Msk (0x10UL)                 /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
34725 #define GPIO_MCUN0INT1STAT_MCUN0GPIO35_Pos (3UL)                    /*!< MCUN0GPIO35 (Bit 3)                                   */
34726 #define GPIO_MCUN0INT1STAT_MCUN0GPIO35_Msk (0x8UL)                  /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
34727 #define GPIO_MCUN0INT1STAT_MCUN0GPIO34_Pos (2UL)                    /*!< MCUN0GPIO34 (Bit 2)                                   */
34728 #define GPIO_MCUN0INT1STAT_MCUN0GPIO34_Msk (0x4UL)                  /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
34729 #define GPIO_MCUN0INT1STAT_MCUN0GPIO33_Pos (1UL)                    /*!< MCUN0GPIO33 (Bit 1)                                   */
34730 #define GPIO_MCUN0INT1STAT_MCUN0GPIO33_Msk (0x2UL)                  /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
34731 #define GPIO_MCUN0INT1STAT_MCUN0GPIO32_Pos (0UL)                    /*!< MCUN0GPIO32 (Bit 0)                                   */
34732 #define GPIO_MCUN0INT1STAT_MCUN0GPIO32_Msk (0x1UL)                  /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
34733 /* =====================================================  MCUN0INT1CLR  ====================================================== */
34734 #define GPIO_MCUN0INT1CLR_MCUN0GPIO63_Pos (31UL)                    /*!< MCUN0GPIO63 (Bit 31)                                  */
34735 #define GPIO_MCUN0INT1CLR_MCUN0GPIO63_Msk (0x80000000UL)            /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
34736 #define GPIO_MCUN0INT1CLR_MCUN0GPIO62_Pos (30UL)                    /*!< MCUN0GPIO62 (Bit 30)                                  */
34737 #define GPIO_MCUN0INT1CLR_MCUN0GPIO62_Msk (0x40000000UL)            /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
34738 #define GPIO_MCUN0INT1CLR_MCUN0GPIO61_Pos (29UL)                    /*!< MCUN0GPIO61 (Bit 29)                                  */
34739 #define GPIO_MCUN0INT1CLR_MCUN0GPIO61_Msk (0x20000000UL)            /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
34740 #define GPIO_MCUN0INT1CLR_MCUN0GPIO60_Pos (28UL)                    /*!< MCUN0GPIO60 (Bit 28)                                  */
34741 #define GPIO_MCUN0INT1CLR_MCUN0GPIO60_Msk (0x10000000UL)            /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
34742 #define GPIO_MCUN0INT1CLR_MCUN0GPIO59_Pos (27UL)                    /*!< MCUN0GPIO59 (Bit 27)                                  */
34743 #define GPIO_MCUN0INT1CLR_MCUN0GPIO59_Msk (0x8000000UL)             /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
34744 #define GPIO_MCUN0INT1CLR_MCUN0GPIO58_Pos (26UL)                    /*!< MCUN0GPIO58 (Bit 26)                                  */
34745 #define GPIO_MCUN0INT1CLR_MCUN0GPIO58_Msk (0x4000000UL)             /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
34746 #define GPIO_MCUN0INT1CLR_MCUN0GPIO57_Pos (25UL)                    /*!< MCUN0GPIO57 (Bit 25)                                  */
34747 #define GPIO_MCUN0INT1CLR_MCUN0GPIO57_Msk (0x2000000UL)             /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
34748 #define GPIO_MCUN0INT1CLR_MCUN0GPIO56_Pos (24UL)                    /*!< MCUN0GPIO56 (Bit 24)                                  */
34749 #define GPIO_MCUN0INT1CLR_MCUN0GPIO56_Msk (0x1000000UL)             /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
34750 #define GPIO_MCUN0INT1CLR_MCUN0GPIO55_Pos (23UL)                    /*!< MCUN0GPIO55 (Bit 23)                                  */
34751 #define GPIO_MCUN0INT1CLR_MCUN0GPIO55_Msk (0x800000UL)              /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
34752 #define GPIO_MCUN0INT1CLR_MCUN0GPIO54_Pos (22UL)                    /*!< MCUN0GPIO54 (Bit 22)                                  */
34753 #define GPIO_MCUN0INT1CLR_MCUN0GPIO54_Msk (0x400000UL)              /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
34754 #define GPIO_MCUN0INT1CLR_MCUN0GPIO53_Pos (21UL)                    /*!< MCUN0GPIO53 (Bit 21)                                  */
34755 #define GPIO_MCUN0INT1CLR_MCUN0GPIO53_Msk (0x200000UL)              /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
34756 #define GPIO_MCUN0INT1CLR_MCUN0GPIO52_Pos (20UL)                    /*!< MCUN0GPIO52 (Bit 20)                                  */
34757 #define GPIO_MCUN0INT1CLR_MCUN0GPIO52_Msk (0x100000UL)              /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
34758 #define GPIO_MCUN0INT1CLR_MCUN0GPIO51_Pos (19UL)                    /*!< MCUN0GPIO51 (Bit 19)                                  */
34759 #define GPIO_MCUN0INT1CLR_MCUN0GPIO51_Msk (0x80000UL)               /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
34760 #define GPIO_MCUN0INT1CLR_MCUN0GPIO50_Pos (18UL)                    /*!< MCUN0GPIO50 (Bit 18)                                  */
34761 #define GPIO_MCUN0INT1CLR_MCUN0GPIO50_Msk (0x40000UL)               /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
34762 #define GPIO_MCUN0INT1CLR_MCUN0GPIO49_Pos (17UL)                    /*!< MCUN0GPIO49 (Bit 17)                                  */
34763 #define GPIO_MCUN0INT1CLR_MCUN0GPIO49_Msk (0x20000UL)               /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
34764 #define GPIO_MCUN0INT1CLR_MCUN0GPIO48_Pos (16UL)                    /*!< MCUN0GPIO48 (Bit 16)                                  */
34765 #define GPIO_MCUN0INT1CLR_MCUN0GPIO48_Msk (0x10000UL)               /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
34766 #define GPIO_MCUN0INT1CLR_MCUN0GPIO47_Pos (15UL)                    /*!< MCUN0GPIO47 (Bit 15)                                  */
34767 #define GPIO_MCUN0INT1CLR_MCUN0GPIO47_Msk (0x8000UL)                /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
34768 #define GPIO_MCUN0INT1CLR_MCUN0GPIO46_Pos (14UL)                    /*!< MCUN0GPIO46 (Bit 14)                                  */
34769 #define GPIO_MCUN0INT1CLR_MCUN0GPIO46_Msk (0x4000UL)                /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
34770 #define GPIO_MCUN0INT1CLR_MCUN0GPIO45_Pos (13UL)                    /*!< MCUN0GPIO45 (Bit 13)                                  */
34771 #define GPIO_MCUN0INT1CLR_MCUN0GPIO45_Msk (0x2000UL)                /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
34772 #define GPIO_MCUN0INT1CLR_MCUN0GPIO44_Pos (12UL)                    /*!< MCUN0GPIO44 (Bit 12)                                  */
34773 #define GPIO_MCUN0INT1CLR_MCUN0GPIO44_Msk (0x1000UL)                /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
34774 #define GPIO_MCUN0INT1CLR_MCUN0GPIO43_Pos (11UL)                    /*!< MCUN0GPIO43 (Bit 11)                                  */
34775 #define GPIO_MCUN0INT1CLR_MCUN0GPIO43_Msk (0x800UL)                 /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
34776 #define GPIO_MCUN0INT1CLR_MCUN0GPIO42_Pos (10UL)                    /*!< MCUN0GPIO42 (Bit 10)                                  */
34777 #define GPIO_MCUN0INT1CLR_MCUN0GPIO42_Msk (0x400UL)                 /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
34778 #define GPIO_MCUN0INT1CLR_MCUN0GPIO41_Pos (9UL)                     /*!< MCUN0GPIO41 (Bit 9)                                   */
34779 #define GPIO_MCUN0INT1CLR_MCUN0GPIO41_Msk (0x200UL)                 /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
34780 #define GPIO_MCUN0INT1CLR_MCUN0GPIO40_Pos (8UL)                     /*!< MCUN0GPIO40 (Bit 8)                                   */
34781 #define GPIO_MCUN0INT1CLR_MCUN0GPIO40_Msk (0x100UL)                 /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
34782 #define GPIO_MCUN0INT1CLR_MCUN0GPIO39_Pos (7UL)                     /*!< MCUN0GPIO39 (Bit 7)                                   */
34783 #define GPIO_MCUN0INT1CLR_MCUN0GPIO39_Msk (0x80UL)                  /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
34784 #define GPIO_MCUN0INT1CLR_MCUN0GPIO38_Pos (6UL)                     /*!< MCUN0GPIO38 (Bit 6)                                   */
34785 #define GPIO_MCUN0INT1CLR_MCUN0GPIO38_Msk (0x40UL)                  /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
34786 #define GPIO_MCUN0INT1CLR_MCUN0GPIO37_Pos (5UL)                     /*!< MCUN0GPIO37 (Bit 5)                                   */
34787 #define GPIO_MCUN0INT1CLR_MCUN0GPIO37_Msk (0x20UL)                  /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
34788 #define GPIO_MCUN0INT1CLR_MCUN0GPIO36_Pos (4UL)                     /*!< MCUN0GPIO36 (Bit 4)                                   */
34789 #define GPIO_MCUN0INT1CLR_MCUN0GPIO36_Msk (0x10UL)                  /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
34790 #define GPIO_MCUN0INT1CLR_MCUN0GPIO35_Pos (3UL)                     /*!< MCUN0GPIO35 (Bit 3)                                   */
34791 #define GPIO_MCUN0INT1CLR_MCUN0GPIO35_Msk (0x8UL)                   /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
34792 #define GPIO_MCUN0INT1CLR_MCUN0GPIO34_Pos (2UL)                     /*!< MCUN0GPIO34 (Bit 2)                                   */
34793 #define GPIO_MCUN0INT1CLR_MCUN0GPIO34_Msk (0x4UL)                   /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
34794 #define GPIO_MCUN0INT1CLR_MCUN0GPIO33_Pos (1UL)                     /*!< MCUN0GPIO33 (Bit 1)                                   */
34795 #define GPIO_MCUN0INT1CLR_MCUN0GPIO33_Msk (0x2UL)                   /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
34796 #define GPIO_MCUN0INT1CLR_MCUN0GPIO32_Pos (0UL)                     /*!< MCUN0GPIO32 (Bit 0)                                   */
34797 #define GPIO_MCUN0INT1CLR_MCUN0GPIO32_Msk (0x1UL)                   /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
34798 /* =====================================================  MCUN0INT1SET  ====================================================== */
34799 #define GPIO_MCUN0INT1SET_MCUN0GPIO63_Pos (31UL)                    /*!< MCUN0GPIO63 (Bit 31)                                  */
34800 #define GPIO_MCUN0INT1SET_MCUN0GPIO63_Msk (0x80000000UL)            /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
34801 #define GPIO_MCUN0INT1SET_MCUN0GPIO62_Pos (30UL)                    /*!< MCUN0GPIO62 (Bit 30)                                  */
34802 #define GPIO_MCUN0INT1SET_MCUN0GPIO62_Msk (0x40000000UL)            /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
34803 #define GPIO_MCUN0INT1SET_MCUN0GPIO61_Pos (29UL)                    /*!< MCUN0GPIO61 (Bit 29)                                  */
34804 #define GPIO_MCUN0INT1SET_MCUN0GPIO61_Msk (0x20000000UL)            /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
34805 #define GPIO_MCUN0INT1SET_MCUN0GPIO60_Pos (28UL)                    /*!< MCUN0GPIO60 (Bit 28)                                  */
34806 #define GPIO_MCUN0INT1SET_MCUN0GPIO60_Msk (0x10000000UL)            /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
34807 #define GPIO_MCUN0INT1SET_MCUN0GPIO59_Pos (27UL)                    /*!< MCUN0GPIO59 (Bit 27)                                  */
34808 #define GPIO_MCUN0INT1SET_MCUN0GPIO59_Msk (0x8000000UL)             /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
34809 #define GPIO_MCUN0INT1SET_MCUN0GPIO58_Pos (26UL)                    /*!< MCUN0GPIO58 (Bit 26)                                  */
34810 #define GPIO_MCUN0INT1SET_MCUN0GPIO58_Msk (0x4000000UL)             /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
34811 #define GPIO_MCUN0INT1SET_MCUN0GPIO57_Pos (25UL)                    /*!< MCUN0GPIO57 (Bit 25)                                  */
34812 #define GPIO_MCUN0INT1SET_MCUN0GPIO57_Msk (0x2000000UL)             /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
34813 #define GPIO_MCUN0INT1SET_MCUN0GPIO56_Pos (24UL)                    /*!< MCUN0GPIO56 (Bit 24)                                  */
34814 #define GPIO_MCUN0INT1SET_MCUN0GPIO56_Msk (0x1000000UL)             /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
34815 #define GPIO_MCUN0INT1SET_MCUN0GPIO55_Pos (23UL)                    /*!< MCUN0GPIO55 (Bit 23)                                  */
34816 #define GPIO_MCUN0INT1SET_MCUN0GPIO55_Msk (0x800000UL)              /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
34817 #define GPIO_MCUN0INT1SET_MCUN0GPIO54_Pos (22UL)                    /*!< MCUN0GPIO54 (Bit 22)                                  */
34818 #define GPIO_MCUN0INT1SET_MCUN0GPIO54_Msk (0x400000UL)              /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
34819 #define GPIO_MCUN0INT1SET_MCUN0GPIO53_Pos (21UL)                    /*!< MCUN0GPIO53 (Bit 21)                                  */
34820 #define GPIO_MCUN0INT1SET_MCUN0GPIO53_Msk (0x200000UL)              /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
34821 #define GPIO_MCUN0INT1SET_MCUN0GPIO52_Pos (20UL)                    /*!< MCUN0GPIO52 (Bit 20)                                  */
34822 #define GPIO_MCUN0INT1SET_MCUN0GPIO52_Msk (0x100000UL)              /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
34823 #define GPIO_MCUN0INT1SET_MCUN0GPIO51_Pos (19UL)                    /*!< MCUN0GPIO51 (Bit 19)                                  */
34824 #define GPIO_MCUN0INT1SET_MCUN0GPIO51_Msk (0x80000UL)               /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
34825 #define GPIO_MCUN0INT1SET_MCUN0GPIO50_Pos (18UL)                    /*!< MCUN0GPIO50 (Bit 18)                                  */
34826 #define GPIO_MCUN0INT1SET_MCUN0GPIO50_Msk (0x40000UL)               /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
34827 #define GPIO_MCUN0INT1SET_MCUN0GPIO49_Pos (17UL)                    /*!< MCUN0GPIO49 (Bit 17)                                  */
34828 #define GPIO_MCUN0INT1SET_MCUN0GPIO49_Msk (0x20000UL)               /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
34829 #define GPIO_MCUN0INT1SET_MCUN0GPIO48_Pos (16UL)                    /*!< MCUN0GPIO48 (Bit 16)                                  */
34830 #define GPIO_MCUN0INT1SET_MCUN0GPIO48_Msk (0x10000UL)               /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
34831 #define GPIO_MCUN0INT1SET_MCUN0GPIO47_Pos (15UL)                    /*!< MCUN0GPIO47 (Bit 15)                                  */
34832 #define GPIO_MCUN0INT1SET_MCUN0GPIO47_Msk (0x8000UL)                /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
34833 #define GPIO_MCUN0INT1SET_MCUN0GPIO46_Pos (14UL)                    /*!< MCUN0GPIO46 (Bit 14)                                  */
34834 #define GPIO_MCUN0INT1SET_MCUN0GPIO46_Msk (0x4000UL)                /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
34835 #define GPIO_MCUN0INT1SET_MCUN0GPIO45_Pos (13UL)                    /*!< MCUN0GPIO45 (Bit 13)                                  */
34836 #define GPIO_MCUN0INT1SET_MCUN0GPIO45_Msk (0x2000UL)                /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
34837 #define GPIO_MCUN0INT1SET_MCUN0GPIO44_Pos (12UL)                    /*!< MCUN0GPIO44 (Bit 12)                                  */
34838 #define GPIO_MCUN0INT1SET_MCUN0GPIO44_Msk (0x1000UL)                /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
34839 #define GPIO_MCUN0INT1SET_MCUN0GPIO43_Pos (11UL)                    /*!< MCUN0GPIO43 (Bit 11)                                  */
34840 #define GPIO_MCUN0INT1SET_MCUN0GPIO43_Msk (0x800UL)                 /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
34841 #define GPIO_MCUN0INT1SET_MCUN0GPIO42_Pos (10UL)                    /*!< MCUN0GPIO42 (Bit 10)                                  */
34842 #define GPIO_MCUN0INT1SET_MCUN0GPIO42_Msk (0x400UL)                 /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
34843 #define GPIO_MCUN0INT1SET_MCUN0GPIO41_Pos (9UL)                     /*!< MCUN0GPIO41 (Bit 9)                                   */
34844 #define GPIO_MCUN0INT1SET_MCUN0GPIO41_Msk (0x200UL)                 /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
34845 #define GPIO_MCUN0INT1SET_MCUN0GPIO40_Pos (8UL)                     /*!< MCUN0GPIO40 (Bit 8)                                   */
34846 #define GPIO_MCUN0INT1SET_MCUN0GPIO40_Msk (0x100UL)                 /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
34847 #define GPIO_MCUN0INT1SET_MCUN0GPIO39_Pos (7UL)                     /*!< MCUN0GPIO39 (Bit 7)                                   */
34848 #define GPIO_MCUN0INT1SET_MCUN0GPIO39_Msk (0x80UL)                  /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
34849 #define GPIO_MCUN0INT1SET_MCUN0GPIO38_Pos (6UL)                     /*!< MCUN0GPIO38 (Bit 6)                                   */
34850 #define GPIO_MCUN0INT1SET_MCUN0GPIO38_Msk (0x40UL)                  /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
34851 #define GPIO_MCUN0INT1SET_MCUN0GPIO37_Pos (5UL)                     /*!< MCUN0GPIO37 (Bit 5)                                   */
34852 #define GPIO_MCUN0INT1SET_MCUN0GPIO37_Msk (0x20UL)                  /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
34853 #define GPIO_MCUN0INT1SET_MCUN0GPIO36_Pos (4UL)                     /*!< MCUN0GPIO36 (Bit 4)                                   */
34854 #define GPIO_MCUN0INT1SET_MCUN0GPIO36_Msk (0x10UL)                  /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
34855 #define GPIO_MCUN0INT1SET_MCUN0GPIO35_Pos (3UL)                     /*!< MCUN0GPIO35 (Bit 3)                                   */
34856 #define GPIO_MCUN0INT1SET_MCUN0GPIO35_Msk (0x8UL)                   /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
34857 #define GPIO_MCUN0INT1SET_MCUN0GPIO34_Pos (2UL)                     /*!< MCUN0GPIO34 (Bit 2)                                   */
34858 #define GPIO_MCUN0INT1SET_MCUN0GPIO34_Msk (0x4UL)                   /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
34859 #define GPIO_MCUN0INT1SET_MCUN0GPIO33_Pos (1UL)                     /*!< MCUN0GPIO33 (Bit 1)                                   */
34860 #define GPIO_MCUN0INT1SET_MCUN0GPIO33_Msk (0x2UL)                   /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
34861 #define GPIO_MCUN0INT1SET_MCUN0GPIO32_Pos (0UL)                     /*!< MCUN0GPIO32 (Bit 0)                                   */
34862 #define GPIO_MCUN0INT1SET_MCUN0GPIO32_Msk (0x1UL)                   /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
34863 /* ======================================================  MCUN0INT2EN  ====================================================== */
34864 #define GPIO_MCUN0INT2EN_MCUN0GPIO95_Pos  (31UL)                    /*!< MCUN0GPIO95 (Bit 31)                                  */
34865 #define GPIO_MCUN0INT2EN_MCUN0GPIO95_Msk  (0x80000000UL)            /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
34866 #define GPIO_MCUN0INT2EN_MCUN0GPIO94_Pos  (30UL)                    /*!< MCUN0GPIO94 (Bit 30)                                  */
34867 #define GPIO_MCUN0INT2EN_MCUN0GPIO94_Msk  (0x40000000UL)            /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
34868 #define GPIO_MCUN0INT2EN_MCUN0GPIO93_Pos  (29UL)                    /*!< MCUN0GPIO93 (Bit 29)                                  */
34869 #define GPIO_MCUN0INT2EN_MCUN0GPIO93_Msk  (0x20000000UL)            /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
34870 #define GPIO_MCUN0INT2EN_MCUN0GPIO92_Pos  (28UL)                    /*!< MCUN0GPIO92 (Bit 28)                                  */
34871 #define GPIO_MCUN0INT2EN_MCUN0GPIO92_Msk  (0x10000000UL)            /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
34872 #define GPIO_MCUN0INT2EN_MCUN0GPIO91_Pos  (27UL)                    /*!< MCUN0GPIO91 (Bit 27)                                  */
34873 #define GPIO_MCUN0INT2EN_MCUN0GPIO91_Msk  (0x8000000UL)             /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
34874 #define GPIO_MCUN0INT2EN_MCUN0GPIO90_Pos  (26UL)                    /*!< MCUN0GPIO90 (Bit 26)                                  */
34875 #define GPIO_MCUN0INT2EN_MCUN0GPIO90_Msk  (0x4000000UL)             /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
34876 #define GPIO_MCUN0INT2EN_MCUN0GPIO89_Pos  (25UL)                    /*!< MCUN0GPIO89 (Bit 25)                                  */
34877 #define GPIO_MCUN0INT2EN_MCUN0GPIO89_Msk  (0x2000000UL)             /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
34878 #define GPIO_MCUN0INT2EN_MCUN0GPIO88_Pos  (24UL)                    /*!< MCUN0GPIO88 (Bit 24)                                  */
34879 #define GPIO_MCUN0INT2EN_MCUN0GPIO88_Msk  (0x1000000UL)             /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
34880 #define GPIO_MCUN0INT2EN_MCUN0GPIO87_Pos  (23UL)                    /*!< MCUN0GPIO87 (Bit 23)                                  */
34881 #define GPIO_MCUN0INT2EN_MCUN0GPIO87_Msk  (0x800000UL)              /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
34882 #define GPIO_MCUN0INT2EN_MCUN0GPIO86_Pos  (22UL)                    /*!< MCUN0GPIO86 (Bit 22)                                  */
34883 #define GPIO_MCUN0INT2EN_MCUN0GPIO86_Msk  (0x400000UL)              /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
34884 #define GPIO_MCUN0INT2EN_MCUN0GPIO85_Pos  (21UL)                    /*!< MCUN0GPIO85 (Bit 21)                                  */
34885 #define GPIO_MCUN0INT2EN_MCUN0GPIO85_Msk  (0x200000UL)              /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
34886 #define GPIO_MCUN0INT2EN_MCUN0GPIO84_Pos  (20UL)                    /*!< MCUN0GPIO84 (Bit 20)                                  */
34887 #define GPIO_MCUN0INT2EN_MCUN0GPIO84_Msk  (0x100000UL)              /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
34888 #define GPIO_MCUN0INT2EN_MCUN0GPIO83_Pos  (19UL)                    /*!< MCUN0GPIO83 (Bit 19)                                  */
34889 #define GPIO_MCUN0INT2EN_MCUN0GPIO83_Msk  (0x80000UL)               /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
34890 #define GPIO_MCUN0INT2EN_MCUN0GPIO82_Pos  (18UL)                    /*!< MCUN0GPIO82 (Bit 18)                                  */
34891 #define GPIO_MCUN0INT2EN_MCUN0GPIO82_Msk  (0x40000UL)               /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
34892 #define GPIO_MCUN0INT2EN_MCUN0GPIO81_Pos  (17UL)                    /*!< MCUN0GPIO81 (Bit 17)                                  */
34893 #define GPIO_MCUN0INT2EN_MCUN0GPIO81_Msk  (0x20000UL)               /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
34894 #define GPIO_MCUN0INT2EN_MCUN0GPIO80_Pos  (16UL)                    /*!< MCUN0GPIO80 (Bit 16)                                  */
34895 #define GPIO_MCUN0INT2EN_MCUN0GPIO80_Msk  (0x10000UL)               /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
34896 #define GPIO_MCUN0INT2EN_MCUN0GPIO79_Pos  (15UL)                    /*!< MCUN0GPIO79 (Bit 15)                                  */
34897 #define GPIO_MCUN0INT2EN_MCUN0GPIO79_Msk  (0x8000UL)                /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
34898 #define GPIO_MCUN0INT2EN_MCUN0GPIO78_Pos  (14UL)                    /*!< MCUN0GPIO78 (Bit 14)                                  */
34899 #define GPIO_MCUN0INT2EN_MCUN0GPIO78_Msk  (0x4000UL)                /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
34900 #define GPIO_MCUN0INT2EN_MCUN0GPIO77_Pos  (13UL)                    /*!< MCUN0GPIO77 (Bit 13)                                  */
34901 #define GPIO_MCUN0INT2EN_MCUN0GPIO77_Msk  (0x2000UL)                /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
34902 #define GPIO_MCUN0INT2EN_MCUN0GPIO76_Pos  (12UL)                    /*!< MCUN0GPIO76 (Bit 12)                                  */
34903 #define GPIO_MCUN0INT2EN_MCUN0GPIO76_Msk  (0x1000UL)                /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
34904 #define GPIO_MCUN0INT2EN_MCUN0GPIO75_Pos  (11UL)                    /*!< MCUN0GPIO75 (Bit 11)                                  */
34905 #define GPIO_MCUN0INT2EN_MCUN0GPIO75_Msk  (0x800UL)                 /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
34906 #define GPIO_MCUN0INT2EN_MCUN0GPIO74_Pos  (10UL)                    /*!< MCUN0GPIO74 (Bit 10)                                  */
34907 #define GPIO_MCUN0INT2EN_MCUN0GPIO74_Msk  (0x400UL)                 /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
34908 #define GPIO_MCUN0INT2EN_MCUN0GPIO73_Pos  (9UL)                     /*!< MCUN0GPIO73 (Bit 9)                                   */
34909 #define GPIO_MCUN0INT2EN_MCUN0GPIO73_Msk  (0x200UL)                 /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
34910 #define GPIO_MCUN0INT2EN_MCUN0GPIO72_Pos  (8UL)                     /*!< MCUN0GPIO72 (Bit 8)                                   */
34911 #define GPIO_MCUN0INT2EN_MCUN0GPIO72_Msk  (0x100UL)                 /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
34912 #define GPIO_MCUN0INT2EN_MCUN0GPIO71_Pos  (7UL)                     /*!< MCUN0GPIO71 (Bit 7)                                   */
34913 #define GPIO_MCUN0INT2EN_MCUN0GPIO71_Msk  (0x80UL)                  /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
34914 #define GPIO_MCUN0INT2EN_MCUN0GPIO70_Pos  (6UL)                     /*!< MCUN0GPIO70 (Bit 6)                                   */
34915 #define GPIO_MCUN0INT2EN_MCUN0GPIO70_Msk  (0x40UL)                  /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
34916 #define GPIO_MCUN0INT2EN_MCUN0GPIO69_Pos  (5UL)                     /*!< MCUN0GPIO69 (Bit 5)                                   */
34917 #define GPIO_MCUN0INT2EN_MCUN0GPIO69_Msk  (0x20UL)                  /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
34918 #define GPIO_MCUN0INT2EN_MCUN0GPIO68_Pos  (4UL)                     /*!< MCUN0GPIO68 (Bit 4)                                   */
34919 #define GPIO_MCUN0INT2EN_MCUN0GPIO68_Msk  (0x10UL)                  /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
34920 #define GPIO_MCUN0INT2EN_MCUN0GPIO67_Pos  (3UL)                     /*!< MCUN0GPIO67 (Bit 3)                                   */
34921 #define GPIO_MCUN0INT2EN_MCUN0GPIO67_Msk  (0x8UL)                   /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
34922 #define GPIO_MCUN0INT2EN_MCUN0GPIO66_Pos  (2UL)                     /*!< MCUN0GPIO66 (Bit 2)                                   */
34923 #define GPIO_MCUN0INT2EN_MCUN0GPIO66_Msk  (0x4UL)                   /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
34924 #define GPIO_MCUN0INT2EN_MCUN0GPIO65_Pos  (1UL)                     /*!< MCUN0GPIO65 (Bit 1)                                   */
34925 #define GPIO_MCUN0INT2EN_MCUN0GPIO65_Msk  (0x2UL)                   /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
34926 #define GPIO_MCUN0INT2EN_MCUN0GPIO64_Pos  (0UL)                     /*!< MCUN0GPIO64 (Bit 0)                                   */
34927 #define GPIO_MCUN0INT2EN_MCUN0GPIO64_Msk  (0x1UL)                   /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
34928 /* =====================================================  MCUN0INT2STAT  ===================================================== */
34929 #define GPIO_MCUN0INT2STAT_MCUN0GPIO95_Pos (31UL)                   /*!< MCUN0GPIO95 (Bit 31)                                  */
34930 #define GPIO_MCUN0INT2STAT_MCUN0GPIO95_Msk (0x80000000UL)           /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
34931 #define GPIO_MCUN0INT2STAT_MCUN0GPIO94_Pos (30UL)                   /*!< MCUN0GPIO94 (Bit 30)                                  */
34932 #define GPIO_MCUN0INT2STAT_MCUN0GPIO94_Msk (0x40000000UL)           /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
34933 #define GPIO_MCUN0INT2STAT_MCUN0GPIO93_Pos (29UL)                   /*!< MCUN0GPIO93 (Bit 29)                                  */
34934 #define GPIO_MCUN0INT2STAT_MCUN0GPIO93_Msk (0x20000000UL)           /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
34935 #define GPIO_MCUN0INT2STAT_MCUN0GPIO92_Pos (28UL)                   /*!< MCUN0GPIO92 (Bit 28)                                  */
34936 #define GPIO_MCUN0INT2STAT_MCUN0GPIO92_Msk (0x10000000UL)           /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
34937 #define GPIO_MCUN0INT2STAT_MCUN0GPIO91_Pos (27UL)                   /*!< MCUN0GPIO91 (Bit 27)                                  */
34938 #define GPIO_MCUN0INT2STAT_MCUN0GPIO91_Msk (0x8000000UL)            /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
34939 #define GPIO_MCUN0INT2STAT_MCUN0GPIO90_Pos (26UL)                   /*!< MCUN0GPIO90 (Bit 26)                                  */
34940 #define GPIO_MCUN0INT2STAT_MCUN0GPIO90_Msk (0x4000000UL)            /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
34941 #define GPIO_MCUN0INT2STAT_MCUN0GPIO89_Pos (25UL)                   /*!< MCUN0GPIO89 (Bit 25)                                  */
34942 #define GPIO_MCUN0INT2STAT_MCUN0GPIO89_Msk (0x2000000UL)            /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
34943 #define GPIO_MCUN0INT2STAT_MCUN0GPIO88_Pos (24UL)                   /*!< MCUN0GPIO88 (Bit 24)                                  */
34944 #define GPIO_MCUN0INT2STAT_MCUN0GPIO88_Msk (0x1000000UL)            /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
34945 #define GPIO_MCUN0INT2STAT_MCUN0GPIO87_Pos (23UL)                   /*!< MCUN0GPIO87 (Bit 23)                                  */
34946 #define GPIO_MCUN0INT2STAT_MCUN0GPIO87_Msk (0x800000UL)             /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
34947 #define GPIO_MCUN0INT2STAT_MCUN0GPIO86_Pos (22UL)                   /*!< MCUN0GPIO86 (Bit 22)                                  */
34948 #define GPIO_MCUN0INT2STAT_MCUN0GPIO86_Msk (0x400000UL)             /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
34949 #define GPIO_MCUN0INT2STAT_MCUN0GPIO85_Pos (21UL)                   /*!< MCUN0GPIO85 (Bit 21)                                  */
34950 #define GPIO_MCUN0INT2STAT_MCUN0GPIO85_Msk (0x200000UL)             /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
34951 #define GPIO_MCUN0INT2STAT_MCUN0GPIO84_Pos (20UL)                   /*!< MCUN0GPIO84 (Bit 20)                                  */
34952 #define GPIO_MCUN0INT2STAT_MCUN0GPIO84_Msk (0x100000UL)             /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
34953 #define GPIO_MCUN0INT2STAT_MCUN0GPIO83_Pos (19UL)                   /*!< MCUN0GPIO83 (Bit 19)                                  */
34954 #define GPIO_MCUN0INT2STAT_MCUN0GPIO83_Msk (0x80000UL)              /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
34955 #define GPIO_MCUN0INT2STAT_MCUN0GPIO82_Pos (18UL)                   /*!< MCUN0GPIO82 (Bit 18)                                  */
34956 #define GPIO_MCUN0INT2STAT_MCUN0GPIO82_Msk (0x40000UL)              /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
34957 #define GPIO_MCUN0INT2STAT_MCUN0GPIO81_Pos (17UL)                   /*!< MCUN0GPIO81 (Bit 17)                                  */
34958 #define GPIO_MCUN0INT2STAT_MCUN0GPIO81_Msk (0x20000UL)              /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
34959 #define GPIO_MCUN0INT2STAT_MCUN0GPIO80_Pos (16UL)                   /*!< MCUN0GPIO80 (Bit 16)                                  */
34960 #define GPIO_MCUN0INT2STAT_MCUN0GPIO80_Msk (0x10000UL)              /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
34961 #define GPIO_MCUN0INT2STAT_MCUN0GPIO79_Pos (15UL)                   /*!< MCUN0GPIO79 (Bit 15)                                  */
34962 #define GPIO_MCUN0INT2STAT_MCUN0GPIO79_Msk (0x8000UL)               /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
34963 #define GPIO_MCUN0INT2STAT_MCUN0GPIO78_Pos (14UL)                   /*!< MCUN0GPIO78 (Bit 14)                                  */
34964 #define GPIO_MCUN0INT2STAT_MCUN0GPIO78_Msk (0x4000UL)               /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
34965 #define GPIO_MCUN0INT2STAT_MCUN0GPIO77_Pos (13UL)                   /*!< MCUN0GPIO77 (Bit 13)                                  */
34966 #define GPIO_MCUN0INT2STAT_MCUN0GPIO77_Msk (0x2000UL)               /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
34967 #define GPIO_MCUN0INT2STAT_MCUN0GPIO76_Pos (12UL)                   /*!< MCUN0GPIO76 (Bit 12)                                  */
34968 #define GPIO_MCUN0INT2STAT_MCUN0GPIO76_Msk (0x1000UL)               /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
34969 #define GPIO_MCUN0INT2STAT_MCUN0GPIO75_Pos (11UL)                   /*!< MCUN0GPIO75 (Bit 11)                                  */
34970 #define GPIO_MCUN0INT2STAT_MCUN0GPIO75_Msk (0x800UL)                /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
34971 #define GPIO_MCUN0INT2STAT_MCUN0GPIO74_Pos (10UL)                   /*!< MCUN0GPIO74 (Bit 10)                                  */
34972 #define GPIO_MCUN0INT2STAT_MCUN0GPIO74_Msk (0x400UL)                /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
34973 #define GPIO_MCUN0INT2STAT_MCUN0GPIO73_Pos (9UL)                    /*!< MCUN0GPIO73 (Bit 9)                                   */
34974 #define GPIO_MCUN0INT2STAT_MCUN0GPIO73_Msk (0x200UL)                /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
34975 #define GPIO_MCUN0INT2STAT_MCUN0GPIO72_Pos (8UL)                    /*!< MCUN0GPIO72 (Bit 8)                                   */
34976 #define GPIO_MCUN0INT2STAT_MCUN0GPIO72_Msk (0x100UL)                /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
34977 #define GPIO_MCUN0INT2STAT_MCUN0GPIO71_Pos (7UL)                    /*!< MCUN0GPIO71 (Bit 7)                                   */
34978 #define GPIO_MCUN0INT2STAT_MCUN0GPIO71_Msk (0x80UL)                 /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
34979 #define GPIO_MCUN0INT2STAT_MCUN0GPIO70_Pos (6UL)                    /*!< MCUN0GPIO70 (Bit 6)                                   */
34980 #define GPIO_MCUN0INT2STAT_MCUN0GPIO70_Msk (0x40UL)                 /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
34981 #define GPIO_MCUN0INT2STAT_MCUN0GPIO69_Pos (5UL)                    /*!< MCUN0GPIO69 (Bit 5)                                   */
34982 #define GPIO_MCUN0INT2STAT_MCUN0GPIO69_Msk (0x20UL)                 /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
34983 #define GPIO_MCUN0INT2STAT_MCUN0GPIO68_Pos (4UL)                    /*!< MCUN0GPIO68 (Bit 4)                                   */
34984 #define GPIO_MCUN0INT2STAT_MCUN0GPIO68_Msk (0x10UL)                 /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
34985 #define GPIO_MCUN0INT2STAT_MCUN0GPIO67_Pos (3UL)                    /*!< MCUN0GPIO67 (Bit 3)                                   */
34986 #define GPIO_MCUN0INT2STAT_MCUN0GPIO67_Msk (0x8UL)                  /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
34987 #define GPIO_MCUN0INT2STAT_MCUN0GPIO66_Pos (2UL)                    /*!< MCUN0GPIO66 (Bit 2)                                   */
34988 #define GPIO_MCUN0INT2STAT_MCUN0GPIO66_Msk (0x4UL)                  /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
34989 #define GPIO_MCUN0INT2STAT_MCUN0GPIO65_Pos (1UL)                    /*!< MCUN0GPIO65 (Bit 1)                                   */
34990 #define GPIO_MCUN0INT2STAT_MCUN0GPIO65_Msk (0x2UL)                  /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
34991 #define GPIO_MCUN0INT2STAT_MCUN0GPIO64_Pos (0UL)                    /*!< MCUN0GPIO64 (Bit 0)                                   */
34992 #define GPIO_MCUN0INT2STAT_MCUN0GPIO64_Msk (0x1UL)                  /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
34993 /* =====================================================  MCUN0INT2CLR  ====================================================== */
34994 #define GPIO_MCUN0INT2CLR_MCUN0GPIO95_Pos (31UL)                    /*!< MCUN0GPIO95 (Bit 31)                                  */
34995 #define GPIO_MCUN0INT2CLR_MCUN0GPIO95_Msk (0x80000000UL)            /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
34996 #define GPIO_MCUN0INT2CLR_MCUN0GPIO94_Pos (30UL)                    /*!< MCUN0GPIO94 (Bit 30)                                  */
34997 #define GPIO_MCUN0INT2CLR_MCUN0GPIO94_Msk (0x40000000UL)            /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
34998 #define GPIO_MCUN0INT2CLR_MCUN0GPIO93_Pos (29UL)                    /*!< MCUN0GPIO93 (Bit 29)                                  */
34999 #define GPIO_MCUN0INT2CLR_MCUN0GPIO93_Msk (0x20000000UL)            /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
35000 #define GPIO_MCUN0INT2CLR_MCUN0GPIO92_Pos (28UL)                    /*!< MCUN0GPIO92 (Bit 28)                                  */
35001 #define GPIO_MCUN0INT2CLR_MCUN0GPIO92_Msk (0x10000000UL)            /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
35002 #define GPIO_MCUN0INT2CLR_MCUN0GPIO91_Pos (27UL)                    /*!< MCUN0GPIO91 (Bit 27)                                  */
35003 #define GPIO_MCUN0INT2CLR_MCUN0GPIO91_Msk (0x8000000UL)             /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
35004 #define GPIO_MCUN0INT2CLR_MCUN0GPIO90_Pos (26UL)                    /*!< MCUN0GPIO90 (Bit 26)                                  */
35005 #define GPIO_MCUN0INT2CLR_MCUN0GPIO90_Msk (0x4000000UL)             /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
35006 #define GPIO_MCUN0INT2CLR_MCUN0GPIO89_Pos (25UL)                    /*!< MCUN0GPIO89 (Bit 25)                                  */
35007 #define GPIO_MCUN0INT2CLR_MCUN0GPIO89_Msk (0x2000000UL)             /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
35008 #define GPIO_MCUN0INT2CLR_MCUN0GPIO88_Pos (24UL)                    /*!< MCUN0GPIO88 (Bit 24)                                  */
35009 #define GPIO_MCUN0INT2CLR_MCUN0GPIO88_Msk (0x1000000UL)             /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
35010 #define GPIO_MCUN0INT2CLR_MCUN0GPIO87_Pos (23UL)                    /*!< MCUN0GPIO87 (Bit 23)                                  */
35011 #define GPIO_MCUN0INT2CLR_MCUN0GPIO87_Msk (0x800000UL)              /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
35012 #define GPIO_MCUN0INT2CLR_MCUN0GPIO86_Pos (22UL)                    /*!< MCUN0GPIO86 (Bit 22)                                  */
35013 #define GPIO_MCUN0INT2CLR_MCUN0GPIO86_Msk (0x400000UL)              /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
35014 #define GPIO_MCUN0INT2CLR_MCUN0GPIO85_Pos (21UL)                    /*!< MCUN0GPIO85 (Bit 21)                                  */
35015 #define GPIO_MCUN0INT2CLR_MCUN0GPIO85_Msk (0x200000UL)              /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
35016 #define GPIO_MCUN0INT2CLR_MCUN0GPIO84_Pos (20UL)                    /*!< MCUN0GPIO84 (Bit 20)                                  */
35017 #define GPIO_MCUN0INT2CLR_MCUN0GPIO84_Msk (0x100000UL)              /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
35018 #define GPIO_MCUN0INT2CLR_MCUN0GPIO83_Pos (19UL)                    /*!< MCUN0GPIO83 (Bit 19)                                  */
35019 #define GPIO_MCUN0INT2CLR_MCUN0GPIO83_Msk (0x80000UL)               /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
35020 #define GPIO_MCUN0INT2CLR_MCUN0GPIO82_Pos (18UL)                    /*!< MCUN0GPIO82 (Bit 18)                                  */
35021 #define GPIO_MCUN0INT2CLR_MCUN0GPIO82_Msk (0x40000UL)               /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
35022 #define GPIO_MCUN0INT2CLR_MCUN0GPIO81_Pos (17UL)                    /*!< MCUN0GPIO81 (Bit 17)                                  */
35023 #define GPIO_MCUN0INT2CLR_MCUN0GPIO81_Msk (0x20000UL)               /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
35024 #define GPIO_MCUN0INT2CLR_MCUN0GPIO80_Pos (16UL)                    /*!< MCUN0GPIO80 (Bit 16)                                  */
35025 #define GPIO_MCUN0INT2CLR_MCUN0GPIO80_Msk (0x10000UL)               /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
35026 #define GPIO_MCUN0INT2CLR_MCUN0GPIO79_Pos (15UL)                    /*!< MCUN0GPIO79 (Bit 15)                                  */
35027 #define GPIO_MCUN0INT2CLR_MCUN0GPIO79_Msk (0x8000UL)                /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
35028 #define GPIO_MCUN0INT2CLR_MCUN0GPIO78_Pos (14UL)                    /*!< MCUN0GPIO78 (Bit 14)                                  */
35029 #define GPIO_MCUN0INT2CLR_MCUN0GPIO78_Msk (0x4000UL)                /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
35030 #define GPIO_MCUN0INT2CLR_MCUN0GPIO77_Pos (13UL)                    /*!< MCUN0GPIO77 (Bit 13)                                  */
35031 #define GPIO_MCUN0INT2CLR_MCUN0GPIO77_Msk (0x2000UL)                /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
35032 #define GPIO_MCUN0INT2CLR_MCUN0GPIO76_Pos (12UL)                    /*!< MCUN0GPIO76 (Bit 12)                                  */
35033 #define GPIO_MCUN0INT2CLR_MCUN0GPIO76_Msk (0x1000UL)                /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
35034 #define GPIO_MCUN0INT2CLR_MCUN0GPIO75_Pos (11UL)                    /*!< MCUN0GPIO75 (Bit 11)                                  */
35035 #define GPIO_MCUN0INT2CLR_MCUN0GPIO75_Msk (0x800UL)                 /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
35036 #define GPIO_MCUN0INT2CLR_MCUN0GPIO74_Pos (10UL)                    /*!< MCUN0GPIO74 (Bit 10)                                  */
35037 #define GPIO_MCUN0INT2CLR_MCUN0GPIO74_Msk (0x400UL)                 /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
35038 #define GPIO_MCUN0INT2CLR_MCUN0GPIO73_Pos (9UL)                     /*!< MCUN0GPIO73 (Bit 9)                                   */
35039 #define GPIO_MCUN0INT2CLR_MCUN0GPIO73_Msk (0x200UL)                 /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
35040 #define GPIO_MCUN0INT2CLR_MCUN0GPIO72_Pos (8UL)                     /*!< MCUN0GPIO72 (Bit 8)                                   */
35041 #define GPIO_MCUN0INT2CLR_MCUN0GPIO72_Msk (0x100UL)                 /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
35042 #define GPIO_MCUN0INT2CLR_MCUN0GPIO71_Pos (7UL)                     /*!< MCUN0GPIO71 (Bit 7)                                   */
35043 #define GPIO_MCUN0INT2CLR_MCUN0GPIO71_Msk (0x80UL)                  /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
35044 #define GPIO_MCUN0INT2CLR_MCUN0GPIO70_Pos (6UL)                     /*!< MCUN0GPIO70 (Bit 6)                                   */
35045 #define GPIO_MCUN0INT2CLR_MCUN0GPIO70_Msk (0x40UL)                  /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
35046 #define GPIO_MCUN0INT2CLR_MCUN0GPIO69_Pos (5UL)                     /*!< MCUN0GPIO69 (Bit 5)                                   */
35047 #define GPIO_MCUN0INT2CLR_MCUN0GPIO69_Msk (0x20UL)                  /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
35048 #define GPIO_MCUN0INT2CLR_MCUN0GPIO68_Pos (4UL)                     /*!< MCUN0GPIO68 (Bit 4)                                   */
35049 #define GPIO_MCUN0INT2CLR_MCUN0GPIO68_Msk (0x10UL)                  /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
35050 #define GPIO_MCUN0INT2CLR_MCUN0GPIO67_Pos (3UL)                     /*!< MCUN0GPIO67 (Bit 3)                                   */
35051 #define GPIO_MCUN0INT2CLR_MCUN0GPIO67_Msk (0x8UL)                   /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
35052 #define GPIO_MCUN0INT2CLR_MCUN0GPIO66_Pos (2UL)                     /*!< MCUN0GPIO66 (Bit 2)                                   */
35053 #define GPIO_MCUN0INT2CLR_MCUN0GPIO66_Msk (0x4UL)                   /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
35054 #define GPIO_MCUN0INT2CLR_MCUN0GPIO65_Pos (1UL)                     /*!< MCUN0GPIO65 (Bit 1)                                   */
35055 #define GPIO_MCUN0INT2CLR_MCUN0GPIO65_Msk (0x2UL)                   /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
35056 #define GPIO_MCUN0INT2CLR_MCUN0GPIO64_Pos (0UL)                     /*!< MCUN0GPIO64 (Bit 0)                                   */
35057 #define GPIO_MCUN0INT2CLR_MCUN0GPIO64_Msk (0x1UL)                   /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
35058 /* =====================================================  MCUN0INT2SET  ====================================================== */
35059 #define GPIO_MCUN0INT2SET_MCUN0GPIO95_Pos (31UL)                    /*!< MCUN0GPIO95 (Bit 31)                                  */
35060 #define GPIO_MCUN0INT2SET_MCUN0GPIO95_Msk (0x80000000UL)            /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
35061 #define GPIO_MCUN0INT2SET_MCUN0GPIO94_Pos (30UL)                    /*!< MCUN0GPIO94 (Bit 30)                                  */
35062 #define GPIO_MCUN0INT2SET_MCUN0GPIO94_Msk (0x40000000UL)            /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
35063 #define GPIO_MCUN0INT2SET_MCUN0GPIO93_Pos (29UL)                    /*!< MCUN0GPIO93 (Bit 29)                                  */
35064 #define GPIO_MCUN0INT2SET_MCUN0GPIO93_Msk (0x20000000UL)            /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
35065 #define GPIO_MCUN0INT2SET_MCUN0GPIO92_Pos (28UL)                    /*!< MCUN0GPIO92 (Bit 28)                                  */
35066 #define GPIO_MCUN0INT2SET_MCUN0GPIO92_Msk (0x10000000UL)            /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
35067 #define GPIO_MCUN0INT2SET_MCUN0GPIO91_Pos (27UL)                    /*!< MCUN0GPIO91 (Bit 27)                                  */
35068 #define GPIO_MCUN0INT2SET_MCUN0GPIO91_Msk (0x8000000UL)             /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
35069 #define GPIO_MCUN0INT2SET_MCUN0GPIO90_Pos (26UL)                    /*!< MCUN0GPIO90 (Bit 26)                                  */
35070 #define GPIO_MCUN0INT2SET_MCUN0GPIO90_Msk (0x4000000UL)             /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
35071 #define GPIO_MCUN0INT2SET_MCUN0GPIO89_Pos (25UL)                    /*!< MCUN0GPIO89 (Bit 25)                                  */
35072 #define GPIO_MCUN0INT2SET_MCUN0GPIO89_Msk (0x2000000UL)             /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
35073 #define GPIO_MCUN0INT2SET_MCUN0GPIO88_Pos (24UL)                    /*!< MCUN0GPIO88 (Bit 24)                                  */
35074 #define GPIO_MCUN0INT2SET_MCUN0GPIO88_Msk (0x1000000UL)             /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
35075 #define GPIO_MCUN0INT2SET_MCUN0GPIO87_Pos (23UL)                    /*!< MCUN0GPIO87 (Bit 23)                                  */
35076 #define GPIO_MCUN0INT2SET_MCUN0GPIO87_Msk (0x800000UL)              /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
35077 #define GPIO_MCUN0INT2SET_MCUN0GPIO86_Pos (22UL)                    /*!< MCUN0GPIO86 (Bit 22)                                  */
35078 #define GPIO_MCUN0INT2SET_MCUN0GPIO86_Msk (0x400000UL)              /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
35079 #define GPIO_MCUN0INT2SET_MCUN0GPIO85_Pos (21UL)                    /*!< MCUN0GPIO85 (Bit 21)                                  */
35080 #define GPIO_MCUN0INT2SET_MCUN0GPIO85_Msk (0x200000UL)              /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
35081 #define GPIO_MCUN0INT2SET_MCUN0GPIO84_Pos (20UL)                    /*!< MCUN0GPIO84 (Bit 20)                                  */
35082 #define GPIO_MCUN0INT2SET_MCUN0GPIO84_Msk (0x100000UL)              /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
35083 #define GPIO_MCUN0INT2SET_MCUN0GPIO83_Pos (19UL)                    /*!< MCUN0GPIO83 (Bit 19)                                  */
35084 #define GPIO_MCUN0INT2SET_MCUN0GPIO83_Msk (0x80000UL)               /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
35085 #define GPIO_MCUN0INT2SET_MCUN0GPIO82_Pos (18UL)                    /*!< MCUN0GPIO82 (Bit 18)                                  */
35086 #define GPIO_MCUN0INT2SET_MCUN0GPIO82_Msk (0x40000UL)               /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
35087 #define GPIO_MCUN0INT2SET_MCUN0GPIO81_Pos (17UL)                    /*!< MCUN0GPIO81 (Bit 17)                                  */
35088 #define GPIO_MCUN0INT2SET_MCUN0GPIO81_Msk (0x20000UL)               /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
35089 #define GPIO_MCUN0INT2SET_MCUN0GPIO80_Pos (16UL)                    /*!< MCUN0GPIO80 (Bit 16)                                  */
35090 #define GPIO_MCUN0INT2SET_MCUN0GPIO80_Msk (0x10000UL)               /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
35091 #define GPIO_MCUN0INT2SET_MCUN0GPIO79_Pos (15UL)                    /*!< MCUN0GPIO79 (Bit 15)                                  */
35092 #define GPIO_MCUN0INT2SET_MCUN0GPIO79_Msk (0x8000UL)                /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
35093 #define GPIO_MCUN0INT2SET_MCUN0GPIO78_Pos (14UL)                    /*!< MCUN0GPIO78 (Bit 14)                                  */
35094 #define GPIO_MCUN0INT2SET_MCUN0GPIO78_Msk (0x4000UL)                /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
35095 #define GPIO_MCUN0INT2SET_MCUN0GPIO77_Pos (13UL)                    /*!< MCUN0GPIO77 (Bit 13)                                  */
35096 #define GPIO_MCUN0INT2SET_MCUN0GPIO77_Msk (0x2000UL)                /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
35097 #define GPIO_MCUN0INT2SET_MCUN0GPIO76_Pos (12UL)                    /*!< MCUN0GPIO76 (Bit 12)                                  */
35098 #define GPIO_MCUN0INT2SET_MCUN0GPIO76_Msk (0x1000UL)                /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
35099 #define GPIO_MCUN0INT2SET_MCUN0GPIO75_Pos (11UL)                    /*!< MCUN0GPIO75 (Bit 11)                                  */
35100 #define GPIO_MCUN0INT2SET_MCUN0GPIO75_Msk (0x800UL)                 /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
35101 #define GPIO_MCUN0INT2SET_MCUN0GPIO74_Pos (10UL)                    /*!< MCUN0GPIO74 (Bit 10)                                  */
35102 #define GPIO_MCUN0INT2SET_MCUN0GPIO74_Msk (0x400UL)                 /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
35103 #define GPIO_MCUN0INT2SET_MCUN0GPIO73_Pos (9UL)                     /*!< MCUN0GPIO73 (Bit 9)                                   */
35104 #define GPIO_MCUN0INT2SET_MCUN0GPIO73_Msk (0x200UL)                 /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
35105 #define GPIO_MCUN0INT2SET_MCUN0GPIO72_Pos (8UL)                     /*!< MCUN0GPIO72 (Bit 8)                                   */
35106 #define GPIO_MCUN0INT2SET_MCUN0GPIO72_Msk (0x100UL)                 /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
35107 #define GPIO_MCUN0INT2SET_MCUN0GPIO71_Pos (7UL)                     /*!< MCUN0GPIO71 (Bit 7)                                   */
35108 #define GPIO_MCUN0INT2SET_MCUN0GPIO71_Msk (0x80UL)                  /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
35109 #define GPIO_MCUN0INT2SET_MCUN0GPIO70_Pos (6UL)                     /*!< MCUN0GPIO70 (Bit 6)                                   */
35110 #define GPIO_MCUN0INT2SET_MCUN0GPIO70_Msk (0x40UL)                  /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
35111 #define GPIO_MCUN0INT2SET_MCUN0GPIO69_Pos (5UL)                     /*!< MCUN0GPIO69 (Bit 5)                                   */
35112 #define GPIO_MCUN0INT2SET_MCUN0GPIO69_Msk (0x20UL)                  /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
35113 #define GPIO_MCUN0INT2SET_MCUN0GPIO68_Pos (4UL)                     /*!< MCUN0GPIO68 (Bit 4)                                   */
35114 #define GPIO_MCUN0INT2SET_MCUN0GPIO68_Msk (0x10UL)                  /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
35115 #define GPIO_MCUN0INT2SET_MCUN0GPIO67_Pos (3UL)                     /*!< MCUN0GPIO67 (Bit 3)                                   */
35116 #define GPIO_MCUN0INT2SET_MCUN0GPIO67_Msk (0x8UL)                   /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
35117 #define GPIO_MCUN0INT2SET_MCUN0GPIO66_Pos (2UL)                     /*!< MCUN0GPIO66 (Bit 2)                                   */
35118 #define GPIO_MCUN0INT2SET_MCUN0GPIO66_Msk (0x4UL)                   /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
35119 #define GPIO_MCUN0INT2SET_MCUN0GPIO65_Pos (1UL)                     /*!< MCUN0GPIO65 (Bit 1)                                   */
35120 #define GPIO_MCUN0INT2SET_MCUN0GPIO65_Msk (0x2UL)                   /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
35121 #define GPIO_MCUN0INT2SET_MCUN0GPIO64_Pos (0UL)                     /*!< MCUN0GPIO64 (Bit 0)                                   */
35122 #define GPIO_MCUN0INT2SET_MCUN0GPIO64_Msk (0x1UL)                   /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
35123 /* ======================================================  MCUN0INT3EN  ====================================================== */
35124 #define GPIO_MCUN0INT3EN_MCUN0GPIO127_Pos (31UL)                    /*!< MCUN0GPIO127 (Bit 31)                                 */
35125 #define GPIO_MCUN0INT3EN_MCUN0GPIO127_Msk (0x80000000UL)            /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
35126 #define GPIO_MCUN0INT3EN_MCUN0GPIO126_Pos (30UL)                    /*!< MCUN0GPIO126 (Bit 30)                                 */
35127 #define GPIO_MCUN0INT3EN_MCUN0GPIO126_Msk (0x40000000UL)            /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
35128 #define GPIO_MCUN0INT3EN_MCUN0GPIO125_Pos (29UL)                    /*!< MCUN0GPIO125 (Bit 29)                                 */
35129 #define GPIO_MCUN0INT3EN_MCUN0GPIO125_Msk (0x20000000UL)            /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
35130 #define GPIO_MCUN0INT3EN_MCUN0GPIO124_Pos (28UL)                    /*!< MCUN0GPIO124 (Bit 28)                                 */
35131 #define GPIO_MCUN0INT3EN_MCUN0GPIO124_Msk (0x10000000UL)            /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
35132 #define GPIO_MCUN0INT3EN_MCUN0GPIO123_Pos (27UL)                    /*!< MCUN0GPIO123 (Bit 27)                                 */
35133 #define GPIO_MCUN0INT3EN_MCUN0GPIO123_Msk (0x8000000UL)             /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
35134 #define GPIO_MCUN0INT3EN_MCUN0GPIO122_Pos (26UL)                    /*!< MCUN0GPIO122 (Bit 26)                                 */
35135 #define GPIO_MCUN0INT3EN_MCUN0GPIO122_Msk (0x4000000UL)             /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
35136 #define GPIO_MCUN0INT3EN_MCUN0GPIO121_Pos (25UL)                    /*!< MCUN0GPIO121 (Bit 25)                                 */
35137 #define GPIO_MCUN0INT3EN_MCUN0GPIO121_Msk (0x2000000UL)             /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
35138 #define GPIO_MCUN0INT3EN_MCUN0GPIO120_Pos (24UL)                    /*!< MCUN0GPIO120 (Bit 24)                                 */
35139 #define GPIO_MCUN0INT3EN_MCUN0GPIO120_Msk (0x1000000UL)             /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
35140 #define GPIO_MCUN0INT3EN_MCUN0GPIO119_Pos (23UL)                    /*!< MCUN0GPIO119 (Bit 23)                                 */
35141 #define GPIO_MCUN0INT3EN_MCUN0GPIO119_Msk (0x800000UL)              /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
35142 #define GPIO_MCUN0INT3EN_MCUN0GPIO118_Pos (22UL)                    /*!< MCUN0GPIO118 (Bit 22)                                 */
35143 #define GPIO_MCUN0INT3EN_MCUN0GPIO118_Msk (0x400000UL)              /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
35144 #define GPIO_MCUN0INT3EN_MCUN0GPIO117_Pos (21UL)                    /*!< MCUN0GPIO117 (Bit 21)                                 */
35145 #define GPIO_MCUN0INT3EN_MCUN0GPIO117_Msk (0x200000UL)              /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
35146 #define GPIO_MCUN0INT3EN_MCUN0GPIO116_Pos (20UL)                    /*!< MCUN0GPIO116 (Bit 20)                                 */
35147 #define GPIO_MCUN0INT3EN_MCUN0GPIO116_Msk (0x100000UL)              /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
35148 #define GPIO_MCUN0INT3EN_MCUN0GPIO115_Pos (19UL)                    /*!< MCUN0GPIO115 (Bit 19)                                 */
35149 #define GPIO_MCUN0INT3EN_MCUN0GPIO115_Msk (0x80000UL)               /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
35150 #define GPIO_MCUN0INT3EN_MCUN0GPIO114_Pos (18UL)                    /*!< MCUN0GPIO114 (Bit 18)                                 */
35151 #define GPIO_MCUN0INT3EN_MCUN0GPIO114_Msk (0x40000UL)               /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
35152 #define GPIO_MCUN0INT3EN_MCUN0GPIO113_Pos (17UL)                    /*!< MCUN0GPIO113 (Bit 17)                                 */
35153 #define GPIO_MCUN0INT3EN_MCUN0GPIO113_Msk (0x20000UL)               /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
35154 #define GPIO_MCUN0INT3EN_MCUN0GPIO112_Pos (16UL)                    /*!< MCUN0GPIO112 (Bit 16)                                 */
35155 #define GPIO_MCUN0INT3EN_MCUN0GPIO112_Msk (0x10000UL)               /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
35156 #define GPIO_MCUN0INT3EN_MCUN0GPIO111_Pos (15UL)                    /*!< MCUN0GPIO111 (Bit 15)                                 */
35157 #define GPIO_MCUN0INT3EN_MCUN0GPIO111_Msk (0x8000UL)                /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
35158 #define GPIO_MCUN0INT3EN_MCUN0GPIO110_Pos (14UL)                    /*!< MCUN0GPIO110 (Bit 14)                                 */
35159 #define GPIO_MCUN0INT3EN_MCUN0GPIO110_Msk (0x4000UL)                /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
35160 #define GPIO_MCUN0INT3EN_MCUN0GPIO109_Pos (13UL)                    /*!< MCUN0GPIO109 (Bit 13)                                 */
35161 #define GPIO_MCUN0INT3EN_MCUN0GPIO109_Msk (0x2000UL)                /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
35162 #define GPIO_MCUN0INT3EN_MCUN0GPIO108_Pos (12UL)                    /*!< MCUN0GPIO108 (Bit 12)                                 */
35163 #define GPIO_MCUN0INT3EN_MCUN0GPIO108_Msk (0x1000UL)                /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
35164 #define GPIO_MCUN0INT3EN_MCUN0GPIO107_Pos (11UL)                    /*!< MCUN0GPIO107 (Bit 11)                                 */
35165 #define GPIO_MCUN0INT3EN_MCUN0GPIO107_Msk (0x800UL)                 /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
35166 #define GPIO_MCUN0INT3EN_MCUN0GPIO106_Pos (10UL)                    /*!< MCUN0GPIO106 (Bit 10)                                 */
35167 #define GPIO_MCUN0INT3EN_MCUN0GPIO106_Msk (0x400UL)                 /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
35168 #define GPIO_MCUN0INT3EN_MCUN0GPIO105_Pos (9UL)                     /*!< MCUN0GPIO105 (Bit 9)                                  */
35169 #define GPIO_MCUN0INT3EN_MCUN0GPIO105_Msk (0x200UL)                 /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
35170 #define GPIO_MCUN0INT3EN_MCUN0GPIO104_Pos (8UL)                     /*!< MCUN0GPIO104 (Bit 8)                                  */
35171 #define GPIO_MCUN0INT3EN_MCUN0GPIO104_Msk (0x100UL)                 /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
35172 #define GPIO_MCUN0INT3EN_MCUN0GPIO103_Pos (7UL)                     /*!< MCUN0GPIO103 (Bit 7)                                  */
35173 #define GPIO_MCUN0INT3EN_MCUN0GPIO103_Msk (0x80UL)                  /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
35174 #define GPIO_MCUN0INT3EN_MCUN0GPIO102_Pos (6UL)                     /*!< MCUN0GPIO102 (Bit 6)                                  */
35175 #define GPIO_MCUN0INT3EN_MCUN0GPIO102_Msk (0x40UL)                  /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
35176 #define GPIO_MCUN0INT3EN_MCUN0GPIO101_Pos (5UL)                     /*!< MCUN0GPIO101 (Bit 5)                                  */
35177 #define GPIO_MCUN0INT3EN_MCUN0GPIO101_Msk (0x20UL)                  /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
35178 #define GPIO_MCUN0INT3EN_MCUN0GPIO100_Pos (4UL)                     /*!< MCUN0GPIO100 (Bit 4)                                  */
35179 #define GPIO_MCUN0INT3EN_MCUN0GPIO100_Msk (0x10UL)                  /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
35180 #define GPIO_MCUN0INT3EN_MCUN0GPIO99_Pos  (3UL)                     /*!< MCUN0GPIO99 (Bit 3)                                   */
35181 #define GPIO_MCUN0INT3EN_MCUN0GPIO99_Msk  (0x8UL)                   /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
35182 #define GPIO_MCUN0INT3EN_MCUN0GPIO98_Pos  (2UL)                     /*!< MCUN0GPIO98 (Bit 2)                                   */
35183 #define GPIO_MCUN0INT3EN_MCUN0GPIO98_Msk  (0x4UL)                   /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
35184 #define GPIO_MCUN0INT3EN_MCUN0GPIO97_Pos  (1UL)                     /*!< MCUN0GPIO97 (Bit 1)                                   */
35185 #define GPIO_MCUN0INT3EN_MCUN0GPIO97_Msk  (0x2UL)                   /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
35186 #define GPIO_MCUN0INT3EN_MCUN0GPIO96_Pos  (0UL)                     /*!< MCUN0GPIO96 (Bit 0)                                   */
35187 #define GPIO_MCUN0INT3EN_MCUN0GPIO96_Msk  (0x1UL)                   /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
35188 /* =====================================================  MCUN0INT3STAT  ===================================================== */
35189 #define GPIO_MCUN0INT3STAT_MCUN0GPIO127_Pos (31UL)                  /*!< MCUN0GPIO127 (Bit 31)                                 */
35190 #define GPIO_MCUN0INT3STAT_MCUN0GPIO127_Msk (0x80000000UL)          /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
35191 #define GPIO_MCUN0INT3STAT_MCUN0GPIO126_Pos (30UL)                  /*!< MCUN0GPIO126 (Bit 30)                                 */
35192 #define GPIO_MCUN0INT3STAT_MCUN0GPIO126_Msk (0x40000000UL)          /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
35193 #define GPIO_MCUN0INT3STAT_MCUN0GPIO125_Pos (29UL)                  /*!< MCUN0GPIO125 (Bit 29)                                 */
35194 #define GPIO_MCUN0INT3STAT_MCUN0GPIO125_Msk (0x20000000UL)          /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
35195 #define GPIO_MCUN0INT3STAT_MCUN0GPIO124_Pos (28UL)                  /*!< MCUN0GPIO124 (Bit 28)                                 */
35196 #define GPIO_MCUN0INT3STAT_MCUN0GPIO124_Msk (0x10000000UL)          /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
35197 #define GPIO_MCUN0INT3STAT_MCUN0GPIO123_Pos (27UL)                  /*!< MCUN0GPIO123 (Bit 27)                                 */
35198 #define GPIO_MCUN0INT3STAT_MCUN0GPIO123_Msk (0x8000000UL)           /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
35199 #define GPIO_MCUN0INT3STAT_MCUN0GPIO122_Pos (26UL)                  /*!< MCUN0GPIO122 (Bit 26)                                 */
35200 #define GPIO_MCUN0INT3STAT_MCUN0GPIO122_Msk (0x4000000UL)           /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
35201 #define GPIO_MCUN0INT3STAT_MCUN0GPIO121_Pos (25UL)                  /*!< MCUN0GPIO121 (Bit 25)                                 */
35202 #define GPIO_MCUN0INT3STAT_MCUN0GPIO121_Msk (0x2000000UL)           /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
35203 #define GPIO_MCUN0INT3STAT_MCUN0GPIO120_Pos (24UL)                  /*!< MCUN0GPIO120 (Bit 24)                                 */
35204 #define GPIO_MCUN0INT3STAT_MCUN0GPIO120_Msk (0x1000000UL)           /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
35205 #define GPIO_MCUN0INT3STAT_MCUN0GPIO119_Pos (23UL)                  /*!< MCUN0GPIO119 (Bit 23)                                 */
35206 #define GPIO_MCUN0INT3STAT_MCUN0GPIO119_Msk (0x800000UL)            /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
35207 #define GPIO_MCUN0INT3STAT_MCUN0GPIO118_Pos (22UL)                  /*!< MCUN0GPIO118 (Bit 22)                                 */
35208 #define GPIO_MCUN0INT3STAT_MCUN0GPIO118_Msk (0x400000UL)            /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
35209 #define GPIO_MCUN0INT3STAT_MCUN0GPIO117_Pos (21UL)                  /*!< MCUN0GPIO117 (Bit 21)                                 */
35210 #define GPIO_MCUN0INT3STAT_MCUN0GPIO117_Msk (0x200000UL)            /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
35211 #define GPIO_MCUN0INT3STAT_MCUN0GPIO116_Pos (20UL)                  /*!< MCUN0GPIO116 (Bit 20)                                 */
35212 #define GPIO_MCUN0INT3STAT_MCUN0GPIO116_Msk (0x100000UL)            /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
35213 #define GPIO_MCUN0INT3STAT_MCUN0GPIO115_Pos (19UL)                  /*!< MCUN0GPIO115 (Bit 19)                                 */
35214 #define GPIO_MCUN0INT3STAT_MCUN0GPIO115_Msk (0x80000UL)             /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
35215 #define GPIO_MCUN0INT3STAT_MCUN0GPIO114_Pos (18UL)                  /*!< MCUN0GPIO114 (Bit 18)                                 */
35216 #define GPIO_MCUN0INT3STAT_MCUN0GPIO114_Msk (0x40000UL)             /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
35217 #define GPIO_MCUN0INT3STAT_MCUN0GPIO113_Pos (17UL)                  /*!< MCUN0GPIO113 (Bit 17)                                 */
35218 #define GPIO_MCUN0INT3STAT_MCUN0GPIO113_Msk (0x20000UL)             /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
35219 #define GPIO_MCUN0INT3STAT_MCUN0GPIO112_Pos (16UL)                  /*!< MCUN0GPIO112 (Bit 16)                                 */
35220 #define GPIO_MCUN0INT3STAT_MCUN0GPIO112_Msk (0x10000UL)             /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
35221 #define GPIO_MCUN0INT3STAT_MCUN0GPIO111_Pos (15UL)                  /*!< MCUN0GPIO111 (Bit 15)                                 */
35222 #define GPIO_MCUN0INT3STAT_MCUN0GPIO111_Msk (0x8000UL)              /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
35223 #define GPIO_MCUN0INT3STAT_MCUN0GPIO110_Pos (14UL)                  /*!< MCUN0GPIO110 (Bit 14)                                 */
35224 #define GPIO_MCUN0INT3STAT_MCUN0GPIO110_Msk (0x4000UL)              /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
35225 #define GPIO_MCUN0INT3STAT_MCUN0GPIO109_Pos (13UL)                  /*!< MCUN0GPIO109 (Bit 13)                                 */
35226 #define GPIO_MCUN0INT3STAT_MCUN0GPIO109_Msk (0x2000UL)              /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
35227 #define GPIO_MCUN0INT3STAT_MCUN0GPIO108_Pos (12UL)                  /*!< MCUN0GPIO108 (Bit 12)                                 */
35228 #define GPIO_MCUN0INT3STAT_MCUN0GPIO108_Msk (0x1000UL)              /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
35229 #define GPIO_MCUN0INT3STAT_MCUN0GPIO107_Pos (11UL)                  /*!< MCUN0GPIO107 (Bit 11)                                 */
35230 #define GPIO_MCUN0INT3STAT_MCUN0GPIO107_Msk (0x800UL)               /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
35231 #define GPIO_MCUN0INT3STAT_MCUN0GPIO106_Pos (10UL)                  /*!< MCUN0GPIO106 (Bit 10)                                 */
35232 #define GPIO_MCUN0INT3STAT_MCUN0GPIO106_Msk (0x400UL)               /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
35233 #define GPIO_MCUN0INT3STAT_MCUN0GPIO105_Pos (9UL)                   /*!< MCUN0GPIO105 (Bit 9)                                  */
35234 #define GPIO_MCUN0INT3STAT_MCUN0GPIO105_Msk (0x200UL)               /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
35235 #define GPIO_MCUN0INT3STAT_MCUN0GPIO104_Pos (8UL)                   /*!< MCUN0GPIO104 (Bit 8)                                  */
35236 #define GPIO_MCUN0INT3STAT_MCUN0GPIO104_Msk (0x100UL)               /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
35237 #define GPIO_MCUN0INT3STAT_MCUN0GPIO103_Pos (7UL)                   /*!< MCUN0GPIO103 (Bit 7)                                  */
35238 #define GPIO_MCUN0INT3STAT_MCUN0GPIO103_Msk (0x80UL)                /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
35239 #define GPIO_MCUN0INT3STAT_MCUN0GPIO102_Pos (6UL)                   /*!< MCUN0GPIO102 (Bit 6)                                  */
35240 #define GPIO_MCUN0INT3STAT_MCUN0GPIO102_Msk (0x40UL)                /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
35241 #define GPIO_MCUN0INT3STAT_MCUN0GPIO101_Pos (5UL)                   /*!< MCUN0GPIO101 (Bit 5)                                  */
35242 #define GPIO_MCUN0INT3STAT_MCUN0GPIO101_Msk (0x20UL)                /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
35243 #define GPIO_MCUN0INT3STAT_MCUN0GPIO100_Pos (4UL)                   /*!< MCUN0GPIO100 (Bit 4)                                  */
35244 #define GPIO_MCUN0INT3STAT_MCUN0GPIO100_Msk (0x10UL)                /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
35245 #define GPIO_MCUN0INT3STAT_MCUN0GPIO99_Pos (3UL)                    /*!< MCUN0GPIO99 (Bit 3)                                   */
35246 #define GPIO_MCUN0INT3STAT_MCUN0GPIO99_Msk (0x8UL)                  /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
35247 #define GPIO_MCUN0INT3STAT_MCUN0GPIO98_Pos (2UL)                    /*!< MCUN0GPIO98 (Bit 2)                                   */
35248 #define GPIO_MCUN0INT3STAT_MCUN0GPIO98_Msk (0x4UL)                  /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
35249 #define GPIO_MCUN0INT3STAT_MCUN0GPIO97_Pos (1UL)                    /*!< MCUN0GPIO97 (Bit 1)                                   */
35250 #define GPIO_MCUN0INT3STAT_MCUN0GPIO97_Msk (0x2UL)                  /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
35251 #define GPIO_MCUN0INT3STAT_MCUN0GPIO96_Pos (0UL)                    /*!< MCUN0GPIO96 (Bit 0)                                   */
35252 #define GPIO_MCUN0INT3STAT_MCUN0GPIO96_Msk (0x1UL)                  /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
35253 /* =====================================================  MCUN0INT3CLR  ====================================================== */
35254 #define GPIO_MCUN0INT3CLR_MCUN0GPIO127_Pos (31UL)                   /*!< MCUN0GPIO127 (Bit 31)                                 */
35255 #define GPIO_MCUN0INT3CLR_MCUN0GPIO127_Msk (0x80000000UL)           /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
35256 #define GPIO_MCUN0INT3CLR_MCUN0GPIO126_Pos (30UL)                   /*!< MCUN0GPIO126 (Bit 30)                                 */
35257 #define GPIO_MCUN0INT3CLR_MCUN0GPIO126_Msk (0x40000000UL)           /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
35258 #define GPIO_MCUN0INT3CLR_MCUN0GPIO125_Pos (29UL)                   /*!< MCUN0GPIO125 (Bit 29)                                 */
35259 #define GPIO_MCUN0INT3CLR_MCUN0GPIO125_Msk (0x20000000UL)           /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
35260 #define GPIO_MCUN0INT3CLR_MCUN0GPIO124_Pos (28UL)                   /*!< MCUN0GPIO124 (Bit 28)                                 */
35261 #define GPIO_MCUN0INT3CLR_MCUN0GPIO124_Msk (0x10000000UL)           /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
35262 #define GPIO_MCUN0INT3CLR_MCUN0GPIO123_Pos (27UL)                   /*!< MCUN0GPIO123 (Bit 27)                                 */
35263 #define GPIO_MCUN0INT3CLR_MCUN0GPIO123_Msk (0x8000000UL)            /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
35264 #define GPIO_MCUN0INT3CLR_MCUN0GPIO122_Pos (26UL)                   /*!< MCUN0GPIO122 (Bit 26)                                 */
35265 #define GPIO_MCUN0INT3CLR_MCUN0GPIO122_Msk (0x4000000UL)            /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
35266 #define GPIO_MCUN0INT3CLR_MCUN0GPIO121_Pos (25UL)                   /*!< MCUN0GPIO121 (Bit 25)                                 */
35267 #define GPIO_MCUN0INT3CLR_MCUN0GPIO121_Msk (0x2000000UL)            /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
35268 #define GPIO_MCUN0INT3CLR_MCUN0GPIO120_Pos (24UL)                   /*!< MCUN0GPIO120 (Bit 24)                                 */
35269 #define GPIO_MCUN0INT3CLR_MCUN0GPIO120_Msk (0x1000000UL)            /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
35270 #define GPIO_MCUN0INT3CLR_MCUN0GPIO119_Pos (23UL)                   /*!< MCUN0GPIO119 (Bit 23)                                 */
35271 #define GPIO_MCUN0INT3CLR_MCUN0GPIO119_Msk (0x800000UL)             /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
35272 #define GPIO_MCUN0INT3CLR_MCUN0GPIO118_Pos (22UL)                   /*!< MCUN0GPIO118 (Bit 22)                                 */
35273 #define GPIO_MCUN0INT3CLR_MCUN0GPIO118_Msk (0x400000UL)             /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
35274 #define GPIO_MCUN0INT3CLR_MCUN0GPIO117_Pos (21UL)                   /*!< MCUN0GPIO117 (Bit 21)                                 */
35275 #define GPIO_MCUN0INT3CLR_MCUN0GPIO117_Msk (0x200000UL)             /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
35276 #define GPIO_MCUN0INT3CLR_MCUN0GPIO116_Pos (20UL)                   /*!< MCUN0GPIO116 (Bit 20)                                 */
35277 #define GPIO_MCUN0INT3CLR_MCUN0GPIO116_Msk (0x100000UL)             /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
35278 #define GPIO_MCUN0INT3CLR_MCUN0GPIO115_Pos (19UL)                   /*!< MCUN0GPIO115 (Bit 19)                                 */
35279 #define GPIO_MCUN0INT3CLR_MCUN0GPIO115_Msk (0x80000UL)              /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
35280 #define GPIO_MCUN0INT3CLR_MCUN0GPIO114_Pos (18UL)                   /*!< MCUN0GPIO114 (Bit 18)                                 */
35281 #define GPIO_MCUN0INT3CLR_MCUN0GPIO114_Msk (0x40000UL)              /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
35282 #define GPIO_MCUN0INT3CLR_MCUN0GPIO113_Pos (17UL)                   /*!< MCUN0GPIO113 (Bit 17)                                 */
35283 #define GPIO_MCUN0INT3CLR_MCUN0GPIO113_Msk (0x20000UL)              /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
35284 #define GPIO_MCUN0INT3CLR_MCUN0GPIO112_Pos (16UL)                   /*!< MCUN0GPIO112 (Bit 16)                                 */
35285 #define GPIO_MCUN0INT3CLR_MCUN0GPIO112_Msk (0x10000UL)              /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
35286 #define GPIO_MCUN0INT3CLR_MCUN0GPIO111_Pos (15UL)                   /*!< MCUN0GPIO111 (Bit 15)                                 */
35287 #define GPIO_MCUN0INT3CLR_MCUN0GPIO111_Msk (0x8000UL)               /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
35288 #define GPIO_MCUN0INT3CLR_MCUN0GPIO110_Pos (14UL)                   /*!< MCUN0GPIO110 (Bit 14)                                 */
35289 #define GPIO_MCUN0INT3CLR_MCUN0GPIO110_Msk (0x4000UL)               /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
35290 #define GPIO_MCUN0INT3CLR_MCUN0GPIO109_Pos (13UL)                   /*!< MCUN0GPIO109 (Bit 13)                                 */
35291 #define GPIO_MCUN0INT3CLR_MCUN0GPIO109_Msk (0x2000UL)               /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
35292 #define GPIO_MCUN0INT3CLR_MCUN0GPIO108_Pos (12UL)                   /*!< MCUN0GPIO108 (Bit 12)                                 */
35293 #define GPIO_MCUN0INT3CLR_MCUN0GPIO108_Msk (0x1000UL)               /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
35294 #define GPIO_MCUN0INT3CLR_MCUN0GPIO107_Pos (11UL)                   /*!< MCUN0GPIO107 (Bit 11)                                 */
35295 #define GPIO_MCUN0INT3CLR_MCUN0GPIO107_Msk (0x800UL)                /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
35296 #define GPIO_MCUN0INT3CLR_MCUN0GPIO106_Pos (10UL)                   /*!< MCUN0GPIO106 (Bit 10)                                 */
35297 #define GPIO_MCUN0INT3CLR_MCUN0GPIO106_Msk (0x400UL)                /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
35298 #define GPIO_MCUN0INT3CLR_MCUN0GPIO105_Pos (9UL)                    /*!< MCUN0GPIO105 (Bit 9)                                  */
35299 #define GPIO_MCUN0INT3CLR_MCUN0GPIO105_Msk (0x200UL)                /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
35300 #define GPIO_MCUN0INT3CLR_MCUN0GPIO104_Pos (8UL)                    /*!< MCUN0GPIO104 (Bit 8)                                  */
35301 #define GPIO_MCUN0INT3CLR_MCUN0GPIO104_Msk (0x100UL)                /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
35302 #define GPIO_MCUN0INT3CLR_MCUN0GPIO103_Pos (7UL)                    /*!< MCUN0GPIO103 (Bit 7)                                  */
35303 #define GPIO_MCUN0INT3CLR_MCUN0GPIO103_Msk (0x80UL)                 /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
35304 #define GPIO_MCUN0INT3CLR_MCUN0GPIO102_Pos (6UL)                    /*!< MCUN0GPIO102 (Bit 6)                                  */
35305 #define GPIO_MCUN0INT3CLR_MCUN0GPIO102_Msk (0x40UL)                 /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
35306 #define GPIO_MCUN0INT3CLR_MCUN0GPIO101_Pos (5UL)                    /*!< MCUN0GPIO101 (Bit 5)                                  */
35307 #define GPIO_MCUN0INT3CLR_MCUN0GPIO101_Msk (0x20UL)                 /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
35308 #define GPIO_MCUN0INT3CLR_MCUN0GPIO100_Pos (4UL)                    /*!< MCUN0GPIO100 (Bit 4)                                  */
35309 #define GPIO_MCUN0INT3CLR_MCUN0GPIO100_Msk (0x10UL)                 /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
35310 #define GPIO_MCUN0INT3CLR_MCUN0GPIO99_Pos (3UL)                     /*!< MCUN0GPIO99 (Bit 3)                                   */
35311 #define GPIO_MCUN0INT3CLR_MCUN0GPIO99_Msk (0x8UL)                   /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
35312 #define GPIO_MCUN0INT3CLR_MCUN0GPIO98_Pos (2UL)                     /*!< MCUN0GPIO98 (Bit 2)                                   */
35313 #define GPIO_MCUN0INT3CLR_MCUN0GPIO98_Msk (0x4UL)                   /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
35314 #define GPIO_MCUN0INT3CLR_MCUN0GPIO97_Pos (1UL)                     /*!< MCUN0GPIO97 (Bit 1)                                   */
35315 #define GPIO_MCUN0INT3CLR_MCUN0GPIO97_Msk (0x2UL)                   /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
35316 #define GPIO_MCUN0INT3CLR_MCUN0GPIO96_Pos (0UL)                     /*!< MCUN0GPIO96 (Bit 0)                                   */
35317 #define GPIO_MCUN0INT3CLR_MCUN0GPIO96_Msk (0x1UL)                   /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
35318 /* =====================================================  MCUN0INT3SET  ====================================================== */
35319 #define GPIO_MCUN0INT3SET_MCUN0GPIO127_Pos (31UL)                   /*!< MCUN0GPIO127 (Bit 31)                                 */
35320 #define GPIO_MCUN0INT3SET_MCUN0GPIO127_Msk (0x80000000UL)           /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
35321 #define GPIO_MCUN0INT3SET_MCUN0GPIO126_Pos (30UL)                   /*!< MCUN0GPIO126 (Bit 30)                                 */
35322 #define GPIO_MCUN0INT3SET_MCUN0GPIO126_Msk (0x40000000UL)           /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
35323 #define GPIO_MCUN0INT3SET_MCUN0GPIO125_Pos (29UL)                   /*!< MCUN0GPIO125 (Bit 29)                                 */
35324 #define GPIO_MCUN0INT3SET_MCUN0GPIO125_Msk (0x20000000UL)           /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
35325 #define GPIO_MCUN0INT3SET_MCUN0GPIO124_Pos (28UL)                   /*!< MCUN0GPIO124 (Bit 28)                                 */
35326 #define GPIO_MCUN0INT3SET_MCUN0GPIO124_Msk (0x10000000UL)           /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
35327 #define GPIO_MCUN0INT3SET_MCUN0GPIO123_Pos (27UL)                   /*!< MCUN0GPIO123 (Bit 27)                                 */
35328 #define GPIO_MCUN0INT3SET_MCUN0GPIO123_Msk (0x8000000UL)            /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
35329 #define GPIO_MCUN0INT3SET_MCUN0GPIO122_Pos (26UL)                   /*!< MCUN0GPIO122 (Bit 26)                                 */
35330 #define GPIO_MCUN0INT3SET_MCUN0GPIO122_Msk (0x4000000UL)            /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
35331 #define GPIO_MCUN0INT3SET_MCUN0GPIO121_Pos (25UL)                   /*!< MCUN0GPIO121 (Bit 25)                                 */
35332 #define GPIO_MCUN0INT3SET_MCUN0GPIO121_Msk (0x2000000UL)            /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
35333 #define GPIO_MCUN0INT3SET_MCUN0GPIO120_Pos (24UL)                   /*!< MCUN0GPIO120 (Bit 24)                                 */
35334 #define GPIO_MCUN0INT3SET_MCUN0GPIO120_Msk (0x1000000UL)            /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
35335 #define GPIO_MCUN0INT3SET_MCUN0GPIO119_Pos (23UL)                   /*!< MCUN0GPIO119 (Bit 23)                                 */
35336 #define GPIO_MCUN0INT3SET_MCUN0GPIO119_Msk (0x800000UL)             /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
35337 #define GPIO_MCUN0INT3SET_MCUN0GPIO118_Pos (22UL)                   /*!< MCUN0GPIO118 (Bit 22)                                 */
35338 #define GPIO_MCUN0INT3SET_MCUN0GPIO118_Msk (0x400000UL)             /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
35339 #define GPIO_MCUN0INT3SET_MCUN0GPIO117_Pos (21UL)                   /*!< MCUN0GPIO117 (Bit 21)                                 */
35340 #define GPIO_MCUN0INT3SET_MCUN0GPIO117_Msk (0x200000UL)             /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
35341 #define GPIO_MCUN0INT3SET_MCUN0GPIO116_Pos (20UL)                   /*!< MCUN0GPIO116 (Bit 20)                                 */
35342 #define GPIO_MCUN0INT3SET_MCUN0GPIO116_Msk (0x100000UL)             /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
35343 #define GPIO_MCUN0INT3SET_MCUN0GPIO115_Pos (19UL)                   /*!< MCUN0GPIO115 (Bit 19)                                 */
35344 #define GPIO_MCUN0INT3SET_MCUN0GPIO115_Msk (0x80000UL)              /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
35345 #define GPIO_MCUN0INT3SET_MCUN0GPIO114_Pos (18UL)                   /*!< MCUN0GPIO114 (Bit 18)                                 */
35346 #define GPIO_MCUN0INT3SET_MCUN0GPIO114_Msk (0x40000UL)              /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
35347 #define GPIO_MCUN0INT3SET_MCUN0GPIO113_Pos (17UL)                   /*!< MCUN0GPIO113 (Bit 17)                                 */
35348 #define GPIO_MCUN0INT3SET_MCUN0GPIO113_Msk (0x20000UL)              /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
35349 #define GPIO_MCUN0INT3SET_MCUN0GPIO112_Pos (16UL)                   /*!< MCUN0GPIO112 (Bit 16)                                 */
35350 #define GPIO_MCUN0INT3SET_MCUN0GPIO112_Msk (0x10000UL)              /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
35351 #define GPIO_MCUN0INT3SET_MCUN0GPIO111_Pos (15UL)                   /*!< MCUN0GPIO111 (Bit 15)                                 */
35352 #define GPIO_MCUN0INT3SET_MCUN0GPIO111_Msk (0x8000UL)               /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
35353 #define GPIO_MCUN0INT3SET_MCUN0GPIO110_Pos (14UL)                   /*!< MCUN0GPIO110 (Bit 14)                                 */
35354 #define GPIO_MCUN0INT3SET_MCUN0GPIO110_Msk (0x4000UL)               /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
35355 #define GPIO_MCUN0INT3SET_MCUN0GPIO109_Pos (13UL)                   /*!< MCUN0GPIO109 (Bit 13)                                 */
35356 #define GPIO_MCUN0INT3SET_MCUN0GPIO109_Msk (0x2000UL)               /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
35357 #define GPIO_MCUN0INT3SET_MCUN0GPIO108_Pos (12UL)                   /*!< MCUN0GPIO108 (Bit 12)                                 */
35358 #define GPIO_MCUN0INT3SET_MCUN0GPIO108_Msk (0x1000UL)               /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
35359 #define GPIO_MCUN0INT3SET_MCUN0GPIO107_Pos (11UL)                   /*!< MCUN0GPIO107 (Bit 11)                                 */
35360 #define GPIO_MCUN0INT3SET_MCUN0GPIO107_Msk (0x800UL)                /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
35361 #define GPIO_MCUN0INT3SET_MCUN0GPIO106_Pos (10UL)                   /*!< MCUN0GPIO106 (Bit 10)                                 */
35362 #define GPIO_MCUN0INT3SET_MCUN0GPIO106_Msk (0x400UL)                /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
35363 #define GPIO_MCUN0INT3SET_MCUN0GPIO105_Pos (9UL)                    /*!< MCUN0GPIO105 (Bit 9)                                  */
35364 #define GPIO_MCUN0INT3SET_MCUN0GPIO105_Msk (0x200UL)                /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
35365 #define GPIO_MCUN0INT3SET_MCUN0GPIO104_Pos (8UL)                    /*!< MCUN0GPIO104 (Bit 8)                                  */
35366 #define GPIO_MCUN0INT3SET_MCUN0GPIO104_Msk (0x100UL)                /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
35367 #define GPIO_MCUN0INT3SET_MCUN0GPIO103_Pos (7UL)                    /*!< MCUN0GPIO103 (Bit 7)                                  */
35368 #define GPIO_MCUN0INT3SET_MCUN0GPIO103_Msk (0x80UL)                 /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
35369 #define GPIO_MCUN0INT3SET_MCUN0GPIO102_Pos (6UL)                    /*!< MCUN0GPIO102 (Bit 6)                                  */
35370 #define GPIO_MCUN0INT3SET_MCUN0GPIO102_Msk (0x40UL)                 /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
35371 #define GPIO_MCUN0INT3SET_MCUN0GPIO101_Pos (5UL)                    /*!< MCUN0GPIO101 (Bit 5)                                  */
35372 #define GPIO_MCUN0INT3SET_MCUN0GPIO101_Msk (0x20UL)                 /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
35373 #define GPIO_MCUN0INT3SET_MCUN0GPIO100_Pos (4UL)                    /*!< MCUN0GPIO100 (Bit 4)                                  */
35374 #define GPIO_MCUN0INT3SET_MCUN0GPIO100_Msk (0x10UL)                 /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
35375 #define GPIO_MCUN0INT3SET_MCUN0GPIO99_Pos (3UL)                     /*!< MCUN0GPIO99 (Bit 3)                                   */
35376 #define GPIO_MCUN0INT3SET_MCUN0GPIO99_Msk (0x8UL)                   /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
35377 #define GPIO_MCUN0INT3SET_MCUN0GPIO98_Pos (2UL)                     /*!< MCUN0GPIO98 (Bit 2)                                   */
35378 #define GPIO_MCUN0INT3SET_MCUN0GPIO98_Msk (0x4UL)                   /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
35379 #define GPIO_MCUN0INT3SET_MCUN0GPIO97_Pos (1UL)                     /*!< MCUN0GPIO97 (Bit 1)                                   */
35380 #define GPIO_MCUN0INT3SET_MCUN0GPIO97_Msk (0x2UL)                   /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
35381 #define GPIO_MCUN0INT3SET_MCUN0GPIO96_Pos (0UL)                     /*!< MCUN0GPIO96 (Bit 0)                                   */
35382 #define GPIO_MCUN0INT3SET_MCUN0GPIO96_Msk (0x1UL)                   /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
35383 /* ======================================================  MCUN1INT0EN  ====================================================== */
35384 #define GPIO_MCUN1INT0EN_MCUN1GPIO31_Pos  (31UL)                    /*!< MCUN1GPIO31 (Bit 31)                                  */
35385 #define GPIO_MCUN1INT0EN_MCUN1GPIO31_Msk  (0x80000000UL)            /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
35386 #define GPIO_MCUN1INT0EN_MCUN1GPIO30_Pos  (30UL)                    /*!< MCUN1GPIO30 (Bit 30)                                  */
35387 #define GPIO_MCUN1INT0EN_MCUN1GPIO30_Msk  (0x40000000UL)            /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
35388 #define GPIO_MCUN1INT0EN_MCUN1GPIO29_Pos  (29UL)                    /*!< MCUN1GPIO29 (Bit 29)                                  */
35389 #define GPIO_MCUN1INT0EN_MCUN1GPIO29_Msk  (0x20000000UL)            /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
35390 #define GPIO_MCUN1INT0EN_MCUN1GPIO28_Pos  (28UL)                    /*!< MCUN1GPIO28 (Bit 28)                                  */
35391 #define GPIO_MCUN1INT0EN_MCUN1GPIO28_Msk  (0x10000000UL)            /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
35392 #define GPIO_MCUN1INT0EN_MCUN1GPIO27_Pos  (27UL)                    /*!< MCUN1GPIO27 (Bit 27)                                  */
35393 #define GPIO_MCUN1INT0EN_MCUN1GPIO27_Msk  (0x8000000UL)             /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
35394 #define GPIO_MCUN1INT0EN_MCUN1GPIO26_Pos  (26UL)                    /*!< MCUN1GPIO26 (Bit 26)                                  */
35395 #define GPIO_MCUN1INT0EN_MCUN1GPIO26_Msk  (0x4000000UL)             /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
35396 #define GPIO_MCUN1INT0EN_MCUN1GPIO25_Pos  (25UL)                    /*!< MCUN1GPIO25 (Bit 25)                                  */
35397 #define GPIO_MCUN1INT0EN_MCUN1GPIO25_Msk  (0x2000000UL)             /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
35398 #define GPIO_MCUN1INT0EN_MCUN1GPIO24_Pos  (24UL)                    /*!< MCUN1GPIO24 (Bit 24)                                  */
35399 #define GPIO_MCUN1INT0EN_MCUN1GPIO24_Msk  (0x1000000UL)             /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
35400 #define GPIO_MCUN1INT0EN_MCUN1GPIO23_Pos  (23UL)                    /*!< MCUN1GPIO23 (Bit 23)                                  */
35401 #define GPIO_MCUN1INT0EN_MCUN1GPIO23_Msk  (0x800000UL)              /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
35402 #define GPIO_MCUN1INT0EN_MCUN1GPIO22_Pos  (22UL)                    /*!< MCUN1GPIO22 (Bit 22)                                  */
35403 #define GPIO_MCUN1INT0EN_MCUN1GPIO22_Msk  (0x400000UL)              /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
35404 #define GPIO_MCUN1INT0EN_MCUN1GPIO21_Pos  (21UL)                    /*!< MCUN1GPIO21 (Bit 21)                                  */
35405 #define GPIO_MCUN1INT0EN_MCUN1GPIO21_Msk  (0x200000UL)              /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
35406 #define GPIO_MCUN1INT0EN_MCUN1GPIO20_Pos  (20UL)                    /*!< MCUN1GPIO20 (Bit 20)                                  */
35407 #define GPIO_MCUN1INT0EN_MCUN1GPIO20_Msk  (0x100000UL)              /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
35408 #define GPIO_MCUN1INT0EN_MCUN1GPIO19_Pos  (19UL)                    /*!< MCUN1GPIO19 (Bit 19)                                  */
35409 #define GPIO_MCUN1INT0EN_MCUN1GPIO19_Msk  (0x80000UL)               /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
35410 #define GPIO_MCUN1INT0EN_MCUN1GPIO18_Pos  (18UL)                    /*!< MCUN1GPIO18 (Bit 18)                                  */
35411 #define GPIO_MCUN1INT0EN_MCUN1GPIO18_Msk  (0x40000UL)               /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
35412 #define GPIO_MCUN1INT0EN_MCUN1GPIO17_Pos  (17UL)                    /*!< MCUN1GPIO17 (Bit 17)                                  */
35413 #define GPIO_MCUN1INT0EN_MCUN1GPIO17_Msk  (0x20000UL)               /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
35414 #define GPIO_MCUN1INT0EN_MCUN1GPIO16_Pos  (16UL)                    /*!< MCUN1GPIO16 (Bit 16)                                  */
35415 #define GPIO_MCUN1INT0EN_MCUN1GPIO16_Msk  (0x10000UL)               /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
35416 #define GPIO_MCUN1INT0EN_MCUN1GPIO15_Pos  (15UL)                    /*!< MCUN1GPIO15 (Bit 15)                                  */
35417 #define GPIO_MCUN1INT0EN_MCUN1GPIO15_Msk  (0x8000UL)                /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
35418 #define GPIO_MCUN1INT0EN_MCUN1GPIO14_Pos  (14UL)                    /*!< MCUN1GPIO14 (Bit 14)                                  */
35419 #define GPIO_MCUN1INT0EN_MCUN1GPIO14_Msk  (0x4000UL)                /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
35420 #define GPIO_MCUN1INT0EN_MCUN1GPIO13_Pos  (13UL)                    /*!< MCUN1GPIO13 (Bit 13)                                  */
35421 #define GPIO_MCUN1INT0EN_MCUN1GPIO13_Msk  (0x2000UL)                /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
35422 #define GPIO_MCUN1INT0EN_MCUN1GPIO12_Pos  (12UL)                    /*!< MCUN1GPIO12 (Bit 12)                                  */
35423 #define GPIO_MCUN1INT0EN_MCUN1GPIO12_Msk  (0x1000UL)                /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
35424 #define GPIO_MCUN1INT0EN_MCUN1GPIO11_Pos  (11UL)                    /*!< MCUN1GPIO11 (Bit 11)                                  */
35425 #define GPIO_MCUN1INT0EN_MCUN1GPIO11_Msk  (0x800UL)                 /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
35426 #define GPIO_MCUN1INT0EN_MCUN1GPIO10_Pos  (10UL)                    /*!< MCUN1GPIO10 (Bit 10)                                  */
35427 #define GPIO_MCUN1INT0EN_MCUN1GPIO10_Msk  (0x400UL)                 /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
35428 #define GPIO_MCUN1INT0EN_MCUN1GPIO9_Pos   (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
35429 #define GPIO_MCUN1INT0EN_MCUN1GPIO9_Msk   (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
35430 #define GPIO_MCUN1INT0EN_MCUN1GPIO8_Pos   (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
35431 #define GPIO_MCUN1INT0EN_MCUN1GPIO8_Msk   (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
35432 #define GPIO_MCUN1INT0EN_MCUN1GPIO7_Pos   (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
35433 #define GPIO_MCUN1INT0EN_MCUN1GPIO7_Msk   (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
35434 #define GPIO_MCUN1INT0EN_MCUN1GPIO6_Pos   (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
35435 #define GPIO_MCUN1INT0EN_MCUN1GPIO6_Msk   (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
35436 #define GPIO_MCUN1INT0EN_MCUN1GPIO5_Pos   (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
35437 #define GPIO_MCUN1INT0EN_MCUN1GPIO5_Msk   (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
35438 #define GPIO_MCUN1INT0EN_MCUN1GPIO4_Pos   (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
35439 #define GPIO_MCUN1INT0EN_MCUN1GPIO4_Msk   (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
35440 #define GPIO_MCUN1INT0EN_MCUN1GPIO3_Pos   (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
35441 #define GPIO_MCUN1INT0EN_MCUN1GPIO3_Msk   (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
35442 #define GPIO_MCUN1INT0EN_MCUN1GPIO2_Pos   (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
35443 #define GPIO_MCUN1INT0EN_MCUN1GPIO2_Msk   (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
35444 #define GPIO_MCUN1INT0EN_MCUN1GPIO1_Pos   (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
35445 #define GPIO_MCUN1INT0EN_MCUN1GPIO1_Msk   (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
35446 #define GPIO_MCUN1INT0EN_MCUN1GPIO0_Pos   (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
35447 #define GPIO_MCUN1INT0EN_MCUN1GPIO0_Msk   (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
35448 /* =====================================================  MCUN1INT0STAT  ===================================================== */
35449 #define GPIO_MCUN1INT0STAT_MCUN1GPIO31_Pos (31UL)                   /*!< MCUN1GPIO31 (Bit 31)                                  */
35450 #define GPIO_MCUN1INT0STAT_MCUN1GPIO31_Msk (0x80000000UL)           /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
35451 #define GPIO_MCUN1INT0STAT_MCUN1GPIO30_Pos (30UL)                   /*!< MCUN1GPIO30 (Bit 30)                                  */
35452 #define GPIO_MCUN1INT0STAT_MCUN1GPIO30_Msk (0x40000000UL)           /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
35453 #define GPIO_MCUN1INT0STAT_MCUN1GPIO29_Pos (29UL)                   /*!< MCUN1GPIO29 (Bit 29)                                  */
35454 #define GPIO_MCUN1INT0STAT_MCUN1GPIO29_Msk (0x20000000UL)           /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
35455 #define GPIO_MCUN1INT0STAT_MCUN1GPIO28_Pos (28UL)                   /*!< MCUN1GPIO28 (Bit 28)                                  */
35456 #define GPIO_MCUN1INT0STAT_MCUN1GPIO28_Msk (0x10000000UL)           /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
35457 #define GPIO_MCUN1INT0STAT_MCUN1GPIO27_Pos (27UL)                   /*!< MCUN1GPIO27 (Bit 27)                                  */
35458 #define GPIO_MCUN1INT0STAT_MCUN1GPIO27_Msk (0x8000000UL)            /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
35459 #define GPIO_MCUN1INT0STAT_MCUN1GPIO26_Pos (26UL)                   /*!< MCUN1GPIO26 (Bit 26)                                  */
35460 #define GPIO_MCUN1INT0STAT_MCUN1GPIO26_Msk (0x4000000UL)            /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
35461 #define GPIO_MCUN1INT0STAT_MCUN1GPIO25_Pos (25UL)                   /*!< MCUN1GPIO25 (Bit 25)                                  */
35462 #define GPIO_MCUN1INT0STAT_MCUN1GPIO25_Msk (0x2000000UL)            /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
35463 #define GPIO_MCUN1INT0STAT_MCUN1GPIO24_Pos (24UL)                   /*!< MCUN1GPIO24 (Bit 24)                                  */
35464 #define GPIO_MCUN1INT0STAT_MCUN1GPIO24_Msk (0x1000000UL)            /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
35465 #define GPIO_MCUN1INT0STAT_MCUN1GPIO23_Pos (23UL)                   /*!< MCUN1GPIO23 (Bit 23)                                  */
35466 #define GPIO_MCUN1INT0STAT_MCUN1GPIO23_Msk (0x800000UL)             /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
35467 #define GPIO_MCUN1INT0STAT_MCUN1GPIO22_Pos (22UL)                   /*!< MCUN1GPIO22 (Bit 22)                                  */
35468 #define GPIO_MCUN1INT0STAT_MCUN1GPIO22_Msk (0x400000UL)             /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
35469 #define GPIO_MCUN1INT0STAT_MCUN1GPIO21_Pos (21UL)                   /*!< MCUN1GPIO21 (Bit 21)                                  */
35470 #define GPIO_MCUN1INT0STAT_MCUN1GPIO21_Msk (0x200000UL)             /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
35471 #define GPIO_MCUN1INT0STAT_MCUN1GPIO20_Pos (20UL)                   /*!< MCUN1GPIO20 (Bit 20)                                  */
35472 #define GPIO_MCUN1INT0STAT_MCUN1GPIO20_Msk (0x100000UL)             /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
35473 #define GPIO_MCUN1INT0STAT_MCUN1GPIO19_Pos (19UL)                   /*!< MCUN1GPIO19 (Bit 19)                                  */
35474 #define GPIO_MCUN1INT0STAT_MCUN1GPIO19_Msk (0x80000UL)              /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
35475 #define GPIO_MCUN1INT0STAT_MCUN1GPIO18_Pos (18UL)                   /*!< MCUN1GPIO18 (Bit 18)                                  */
35476 #define GPIO_MCUN1INT0STAT_MCUN1GPIO18_Msk (0x40000UL)              /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
35477 #define GPIO_MCUN1INT0STAT_MCUN1GPIO17_Pos (17UL)                   /*!< MCUN1GPIO17 (Bit 17)                                  */
35478 #define GPIO_MCUN1INT0STAT_MCUN1GPIO17_Msk (0x20000UL)              /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
35479 #define GPIO_MCUN1INT0STAT_MCUN1GPIO16_Pos (16UL)                   /*!< MCUN1GPIO16 (Bit 16)                                  */
35480 #define GPIO_MCUN1INT0STAT_MCUN1GPIO16_Msk (0x10000UL)              /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
35481 #define GPIO_MCUN1INT0STAT_MCUN1GPIO15_Pos (15UL)                   /*!< MCUN1GPIO15 (Bit 15)                                  */
35482 #define GPIO_MCUN1INT0STAT_MCUN1GPIO15_Msk (0x8000UL)               /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
35483 #define GPIO_MCUN1INT0STAT_MCUN1GPIO14_Pos (14UL)                   /*!< MCUN1GPIO14 (Bit 14)                                  */
35484 #define GPIO_MCUN1INT0STAT_MCUN1GPIO14_Msk (0x4000UL)               /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
35485 #define GPIO_MCUN1INT0STAT_MCUN1GPIO13_Pos (13UL)                   /*!< MCUN1GPIO13 (Bit 13)                                  */
35486 #define GPIO_MCUN1INT0STAT_MCUN1GPIO13_Msk (0x2000UL)               /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
35487 #define GPIO_MCUN1INT0STAT_MCUN1GPIO12_Pos (12UL)                   /*!< MCUN1GPIO12 (Bit 12)                                  */
35488 #define GPIO_MCUN1INT0STAT_MCUN1GPIO12_Msk (0x1000UL)               /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
35489 #define GPIO_MCUN1INT0STAT_MCUN1GPIO11_Pos (11UL)                   /*!< MCUN1GPIO11 (Bit 11)                                  */
35490 #define GPIO_MCUN1INT0STAT_MCUN1GPIO11_Msk (0x800UL)                /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
35491 #define GPIO_MCUN1INT0STAT_MCUN1GPIO10_Pos (10UL)                   /*!< MCUN1GPIO10 (Bit 10)                                  */
35492 #define GPIO_MCUN1INT0STAT_MCUN1GPIO10_Msk (0x400UL)                /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
35493 #define GPIO_MCUN1INT0STAT_MCUN1GPIO9_Pos (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
35494 #define GPIO_MCUN1INT0STAT_MCUN1GPIO9_Msk (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
35495 #define GPIO_MCUN1INT0STAT_MCUN1GPIO8_Pos (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
35496 #define GPIO_MCUN1INT0STAT_MCUN1GPIO8_Msk (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
35497 #define GPIO_MCUN1INT0STAT_MCUN1GPIO7_Pos (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
35498 #define GPIO_MCUN1INT0STAT_MCUN1GPIO7_Msk (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
35499 #define GPIO_MCUN1INT0STAT_MCUN1GPIO6_Pos (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
35500 #define GPIO_MCUN1INT0STAT_MCUN1GPIO6_Msk (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
35501 #define GPIO_MCUN1INT0STAT_MCUN1GPIO5_Pos (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
35502 #define GPIO_MCUN1INT0STAT_MCUN1GPIO5_Msk (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
35503 #define GPIO_MCUN1INT0STAT_MCUN1GPIO4_Pos (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
35504 #define GPIO_MCUN1INT0STAT_MCUN1GPIO4_Msk (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
35505 #define GPIO_MCUN1INT0STAT_MCUN1GPIO3_Pos (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
35506 #define GPIO_MCUN1INT0STAT_MCUN1GPIO3_Msk (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
35507 #define GPIO_MCUN1INT0STAT_MCUN1GPIO2_Pos (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
35508 #define GPIO_MCUN1INT0STAT_MCUN1GPIO2_Msk (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
35509 #define GPIO_MCUN1INT0STAT_MCUN1GPIO1_Pos (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
35510 #define GPIO_MCUN1INT0STAT_MCUN1GPIO1_Msk (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
35511 #define GPIO_MCUN1INT0STAT_MCUN1GPIO0_Pos (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
35512 #define GPIO_MCUN1INT0STAT_MCUN1GPIO0_Msk (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
35513 /* =====================================================  MCUN1INT0CLR  ====================================================== */
35514 #define GPIO_MCUN1INT0CLR_MCUN1GPIO31_Pos (31UL)                    /*!< MCUN1GPIO31 (Bit 31)                                  */
35515 #define GPIO_MCUN1INT0CLR_MCUN1GPIO31_Msk (0x80000000UL)            /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
35516 #define GPIO_MCUN1INT0CLR_MCUN1GPIO30_Pos (30UL)                    /*!< MCUN1GPIO30 (Bit 30)                                  */
35517 #define GPIO_MCUN1INT0CLR_MCUN1GPIO30_Msk (0x40000000UL)            /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
35518 #define GPIO_MCUN1INT0CLR_MCUN1GPIO29_Pos (29UL)                    /*!< MCUN1GPIO29 (Bit 29)                                  */
35519 #define GPIO_MCUN1INT0CLR_MCUN1GPIO29_Msk (0x20000000UL)            /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
35520 #define GPIO_MCUN1INT0CLR_MCUN1GPIO28_Pos (28UL)                    /*!< MCUN1GPIO28 (Bit 28)                                  */
35521 #define GPIO_MCUN1INT0CLR_MCUN1GPIO28_Msk (0x10000000UL)            /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
35522 #define GPIO_MCUN1INT0CLR_MCUN1GPIO27_Pos (27UL)                    /*!< MCUN1GPIO27 (Bit 27)                                  */
35523 #define GPIO_MCUN1INT0CLR_MCUN1GPIO27_Msk (0x8000000UL)             /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
35524 #define GPIO_MCUN1INT0CLR_MCUN1GPIO26_Pos (26UL)                    /*!< MCUN1GPIO26 (Bit 26)                                  */
35525 #define GPIO_MCUN1INT0CLR_MCUN1GPIO26_Msk (0x4000000UL)             /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
35526 #define GPIO_MCUN1INT0CLR_MCUN1GPIO25_Pos (25UL)                    /*!< MCUN1GPIO25 (Bit 25)                                  */
35527 #define GPIO_MCUN1INT0CLR_MCUN1GPIO25_Msk (0x2000000UL)             /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
35528 #define GPIO_MCUN1INT0CLR_MCUN1GPIO24_Pos (24UL)                    /*!< MCUN1GPIO24 (Bit 24)                                  */
35529 #define GPIO_MCUN1INT0CLR_MCUN1GPIO24_Msk (0x1000000UL)             /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
35530 #define GPIO_MCUN1INT0CLR_MCUN1GPIO23_Pos (23UL)                    /*!< MCUN1GPIO23 (Bit 23)                                  */
35531 #define GPIO_MCUN1INT0CLR_MCUN1GPIO23_Msk (0x800000UL)              /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
35532 #define GPIO_MCUN1INT0CLR_MCUN1GPIO22_Pos (22UL)                    /*!< MCUN1GPIO22 (Bit 22)                                  */
35533 #define GPIO_MCUN1INT0CLR_MCUN1GPIO22_Msk (0x400000UL)              /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
35534 #define GPIO_MCUN1INT0CLR_MCUN1GPIO21_Pos (21UL)                    /*!< MCUN1GPIO21 (Bit 21)                                  */
35535 #define GPIO_MCUN1INT0CLR_MCUN1GPIO21_Msk (0x200000UL)              /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
35536 #define GPIO_MCUN1INT0CLR_MCUN1GPIO20_Pos (20UL)                    /*!< MCUN1GPIO20 (Bit 20)                                  */
35537 #define GPIO_MCUN1INT0CLR_MCUN1GPIO20_Msk (0x100000UL)              /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
35538 #define GPIO_MCUN1INT0CLR_MCUN1GPIO19_Pos (19UL)                    /*!< MCUN1GPIO19 (Bit 19)                                  */
35539 #define GPIO_MCUN1INT0CLR_MCUN1GPIO19_Msk (0x80000UL)               /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
35540 #define GPIO_MCUN1INT0CLR_MCUN1GPIO18_Pos (18UL)                    /*!< MCUN1GPIO18 (Bit 18)                                  */
35541 #define GPIO_MCUN1INT0CLR_MCUN1GPIO18_Msk (0x40000UL)               /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
35542 #define GPIO_MCUN1INT0CLR_MCUN1GPIO17_Pos (17UL)                    /*!< MCUN1GPIO17 (Bit 17)                                  */
35543 #define GPIO_MCUN1INT0CLR_MCUN1GPIO17_Msk (0x20000UL)               /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
35544 #define GPIO_MCUN1INT0CLR_MCUN1GPIO16_Pos (16UL)                    /*!< MCUN1GPIO16 (Bit 16)                                  */
35545 #define GPIO_MCUN1INT0CLR_MCUN1GPIO16_Msk (0x10000UL)               /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
35546 #define GPIO_MCUN1INT0CLR_MCUN1GPIO15_Pos (15UL)                    /*!< MCUN1GPIO15 (Bit 15)                                  */
35547 #define GPIO_MCUN1INT0CLR_MCUN1GPIO15_Msk (0x8000UL)                /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
35548 #define GPIO_MCUN1INT0CLR_MCUN1GPIO14_Pos (14UL)                    /*!< MCUN1GPIO14 (Bit 14)                                  */
35549 #define GPIO_MCUN1INT0CLR_MCUN1GPIO14_Msk (0x4000UL)                /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
35550 #define GPIO_MCUN1INT0CLR_MCUN1GPIO13_Pos (13UL)                    /*!< MCUN1GPIO13 (Bit 13)                                  */
35551 #define GPIO_MCUN1INT0CLR_MCUN1GPIO13_Msk (0x2000UL)                /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
35552 #define GPIO_MCUN1INT0CLR_MCUN1GPIO12_Pos (12UL)                    /*!< MCUN1GPIO12 (Bit 12)                                  */
35553 #define GPIO_MCUN1INT0CLR_MCUN1GPIO12_Msk (0x1000UL)                /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
35554 #define GPIO_MCUN1INT0CLR_MCUN1GPIO11_Pos (11UL)                    /*!< MCUN1GPIO11 (Bit 11)                                  */
35555 #define GPIO_MCUN1INT0CLR_MCUN1GPIO11_Msk (0x800UL)                 /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
35556 #define GPIO_MCUN1INT0CLR_MCUN1GPIO10_Pos (10UL)                    /*!< MCUN1GPIO10 (Bit 10)                                  */
35557 #define GPIO_MCUN1INT0CLR_MCUN1GPIO10_Msk (0x400UL)                 /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
35558 #define GPIO_MCUN1INT0CLR_MCUN1GPIO9_Pos  (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
35559 #define GPIO_MCUN1INT0CLR_MCUN1GPIO9_Msk  (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
35560 #define GPIO_MCUN1INT0CLR_MCUN1GPIO8_Pos  (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
35561 #define GPIO_MCUN1INT0CLR_MCUN1GPIO8_Msk  (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
35562 #define GPIO_MCUN1INT0CLR_MCUN1GPIO7_Pos  (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
35563 #define GPIO_MCUN1INT0CLR_MCUN1GPIO7_Msk  (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
35564 #define GPIO_MCUN1INT0CLR_MCUN1GPIO6_Pos  (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
35565 #define GPIO_MCUN1INT0CLR_MCUN1GPIO6_Msk  (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
35566 #define GPIO_MCUN1INT0CLR_MCUN1GPIO5_Pos  (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
35567 #define GPIO_MCUN1INT0CLR_MCUN1GPIO5_Msk  (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
35568 #define GPIO_MCUN1INT0CLR_MCUN1GPIO4_Pos  (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
35569 #define GPIO_MCUN1INT0CLR_MCUN1GPIO4_Msk  (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
35570 #define GPIO_MCUN1INT0CLR_MCUN1GPIO3_Pos  (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
35571 #define GPIO_MCUN1INT0CLR_MCUN1GPIO3_Msk  (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
35572 #define GPIO_MCUN1INT0CLR_MCUN1GPIO2_Pos  (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
35573 #define GPIO_MCUN1INT0CLR_MCUN1GPIO2_Msk  (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
35574 #define GPIO_MCUN1INT0CLR_MCUN1GPIO1_Pos  (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
35575 #define GPIO_MCUN1INT0CLR_MCUN1GPIO1_Msk  (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
35576 #define GPIO_MCUN1INT0CLR_MCUN1GPIO0_Pos  (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
35577 #define GPIO_MCUN1INT0CLR_MCUN1GPIO0_Msk  (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
35578 /* =====================================================  MCUN1INT0SET  ====================================================== */
35579 #define GPIO_MCUN1INT0SET_MCUN1GPIO31_Pos (31UL)                    /*!< MCUN1GPIO31 (Bit 31)                                  */
35580 #define GPIO_MCUN1INT0SET_MCUN1GPIO31_Msk (0x80000000UL)            /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
35581 #define GPIO_MCUN1INT0SET_MCUN1GPIO30_Pos (30UL)                    /*!< MCUN1GPIO30 (Bit 30)                                  */
35582 #define GPIO_MCUN1INT0SET_MCUN1GPIO30_Msk (0x40000000UL)            /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
35583 #define GPIO_MCUN1INT0SET_MCUN1GPIO29_Pos (29UL)                    /*!< MCUN1GPIO29 (Bit 29)                                  */
35584 #define GPIO_MCUN1INT0SET_MCUN1GPIO29_Msk (0x20000000UL)            /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
35585 #define GPIO_MCUN1INT0SET_MCUN1GPIO28_Pos (28UL)                    /*!< MCUN1GPIO28 (Bit 28)                                  */
35586 #define GPIO_MCUN1INT0SET_MCUN1GPIO28_Msk (0x10000000UL)            /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
35587 #define GPIO_MCUN1INT0SET_MCUN1GPIO27_Pos (27UL)                    /*!< MCUN1GPIO27 (Bit 27)                                  */
35588 #define GPIO_MCUN1INT0SET_MCUN1GPIO27_Msk (0x8000000UL)             /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
35589 #define GPIO_MCUN1INT0SET_MCUN1GPIO26_Pos (26UL)                    /*!< MCUN1GPIO26 (Bit 26)                                  */
35590 #define GPIO_MCUN1INT0SET_MCUN1GPIO26_Msk (0x4000000UL)             /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
35591 #define GPIO_MCUN1INT0SET_MCUN1GPIO25_Pos (25UL)                    /*!< MCUN1GPIO25 (Bit 25)                                  */
35592 #define GPIO_MCUN1INT0SET_MCUN1GPIO25_Msk (0x2000000UL)             /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
35593 #define GPIO_MCUN1INT0SET_MCUN1GPIO24_Pos (24UL)                    /*!< MCUN1GPIO24 (Bit 24)                                  */
35594 #define GPIO_MCUN1INT0SET_MCUN1GPIO24_Msk (0x1000000UL)             /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
35595 #define GPIO_MCUN1INT0SET_MCUN1GPIO23_Pos (23UL)                    /*!< MCUN1GPIO23 (Bit 23)                                  */
35596 #define GPIO_MCUN1INT0SET_MCUN1GPIO23_Msk (0x800000UL)              /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
35597 #define GPIO_MCUN1INT0SET_MCUN1GPIO22_Pos (22UL)                    /*!< MCUN1GPIO22 (Bit 22)                                  */
35598 #define GPIO_MCUN1INT0SET_MCUN1GPIO22_Msk (0x400000UL)              /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
35599 #define GPIO_MCUN1INT0SET_MCUN1GPIO21_Pos (21UL)                    /*!< MCUN1GPIO21 (Bit 21)                                  */
35600 #define GPIO_MCUN1INT0SET_MCUN1GPIO21_Msk (0x200000UL)              /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
35601 #define GPIO_MCUN1INT0SET_MCUN1GPIO20_Pos (20UL)                    /*!< MCUN1GPIO20 (Bit 20)                                  */
35602 #define GPIO_MCUN1INT0SET_MCUN1GPIO20_Msk (0x100000UL)              /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
35603 #define GPIO_MCUN1INT0SET_MCUN1GPIO19_Pos (19UL)                    /*!< MCUN1GPIO19 (Bit 19)                                  */
35604 #define GPIO_MCUN1INT0SET_MCUN1GPIO19_Msk (0x80000UL)               /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
35605 #define GPIO_MCUN1INT0SET_MCUN1GPIO18_Pos (18UL)                    /*!< MCUN1GPIO18 (Bit 18)                                  */
35606 #define GPIO_MCUN1INT0SET_MCUN1GPIO18_Msk (0x40000UL)               /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
35607 #define GPIO_MCUN1INT0SET_MCUN1GPIO17_Pos (17UL)                    /*!< MCUN1GPIO17 (Bit 17)                                  */
35608 #define GPIO_MCUN1INT0SET_MCUN1GPIO17_Msk (0x20000UL)               /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
35609 #define GPIO_MCUN1INT0SET_MCUN1GPIO16_Pos (16UL)                    /*!< MCUN1GPIO16 (Bit 16)                                  */
35610 #define GPIO_MCUN1INT0SET_MCUN1GPIO16_Msk (0x10000UL)               /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
35611 #define GPIO_MCUN1INT0SET_MCUN1GPIO15_Pos (15UL)                    /*!< MCUN1GPIO15 (Bit 15)                                  */
35612 #define GPIO_MCUN1INT0SET_MCUN1GPIO15_Msk (0x8000UL)                /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
35613 #define GPIO_MCUN1INT0SET_MCUN1GPIO14_Pos (14UL)                    /*!< MCUN1GPIO14 (Bit 14)                                  */
35614 #define GPIO_MCUN1INT0SET_MCUN1GPIO14_Msk (0x4000UL)                /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
35615 #define GPIO_MCUN1INT0SET_MCUN1GPIO13_Pos (13UL)                    /*!< MCUN1GPIO13 (Bit 13)                                  */
35616 #define GPIO_MCUN1INT0SET_MCUN1GPIO13_Msk (0x2000UL)                /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
35617 #define GPIO_MCUN1INT0SET_MCUN1GPIO12_Pos (12UL)                    /*!< MCUN1GPIO12 (Bit 12)                                  */
35618 #define GPIO_MCUN1INT0SET_MCUN1GPIO12_Msk (0x1000UL)                /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
35619 #define GPIO_MCUN1INT0SET_MCUN1GPIO11_Pos (11UL)                    /*!< MCUN1GPIO11 (Bit 11)                                  */
35620 #define GPIO_MCUN1INT0SET_MCUN1GPIO11_Msk (0x800UL)                 /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
35621 #define GPIO_MCUN1INT0SET_MCUN1GPIO10_Pos (10UL)                    /*!< MCUN1GPIO10 (Bit 10)                                  */
35622 #define GPIO_MCUN1INT0SET_MCUN1GPIO10_Msk (0x400UL)                 /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
35623 #define GPIO_MCUN1INT0SET_MCUN1GPIO9_Pos  (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
35624 #define GPIO_MCUN1INT0SET_MCUN1GPIO9_Msk  (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
35625 #define GPIO_MCUN1INT0SET_MCUN1GPIO8_Pos  (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
35626 #define GPIO_MCUN1INT0SET_MCUN1GPIO8_Msk  (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
35627 #define GPIO_MCUN1INT0SET_MCUN1GPIO7_Pos  (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
35628 #define GPIO_MCUN1INT0SET_MCUN1GPIO7_Msk  (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
35629 #define GPIO_MCUN1INT0SET_MCUN1GPIO6_Pos  (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
35630 #define GPIO_MCUN1INT0SET_MCUN1GPIO6_Msk  (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
35631 #define GPIO_MCUN1INT0SET_MCUN1GPIO5_Pos  (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
35632 #define GPIO_MCUN1INT0SET_MCUN1GPIO5_Msk  (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
35633 #define GPIO_MCUN1INT0SET_MCUN1GPIO4_Pos  (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
35634 #define GPIO_MCUN1INT0SET_MCUN1GPIO4_Msk  (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
35635 #define GPIO_MCUN1INT0SET_MCUN1GPIO3_Pos  (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
35636 #define GPIO_MCUN1INT0SET_MCUN1GPIO3_Msk  (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
35637 #define GPIO_MCUN1INT0SET_MCUN1GPIO2_Pos  (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
35638 #define GPIO_MCUN1INT0SET_MCUN1GPIO2_Msk  (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
35639 #define GPIO_MCUN1INT0SET_MCUN1GPIO1_Pos  (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
35640 #define GPIO_MCUN1INT0SET_MCUN1GPIO1_Msk  (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
35641 #define GPIO_MCUN1INT0SET_MCUN1GPIO0_Pos  (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
35642 #define GPIO_MCUN1INT0SET_MCUN1GPIO0_Msk  (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
35643 /* ======================================================  MCUN1INT1EN  ====================================================== */
35644 #define GPIO_MCUN1INT1EN_MCUN1GPIO63_Pos  (31UL)                    /*!< MCUN1GPIO63 (Bit 31)                                  */
35645 #define GPIO_MCUN1INT1EN_MCUN1GPIO63_Msk  (0x80000000UL)            /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
35646 #define GPIO_MCUN1INT1EN_MCUN1GPIO62_Pos  (30UL)                    /*!< MCUN1GPIO62 (Bit 30)                                  */
35647 #define GPIO_MCUN1INT1EN_MCUN1GPIO62_Msk  (0x40000000UL)            /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
35648 #define GPIO_MCUN1INT1EN_MCUN1GPIO61_Pos  (29UL)                    /*!< MCUN1GPIO61 (Bit 29)                                  */
35649 #define GPIO_MCUN1INT1EN_MCUN1GPIO61_Msk  (0x20000000UL)            /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
35650 #define GPIO_MCUN1INT1EN_MCUN1GPIO60_Pos  (28UL)                    /*!< MCUN1GPIO60 (Bit 28)                                  */
35651 #define GPIO_MCUN1INT1EN_MCUN1GPIO60_Msk  (0x10000000UL)            /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
35652 #define GPIO_MCUN1INT1EN_MCUN1GPIO59_Pos  (27UL)                    /*!< MCUN1GPIO59 (Bit 27)                                  */
35653 #define GPIO_MCUN1INT1EN_MCUN1GPIO59_Msk  (0x8000000UL)             /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
35654 #define GPIO_MCUN1INT1EN_MCUN1GPIO58_Pos  (26UL)                    /*!< MCUN1GPIO58 (Bit 26)                                  */
35655 #define GPIO_MCUN1INT1EN_MCUN1GPIO58_Msk  (0x4000000UL)             /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
35656 #define GPIO_MCUN1INT1EN_MCUN1GPIO57_Pos  (25UL)                    /*!< MCUN1GPIO57 (Bit 25)                                  */
35657 #define GPIO_MCUN1INT1EN_MCUN1GPIO57_Msk  (0x2000000UL)             /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
35658 #define GPIO_MCUN1INT1EN_MCUN1GPIO56_Pos  (24UL)                    /*!< MCUN1GPIO56 (Bit 24)                                  */
35659 #define GPIO_MCUN1INT1EN_MCUN1GPIO56_Msk  (0x1000000UL)             /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
35660 #define GPIO_MCUN1INT1EN_MCUN1GPIO55_Pos  (23UL)                    /*!< MCUN1GPIO55 (Bit 23)                                  */
35661 #define GPIO_MCUN1INT1EN_MCUN1GPIO55_Msk  (0x800000UL)              /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
35662 #define GPIO_MCUN1INT1EN_MCUN1GPIO54_Pos  (22UL)                    /*!< MCUN1GPIO54 (Bit 22)                                  */
35663 #define GPIO_MCUN1INT1EN_MCUN1GPIO54_Msk  (0x400000UL)              /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
35664 #define GPIO_MCUN1INT1EN_MCUN1GPIO53_Pos  (21UL)                    /*!< MCUN1GPIO53 (Bit 21)                                  */
35665 #define GPIO_MCUN1INT1EN_MCUN1GPIO53_Msk  (0x200000UL)              /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
35666 #define GPIO_MCUN1INT1EN_MCUN1GPIO52_Pos  (20UL)                    /*!< MCUN1GPIO52 (Bit 20)                                  */
35667 #define GPIO_MCUN1INT1EN_MCUN1GPIO52_Msk  (0x100000UL)              /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
35668 #define GPIO_MCUN1INT1EN_MCUN1GPIO51_Pos  (19UL)                    /*!< MCUN1GPIO51 (Bit 19)                                  */
35669 #define GPIO_MCUN1INT1EN_MCUN1GPIO51_Msk  (0x80000UL)               /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
35670 #define GPIO_MCUN1INT1EN_MCUN1GPIO50_Pos  (18UL)                    /*!< MCUN1GPIO50 (Bit 18)                                  */
35671 #define GPIO_MCUN1INT1EN_MCUN1GPIO50_Msk  (0x40000UL)               /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
35672 #define GPIO_MCUN1INT1EN_MCUN1GPIO49_Pos  (17UL)                    /*!< MCUN1GPIO49 (Bit 17)                                  */
35673 #define GPIO_MCUN1INT1EN_MCUN1GPIO49_Msk  (0x20000UL)               /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
35674 #define GPIO_MCUN1INT1EN_MCUN1GPIO48_Pos  (16UL)                    /*!< MCUN1GPIO48 (Bit 16)                                  */
35675 #define GPIO_MCUN1INT1EN_MCUN1GPIO48_Msk  (0x10000UL)               /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
35676 #define GPIO_MCUN1INT1EN_MCUN1GPIO47_Pos  (15UL)                    /*!< MCUN1GPIO47 (Bit 15)                                  */
35677 #define GPIO_MCUN1INT1EN_MCUN1GPIO47_Msk  (0x8000UL)                /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
35678 #define GPIO_MCUN1INT1EN_MCUN1GPIO46_Pos  (14UL)                    /*!< MCUN1GPIO46 (Bit 14)                                  */
35679 #define GPIO_MCUN1INT1EN_MCUN1GPIO46_Msk  (0x4000UL)                /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
35680 #define GPIO_MCUN1INT1EN_MCUN1GPIO45_Pos  (13UL)                    /*!< MCUN1GPIO45 (Bit 13)                                  */
35681 #define GPIO_MCUN1INT1EN_MCUN1GPIO45_Msk  (0x2000UL)                /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
35682 #define GPIO_MCUN1INT1EN_MCUN1GPIO44_Pos  (12UL)                    /*!< MCUN1GPIO44 (Bit 12)                                  */
35683 #define GPIO_MCUN1INT1EN_MCUN1GPIO44_Msk  (0x1000UL)                /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
35684 #define GPIO_MCUN1INT1EN_MCUN1GPIO43_Pos  (11UL)                    /*!< MCUN1GPIO43 (Bit 11)                                  */
35685 #define GPIO_MCUN1INT1EN_MCUN1GPIO43_Msk  (0x800UL)                 /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
35686 #define GPIO_MCUN1INT1EN_MCUN1GPIO42_Pos  (10UL)                    /*!< MCUN1GPIO42 (Bit 10)                                  */
35687 #define GPIO_MCUN1INT1EN_MCUN1GPIO42_Msk  (0x400UL)                 /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
35688 #define GPIO_MCUN1INT1EN_MCUN1GPIO41_Pos  (9UL)                     /*!< MCUN1GPIO41 (Bit 9)                                   */
35689 #define GPIO_MCUN1INT1EN_MCUN1GPIO41_Msk  (0x200UL)                 /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
35690 #define GPIO_MCUN1INT1EN_MCUN1GPIO40_Pos  (8UL)                     /*!< MCUN1GPIO40 (Bit 8)                                   */
35691 #define GPIO_MCUN1INT1EN_MCUN1GPIO40_Msk  (0x100UL)                 /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
35692 #define GPIO_MCUN1INT1EN_MCUN1GPIO39_Pos  (7UL)                     /*!< MCUN1GPIO39 (Bit 7)                                   */
35693 #define GPIO_MCUN1INT1EN_MCUN1GPIO39_Msk  (0x80UL)                  /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
35694 #define GPIO_MCUN1INT1EN_MCUN1GPIO38_Pos  (6UL)                     /*!< MCUN1GPIO38 (Bit 6)                                   */
35695 #define GPIO_MCUN1INT1EN_MCUN1GPIO38_Msk  (0x40UL)                  /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
35696 #define GPIO_MCUN1INT1EN_MCUN1GPIO37_Pos  (5UL)                     /*!< MCUN1GPIO37 (Bit 5)                                   */
35697 #define GPIO_MCUN1INT1EN_MCUN1GPIO37_Msk  (0x20UL)                  /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
35698 #define GPIO_MCUN1INT1EN_MCUN1GPIO36_Pos  (4UL)                     /*!< MCUN1GPIO36 (Bit 4)                                   */
35699 #define GPIO_MCUN1INT1EN_MCUN1GPIO36_Msk  (0x10UL)                  /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
35700 #define GPIO_MCUN1INT1EN_MCUN1GPIO35_Pos  (3UL)                     /*!< MCUN1GPIO35 (Bit 3)                                   */
35701 #define GPIO_MCUN1INT1EN_MCUN1GPIO35_Msk  (0x8UL)                   /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
35702 #define GPIO_MCUN1INT1EN_MCUN1GPIO34_Pos  (2UL)                     /*!< MCUN1GPIO34 (Bit 2)                                   */
35703 #define GPIO_MCUN1INT1EN_MCUN1GPIO34_Msk  (0x4UL)                   /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
35704 #define GPIO_MCUN1INT1EN_MCUN1GPIO33_Pos  (1UL)                     /*!< MCUN1GPIO33 (Bit 1)                                   */
35705 #define GPIO_MCUN1INT1EN_MCUN1GPIO33_Msk  (0x2UL)                   /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
35706 #define GPIO_MCUN1INT1EN_MCUN1GPIO32_Pos  (0UL)                     /*!< MCUN1GPIO32 (Bit 0)                                   */
35707 #define GPIO_MCUN1INT1EN_MCUN1GPIO32_Msk  (0x1UL)                   /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
35708 /* =====================================================  MCUN1INT1STAT  ===================================================== */
35709 #define GPIO_MCUN1INT1STAT_MCUN1GPIO63_Pos (31UL)                   /*!< MCUN1GPIO63 (Bit 31)                                  */
35710 #define GPIO_MCUN1INT1STAT_MCUN1GPIO63_Msk (0x80000000UL)           /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
35711 #define GPIO_MCUN1INT1STAT_MCUN1GPIO62_Pos (30UL)                   /*!< MCUN1GPIO62 (Bit 30)                                  */
35712 #define GPIO_MCUN1INT1STAT_MCUN1GPIO62_Msk (0x40000000UL)           /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
35713 #define GPIO_MCUN1INT1STAT_MCUN1GPIO61_Pos (29UL)                   /*!< MCUN1GPIO61 (Bit 29)                                  */
35714 #define GPIO_MCUN1INT1STAT_MCUN1GPIO61_Msk (0x20000000UL)           /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
35715 #define GPIO_MCUN1INT1STAT_MCUN1GPIO60_Pos (28UL)                   /*!< MCUN1GPIO60 (Bit 28)                                  */
35716 #define GPIO_MCUN1INT1STAT_MCUN1GPIO60_Msk (0x10000000UL)           /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
35717 #define GPIO_MCUN1INT1STAT_MCUN1GPIO59_Pos (27UL)                   /*!< MCUN1GPIO59 (Bit 27)                                  */
35718 #define GPIO_MCUN1INT1STAT_MCUN1GPIO59_Msk (0x8000000UL)            /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
35719 #define GPIO_MCUN1INT1STAT_MCUN1GPIO58_Pos (26UL)                   /*!< MCUN1GPIO58 (Bit 26)                                  */
35720 #define GPIO_MCUN1INT1STAT_MCUN1GPIO58_Msk (0x4000000UL)            /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
35721 #define GPIO_MCUN1INT1STAT_MCUN1GPIO57_Pos (25UL)                   /*!< MCUN1GPIO57 (Bit 25)                                  */
35722 #define GPIO_MCUN1INT1STAT_MCUN1GPIO57_Msk (0x2000000UL)            /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
35723 #define GPIO_MCUN1INT1STAT_MCUN1GPIO56_Pos (24UL)                   /*!< MCUN1GPIO56 (Bit 24)                                  */
35724 #define GPIO_MCUN1INT1STAT_MCUN1GPIO56_Msk (0x1000000UL)            /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
35725 #define GPIO_MCUN1INT1STAT_MCUN1GPIO55_Pos (23UL)                   /*!< MCUN1GPIO55 (Bit 23)                                  */
35726 #define GPIO_MCUN1INT1STAT_MCUN1GPIO55_Msk (0x800000UL)             /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
35727 #define GPIO_MCUN1INT1STAT_MCUN1GPIO54_Pos (22UL)                   /*!< MCUN1GPIO54 (Bit 22)                                  */
35728 #define GPIO_MCUN1INT1STAT_MCUN1GPIO54_Msk (0x400000UL)             /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
35729 #define GPIO_MCUN1INT1STAT_MCUN1GPIO53_Pos (21UL)                   /*!< MCUN1GPIO53 (Bit 21)                                  */
35730 #define GPIO_MCUN1INT1STAT_MCUN1GPIO53_Msk (0x200000UL)             /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
35731 #define GPIO_MCUN1INT1STAT_MCUN1GPIO52_Pos (20UL)                   /*!< MCUN1GPIO52 (Bit 20)                                  */
35732 #define GPIO_MCUN1INT1STAT_MCUN1GPIO52_Msk (0x100000UL)             /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
35733 #define GPIO_MCUN1INT1STAT_MCUN1GPIO51_Pos (19UL)                   /*!< MCUN1GPIO51 (Bit 19)                                  */
35734 #define GPIO_MCUN1INT1STAT_MCUN1GPIO51_Msk (0x80000UL)              /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
35735 #define GPIO_MCUN1INT1STAT_MCUN1GPIO50_Pos (18UL)                   /*!< MCUN1GPIO50 (Bit 18)                                  */
35736 #define GPIO_MCUN1INT1STAT_MCUN1GPIO50_Msk (0x40000UL)              /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
35737 #define GPIO_MCUN1INT1STAT_MCUN1GPIO49_Pos (17UL)                   /*!< MCUN1GPIO49 (Bit 17)                                  */
35738 #define GPIO_MCUN1INT1STAT_MCUN1GPIO49_Msk (0x20000UL)              /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
35739 #define GPIO_MCUN1INT1STAT_MCUN1GPIO48_Pos (16UL)                   /*!< MCUN1GPIO48 (Bit 16)                                  */
35740 #define GPIO_MCUN1INT1STAT_MCUN1GPIO48_Msk (0x10000UL)              /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
35741 #define GPIO_MCUN1INT1STAT_MCUN1GPIO47_Pos (15UL)                   /*!< MCUN1GPIO47 (Bit 15)                                  */
35742 #define GPIO_MCUN1INT1STAT_MCUN1GPIO47_Msk (0x8000UL)               /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
35743 #define GPIO_MCUN1INT1STAT_MCUN1GPIO46_Pos (14UL)                   /*!< MCUN1GPIO46 (Bit 14)                                  */
35744 #define GPIO_MCUN1INT1STAT_MCUN1GPIO46_Msk (0x4000UL)               /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
35745 #define GPIO_MCUN1INT1STAT_MCUN1GPIO45_Pos (13UL)                   /*!< MCUN1GPIO45 (Bit 13)                                  */
35746 #define GPIO_MCUN1INT1STAT_MCUN1GPIO45_Msk (0x2000UL)               /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
35747 #define GPIO_MCUN1INT1STAT_MCUN1GPIO44_Pos (12UL)                   /*!< MCUN1GPIO44 (Bit 12)                                  */
35748 #define GPIO_MCUN1INT1STAT_MCUN1GPIO44_Msk (0x1000UL)               /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
35749 #define GPIO_MCUN1INT1STAT_MCUN1GPIO43_Pos (11UL)                   /*!< MCUN1GPIO43 (Bit 11)                                  */
35750 #define GPIO_MCUN1INT1STAT_MCUN1GPIO43_Msk (0x800UL)                /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
35751 #define GPIO_MCUN1INT1STAT_MCUN1GPIO42_Pos (10UL)                   /*!< MCUN1GPIO42 (Bit 10)                                  */
35752 #define GPIO_MCUN1INT1STAT_MCUN1GPIO42_Msk (0x400UL)                /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
35753 #define GPIO_MCUN1INT1STAT_MCUN1GPIO41_Pos (9UL)                    /*!< MCUN1GPIO41 (Bit 9)                                   */
35754 #define GPIO_MCUN1INT1STAT_MCUN1GPIO41_Msk (0x200UL)                /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
35755 #define GPIO_MCUN1INT1STAT_MCUN1GPIO40_Pos (8UL)                    /*!< MCUN1GPIO40 (Bit 8)                                   */
35756 #define GPIO_MCUN1INT1STAT_MCUN1GPIO40_Msk (0x100UL)                /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
35757 #define GPIO_MCUN1INT1STAT_MCUN1GPIO39_Pos (7UL)                    /*!< MCUN1GPIO39 (Bit 7)                                   */
35758 #define GPIO_MCUN1INT1STAT_MCUN1GPIO39_Msk (0x80UL)                 /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
35759 #define GPIO_MCUN1INT1STAT_MCUN1GPIO38_Pos (6UL)                    /*!< MCUN1GPIO38 (Bit 6)                                   */
35760 #define GPIO_MCUN1INT1STAT_MCUN1GPIO38_Msk (0x40UL)                 /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
35761 #define GPIO_MCUN1INT1STAT_MCUN1GPIO37_Pos (5UL)                    /*!< MCUN1GPIO37 (Bit 5)                                   */
35762 #define GPIO_MCUN1INT1STAT_MCUN1GPIO37_Msk (0x20UL)                 /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
35763 #define GPIO_MCUN1INT1STAT_MCUN1GPIO36_Pos (4UL)                    /*!< MCUN1GPIO36 (Bit 4)                                   */
35764 #define GPIO_MCUN1INT1STAT_MCUN1GPIO36_Msk (0x10UL)                 /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
35765 #define GPIO_MCUN1INT1STAT_MCUN1GPIO35_Pos (3UL)                    /*!< MCUN1GPIO35 (Bit 3)                                   */
35766 #define GPIO_MCUN1INT1STAT_MCUN1GPIO35_Msk (0x8UL)                  /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
35767 #define GPIO_MCUN1INT1STAT_MCUN1GPIO34_Pos (2UL)                    /*!< MCUN1GPIO34 (Bit 2)                                   */
35768 #define GPIO_MCUN1INT1STAT_MCUN1GPIO34_Msk (0x4UL)                  /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
35769 #define GPIO_MCUN1INT1STAT_MCUN1GPIO33_Pos (1UL)                    /*!< MCUN1GPIO33 (Bit 1)                                   */
35770 #define GPIO_MCUN1INT1STAT_MCUN1GPIO33_Msk (0x2UL)                  /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
35771 #define GPIO_MCUN1INT1STAT_MCUN1GPIO32_Pos (0UL)                    /*!< MCUN1GPIO32 (Bit 0)                                   */
35772 #define GPIO_MCUN1INT1STAT_MCUN1GPIO32_Msk (0x1UL)                  /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
35773 /* =====================================================  MCUN1INT1CLR  ====================================================== */
35774 #define GPIO_MCUN1INT1CLR_MCUN1GPIO63_Pos (31UL)                    /*!< MCUN1GPIO63 (Bit 31)                                  */
35775 #define GPIO_MCUN1INT1CLR_MCUN1GPIO63_Msk (0x80000000UL)            /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
35776 #define GPIO_MCUN1INT1CLR_MCUN1GPIO62_Pos (30UL)                    /*!< MCUN1GPIO62 (Bit 30)                                  */
35777 #define GPIO_MCUN1INT1CLR_MCUN1GPIO62_Msk (0x40000000UL)            /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
35778 #define GPIO_MCUN1INT1CLR_MCUN1GPIO61_Pos (29UL)                    /*!< MCUN1GPIO61 (Bit 29)                                  */
35779 #define GPIO_MCUN1INT1CLR_MCUN1GPIO61_Msk (0x20000000UL)            /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
35780 #define GPIO_MCUN1INT1CLR_MCUN1GPIO60_Pos (28UL)                    /*!< MCUN1GPIO60 (Bit 28)                                  */
35781 #define GPIO_MCUN1INT1CLR_MCUN1GPIO60_Msk (0x10000000UL)            /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
35782 #define GPIO_MCUN1INT1CLR_MCUN1GPIO59_Pos (27UL)                    /*!< MCUN1GPIO59 (Bit 27)                                  */
35783 #define GPIO_MCUN1INT1CLR_MCUN1GPIO59_Msk (0x8000000UL)             /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
35784 #define GPIO_MCUN1INT1CLR_MCUN1GPIO58_Pos (26UL)                    /*!< MCUN1GPIO58 (Bit 26)                                  */
35785 #define GPIO_MCUN1INT1CLR_MCUN1GPIO58_Msk (0x4000000UL)             /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
35786 #define GPIO_MCUN1INT1CLR_MCUN1GPIO57_Pos (25UL)                    /*!< MCUN1GPIO57 (Bit 25)                                  */
35787 #define GPIO_MCUN1INT1CLR_MCUN1GPIO57_Msk (0x2000000UL)             /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
35788 #define GPIO_MCUN1INT1CLR_MCUN1GPIO56_Pos (24UL)                    /*!< MCUN1GPIO56 (Bit 24)                                  */
35789 #define GPIO_MCUN1INT1CLR_MCUN1GPIO56_Msk (0x1000000UL)             /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
35790 #define GPIO_MCUN1INT1CLR_MCUN1GPIO55_Pos (23UL)                    /*!< MCUN1GPIO55 (Bit 23)                                  */
35791 #define GPIO_MCUN1INT1CLR_MCUN1GPIO55_Msk (0x800000UL)              /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
35792 #define GPIO_MCUN1INT1CLR_MCUN1GPIO54_Pos (22UL)                    /*!< MCUN1GPIO54 (Bit 22)                                  */
35793 #define GPIO_MCUN1INT1CLR_MCUN1GPIO54_Msk (0x400000UL)              /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
35794 #define GPIO_MCUN1INT1CLR_MCUN1GPIO53_Pos (21UL)                    /*!< MCUN1GPIO53 (Bit 21)                                  */
35795 #define GPIO_MCUN1INT1CLR_MCUN1GPIO53_Msk (0x200000UL)              /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
35796 #define GPIO_MCUN1INT1CLR_MCUN1GPIO52_Pos (20UL)                    /*!< MCUN1GPIO52 (Bit 20)                                  */
35797 #define GPIO_MCUN1INT1CLR_MCUN1GPIO52_Msk (0x100000UL)              /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
35798 #define GPIO_MCUN1INT1CLR_MCUN1GPIO51_Pos (19UL)                    /*!< MCUN1GPIO51 (Bit 19)                                  */
35799 #define GPIO_MCUN1INT1CLR_MCUN1GPIO51_Msk (0x80000UL)               /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
35800 #define GPIO_MCUN1INT1CLR_MCUN1GPIO50_Pos (18UL)                    /*!< MCUN1GPIO50 (Bit 18)                                  */
35801 #define GPIO_MCUN1INT1CLR_MCUN1GPIO50_Msk (0x40000UL)               /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
35802 #define GPIO_MCUN1INT1CLR_MCUN1GPIO49_Pos (17UL)                    /*!< MCUN1GPIO49 (Bit 17)                                  */
35803 #define GPIO_MCUN1INT1CLR_MCUN1GPIO49_Msk (0x20000UL)               /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
35804 #define GPIO_MCUN1INT1CLR_MCUN1GPIO48_Pos (16UL)                    /*!< MCUN1GPIO48 (Bit 16)                                  */
35805 #define GPIO_MCUN1INT1CLR_MCUN1GPIO48_Msk (0x10000UL)               /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
35806 #define GPIO_MCUN1INT1CLR_MCUN1GPIO47_Pos (15UL)                    /*!< MCUN1GPIO47 (Bit 15)                                  */
35807 #define GPIO_MCUN1INT1CLR_MCUN1GPIO47_Msk (0x8000UL)                /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
35808 #define GPIO_MCUN1INT1CLR_MCUN1GPIO46_Pos (14UL)                    /*!< MCUN1GPIO46 (Bit 14)                                  */
35809 #define GPIO_MCUN1INT1CLR_MCUN1GPIO46_Msk (0x4000UL)                /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
35810 #define GPIO_MCUN1INT1CLR_MCUN1GPIO45_Pos (13UL)                    /*!< MCUN1GPIO45 (Bit 13)                                  */
35811 #define GPIO_MCUN1INT1CLR_MCUN1GPIO45_Msk (0x2000UL)                /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
35812 #define GPIO_MCUN1INT1CLR_MCUN1GPIO44_Pos (12UL)                    /*!< MCUN1GPIO44 (Bit 12)                                  */
35813 #define GPIO_MCUN1INT1CLR_MCUN1GPIO44_Msk (0x1000UL)                /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
35814 #define GPIO_MCUN1INT1CLR_MCUN1GPIO43_Pos (11UL)                    /*!< MCUN1GPIO43 (Bit 11)                                  */
35815 #define GPIO_MCUN1INT1CLR_MCUN1GPIO43_Msk (0x800UL)                 /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
35816 #define GPIO_MCUN1INT1CLR_MCUN1GPIO42_Pos (10UL)                    /*!< MCUN1GPIO42 (Bit 10)                                  */
35817 #define GPIO_MCUN1INT1CLR_MCUN1GPIO42_Msk (0x400UL)                 /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
35818 #define GPIO_MCUN1INT1CLR_MCUN1GPIO41_Pos (9UL)                     /*!< MCUN1GPIO41 (Bit 9)                                   */
35819 #define GPIO_MCUN1INT1CLR_MCUN1GPIO41_Msk (0x200UL)                 /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
35820 #define GPIO_MCUN1INT1CLR_MCUN1GPIO40_Pos (8UL)                     /*!< MCUN1GPIO40 (Bit 8)                                   */
35821 #define GPIO_MCUN1INT1CLR_MCUN1GPIO40_Msk (0x100UL)                 /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
35822 #define GPIO_MCUN1INT1CLR_MCUN1GPIO39_Pos (7UL)                     /*!< MCUN1GPIO39 (Bit 7)                                   */
35823 #define GPIO_MCUN1INT1CLR_MCUN1GPIO39_Msk (0x80UL)                  /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
35824 #define GPIO_MCUN1INT1CLR_MCUN1GPIO38_Pos (6UL)                     /*!< MCUN1GPIO38 (Bit 6)                                   */
35825 #define GPIO_MCUN1INT1CLR_MCUN1GPIO38_Msk (0x40UL)                  /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
35826 #define GPIO_MCUN1INT1CLR_MCUN1GPIO37_Pos (5UL)                     /*!< MCUN1GPIO37 (Bit 5)                                   */
35827 #define GPIO_MCUN1INT1CLR_MCUN1GPIO37_Msk (0x20UL)                  /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
35828 #define GPIO_MCUN1INT1CLR_MCUN1GPIO36_Pos (4UL)                     /*!< MCUN1GPIO36 (Bit 4)                                   */
35829 #define GPIO_MCUN1INT1CLR_MCUN1GPIO36_Msk (0x10UL)                  /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
35830 #define GPIO_MCUN1INT1CLR_MCUN1GPIO35_Pos (3UL)                     /*!< MCUN1GPIO35 (Bit 3)                                   */
35831 #define GPIO_MCUN1INT1CLR_MCUN1GPIO35_Msk (0x8UL)                   /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
35832 #define GPIO_MCUN1INT1CLR_MCUN1GPIO34_Pos (2UL)                     /*!< MCUN1GPIO34 (Bit 2)                                   */
35833 #define GPIO_MCUN1INT1CLR_MCUN1GPIO34_Msk (0x4UL)                   /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
35834 #define GPIO_MCUN1INT1CLR_MCUN1GPIO33_Pos (1UL)                     /*!< MCUN1GPIO33 (Bit 1)                                   */
35835 #define GPIO_MCUN1INT1CLR_MCUN1GPIO33_Msk (0x2UL)                   /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
35836 #define GPIO_MCUN1INT1CLR_MCUN1GPIO32_Pos (0UL)                     /*!< MCUN1GPIO32 (Bit 0)                                   */
35837 #define GPIO_MCUN1INT1CLR_MCUN1GPIO32_Msk (0x1UL)                   /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
35838 /* =====================================================  MCUN1INT1SET  ====================================================== */
35839 #define GPIO_MCUN1INT1SET_MCUN1GPIO63_Pos (31UL)                    /*!< MCUN1GPIO63 (Bit 31)                                  */
35840 #define GPIO_MCUN1INT1SET_MCUN1GPIO63_Msk (0x80000000UL)            /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
35841 #define GPIO_MCUN1INT1SET_MCUN1GPIO62_Pos (30UL)                    /*!< MCUN1GPIO62 (Bit 30)                                  */
35842 #define GPIO_MCUN1INT1SET_MCUN1GPIO62_Msk (0x40000000UL)            /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
35843 #define GPIO_MCUN1INT1SET_MCUN1GPIO61_Pos (29UL)                    /*!< MCUN1GPIO61 (Bit 29)                                  */
35844 #define GPIO_MCUN1INT1SET_MCUN1GPIO61_Msk (0x20000000UL)            /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
35845 #define GPIO_MCUN1INT1SET_MCUN1GPIO60_Pos (28UL)                    /*!< MCUN1GPIO60 (Bit 28)                                  */
35846 #define GPIO_MCUN1INT1SET_MCUN1GPIO60_Msk (0x10000000UL)            /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
35847 #define GPIO_MCUN1INT1SET_MCUN1GPIO59_Pos (27UL)                    /*!< MCUN1GPIO59 (Bit 27)                                  */
35848 #define GPIO_MCUN1INT1SET_MCUN1GPIO59_Msk (0x8000000UL)             /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
35849 #define GPIO_MCUN1INT1SET_MCUN1GPIO58_Pos (26UL)                    /*!< MCUN1GPIO58 (Bit 26)                                  */
35850 #define GPIO_MCUN1INT1SET_MCUN1GPIO58_Msk (0x4000000UL)             /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
35851 #define GPIO_MCUN1INT1SET_MCUN1GPIO57_Pos (25UL)                    /*!< MCUN1GPIO57 (Bit 25)                                  */
35852 #define GPIO_MCUN1INT1SET_MCUN1GPIO57_Msk (0x2000000UL)             /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
35853 #define GPIO_MCUN1INT1SET_MCUN1GPIO56_Pos (24UL)                    /*!< MCUN1GPIO56 (Bit 24)                                  */
35854 #define GPIO_MCUN1INT1SET_MCUN1GPIO56_Msk (0x1000000UL)             /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
35855 #define GPIO_MCUN1INT1SET_MCUN1GPIO55_Pos (23UL)                    /*!< MCUN1GPIO55 (Bit 23)                                  */
35856 #define GPIO_MCUN1INT1SET_MCUN1GPIO55_Msk (0x800000UL)              /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
35857 #define GPIO_MCUN1INT1SET_MCUN1GPIO54_Pos (22UL)                    /*!< MCUN1GPIO54 (Bit 22)                                  */
35858 #define GPIO_MCUN1INT1SET_MCUN1GPIO54_Msk (0x400000UL)              /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
35859 #define GPIO_MCUN1INT1SET_MCUN1GPIO53_Pos (21UL)                    /*!< MCUN1GPIO53 (Bit 21)                                  */
35860 #define GPIO_MCUN1INT1SET_MCUN1GPIO53_Msk (0x200000UL)              /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
35861 #define GPIO_MCUN1INT1SET_MCUN1GPIO52_Pos (20UL)                    /*!< MCUN1GPIO52 (Bit 20)                                  */
35862 #define GPIO_MCUN1INT1SET_MCUN1GPIO52_Msk (0x100000UL)              /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
35863 #define GPIO_MCUN1INT1SET_MCUN1GPIO51_Pos (19UL)                    /*!< MCUN1GPIO51 (Bit 19)                                  */
35864 #define GPIO_MCUN1INT1SET_MCUN1GPIO51_Msk (0x80000UL)               /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
35865 #define GPIO_MCUN1INT1SET_MCUN1GPIO50_Pos (18UL)                    /*!< MCUN1GPIO50 (Bit 18)                                  */
35866 #define GPIO_MCUN1INT1SET_MCUN1GPIO50_Msk (0x40000UL)               /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
35867 #define GPIO_MCUN1INT1SET_MCUN1GPIO49_Pos (17UL)                    /*!< MCUN1GPIO49 (Bit 17)                                  */
35868 #define GPIO_MCUN1INT1SET_MCUN1GPIO49_Msk (0x20000UL)               /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
35869 #define GPIO_MCUN1INT1SET_MCUN1GPIO48_Pos (16UL)                    /*!< MCUN1GPIO48 (Bit 16)                                  */
35870 #define GPIO_MCUN1INT1SET_MCUN1GPIO48_Msk (0x10000UL)               /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
35871 #define GPIO_MCUN1INT1SET_MCUN1GPIO47_Pos (15UL)                    /*!< MCUN1GPIO47 (Bit 15)                                  */
35872 #define GPIO_MCUN1INT1SET_MCUN1GPIO47_Msk (0x8000UL)                /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
35873 #define GPIO_MCUN1INT1SET_MCUN1GPIO46_Pos (14UL)                    /*!< MCUN1GPIO46 (Bit 14)                                  */
35874 #define GPIO_MCUN1INT1SET_MCUN1GPIO46_Msk (0x4000UL)                /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
35875 #define GPIO_MCUN1INT1SET_MCUN1GPIO45_Pos (13UL)                    /*!< MCUN1GPIO45 (Bit 13)                                  */
35876 #define GPIO_MCUN1INT1SET_MCUN1GPIO45_Msk (0x2000UL)                /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
35877 #define GPIO_MCUN1INT1SET_MCUN1GPIO44_Pos (12UL)                    /*!< MCUN1GPIO44 (Bit 12)                                  */
35878 #define GPIO_MCUN1INT1SET_MCUN1GPIO44_Msk (0x1000UL)                /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
35879 #define GPIO_MCUN1INT1SET_MCUN1GPIO43_Pos (11UL)                    /*!< MCUN1GPIO43 (Bit 11)                                  */
35880 #define GPIO_MCUN1INT1SET_MCUN1GPIO43_Msk (0x800UL)                 /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
35881 #define GPIO_MCUN1INT1SET_MCUN1GPIO42_Pos (10UL)                    /*!< MCUN1GPIO42 (Bit 10)                                  */
35882 #define GPIO_MCUN1INT1SET_MCUN1GPIO42_Msk (0x400UL)                 /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
35883 #define GPIO_MCUN1INT1SET_MCUN1GPIO41_Pos (9UL)                     /*!< MCUN1GPIO41 (Bit 9)                                   */
35884 #define GPIO_MCUN1INT1SET_MCUN1GPIO41_Msk (0x200UL)                 /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
35885 #define GPIO_MCUN1INT1SET_MCUN1GPIO40_Pos (8UL)                     /*!< MCUN1GPIO40 (Bit 8)                                   */
35886 #define GPIO_MCUN1INT1SET_MCUN1GPIO40_Msk (0x100UL)                 /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
35887 #define GPIO_MCUN1INT1SET_MCUN1GPIO39_Pos (7UL)                     /*!< MCUN1GPIO39 (Bit 7)                                   */
35888 #define GPIO_MCUN1INT1SET_MCUN1GPIO39_Msk (0x80UL)                  /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
35889 #define GPIO_MCUN1INT1SET_MCUN1GPIO38_Pos (6UL)                     /*!< MCUN1GPIO38 (Bit 6)                                   */
35890 #define GPIO_MCUN1INT1SET_MCUN1GPIO38_Msk (0x40UL)                  /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
35891 #define GPIO_MCUN1INT1SET_MCUN1GPIO37_Pos (5UL)                     /*!< MCUN1GPIO37 (Bit 5)                                   */
35892 #define GPIO_MCUN1INT1SET_MCUN1GPIO37_Msk (0x20UL)                  /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
35893 #define GPIO_MCUN1INT1SET_MCUN1GPIO36_Pos (4UL)                     /*!< MCUN1GPIO36 (Bit 4)                                   */
35894 #define GPIO_MCUN1INT1SET_MCUN1GPIO36_Msk (0x10UL)                  /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
35895 #define GPIO_MCUN1INT1SET_MCUN1GPIO35_Pos (3UL)                     /*!< MCUN1GPIO35 (Bit 3)                                   */
35896 #define GPIO_MCUN1INT1SET_MCUN1GPIO35_Msk (0x8UL)                   /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
35897 #define GPIO_MCUN1INT1SET_MCUN1GPIO34_Pos (2UL)                     /*!< MCUN1GPIO34 (Bit 2)                                   */
35898 #define GPIO_MCUN1INT1SET_MCUN1GPIO34_Msk (0x4UL)                   /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
35899 #define GPIO_MCUN1INT1SET_MCUN1GPIO33_Pos (1UL)                     /*!< MCUN1GPIO33 (Bit 1)                                   */
35900 #define GPIO_MCUN1INT1SET_MCUN1GPIO33_Msk (0x2UL)                   /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
35901 #define GPIO_MCUN1INT1SET_MCUN1GPIO32_Pos (0UL)                     /*!< MCUN1GPIO32 (Bit 0)                                   */
35902 #define GPIO_MCUN1INT1SET_MCUN1GPIO32_Msk (0x1UL)                   /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
35903 /* ======================================================  MCUN1INT2EN  ====================================================== */
35904 #define GPIO_MCUN1INT2EN_MCUN1GPIO95_Pos  (31UL)                    /*!< MCUN1GPIO95 (Bit 31)                                  */
35905 #define GPIO_MCUN1INT2EN_MCUN1GPIO95_Msk  (0x80000000UL)            /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
35906 #define GPIO_MCUN1INT2EN_MCUN1GPIO94_Pos  (30UL)                    /*!< MCUN1GPIO94 (Bit 30)                                  */
35907 #define GPIO_MCUN1INT2EN_MCUN1GPIO94_Msk  (0x40000000UL)            /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
35908 #define GPIO_MCUN1INT2EN_MCUN1GPIO93_Pos  (29UL)                    /*!< MCUN1GPIO93 (Bit 29)                                  */
35909 #define GPIO_MCUN1INT2EN_MCUN1GPIO93_Msk  (0x20000000UL)            /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
35910 #define GPIO_MCUN1INT2EN_MCUN1GPIO92_Pos  (28UL)                    /*!< MCUN1GPIO92 (Bit 28)                                  */
35911 #define GPIO_MCUN1INT2EN_MCUN1GPIO92_Msk  (0x10000000UL)            /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
35912 #define GPIO_MCUN1INT2EN_MCUN1GPIO91_Pos  (27UL)                    /*!< MCUN1GPIO91 (Bit 27)                                  */
35913 #define GPIO_MCUN1INT2EN_MCUN1GPIO91_Msk  (0x8000000UL)             /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
35914 #define GPIO_MCUN1INT2EN_MCUN1GPIO90_Pos  (26UL)                    /*!< MCUN1GPIO90 (Bit 26)                                  */
35915 #define GPIO_MCUN1INT2EN_MCUN1GPIO90_Msk  (0x4000000UL)             /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
35916 #define GPIO_MCUN1INT2EN_MCUN1GPIO89_Pos  (25UL)                    /*!< MCUN1GPIO89 (Bit 25)                                  */
35917 #define GPIO_MCUN1INT2EN_MCUN1GPIO89_Msk  (0x2000000UL)             /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
35918 #define GPIO_MCUN1INT2EN_MCUN1GPIO88_Pos  (24UL)                    /*!< MCUN1GPIO88 (Bit 24)                                  */
35919 #define GPIO_MCUN1INT2EN_MCUN1GPIO88_Msk  (0x1000000UL)             /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
35920 #define GPIO_MCUN1INT2EN_MCUN1GPIO87_Pos  (23UL)                    /*!< MCUN1GPIO87 (Bit 23)                                  */
35921 #define GPIO_MCUN1INT2EN_MCUN1GPIO87_Msk  (0x800000UL)              /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
35922 #define GPIO_MCUN1INT2EN_MCUN1GPIO86_Pos  (22UL)                    /*!< MCUN1GPIO86 (Bit 22)                                  */
35923 #define GPIO_MCUN1INT2EN_MCUN1GPIO86_Msk  (0x400000UL)              /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
35924 #define GPIO_MCUN1INT2EN_MCUN1GPIO85_Pos  (21UL)                    /*!< MCUN1GPIO85 (Bit 21)                                  */
35925 #define GPIO_MCUN1INT2EN_MCUN1GPIO85_Msk  (0x200000UL)              /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
35926 #define GPIO_MCUN1INT2EN_MCUN1GPIO84_Pos  (20UL)                    /*!< MCUN1GPIO84 (Bit 20)                                  */
35927 #define GPIO_MCUN1INT2EN_MCUN1GPIO84_Msk  (0x100000UL)              /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
35928 #define GPIO_MCUN1INT2EN_MCUN1GPIO83_Pos  (19UL)                    /*!< MCUN1GPIO83 (Bit 19)                                  */
35929 #define GPIO_MCUN1INT2EN_MCUN1GPIO83_Msk  (0x80000UL)               /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
35930 #define GPIO_MCUN1INT2EN_MCUN1GPIO82_Pos  (18UL)                    /*!< MCUN1GPIO82 (Bit 18)                                  */
35931 #define GPIO_MCUN1INT2EN_MCUN1GPIO82_Msk  (0x40000UL)               /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
35932 #define GPIO_MCUN1INT2EN_MCUN1GPIO81_Pos  (17UL)                    /*!< MCUN1GPIO81 (Bit 17)                                  */
35933 #define GPIO_MCUN1INT2EN_MCUN1GPIO81_Msk  (0x20000UL)               /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
35934 #define GPIO_MCUN1INT2EN_MCUN1GPIO80_Pos  (16UL)                    /*!< MCUN1GPIO80 (Bit 16)                                  */
35935 #define GPIO_MCUN1INT2EN_MCUN1GPIO80_Msk  (0x10000UL)               /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
35936 #define GPIO_MCUN1INT2EN_MCUN1GPIO79_Pos  (15UL)                    /*!< MCUN1GPIO79 (Bit 15)                                  */
35937 #define GPIO_MCUN1INT2EN_MCUN1GPIO79_Msk  (0x8000UL)                /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
35938 #define GPIO_MCUN1INT2EN_MCUN1GPIO78_Pos  (14UL)                    /*!< MCUN1GPIO78 (Bit 14)                                  */
35939 #define GPIO_MCUN1INT2EN_MCUN1GPIO78_Msk  (0x4000UL)                /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
35940 #define GPIO_MCUN1INT2EN_MCUN1GPIO77_Pos  (13UL)                    /*!< MCUN1GPIO77 (Bit 13)                                  */
35941 #define GPIO_MCUN1INT2EN_MCUN1GPIO77_Msk  (0x2000UL)                /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
35942 #define GPIO_MCUN1INT2EN_MCUN1GPIO76_Pos  (12UL)                    /*!< MCUN1GPIO76 (Bit 12)                                  */
35943 #define GPIO_MCUN1INT2EN_MCUN1GPIO76_Msk  (0x1000UL)                /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
35944 #define GPIO_MCUN1INT2EN_MCUN1GPIO75_Pos  (11UL)                    /*!< MCUN1GPIO75 (Bit 11)                                  */
35945 #define GPIO_MCUN1INT2EN_MCUN1GPIO75_Msk  (0x800UL)                 /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
35946 #define GPIO_MCUN1INT2EN_MCUN1GPIO74_Pos  (10UL)                    /*!< MCUN1GPIO74 (Bit 10)                                  */
35947 #define GPIO_MCUN1INT2EN_MCUN1GPIO74_Msk  (0x400UL)                 /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
35948 #define GPIO_MCUN1INT2EN_MCUN1GPIO73_Pos  (9UL)                     /*!< MCUN1GPIO73 (Bit 9)                                   */
35949 #define GPIO_MCUN1INT2EN_MCUN1GPIO73_Msk  (0x200UL)                 /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
35950 #define GPIO_MCUN1INT2EN_MCUN1GPIO72_Pos  (8UL)                     /*!< MCUN1GPIO72 (Bit 8)                                   */
35951 #define GPIO_MCUN1INT2EN_MCUN1GPIO72_Msk  (0x100UL)                 /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
35952 #define GPIO_MCUN1INT2EN_MCUN1GPIO71_Pos  (7UL)                     /*!< MCUN1GPIO71 (Bit 7)                                   */
35953 #define GPIO_MCUN1INT2EN_MCUN1GPIO71_Msk  (0x80UL)                  /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
35954 #define GPIO_MCUN1INT2EN_MCUN1GPIO70_Pos  (6UL)                     /*!< MCUN1GPIO70 (Bit 6)                                   */
35955 #define GPIO_MCUN1INT2EN_MCUN1GPIO70_Msk  (0x40UL)                  /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
35956 #define GPIO_MCUN1INT2EN_MCUN1GPIO69_Pos  (5UL)                     /*!< MCUN1GPIO69 (Bit 5)                                   */
35957 #define GPIO_MCUN1INT2EN_MCUN1GPIO69_Msk  (0x20UL)                  /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
35958 #define GPIO_MCUN1INT2EN_MCUN1GPIO68_Pos  (4UL)                     /*!< MCUN1GPIO68 (Bit 4)                                   */
35959 #define GPIO_MCUN1INT2EN_MCUN1GPIO68_Msk  (0x10UL)                  /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
35960 #define GPIO_MCUN1INT2EN_MCUN1GPIO67_Pos  (3UL)                     /*!< MCUN1GPIO67 (Bit 3)                                   */
35961 #define GPIO_MCUN1INT2EN_MCUN1GPIO67_Msk  (0x8UL)                   /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
35962 #define GPIO_MCUN1INT2EN_MCUN1GPIO66_Pos  (2UL)                     /*!< MCUN1GPIO66 (Bit 2)                                   */
35963 #define GPIO_MCUN1INT2EN_MCUN1GPIO66_Msk  (0x4UL)                   /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
35964 #define GPIO_MCUN1INT2EN_MCUN1GPIO65_Pos  (1UL)                     /*!< MCUN1GPIO65 (Bit 1)                                   */
35965 #define GPIO_MCUN1INT2EN_MCUN1GPIO65_Msk  (0x2UL)                   /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
35966 #define GPIO_MCUN1INT2EN_MCUN1GPIO64_Pos  (0UL)                     /*!< MCUN1GPIO64 (Bit 0)                                   */
35967 #define GPIO_MCUN1INT2EN_MCUN1GPIO64_Msk  (0x1UL)                   /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
35968 /* =====================================================  MCUN1INT2STAT  ===================================================== */
35969 #define GPIO_MCUN1INT2STAT_MCUN1GPIO95_Pos (31UL)                   /*!< MCUN1GPIO95 (Bit 31)                                  */
35970 #define GPIO_MCUN1INT2STAT_MCUN1GPIO95_Msk (0x80000000UL)           /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
35971 #define GPIO_MCUN1INT2STAT_MCUN1GPIO94_Pos (30UL)                   /*!< MCUN1GPIO94 (Bit 30)                                  */
35972 #define GPIO_MCUN1INT2STAT_MCUN1GPIO94_Msk (0x40000000UL)           /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
35973 #define GPIO_MCUN1INT2STAT_MCUN1GPIO93_Pos (29UL)                   /*!< MCUN1GPIO93 (Bit 29)                                  */
35974 #define GPIO_MCUN1INT2STAT_MCUN1GPIO93_Msk (0x20000000UL)           /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
35975 #define GPIO_MCUN1INT2STAT_MCUN1GPIO92_Pos (28UL)                   /*!< MCUN1GPIO92 (Bit 28)                                  */
35976 #define GPIO_MCUN1INT2STAT_MCUN1GPIO92_Msk (0x10000000UL)           /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
35977 #define GPIO_MCUN1INT2STAT_MCUN1GPIO91_Pos (27UL)                   /*!< MCUN1GPIO91 (Bit 27)                                  */
35978 #define GPIO_MCUN1INT2STAT_MCUN1GPIO91_Msk (0x8000000UL)            /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
35979 #define GPIO_MCUN1INT2STAT_MCUN1GPIO90_Pos (26UL)                   /*!< MCUN1GPIO90 (Bit 26)                                  */
35980 #define GPIO_MCUN1INT2STAT_MCUN1GPIO90_Msk (0x4000000UL)            /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
35981 #define GPIO_MCUN1INT2STAT_MCUN1GPIO89_Pos (25UL)                   /*!< MCUN1GPIO89 (Bit 25)                                  */
35982 #define GPIO_MCUN1INT2STAT_MCUN1GPIO89_Msk (0x2000000UL)            /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
35983 #define GPIO_MCUN1INT2STAT_MCUN1GPIO88_Pos (24UL)                   /*!< MCUN1GPIO88 (Bit 24)                                  */
35984 #define GPIO_MCUN1INT2STAT_MCUN1GPIO88_Msk (0x1000000UL)            /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
35985 #define GPIO_MCUN1INT2STAT_MCUN1GPIO87_Pos (23UL)                   /*!< MCUN1GPIO87 (Bit 23)                                  */
35986 #define GPIO_MCUN1INT2STAT_MCUN1GPIO87_Msk (0x800000UL)             /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
35987 #define GPIO_MCUN1INT2STAT_MCUN1GPIO86_Pos (22UL)                   /*!< MCUN1GPIO86 (Bit 22)                                  */
35988 #define GPIO_MCUN1INT2STAT_MCUN1GPIO86_Msk (0x400000UL)             /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
35989 #define GPIO_MCUN1INT2STAT_MCUN1GPIO85_Pos (21UL)                   /*!< MCUN1GPIO85 (Bit 21)                                  */
35990 #define GPIO_MCUN1INT2STAT_MCUN1GPIO85_Msk (0x200000UL)             /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
35991 #define GPIO_MCUN1INT2STAT_MCUN1GPIO84_Pos (20UL)                   /*!< MCUN1GPIO84 (Bit 20)                                  */
35992 #define GPIO_MCUN1INT2STAT_MCUN1GPIO84_Msk (0x100000UL)             /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
35993 #define GPIO_MCUN1INT2STAT_MCUN1GPIO83_Pos (19UL)                   /*!< MCUN1GPIO83 (Bit 19)                                  */
35994 #define GPIO_MCUN1INT2STAT_MCUN1GPIO83_Msk (0x80000UL)              /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
35995 #define GPIO_MCUN1INT2STAT_MCUN1GPIO82_Pos (18UL)                   /*!< MCUN1GPIO82 (Bit 18)                                  */
35996 #define GPIO_MCUN1INT2STAT_MCUN1GPIO82_Msk (0x40000UL)              /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
35997 #define GPIO_MCUN1INT2STAT_MCUN1GPIO81_Pos (17UL)                   /*!< MCUN1GPIO81 (Bit 17)                                  */
35998 #define GPIO_MCUN1INT2STAT_MCUN1GPIO81_Msk (0x20000UL)              /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
35999 #define GPIO_MCUN1INT2STAT_MCUN1GPIO80_Pos (16UL)                   /*!< MCUN1GPIO80 (Bit 16)                                  */
36000 #define GPIO_MCUN1INT2STAT_MCUN1GPIO80_Msk (0x10000UL)              /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
36001 #define GPIO_MCUN1INT2STAT_MCUN1GPIO79_Pos (15UL)                   /*!< MCUN1GPIO79 (Bit 15)                                  */
36002 #define GPIO_MCUN1INT2STAT_MCUN1GPIO79_Msk (0x8000UL)               /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
36003 #define GPIO_MCUN1INT2STAT_MCUN1GPIO78_Pos (14UL)                   /*!< MCUN1GPIO78 (Bit 14)                                  */
36004 #define GPIO_MCUN1INT2STAT_MCUN1GPIO78_Msk (0x4000UL)               /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
36005 #define GPIO_MCUN1INT2STAT_MCUN1GPIO77_Pos (13UL)                   /*!< MCUN1GPIO77 (Bit 13)                                  */
36006 #define GPIO_MCUN1INT2STAT_MCUN1GPIO77_Msk (0x2000UL)               /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
36007 #define GPIO_MCUN1INT2STAT_MCUN1GPIO76_Pos (12UL)                   /*!< MCUN1GPIO76 (Bit 12)                                  */
36008 #define GPIO_MCUN1INT2STAT_MCUN1GPIO76_Msk (0x1000UL)               /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
36009 #define GPIO_MCUN1INT2STAT_MCUN1GPIO75_Pos (11UL)                   /*!< MCUN1GPIO75 (Bit 11)                                  */
36010 #define GPIO_MCUN1INT2STAT_MCUN1GPIO75_Msk (0x800UL)                /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
36011 #define GPIO_MCUN1INT2STAT_MCUN1GPIO74_Pos (10UL)                   /*!< MCUN1GPIO74 (Bit 10)                                  */
36012 #define GPIO_MCUN1INT2STAT_MCUN1GPIO74_Msk (0x400UL)                /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
36013 #define GPIO_MCUN1INT2STAT_MCUN1GPIO73_Pos (9UL)                    /*!< MCUN1GPIO73 (Bit 9)                                   */
36014 #define GPIO_MCUN1INT2STAT_MCUN1GPIO73_Msk (0x200UL)                /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
36015 #define GPIO_MCUN1INT2STAT_MCUN1GPIO72_Pos (8UL)                    /*!< MCUN1GPIO72 (Bit 8)                                   */
36016 #define GPIO_MCUN1INT2STAT_MCUN1GPIO72_Msk (0x100UL)                /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
36017 #define GPIO_MCUN1INT2STAT_MCUN1GPIO71_Pos (7UL)                    /*!< MCUN1GPIO71 (Bit 7)                                   */
36018 #define GPIO_MCUN1INT2STAT_MCUN1GPIO71_Msk (0x80UL)                 /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
36019 #define GPIO_MCUN1INT2STAT_MCUN1GPIO70_Pos (6UL)                    /*!< MCUN1GPIO70 (Bit 6)                                   */
36020 #define GPIO_MCUN1INT2STAT_MCUN1GPIO70_Msk (0x40UL)                 /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
36021 #define GPIO_MCUN1INT2STAT_MCUN1GPIO69_Pos (5UL)                    /*!< MCUN1GPIO69 (Bit 5)                                   */
36022 #define GPIO_MCUN1INT2STAT_MCUN1GPIO69_Msk (0x20UL)                 /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
36023 #define GPIO_MCUN1INT2STAT_MCUN1GPIO68_Pos (4UL)                    /*!< MCUN1GPIO68 (Bit 4)                                   */
36024 #define GPIO_MCUN1INT2STAT_MCUN1GPIO68_Msk (0x10UL)                 /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
36025 #define GPIO_MCUN1INT2STAT_MCUN1GPIO67_Pos (3UL)                    /*!< MCUN1GPIO67 (Bit 3)                                   */
36026 #define GPIO_MCUN1INT2STAT_MCUN1GPIO67_Msk (0x8UL)                  /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
36027 #define GPIO_MCUN1INT2STAT_MCUN1GPIO66_Pos (2UL)                    /*!< MCUN1GPIO66 (Bit 2)                                   */
36028 #define GPIO_MCUN1INT2STAT_MCUN1GPIO66_Msk (0x4UL)                  /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
36029 #define GPIO_MCUN1INT2STAT_MCUN1GPIO65_Pos (1UL)                    /*!< MCUN1GPIO65 (Bit 1)                                   */
36030 #define GPIO_MCUN1INT2STAT_MCUN1GPIO65_Msk (0x2UL)                  /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
36031 #define GPIO_MCUN1INT2STAT_MCUN1GPIO64_Pos (0UL)                    /*!< MCUN1GPIO64 (Bit 0)                                   */
36032 #define GPIO_MCUN1INT2STAT_MCUN1GPIO64_Msk (0x1UL)                  /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
36033 /* =====================================================  MCUN1INT2CLR  ====================================================== */
36034 #define GPIO_MCUN1INT2CLR_MCUN1GPIO95_Pos (31UL)                    /*!< MCUN1GPIO95 (Bit 31)                                  */
36035 #define GPIO_MCUN1INT2CLR_MCUN1GPIO95_Msk (0x80000000UL)            /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
36036 #define GPIO_MCUN1INT2CLR_MCUN1GPIO94_Pos (30UL)                    /*!< MCUN1GPIO94 (Bit 30)                                  */
36037 #define GPIO_MCUN1INT2CLR_MCUN1GPIO94_Msk (0x40000000UL)            /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
36038 #define GPIO_MCUN1INT2CLR_MCUN1GPIO93_Pos (29UL)                    /*!< MCUN1GPIO93 (Bit 29)                                  */
36039 #define GPIO_MCUN1INT2CLR_MCUN1GPIO93_Msk (0x20000000UL)            /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
36040 #define GPIO_MCUN1INT2CLR_MCUN1GPIO92_Pos (28UL)                    /*!< MCUN1GPIO92 (Bit 28)                                  */
36041 #define GPIO_MCUN1INT2CLR_MCUN1GPIO92_Msk (0x10000000UL)            /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
36042 #define GPIO_MCUN1INT2CLR_MCUN1GPIO91_Pos (27UL)                    /*!< MCUN1GPIO91 (Bit 27)                                  */
36043 #define GPIO_MCUN1INT2CLR_MCUN1GPIO91_Msk (0x8000000UL)             /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
36044 #define GPIO_MCUN1INT2CLR_MCUN1GPIO90_Pos (26UL)                    /*!< MCUN1GPIO90 (Bit 26)                                  */
36045 #define GPIO_MCUN1INT2CLR_MCUN1GPIO90_Msk (0x4000000UL)             /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
36046 #define GPIO_MCUN1INT2CLR_MCUN1GPIO89_Pos (25UL)                    /*!< MCUN1GPIO89 (Bit 25)                                  */
36047 #define GPIO_MCUN1INT2CLR_MCUN1GPIO89_Msk (0x2000000UL)             /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
36048 #define GPIO_MCUN1INT2CLR_MCUN1GPIO88_Pos (24UL)                    /*!< MCUN1GPIO88 (Bit 24)                                  */
36049 #define GPIO_MCUN1INT2CLR_MCUN1GPIO88_Msk (0x1000000UL)             /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
36050 #define GPIO_MCUN1INT2CLR_MCUN1GPIO87_Pos (23UL)                    /*!< MCUN1GPIO87 (Bit 23)                                  */
36051 #define GPIO_MCUN1INT2CLR_MCUN1GPIO87_Msk (0x800000UL)              /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
36052 #define GPIO_MCUN1INT2CLR_MCUN1GPIO86_Pos (22UL)                    /*!< MCUN1GPIO86 (Bit 22)                                  */
36053 #define GPIO_MCUN1INT2CLR_MCUN1GPIO86_Msk (0x400000UL)              /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
36054 #define GPIO_MCUN1INT2CLR_MCUN1GPIO85_Pos (21UL)                    /*!< MCUN1GPIO85 (Bit 21)                                  */
36055 #define GPIO_MCUN1INT2CLR_MCUN1GPIO85_Msk (0x200000UL)              /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
36056 #define GPIO_MCUN1INT2CLR_MCUN1GPIO84_Pos (20UL)                    /*!< MCUN1GPIO84 (Bit 20)                                  */
36057 #define GPIO_MCUN1INT2CLR_MCUN1GPIO84_Msk (0x100000UL)              /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
36058 #define GPIO_MCUN1INT2CLR_MCUN1GPIO83_Pos (19UL)                    /*!< MCUN1GPIO83 (Bit 19)                                  */
36059 #define GPIO_MCUN1INT2CLR_MCUN1GPIO83_Msk (0x80000UL)               /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
36060 #define GPIO_MCUN1INT2CLR_MCUN1GPIO82_Pos (18UL)                    /*!< MCUN1GPIO82 (Bit 18)                                  */
36061 #define GPIO_MCUN1INT2CLR_MCUN1GPIO82_Msk (0x40000UL)               /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
36062 #define GPIO_MCUN1INT2CLR_MCUN1GPIO81_Pos (17UL)                    /*!< MCUN1GPIO81 (Bit 17)                                  */
36063 #define GPIO_MCUN1INT2CLR_MCUN1GPIO81_Msk (0x20000UL)               /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
36064 #define GPIO_MCUN1INT2CLR_MCUN1GPIO80_Pos (16UL)                    /*!< MCUN1GPIO80 (Bit 16)                                  */
36065 #define GPIO_MCUN1INT2CLR_MCUN1GPIO80_Msk (0x10000UL)               /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
36066 #define GPIO_MCUN1INT2CLR_MCUN1GPIO79_Pos (15UL)                    /*!< MCUN1GPIO79 (Bit 15)                                  */
36067 #define GPIO_MCUN1INT2CLR_MCUN1GPIO79_Msk (0x8000UL)                /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
36068 #define GPIO_MCUN1INT2CLR_MCUN1GPIO78_Pos (14UL)                    /*!< MCUN1GPIO78 (Bit 14)                                  */
36069 #define GPIO_MCUN1INT2CLR_MCUN1GPIO78_Msk (0x4000UL)                /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
36070 #define GPIO_MCUN1INT2CLR_MCUN1GPIO77_Pos (13UL)                    /*!< MCUN1GPIO77 (Bit 13)                                  */
36071 #define GPIO_MCUN1INT2CLR_MCUN1GPIO77_Msk (0x2000UL)                /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
36072 #define GPIO_MCUN1INT2CLR_MCUN1GPIO76_Pos (12UL)                    /*!< MCUN1GPIO76 (Bit 12)                                  */
36073 #define GPIO_MCUN1INT2CLR_MCUN1GPIO76_Msk (0x1000UL)                /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
36074 #define GPIO_MCUN1INT2CLR_MCUN1GPIO75_Pos (11UL)                    /*!< MCUN1GPIO75 (Bit 11)                                  */
36075 #define GPIO_MCUN1INT2CLR_MCUN1GPIO75_Msk (0x800UL)                 /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
36076 #define GPIO_MCUN1INT2CLR_MCUN1GPIO74_Pos (10UL)                    /*!< MCUN1GPIO74 (Bit 10)                                  */
36077 #define GPIO_MCUN1INT2CLR_MCUN1GPIO74_Msk (0x400UL)                 /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
36078 #define GPIO_MCUN1INT2CLR_MCUN1GPIO73_Pos (9UL)                     /*!< MCUN1GPIO73 (Bit 9)                                   */
36079 #define GPIO_MCUN1INT2CLR_MCUN1GPIO73_Msk (0x200UL)                 /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
36080 #define GPIO_MCUN1INT2CLR_MCUN1GPIO72_Pos (8UL)                     /*!< MCUN1GPIO72 (Bit 8)                                   */
36081 #define GPIO_MCUN1INT2CLR_MCUN1GPIO72_Msk (0x100UL)                 /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
36082 #define GPIO_MCUN1INT2CLR_MCUN1GPIO71_Pos (7UL)                     /*!< MCUN1GPIO71 (Bit 7)                                   */
36083 #define GPIO_MCUN1INT2CLR_MCUN1GPIO71_Msk (0x80UL)                  /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
36084 #define GPIO_MCUN1INT2CLR_MCUN1GPIO70_Pos (6UL)                     /*!< MCUN1GPIO70 (Bit 6)                                   */
36085 #define GPIO_MCUN1INT2CLR_MCUN1GPIO70_Msk (0x40UL)                  /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
36086 #define GPIO_MCUN1INT2CLR_MCUN1GPIO69_Pos (5UL)                     /*!< MCUN1GPIO69 (Bit 5)                                   */
36087 #define GPIO_MCUN1INT2CLR_MCUN1GPIO69_Msk (0x20UL)                  /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
36088 #define GPIO_MCUN1INT2CLR_MCUN1GPIO68_Pos (4UL)                     /*!< MCUN1GPIO68 (Bit 4)                                   */
36089 #define GPIO_MCUN1INT2CLR_MCUN1GPIO68_Msk (0x10UL)                  /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
36090 #define GPIO_MCUN1INT2CLR_MCUN1GPIO67_Pos (3UL)                     /*!< MCUN1GPIO67 (Bit 3)                                   */
36091 #define GPIO_MCUN1INT2CLR_MCUN1GPIO67_Msk (0x8UL)                   /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
36092 #define GPIO_MCUN1INT2CLR_MCUN1GPIO66_Pos (2UL)                     /*!< MCUN1GPIO66 (Bit 2)                                   */
36093 #define GPIO_MCUN1INT2CLR_MCUN1GPIO66_Msk (0x4UL)                   /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
36094 #define GPIO_MCUN1INT2CLR_MCUN1GPIO65_Pos (1UL)                     /*!< MCUN1GPIO65 (Bit 1)                                   */
36095 #define GPIO_MCUN1INT2CLR_MCUN1GPIO65_Msk (0x2UL)                   /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
36096 #define GPIO_MCUN1INT2CLR_MCUN1GPIO64_Pos (0UL)                     /*!< MCUN1GPIO64 (Bit 0)                                   */
36097 #define GPIO_MCUN1INT2CLR_MCUN1GPIO64_Msk (0x1UL)                   /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
36098 /* =====================================================  MCUN1INT2SET  ====================================================== */
36099 #define GPIO_MCUN1INT2SET_MCUN1GPIO95_Pos (31UL)                    /*!< MCUN1GPIO95 (Bit 31)                                  */
36100 #define GPIO_MCUN1INT2SET_MCUN1GPIO95_Msk (0x80000000UL)            /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
36101 #define GPIO_MCUN1INT2SET_MCUN1GPIO94_Pos (30UL)                    /*!< MCUN1GPIO94 (Bit 30)                                  */
36102 #define GPIO_MCUN1INT2SET_MCUN1GPIO94_Msk (0x40000000UL)            /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
36103 #define GPIO_MCUN1INT2SET_MCUN1GPIO93_Pos (29UL)                    /*!< MCUN1GPIO93 (Bit 29)                                  */
36104 #define GPIO_MCUN1INT2SET_MCUN1GPIO93_Msk (0x20000000UL)            /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
36105 #define GPIO_MCUN1INT2SET_MCUN1GPIO92_Pos (28UL)                    /*!< MCUN1GPIO92 (Bit 28)                                  */
36106 #define GPIO_MCUN1INT2SET_MCUN1GPIO92_Msk (0x10000000UL)            /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
36107 #define GPIO_MCUN1INT2SET_MCUN1GPIO91_Pos (27UL)                    /*!< MCUN1GPIO91 (Bit 27)                                  */
36108 #define GPIO_MCUN1INT2SET_MCUN1GPIO91_Msk (0x8000000UL)             /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
36109 #define GPIO_MCUN1INT2SET_MCUN1GPIO90_Pos (26UL)                    /*!< MCUN1GPIO90 (Bit 26)                                  */
36110 #define GPIO_MCUN1INT2SET_MCUN1GPIO90_Msk (0x4000000UL)             /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
36111 #define GPIO_MCUN1INT2SET_MCUN1GPIO89_Pos (25UL)                    /*!< MCUN1GPIO89 (Bit 25)                                  */
36112 #define GPIO_MCUN1INT2SET_MCUN1GPIO89_Msk (0x2000000UL)             /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
36113 #define GPIO_MCUN1INT2SET_MCUN1GPIO88_Pos (24UL)                    /*!< MCUN1GPIO88 (Bit 24)                                  */
36114 #define GPIO_MCUN1INT2SET_MCUN1GPIO88_Msk (0x1000000UL)             /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
36115 #define GPIO_MCUN1INT2SET_MCUN1GPIO87_Pos (23UL)                    /*!< MCUN1GPIO87 (Bit 23)                                  */
36116 #define GPIO_MCUN1INT2SET_MCUN1GPIO87_Msk (0x800000UL)              /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
36117 #define GPIO_MCUN1INT2SET_MCUN1GPIO86_Pos (22UL)                    /*!< MCUN1GPIO86 (Bit 22)                                  */
36118 #define GPIO_MCUN1INT2SET_MCUN1GPIO86_Msk (0x400000UL)              /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
36119 #define GPIO_MCUN1INT2SET_MCUN1GPIO85_Pos (21UL)                    /*!< MCUN1GPIO85 (Bit 21)                                  */
36120 #define GPIO_MCUN1INT2SET_MCUN1GPIO85_Msk (0x200000UL)              /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
36121 #define GPIO_MCUN1INT2SET_MCUN1GPIO84_Pos (20UL)                    /*!< MCUN1GPIO84 (Bit 20)                                  */
36122 #define GPIO_MCUN1INT2SET_MCUN1GPIO84_Msk (0x100000UL)              /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
36123 #define GPIO_MCUN1INT2SET_MCUN1GPIO83_Pos (19UL)                    /*!< MCUN1GPIO83 (Bit 19)                                  */
36124 #define GPIO_MCUN1INT2SET_MCUN1GPIO83_Msk (0x80000UL)               /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
36125 #define GPIO_MCUN1INT2SET_MCUN1GPIO82_Pos (18UL)                    /*!< MCUN1GPIO82 (Bit 18)                                  */
36126 #define GPIO_MCUN1INT2SET_MCUN1GPIO82_Msk (0x40000UL)               /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
36127 #define GPIO_MCUN1INT2SET_MCUN1GPIO81_Pos (17UL)                    /*!< MCUN1GPIO81 (Bit 17)                                  */
36128 #define GPIO_MCUN1INT2SET_MCUN1GPIO81_Msk (0x20000UL)               /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
36129 #define GPIO_MCUN1INT2SET_MCUN1GPIO80_Pos (16UL)                    /*!< MCUN1GPIO80 (Bit 16)                                  */
36130 #define GPIO_MCUN1INT2SET_MCUN1GPIO80_Msk (0x10000UL)               /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
36131 #define GPIO_MCUN1INT2SET_MCUN1GPIO79_Pos (15UL)                    /*!< MCUN1GPIO79 (Bit 15)                                  */
36132 #define GPIO_MCUN1INT2SET_MCUN1GPIO79_Msk (0x8000UL)                /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
36133 #define GPIO_MCUN1INT2SET_MCUN1GPIO78_Pos (14UL)                    /*!< MCUN1GPIO78 (Bit 14)                                  */
36134 #define GPIO_MCUN1INT2SET_MCUN1GPIO78_Msk (0x4000UL)                /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
36135 #define GPIO_MCUN1INT2SET_MCUN1GPIO77_Pos (13UL)                    /*!< MCUN1GPIO77 (Bit 13)                                  */
36136 #define GPIO_MCUN1INT2SET_MCUN1GPIO77_Msk (0x2000UL)                /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
36137 #define GPIO_MCUN1INT2SET_MCUN1GPIO76_Pos (12UL)                    /*!< MCUN1GPIO76 (Bit 12)                                  */
36138 #define GPIO_MCUN1INT2SET_MCUN1GPIO76_Msk (0x1000UL)                /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
36139 #define GPIO_MCUN1INT2SET_MCUN1GPIO75_Pos (11UL)                    /*!< MCUN1GPIO75 (Bit 11)                                  */
36140 #define GPIO_MCUN1INT2SET_MCUN1GPIO75_Msk (0x800UL)                 /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
36141 #define GPIO_MCUN1INT2SET_MCUN1GPIO74_Pos (10UL)                    /*!< MCUN1GPIO74 (Bit 10)                                  */
36142 #define GPIO_MCUN1INT2SET_MCUN1GPIO74_Msk (0x400UL)                 /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
36143 #define GPIO_MCUN1INT2SET_MCUN1GPIO73_Pos (9UL)                     /*!< MCUN1GPIO73 (Bit 9)                                   */
36144 #define GPIO_MCUN1INT2SET_MCUN1GPIO73_Msk (0x200UL)                 /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
36145 #define GPIO_MCUN1INT2SET_MCUN1GPIO72_Pos (8UL)                     /*!< MCUN1GPIO72 (Bit 8)                                   */
36146 #define GPIO_MCUN1INT2SET_MCUN1GPIO72_Msk (0x100UL)                 /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
36147 #define GPIO_MCUN1INT2SET_MCUN1GPIO71_Pos (7UL)                     /*!< MCUN1GPIO71 (Bit 7)                                   */
36148 #define GPIO_MCUN1INT2SET_MCUN1GPIO71_Msk (0x80UL)                  /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
36149 #define GPIO_MCUN1INT2SET_MCUN1GPIO70_Pos (6UL)                     /*!< MCUN1GPIO70 (Bit 6)                                   */
36150 #define GPIO_MCUN1INT2SET_MCUN1GPIO70_Msk (0x40UL)                  /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
36151 #define GPIO_MCUN1INT2SET_MCUN1GPIO69_Pos (5UL)                     /*!< MCUN1GPIO69 (Bit 5)                                   */
36152 #define GPIO_MCUN1INT2SET_MCUN1GPIO69_Msk (0x20UL)                  /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
36153 #define GPIO_MCUN1INT2SET_MCUN1GPIO68_Pos (4UL)                     /*!< MCUN1GPIO68 (Bit 4)                                   */
36154 #define GPIO_MCUN1INT2SET_MCUN1GPIO68_Msk (0x10UL)                  /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
36155 #define GPIO_MCUN1INT2SET_MCUN1GPIO67_Pos (3UL)                     /*!< MCUN1GPIO67 (Bit 3)                                   */
36156 #define GPIO_MCUN1INT2SET_MCUN1GPIO67_Msk (0x8UL)                   /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
36157 #define GPIO_MCUN1INT2SET_MCUN1GPIO66_Pos (2UL)                     /*!< MCUN1GPIO66 (Bit 2)                                   */
36158 #define GPIO_MCUN1INT2SET_MCUN1GPIO66_Msk (0x4UL)                   /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
36159 #define GPIO_MCUN1INT2SET_MCUN1GPIO65_Pos (1UL)                     /*!< MCUN1GPIO65 (Bit 1)                                   */
36160 #define GPIO_MCUN1INT2SET_MCUN1GPIO65_Msk (0x2UL)                   /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
36161 #define GPIO_MCUN1INT2SET_MCUN1GPIO64_Pos (0UL)                     /*!< MCUN1GPIO64 (Bit 0)                                   */
36162 #define GPIO_MCUN1INT2SET_MCUN1GPIO64_Msk (0x1UL)                   /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
36163 /* ======================================================  MCUN1INT3EN  ====================================================== */
36164 #define GPIO_MCUN1INT3EN_MCUN1GPIO127_Pos (31UL)                    /*!< MCUN1GPIO127 (Bit 31)                                 */
36165 #define GPIO_MCUN1INT3EN_MCUN1GPIO127_Msk (0x80000000UL)            /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
36166 #define GPIO_MCUN1INT3EN_MCUN1GPIO126_Pos (30UL)                    /*!< MCUN1GPIO126 (Bit 30)                                 */
36167 #define GPIO_MCUN1INT3EN_MCUN1GPIO126_Msk (0x40000000UL)            /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
36168 #define GPIO_MCUN1INT3EN_MCUN1GPIO125_Pos (29UL)                    /*!< MCUN1GPIO125 (Bit 29)                                 */
36169 #define GPIO_MCUN1INT3EN_MCUN1GPIO125_Msk (0x20000000UL)            /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
36170 #define GPIO_MCUN1INT3EN_MCUN1GPIO124_Pos (28UL)                    /*!< MCUN1GPIO124 (Bit 28)                                 */
36171 #define GPIO_MCUN1INT3EN_MCUN1GPIO124_Msk (0x10000000UL)            /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
36172 #define GPIO_MCUN1INT3EN_MCUN1GPIO123_Pos (27UL)                    /*!< MCUN1GPIO123 (Bit 27)                                 */
36173 #define GPIO_MCUN1INT3EN_MCUN1GPIO123_Msk (0x8000000UL)             /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
36174 #define GPIO_MCUN1INT3EN_MCUN1GPIO122_Pos (26UL)                    /*!< MCUN1GPIO122 (Bit 26)                                 */
36175 #define GPIO_MCUN1INT3EN_MCUN1GPIO122_Msk (0x4000000UL)             /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
36176 #define GPIO_MCUN1INT3EN_MCUN1GPIO121_Pos (25UL)                    /*!< MCUN1GPIO121 (Bit 25)                                 */
36177 #define GPIO_MCUN1INT3EN_MCUN1GPIO121_Msk (0x2000000UL)             /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
36178 #define GPIO_MCUN1INT3EN_MCUN1GPIO120_Pos (24UL)                    /*!< MCUN1GPIO120 (Bit 24)                                 */
36179 #define GPIO_MCUN1INT3EN_MCUN1GPIO120_Msk (0x1000000UL)             /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
36180 #define GPIO_MCUN1INT3EN_MCUN1GPIO119_Pos (23UL)                    /*!< MCUN1GPIO119 (Bit 23)                                 */
36181 #define GPIO_MCUN1INT3EN_MCUN1GPIO119_Msk (0x800000UL)              /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
36182 #define GPIO_MCUN1INT3EN_MCUN1GPIO118_Pos (22UL)                    /*!< MCUN1GPIO118 (Bit 22)                                 */
36183 #define GPIO_MCUN1INT3EN_MCUN1GPIO118_Msk (0x400000UL)              /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
36184 #define GPIO_MCUN1INT3EN_MCUN1GPIO117_Pos (21UL)                    /*!< MCUN1GPIO117 (Bit 21)                                 */
36185 #define GPIO_MCUN1INT3EN_MCUN1GPIO117_Msk (0x200000UL)              /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
36186 #define GPIO_MCUN1INT3EN_MCUN1GPIO116_Pos (20UL)                    /*!< MCUN1GPIO116 (Bit 20)                                 */
36187 #define GPIO_MCUN1INT3EN_MCUN1GPIO116_Msk (0x100000UL)              /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
36188 #define GPIO_MCUN1INT3EN_MCUN1GPIO115_Pos (19UL)                    /*!< MCUN1GPIO115 (Bit 19)                                 */
36189 #define GPIO_MCUN1INT3EN_MCUN1GPIO115_Msk (0x80000UL)               /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
36190 #define GPIO_MCUN1INT3EN_MCUN1GPIO114_Pos (18UL)                    /*!< MCUN1GPIO114 (Bit 18)                                 */
36191 #define GPIO_MCUN1INT3EN_MCUN1GPIO114_Msk (0x40000UL)               /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
36192 #define GPIO_MCUN1INT3EN_MCUN1GPIO113_Pos (17UL)                    /*!< MCUN1GPIO113 (Bit 17)                                 */
36193 #define GPIO_MCUN1INT3EN_MCUN1GPIO113_Msk (0x20000UL)               /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
36194 #define GPIO_MCUN1INT3EN_MCUN1GPIO112_Pos (16UL)                    /*!< MCUN1GPIO112 (Bit 16)                                 */
36195 #define GPIO_MCUN1INT3EN_MCUN1GPIO112_Msk (0x10000UL)               /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
36196 #define GPIO_MCUN1INT3EN_MCUN1GPIO111_Pos (15UL)                    /*!< MCUN1GPIO111 (Bit 15)                                 */
36197 #define GPIO_MCUN1INT3EN_MCUN1GPIO111_Msk (0x8000UL)                /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
36198 #define GPIO_MCUN1INT3EN_MCUN1GPIO110_Pos (14UL)                    /*!< MCUN1GPIO110 (Bit 14)                                 */
36199 #define GPIO_MCUN1INT3EN_MCUN1GPIO110_Msk (0x4000UL)                /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
36200 #define GPIO_MCUN1INT3EN_MCUN1GPIO109_Pos (13UL)                    /*!< MCUN1GPIO109 (Bit 13)                                 */
36201 #define GPIO_MCUN1INT3EN_MCUN1GPIO109_Msk (0x2000UL)                /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
36202 #define GPIO_MCUN1INT3EN_MCUN1GPIO108_Pos (12UL)                    /*!< MCUN1GPIO108 (Bit 12)                                 */
36203 #define GPIO_MCUN1INT3EN_MCUN1GPIO108_Msk (0x1000UL)                /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
36204 #define GPIO_MCUN1INT3EN_MCUN1GPIO107_Pos (11UL)                    /*!< MCUN1GPIO107 (Bit 11)                                 */
36205 #define GPIO_MCUN1INT3EN_MCUN1GPIO107_Msk (0x800UL)                 /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
36206 #define GPIO_MCUN1INT3EN_MCUN1GPIO106_Pos (10UL)                    /*!< MCUN1GPIO106 (Bit 10)                                 */
36207 #define GPIO_MCUN1INT3EN_MCUN1GPIO106_Msk (0x400UL)                 /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
36208 #define GPIO_MCUN1INT3EN_MCUN1GPIO105_Pos (9UL)                     /*!< MCUN1GPIO105 (Bit 9)                                  */
36209 #define GPIO_MCUN1INT3EN_MCUN1GPIO105_Msk (0x200UL)                 /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
36210 #define GPIO_MCUN1INT3EN_MCUN1GPIO104_Pos (8UL)                     /*!< MCUN1GPIO104 (Bit 8)                                  */
36211 #define GPIO_MCUN1INT3EN_MCUN1GPIO104_Msk (0x100UL)                 /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
36212 #define GPIO_MCUN1INT3EN_MCUN1GPIO103_Pos (7UL)                     /*!< MCUN1GPIO103 (Bit 7)                                  */
36213 #define GPIO_MCUN1INT3EN_MCUN1GPIO103_Msk (0x80UL)                  /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
36214 #define GPIO_MCUN1INT3EN_MCUN1GPIO102_Pos (6UL)                     /*!< MCUN1GPIO102 (Bit 6)                                  */
36215 #define GPIO_MCUN1INT3EN_MCUN1GPIO102_Msk (0x40UL)                  /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
36216 #define GPIO_MCUN1INT3EN_MCUN1GPIO101_Pos (5UL)                     /*!< MCUN1GPIO101 (Bit 5)                                  */
36217 #define GPIO_MCUN1INT3EN_MCUN1GPIO101_Msk (0x20UL)                  /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
36218 #define GPIO_MCUN1INT3EN_MCUN1GPIO100_Pos (4UL)                     /*!< MCUN1GPIO100 (Bit 4)                                  */
36219 #define GPIO_MCUN1INT3EN_MCUN1GPIO100_Msk (0x10UL)                  /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
36220 #define GPIO_MCUN1INT3EN_MCUN1GPIO99_Pos  (3UL)                     /*!< MCUN1GPIO99 (Bit 3)                                   */
36221 #define GPIO_MCUN1INT3EN_MCUN1GPIO99_Msk  (0x8UL)                   /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
36222 #define GPIO_MCUN1INT3EN_MCUN1GPIO98_Pos  (2UL)                     /*!< MCUN1GPIO98 (Bit 2)                                   */
36223 #define GPIO_MCUN1INT3EN_MCUN1GPIO98_Msk  (0x4UL)                   /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
36224 #define GPIO_MCUN1INT3EN_MCUN1GPIO97_Pos  (1UL)                     /*!< MCUN1GPIO97 (Bit 1)                                   */
36225 #define GPIO_MCUN1INT3EN_MCUN1GPIO97_Msk  (0x2UL)                   /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
36226 #define GPIO_MCUN1INT3EN_MCUN1GPIO96_Pos  (0UL)                     /*!< MCUN1GPIO96 (Bit 0)                                   */
36227 #define GPIO_MCUN1INT3EN_MCUN1GPIO96_Msk  (0x1UL)                   /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
36228 /* =====================================================  MCUN1INT3STAT  ===================================================== */
36229 #define GPIO_MCUN1INT3STAT_MCUN1GPIO127_Pos (31UL)                  /*!< MCUN1GPIO127 (Bit 31)                                 */
36230 #define GPIO_MCUN1INT3STAT_MCUN1GPIO127_Msk (0x80000000UL)          /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
36231 #define GPIO_MCUN1INT3STAT_MCUN1GPIO126_Pos (30UL)                  /*!< MCUN1GPIO126 (Bit 30)                                 */
36232 #define GPIO_MCUN1INT3STAT_MCUN1GPIO126_Msk (0x40000000UL)          /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
36233 #define GPIO_MCUN1INT3STAT_MCUN1GPIO125_Pos (29UL)                  /*!< MCUN1GPIO125 (Bit 29)                                 */
36234 #define GPIO_MCUN1INT3STAT_MCUN1GPIO125_Msk (0x20000000UL)          /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
36235 #define GPIO_MCUN1INT3STAT_MCUN1GPIO124_Pos (28UL)                  /*!< MCUN1GPIO124 (Bit 28)                                 */
36236 #define GPIO_MCUN1INT3STAT_MCUN1GPIO124_Msk (0x10000000UL)          /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
36237 #define GPIO_MCUN1INT3STAT_MCUN1GPIO123_Pos (27UL)                  /*!< MCUN1GPIO123 (Bit 27)                                 */
36238 #define GPIO_MCUN1INT3STAT_MCUN1GPIO123_Msk (0x8000000UL)           /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
36239 #define GPIO_MCUN1INT3STAT_MCUN1GPIO122_Pos (26UL)                  /*!< MCUN1GPIO122 (Bit 26)                                 */
36240 #define GPIO_MCUN1INT3STAT_MCUN1GPIO122_Msk (0x4000000UL)           /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
36241 #define GPIO_MCUN1INT3STAT_MCUN1GPIO121_Pos (25UL)                  /*!< MCUN1GPIO121 (Bit 25)                                 */
36242 #define GPIO_MCUN1INT3STAT_MCUN1GPIO121_Msk (0x2000000UL)           /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
36243 #define GPIO_MCUN1INT3STAT_MCUN1GPIO120_Pos (24UL)                  /*!< MCUN1GPIO120 (Bit 24)                                 */
36244 #define GPIO_MCUN1INT3STAT_MCUN1GPIO120_Msk (0x1000000UL)           /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
36245 #define GPIO_MCUN1INT3STAT_MCUN1GPIO119_Pos (23UL)                  /*!< MCUN1GPIO119 (Bit 23)                                 */
36246 #define GPIO_MCUN1INT3STAT_MCUN1GPIO119_Msk (0x800000UL)            /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
36247 #define GPIO_MCUN1INT3STAT_MCUN1GPIO118_Pos (22UL)                  /*!< MCUN1GPIO118 (Bit 22)                                 */
36248 #define GPIO_MCUN1INT3STAT_MCUN1GPIO118_Msk (0x400000UL)            /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
36249 #define GPIO_MCUN1INT3STAT_MCUN1GPIO117_Pos (21UL)                  /*!< MCUN1GPIO117 (Bit 21)                                 */
36250 #define GPIO_MCUN1INT3STAT_MCUN1GPIO117_Msk (0x200000UL)            /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
36251 #define GPIO_MCUN1INT3STAT_MCUN1GPIO116_Pos (20UL)                  /*!< MCUN1GPIO116 (Bit 20)                                 */
36252 #define GPIO_MCUN1INT3STAT_MCUN1GPIO116_Msk (0x100000UL)            /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
36253 #define GPIO_MCUN1INT3STAT_MCUN1GPIO115_Pos (19UL)                  /*!< MCUN1GPIO115 (Bit 19)                                 */
36254 #define GPIO_MCUN1INT3STAT_MCUN1GPIO115_Msk (0x80000UL)             /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
36255 #define GPIO_MCUN1INT3STAT_MCUN1GPIO114_Pos (18UL)                  /*!< MCUN1GPIO114 (Bit 18)                                 */
36256 #define GPIO_MCUN1INT3STAT_MCUN1GPIO114_Msk (0x40000UL)             /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
36257 #define GPIO_MCUN1INT3STAT_MCUN1GPIO113_Pos (17UL)                  /*!< MCUN1GPIO113 (Bit 17)                                 */
36258 #define GPIO_MCUN1INT3STAT_MCUN1GPIO113_Msk (0x20000UL)             /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
36259 #define GPIO_MCUN1INT3STAT_MCUN1GPIO112_Pos (16UL)                  /*!< MCUN1GPIO112 (Bit 16)                                 */
36260 #define GPIO_MCUN1INT3STAT_MCUN1GPIO112_Msk (0x10000UL)             /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
36261 #define GPIO_MCUN1INT3STAT_MCUN1GPIO111_Pos (15UL)                  /*!< MCUN1GPIO111 (Bit 15)                                 */
36262 #define GPIO_MCUN1INT3STAT_MCUN1GPIO111_Msk (0x8000UL)              /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
36263 #define GPIO_MCUN1INT3STAT_MCUN1GPIO110_Pos (14UL)                  /*!< MCUN1GPIO110 (Bit 14)                                 */
36264 #define GPIO_MCUN1INT3STAT_MCUN1GPIO110_Msk (0x4000UL)              /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
36265 #define GPIO_MCUN1INT3STAT_MCUN1GPIO109_Pos (13UL)                  /*!< MCUN1GPIO109 (Bit 13)                                 */
36266 #define GPIO_MCUN1INT3STAT_MCUN1GPIO109_Msk (0x2000UL)              /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
36267 #define GPIO_MCUN1INT3STAT_MCUN1GPIO108_Pos (12UL)                  /*!< MCUN1GPIO108 (Bit 12)                                 */
36268 #define GPIO_MCUN1INT3STAT_MCUN1GPIO108_Msk (0x1000UL)              /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
36269 #define GPIO_MCUN1INT3STAT_MCUN1GPIO107_Pos (11UL)                  /*!< MCUN1GPIO107 (Bit 11)                                 */
36270 #define GPIO_MCUN1INT3STAT_MCUN1GPIO107_Msk (0x800UL)               /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
36271 #define GPIO_MCUN1INT3STAT_MCUN1GPIO106_Pos (10UL)                  /*!< MCUN1GPIO106 (Bit 10)                                 */
36272 #define GPIO_MCUN1INT3STAT_MCUN1GPIO106_Msk (0x400UL)               /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
36273 #define GPIO_MCUN1INT3STAT_MCUN1GPIO105_Pos (9UL)                   /*!< MCUN1GPIO105 (Bit 9)                                  */
36274 #define GPIO_MCUN1INT3STAT_MCUN1GPIO105_Msk (0x200UL)               /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
36275 #define GPIO_MCUN1INT3STAT_MCUN1GPIO104_Pos (8UL)                   /*!< MCUN1GPIO104 (Bit 8)                                  */
36276 #define GPIO_MCUN1INT3STAT_MCUN1GPIO104_Msk (0x100UL)               /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
36277 #define GPIO_MCUN1INT3STAT_MCUN1GPIO103_Pos (7UL)                   /*!< MCUN1GPIO103 (Bit 7)                                  */
36278 #define GPIO_MCUN1INT3STAT_MCUN1GPIO103_Msk (0x80UL)                /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
36279 #define GPIO_MCUN1INT3STAT_MCUN1GPIO102_Pos (6UL)                   /*!< MCUN1GPIO102 (Bit 6)                                  */
36280 #define GPIO_MCUN1INT3STAT_MCUN1GPIO102_Msk (0x40UL)                /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
36281 #define GPIO_MCUN1INT3STAT_MCUN1GPIO101_Pos (5UL)                   /*!< MCUN1GPIO101 (Bit 5)                                  */
36282 #define GPIO_MCUN1INT3STAT_MCUN1GPIO101_Msk (0x20UL)                /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
36283 #define GPIO_MCUN1INT3STAT_MCUN1GPIO100_Pos (4UL)                   /*!< MCUN1GPIO100 (Bit 4)                                  */
36284 #define GPIO_MCUN1INT3STAT_MCUN1GPIO100_Msk (0x10UL)                /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
36285 #define GPIO_MCUN1INT3STAT_MCUN1GPIO99_Pos (3UL)                    /*!< MCUN1GPIO99 (Bit 3)                                   */
36286 #define GPIO_MCUN1INT3STAT_MCUN1GPIO99_Msk (0x8UL)                  /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
36287 #define GPIO_MCUN1INT3STAT_MCUN1GPIO98_Pos (2UL)                    /*!< MCUN1GPIO98 (Bit 2)                                   */
36288 #define GPIO_MCUN1INT3STAT_MCUN1GPIO98_Msk (0x4UL)                  /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
36289 #define GPIO_MCUN1INT3STAT_MCUN1GPIO97_Pos (1UL)                    /*!< MCUN1GPIO97 (Bit 1)                                   */
36290 #define GPIO_MCUN1INT3STAT_MCUN1GPIO97_Msk (0x2UL)                  /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
36291 #define GPIO_MCUN1INT3STAT_MCUN1GPIO96_Pos (0UL)                    /*!< MCUN1GPIO96 (Bit 0)                                   */
36292 #define GPIO_MCUN1INT3STAT_MCUN1GPIO96_Msk (0x1UL)                  /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
36293 /* =====================================================  MCUN1INT3CLR  ====================================================== */
36294 #define GPIO_MCUN1INT3CLR_MCUN1GPIO127_Pos (31UL)                   /*!< MCUN1GPIO127 (Bit 31)                                 */
36295 #define GPIO_MCUN1INT3CLR_MCUN1GPIO127_Msk (0x80000000UL)           /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
36296 #define GPIO_MCUN1INT3CLR_MCUN1GPIO126_Pos (30UL)                   /*!< MCUN1GPIO126 (Bit 30)                                 */
36297 #define GPIO_MCUN1INT3CLR_MCUN1GPIO126_Msk (0x40000000UL)           /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
36298 #define GPIO_MCUN1INT3CLR_MCUN1GPIO125_Pos (29UL)                   /*!< MCUN1GPIO125 (Bit 29)                                 */
36299 #define GPIO_MCUN1INT3CLR_MCUN1GPIO125_Msk (0x20000000UL)           /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
36300 #define GPIO_MCUN1INT3CLR_MCUN1GPIO124_Pos (28UL)                   /*!< MCUN1GPIO124 (Bit 28)                                 */
36301 #define GPIO_MCUN1INT3CLR_MCUN1GPIO124_Msk (0x10000000UL)           /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
36302 #define GPIO_MCUN1INT3CLR_MCUN1GPIO123_Pos (27UL)                   /*!< MCUN1GPIO123 (Bit 27)                                 */
36303 #define GPIO_MCUN1INT3CLR_MCUN1GPIO123_Msk (0x8000000UL)            /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
36304 #define GPIO_MCUN1INT3CLR_MCUN1GPIO122_Pos (26UL)                   /*!< MCUN1GPIO122 (Bit 26)                                 */
36305 #define GPIO_MCUN1INT3CLR_MCUN1GPIO122_Msk (0x4000000UL)            /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
36306 #define GPIO_MCUN1INT3CLR_MCUN1GPIO121_Pos (25UL)                   /*!< MCUN1GPIO121 (Bit 25)                                 */
36307 #define GPIO_MCUN1INT3CLR_MCUN1GPIO121_Msk (0x2000000UL)            /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
36308 #define GPIO_MCUN1INT3CLR_MCUN1GPIO120_Pos (24UL)                   /*!< MCUN1GPIO120 (Bit 24)                                 */
36309 #define GPIO_MCUN1INT3CLR_MCUN1GPIO120_Msk (0x1000000UL)            /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
36310 #define GPIO_MCUN1INT3CLR_MCUN1GPIO119_Pos (23UL)                   /*!< MCUN1GPIO119 (Bit 23)                                 */
36311 #define GPIO_MCUN1INT3CLR_MCUN1GPIO119_Msk (0x800000UL)             /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
36312 #define GPIO_MCUN1INT3CLR_MCUN1GPIO118_Pos (22UL)                   /*!< MCUN1GPIO118 (Bit 22)                                 */
36313 #define GPIO_MCUN1INT3CLR_MCUN1GPIO118_Msk (0x400000UL)             /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
36314 #define GPIO_MCUN1INT3CLR_MCUN1GPIO117_Pos (21UL)                   /*!< MCUN1GPIO117 (Bit 21)                                 */
36315 #define GPIO_MCUN1INT3CLR_MCUN1GPIO117_Msk (0x200000UL)             /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
36316 #define GPIO_MCUN1INT3CLR_MCUN1GPIO116_Pos (20UL)                   /*!< MCUN1GPIO116 (Bit 20)                                 */
36317 #define GPIO_MCUN1INT3CLR_MCUN1GPIO116_Msk (0x100000UL)             /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
36318 #define GPIO_MCUN1INT3CLR_MCUN1GPIO115_Pos (19UL)                   /*!< MCUN1GPIO115 (Bit 19)                                 */
36319 #define GPIO_MCUN1INT3CLR_MCUN1GPIO115_Msk (0x80000UL)              /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
36320 #define GPIO_MCUN1INT3CLR_MCUN1GPIO114_Pos (18UL)                   /*!< MCUN1GPIO114 (Bit 18)                                 */
36321 #define GPIO_MCUN1INT3CLR_MCUN1GPIO114_Msk (0x40000UL)              /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
36322 #define GPIO_MCUN1INT3CLR_MCUN1GPIO113_Pos (17UL)                   /*!< MCUN1GPIO113 (Bit 17)                                 */
36323 #define GPIO_MCUN1INT3CLR_MCUN1GPIO113_Msk (0x20000UL)              /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
36324 #define GPIO_MCUN1INT3CLR_MCUN1GPIO112_Pos (16UL)                   /*!< MCUN1GPIO112 (Bit 16)                                 */
36325 #define GPIO_MCUN1INT3CLR_MCUN1GPIO112_Msk (0x10000UL)              /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
36326 #define GPIO_MCUN1INT3CLR_MCUN1GPIO111_Pos (15UL)                   /*!< MCUN1GPIO111 (Bit 15)                                 */
36327 #define GPIO_MCUN1INT3CLR_MCUN1GPIO111_Msk (0x8000UL)               /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
36328 #define GPIO_MCUN1INT3CLR_MCUN1GPIO110_Pos (14UL)                   /*!< MCUN1GPIO110 (Bit 14)                                 */
36329 #define GPIO_MCUN1INT3CLR_MCUN1GPIO110_Msk (0x4000UL)               /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
36330 #define GPIO_MCUN1INT3CLR_MCUN1GPIO109_Pos (13UL)                   /*!< MCUN1GPIO109 (Bit 13)                                 */
36331 #define GPIO_MCUN1INT3CLR_MCUN1GPIO109_Msk (0x2000UL)               /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
36332 #define GPIO_MCUN1INT3CLR_MCUN1GPIO108_Pos (12UL)                   /*!< MCUN1GPIO108 (Bit 12)                                 */
36333 #define GPIO_MCUN1INT3CLR_MCUN1GPIO108_Msk (0x1000UL)               /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
36334 #define GPIO_MCUN1INT3CLR_MCUN1GPIO107_Pos (11UL)                   /*!< MCUN1GPIO107 (Bit 11)                                 */
36335 #define GPIO_MCUN1INT3CLR_MCUN1GPIO107_Msk (0x800UL)                /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
36336 #define GPIO_MCUN1INT3CLR_MCUN1GPIO106_Pos (10UL)                   /*!< MCUN1GPIO106 (Bit 10)                                 */
36337 #define GPIO_MCUN1INT3CLR_MCUN1GPIO106_Msk (0x400UL)                /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
36338 #define GPIO_MCUN1INT3CLR_MCUN1GPIO105_Pos (9UL)                    /*!< MCUN1GPIO105 (Bit 9)                                  */
36339 #define GPIO_MCUN1INT3CLR_MCUN1GPIO105_Msk (0x200UL)                /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
36340 #define GPIO_MCUN1INT3CLR_MCUN1GPIO104_Pos (8UL)                    /*!< MCUN1GPIO104 (Bit 8)                                  */
36341 #define GPIO_MCUN1INT3CLR_MCUN1GPIO104_Msk (0x100UL)                /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
36342 #define GPIO_MCUN1INT3CLR_MCUN1GPIO103_Pos (7UL)                    /*!< MCUN1GPIO103 (Bit 7)                                  */
36343 #define GPIO_MCUN1INT3CLR_MCUN1GPIO103_Msk (0x80UL)                 /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
36344 #define GPIO_MCUN1INT3CLR_MCUN1GPIO102_Pos (6UL)                    /*!< MCUN1GPIO102 (Bit 6)                                  */
36345 #define GPIO_MCUN1INT3CLR_MCUN1GPIO102_Msk (0x40UL)                 /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
36346 #define GPIO_MCUN1INT3CLR_MCUN1GPIO101_Pos (5UL)                    /*!< MCUN1GPIO101 (Bit 5)                                  */
36347 #define GPIO_MCUN1INT3CLR_MCUN1GPIO101_Msk (0x20UL)                 /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
36348 #define GPIO_MCUN1INT3CLR_MCUN1GPIO100_Pos (4UL)                    /*!< MCUN1GPIO100 (Bit 4)                                  */
36349 #define GPIO_MCUN1INT3CLR_MCUN1GPIO100_Msk (0x10UL)                 /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
36350 #define GPIO_MCUN1INT3CLR_MCUN1GPIO99_Pos (3UL)                     /*!< MCUN1GPIO99 (Bit 3)                                   */
36351 #define GPIO_MCUN1INT3CLR_MCUN1GPIO99_Msk (0x8UL)                   /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
36352 #define GPIO_MCUN1INT3CLR_MCUN1GPIO98_Pos (2UL)                     /*!< MCUN1GPIO98 (Bit 2)                                   */
36353 #define GPIO_MCUN1INT3CLR_MCUN1GPIO98_Msk (0x4UL)                   /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
36354 #define GPIO_MCUN1INT3CLR_MCUN1GPIO97_Pos (1UL)                     /*!< MCUN1GPIO97 (Bit 1)                                   */
36355 #define GPIO_MCUN1INT3CLR_MCUN1GPIO97_Msk (0x2UL)                   /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
36356 #define GPIO_MCUN1INT3CLR_MCUN1GPIO96_Pos (0UL)                     /*!< MCUN1GPIO96 (Bit 0)                                   */
36357 #define GPIO_MCUN1INT3CLR_MCUN1GPIO96_Msk (0x1UL)                   /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
36358 /* =====================================================  MCUN1INT3SET  ====================================================== */
36359 #define GPIO_MCUN1INT3SET_MCUN1GPIO127_Pos (31UL)                   /*!< MCUN1GPIO127 (Bit 31)                                 */
36360 #define GPIO_MCUN1INT3SET_MCUN1GPIO127_Msk (0x80000000UL)           /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
36361 #define GPIO_MCUN1INT3SET_MCUN1GPIO126_Pos (30UL)                   /*!< MCUN1GPIO126 (Bit 30)                                 */
36362 #define GPIO_MCUN1INT3SET_MCUN1GPIO126_Msk (0x40000000UL)           /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
36363 #define GPIO_MCUN1INT3SET_MCUN1GPIO125_Pos (29UL)                   /*!< MCUN1GPIO125 (Bit 29)                                 */
36364 #define GPIO_MCUN1INT3SET_MCUN1GPIO125_Msk (0x20000000UL)           /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
36365 #define GPIO_MCUN1INT3SET_MCUN1GPIO124_Pos (28UL)                   /*!< MCUN1GPIO124 (Bit 28)                                 */
36366 #define GPIO_MCUN1INT3SET_MCUN1GPIO124_Msk (0x10000000UL)           /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
36367 #define GPIO_MCUN1INT3SET_MCUN1GPIO123_Pos (27UL)                   /*!< MCUN1GPIO123 (Bit 27)                                 */
36368 #define GPIO_MCUN1INT3SET_MCUN1GPIO123_Msk (0x8000000UL)            /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
36369 #define GPIO_MCUN1INT3SET_MCUN1GPIO122_Pos (26UL)                   /*!< MCUN1GPIO122 (Bit 26)                                 */
36370 #define GPIO_MCUN1INT3SET_MCUN1GPIO122_Msk (0x4000000UL)            /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
36371 #define GPIO_MCUN1INT3SET_MCUN1GPIO121_Pos (25UL)                   /*!< MCUN1GPIO121 (Bit 25)                                 */
36372 #define GPIO_MCUN1INT3SET_MCUN1GPIO121_Msk (0x2000000UL)            /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
36373 #define GPIO_MCUN1INT3SET_MCUN1GPIO120_Pos (24UL)                   /*!< MCUN1GPIO120 (Bit 24)                                 */
36374 #define GPIO_MCUN1INT3SET_MCUN1GPIO120_Msk (0x1000000UL)            /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
36375 #define GPIO_MCUN1INT3SET_MCUN1GPIO119_Pos (23UL)                   /*!< MCUN1GPIO119 (Bit 23)                                 */
36376 #define GPIO_MCUN1INT3SET_MCUN1GPIO119_Msk (0x800000UL)             /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
36377 #define GPIO_MCUN1INT3SET_MCUN1GPIO118_Pos (22UL)                   /*!< MCUN1GPIO118 (Bit 22)                                 */
36378 #define GPIO_MCUN1INT3SET_MCUN1GPIO118_Msk (0x400000UL)             /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
36379 #define GPIO_MCUN1INT3SET_MCUN1GPIO117_Pos (21UL)                   /*!< MCUN1GPIO117 (Bit 21)                                 */
36380 #define GPIO_MCUN1INT3SET_MCUN1GPIO117_Msk (0x200000UL)             /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
36381 #define GPIO_MCUN1INT3SET_MCUN1GPIO116_Pos (20UL)                   /*!< MCUN1GPIO116 (Bit 20)                                 */
36382 #define GPIO_MCUN1INT3SET_MCUN1GPIO116_Msk (0x100000UL)             /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
36383 #define GPIO_MCUN1INT3SET_MCUN1GPIO115_Pos (19UL)                   /*!< MCUN1GPIO115 (Bit 19)                                 */
36384 #define GPIO_MCUN1INT3SET_MCUN1GPIO115_Msk (0x80000UL)              /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
36385 #define GPIO_MCUN1INT3SET_MCUN1GPIO114_Pos (18UL)                   /*!< MCUN1GPIO114 (Bit 18)                                 */
36386 #define GPIO_MCUN1INT3SET_MCUN1GPIO114_Msk (0x40000UL)              /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
36387 #define GPIO_MCUN1INT3SET_MCUN1GPIO113_Pos (17UL)                   /*!< MCUN1GPIO113 (Bit 17)                                 */
36388 #define GPIO_MCUN1INT3SET_MCUN1GPIO113_Msk (0x20000UL)              /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
36389 #define GPIO_MCUN1INT3SET_MCUN1GPIO112_Pos (16UL)                   /*!< MCUN1GPIO112 (Bit 16)                                 */
36390 #define GPIO_MCUN1INT3SET_MCUN1GPIO112_Msk (0x10000UL)              /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
36391 #define GPIO_MCUN1INT3SET_MCUN1GPIO111_Pos (15UL)                   /*!< MCUN1GPIO111 (Bit 15)                                 */
36392 #define GPIO_MCUN1INT3SET_MCUN1GPIO111_Msk (0x8000UL)               /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
36393 #define GPIO_MCUN1INT3SET_MCUN1GPIO110_Pos (14UL)                   /*!< MCUN1GPIO110 (Bit 14)                                 */
36394 #define GPIO_MCUN1INT3SET_MCUN1GPIO110_Msk (0x4000UL)               /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
36395 #define GPIO_MCUN1INT3SET_MCUN1GPIO109_Pos (13UL)                   /*!< MCUN1GPIO109 (Bit 13)                                 */
36396 #define GPIO_MCUN1INT3SET_MCUN1GPIO109_Msk (0x2000UL)               /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
36397 #define GPIO_MCUN1INT3SET_MCUN1GPIO108_Pos (12UL)                   /*!< MCUN1GPIO108 (Bit 12)                                 */
36398 #define GPIO_MCUN1INT3SET_MCUN1GPIO108_Msk (0x1000UL)               /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
36399 #define GPIO_MCUN1INT3SET_MCUN1GPIO107_Pos (11UL)                   /*!< MCUN1GPIO107 (Bit 11)                                 */
36400 #define GPIO_MCUN1INT3SET_MCUN1GPIO107_Msk (0x800UL)                /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
36401 #define GPIO_MCUN1INT3SET_MCUN1GPIO106_Pos (10UL)                   /*!< MCUN1GPIO106 (Bit 10)                                 */
36402 #define GPIO_MCUN1INT3SET_MCUN1GPIO106_Msk (0x400UL)                /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
36403 #define GPIO_MCUN1INT3SET_MCUN1GPIO105_Pos (9UL)                    /*!< MCUN1GPIO105 (Bit 9)                                  */
36404 #define GPIO_MCUN1INT3SET_MCUN1GPIO105_Msk (0x200UL)                /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
36405 #define GPIO_MCUN1INT3SET_MCUN1GPIO104_Pos (8UL)                    /*!< MCUN1GPIO104 (Bit 8)                                  */
36406 #define GPIO_MCUN1INT3SET_MCUN1GPIO104_Msk (0x100UL)                /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
36407 #define GPIO_MCUN1INT3SET_MCUN1GPIO103_Pos (7UL)                    /*!< MCUN1GPIO103 (Bit 7)                                  */
36408 #define GPIO_MCUN1INT3SET_MCUN1GPIO103_Msk (0x80UL)                 /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
36409 #define GPIO_MCUN1INT3SET_MCUN1GPIO102_Pos (6UL)                    /*!< MCUN1GPIO102 (Bit 6)                                  */
36410 #define GPIO_MCUN1INT3SET_MCUN1GPIO102_Msk (0x40UL)                 /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
36411 #define GPIO_MCUN1INT3SET_MCUN1GPIO101_Pos (5UL)                    /*!< MCUN1GPIO101 (Bit 5)                                  */
36412 #define GPIO_MCUN1INT3SET_MCUN1GPIO101_Msk (0x20UL)                 /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
36413 #define GPIO_MCUN1INT3SET_MCUN1GPIO100_Pos (4UL)                    /*!< MCUN1GPIO100 (Bit 4)                                  */
36414 #define GPIO_MCUN1INT3SET_MCUN1GPIO100_Msk (0x10UL)                 /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
36415 #define GPIO_MCUN1INT3SET_MCUN1GPIO99_Pos (3UL)                     /*!< MCUN1GPIO99 (Bit 3)                                   */
36416 #define GPIO_MCUN1INT3SET_MCUN1GPIO99_Msk (0x8UL)                   /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
36417 #define GPIO_MCUN1INT3SET_MCUN1GPIO98_Pos (2UL)                     /*!< MCUN1GPIO98 (Bit 2)                                   */
36418 #define GPIO_MCUN1INT3SET_MCUN1GPIO98_Msk (0x4UL)                   /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
36419 #define GPIO_MCUN1INT3SET_MCUN1GPIO97_Pos (1UL)                     /*!< MCUN1GPIO97 (Bit 1)                                   */
36420 #define GPIO_MCUN1INT3SET_MCUN1GPIO97_Msk (0x2UL)                   /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
36421 #define GPIO_MCUN1INT3SET_MCUN1GPIO96_Pos (0UL)                     /*!< MCUN1GPIO96 (Bit 0)                                   */
36422 #define GPIO_MCUN1INT3SET_MCUN1GPIO96_Msk (0x1UL)                   /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
36423 /* =====================================================  DSP0N0INT0EN  ====================================================== */
36424 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO31_Pos (31UL)                   /*!< DSP0N0GPIO31 (Bit 31)                                 */
36425 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO31_Msk (0x80000000UL)           /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
36426 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO30_Pos (30UL)                   /*!< DSP0N0GPIO30 (Bit 30)                                 */
36427 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO30_Msk (0x40000000UL)           /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
36428 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO29_Pos (29UL)                   /*!< DSP0N0GPIO29 (Bit 29)                                 */
36429 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO29_Msk (0x20000000UL)           /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
36430 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO28_Pos (28UL)                   /*!< DSP0N0GPIO28 (Bit 28)                                 */
36431 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO28_Msk (0x10000000UL)           /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
36432 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO27_Pos (27UL)                   /*!< DSP0N0GPIO27 (Bit 27)                                 */
36433 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO27_Msk (0x8000000UL)            /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
36434 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO26_Pos (26UL)                   /*!< DSP0N0GPIO26 (Bit 26)                                 */
36435 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO26_Msk (0x4000000UL)            /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
36436 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO25_Pos (25UL)                   /*!< DSP0N0GPIO25 (Bit 25)                                 */
36437 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO25_Msk (0x2000000UL)            /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
36438 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO24_Pos (24UL)                   /*!< DSP0N0GPIO24 (Bit 24)                                 */
36439 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO24_Msk (0x1000000UL)            /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
36440 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO23_Pos (23UL)                   /*!< DSP0N0GPIO23 (Bit 23)                                 */
36441 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO23_Msk (0x800000UL)             /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
36442 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO22_Pos (22UL)                   /*!< DSP0N0GPIO22 (Bit 22)                                 */
36443 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO22_Msk (0x400000UL)             /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
36444 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO21_Pos (21UL)                   /*!< DSP0N0GPIO21 (Bit 21)                                 */
36445 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO21_Msk (0x200000UL)             /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
36446 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO20_Pos (20UL)                   /*!< DSP0N0GPIO20 (Bit 20)                                 */
36447 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO20_Msk (0x100000UL)             /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
36448 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO19_Pos (19UL)                   /*!< DSP0N0GPIO19 (Bit 19)                                 */
36449 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO19_Msk (0x80000UL)              /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
36450 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO18_Pos (18UL)                   /*!< DSP0N0GPIO18 (Bit 18)                                 */
36451 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO18_Msk (0x40000UL)              /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
36452 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO17_Pos (17UL)                   /*!< DSP0N0GPIO17 (Bit 17)                                 */
36453 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO17_Msk (0x20000UL)              /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
36454 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO16_Pos (16UL)                   /*!< DSP0N0GPIO16 (Bit 16)                                 */
36455 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO16_Msk (0x10000UL)              /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
36456 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO15_Pos (15UL)                   /*!< DSP0N0GPIO15 (Bit 15)                                 */
36457 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO15_Msk (0x8000UL)               /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
36458 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO14_Pos (14UL)                   /*!< DSP0N0GPIO14 (Bit 14)                                 */
36459 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO14_Msk (0x4000UL)               /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
36460 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO13_Pos (13UL)                   /*!< DSP0N0GPIO13 (Bit 13)                                 */
36461 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO13_Msk (0x2000UL)               /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
36462 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO12_Pos (12UL)                   /*!< DSP0N0GPIO12 (Bit 12)                                 */
36463 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO12_Msk (0x1000UL)               /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
36464 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO11_Pos (11UL)                   /*!< DSP0N0GPIO11 (Bit 11)                                 */
36465 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO11_Msk (0x800UL)                /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
36466 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO10_Pos (10UL)                   /*!< DSP0N0GPIO10 (Bit 10)                                 */
36467 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO10_Msk (0x400UL)                /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
36468 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO9_Pos (9UL)                     /*!< DSP0N0GPIO9 (Bit 9)                                   */
36469 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO9_Msk (0x200UL)                 /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
36470 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO8_Pos (8UL)                     /*!< DSP0N0GPIO8 (Bit 8)                                   */
36471 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO8_Msk (0x100UL)                 /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
36472 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO7_Pos (7UL)                     /*!< DSP0N0GPIO7 (Bit 7)                                   */
36473 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO7_Msk (0x80UL)                  /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
36474 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO6_Pos (6UL)                     /*!< DSP0N0GPIO6 (Bit 6)                                   */
36475 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO6_Msk (0x40UL)                  /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
36476 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO5_Pos (5UL)                     /*!< DSP0N0GPIO5 (Bit 5)                                   */
36477 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO5_Msk (0x20UL)                  /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
36478 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO4_Pos (4UL)                     /*!< DSP0N0GPIO4 (Bit 4)                                   */
36479 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO4_Msk (0x10UL)                  /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
36480 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO3_Pos (3UL)                     /*!< DSP0N0GPIO3 (Bit 3)                                   */
36481 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO3_Msk (0x8UL)                   /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
36482 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO2_Pos (2UL)                     /*!< DSP0N0GPIO2 (Bit 2)                                   */
36483 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO2_Msk (0x4UL)                   /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
36484 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO1_Pos (1UL)                     /*!< DSP0N0GPIO1 (Bit 1)                                   */
36485 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO1_Msk (0x2UL)                   /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
36486 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO0_Pos (0UL)                     /*!< DSP0N0GPIO0 (Bit 0)                                   */
36487 #define GPIO_DSP0N0INT0EN_DSP0N0GPIO0_Msk (0x1UL)                   /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
36488 /* ====================================================  DSP0N0INT0STAT  ===================================================== */
36489 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO31_Pos (31UL)                 /*!< DSP0N0GPIO31 (Bit 31)                                 */
36490 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO31_Msk (0x80000000UL)         /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
36491 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO30_Pos (30UL)                 /*!< DSP0N0GPIO30 (Bit 30)                                 */
36492 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO30_Msk (0x40000000UL)         /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
36493 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO29_Pos (29UL)                 /*!< DSP0N0GPIO29 (Bit 29)                                 */
36494 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO29_Msk (0x20000000UL)         /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
36495 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO28_Pos (28UL)                 /*!< DSP0N0GPIO28 (Bit 28)                                 */
36496 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO28_Msk (0x10000000UL)         /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
36497 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO27_Pos (27UL)                 /*!< DSP0N0GPIO27 (Bit 27)                                 */
36498 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO27_Msk (0x8000000UL)          /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
36499 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO26_Pos (26UL)                 /*!< DSP0N0GPIO26 (Bit 26)                                 */
36500 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO26_Msk (0x4000000UL)          /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
36501 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO25_Pos (25UL)                 /*!< DSP0N0GPIO25 (Bit 25)                                 */
36502 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO25_Msk (0x2000000UL)          /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
36503 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO24_Pos (24UL)                 /*!< DSP0N0GPIO24 (Bit 24)                                 */
36504 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO24_Msk (0x1000000UL)          /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
36505 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO23_Pos (23UL)                 /*!< DSP0N0GPIO23 (Bit 23)                                 */
36506 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO23_Msk (0x800000UL)           /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
36507 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO22_Pos (22UL)                 /*!< DSP0N0GPIO22 (Bit 22)                                 */
36508 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO22_Msk (0x400000UL)           /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
36509 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO21_Pos (21UL)                 /*!< DSP0N0GPIO21 (Bit 21)                                 */
36510 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO21_Msk (0x200000UL)           /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
36511 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO20_Pos (20UL)                 /*!< DSP0N0GPIO20 (Bit 20)                                 */
36512 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO20_Msk (0x100000UL)           /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
36513 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO19_Pos (19UL)                 /*!< DSP0N0GPIO19 (Bit 19)                                 */
36514 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO19_Msk (0x80000UL)            /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
36515 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO18_Pos (18UL)                 /*!< DSP0N0GPIO18 (Bit 18)                                 */
36516 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO18_Msk (0x40000UL)            /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
36517 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO17_Pos (17UL)                 /*!< DSP0N0GPIO17 (Bit 17)                                 */
36518 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO17_Msk (0x20000UL)            /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
36519 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO16_Pos (16UL)                 /*!< DSP0N0GPIO16 (Bit 16)                                 */
36520 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO16_Msk (0x10000UL)            /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
36521 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO15_Pos (15UL)                 /*!< DSP0N0GPIO15 (Bit 15)                                 */
36522 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO15_Msk (0x8000UL)             /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
36523 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO14_Pos (14UL)                 /*!< DSP0N0GPIO14 (Bit 14)                                 */
36524 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO14_Msk (0x4000UL)             /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
36525 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO13_Pos (13UL)                 /*!< DSP0N0GPIO13 (Bit 13)                                 */
36526 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO13_Msk (0x2000UL)             /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
36527 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO12_Pos (12UL)                 /*!< DSP0N0GPIO12 (Bit 12)                                 */
36528 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO12_Msk (0x1000UL)             /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
36529 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO11_Pos (11UL)                 /*!< DSP0N0GPIO11 (Bit 11)                                 */
36530 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO11_Msk (0x800UL)              /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
36531 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO10_Pos (10UL)                 /*!< DSP0N0GPIO10 (Bit 10)                                 */
36532 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO10_Msk (0x400UL)              /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
36533 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO9_Pos (9UL)                   /*!< DSP0N0GPIO9 (Bit 9)                                   */
36534 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO9_Msk (0x200UL)               /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
36535 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO8_Pos (8UL)                   /*!< DSP0N0GPIO8 (Bit 8)                                   */
36536 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO8_Msk (0x100UL)               /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
36537 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO7_Pos (7UL)                   /*!< DSP0N0GPIO7 (Bit 7)                                   */
36538 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO7_Msk (0x80UL)                /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
36539 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO6_Pos (6UL)                   /*!< DSP0N0GPIO6 (Bit 6)                                   */
36540 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO6_Msk (0x40UL)                /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
36541 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO5_Pos (5UL)                   /*!< DSP0N0GPIO5 (Bit 5)                                   */
36542 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO5_Msk (0x20UL)                /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
36543 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO4_Pos (4UL)                   /*!< DSP0N0GPIO4 (Bit 4)                                   */
36544 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO4_Msk (0x10UL)                /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
36545 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO3_Pos (3UL)                   /*!< DSP0N0GPIO3 (Bit 3)                                   */
36546 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO3_Msk (0x8UL)                 /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
36547 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO2_Pos (2UL)                   /*!< DSP0N0GPIO2 (Bit 2)                                   */
36548 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO2_Msk (0x4UL)                 /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
36549 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO1_Pos (1UL)                   /*!< DSP0N0GPIO1 (Bit 1)                                   */
36550 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO1_Msk (0x2UL)                 /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
36551 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO0_Pos (0UL)                   /*!< DSP0N0GPIO0 (Bit 0)                                   */
36552 #define GPIO_DSP0N0INT0STAT_DSP0N0GPIO0_Msk (0x1UL)                 /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
36553 /* =====================================================  DSP0N0INT0CLR  ===================================================== */
36554 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO31_Pos (31UL)                  /*!< DSP0N0GPIO31 (Bit 31)                                 */
36555 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO31_Msk (0x80000000UL)          /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
36556 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO30_Pos (30UL)                  /*!< DSP0N0GPIO30 (Bit 30)                                 */
36557 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO30_Msk (0x40000000UL)          /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
36558 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO29_Pos (29UL)                  /*!< DSP0N0GPIO29 (Bit 29)                                 */
36559 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO29_Msk (0x20000000UL)          /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
36560 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO28_Pos (28UL)                  /*!< DSP0N0GPIO28 (Bit 28)                                 */
36561 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO28_Msk (0x10000000UL)          /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
36562 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO27_Pos (27UL)                  /*!< DSP0N0GPIO27 (Bit 27)                                 */
36563 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO27_Msk (0x8000000UL)           /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
36564 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO26_Pos (26UL)                  /*!< DSP0N0GPIO26 (Bit 26)                                 */
36565 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO26_Msk (0x4000000UL)           /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
36566 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO25_Pos (25UL)                  /*!< DSP0N0GPIO25 (Bit 25)                                 */
36567 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO25_Msk (0x2000000UL)           /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
36568 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO24_Pos (24UL)                  /*!< DSP0N0GPIO24 (Bit 24)                                 */
36569 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO24_Msk (0x1000000UL)           /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
36570 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO23_Pos (23UL)                  /*!< DSP0N0GPIO23 (Bit 23)                                 */
36571 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO23_Msk (0x800000UL)            /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
36572 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO22_Pos (22UL)                  /*!< DSP0N0GPIO22 (Bit 22)                                 */
36573 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO22_Msk (0x400000UL)            /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
36574 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO21_Pos (21UL)                  /*!< DSP0N0GPIO21 (Bit 21)                                 */
36575 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO21_Msk (0x200000UL)            /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
36576 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO20_Pos (20UL)                  /*!< DSP0N0GPIO20 (Bit 20)                                 */
36577 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO20_Msk (0x100000UL)            /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
36578 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO19_Pos (19UL)                  /*!< DSP0N0GPIO19 (Bit 19)                                 */
36579 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO19_Msk (0x80000UL)             /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
36580 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO18_Pos (18UL)                  /*!< DSP0N0GPIO18 (Bit 18)                                 */
36581 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO18_Msk (0x40000UL)             /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
36582 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO17_Pos (17UL)                  /*!< DSP0N0GPIO17 (Bit 17)                                 */
36583 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO17_Msk (0x20000UL)             /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
36584 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO16_Pos (16UL)                  /*!< DSP0N0GPIO16 (Bit 16)                                 */
36585 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO16_Msk (0x10000UL)             /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
36586 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO15_Pos (15UL)                  /*!< DSP0N0GPIO15 (Bit 15)                                 */
36587 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO15_Msk (0x8000UL)              /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
36588 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO14_Pos (14UL)                  /*!< DSP0N0GPIO14 (Bit 14)                                 */
36589 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO14_Msk (0x4000UL)              /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
36590 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO13_Pos (13UL)                  /*!< DSP0N0GPIO13 (Bit 13)                                 */
36591 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO13_Msk (0x2000UL)              /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
36592 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO12_Pos (12UL)                  /*!< DSP0N0GPIO12 (Bit 12)                                 */
36593 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO12_Msk (0x1000UL)              /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
36594 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO11_Pos (11UL)                  /*!< DSP0N0GPIO11 (Bit 11)                                 */
36595 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO11_Msk (0x800UL)               /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
36596 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO10_Pos (10UL)                  /*!< DSP0N0GPIO10 (Bit 10)                                 */
36597 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO10_Msk (0x400UL)               /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
36598 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO9_Pos (9UL)                    /*!< DSP0N0GPIO9 (Bit 9)                                   */
36599 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO9_Msk (0x200UL)                /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
36600 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO8_Pos (8UL)                    /*!< DSP0N0GPIO8 (Bit 8)                                   */
36601 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO8_Msk (0x100UL)                /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
36602 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO7_Pos (7UL)                    /*!< DSP0N0GPIO7 (Bit 7)                                   */
36603 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO7_Msk (0x80UL)                 /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
36604 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO6_Pos (6UL)                    /*!< DSP0N0GPIO6 (Bit 6)                                   */
36605 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO6_Msk (0x40UL)                 /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
36606 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO5_Pos (5UL)                    /*!< DSP0N0GPIO5 (Bit 5)                                   */
36607 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO5_Msk (0x20UL)                 /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
36608 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO4_Pos (4UL)                    /*!< DSP0N0GPIO4 (Bit 4)                                   */
36609 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO4_Msk (0x10UL)                 /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
36610 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO3_Pos (3UL)                    /*!< DSP0N0GPIO3 (Bit 3)                                   */
36611 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO3_Msk (0x8UL)                  /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
36612 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO2_Pos (2UL)                    /*!< DSP0N0GPIO2 (Bit 2)                                   */
36613 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO2_Msk (0x4UL)                  /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
36614 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO1_Pos (1UL)                    /*!< DSP0N0GPIO1 (Bit 1)                                   */
36615 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO1_Msk (0x2UL)                  /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
36616 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO0_Pos (0UL)                    /*!< DSP0N0GPIO0 (Bit 0)                                   */
36617 #define GPIO_DSP0N0INT0CLR_DSP0N0GPIO0_Msk (0x1UL)                  /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
36618 /* =====================================================  DSP0N0INT0SET  ===================================================== */
36619 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO31_Pos (31UL)                  /*!< DSP0N0GPIO31 (Bit 31)                                 */
36620 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO31_Msk (0x80000000UL)          /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
36621 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO30_Pos (30UL)                  /*!< DSP0N0GPIO30 (Bit 30)                                 */
36622 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO30_Msk (0x40000000UL)          /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
36623 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO29_Pos (29UL)                  /*!< DSP0N0GPIO29 (Bit 29)                                 */
36624 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO29_Msk (0x20000000UL)          /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
36625 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO28_Pos (28UL)                  /*!< DSP0N0GPIO28 (Bit 28)                                 */
36626 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO28_Msk (0x10000000UL)          /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
36627 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO27_Pos (27UL)                  /*!< DSP0N0GPIO27 (Bit 27)                                 */
36628 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO27_Msk (0x8000000UL)           /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
36629 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO26_Pos (26UL)                  /*!< DSP0N0GPIO26 (Bit 26)                                 */
36630 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO26_Msk (0x4000000UL)           /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
36631 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO25_Pos (25UL)                  /*!< DSP0N0GPIO25 (Bit 25)                                 */
36632 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO25_Msk (0x2000000UL)           /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
36633 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO24_Pos (24UL)                  /*!< DSP0N0GPIO24 (Bit 24)                                 */
36634 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO24_Msk (0x1000000UL)           /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
36635 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO23_Pos (23UL)                  /*!< DSP0N0GPIO23 (Bit 23)                                 */
36636 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO23_Msk (0x800000UL)            /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
36637 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO22_Pos (22UL)                  /*!< DSP0N0GPIO22 (Bit 22)                                 */
36638 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO22_Msk (0x400000UL)            /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
36639 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO21_Pos (21UL)                  /*!< DSP0N0GPIO21 (Bit 21)                                 */
36640 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO21_Msk (0x200000UL)            /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
36641 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO20_Pos (20UL)                  /*!< DSP0N0GPIO20 (Bit 20)                                 */
36642 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO20_Msk (0x100000UL)            /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
36643 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO19_Pos (19UL)                  /*!< DSP0N0GPIO19 (Bit 19)                                 */
36644 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO19_Msk (0x80000UL)             /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
36645 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO18_Pos (18UL)                  /*!< DSP0N0GPIO18 (Bit 18)                                 */
36646 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO18_Msk (0x40000UL)             /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
36647 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO17_Pos (17UL)                  /*!< DSP0N0GPIO17 (Bit 17)                                 */
36648 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO17_Msk (0x20000UL)             /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
36649 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO16_Pos (16UL)                  /*!< DSP0N0GPIO16 (Bit 16)                                 */
36650 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO16_Msk (0x10000UL)             /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
36651 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO15_Pos (15UL)                  /*!< DSP0N0GPIO15 (Bit 15)                                 */
36652 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO15_Msk (0x8000UL)              /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
36653 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO14_Pos (14UL)                  /*!< DSP0N0GPIO14 (Bit 14)                                 */
36654 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO14_Msk (0x4000UL)              /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
36655 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO13_Pos (13UL)                  /*!< DSP0N0GPIO13 (Bit 13)                                 */
36656 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO13_Msk (0x2000UL)              /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
36657 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO12_Pos (12UL)                  /*!< DSP0N0GPIO12 (Bit 12)                                 */
36658 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO12_Msk (0x1000UL)              /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
36659 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO11_Pos (11UL)                  /*!< DSP0N0GPIO11 (Bit 11)                                 */
36660 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO11_Msk (0x800UL)               /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
36661 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO10_Pos (10UL)                  /*!< DSP0N0GPIO10 (Bit 10)                                 */
36662 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO10_Msk (0x400UL)               /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
36663 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO9_Pos (9UL)                    /*!< DSP0N0GPIO9 (Bit 9)                                   */
36664 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO9_Msk (0x200UL)                /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
36665 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO8_Pos (8UL)                    /*!< DSP0N0GPIO8 (Bit 8)                                   */
36666 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO8_Msk (0x100UL)                /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
36667 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO7_Pos (7UL)                    /*!< DSP0N0GPIO7 (Bit 7)                                   */
36668 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO7_Msk (0x80UL)                 /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
36669 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO6_Pos (6UL)                    /*!< DSP0N0GPIO6 (Bit 6)                                   */
36670 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO6_Msk (0x40UL)                 /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
36671 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO5_Pos (5UL)                    /*!< DSP0N0GPIO5 (Bit 5)                                   */
36672 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO5_Msk (0x20UL)                 /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
36673 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO4_Pos (4UL)                    /*!< DSP0N0GPIO4 (Bit 4)                                   */
36674 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO4_Msk (0x10UL)                 /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
36675 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO3_Pos (3UL)                    /*!< DSP0N0GPIO3 (Bit 3)                                   */
36676 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO3_Msk (0x8UL)                  /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
36677 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO2_Pos (2UL)                    /*!< DSP0N0GPIO2 (Bit 2)                                   */
36678 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO2_Msk (0x4UL)                  /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
36679 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO1_Pos (1UL)                    /*!< DSP0N0GPIO1 (Bit 1)                                   */
36680 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO1_Msk (0x2UL)                  /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
36681 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO0_Pos (0UL)                    /*!< DSP0N0GPIO0 (Bit 0)                                   */
36682 #define GPIO_DSP0N0INT0SET_DSP0N0GPIO0_Msk (0x1UL)                  /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
36683 /* =====================================================  DSP0N0INT1EN  ====================================================== */
36684 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO63_Pos (31UL)                   /*!< DSP0N0GPIO63 (Bit 31)                                 */
36685 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO63_Msk (0x80000000UL)           /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
36686 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO62_Pos (30UL)                   /*!< DSP0N0GPIO62 (Bit 30)                                 */
36687 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO62_Msk (0x40000000UL)           /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
36688 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO61_Pos (29UL)                   /*!< DSP0N0GPIO61 (Bit 29)                                 */
36689 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO61_Msk (0x20000000UL)           /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
36690 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO60_Pos (28UL)                   /*!< DSP0N0GPIO60 (Bit 28)                                 */
36691 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO60_Msk (0x10000000UL)           /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
36692 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO59_Pos (27UL)                   /*!< DSP0N0GPIO59 (Bit 27)                                 */
36693 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO59_Msk (0x8000000UL)            /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
36694 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO58_Pos (26UL)                   /*!< DSP0N0GPIO58 (Bit 26)                                 */
36695 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO58_Msk (0x4000000UL)            /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
36696 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO57_Pos (25UL)                   /*!< DSP0N0GPIO57 (Bit 25)                                 */
36697 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO57_Msk (0x2000000UL)            /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
36698 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO56_Pos (24UL)                   /*!< DSP0N0GPIO56 (Bit 24)                                 */
36699 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO56_Msk (0x1000000UL)            /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
36700 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO55_Pos (23UL)                   /*!< DSP0N0GPIO55 (Bit 23)                                 */
36701 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO55_Msk (0x800000UL)             /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
36702 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO54_Pos (22UL)                   /*!< DSP0N0GPIO54 (Bit 22)                                 */
36703 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO54_Msk (0x400000UL)             /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
36704 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO53_Pos (21UL)                   /*!< DSP0N0GPIO53 (Bit 21)                                 */
36705 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO53_Msk (0x200000UL)             /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
36706 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO52_Pos (20UL)                   /*!< DSP0N0GPIO52 (Bit 20)                                 */
36707 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO52_Msk (0x100000UL)             /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
36708 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO51_Pos (19UL)                   /*!< DSP0N0GPIO51 (Bit 19)                                 */
36709 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO51_Msk (0x80000UL)              /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
36710 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO50_Pos (18UL)                   /*!< DSP0N0GPIO50 (Bit 18)                                 */
36711 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO50_Msk (0x40000UL)              /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
36712 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO49_Pos (17UL)                   /*!< DSP0N0GPIO49 (Bit 17)                                 */
36713 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO49_Msk (0x20000UL)              /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
36714 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO48_Pos (16UL)                   /*!< DSP0N0GPIO48 (Bit 16)                                 */
36715 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO48_Msk (0x10000UL)              /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
36716 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO47_Pos (15UL)                   /*!< DSP0N0GPIO47 (Bit 15)                                 */
36717 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO47_Msk (0x8000UL)               /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
36718 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO46_Pos (14UL)                   /*!< DSP0N0GPIO46 (Bit 14)                                 */
36719 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO46_Msk (0x4000UL)               /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
36720 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO45_Pos (13UL)                   /*!< DSP0N0GPIO45 (Bit 13)                                 */
36721 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO45_Msk (0x2000UL)               /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
36722 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO44_Pos (12UL)                   /*!< DSP0N0GPIO44 (Bit 12)                                 */
36723 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO44_Msk (0x1000UL)               /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
36724 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO43_Pos (11UL)                   /*!< DSP0N0GPIO43 (Bit 11)                                 */
36725 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO43_Msk (0x800UL)                /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
36726 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO42_Pos (10UL)                   /*!< DSP0N0GPIO42 (Bit 10)                                 */
36727 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO42_Msk (0x400UL)                /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
36728 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO41_Pos (9UL)                    /*!< DSP0N0GPIO41 (Bit 9)                                  */
36729 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO41_Msk (0x200UL)                /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
36730 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO40_Pos (8UL)                    /*!< DSP0N0GPIO40 (Bit 8)                                  */
36731 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO40_Msk (0x100UL)                /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
36732 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO39_Pos (7UL)                    /*!< DSP0N0GPIO39 (Bit 7)                                  */
36733 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO39_Msk (0x80UL)                 /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
36734 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO38_Pos (6UL)                    /*!< DSP0N0GPIO38 (Bit 6)                                  */
36735 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO38_Msk (0x40UL)                 /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
36736 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO37_Pos (5UL)                    /*!< DSP0N0GPIO37 (Bit 5)                                  */
36737 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO37_Msk (0x20UL)                 /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
36738 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO36_Pos (4UL)                    /*!< DSP0N0GPIO36 (Bit 4)                                  */
36739 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO36_Msk (0x10UL)                 /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
36740 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO35_Pos (3UL)                    /*!< DSP0N0GPIO35 (Bit 3)                                  */
36741 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO35_Msk (0x8UL)                  /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
36742 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO34_Pos (2UL)                    /*!< DSP0N0GPIO34 (Bit 2)                                  */
36743 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO34_Msk (0x4UL)                  /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
36744 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO33_Pos (1UL)                    /*!< DSP0N0GPIO33 (Bit 1)                                  */
36745 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO33_Msk (0x2UL)                  /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
36746 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO32_Pos (0UL)                    /*!< DSP0N0GPIO32 (Bit 0)                                  */
36747 #define GPIO_DSP0N0INT1EN_DSP0N0GPIO32_Msk (0x1UL)                  /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
36748 /* ====================================================  DSP0N0INT1STAT  ===================================================== */
36749 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO63_Pos (31UL)                 /*!< DSP0N0GPIO63 (Bit 31)                                 */
36750 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO63_Msk (0x80000000UL)         /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
36751 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO62_Pos (30UL)                 /*!< DSP0N0GPIO62 (Bit 30)                                 */
36752 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO62_Msk (0x40000000UL)         /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
36753 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO61_Pos (29UL)                 /*!< DSP0N0GPIO61 (Bit 29)                                 */
36754 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO61_Msk (0x20000000UL)         /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
36755 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO60_Pos (28UL)                 /*!< DSP0N0GPIO60 (Bit 28)                                 */
36756 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO60_Msk (0x10000000UL)         /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
36757 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO59_Pos (27UL)                 /*!< DSP0N0GPIO59 (Bit 27)                                 */
36758 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO59_Msk (0x8000000UL)          /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
36759 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO58_Pos (26UL)                 /*!< DSP0N0GPIO58 (Bit 26)                                 */
36760 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO58_Msk (0x4000000UL)          /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
36761 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO57_Pos (25UL)                 /*!< DSP0N0GPIO57 (Bit 25)                                 */
36762 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO57_Msk (0x2000000UL)          /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
36763 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO56_Pos (24UL)                 /*!< DSP0N0GPIO56 (Bit 24)                                 */
36764 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO56_Msk (0x1000000UL)          /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
36765 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO55_Pos (23UL)                 /*!< DSP0N0GPIO55 (Bit 23)                                 */
36766 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO55_Msk (0x800000UL)           /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
36767 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO54_Pos (22UL)                 /*!< DSP0N0GPIO54 (Bit 22)                                 */
36768 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO54_Msk (0x400000UL)           /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
36769 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO53_Pos (21UL)                 /*!< DSP0N0GPIO53 (Bit 21)                                 */
36770 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO53_Msk (0x200000UL)           /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
36771 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO52_Pos (20UL)                 /*!< DSP0N0GPIO52 (Bit 20)                                 */
36772 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO52_Msk (0x100000UL)           /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
36773 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO51_Pos (19UL)                 /*!< DSP0N0GPIO51 (Bit 19)                                 */
36774 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO51_Msk (0x80000UL)            /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
36775 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO50_Pos (18UL)                 /*!< DSP0N0GPIO50 (Bit 18)                                 */
36776 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO50_Msk (0x40000UL)            /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
36777 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO49_Pos (17UL)                 /*!< DSP0N0GPIO49 (Bit 17)                                 */
36778 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO49_Msk (0x20000UL)            /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
36779 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO48_Pos (16UL)                 /*!< DSP0N0GPIO48 (Bit 16)                                 */
36780 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO48_Msk (0x10000UL)            /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
36781 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO47_Pos (15UL)                 /*!< DSP0N0GPIO47 (Bit 15)                                 */
36782 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO47_Msk (0x8000UL)             /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
36783 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO46_Pos (14UL)                 /*!< DSP0N0GPIO46 (Bit 14)                                 */
36784 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO46_Msk (0x4000UL)             /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
36785 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO45_Pos (13UL)                 /*!< DSP0N0GPIO45 (Bit 13)                                 */
36786 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO45_Msk (0x2000UL)             /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
36787 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO44_Pos (12UL)                 /*!< DSP0N0GPIO44 (Bit 12)                                 */
36788 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO44_Msk (0x1000UL)             /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
36789 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO43_Pos (11UL)                 /*!< DSP0N0GPIO43 (Bit 11)                                 */
36790 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO43_Msk (0x800UL)              /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
36791 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO42_Pos (10UL)                 /*!< DSP0N0GPIO42 (Bit 10)                                 */
36792 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO42_Msk (0x400UL)              /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
36793 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO41_Pos (9UL)                  /*!< DSP0N0GPIO41 (Bit 9)                                  */
36794 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO41_Msk (0x200UL)              /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
36795 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO40_Pos (8UL)                  /*!< DSP0N0GPIO40 (Bit 8)                                  */
36796 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO40_Msk (0x100UL)              /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
36797 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO39_Pos (7UL)                  /*!< DSP0N0GPIO39 (Bit 7)                                  */
36798 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO39_Msk (0x80UL)               /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
36799 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO38_Pos (6UL)                  /*!< DSP0N0GPIO38 (Bit 6)                                  */
36800 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO38_Msk (0x40UL)               /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
36801 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO37_Pos (5UL)                  /*!< DSP0N0GPIO37 (Bit 5)                                  */
36802 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO37_Msk (0x20UL)               /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
36803 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO36_Pos (4UL)                  /*!< DSP0N0GPIO36 (Bit 4)                                  */
36804 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO36_Msk (0x10UL)               /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
36805 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO35_Pos (3UL)                  /*!< DSP0N0GPIO35 (Bit 3)                                  */
36806 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO35_Msk (0x8UL)                /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
36807 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO34_Pos (2UL)                  /*!< DSP0N0GPIO34 (Bit 2)                                  */
36808 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO34_Msk (0x4UL)                /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
36809 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO33_Pos (1UL)                  /*!< DSP0N0GPIO33 (Bit 1)                                  */
36810 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO33_Msk (0x2UL)                /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
36811 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO32_Pos (0UL)                  /*!< DSP0N0GPIO32 (Bit 0)                                  */
36812 #define GPIO_DSP0N0INT1STAT_DSP0N0GPIO32_Msk (0x1UL)                /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
36813 /* =====================================================  DSP0N0INT1CLR  ===================================================== */
36814 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO63_Pos (31UL)                  /*!< DSP0N0GPIO63 (Bit 31)                                 */
36815 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO63_Msk (0x80000000UL)          /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
36816 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO62_Pos (30UL)                  /*!< DSP0N0GPIO62 (Bit 30)                                 */
36817 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO62_Msk (0x40000000UL)          /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
36818 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO61_Pos (29UL)                  /*!< DSP0N0GPIO61 (Bit 29)                                 */
36819 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO61_Msk (0x20000000UL)          /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
36820 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO60_Pos (28UL)                  /*!< DSP0N0GPIO60 (Bit 28)                                 */
36821 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO60_Msk (0x10000000UL)          /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
36822 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO59_Pos (27UL)                  /*!< DSP0N0GPIO59 (Bit 27)                                 */
36823 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO59_Msk (0x8000000UL)           /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
36824 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO58_Pos (26UL)                  /*!< DSP0N0GPIO58 (Bit 26)                                 */
36825 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO58_Msk (0x4000000UL)           /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
36826 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO57_Pos (25UL)                  /*!< DSP0N0GPIO57 (Bit 25)                                 */
36827 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO57_Msk (0x2000000UL)           /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
36828 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO56_Pos (24UL)                  /*!< DSP0N0GPIO56 (Bit 24)                                 */
36829 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO56_Msk (0x1000000UL)           /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
36830 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO55_Pos (23UL)                  /*!< DSP0N0GPIO55 (Bit 23)                                 */
36831 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO55_Msk (0x800000UL)            /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
36832 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO54_Pos (22UL)                  /*!< DSP0N0GPIO54 (Bit 22)                                 */
36833 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO54_Msk (0x400000UL)            /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
36834 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO53_Pos (21UL)                  /*!< DSP0N0GPIO53 (Bit 21)                                 */
36835 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO53_Msk (0x200000UL)            /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
36836 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO52_Pos (20UL)                  /*!< DSP0N0GPIO52 (Bit 20)                                 */
36837 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO52_Msk (0x100000UL)            /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
36838 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO51_Pos (19UL)                  /*!< DSP0N0GPIO51 (Bit 19)                                 */
36839 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO51_Msk (0x80000UL)             /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
36840 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO50_Pos (18UL)                  /*!< DSP0N0GPIO50 (Bit 18)                                 */
36841 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO50_Msk (0x40000UL)             /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
36842 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO49_Pos (17UL)                  /*!< DSP0N0GPIO49 (Bit 17)                                 */
36843 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO49_Msk (0x20000UL)             /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
36844 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO48_Pos (16UL)                  /*!< DSP0N0GPIO48 (Bit 16)                                 */
36845 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO48_Msk (0x10000UL)             /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
36846 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO47_Pos (15UL)                  /*!< DSP0N0GPIO47 (Bit 15)                                 */
36847 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO47_Msk (0x8000UL)              /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
36848 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO46_Pos (14UL)                  /*!< DSP0N0GPIO46 (Bit 14)                                 */
36849 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO46_Msk (0x4000UL)              /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
36850 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO45_Pos (13UL)                  /*!< DSP0N0GPIO45 (Bit 13)                                 */
36851 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO45_Msk (0x2000UL)              /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
36852 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO44_Pos (12UL)                  /*!< DSP0N0GPIO44 (Bit 12)                                 */
36853 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO44_Msk (0x1000UL)              /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
36854 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO43_Pos (11UL)                  /*!< DSP0N0GPIO43 (Bit 11)                                 */
36855 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO43_Msk (0x800UL)               /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
36856 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO42_Pos (10UL)                  /*!< DSP0N0GPIO42 (Bit 10)                                 */
36857 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO42_Msk (0x400UL)               /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
36858 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO41_Pos (9UL)                   /*!< DSP0N0GPIO41 (Bit 9)                                  */
36859 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO41_Msk (0x200UL)               /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
36860 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO40_Pos (8UL)                   /*!< DSP0N0GPIO40 (Bit 8)                                  */
36861 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO40_Msk (0x100UL)               /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
36862 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO39_Pos (7UL)                   /*!< DSP0N0GPIO39 (Bit 7)                                  */
36863 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO39_Msk (0x80UL)                /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
36864 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO38_Pos (6UL)                   /*!< DSP0N0GPIO38 (Bit 6)                                  */
36865 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO38_Msk (0x40UL)                /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
36866 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO37_Pos (5UL)                   /*!< DSP0N0GPIO37 (Bit 5)                                  */
36867 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO37_Msk (0x20UL)                /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
36868 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO36_Pos (4UL)                   /*!< DSP0N0GPIO36 (Bit 4)                                  */
36869 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO36_Msk (0x10UL)                /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
36870 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO35_Pos (3UL)                   /*!< DSP0N0GPIO35 (Bit 3)                                  */
36871 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO35_Msk (0x8UL)                 /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
36872 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO34_Pos (2UL)                   /*!< DSP0N0GPIO34 (Bit 2)                                  */
36873 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO34_Msk (0x4UL)                 /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
36874 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO33_Pos (1UL)                   /*!< DSP0N0GPIO33 (Bit 1)                                  */
36875 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO33_Msk (0x2UL)                 /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
36876 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO32_Pos (0UL)                   /*!< DSP0N0GPIO32 (Bit 0)                                  */
36877 #define GPIO_DSP0N0INT1CLR_DSP0N0GPIO32_Msk (0x1UL)                 /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
36878 /* =====================================================  DSP0N0INT1SET  ===================================================== */
36879 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO63_Pos (31UL)                  /*!< DSP0N0GPIO63 (Bit 31)                                 */
36880 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO63_Msk (0x80000000UL)          /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
36881 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO62_Pos (30UL)                  /*!< DSP0N0GPIO62 (Bit 30)                                 */
36882 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO62_Msk (0x40000000UL)          /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
36883 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO61_Pos (29UL)                  /*!< DSP0N0GPIO61 (Bit 29)                                 */
36884 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO61_Msk (0x20000000UL)          /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
36885 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO60_Pos (28UL)                  /*!< DSP0N0GPIO60 (Bit 28)                                 */
36886 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO60_Msk (0x10000000UL)          /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
36887 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO59_Pos (27UL)                  /*!< DSP0N0GPIO59 (Bit 27)                                 */
36888 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO59_Msk (0x8000000UL)           /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
36889 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO58_Pos (26UL)                  /*!< DSP0N0GPIO58 (Bit 26)                                 */
36890 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO58_Msk (0x4000000UL)           /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
36891 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO57_Pos (25UL)                  /*!< DSP0N0GPIO57 (Bit 25)                                 */
36892 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO57_Msk (0x2000000UL)           /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
36893 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO56_Pos (24UL)                  /*!< DSP0N0GPIO56 (Bit 24)                                 */
36894 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO56_Msk (0x1000000UL)           /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
36895 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO55_Pos (23UL)                  /*!< DSP0N0GPIO55 (Bit 23)                                 */
36896 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO55_Msk (0x800000UL)            /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
36897 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO54_Pos (22UL)                  /*!< DSP0N0GPIO54 (Bit 22)                                 */
36898 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO54_Msk (0x400000UL)            /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
36899 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO53_Pos (21UL)                  /*!< DSP0N0GPIO53 (Bit 21)                                 */
36900 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO53_Msk (0x200000UL)            /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
36901 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO52_Pos (20UL)                  /*!< DSP0N0GPIO52 (Bit 20)                                 */
36902 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO52_Msk (0x100000UL)            /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
36903 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO51_Pos (19UL)                  /*!< DSP0N0GPIO51 (Bit 19)                                 */
36904 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO51_Msk (0x80000UL)             /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
36905 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO50_Pos (18UL)                  /*!< DSP0N0GPIO50 (Bit 18)                                 */
36906 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO50_Msk (0x40000UL)             /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
36907 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO49_Pos (17UL)                  /*!< DSP0N0GPIO49 (Bit 17)                                 */
36908 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO49_Msk (0x20000UL)             /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
36909 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO48_Pos (16UL)                  /*!< DSP0N0GPIO48 (Bit 16)                                 */
36910 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO48_Msk (0x10000UL)             /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
36911 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO47_Pos (15UL)                  /*!< DSP0N0GPIO47 (Bit 15)                                 */
36912 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO47_Msk (0x8000UL)              /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
36913 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO46_Pos (14UL)                  /*!< DSP0N0GPIO46 (Bit 14)                                 */
36914 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO46_Msk (0x4000UL)              /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
36915 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO45_Pos (13UL)                  /*!< DSP0N0GPIO45 (Bit 13)                                 */
36916 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO45_Msk (0x2000UL)              /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
36917 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO44_Pos (12UL)                  /*!< DSP0N0GPIO44 (Bit 12)                                 */
36918 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO44_Msk (0x1000UL)              /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
36919 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO43_Pos (11UL)                  /*!< DSP0N0GPIO43 (Bit 11)                                 */
36920 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO43_Msk (0x800UL)               /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
36921 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO42_Pos (10UL)                  /*!< DSP0N0GPIO42 (Bit 10)                                 */
36922 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO42_Msk (0x400UL)               /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
36923 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO41_Pos (9UL)                   /*!< DSP0N0GPIO41 (Bit 9)                                  */
36924 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO41_Msk (0x200UL)               /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
36925 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO40_Pos (8UL)                   /*!< DSP0N0GPIO40 (Bit 8)                                  */
36926 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO40_Msk (0x100UL)               /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
36927 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO39_Pos (7UL)                   /*!< DSP0N0GPIO39 (Bit 7)                                  */
36928 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO39_Msk (0x80UL)                /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
36929 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO38_Pos (6UL)                   /*!< DSP0N0GPIO38 (Bit 6)                                  */
36930 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO38_Msk (0x40UL)                /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
36931 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO37_Pos (5UL)                   /*!< DSP0N0GPIO37 (Bit 5)                                  */
36932 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO37_Msk (0x20UL)                /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
36933 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO36_Pos (4UL)                   /*!< DSP0N0GPIO36 (Bit 4)                                  */
36934 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO36_Msk (0x10UL)                /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
36935 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO35_Pos (3UL)                   /*!< DSP0N0GPIO35 (Bit 3)                                  */
36936 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO35_Msk (0x8UL)                 /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
36937 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO34_Pos (2UL)                   /*!< DSP0N0GPIO34 (Bit 2)                                  */
36938 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO34_Msk (0x4UL)                 /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
36939 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO33_Pos (1UL)                   /*!< DSP0N0GPIO33 (Bit 1)                                  */
36940 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO33_Msk (0x2UL)                 /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
36941 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO32_Pos (0UL)                   /*!< DSP0N0GPIO32 (Bit 0)                                  */
36942 #define GPIO_DSP0N0INT1SET_DSP0N0GPIO32_Msk (0x1UL)                 /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
36943 /* =====================================================  DSP0N0INT2EN  ====================================================== */
36944 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO95_Pos (31UL)                   /*!< DSP0N0GPIO95 (Bit 31)                                 */
36945 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO95_Msk (0x80000000UL)           /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
36946 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO94_Pos (30UL)                   /*!< DSP0N0GPIO94 (Bit 30)                                 */
36947 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO94_Msk (0x40000000UL)           /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
36948 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO93_Pos (29UL)                   /*!< DSP0N0GPIO93 (Bit 29)                                 */
36949 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO93_Msk (0x20000000UL)           /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
36950 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO92_Pos (28UL)                   /*!< DSP0N0GPIO92 (Bit 28)                                 */
36951 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO92_Msk (0x10000000UL)           /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
36952 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO91_Pos (27UL)                   /*!< DSP0N0GPIO91 (Bit 27)                                 */
36953 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO91_Msk (0x8000000UL)            /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
36954 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO90_Pos (26UL)                   /*!< DSP0N0GPIO90 (Bit 26)                                 */
36955 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO90_Msk (0x4000000UL)            /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
36956 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO89_Pos (25UL)                   /*!< DSP0N0GPIO89 (Bit 25)                                 */
36957 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO89_Msk (0x2000000UL)            /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
36958 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO88_Pos (24UL)                   /*!< DSP0N0GPIO88 (Bit 24)                                 */
36959 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO88_Msk (0x1000000UL)            /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
36960 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO87_Pos (23UL)                   /*!< DSP0N0GPIO87 (Bit 23)                                 */
36961 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO87_Msk (0x800000UL)             /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
36962 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO86_Pos (22UL)                   /*!< DSP0N0GPIO86 (Bit 22)                                 */
36963 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO86_Msk (0x400000UL)             /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
36964 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO85_Pos (21UL)                   /*!< DSP0N0GPIO85 (Bit 21)                                 */
36965 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO85_Msk (0x200000UL)             /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
36966 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO84_Pos (20UL)                   /*!< DSP0N0GPIO84 (Bit 20)                                 */
36967 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO84_Msk (0x100000UL)             /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
36968 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO83_Pos (19UL)                   /*!< DSP0N0GPIO83 (Bit 19)                                 */
36969 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO83_Msk (0x80000UL)              /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
36970 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO82_Pos (18UL)                   /*!< DSP0N0GPIO82 (Bit 18)                                 */
36971 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO82_Msk (0x40000UL)              /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
36972 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO81_Pos (17UL)                   /*!< DSP0N0GPIO81 (Bit 17)                                 */
36973 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO81_Msk (0x20000UL)              /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
36974 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO80_Pos (16UL)                   /*!< DSP0N0GPIO80 (Bit 16)                                 */
36975 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO80_Msk (0x10000UL)              /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
36976 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO79_Pos (15UL)                   /*!< DSP0N0GPIO79 (Bit 15)                                 */
36977 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO79_Msk (0x8000UL)               /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
36978 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO78_Pos (14UL)                   /*!< DSP0N0GPIO78 (Bit 14)                                 */
36979 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO78_Msk (0x4000UL)               /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
36980 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO77_Pos (13UL)                   /*!< DSP0N0GPIO77 (Bit 13)                                 */
36981 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO77_Msk (0x2000UL)               /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
36982 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO76_Pos (12UL)                   /*!< DSP0N0GPIO76 (Bit 12)                                 */
36983 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO76_Msk (0x1000UL)               /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
36984 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO75_Pos (11UL)                   /*!< DSP0N0GPIO75 (Bit 11)                                 */
36985 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO75_Msk (0x800UL)                /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
36986 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO74_Pos (10UL)                   /*!< DSP0N0GPIO74 (Bit 10)                                 */
36987 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO74_Msk (0x400UL)                /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
36988 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO73_Pos (9UL)                    /*!< DSP0N0GPIO73 (Bit 9)                                  */
36989 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO73_Msk (0x200UL)                /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
36990 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO72_Pos (8UL)                    /*!< DSP0N0GPIO72 (Bit 8)                                  */
36991 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO72_Msk (0x100UL)                /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
36992 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO71_Pos (7UL)                    /*!< DSP0N0GPIO71 (Bit 7)                                  */
36993 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO71_Msk (0x80UL)                 /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
36994 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO70_Pos (6UL)                    /*!< DSP0N0GPIO70 (Bit 6)                                  */
36995 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO70_Msk (0x40UL)                 /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
36996 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO69_Pos (5UL)                    /*!< DSP0N0GPIO69 (Bit 5)                                  */
36997 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO69_Msk (0x20UL)                 /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
36998 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO68_Pos (4UL)                    /*!< DSP0N0GPIO68 (Bit 4)                                  */
36999 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO68_Msk (0x10UL)                 /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
37000 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO67_Pos (3UL)                    /*!< DSP0N0GPIO67 (Bit 3)                                  */
37001 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO67_Msk (0x8UL)                  /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
37002 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO66_Pos (2UL)                    /*!< DSP0N0GPIO66 (Bit 2)                                  */
37003 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO66_Msk (0x4UL)                  /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
37004 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO65_Pos (1UL)                    /*!< DSP0N0GPIO65 (Bit 1)                                  */
37005 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO65_Msk (0x2UL)                  /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
37006 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO64_Pos (0UL)                    /*!< DSP0N0GPIO64 (Bit 0)                                  */
37007 #define GPIO_DSP0N0INT2EN_DSP0N0GPIO64_Msk (0x1UL)                  /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
37008 /* ====================================================  DSP0N0INT2STAT  ===================================================== */
37009 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO95_Pos (31UL)                 /*!< DSP0N0GPIO95 (Bit 31)                                 */
37010 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO95_Msk (0x80000000UL)         /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
37011 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO94_Pos (30UL)                 /*!< DSP0N0GPIO94 (Bit 30)                                 */
37012 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO94_Msk (0x40000000UL)         /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
37013 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO93_Pos (29UL)                 /*!< DSP0N0GPIO93 (Bit 29)                                 */
37014 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO93_Msk (0x20000000UL)         /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
37015 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO92_Pos (28UL)                 /*!< DSP0N0GPIO92 (Bit 28)                                 */
37016 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO92_Msk (0x10000000UL)         /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
37017 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO91_Pos (27UL)                 /*!< DSP0N0GPIO91 (Bit 27)                                 */
37018 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO91_Msk (0x8000000UL)          /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
37019 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO90_Pos (26UL)                 /*!< DSP0N0GPIO90 (Bit 26)                                 */
37020 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO90_Msk (0x4000000UL)          /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
37021 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO89_Pos (25UL)                 /*!< DSP0N0GPIO89 (Bit 25)                                 */
37022 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO89_Msk (0x2000000UL)          /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
37023 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO88_Pos (24UL)                 /*!< DSP0N0GPIO88 (Bit 24)                                 */
37024 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO88_Msk (0x1000000UL)          /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
37025 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO87_Pos (23UL)                 /*!< DSP0N0GPIO87 (Bit 23)                                 */
37026 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO87_Msk (0x800000UL)           /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
37027 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO86_Pos (22UL)                 /*!< DSP0N0GPIO86 (Bit 22)                                 */
37028 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO86_Msk (0x400000UL)           /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
37029 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO85_Pos (21UL)                 /*!< DSP0N0GPIO85 (Bit 21)                                 */
37030 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO85_Msk (0x200000UL)           /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
37031 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO84_Pos (20UL)                 /*!< DSP0N0GPIO84 (Bit 20)                                 */
37032 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO84_Msk (0x100000UL)           /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
37033 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO83_Pos (19UL)                 /*!< DSP0N0GPIO83 (Bit 19)                                 */
37034 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO83_Msk (0x80000UL)            /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
37035 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO82_Pos (18UL)                 /*!< DSP0N0GPIO82 (Bit 18)                                 */
37036 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO82_Msk (0x40000UL)            /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
37037 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO81_Pos (17UL)                 /*!< DSP0N0GPIO81 (Bit 17)                                 */
37038 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO81_Msk (0x20000UL)            /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
37039 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO80_Pos (16UL)                 /*!< DSP0N0GPIO80 (Bit 16)                                 */
37040 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO80_Msk (0x10000UL)            /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
37041 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO79_Pos (15UL)                 /*!< DSP0N0GPIO79 (Bit 15)                                 */
37042 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO79_Msk (0x8000UL)             /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
37043 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO78_Pos (14UL)                 /*!< DSP0N0GPIO78 (Bit 14)                                 */
37044 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO78_Msk (0x4000UL)             /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
37045 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO77_Pos (13UL)                 /*!< DSP0N0GPIO77 (Bit 13)                                 */
37046 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO77_Msk (0x2000UL)             /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
37047 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO76_Pos (12UL)                 /*!< DSP0N0GPIO76 (Bit 12)                                 */
37048 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO76_Msk (0x1000UL)             /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
37049 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO75_Pos (11UL)                 /*!< DSP0N0GPIO75 (Bit 11)                                 */
37050 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO75_Msk (0x800UL)              /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
37051 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO74_Pos (10UL)                 /*!< DSP0N0GPIO74 (Bit 10)                                 */
37052 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO74_Msk (0x400UL)              /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
37053 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO73_Pos (9UL)                  /*!< DSP0N0GPIO73 (Bit 9)                                  */
37054 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO73_Msk (0x200UL)              /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
37055 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO72_Pos (8UL)                  /*!< DSP0N0GPIO72 (Bit 8)                                  */
37056 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO72_Msk (0x100UL)              /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
37057 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO71_Pos (7UL)                  /*!< DSP0N0GPIO71 (Bit 7)                                  */
37058 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO71_Msk (0x80UL)               /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
37059 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO70_Pos (6UL)                  /*!< DSP0N0GPIO70 (Bit 6)                                  */
37060 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO70_Msk (0x40UL)               /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
37061 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO69_Pos (5UL)                  /*!< DSP0N0GPIO69 (Bit 5)                                  */
37062 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO69_Msk (0x20UL)               /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
37063 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO68_Pos (4UL)                  /*!< DSP0N0GPIO68 (Bit 4)                                  */
37064 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO68_Msk (0x10UL)               /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
37065 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO67_Pos (3UL)                  /*!< DSP0N0GPIO67 (Bit 3)                                  */
37066 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO67_Msk (0x8UL)                /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
37067 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO66_Pos (2UL)                  /*!< DSP0N0GPIO66 (Bit 2)                                  */
37068 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO66_Msk (0x4UL)                /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
37069 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO65_Pos (1UL)                  /*!< DSP0N0GPIO65 (Bit 1)                                  */
37070 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO65_Msk (0x2UL)                /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
37071 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO64_Pos (0UL)                  /*!< DSP0N0GPIO64 (Bit 0)                                  */
37072 #define GPIO_DSP0N0INT2STAT_DSP0N0GPIO64_Msk (0x1UL)                /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
37073 /* =====================================================  DSP0N0INT2CLR  ===================================================== */
37074 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO95_Pos (31UL)                  /*!< DSP0N0GPIO95 (Bit 31)                                 */
37075 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO95_Msk (0x80000000UL)          /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
37076 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO94_Pos (30UL)                  /*!< DSP0N0GPIO94 (Bit 30)                                 */
37077 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO94_Msk (0x40000000UL)          /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
37078 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO93_Pos (29UL)                  /*!< DSP0N0GPIO93 (Bit 29)                                 */
37079 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO93_Msk (0x20000000UL)          /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
37080 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO92_Pos (28UL)                  /*!< DSP0N0GPIO92 (Bit 28)                                 */
37081 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO92_Msk (0x10000000UL)          /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
37082 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO91_Pos (27UL)                  /*!< DSP0N0GPIO91 (Bit 27)                                 */
37083 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO91_Msk (0x8000000UL)           /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
37084 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO90_Pos (26UL)                  /*!< DSP0N0GPIO90 (Bit 26)                                 */
37085 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO90_Msk (0x4000000UL)           /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
37086 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO89_Pos (25UL)                  /*!< DSP0N0GPIO89 (Bit 25)                                 */
37087 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO89_Msk (0x2000000UL)           /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
37088 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO88_Pos (24UL)                  /*!< DSP0N0GPIO88 (Bit 24)                                 */
37089 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO88_Msk (0x1000000UL)           /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
37090 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO87_Pos (23UL)                  /*!< DSP0N0GPIO87 (Bit 23)                                 */
37091 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO87_Msk (0x800000UL)            /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
37092 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO86_Pos (22UL)                  /*!< DSP0N0GPIO86 (Bit 22)                                 */
37093 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO86_Msk (0x400000UL)            /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
37094 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO85_Pos (21UL)                  /*!< DSP0N0GPIO85 (Bit 21)                                 */
37095 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO85_Msk (0x200000UL)            /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
37096 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO84_Pos (20UL)                  /*!< DSP0N0GPIO84 (Bit 20)                                 */
37097 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO84_Msk (0x100000UL)            /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
37098 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO83_Pos (19UL)                  /*!< DSP0N0GPIO83 (Bit 19)                                 */
37099 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO83_Msk (0x80000UL)             /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
37100 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO82_Pos (18UL)                  /*!< DSP0N0GPIO82 (Bit 18)                                 */
37101 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO82_Msk (0x40000UL)             /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
37102 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO81_Pos (17UL)                  /*!< DSP0N0GPIO81 (Bit 17)                                 */
37103 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO81_Msk (0x20000UL)             /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
37104 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO80_Pos (16UL)                  /*!< DSP0N0GPIO80 (Bit 16)                                 */
37105 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO80_Msk (0x10000UL)             /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
37106 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO79_Pos (15UL)                  /*!< DSP0N0GPIO79 (Bit 15)                                 */
37107 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO79_Msk (0x8000UL)              /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
37108 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO78_Pos (14UL)                  /*!< DSP0N0GPIO78 (Bit 14)                                 */
37109 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO78_Msk (0x4000UL)              /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
37110 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO77_Pos (13UL)                  /*!< DSP0N0GPIO77 (Bit 13)                                 */
37111 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO77_Msk (0x2000UL)              /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
37112 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO76_Pos (12UL)                  /*!< DSP0N0GPIO76 (Bit 12)                                 */
37113 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO76_Msk (0x1000UL)              /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
37114 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO75_Pos (11UL)                  /*!< DSP0N0GPIO75 (Bit 11)                                 */
37115 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO75_Msk (0x800UL)               /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
37116 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO74_Pos (10UL)                  /*!< DSP0N0GPIO74 (Bit 10)                                 */
37117 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO74_Msk (0x400UL)               /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
37118 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO73_Pos (9UL)                   /*!< DSP0N0GPIO73 (Bit 9)                                  */
37119 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO73_Msk (0x200UL)               /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
37120 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO72_Pos (8UL)                   /*!< DSP0N0GPIO72 (Bit 8)                                  */
37121 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO72_Msk (0x100UL)               /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
37122 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO71_Pos (7UL)                   /*!< DSP0N0GPIO71 (Bit 7)                                  */
37123 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO71_Msk (0x80UL)                /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
37124 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO70_Pos (6UL)                   /*!< DSP0N0GPIO70 (Bit 6)                                  */
37125 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO70_Msk (0x40UL)                /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
37126 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO69_Pos (5UL)                   /*!< DSP0N0GPIO69 (Bit 5)                                  */
37127 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO69_Msk (0x20UL)                /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
37128 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO68_Pos (4UL)                   /*!< DSP0N0GPIO68 (Bit 4)                                  */
37129 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO68_Msk (0x10UL)                /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
37130 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO67_Pos (3UL)                   /*!< DSP0N0GPIO67 (Bit 3)                                  */
37131 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO67_Msk (0x8UL)                 /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
37132 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO66_Pos (2UL)                   /*!< DSP0N0GPIO66 (Bit 2)                                  */
37133 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO66_Msk (0x4UL)                 /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
37134 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO65_Pos (1UL)                   /*!< DSP0N0GPIO65 (Bit 1)                                  */
37135 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO65_Msk (0x2UL)                 /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
37136 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO64_Pos (0UL)                   /*!< DSP0N0GPIO64 (Bit 0)                                  */
37137 #define GPIO_DSP0N0INT2CLR_DSP0N0GPIO64_Msk (0x1UL)                 /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
37138 /* =====================================================  DSP0N0INT2SET  ===================================================== */
37139 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO95_Pos (31UL)                  /*!< DSP0N0GPIO95 (Bit 31)                                 */
37140 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO95_Msk (0x80000000UL)          /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
37141 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO94_Pos (30UL)                  /*!< DSP0N0GPIO94 (Bit 30)                                 */
37142 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO94_Msk (0x40000000UL)          /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
37143 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO93_Pos (29UL)                  /*!< DSP0N0GPIO93 (Bit 29)                                 */
37144 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO93_Msk (0x20000000UL)          /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
37145 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO92_Pos (28UL)                  /*!< DSP0N0GPIO92 (Bit 28)                                 */
37146 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO92_Msk (0x10000000UL)          /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
37147 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO91_Pos (27UL)                  /*!< DSP0N0GPIO91 (Bit 27)                                 */
37148 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO91_Msk (0x8000000UL)           /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
37149 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO90_Pos (26UL)                  /*!< DSP0N0GPIO90 (Bit 26)                                 */
37150 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO90_Msk (0x4000000UL)           /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
37151 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO89_Pos (25UL)                  /*!< DSP0N0GPIO89 (Bit 25)                                 */
37152 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO89_Msk (0x2000000UL)           /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
37153 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO88_Pos (24UL)                  /*!< DSP0N0GPIO88 (Bit 24)                                 */
37154 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO88_Msk (0x1000000UL)           /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
37155 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO87_Pos (23UL)                  /*!< DSP0N0GPIO87 (Bit 23)                                 */
37156 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO87_Msk (0x800000UL)            /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
37157 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO86_Pos (22UL)                  /*!< DSP0N0GPIO86 (Bit 22)                                 */
37158 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO86_Msk (0x400000UL)            /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
37159 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO85_Pos (21UL)                  /*!< DSP0N0GPIO85 (Bit 21)                                 */
37160 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO85_Msk (0x200000UL)            /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
37161 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO84_Pos (20UL)                  /*!< DSP0N0GPIO84 (Bit 20)                                 */
37162 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO84_Msk (0x100000UL)            /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
37163 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO83_Pos (19UL)                  /*!< DSP0N0GPIO83 (Bit 19)                                 */
37164 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO83_Msk (0x80000UL)             /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
37165 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO82_Pos (18UL)                  /*!< DSP0N0GPIO82 (Bit 18)                                 */
37166 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO82_Msk (0x40000UL)             /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
37167 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO81_Pos (17UL)                  /*!< DSP0N0GPIO81 (Bit 17)                                 */
37168 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO81_Msk (0x20000UL)             /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
37169 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO80_Pos (16UL)                  /*!< DSP0N0GPIO80 (Bit 16)                                 */
37170 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO80_Msk (0x10000UL)             /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
37171 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO79_Pos (15UL)                  /*!< DSP0N0GPIO79 (Bit 15)                                 */
37172 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO79_Msk (0x8000UL)              /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
37173 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO78_Pos (14UL)                  /*!< DSP0N0GPIO78 (Bit 14)                                 */
37174 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO78_Msk (0x4000UL)              /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
37175 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO77_Pos (13UL)                  /*!< DSP0N0GPIO77 (Bit 13)                                 */
37176 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO77_Msk (0x2000UL)              /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
37177 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO76_Pos (12UL)                  /*!< DSP0N0GPIO76 (Bit 12)                                 */
37178 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO76_Msk (0x1000UL)              /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
37179 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO75_Pos (11UL)                  /*!< DSP0N0GPIO75 (Bit 11)                                 */
37180 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO75_Msk (0x800UL)               /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
37181 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO74_Pos (10UL)                  /*!< DSP0N0GPIO74 (Bit 10)                                 */
37182 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO74_Msk (0x400UL)               /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
37183 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO73_Pos (9UL)                   /*!< DSP0N0GPIO73 (Bit 9)                                  */
37184 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO73_Msk (0x200UL)               /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
37185 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO72_Pos (8UL)                   /*!< DSP0N0GPIO72 (Bit 8)                                  */
37186 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO72_Msk (0x100UL)               /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
37187 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO71_Pos (7UL)                   /*!< DSP0N0GPIO71 (Bit 7)                                  */
37188 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO71_Msk (0x80UL)                /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
37189 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO70_Pos (6UL)                   /*!< DSP0N0GPIO70 (Bit 6)                                  */
37190 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO70_Msk (0x40UL)                /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
37191 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO69_Pos (5UL)                   /*!< DSP0N0GPIO69 (Bit 5)                                  */
37192 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO69_Msk (0x20UL)                /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
37193 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO68_Pos (4UL)                   /*!< DSP0N0GPIO68 (Bit 4)                                  */
37194 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO68_Msk (0x10UL)                /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
37195 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO67_Pos (3UL)                   /*!< DSP0N0GPIO67 (Bit 3)                                  */
37196 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO67_Msk (0x8UL)                 /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
37197 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO66_Pos (2UL)                   /*!< DSP0N0GPIO66 (Bit 2)                                  */
37198 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO66_Msk (0x4UL)                 /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
37199 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO65_Pos (1UL)                   /*!< DSP0N0GPIO65 (Bit 1)                                  */
37200 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO65_Msk (0x2UL)                 /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
37201 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO64_Pos (0UL)                   /*!< DSP0N0GPIO64 (Bit 0)                                  */
37202 #define GPIO_DSP0N0INT2SET_DSP0N0GPIO64_Msk (0x1UL)                 /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
37203 /* =====================================================  DSP0N0INT3EN  ====================================================== */
37204 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO127_Pos (31UL)                  /*!< DSP0N0GPIO127 (Bit 31)                                */
37205 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO127_Msk (0x80000000UL)          /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
37206 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO126_Pos (30UL)                  /*!< DSP0N0GPIO126 (Bit 30)                                */
37207 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO126_Msk (0x40000000UL)          /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
37208 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO125_Pos (29UL)                  /*!< DSP0N0GPIO125 (Bit 29)                                */
37209 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO125_Msk (0x20000000UL)          /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
37210 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO124_Pos (28UL)                  /*!< DSP0N0GPIO124 (Bit 28)                                */
37211 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO124_Msk (0x10000000UL)          /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
37212 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO123_Pos (27UL)                  /*!< DSP0N0GPIO123 (Bit 27)                                */
37213 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO123_Msk (0x8000000UL)           /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
37214 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO122_Pos (26UL)                  /*!< DSP0N0GPIO122 (Bit 26)                                */
37215 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO122_Msk (0x4000000UL)           /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
37216 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO121_Pos (25UL)                  /*!< DSP0N0GPIO121 (Bit 25)                                */
37217 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO121_Msk (0x2000000UL)           /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
37218 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO120_Pos (24UL)                  /*!< DSP0N0GPIO120 (Bit 24)                                */
37219 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO120_Msk (0x1000000UL)           /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
37220 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO119_Pos (23UL)                  /*!< DSP0N0GPIO119 (Bit 23)                                */
37221 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO119_Msk (0x800000UL)            /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
37222 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO118_Pos (22UL)                  /*!< DSP0N0GPIO118 (Bit 22)                                */
37223 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO118_Msk (0x400000UL)            /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
37224 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO117_Pos (21UL)                  /*!< DSP0N0GPIO117 (Bit 21)                                */
37225 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO117_Msk (0x200000UL)            /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
37226 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO116_Pos (20UL)                  /*!< DSP0N0GPIO116 (Bit 20)                                */
37227 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO116_Msk (0x100000UL)            /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
37228 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO115_Pos (19UL)                  /*!< DSP0N0GPIO115 (Bit 19)                                */
37229 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO115_Msk (0x80000UL)             /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
37230 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO114_Pos (18UL)                  /*!< DSP0N0GPIO114 (Bit 18)                                */
37231 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO114_Msk (0x40000UL)             /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
37232 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO113_Pos (17UL)                  /*!< DSP0N0GPIO113 (Bit 17)                                */
37233 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO113_Msk (0x20000UL)             /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
37234 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO112_Pos (16UL)                  /*!< DSP0N0GPIO112 (Bit 16)                                */
37235 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO112_Msk (0x10000UL)             /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
37236 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO111_Pos (15UL)                  /*!< DSP0N0GPIO111 (Bit 15)                                */
37237 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO111_Msk (0x8000UL)              /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
37238 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO110_Pos (14UL)                  /*!< DSP0N0GPIO110 (Bit 14)                                */
37239 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO110_Msk (0x4000UL)              /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
37240 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO109_Pos (13UL)                  /*!< DSP0N0GPIO109 (Bit 13)                                */
37241 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO109_Msk (0x2000UL)              /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
37242 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO108_Pos (12UL)                  /*!< DSP0N0GPIO108 (Bit 12)                                */
37243 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO108_Msk (0x1000UL)              /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
37244 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO107_Pos (11UL)                  /*!< DSP0N0GPIO107 (Bit 11)                                */
37245 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO107_Msk (0x800UL)               /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
37246 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO106_Pos (10UL)                  /*!< DSP0N0GPIO106 (Bit 10)                                */
37247 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO106_Msk (0x400UL)               /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
37248 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO105_Pos (9UL)                   /*!< DSP0N0GPIO105 (Bit 9)                                 */
37249 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO105_Msk (0x200UL)               /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
37250 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO104_Pos (8UL)                   /*!< DSP0N0GPIO104 (Bit 8)                                 */
37251 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO104_Msk (0x100UL)               /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
37252 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO103_Pos (7UL)                   /*!< DSP0N0GPIO103 (Bit 7)                                 */
37253 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO103_Msk (0x80UL)                /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
37254 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO102_Pos (6UL)                   /*!< DSP0N0GPIO102 (Bit 6)                                 */
37255 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO102_Msk (0x40UL)                /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
37256 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO101_Pos (5UL)                   /*!< DSP0N0GPIO101 (Bit 5)                                 */
37257 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO101_Msk (0x20UL)                /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
37258 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO100_Pos (4UL)                   /*!< DSP0N0GPIO100 (Bit 4)                                 */
37259 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO100_Msk (0x10UL)                /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
37260 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO99_Pos (3UL)                    /*!< DSP0N0GPIO99 (Bit 3)                                  */
37261 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO99_Msk (0x8UL)                  /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
37262 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO98_Pos (2UL)                    /*!< DSP0N0GPIO98 (Bit 2)                                  */
37263 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO98_Msk (0x4UL)                  /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
37264 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO97_Pos (1UL)                    /*!< DSP0N0GPIO97 (Bit 1)                                  */
37265 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO97_Msk (0x2UL)                  /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
37266 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO96_Pos (0UL)                    /*!< DSP0N0GPIO96 (Bit 0)                                  */
37267 #define GPIO_DSP0N0INT3EN_DSP0N0GPIO96_Msk (0x1UL)                  /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
37268 /* ====================================================  DSP0N0INT3STAT  ===================================================== */
37269 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO127_Pos (31UL)                /*!< DSP0N0GPIO127 (Bit 31)                                */
37270 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO127_Msk (0x80000000UL)        /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
37271 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO126_Pos (30UL)                /*!< DSP0N0GPIO126 (Bit 30)                                */
37272 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO126_Msk (0x40000000UL)        /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
37273 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO125_Pos (29UL)                /*!< DSP0N0GPIO125 (Bit 29)                                */
37274 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO125_Msk (0x20000000UL)        /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
37275 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO124_Pos (28UL)                /*!< DSP0N0GPIO124 (Bit 28)                                */
37276 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO124_Msk (0x10000000UL)        /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
37277 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO123_Pos (27UL)                /*!< DSP0N0GPIO123 (Bit 27)                                */
37278 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO123_Msk (0x8000000UL)         /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
37279 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO122_Pos (26UL)                /*!< DSP0N0GPIO122 (Bit 26)                                */
37280 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO122_Msk (0x4000000UL)         /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
37281 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO121_Pos (25UL)                /*!< DSP0N0GPIO121 (Bit 25)                                */
37282 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO121_Msk (0x2000000UL)         /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
37283 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO120_Pos (24UL)                /*!< DSP0N0GPIO120 (Bit 24)                                */
37284 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO120_Msk (0x1000000UL)         /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
37285 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO119_Pos (23UL)                /*!< DSP0N0GPIO119 (Bit 23)                                */
37286 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO119_Msk (0x800000UL)          /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
37287 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO118_Pos (22UL)                /*!< DSP0N0GPIO118 (Bit 22)                                */
37288 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO118_Msk (0x400000UL)          /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
37289 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO117_Pos (21UL)                /*!< DSP0N0GPIO117 (Bit 21)                                */
37290 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO117_Msk (0x200000UL)          /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
37291 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO116_Pos (20UL)                /*!< DSP0N0GPIO116 (Bit 20)                                */
37292 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO116_Msk (0x100000UL)          /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
37293 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO115_Pos (19UL)                /*!< DSP0N0GPIO115 (Bit 19)                                */
37294 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO115_Msk (0x80000UL)           /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
37295 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO114_Pos (18UL)                /*!< DSP0N0GPIO114 (Bit 18)                                */
37296 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO114_Msk (0x40000UL)           /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
37297 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO113_Pos (17UL)                /*!< DSP0N0GPIO113 (Bit 17)                                */
37298 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO113_Msk (0x20000UL)           /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
37299 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO112_Pos (16UL)                /*!< DSP0N0GPIO112 (Bit 16)                                */
37300 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO112_Msk (0x10000UL)           /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
37301 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO111_Pos (15UL)                /*!< DSP0N0GPIO111 (Bit 15)                                */
37302 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO111_Msk (0x8000UL)            /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
37303 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO110_Pos (14UL)                /*!< DSP0N0GPIO110 (Bit 14)                                */
37304 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO110_Msk (0x4000UL)            /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
37305 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO109_Pos (13UL)                /*!< DSP0N0GPIO109 (Bit 13)                                */
37306 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO109_Msk (0x2000UL)            /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
37307 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO108_Pos (12UL)                /*!< DSP0N0GPIO108 (Bit 12)                                */
37308 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO108_Msk (0x1000UL)            /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
37309 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO107_Pos (11UL)                /*!< DSP0N0GPIO107 (Bit 11)                                */
37310 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO107_Msk (0x800UL)             /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
37311 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO106_Pos (10UL)                /*!< DSP0N0GPIO106 (Bit 10)                                */
37312 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO106_Msk (0x400UL)             /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
37313 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO105_Pos (9UL)                 /*!< DSP0N0GPIO105 (Bit 9)                                 */
37314 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO105_Msk (0x200UL)             /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
37315 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO104_Pos (8UL)                 /*!< DSP0N0GPIO104 (Bit 8)                                 */
37316 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO104_Msk (0x100UL)             /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
37317 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO103_Pos (7UL)                 /*!< DSP0N0GPIO103 (Bit 7)                                 */
37318 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO103_Msk (0x80UL)              /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
37319 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO102_Pos (6UL)                 /*!< DSP0N0GPIO102 (Bit 6)                                 */
37320 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO102_Msk (0x40UL)              /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
37321 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO101_Pos (5UL)                 /*!< DSP0N0GPIO101 (Bit 5)                                 */
37322 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO101_Msk (0x20UL)              /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
37323 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO100_Pos (4UL)                 /*!< DSP0N0GPIO100 (Bit 4)                                 */
37324 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO100_Msk (0x10UL)              /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
37325 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO99_Pos (3UL)                  /*!< DSP0N0GPIO99 (Bit 3)                                  */
37326 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO99_Msk (0x8UL)                /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
37327 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO98_Pos (2UL)                  /*!< DSP0N0GPIO98 (Bit 2)                                  */
37328 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO98_Msk (0x4UL)                /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
37329 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO97_Pos (1UL)                  /*!< DSP0N0GPIO97 (Bit 1)                                  */
37330 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO97_Msk (0x2UL)                /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
37331 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO96_Pos (0UL)                  /*!< DSP0N0GPIO96 (Bit 0)                                  */
37332 #define GPIO_DSP0N0INT3STAT_DSP0N0GPIO96_Msk (0x1UL)                /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
37333 /* =====================================================  DSP0N0INT3CLR  ===================================================== */
37334 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO127_Pos (31UL)                 /*!< DSP0N0GPIO127 (Bit 31)                                */
37335 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO127_Msk (0x80000000UL)         /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
37336 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO126_Pos (30UL)                 /*!< DSP0N0GPIO126 (Bit 30)                                */
37337 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO126_Msk (0x40000000UL)         /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
37338 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO125_Pos (29UL)                 /*!< DSP0N0GPIO125 (Bit 29)                                */
37339 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO125_Msk (0x20000000UL)         /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
37340 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO124_Pos (28UL)                 /*!< DSP0N0GPIO124 (Bit 28)                                */
37341 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO124_Msk (0x10000000UL)         /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
37342 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO123_Pos (27UL)                 /*!< DSP0N0GPIO123 (Bit 27)                                */
37343 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO123_Msk (0x8000000UL)          /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
37344 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO122_Pos (26UL)                 /*!< DSP0N0GPIO122 (Bit 26)                                */
37345 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO122_Msk (0x4000000UL)          /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
37346 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO121_Pos (25UL)                 /*!< DSP0N0GPIO121 (Bit 25)                                */
37347 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO121_Msk (0x2000000UL)          /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
37348 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO120_Pos (24UL)                 /*!< DSP0N0GPIO120 (Bit 24)                                */
37349 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO120_Msk (0x1000000UL)          /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
37350 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO119_Pos (23UL)                 /*!< DSP0N0GPIO119 (Bit 23)                                */
37351 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO119_Msk (0x800000UL)           /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
37352 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO118_Pos (22UL)                 /*!< DSP0N0GPIO118 (Bit 22)                                */
37353 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO118_Msk (0x400000UL)           /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
37354 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO117_Pos (21UL)                 /*!< DSP0N0GPIO117 (Bit 21)                                */
37355 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO117_Msk (0x200000UL)           /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
37356 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO116_Pos (20UL)                 /*!< DSP0N0GPIO116 (Bit 20)                                */
37357 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO116_Msk (0x100000UL)           /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
37358 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO115_Pos (19UL)                 /*!< DSP0N0GPIO115 (Bit 19)                                */
37359 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO115_Msk (0x80000UL)            /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
37360 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO114_Pos (18UL)                 /*!< DSP0N0GPIO114 (Bit 18)                                */
37361 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO114_Msk (0x40000UL)            /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
37362 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO113_Pos (17UL)                 /*!< DSP0N0GPIO113 (Bit 17)                                */
37363 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO113_Msk (0x20000UL)            /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
37364 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO112_Pos (16UL)                 /*!< DSP0N0GPIO112 (Bit 16)                                */
37365 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO112_Msk (0x10000UL)            /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
37366 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO111_Pos (15UL)                 /*!< DSP0N0GPIO111 (Bit 15)                                */
37367 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO111_Msk (0x8000UL)             /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
37368 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO110_Pos (14UL)                 /*!< DSP0N0GPIO110 (Bit 14)                                */
37369 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO110_Msk (0x4000UL)             /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
37370 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO109_Pos (13UL)                 /*!< DSP0N0GPIO109 (Bit 13)                                */
37371 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO109_Msk (0x2000UL)             /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
37372 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO108_Pos (12UL)                 /*!< DSP0N0GPIO108 (Bit 12)                                */
37373 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO108_Msk (0x1000UL)             /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
37374 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO107_Pos (11UL)                 /*!< DSP0N0GPIO107 (Bit 11)                                */
37375 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO107_Msk (0x800UL)              /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
37376 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO106_Pos (10UL)                 /*!< DSP0N0GPIO106 (Bit 10)                                */
37377 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO106_Msk (0x400UL)              /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
37378 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO105_Pos (9UL)                  /*!< DSP0N0GPIO105 (Bit 9)                                 */
37379 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO105_Msk (0x200UL)              /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
37380 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO104_Pos (8UL)                  /*!< DSP0N0GPIO104 (Bit 8)                                 */
37381 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO104_Msk (0x100UL)              /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
37382 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO103_Pos (7UL)                  /*!< DSP0N0GPIO103 (Bit 7)                                 */
37383 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO103_Msk (0x80UL)               /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
37384 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO102_Pos (6UL)                  /*!< DSP0N0GPIO102 (Bit 6)                                 */
37385 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO102_Msk (0x40UL)               /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
37386 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO101_Pos (5UL)                  /*!< DSP0N0GPIO101 (Bit 5)                                 */
37387 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO101_Msk (0x20UL)               /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
37388 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO100_Pos (4UL)                  /*!< DSP0N0GPIO100 (Bit 4)                                 */
37389 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO100_Msk (0x10UL)               /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
37390 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO99_Pos (3UL)                   /*!< DSP0N0GPIO99 (Bit 3)                                  */
37391 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO99_Msk (0x8UL)                 /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
37392 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO98_Pos (2UL)                   /*!< DSP0N0GPIO98 (Bit 2)                                  */
37393 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO98_Msk (0x4UL)                 /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
37394 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO97_Pos (1UL)                   /*!< DSP0N0GPIO97 (Bit 1)                                  */
37395 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO97_Msk (0x2UL)                 /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
37396 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO96_Pos (0UL)                   /*!< DSP0N0GPIO96 (Bit 0)                                  */
37397 #define GPIO_DSP0N0INT3CLR_DSP0N0GPIO96_Msk (0x1UL)                 /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
37398 /* =====================================================  DSP0N0INT3SET  ===================================================== */
37399 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO127_Pos (31UL)                 /*!< DSP0N0GPIO127 (Bit 31)                                */
37400 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO127_Msk (0x80000000UL)         /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
37401 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO126_Pos (30UL)                 /*!< DSP0N0GPIO126 (Bit 30)                                */
37402 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO126_Msk (0x40000000UL)         /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
37403 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO125_Pos (29UL)                 /*!< DSP0N0GPIO125 (Bit 29)                                */
37404 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO125_Msk (0x20000000UL)         /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
37405 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO124_Pos (28UL)                 /*!< DSP0N0GPIO124 (Bit 28)                                */
37406 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO124_Msk (0x10000000UL)         /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
37407 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO123_Pos (27UL)                 /*!< DSP0N0GPIO123 (Bit 27)                                */
37408 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO123_Msk (0x8000000UL)          /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
37409 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO122_Pos (26UL)                 /*!< DSP0N0GPIO122 (Bit 26)                                */
37410 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO122_Msk (0x4000000UL)          /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
37411 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO121_Pos (25UL)                 /*!< DSP0N0GPIO121 (Bit 25)                                */
37412 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO121_Msk (0x2000000UL)          /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
37413 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO120_Pos (24UL)                 /*!< DSP0N0GPIO120 (Bit 24)                                */
37414 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO120_Msk (0x1000000UL)          /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
37415 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO119_Pos (23UL)                 /*!< DSP0N0GPIO119 (Bit 23)                                */
37416 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO119_Msk (0x800000UL)           /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
37417 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO118_Pos (22UL)                 /*!< DSP0N0GPIO118 (Bit 22)                                */
37418 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO118_Msk (0x400000UL)           /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
37419 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO117_Pos (21UL)                 /*!< DSP0N0GPIO117 (Bit 21)                                */
37420 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO117_Msk (0x200000UL)           /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
37421 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO116_Pos (20UL)                 /*!< DSP0N0GPIO116 (Bit 20)                                */
37422 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO116_Msk (0x100000UL)           /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
37423 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO115_Pos (19UL)                 /*!< DSP0N0GPIO115 (Bit 19)                                */
37424 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO115_Msk (0x80000UL)            /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
37425 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO114_Pos (18UL)                 /*!< DSP0N0GPIO114 (Bit 18)                                */
37426 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO114_Msk (0x40000UL)            /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
37427 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO113_Pos (17UL)                 /*!< DSP0N0GPIO113 (Bit 17)                                */
37428 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO113_Msk (0x20000UL)            /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
37429 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO112_Pos (16UL)                 /*!< DSP0N0GPIO112 (Bit 16)                                */
37430 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO112_Msk (0x10000UL)            /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
37431 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO111_Pos (15UL)                 /*!< DSP0N0GPIO111 (Bit 15)                                */
37432 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO111_Msk (0x8000UL)             /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
37433 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO110_Pos (14UL)                 /*!< DSP0N0GPIO110 (Bit 14)                                */
37434 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO110_Msk (0x4000UL)             /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
37435 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO109_Pos (13UL)                 /*!< DSP0N0GPIO109 (Bit 13)                                */
37436 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO109_Msk (0x2000UL)             /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
37437 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO108_Pos (12UL)                 /*!< DSP0N0GPIO108 (Bit 12)                                */
37438 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO108_Msk (0x1000UL)             /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
37439 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO107_Pos (11UL)                 /*!< DSP0N0GPIO107 (Bit 11)                                */
37440 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO107_Msk (0x800UL)              /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
37441 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO106_Pos (10UL)                 /*!< DSP0N0GPIO106 (Bit 10)                                */
37442 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO106_Msk (0x400UL)              /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
37443 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO105_Pos (9UL)                  /*!< DSP0N0GPIO105 (Bit 9)                                 */
37444 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO105_Msk (0x200UL)              /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
37445 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO104_Pos (8UL)                  /*!< DSP0N0GPIO104 (Bit 8)                                 */
37446 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO104_Msk (0x100UL)              /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
37447 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO103_Pos (7UL)                  /*!< DSP0N0GPIO103 (Bit 7)                                 */
37448 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO103_Msk (0x80UL)               /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
37449 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO102_Pos (6UL)                  /*!< DSP0N0GPIO102 (Bit 6)                                 */
37450 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO102_Msk (0x40UL)               /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
37451 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO101_Pos (5UL)                  /*!< DSP0N0GPIO101 (Bit 5)                                 */
37452 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO101_Msk (0x20UL)               /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
37453 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO100_Pos (4UL)                  /*!< DSP0N0GPIO100 (Bit 4)                                 */
37454 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO100_Msk (0x10UL)               /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
37455 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO99_Pos (3UL)                   /*!< DSP0N0GPIO99 (Bit 3)                                  */
37456 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO99_Msk (0x8UL)                 /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
37457 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO98_Pos (2UL)                   /*!< DSP0N0GPIO98 (Bit 2)                                  */
37458 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO98_Msk (0x4UL)                 /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
37459 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO97_Pos (1UL)                   /*!< DSP0N0GPIO97 (Bit 1)                                  */
37460 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO97_Msk (0x2UL)                 /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
37461 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO96_Pos (0UL)                   /*!< DSP0N0GPIO96 (Bit 0)                                  */
37462 #define GPIO_DSP0N0INT3SET_DSP0N0GPIO96_Msk (0x1UL)                 /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
37463 /* =====================================================  DSP0N1INT0EN  ====================================================== */
37464 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO31_Pos (31UL)                   /*!< DSP0N1GPIO31 (Bit 31)                                 */
37465 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO31_Msk (0x80000000UL)           /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
37466 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO30_Pos (30UL)                   /*!< DSP0N1GPIO30 (Bit 30)                                 */
37467 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO30_Msk (0x40000000UL)           /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
37468 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO29_Pos (29UL)                   /*!< DSP0N1GPIO29 (Bit 29)                                 */
37469 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO29_Msk (0x20000000UL)           /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
37470 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO28_Pos (28UL)                   /*!< DSP0N1GPIO28 (Bit 28)                                 */
37471 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO28_Msk (0x10000000UL)           /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
37472 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO27_Pos (27UL)                   /*!< DSP0N1GPIO27 (Bit 27)                                 */
37473 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO27_Msk (0x8000000UL)            /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
37474 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO26_Pos (26UL)                   /*!< DSP0N1GPIO26 (Bit 26)                                 */
37475 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO26_Msk (0x4000000UL)            /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
37476 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO25_Pos (25UL)                   /*!< DSP0N1GPIO25 (Bit 25)                                 */
37477 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO25_Msk (0x2000000UL)            /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
37478 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO24_Pos (24UL)                   /*!< DSP0N1GPIO24 (Bit 24)                                 */
37479 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO24_Msk (0x1000000UL)            /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
37480 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO23_Pos (23UL)                   /*!< DSP0N1GPIO23 (Bit 23)                                 */
37481 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO23_Msk (0x800000UL)             /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
37482 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO22_Pos (22UL)                   /*!< DSP0N1GPIO22 (Bit 22)                                 */
37483 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO22_Msk (0x400000UL)             /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
37484 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO21_Pos (21UL)                   /*!< DSP0N1GPIO21 (Bit 21)                                 */
37485 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO21_Msk (0x200000UL)             /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
37486 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO20_Pos (20UL)                   /*!< DSP0N1GPIO20 (Bit 20)                                 */
37487 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO20_Msk (0x100000UL)             /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
37488 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO19_Pos (19UL)                   /*!< DSP0N1GPIO19 (Bit 19)                                 */
37489 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO19_Msk (0x80000UL)              /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
37490 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO18_Pos (18UL)                   /*!< DSP0N1GPIO18 (Bit 18)                                 */
37491 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO18_Msk (0x40000UL)              /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
37492 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO17_Pos (17UL)                   /*!< DSP0N1GPIO17 (Bit 17)                                 */
37493 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO17_Msk (0x20000UL)              /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
37494 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO16_Pos (16UL)                   /*!< DSP0N1GPIO16 (Bit 16)                                 */
37495 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO16_Msk (0x10000UL)              /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
37496 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO15_Pos (15UL)                   /*!< DSP0N1GPIO15 (Bit 15)                                 */
37497 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO15_Msk (0x8000UL)               /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
37498 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO14_Pos (14UL)                   /*!< DSP0N1GPIO14 (Bit 14)                                 */
37499 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO14_Msk (0x4000UL)               /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
37500 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO13_Pos (13UL)                   /*!< DSP0N1GPIO13 (Bit 13)                                 */
37501 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO13_Msk (0x2000UL)               /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
37502 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO12_Pos (12UL)                   /*!< DSP0N1GPIO12 (Bit 12)                                 */
37503 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO12_Msk (0x1000UL)               /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
37504 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO11_Pos (11UL)                   /*!< DSP0N1GPIO11 (Bit 11)                                 */
37505 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO11_Msk (0x800UL)                /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
37506 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO10_Pos (10UL)                   /*!< DSP0N1GPIO10 (Bit 10)                                 */
37507 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO10_Msk (0x400UL)                /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
37508 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO9_Pos (9UL)                     /*!< DSP0N1GPIO9 (Bit 9)                                   */
37509 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO9_Msk (0x200UL)                 /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
37510 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO8_Pos (8UL)                     /*!< DSP0N1GPIO8 (Bit 8)                                   */
37511 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO8_Msk (0x100UL)                 /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
37512 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO7_Pos (7UL)                     /*!< DSP0N1GPIO7 (Bit 7)                                   */
37513 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO7_Msk (0x80UL)                  /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
37514 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO6_Pos (6UL)                     /*!< DSP0N1GPIO6 (Bit 6)                                   */
37515 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO6_Msk (0x40UL)                  /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
37516 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO5_Pos (5UL)                     /*!< DSP0N1GPIO5 (Bit 5)                                   */
37517 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO5_Msk (0x20UL)                  /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
37518 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO4_Pos (4UL)                     /*!< DSP0N1GPIO4 (Bit 4)                                   */
37519 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO4_Msk (0x10UL)                  /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
37520 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO3_Pos (3UL)                     /*!< DSP0N1GPIO3 (Bit 3)                                   */
37521 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO3_Msk (0x8UL)                   /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
37522 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO2_Pos (2UL)                     /*!< DSP0N1GPIO2 (Bit 2)                                   */
37523 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO2_Msk (0x4UL)                   /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
37524 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO1_Pos (1UL)                     /*!< DSP0N1GPIO1 (Bit 1)                                   */
37525 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO1_Msk (0x2UL)                   /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
37526 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO0_Pos (0UL)                     /*!< DSP0N1GPIO0 (Bit 0)                                   */
37527 #define GPIO_DSP0N1INT0EN_DSP0N1GPIO0_Msk (0x1UL)                   /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
37528 /* ====================================================  DSP0N1INT0STAT  ===================================================== */
37529 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO31_Pos (31UL)                 /*!< DSP0N1GPIO31 (Bit 31)                                 */
37530 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO31_Msk (0x80000000UL)         /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
37531 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO30_Pos (30UL)                 /*!< DSP0N1GPIO30 (Bit 30)                                 */
37532 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO30_Msk (0x40000000UL)         /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
37533 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO29_Pos (29UL)                 /*!< DSP0N1GPIO29 (Bit 29)                                 */
37534 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO29_Msk (0x20000000UL)         /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
37535 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO28_Pos (28UL)                 /*!< DSP0N1GPIO28 (Bit 28)                                 */
37536 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO28_Msk (0x10000000UL)         /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
37537 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO27_Pos (27UL)                 /*!< DSP0N1GPIO27 (Bit 27)                                 */
37538 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO27_Msk (0x8000000UL)          /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
37539 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO26_Pos (26UL)                 /*!< DSP0N1GPIO26 (Bit 26)                                 */
37540 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO26_Msk (0x4000000UL)          /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
37541 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO25_Pos (25UL)                 /*!< DSP0N1GPIO25 (Bit 25)                                 */
37542 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO25_Msk (0x2000000UL)          /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
37543 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO24_Pos (24UL)                 /*!< DSP0N1GPIO24 (Bit 24)                                 */
37544 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO24_Msk (0x1000000UL)          /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
37545 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO23_Pos (23UL)                 /*!< DSP0N1GPIO23 (Bit 23)                                 */
37546 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO23_Msk (0x800000UL)           /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
37547 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO22_Pos (22UL)                 /*!< DSP0N1GPIO22 (Bit 22)                                 */
37548 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO22_Msk (0x400000UL)           /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
37549 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO21_Pos (21UL)                 /*!< DSP0N1GPIO21 (Bit 21)                                 */
37550 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO21_Msk (0x200000UL)           /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
37551 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO20_Pos (20UL)                 /*!< DSP0N1GPIO20 (Bit 20)                                 */
37552 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO20_Msk (0x100000UL)           /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
37553 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO19_Pos (19UL)                 /*!< DSP0N1GPIO19 (Bit 19)                                 */
37554 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO19_Msk (0x80000UL)            /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
37555 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO18_Pos (18UL)                 /*!< DSP0N1GPIO18 (Bit 18)                                 */
37556 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO18_Msk (0x40000UL)            /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
37557 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO17_Pos (17UL)                 /*!< DSP0N1GPIO17 (Bit 17)                                 */
37558 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO17_Msk (0x20000UL)            /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
37559 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO16_Pos (16UL)                 /*!< DSP0N1GPIO16 (Bit 16)                                 */
37560 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO16_Msk (0x10000UL)            /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
37561 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO15_Pos (15UL)                 /*!< DSP0N1GPIO15 (Bit 15)                                 */
37562 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO15_Msk (0x8000UL)             /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
37563 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO14_Pos (14UL)                 /*!< DSP0N1GPIO14 (Bit 14)                                 */
37564 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO14_Msk (0x4000UL)             /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
37565 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO13_Pos (13UL)                 /*!< DSP0N1GPIO13 (Bit 13)                                 */
37566 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO13_Msk (0x2000UL)             /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
37567 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO12_Pos (12UL)                 /*!< DSP0N1GPIO12 (Bit 12)                                 */
37568 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO12_Msk (0x1000UL)             /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
37569 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO11_Pos (11UL)                 /*!< DSP0N1GPIO11 (Bit 11)                                 */
37570 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO11_Msk (0x800UL)              /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
37571 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO10_Pos (10UL)                 /*!< DSP0N1GPIO10 (Bit 10)                                 */
37572 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO10_Msk (0x400UL)              /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
37573 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO9_Pos (9UL)                   /*!< DSP0N1GPIO9 (Bit 9)                                   */
37574 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO9_Msk (0x200UL)               /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
37575 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO8_Pos (8UL)                   /*!< DSP0N1GPIO8 (Bit 8)                                   */
37576 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO8_Msk (0x100UL)               /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
37577 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO7_Pos (7UL)                   /*!< DSP0N1GPIO7 (Bit 7)                                   */
37578 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO7_Msk (0x80UL)                /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
37579 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO6_Pos (6UL)                   /*!< DSP0N1GPIO6 (Bit 6)                                   */
37580 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO6_Msk (0x40UL)                /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
37581 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO5_Pos (5UL)                   /*!< DSP0N1GPIO5 (Bit 5)                                   */
37582 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO5_Msk (0x20UL)                /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
37583 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO4_Pos (4UL)                   /*!< DSP0N1GPIO4 (Bit 4)                                   */
37584 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO4_Msk (0x10UL)                /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
37585 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO3_Pos (3UL)                   /*!< DSP0N1GPIO3 (Bit 3)                                   */
37586 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO3_Msk (0x8UL)                 /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
37587 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO2_Pos (2UL)                   /*!< DSP0N1GPIO2 (Bit 2)                                   */
37588 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO2_Msk (0x4UL)                 /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
37589 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO1_Pos (1UL)                   /*!< DSP0N1GPIO1 (Bit 1)                                   */
37590 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO1_Msk (0x2UL)                 /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
37591 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO0_Pos (0UL)                   /*!< DSP0N1GPIO0 (Bit 0)                                   */
37592 #define GPIO_DSP0N1INT0STAT_DSP0N1GPIO0_Msk (0x1UL)                 /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
37593 /* =====================================================  DSP0N1INT0CLR  ===================================================== */
37594 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO31_Pos (31UL)                  /*!< DSP0N1GPIO31 (Bit 31)                                 */
37595 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO31_Msk (0x80000000UL)          /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
37596 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO30_Pos (30UL)                  /*!< DSP0N1GPIO30 (Bit 30)                                 */
37597 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO30_Msk (0x40000000UL)          /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
37598 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO29_Pos (29UL)                  /*!< DSP0N1GPIO29 (Bit 29)                                 */
37599 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO29_Msk (0x20000000UL)          /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
37600 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO28_Pos (28UL)                  /*!< DSP0N1GPIO28 (Bit 28)                                 */
37601 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO28_Msk (0x10000000UL)          /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
37602 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO27_Pos (27UL)                  /*!< DSP0N1GPIO27 (Bit 27)                                 */
37603 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO27_Msk (0x8000000UL)           /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
37604 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO26_Pos (26UL)                  /*!< DSP0N1GPIO26 (Bit 26)                                 */
37605 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO26_Msk (0x4000000UL)           /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
37606 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO25_Pos (25UL)                  /*!< DSP0N1GPIO25 (Bit 25)                                 */
37607 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO25_Msk (0x2000000UL)           /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
37608 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO24_Pos (24UL)                  /*!< DSP0N1GPIO24 (Bit 24)                                 */
37609 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO24_Msk (0x1000000UL)           /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
37610 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO23_Pos (23UL)                  /*!< DSP0N1GPIO23 (Bit 23)                                 */
37611 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO23_Msk (0x800000UL)            /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
37612 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO22_Pos (22UL)                  /*!< DSP0N1GPIO22 (Bit 22)                                 */
37613 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO22_Msk (0x400000UL)            /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
37614 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO21_Pos (21UL)                  /*!< DSP0N1GPIO21 (Bit 21)                                 */
37615 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO21_Msk (0x200000UL)            /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
37616 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO20_Pos (20UL)                  /*!< DSP0N1GPIO20 (Bit 20)                                 */
37617 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO20_Msk (0x100000UL)            /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
37618 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO19_Pos (19UL)                  /*!< DSP0N1GPIO19 (Bit 19)                                 */
37619 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO19_Msk (0x80000UL)             /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
37620 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO18_Pos (18UL)                  /*!< DSP0N1GPIO18 (Bit 18)                                 */
37621 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO18_Msk (0x40000UL)             /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
37622 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO17_Pos (17UL)                  /*!< DSP0N1GPIO17 (Bit 17)                                 */
37623 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO17_Msk (0x20000UL)             /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
37624 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO16_Pos (16UL)                  /*!< DSP0N1GPIO16 (Bit 16)                                 */
37625 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO16_Msk (0x10000UL)             /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
37626 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO15_Pos (15UL)                  /*!< DSP0N1GPIO15 (Bit 15)                                 */
37627 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO15_Msk (0x8000UL)              /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
37628 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO14_Pos (14UL)                  /*!< DSP0N1GPIO14 (Bit 14)                                 */
37629 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO14_Msk (0x4000UL)              /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
37630 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO13_Pos (13UL)                  /*!< DSP0N1GPIO13 (Bit 13)                                 */
37631 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO13_Msk (0x2000UL)              /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
37632 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO12_Pos (12UL)                  /*!< DSP0N1GPIO12 (Bit 12)                                 */
37633 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO12_Msk (0x1000UL)              /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
37634 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO11_Pos (11UL)                  /*!< DSP0N1GPIO11 (Bit 11)                                 */
37635 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO11_Msk (0x800UL)               /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
37636 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO10_Pos (10UL)                  /*!< DSP0N1GPIO10 (Bit 10)                                 */
37637 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO10_Msk (0x400UL)               /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
37638 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO9_Pos (9UL)                    /*!< DSP0N1GPIO9 (Bit 9)                                   */
37639 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO9_Msk (0x200UL)                /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
37640 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO8_Pos (8UL)                    /*!< DSP0N1GPIO8 (Bit 8)                                   */
37641 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO8_Msk (0x100UL)                /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
37642 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO7_Pos (7UL)                    /*!< DSP0N1GPIO7 (Bit 7)                                   */
37643 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO7_Msk (0x80UL)                 /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
37644 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO6_Pos (6UL)                    /*!< DSP0N1GPIO6 (Bit 6)                                   */
37645 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO6_Msk (0x40UL)                 /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
37646 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO5_Pos (5UL)                    /*!< DSP0N1GPIO5 (Bit 5)                                   */
37647 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO5_Msk (0x20UL)                 /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
37648 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO4_Pos (4UL)                    /*!< DSP0N1GPIO4 (Bit 4)                                   */
37649 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO4_Msk (0x10UL)                 /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
37650 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO3_Pos (3UL)                    /*!< DSP0N1GPIO3 (Bit 3)                                   */
37651 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO3_Msk (0x8UL)                  /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
37652 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO2_Pos (2UL)                    /*!< DSP0N1GPIO2 (Bit 2)                                   */
37653 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO2_Msk (0x4UL)                  /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
37654 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO1_Pos (1UL)                    /*!< DSP0N1GPIO1 (Bit 1)                                   */
37655 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO1_Msk (0x2UL)                  /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
37656 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO0_Pos (0UL)                    /*!< DSP0N1GPIO0 (Bit 0)                                   */
37657 #define GPIO_DSP0N1INT0CLR_DSP0N1GPIO0_Msk (0x1UL)                  /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
37658 /* =====================================================  DSP0N1INT0SET  ===================================================== */
37659 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO31_Pos (31UL)                  /*!< DSP0N1GPIO31 (Bit 31)                                 */
37660 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO31_Msk (0x80000000UL)          /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
37661 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO30_Pos (30UL)                  /*!< DSP0N1GPIO30 (Bit 30)                                 */
37662 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO30_Msk (0x40000000UL)          /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
37663 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO29_Pos (29UL)                  /*!< DSP0N1GPIO29 (Bit 29)                                 */
37664 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO29_Msk (0x20000000UL)          /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
37665 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO28_Pos (28UL)                  /*!< DSP0N1GPIO28 (Bit 28)                                 */
37666 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO28_Msk (0x10000000UL)          /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
37667 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO27_Pos (27UL)                  /*!< DSP0N1GPIO27 (Bit 27)                                 */
37668 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO27_Msk (0x8000000UL)           /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
37669 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO26_Pos (26UL)                  /*!< DSP0N1GPIO26 (Bit 26)                                 */
37670 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO26_Msk (0x4000000UL)           /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
37671 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO25_Pos (25UL)                  /*!< DSP0N1GPIO25 (Bit 25)                                 */
37672 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO25_Msk (0x2000000UL)           /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
37673 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO24_Pos (24UL)                  /*!< DSP0N1GPIO24 (Bit 24)                                 */
37674 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO24_Msk (0x1000000UL)           /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
37675 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO23_Pos (23UL)                  /*!< DSP0N1GPIO23 (Bit 23)                                 */
37676 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO23_Msk (0x800000UL)            /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
37677 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO22_Pos (22UL)                  /*!< DSP0N1GPIO22 (Bit 22)                                 */
37678 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO22_Msk (0x400000UL)            /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
37679 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO21_Pos (21UL)                  /*!< DSP0N1GPIO21 (Bit 21)                                 */
37680 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO21_Msk (0x200000UL)            /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
37681 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO20_Pos (20UL)                  /*!< DSP0N1GPIO20 (Bit 20)                                 */
37682 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO20_Msk (0x100000UL)            /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
37683 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO19_Pos (19UL)                  /*!< DSP0N1GPIO19 (Bit 19)                                 */
37684 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO19_Msk (0x80000UL)             /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
37685 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO18_Pos (18UL)                  /*!< DSP0N1GPIO18 (Bit 18)                                 */
37686 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO18_Msk (0x40000UL)             /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
37687 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO17_Pos (17UL)                  /*!< DSP0N1GPIO17 (Bit 17)                                 */
37688 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO17_Msk (0x20000UL)             /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
37689 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO16_Pos (16UL)                  /*!< DSP0N1GPIO16 (Bit 16)                                 */
37690 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO16_Msk (0x10000UL)             /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
37691 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO15_Pos (15UL)                  /*!< DSP0N1GPIO15 (Bit 15)                                 */
37692 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO15_Msk (0x8000UL)              /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
37693 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO14_Pos (14UL)                  /*!< DSP0N1GPIO14 (Bit 14)                                 */
37694 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO14_Msk (0x4000UL)              /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
37695 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO13_Pos (13UL)                  /*!< DSP0N1GPIO13 (Bit 13)                                 */
37696 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO13_Msk (0x2000UL)              /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
37697 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO12_Pos (12UL)                  /*!< DSP0N1GPIO12 (Bit 12)                                 */
37698 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO12_Msk (0x1000UL)              /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
37699 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO11_Pos (11UL)                  /*!< DSP0N1GPIO11 (Bit 11)                                 */
37700 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO11_Msk (0x800UL)               /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
37701 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO10_Pos (10UL)                  /*!< DSP0N1GPIO10 (Bit 10)                                 */
37702 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO10_Msk (0x400UL)               /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
37703 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO9_Pos (9UL)                    /*!< DSP0N1GPIO9 (Bit 9)                                   */
37704 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO9_Msk (0x200UL)                /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
37705 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO8_Pos (8UL)                    /*!< DSP0N1GPIO8 (Bit 8)                                   */
37706 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO8_Msk (0x100UL)                /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
37707 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO7_Pos (7UL)                    /*!< DSP0N1GPIO7 (Bit 7)                                   */
37708 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO7_Msk (0x80UL)                 /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
37709 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO6_Pos (6UL)                    /*!< DSP0N1GPIO6 (Bit 6)                                   */
37710 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO6_Msk (0x40UL)                 /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
37711 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO5_Pos (5UL)                    /*!< DSP0N1GPIO5 (Bit 5)                                   */
37712 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO5_Msk (0x20UL)                 /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
37713 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO4_Pos (4UL)                    /*!< DSP0N1GPIO4 (Bit 4)                                   */
37714 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO4_Msk (0x10UL)                 /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
37715 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO3_Pos (3UL)                    /*!< DSP0N1GPIO3 (Bit 3)                                   */
37716 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO3_Msk (0x8UL)                  /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
37717 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO2_Pos (2UL)                    /*!< DSP0N1GPIO2 (Bit 2)                                   */
37718 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO2_Msk (0x4UL)                  /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
37719 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO1_Pos (1UL)                    /*!< DSP0N1GPIO1 (Bit 1)                                   */
37720 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO1_Msk (0x2UL)                  /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
37721 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO0_Pos (0UL)                    /*!< DSP0N1GPIO0 (Bit 0)                                   */
37722 #define GPIO_DSP0N1INT0SET_DSP0N1GPIO0_Msk (0x1UL)                  /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
37723 /* =====================================================  DSP0N1INT1EN  ====================================================== */
37724 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO63_Pos (31UL)                   /*!< DSP0N1GPIO63 (Bit 31)                                 */
37725 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO63_Msk (0x80000000UL)           /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
37726 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO62_Pos (30UL)                   /*!< DSP0N1GPIO62 (Bit 30)                                 */
37727 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO62_Msk (0x40000000UL)           /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
37728 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO61_Pos (29UL)                   /*!< DSP0N1GPIO61 (Bit 29)                                 */
37729 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO61_Msk (0x20000000UL)           /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
37730 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO60_Pos (28UL)                   /*!< DSP0N1GPIO60 (Bit 28)                                 */
37731 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO60_Msk (0x10000000UL)           /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
37732 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO59_Pos (27UL)                   /*!< DSP0N1GPIO59 (Bit 27)                                 */
37733 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO59_Msk (0x8000000UL)            /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
37734 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO58_Pos (26UL)                   /*!< DSP0N1GPIO58 (Bit 26)                                 */
37735 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO58_Msk (0x4000000UL)            /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
37736 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO57_Pos (25UL)                   /*!< DSP0N1GPIO57 (Bit 25)                                 */
37737 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO57_Msk (0x2000000UL)            /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
37738 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO56_Pos (24UL)                   /*!< DSP0N1GPIO56 (Bit 24)                                 */
37739 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO56_Msk (0x1000000UL)            /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
37740 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO55_Pos (23UL)                   /*!< DSP0N1GPIO55 (Bit 23)                                 */
37741 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO55_Msk (0x800000UL)             /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
37742 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO54_Pos (22UL)                   /*!< DSP0N1GPIO54 (Bit 22)                                 */
37743 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO54_Msk (0x400000UL)             /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
37744 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO53_Pos (21UL)                   /*!< DSP0N1GPIO53 (Bit 21)                                 */
37745 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO53_Msk (0x200000UL)             /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
37746 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO52_Pos (20UL)                   /*!< DSP0N1GPIO52 (Bit 20)                                 */
37747 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO52_Msk (0x100000UL)             /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
37748 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO51_Pos (19UL)                   /*!< DSP0N1GPIO51 (Bit 19)                                 */
37749 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO51_Msk (0x80000UL)              /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
37750 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO50_Pos (18UL)                   /*!< DSP0N1GPIO50 (Bit 18)                                 */
37751 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO50_Msk (0x40000UL)              /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
37752 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO49_Pos (17UL)                   /*!< DSP0N1GPIO49 (Bit 17)                                 */
37753 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO49_Msk (0x20000UL)              /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
37754 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO48_Pos (16UL)                   /*!< DSP0N1GPIO48 (Bit 16)                                 */
37755 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO48_Msk (0x10000UL)              /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
37756 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO47_Pos (15UL)                   /*!< DSP0N1GPIO47 (Bit 15)                                 */
37757 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO47_Msk (0x8000UL)               /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
37758 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO46_Pos (14UL)                   /*!< DSP0N1GPIO46 (Bit 14)                                 */
37759 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO46_Msk (0x4000UL)               /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
37760 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO45_Pos (13UL)                   /*!< DSP0N1GPIO45 (Bit 13)                                 */
37761 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO45_Msk (0x2000UL)               /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
37762 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO44_Pos (12UL)                   /*!< DSP0N1GPIO44 (Bit 12)                                 */
37763 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO44_Msk (0x1000UL)               /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
37764 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO43_Pos (11UL)                   /*!< DSP0N1GPIO43 (Bit 11)                                 */
37765 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO43_Msk (0x800UL)                /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
37766 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO42_Pos (10UL)                   /*!< DSP0N1GPIO42 (Bit 10)                                 */
37767 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO42_Msk (0x400UL)                /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
37768 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO41_Pos (9UL)                    /*!< DSP0N1GPIO41 (Bit 9)                                  */
37769 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO41_Msk (0x200UL)                /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
37770 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO40_Pos (8UL)                    /*!< DSP0N1GPIO40 (Bit 8)                                  */
37771 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO40_Msk (0x100UL)                /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
37772 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO39_Pos (7UL)                    /*!< DSP0N1GPIO39 (Bit 7)                                  */
37773 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO39_Msk (0x80UL)                 /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
37774 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO38_Pos (6UL)                    /*!< DSP0N1GPIO38 (Bit 6)                                  */
37775 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO38_Msk (0x40UL)                 /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
37776 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO37_Pos (5UL)                    /*!< DSP0N1GPIO37 (Bit 5)                                  */
37777 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO37_Msk (0x20UL)                 /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
37778 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO36_Pos (4UL)                    /*!< DSP0N1GPIO36 (Bit 4)                                  */
37779 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO36_Msk (0x10UL)                 /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
37780 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO35_Pos (3UL)                    /*!< DSP0N1GPIO35 (Bit 3)                                  */
37781 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO35_Msk (0x8UL)                  /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
37782 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO34_Pos (2UL)                    /*!< DSP0N1GPIO34 (Bit 2)                                  */
37783 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO34_Msk (0x4UL)                  /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
37784 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO33_Pos (1UL)                    /*!< DSP0N1GPIO33 (Bit 1)                                  */
37785 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO33_Msk (0x2UL)                  /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
37786 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO32_Pos (0UL)                    /*!< DSP0N1GPIO32 (Bit 0)                                  */
37787 #define GPIO_DSP0N1INT1EN_DSP0N1GPIO32_Msk (0x1UL)                  /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
37788 /* ====================================================  DSP0N1INT1STAT  ===================================================== */
37789 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO63_Pos (31UL)                 /*!< DSP0N1GPIO63 (Bit 31)                                 */
37790 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO63_Msk (0x80000000UL)         /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
37791 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO62_Pos (30UL)                 /*!< DSP0N1GPIO62 (Bit 30)                                 */
37792 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO62_Msk (0x40000000UL)         /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
37793 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO61_Pos (29UL)                 /*!< DSP0N1GPIO61 (Bit 29)                                 */
37794 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO61_Msk (0x20000000UL)         /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
37795 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO60_Pos (28UL)                 /*!< DSP0N1GPIO60 (Bit 28)                                 */
37796 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO60_Msk (0x10000000UL)         /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
37797 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO59_Pos (27UL)                 /*!< DSP0N1GPIO59 (Bit 27)                                 */
37798 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO59_Msk (0x8000000UL)          /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
37799 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO58_Pos (26UL)                 /*!< DSP0N1GPIO58 (Bit 26)                                 */
37800 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO58_Msk (0x4000000UL)          /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
37801 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO57_Pos (25UL)                 /*!< DSP0N1GPIO57 (Bit 25)                                 */
37802 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO57_Msk (0x2000000UL)          /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
37803 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO56_Pos (24UL)                 /*!< DSP0N1GPIO56 (Bit 24)                                 */
37804 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO56_Msk (0x1000000UL)          /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
37805 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO55_Pos (23UL)                 /*!< DSP0N1GPIO55 (Bit 23)                                 */
37806 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO55_Msk (0x800000UL)           /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
37807 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO54_Pos (22UL)                 /*!< DSP0N1GPIO54 (Bit 22)                                 */
37808 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO54_Msk (0x400000UL)           /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
37809 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO53_Pos (21UL)                 /*!< DSP0N1GPIO53 (Bit 21)                                 */
37810 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO53_Msk (0x200000UL)           /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
37811 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO52_Pos (20UL)                 /*!< DSP0N1GPIO52 (Bit 20)                                 */
37812 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO52_Msk (0x100000UL)           /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
37813 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO51_Pos (19UL)                 /*!< DSP0N1GPIO51 (Bit 19)                                 */
37814 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO51_Msk (0x80000UL)            /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
37815 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO50_Pos (18UL)                 /*!< DSP0N1GPIO50 (Bit 18)                                 */
37816 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO50_Msk (0x40000UL)            /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
37817 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO49_Pos (17UL)                 /*!< DSP0N1GPIO49 (Bit 17)                                 */
37818 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO49_Msk (0x20000UL)            /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
37819 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO48_Pos (16UL)                 /*!< DSP0N1GPIO48 (Bit 16)                                 */
37820 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO48_Msk (0x10000UL)            /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
37821 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO47_Pos (15UL)                 /*!< DSP0N1GPIO47 (Bit 15)                                 */
37822 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO47_Msk (0x8000UL)             /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
37823 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO46_Pos (14UL)                 /*!< DSP0N1GPIO46 (Bit 14)                                 */
37824 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO46_Msk (0x4000UL)             /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
37825 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO45_Pos (13UL)                 /*!< DSP0N1GPIO45 (Bit 13)                                 */
37826 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO45_Msk (0x2000UL)             /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
37827 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO44_Pos (12UL)                 /*!< DSP0N1GPIO44 (Bit 12)                                 */
37828 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO44_Msk (0x1000UL)             /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
37829 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO43_Pos (11UL)                 /*!< DSP0N1GPIO43 (Bit 11)                                 */
37830 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO43_Msk (0x800UL)              /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
37831 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO42_Pos (10UL)                 /*!< DSP0N1GPIO42 (Bit 10)                                 */
37832 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO42_Msk (0x400UL)              /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
37833 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO41_Pos (9UL)                  /*!< DSP0N1GPIO41 (Bit 9)                                  */
37834 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO41_Msk (0x200UL)              /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
37835 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO40_Pos (8UL)                  /*!< DSP0N1GPIO40 (Bit 8)                                  */
37836 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO40_Msk (0x100UL)              /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
37837 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO39_Pos (7UL)                  /*!< DSP0N1GPIO39 (Bit 7)                                  */
37838 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO39_Msk (0x80UL)               /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
37839 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO38_Pos (6UL)                  /*!< DSP0N1GPIO38 (Bit 6)                                  */
37840 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO38_Msk (0x40UL)               /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
37841 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO37_Pos (5UL)                  /*!< DSP0N1GPIO37 (Bit 5)                                  */
37842 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO37_Msk (0x20UL)               /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
37843 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO36_Pos (4UL)                  /*!< DSP0N1GPIO36 (Bit 4)                                  */
37844 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO36_Msk (0x10UL)               /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
37845 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO35_Pos (3UL)                  /*!< DSP0N1GPIO35 (Bit 3)                                  */
37846 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO35_Msk (0x8UL)                /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
37847 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO34_Pos (2UL)                  /*!< DSP0N1GPIO34 (Bit 2)                                  */
37848 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO34_Msk (0x4UL)                /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
37849 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO33_Pos (1UL)                  /*!< DSP0N1GPIO33 (Bit 1)                                  */
37850 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO33_Msk (0x2UL)                /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
37851 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO32_Pos (0UL)                  /*!< DSP0N1GPIO32 (Bit 0)                                  */
37852 #define GPIO_DSP0N1INT1STAT_DSP0N1GPIO32_Msk (0x1UL)                /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
37853 /* =====================================================  DSP0N1INT1CLR  ===================================================== */
37854 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO63_Pos (31UL)                  /*!< DSP0N1GPIO63 (Bit 31)                                 */
37855 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO63_Msk (0x80000000UL)          /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
37856 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO62_Pos (30UL)                  /*!< DSP0N1GPIO62 (Bit 30)                                 */
37857 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO62_Msk (0x40000000UL)          /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
37858 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO61_Pos (29UL)                  /*!< DSP0N1GPIO61 (Bit 29)                                 */
37859 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO61_Msk (0x20000000UL)          /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
37860 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO60_Pos (28UL)                  /*!< DSP0N1GPIO60 (Bit 28)                                 */
37861 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO60_Msk (0x10000000UL)          /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
37862 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO59_Pos (27UL)                  /*!< DSP0N1GPIO59 (Bit 27)                                 */
37863 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO59_Msk (0x8000000UL)           /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
37864 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO58_Pos (26UL)                  /*!< DSP0N1GPIO58 (Bit 26)                                 */
37865 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO58_Msk (0x4000000UL)           /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
37866 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO57_Pos (25UL)                  /*!< DSP0N1GPIO57 (Bit 25)                                 */
37867 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO57_Msk (0x2000000UL)           /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
37868 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO56_Pos (24UL)                  /*!< DSP0N1GPIO56 (Bit 24)                                 */
37869 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO56_Msk (0x1000000UL)           /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
37870 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO55_Pos (23UL)                  /*!< DSP0N1GPIO55 (Bit 23)                                 */
37871 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO55_Msk (0x800000UL)            /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
37872 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO54_Pos (22UL)                  /*!< DSP0N1GPIO54 (Bit 22)                                 */
37873 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO54_Msk (0x400000UL)            /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
37874 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO53_Pos (21UL)                  /*!< DSP0N1GPIO53 (Bit 21)                                 */
37875 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO53_Msk (0x200000UL)            /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
37876 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO52_Pos (20UL)                  /*!< DSP0N1GPIO52 (Bit 20)                                 */
37877 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO52_Msk (0x100000UL)            /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
37878 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO51_Pos (19UL)                  /*!< DSP0N1GPIO51 (Bit 19)                                 */
37879 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO51_Msk (0x80000UL)             /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
37880 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO50_Pos (18UL)                  /*!< DSP0N1GPIO50 (Bit 18)                                 */
37881 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO50_Msk (0x40000UL)             /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
37882 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO49_Pos (17UL)                  /*!< DSP0N1GPIO49 (Bit 17)                                 */
37883 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO49_Msk (0x20000UL)             /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
37884 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO48_Pos (16UL)                  /*!< DSP0N1GPIO48 (Bit 16)                                 */
37885 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO48_Msk (0x10000UL)             /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
37886 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO47_Pos (15UL)                  /*!< DSP0N1GPIO47 (Bit 15)                                 */
37887 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO47_Msk (0x8000UL)              /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
37888 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO46_Pos (14UL)                  /*!< DSP0N1GPIO46 (Bit 14)                                 */
37889 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO46_Msk (0x4000UL)              /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
37890 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO45_Pos (13UL)                  /*!< DSP0N1GPIO45 (Bit 13)                                 */
37891 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO45_Msk (0x2000UL)              /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
37892 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO44_Pos (12UL)                  /*!< DSP0N1GPIO44 (Bit 12)                                 */
37893 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO44_Msk (0x1000UL)              /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
37894 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO43_Pos (11UL)                  /*!< DSP0N1GPIO43 (Bit 11)                                 */
37895 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO43_Msk (0x800UL)               /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
37896 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO42_Pos (10UL)                  /*!< DSP0N1GPIO42 (Bit 10)                                 */
37897 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO42_Msk (0x400UL)               /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
37898 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO41_Pos (9UL)                   /*!< DSP0N1GPIO41 (Bit 9)                                  */
37899 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO41_Msk (0x200UL)               /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
37900 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO40_Pos (8UL)                   /*!< DSP0N1GPIO40 (Bit 8)                                  */
37901 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO40_Msk (0x100UL)               /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
37902 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO39_Pos (7UL)                   /*!< DSP0N1GPIO39 (Bit 7)                                  */
37903 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO39_Msk (0x80UL)                /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
37904 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO38_Pos (6UL)                   /*!< DSP0N1GPIO38 (Bit 6)                                  */
37905 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO38_Msk (0x40UL)                /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
37906 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO37_Pos (5UL)                   /*!< DSP0N1GPIO37 (Bit 5)                                  */
37907 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO37_Msk (0x20UL)                /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
37908 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO36_Pos (4UL)                   /*!< DSP0N1GPIO36 (Bit 4)                                  */
37909 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO36_Msk (0x10UL)                /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
37910 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO35_Pos (3UL)                   /*!< DSP0N1GPIO35 (Bit 3)                                  */
37911 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO35_Msk (0x8UL)                 /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
37912 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO34_Pos (2UL)                   /*!< DSP0N1GPIO34 (Bit 2)                                  */
37913 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO34_Msk (0x4UL)                 /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
37914 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO33_Pos (1UL)                   /*!< DSP0N1GPIO33 (Bit 1)                                  */
37915 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO33_Msk (0x2UL)                 /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
37916 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO32_Pos (0UL)                   /*!< DSP0N1GPIO32 (Bit 0)                                  */
37917 #define GPIO_DSP0N1INT1CLR_DSP0N1GPIO32_Msk (0x1UL)                 /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
37918 /* =====================================================  DSP0N1INT1SET  ===================================================== */
37919 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO63_Pos (31UL)                  /*!< DSP0N1GPIO63 (Bit 31)                                 */
37920 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO63_Msk (0x80000000UL)          /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
37921 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO62_Pos (30UL)                  /*!< DSP0N1GPIO62 (Bit 30)                                 */
37922 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO62_Msk (0x40000000UL)          /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
37923 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO61_Pos (29UL)                  /*!< DSP0N1GPIO61 (Bit 29)                                 */
37924 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO61_Msk (0x20000000UL)          /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
37925 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO60_Pos (28UL)                  /*!< DSP0N1GPIO60 (Bit 28)                                 */
37926 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO60_Msk (0x10000000UL)          /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
37927 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO59_Pos (27UL)                  /*!< DSP0N1GPIO59 (Bit 27)                                 */
37928 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO59_Msk (0x8000000UL)           /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
37929 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO58_Pos (26UL)                  /*!< DSP0N1GPIO58 (Bit 26)                                 */
37930 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO58_Msk (0x4000000UL)           /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
37931 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO57_Pos (25UL)                  /*!< DSP0N1GPIO57 (Bit 25)                                 */
37932 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO57_Msk (0x2000000UL)           /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
37933 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO56_Pos (24UL)                  /*!< DSP0N1GPIO56 (Bit 24)                                 */
37934 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO56_Msk (0x1000000UL)           /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
37935 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO55_Pos (23UL)                  /*!< DSP0N1GPIO55 (Bit 23)                                 */
37936 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO55_Msk (0x800000UL)            /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
37937 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO54_Pos (22UL)                  /*!< DSP0N1GPIO54 (Bit 22)                                 */
37938 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO54_Msk (0x400000UL)            /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
37939 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO53_Pos (21UL)                  /*!< DSP0N1GPIO53 (Bit 21)                                 */
37940 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO53_Msk (0x200000UL)            /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
37941 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO52_Pos (20UL)                  /*!< DSP0N1GPIO52 (Bit 20)                                 */
37942 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO52_Msk (0x100000UL)            /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
37943 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO51_Pos (19UL)                  /*!< DSP0N1GPIO51 (Bit 19)                                 */
37944 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO51_Msk (0x80000UL)             /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
37945 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO50_Pos (18UL)                  /*!< DSP0N1GPIO50 (Bit 18)                                 */
37946 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO50_Msk (0x40000UL)             /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
37947 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO49_Pos (17UL)                  /*!< DSP0N1GPIO49 (Bit 17)                                 */
37948 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO49_Msk (0x20000UL)             /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
37949 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO48_Pos (16UL)                  /*!< DSP0N1GPIO48 (Bit 16)                                 */
37950 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO48_Msk (0x10000UL)             /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
37951 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO47_Pos (15UL)                  /*!< DSP0N1GPIO47 (Bit 15)                                 */
37952 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO47_Msk (0x8000UL)              /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
37953 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO46_Pos (14UL)                  /*!< DSP0N1GPIO46 (Bit 14)                                 */
37954 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO46_Msk (0x4000UL)              /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
37955 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO45_Pos (13UL)                  /*!< DSP0N1GPIO45 (Bit 13)                                 */
37956 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO45_Msk (0x2000UL)              /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
37957 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO44_Pos (12UL)                  /*!< DSP0N1GPIO44 (Bit 12)                                 */
37958 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO44_Msk (0x1000UL)              /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
37959 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO43_Pos (11UL)                  /*!< DSP0N1GPIO43 (Bit 11)                                 */
37960 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO43_Msk (0x800UL)               /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
37961 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO42_Pos (10UL)                  /*!< DSP0N1GPIO42 (Bit 10)                                 */
37962 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO42_Msk (0x400UL)               /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
37963 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO41_Pos (9UL)                   /*!< DSP0N1GPIO41 (Bit 9)                                  */
37964 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO41_Msk (0x200UL)               /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
37965 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO40_Pos (8UL)                   /*!< DSP0N1GPIO40 (Bit 8)                                  */
37966 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO40_Msk (0x100UL)               /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
37967 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO39_Pos (7UL)                   /*!< DSP0N1GPIO39 (Bit 7)                                  */
37968 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO39_Msk (0x80UL)                /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
37969 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO38_Pos (6UL)                   /*!< DSP0N1GPIO38 (Bit 6)                                  */
37970 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO38_Msk (0x40UL)                /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
37971 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO37_Pos (5UL)                   /*!< DSP0N1GPIO37 (Bit 5)                                  */
37972 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO37_Msk (0x20UL)                /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
37973 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO36_Pos (4UL)                   /*!< DSP0N1GPIO36 (Bit 4)                                  */
37974 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO36_Msk (0x10UL)                /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
37975 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO35_Pos (3UL)                   /*!< DSP0N1GPIO35 (Bit 3)                                  */
37976 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO35_Msk (0x8UL)                 /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
37977 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO34_Pos (2UL)                   /*!< DSP0N1GPIO34 (Bit 2)                                  */
37978 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO34_Msk (0x4UL)                 /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
37979 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO33_Pos (1UL)                   /*!< DSP0N1GPIO33 (Bit 1)                                  */
37980 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO33_Msk (0x2UL)                 /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
37981 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO32_Pos (0UL)                   /*!< DSP0N1GPIO32 (Bit 0)                                  */
37982 #define GPIO_DSP0N1INT1SET_DSP0N1GPIO32_Msk (0x1UL)                 /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
37983 /* =====================================================  DSP0N1INT2EN  ====================================================== */
37984 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO95_Pos (31UL)                   /*!< DSP0N1GPIO95 (Bit 31)                                 */
37985 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO95_Msk (0x80000000UL)           /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
37986 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO94_Pos (30UL)                   /*!< DSP0N1GPIO94 (Bit 30)                                 */
37987 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO94_Msk (0x40000000UL)           /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
37988 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO93_Pos (29UL)                   /*!< DSP0N1GPIO93 (Bit 29)                                 */
37989 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO93_Msk (0x20000000UL)           /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
37990 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO92_Pos (28UL)                   /*!< DSP0N1GPIO92 (Bit 28)                                 */
37991 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO92_Msk (0x10000000UL)           /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
37992 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO91_Pos (27UL)                   /*!< DSP0N1GPIO91 (Bit 27)                                 */
37993 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO91_Msk (0x8000000UL)            /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
37994 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO90_Pos (26UL)                   /*!< DSP0N1GPIO90 (Bit 26)                                 */
37995 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO90_Msk (0x4000000UL)            /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
37996 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO89_Pos (25UL)                   /*!< DSP0N1GPIO89 (Bit 25)                                 */
37997 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO89_Msk (0x2000000UL)            /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
37998 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO88_Pos (24UL)                   /*!< DSP0N1GPIO88 (Bit 24)                                 */
37999 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO88_Msk (0x1000000UL)            /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
38000 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO87_Pos (23UL)                   /*!< DSP0N1GPIO87 (Bit 23)                                 */
38001 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO87_Msk (0x800000UL)             /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
38002 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO86_Pos (22UL)                   /*!< DSP0N1GPIO86 (Bit 22)                                 */
38003 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO86_Msk (0x400000UL)             /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
38004 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO85_Pos (21UL)                   /*!< DSP0N1GPIO85 (Bit 21)                                 */
38005 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO85_Msk (0x200000UL)             /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
38006 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO84_Pos (20UL)                   /*!< DSP0N1GPIO84 (Bit 20)                                 */
38007 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO84_Msk (0x100000UL)             /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
38008 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO83_Pos (19UL)                   /*!< DSP0N1GPIO83 (Bit 19)                                 */
38009 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO83_Msk (0x80000UL)              /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
38010 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO82_Pos (18UL)                   /*!< DSP0N1GPIO82 (Bit 18)                                 */
38011 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO82_Msk (0x40000UL)              /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
38012 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO81_Pos (17UL)                   /*!< DSP0N1GPIO81 (Bit 17)                                 */
38013 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO81_Msk (0x20000UL)              /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
38014 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO80_Pos (16UL)                   /*!< DSP0N1GPIO80 (Bit 16)                                 */
38015 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO80_Msk (0x10000UL)              /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
38016 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO79_Pos (15UL)                   /*!< DSP0N1GPIO79 (Bit 15)                                 */
38017 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO79_Msk (0x8000UL)               /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
38018 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO78_Pos (14UL)                   /*!< DSP0N1GPIO78 (Bit 14)                                 */
38019 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO78_Msk (0x4000UL)               /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
38020 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO77_Pos (13UL)                   /*!< DSP0N1GPIO77 (Bit 13)                                 */
38021 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO77_Msk (0x2000UL)               /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
38022 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO76_Pos (12UL)                   /*!< DSP0N1GPIO76 (Bit 12)                                 */
38023 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO76_Msk (0x1000UL)               /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
38024 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO75_Pos (11UL)                   /*!< DSP0N1GPIO75 (Bit 11)                                 */
38025 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO75_Msk (0x800UL)                /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
38026 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO74_Pos (10UL)                   /*!< DSP0N1GPIO74 (Bit 10)                                 */
38027 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO74_Msk (0x400UL)                /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
38028 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO73_Pos (9UL)                    /*!< DSP0N1GPIO73 (Bit 9)                                  */
38029 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO73_Msk (0x200UL)                /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
38030 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO72_Pos (8UL)                    /*!< DSP0N1GPIO72 (Bit 8)                                  */
38031 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO72_Msk (0x100UL)                /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
38032 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO71_Pos (7UL)                    /*!< DSP0N1GPIO71 (Bit 7)                                  */
38033 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO71_Msk (0x80UL)                 /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
38034 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO70_Pos (6UL)                    /*!< DSP0N1GPIO70 (Bit 6)                                  */
38035 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO70_Msk (0x40UL)                 /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
38036 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO69_Pos (5UL)                    /*!< DSP0N1GPIO69 (Bit 5)                                  */
38037 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO69_Msk (0x20UL)                 /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
38038 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO68_Pos (4UL)                    /*!< DSP0N1GPIO68 (Bit 4)                                  */
38039 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO68_Msk (0x10UL)                 /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
38040 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO67_Pos (3UL)                    /*!< DSP0N1GPIO67 (Bit 3)                                  */
38041 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO67_Msk (0x8UL)                  /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
38042 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO66_Pos (2UL)                    /*!< DSP0N1GPIO66 (Bit 2)                                  */
38043 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO66_Msk (0x4UL)                  /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
38044 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO65_Pos (1UL)                    /*!< DSP0N1GPIO65 (Bit 1)                                  */
38045 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO65_Msk (0x2UL)                  /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
38046 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO64_Pos (0UL)                    /*!< DSP0N1GPIO64 (Bit 0)                                  */
38047 #define GPIO_DSP0N1INT2EN_DSP0N1GPIO64_Msk (0x1UL)                  /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
38048 /* ====================================================  DSP0N1INT2STAT  ===================================================== */
38049 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO95_Pos (31UL)                 /*!< DSP0N1GPIO95 (Bit 31)                                 */
38050 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO95_Msk (0x80000000UL)         /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
38051 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO94_Pos (30UL)                 /*!< DSP0N1GPIO94 (Bit 30)                                 */
38052 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO94_Msk (0x40000000UL)         /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
38053 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO93_Pos (29UL)                 /*!< DSP0N1GPIO93 (Bit 29)                                 */
38054 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO93_Msk (0x20000000UL)         /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
38055 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO92_Pos (28UL)                 /*!< DSP0N1GPIO92 (Bit 28)                                 */
38056 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO92_Msk (0x10000000UL)         /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
38057 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO91_Pos (27UL)                 /*!< DSP0N1GPIO91 (Bit 27)                                 */
38058 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO91_Msk (0x8000000UL)          /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
38059 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO90_Pos (26UL)                 /*!< DSP0N1GPIO90 (Bit 26)                                 */
38060 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO90_Msk (0x4000000UL)          /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
38061 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO89_Pos (25UL)                 /*!< DSP0N1GPIO89 (Bit 25)                                 */
38062 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO89_Msk (0x2000000UL)          /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
38063 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO88_Pos (24UL)                 /*!< DSP0N1GPIO88 (Bit 24)                                 */
38064 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO88_Msk (0x1000000UL)          /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
38065 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO87_Pos (23UL)                 /*!< DSP0N1GPIO87 (Bit 23)                                 */
38066 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO87_Msk (0x800000UL)           /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
38067 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO86_Pos (22UL)                 /*!< DSP0N1GPIO86 (Bit 22)                                 */
38068 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO86_Msk (0x400000UL)           /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
38069 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO85_Pos (21UL)                 /*!< DSP0N1GPIO85 (Bit 21)                                 */
38070 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO85_Msk (0x200000UL)           /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
38071 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO84_Pos (20UL)                 /*!< DSP0N1GPIO84 (Bit 20)                                 */
38072 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO84_Msk (0x100000UL)           /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
38073 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO83_Pos (19UL)                 /*!< DSP0N1GPIO83 (Bit 19)                                 */
38074 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO83_Msk (0x80000UL)            /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
38075 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO82_Pos (18UL)                 /*!< DSP0N1GPIO82 (Bit 18)                                 */
38076 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO82_Msk (0x40000UL)            /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
38077 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO81_Pos (17UL)                 /*!< DSP0N1GPIO81 (Bit 17)                                 */
38078 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO81_Msk (0x20000UL)            /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
38079 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO80_Pos (16UL)                 /*!< DSP0N1GPIO80 (Bit 16)                                 */
38080 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO80_Msk (0x10000UL)            /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
38081 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO79_Pos (15UL)                 /*!< DSP0N1GPIO79 (Bit 15)                                 */
38082 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO79_Msk (0x8000UL)             /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
38083 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO78_Pos (14UL)                 /*!< DSP0N1GPIO78 (Bit 14)                                 */
38084 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO78_Msk (0x4000UL)             /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
38085 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO77_Pos (13UL)                 /*!< DSP0N1GPIO77 (Bit 13)                                 */
38086 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO77_Msk (0x2000UL)             /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
38087 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO76_Pos (12UL)                 /*!< DSP0N1GPIO76 (Bit 12)                                 */
38088 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO76_Msk (0x1000UL)             /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
38089 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO75_Pos (11UL)                 /*!< DSP0N1GPIO75 (Bit 11)                                 */
38090 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO75_Msk (0x800UL)              /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
38091 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO74_Pos (10UL)                 /*!< DSP0N1GPIO74 (Bit 10)                                 */
38092 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO74_Msk (0x400UL)              /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
38093 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO73_Pos (9UL)                  /*!< DSP0N1GPIO73 (Bit 9)                                  */
38094 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO73_Msk (0x200UL)              /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
38095 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO72_Pos (8UL)                  /*!< DSP0N1GPIO72 (Bit 8)                                  */
38096 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO72_Msk (0x100UL)              /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
38097 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO71_Pos (7UL)                  /*!< DSP0N1GPIO71 (Bit 7)                                  */
38098 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO71_Msk (0x80UL)               /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
38099 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO70_Pos (6UL)                  /*!< DSP0N1GPIO70 (Bit 6)                                  */
38100 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO70_Msk (0x40UL)               /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
38101 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO69_Pos (5UL)                  /*!< DSP0N1GPIO69 (Bit 5)                                  */
38102 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO69_Msk (0x20UL)               /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
38103 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO68_Pos (4UL)                  /*!< DSP0N1GPIO68 (Bit 4)                                  */
38104 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO68_Msk (0x10UL)               /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
38105 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO67_Pos (3UL)                  /*!< DSP0N1GPIO67 (Bit 3)                                  */
38106 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO67_Msk (0x8UL)                /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
38107 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO66_Pos (2UL)                  /*!< DSP0N1GPIO66 (Bit 2)                                  */
38108 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO66_Msk (0x4UL)                /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
38109 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO65_Pos (1UL)                  /*!< DSP0N1GPIO65 (Bit 1)                                  */
38110 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO65_Msk (0x2UL)                /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
38111 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO64_Pos (0UL)                  /*!< DSP0N1GPIO64 (Bit 0)                                  */
38112 #define GPIO_DSP0N1INT2STAT_DSP0N1GPIO64_Msk (0x1UL)                /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
38113 /* =====================================================  DSP0N1INT2CLR  ===================================================== */
38114 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO95_Pos (31UL)                  /*!< DSP0N1GPIO95 (Bit 31)                                 */
38115 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO95_Msk (0x80000000UL)          /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
38116 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO94_Pos (30UL)                  /*!< DSP0N1GPIO94 (Bit 30)                                 */
38117 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO94_Msk (0x40000000UL)          /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
38118 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO93_Pos (29UL)                  /*!< DSP0N1GPIO93 (Bit 29)                                 */
38119 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO93_Msk (0x20000000UL)          /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
38120 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO92_Pos (28UL)                  /*!< DSP0N1GPIO92 (Bit 28)                                 */
38121 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO92_Msk (0x10000000UL)          /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
38122 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO91_Pos (27UL)                  /*!< DSP0N1GPIO91 (Bit 27)                                 */
38123 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO91_Msk (0x8000000UL)           /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
38124 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO90_Pos (26UL)                  /*!< DSP0N1GPIO90 (Bit 26)                                 */
38125 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO90_Msk (0x4000000UL)           /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
38126 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO89_Pos (25UL)                  /*!< DSP0N1GPIO89 (Bit 25)                                 */
38127 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO89_Msk (0x2000000UL)           /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
38128 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO88_Pos (24UL)                  /*!< DSP0N1GPIO88 (Bit 24)                                 */
38129 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO88_Msk (0x1000000UL)           /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
38130 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO87_Pos (23UL)                  /*!< DSP0N1GPIO87 (Bit 23)                                 */
38131 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO87_Msk (0x800000UL)            /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
38132 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO86_Pos (22UL)                  /*!< DSP0N1GPIO86 (Bit 22)                                 */
38133 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO86_Msk (0x400000UL)            /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
38134 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO85_Pos (21UL)                  /*!< DSP0N1GPIO85 (Bit 21)                                 */
38135 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO85_Msk (0x200000UL)            /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
38136 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO84_Pos (20UL)                  /*!< DSP0N1GPIO84 (Bit 20)                                 */
38137 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO84_Msk (0x100000UL)            /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
38138 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO83_Pos (19UL)                  /*!< DSP0N1GPIO83 (Bit 19)                                 */
38139 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO83_Msk (0x80000UL)             /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
38140 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO82_Pos (18UL)                  /*!< DSP0N1GPIO82 (Bit 18)                                 */
38141 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO82_Msk (0x40000UL)             /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
38142 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO81_Pos (17UL)                  /*!< DSP0N1GPIO81 (Bit 17)                                 */
38143 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO81_Msk (0x20000UL)             /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
38144 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO80_Pos (16UL)                  /*!< DSP0N1GPIO80 (Bit 16)                                 */
38145 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO80_Msk (0x10000UL)             /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
38146 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO79_Pos (15UL)                  /*!< DSP0N1GPIO79 (Bit 15)                                 */
38147 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO79_Msk (0x8000UL)              /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
38148 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO78_Pos (14UL)                  /*!< DSP0N1GPIO78 (Bit 14)                                 */
38149 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO78_Msk (0x4000UL)              /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
38150 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO77_Pos (13UL)                  /*!< DSP0N1GPIO77 (Bit 13)                                 */
38151 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO77_Msk (0x2000UL)              /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
38152 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO76_Pos (12UL)                  /*!< DSP0N1GPIO76 (Bit 12)                                 */
38153 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO76_Msk (0x1000UL)              /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
38154 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO75_Pos (11UL)                  /*!< DSP0N1GPIO75 (Bit 11)                                 */
38155 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO75_Msk (0x800UL)               /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
38156 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO74_Pos (10UL)                  /*!< DSP0N1GPIO74 (Bit 10)                                 */
38157 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO74_Msk (0x400UL)               /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
38158 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO73_Pos (9UL)                   /*!< DSP0N1GPIO73 (Bit 9)                                  */
38159 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO73_Msk (0x200UL)               /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
38160 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO72_Pos (8UL)                   /*!< DSP0N1GPIO72 (Bit 8)                                  */
38161 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO72_Msk (0x100UL)               /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
38162 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO71_Pos (7UL)                   /*!< DSP0N1GPIO71 (Bit 7)                                  */
38163 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO71_Msk (0x80UL)                /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
38164 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO70_Pos (6UL)                   /*!< DSP0N1GPIO70 (Bit 6)                                  */
38165 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO70_Msk (0x40UL)                /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
38166 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO69_Pos (5UL)                   /*!< DSP0N1GPIO69 (Bit 5)                                  */
38167 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO69_Msk (0x20UL)                /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
38168 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO68_Pos (4UL)                   /*!< DSP0N1GPIO68 (Bit 4)                                  */
38169 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO68_Msk (0x10UL)                /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
38170 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO67_Pos (3UL)                   /*!< DSP0N1GPIO67 (Bit 3)                                  */
38171 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO67_Msk (0x8UL)                 /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
38172 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO66_Pos (2UL)                   /*!< DSP0N1GPIO66 (Bit 2)                                  */
38173 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO66_Msk (0x4UL)                 /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
38174 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO65_Pos (1UL)                   /*!< DSP0N1GPIO65 (Bit 1)                                  */
38175 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO65_Msk (0x2UL)                 /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
38176 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO64_Pos (0UL)                   /*!< DSP0N1GPIO64 (Bit 0)                                  */
38177 #define GPIO_DSP0N1INT2CLR_DSP0N1GPIO64_Msk (0x1UL)                 /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
38178 /* =====================================================  DSP0N1INT2SET  ===================================================== */
38179 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO95_Pos (31UL)                  /*!< DSP0N1GPIO95 (Bit 31)                                 */
38180 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO95_Msk (0x80000000UL)          /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
38181 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO94_Pos (30UL)                  /*!< DSP0N1GPIO94 (Bit 30)                                 */
38182 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO94_Msk (0x40000000UL)          /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
38183 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO93_Pos (29UL)                  /*!< DSP0N1GPIO93 (Bit 29)                                 */
38184 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO93_Msk (0x20000000UL)          /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
38185 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO92_Pos (28UL)                  /*!< DSP0N1GPIO92 (Bit 28)                                 */
38186 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO92_Msk (0x10000000UL)          /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
38187 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO91_Pos (27UL)                  /*!< DSP0N1GPIO91 (Bit 27)                                 */
38188 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO91_Msk (0x8000000UL)           /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
38189 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO90_Pos (26UL)                  /*!< DSP0N1GPIO90 (Bit 26)                                 */
38190 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO90_Msk (0x4000000UL)           /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
38191 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO89_Pos (25UL)                  /*!< DSP0N1GPIO89 (Bit 25)                                 */
38192 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO89_Msk (0x2000000UL)           /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
38193 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO88_Pos (24UL)                  /*!< DSP0N1GPIO88 (Bit 24)                                 */
38194 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO88_Msk (0x1000000UL)           /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
38195 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO87_Pos (23UL)                  /*!< DSP0N1GPIO87 (Bit 23)                                 */
38196 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO87_Msk (0x800000UL)            /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
38197 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO86_Pos (22UL)                  /*!< DSP0N1GPIO86 (Bit 22)                                 */
38198 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO86_Msk (0x400000UL)            /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
38199 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO85_Pos (21UL)                  /*!< DSP0N1GPIO85 (Bit 21)                                 */
38200 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO85_Msk (0x200000UL)            /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
38201 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO84_Pos (20UL)                  /*!< DSP0N1GPIO84 (Bit 20)                                 */
38202 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO84_Msk (0x100000UL)            /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
38203 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO83_Pos (19UL)                  /*!< DSP0N1GPIO83 (Bit 19)                                 */
38204 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO83_Msk (0x80000UL)             /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
38205 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO82_Pos (18UL)                  /*!< DSP0N1GPIO82 (Bit 18)                                 */
38206 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO82_Msk (0x40000UL)             /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
38207 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO81_Pos (17UL)                  /*!< DSP0N1GPIO81 (Bit 17)                                 */
38208 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO81_Msk (0x20000UL)             /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
38209 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO80_Pos (16UL)                  /*!< DSP0N1GPIO80 (Bit 16)                                 */
38210 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO80_Msk (0x10000UL)             /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
38211 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO79_Pos (15UL)                  /*!< DSP0N1GPIO79 (Bit 15)                                 */
38212 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO79_Msk (0x8000UL)              /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
38213 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO78_Pos (14UL)                  /*!< DSP0N1GPIO78 (Bit 14)                                 */
38214 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO78_Msk (0x4000UL)              /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
38215 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO77_Pos (13UL)                  /*!< DSP0N1GPIO77 (Bit 13)                                 */
38216 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO77_Msk (0x2000UL)              /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
38217 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO76_Pos (12UL)                  /*!< DSP0N1GPIO76 (Bit 12)                                 */
38218 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO76_Msk (0x1000UL)              /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
38219 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO75_Pos (11UL)                  /*!< DSP0N1GPIO75 (Bit 11)                                 */
38220 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO75_Msk (0x800UL)               /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
38221 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO74_Pos (10UL)                  /*!< DSP0N1GPIO74 (Bit 10)                                 */
38222 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO74_Msk (0x400UL)               /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
38223 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO73_Pos (9UL)                   /*!< DSP0N1GPIO73 (Bit 9)                                  */
38224 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO73_Msk (0x200UL)               /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
38225 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO72_Pos (8UL)                   /*!< DSP0N1GPIO72 (Bit 8)                                  */
38226 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO72_Msk (0x100UL)               /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
38227 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO71_Pos (7UL)                   /*!< DSP0N1GPIO71 (Bit 7)                                  */
38228 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO71_Msk (0x80UL)                /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
38229 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO70_Pos (6UL)                   /*!< DSP0N1GPIO70 (Bit 6)                                  */
38230 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO70_Msk (0x40UL)                /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
38231 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO69_Pos (5UL)                   /*!< DSP0N1GPIO69 (Bit 5)                                  */
38232 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO69_Msk (0x20UL)                /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
38233 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO68_Pos (4UL)                   /*!< DSP0N1GPIO68 (Bit 4)                                  */
38234 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO68_Msk (0x10UL)                /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
38235 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO67_Pos (3UL)                   /*!< DSP0N1GPIO67 (Bit 3)                                  */
38236 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO67_Msk (0x8UL)                 /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
38237 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO66_Pos (2UL)                   /*!< DSP0N1GPIO66 (Bit 2)                                  */
38238 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO66_Msk (0x4UL)                 /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
38239 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO65_Pos (1UL)                   /*!< DSP0N1GPIO65 (Bit 1)                                  */
38240 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO65_Msk (0x2UL)                 /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
38241 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO64_Pos (0UL)                   /*!< DSP0N1GPIO64 (Bit 0)                                  */
38242 #define GPIO_DSP0N1INT2SET_DSP0N1GPIO64_Msk (0x1UL)                 /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
38243 /* =====================================================  DSP0N1INT3EN  ====================================================== */
38244 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO127_Pos (31UL)                  /*!< DSP0N1GPIO127 (Bit 31)                                */
38245 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO127_Msk (0x80000000UL)          /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
38246 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO126_Pos (30UL)                  /*!< DSP0N1GPIO126 (Bit 30)                                */
38247 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO126_Msk (0x40000000UL)          /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
38248 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO125_Pos (29UL)                  /*!< DSP0N1GPIO125 (Bit 29)                                */
38249 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO125_Msk (0x20000000UL)          /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
38250 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO124_Pos (28UL)                  /*!< DSP0N1GPIO124 (Bit 28)                                */
38251 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO124_Msk (0x10000000UL)          /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
38252 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO123_Pos (27UL)                  /*!< DSP0N1GPIO123 (Bit 27)                                */
38253 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO123_Msk (0x8000000UL)           /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
38254 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO122_Pos (26UL)                  /*!< DSP0N1GPIO122 (Bit 26)                                */
38255 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO122_Msk (0x4000000UL)           /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
38256 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO121_Pos (25UL)                  /*!< DSP0N1GPIO121 (Bit 25)                                */
38257 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO121_Msk (0x2000000UL)           /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
38258 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO120_Pos (24UL)                  /*!< DSP0N1GPIO120 (Bit 24)                                */
38259 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO120_Msk (0x1000000UL)           /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
38260 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO119_Pos (23UL)                  /*!< DSP0N1GPIO119 (Bit 23)                                */
38261 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO119_Msk (0x800000UL)            /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
38262 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO118_Pos (22UL)                  /*!< DSP0N1GPIO118 (Bit 22)                                */
38263 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO118_Msk (0x400000UL)            /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
38264 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO117_Pos (21UL)                  /*!< DSP0N1GPIO117 (Bit 21)                                */
38265 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO117_Msk (0x200000UL)            /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
38266 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO116_Pos (20UL)                  /*!< DSP0N1GPIO116 (Bit 20)                                */
38267 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO116_Msk (0x100000UL)            /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
38268 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO115_Pos (19UL)                  /*!< DSP0N1GPIO115 (Bit 19)                                */
38269 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO115_Msk (0x80000UL)             /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
38270 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO114_Pos (18UL)                  /*!< DSP0N1GPIO114 (Bit 18)                                */
38271 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO114_Msk (0x40000UL)             /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
38272 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO113_Pos (17UL)                  /*!< DSP0N1GPIO113 (Bit 17)                                */
38273 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO113_Msk (0x20000UL)             /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
38274 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO112_Pos (16UL)                  /*!< DSP0N1GPIO112 (Bit 16)                                */
38275 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO112_Msk (0x10000UL)             /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
38276 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO111_Pos (15UL)                  /*!< DSP0N1GPIO111 (Bit 15)                                */
38277 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO111_Msk (0x8000UL)              /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
38278 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO110_Pos (14UL)                  /*!< DSP0N1GPIO110 (Bit 14)                                */
38279 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO110_Msk (0x4000UL)              /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
38280 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO109_Pos (13UL)                  /*!< DSP0N1GPIO109 (Bit 13)                                */
38281 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO109_Msk (0x2000UL)              /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
38282 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO108_Pos (12UL)                  /*!< DSP0N1GPIO108 (Bit 12)                                */
38283 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO108_Msk (0x1000UL)              /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
38284 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO107_Pos (11UL)                  /*!< DSP0N1GPIO107 (Bit 11)                                */
38285 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO107_Msk (0x800UL)               /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
38286 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO106_Pos (10UL)                  /*!< DSP0N1GPIO106 (Bit 10)                                */
38287 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO106_Msk (0x400UL)               /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
38288 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO105_Pos (9UL)                   /*!< DSP0N1GPIO105 (Bit 9)                                 */
38289 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO105_Msk (0x200UL)               /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
38290 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO104_Pos (8UL)                   /*!< DSP0N1GPIO104 (Bit 8)                                 */
38291 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO104_Msk (0x100UL)               /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
38292 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO103_Pos (7UL)                   /*!< DSP0N1GPIO103 (Bit 7)                                 */
38293 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO103_Msk (0x80UL)                /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
38294 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO102_Pos (6UL)                   /*!< DSP0N1GPIO102 (Bit 6)                                 */
38295 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO102_Msk (0x40UL)                /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
38296 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO101_Pos (5UL)                   /*!< DSP0N1GPIO101 (Bit 5)                                 */
38297 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO101_Msk (0x20UL)                /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
38298 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO100_Pos (4UL)                   /*!< DSP0N1GPIO100 (Bit 4)                                 */
38299 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO100_Msk (0x10UL)                /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
38300 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO99_Pos (3UL)                    /*!< DSP0N1GPIO99 (Bit 3)                                  */
38301 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO99_Msk (0x8UL)                  /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
38302 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO98_Pos (2UL)                    /*!< DSP0N1GPIO98 (Bit 2)                                  */
38303 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO98_Msk (0x4UL)                  /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
38304 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO97_Pos (1UL)                    /*!< DSP0N1GPIO97 (Bit 1)                                  */
38305 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO97_Msk (0x2UL)                  /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
38306 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO96_Pos (0UL)                    /*!< DSP0N1GPIO96 (Bit 0)                                  */
38307 #define GPIO_DSP0N1INT3EN_DSP0N1GPIO96_Msk (0x1UL)                  /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
38308 /* ====================================================  DSP0N1INT3STAT  ===================================================== */
38309 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO127_Pos (31UL)                /*!< DSP0N1GPIO127 (Bit 31)                                */
38310 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO127_Msk (0x80000000UL)        /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
38311 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO126_Pos (30UL)                /*!< DSP0N1GPIO126 (Bit 30)                                */
38312 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO126_Msk (0x40000000UL)        /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
38313 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO125_Pos (29UL)                /*!< DSP0N1GPIO125 (Bit 29)                                */
38314 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO125_Msk (0x20000000UL)        /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
38315 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO124_Pos (28UL)                /*!< DSP0N1GPIO124 (Bit 28)                                */
38316 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO124_Msk (0x10000000UL)        /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
38317 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO123_Pos (27UL)                /*!< DSP0N1GPIO123 (Bit 27)                                */
38318 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO123_Msk (0x8000000UL)         /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
38319 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO122_Pos (26UL)                /*!< DSP0N1GPIO122 (Bit 26)                                */
38320 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO122_Msk (0x4000000UL)         /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
38321 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO121_Pos (25UL)                /*!< DSP0N1GPIO121 (Bit 25)                                */
38322 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO121_Msk (0x2000000UL)         /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
38323 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO120_Pos (24UL)                /*!< DSP0N1GPIO120 (Bit 24)                                */
38324 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO120_Msk (0x1000000UL)         /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
38325 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO119_Pos (23UL)                /*!< DSP0N1GPIO119 (Bit 23)                                */
38326 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO119_Msk (0x800000UL)          /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
38327 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO118_Pos (22UL)                /*!< DSP0N1GPIO118 (Bit 22)                                */
38328 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO118_Msk (0x400000UL)          /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
38329 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO117_Pos (21UL)                /*!< DSP0N1GPIO117 (Bit 21)                                */
38330 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO117_Msk (0x200000UL)          /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
38331 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO116_Pos (20UL)                /*!< DSP0N1GPIO116 (Bit 20)                                */
38332 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO116_Msk (0x100000UL)          /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
38333 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO115_Pos (19UL)                /*!< DSP0N1GPIO115 (Bit 19)                                */
38334 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO115_Msk (0x80000UL)           /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
38335 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO114_Pos (18UL)                /*!< DSP0N1GPIO114 (Bit 18)                                */
38336 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO114_Msk (0x40000UL)           /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
38337 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO113_Pos (17UL)                /*!< DSP0N1GPIO113 (Bit 17)                                */
38338 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO113_Msk (0x20000UL)           /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
38339 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO112_Pos (16UL)                /*!< DSP0N1GPIO112 (Bit 16)                                */
38340 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO112_Msk (0x10000UL)           /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
38341 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO111_Pos (15UL)                /*!< DSP0N1GPIO111 (Bit 15)                                */
38342 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO111_Msk (0x8000UL)            /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
38343 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO110_Pos (14UL)                /*!< DSP0N1GPIO110 (Bit 14)                                */
38344 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO110_Msk (0x4000UL)            /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
38345 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO109_Pos (13UL)                /*!< DSP0N1GPIO109 (Bit 13)                                */
38346 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO109_Msk (0x2000UL)            /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
38347 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO108_Pos (12UL)                /*!< DSP0N1GPIO108 (Bit 12)                                */
38348 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO108_Msk (0x1000UL)            /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
38349 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO107_Pos (11UL)                /*!< DSP0N1GPIO107 (Bit 11)                                */
38350 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO107_Msk (0x800UL)             /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
38351 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO106_Pos (10UL)                /*!< DSP0N1GPIO106 (Bit 10)                                */
38352 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO106_Msk (0x400UL)             /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
38353 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO105_Pos (9UL)                 /*!< DSP0N1GPIO105 (Bit 9)                                 */
38354 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO105_Msk (0x200UL)             /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
38355 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO104_Pos (8UL)                 /*!< DSP0N1GPIO104 (Bit 8)                                 */
38356 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO104_Msk (0x100UL)             /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
38357 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO103_Pos (7UL)                 /*!< DSP0N1GPIO103 (Bit 7)                                 */
38358 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO103_Msk (0x80UL)              /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
38359 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO102_Pos (6UL)                 /*!< DSP0N1GPIO102 (Bit 6)                                 */
38360 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO102_Msk (0x40UL)              /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
38361 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO101_Pos (5UL)                 /*!< DSP0N1GPIO101 (Bit 5)                                 */
38362 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO101_Msk (0x20UL)              /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
38363 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO100_Pos (4UL)                 /*!< DSP0N1GPIO100 (Bit 4)                                 */
38364 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO100_Msk (0x10UL)              /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
38365 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO99_Pos (3UL)                  /*!< DSP0N1GPIO99 (Bit 3)                                  */
38366 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO99_Msk (0x8UL)                /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
38367 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO98_Pos (2UL)                  /*!< DSP0N1GPIO98 (Bit 2)                                  */
38368 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO98_Msk (0x4UL)                /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
38369 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO97_Pos (1UL)                  /*!< DSP0N1GPIO97 (Bit 1)                                  */
38370 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO97_Msk (0x2UL)                /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
38371 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO96_Pos (0UL)                  /*!< DSP0N1GPIO96 (Bit 0)                                  */
38372 #define GPIO_DSP0N1INT3STAT_DSP0N1GPIO96_Msk (0x1UL)                /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
38373 /* =====================================================  DSP0N1INT3CLR  ===================================================== */
38374 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO127_Pos (31UL)                 /*!< DSP0N1GPIO127 (Bit 31)                                */
38375 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO127_Msk (0x80000000UL)         /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
38376 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO126_Pos (30UL)                 /*!< DSP0N1GPIO126 (Bit 30)                                */
38377 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO126_Msk (0x40000000UL)         /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
38378 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO125_Pos (29UL)                 /*!< DSP0N1GPIO125 (Bit 29)                                */
38379 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO125_Msk (0x20000000UL)         /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
38380 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO124_Pos (28UL)                 /*!< DSP0N1GPIO124 (Bit 28)                                */
38381 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO124_Msk (0x10000000UL)         /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
38382 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO123_Pos (27UL)                 /*!< DSP0N1GPIO123 (Bit 27)                                */
38383 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO123_Msk (0x8000000UL)          /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
38384 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO122_Pos (26UL)                 /*!< DSP0N1GPIO122 (Bit 26)                                */
38385 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO122_Msk (0x4000000UL)          /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
38386 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO121_Pos (25UL)                 /*!< DSP0N1GPIO121 (Bit 25)                                */
38387 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO121_Msk (0x2000000UL)          /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
38388 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO120_Pos (24UL)                 /*!< DSP0N1GPIO120 (Bit 24)                                */
38389 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO120_Msk (0x1000000UL)          /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
38390 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO119_Pos (23UL)                 /*!< DSP0N1GPIO119 (Bit 23)                                */
38391 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO119_Msk (0x800000UL)           /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
38392 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO118_Pos (22UL)                 /*!< DSP0N1GPIO118 (Bit 22)                                */
38393 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO118_Msk (0x400000UL)           /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
38394 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO117_Pos (21UL)                 /*!< DSP0N1GPIO117 (Bit 21)                                */
38395 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO117_Msk (0x200000UL)           /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
38396 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO116_Pos (20UL)                 /*!< DSP0N1GPIO116 (Bit 20)                                */
38397 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO116_Msk (0x100000UL)           /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
38398 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO115_Pos (19UL)                 /*!< DSP0N1GPIO115 (Bit 19)                                */
38399 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO115_Msk (0x80000UL)            /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
38400 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO114_Pos (18UL)                 /*!< DSP0N1GPIO114 (Bit 18)                                */
38401 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO114_Msk (0x40000UL)            /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
38402 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO113_Pos (17UL)                 /*!< DSP0N1GPIO113 (Bit 17)                                */
38403 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO113_Msk (0x20000UL)            /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
38404 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO112_Pos (16UL)                 /*!< DSP0N1GPIO112 (Bit 16)                                */
38405 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO112_Msk (0x10000UL)            /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
38406 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO111_Pos (15UL)                 /*!< DSP0N1GPIO111 (Bit 15)                                */
38407 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO111_Msk (0x8000UL)             /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
38408 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO110_Pos (14UL)                 /*!< DSP0N1GPIO110 (Bit 14)                                */
38409 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO110_Msk (0x4000UL)             /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
38410 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO109_Pos (13UL)                 /*!< DSP0N1GPIO109 (Bit 13)                                */
38411 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO109_Msk (0x2000UL)             /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
38412 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO108_Pos (12UL)                 /*!< DSP0N1GPIO108 (Bit 12)                                */
38413 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO108_Msk (0x1000UL)             /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
38414 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO107_Pos (11UL)                 /*!< DSP0N1GPIO107 (Bit 11)                                */
38415 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO107_Msk (0x800UL)              /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
38416 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO106_Pos (10UL)                 /*!< DSP0N1GPIO106 (Bit 10)                                */
38417 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO106_Msk (0x400UL)              /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
38418 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO105_Pos (9UL)                  /*!< DSP0N1GPIO105 (Bit 9)                                 */
38419 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO105_Msk (0x200UL)              /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
38420 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO104_Pos (8UL)                  /*!< DSP0N1GPIO104 (Bit 8)                                 */
38421 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO104_Msk (0x100UL)              /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
38422 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO103_Pos (7UL)                  /*!< DSP0N1GPIO103 (Bit 7)                                 */
38423 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO103_Msk (0x80UL)               /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
38424 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO102_Pos (6UL)                  /*!< DSP0N1GPIO102 (Bit 6)                                 */
38425 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO102_Msk (0x40UL)               /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
38426 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO101_Pos (5UL)                  /*!< DSP0N1GPIO101 (Bit 5)                                 */
38427 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO101_Msk (0x20UL)               /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
38428 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO100_Pos (4UL)                  /*!< DSP0N1GPIO100 (Bit 4)                                 */
38429 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO100_Msk (0x10UL)               /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
38430 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO99_Pos (3UL)                   /*!< DSP0N1GPIO99 (Bit 3)                                  */
38431 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO99_Msk (0x8UL)                 /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
38432 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO98_Pos (2UL)                   /*!< DSP0N1GPIO98 (Bit 2)                                  */
38433 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO98_Msk (0x4UL)                 /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
38434 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO97_Pos (1UL)                   /*!< DSP0N1GPIO97 (Bit 1)                                  */
38435 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO97_Msk (0x2UL)                 /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
38436 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO96_Pos (0UL)                   /*!< DSP0N1GPIO96 (Bit 0)                                  */
38437 #define GPIO_DSP0N1INT3CLR_DSP0N1GPIO96_Msk (0x1UL)                 /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
38438 /* =====================================================  DSP0N1INT3SET  ===================================================== */
38439 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO127_Pos (31UL)                 /*!< DSP0N1GPIO127 (Bit 31)                                */
38440 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO127_Msk (0x80000000UL)         /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
38441 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO126_Pos (30UL)                 /*!< DSP0N1GPIO126 (Bit 30)                                */
38442 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO126_Msk (0x40000000UL)         /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
38443 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO125_Pos (29UL)                 /*!< DSP0N1GPIO125 (Bit 29)                                */
38444 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO125_Msk (0x20000000UL)         /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
38445 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO124_Pos (28UL)                 /*!< DSP0N1GPIO124 (Bit 28)                                */
38446 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO124_Msk (0x10000000UL)         /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
38447 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO123_Pos (27UL)                 /*!< DSP0N1GPIO123 (Bit 27)                                */
38448 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO123_Msk (0x8000000UL)          /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
38449 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO122_Pos (26UL)                 /*!< DSP0N1GPIO122 (Bit 26)                                */
38450 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO122_Msk (0x4000000UL)          /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
38451 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO121_Pos (25UL)                 /*!< DSP0N1GPIO121 (Bit 25)                                */
38452 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO121_Msk (0x2000000UL)          /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
38453 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO120_Pos (24UL)                 /*!< DSP0N1GPIO120 (Bit 24)                                */
38454 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO120_Msk (0x1000000UL)          /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
38455 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO119_Pos (23UL)                 /*!< DSP0N1GPIO119 (Bit 23)                                */
38456 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO119_Msk (0x800000UL)           /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
38457 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO118_Pos (22UL)                 /*!< DSP0N1GPIO118 (Bit 22)                                */
38458 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO118_Msk (0x400000UL)           /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
38459 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO117_Pos (21UL)                 /*!< DSP0N1GPIO117 (Bit 21)                                */
38460 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO117_Msk (0x200000UL)           /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
38461 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO116_Pos (20UL)                 /*!< DSP0N1GPIO116 (Bit 20)                                */
38462 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO116_Msk (0x100000UL)           /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
38463 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO115_Pos (19UL)                 /*!< DSP0N1GPIO115 (Bit 19)                                */
38464 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO115_Msk (0x80000UL)            /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
38465 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO114_Pos (18UL)                 /*!< DSP0N1GPIO114 (Bit 18)                                */
38466 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO114_Msk (0x40000UL)            /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
38467 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO113_Pos (17UL)                 /*!< DSP0N1GPIO113 (Bit 17)                                */
38468 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO113_Msk (0x20000UL)            /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
38469 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO112_Pos (16UL)                 /*!< DSP0N1GPIO112 (Bit 16)                                */
38470 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO112_Msk (0x10000UL)            /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
38471 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO111_Pos (15UL)                 /*!< DSP0N1GPIO111 (Bit 15)                                */
38472 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO111_Msk (0x8000UL)             /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
38473 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO110_Pos (14UL)                 /*!< DSP0N1GPIO110 (Bit 14)                                */
38474 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO110_Msk (0x4000UL)             /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
38475 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO109_Pos (13UL)                 /*!< DSP0N1GPIO109 (Bit 13)                                */
38476 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO109_Msk (0x2000UL)             /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
38477 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO108_Pos (12UL)                 /*!< DSP0N1GPIO108 (Bit 12)                                */
38478 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO108_Msk (0x1000UL)             /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
38479 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO107_Pos (11UL)                 /*!< DSP0N1GPIO107 (Bit 11)                                */
38480 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO107_Msk (0x800UL)              /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
38481 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO106_Pos (10UL)                 /*!< DSP0N1GPIO106 (Bit 10)                                */
38482 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO106_Msk (0x400UL)              /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
38483 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO105_Pos (9UL)                  /*!< DSP0N1GPIO105 (Bit 9)                                 */
38484 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO105_Msk (0x200UL)              /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
38485 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO104_Pos (8UL)                  /*!< DSP0N1GPIO104 (Bit 8)                                 */
38486 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO104_Msk (0x100UL)              /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
38487 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO103_Pos (7UL)                  /*!< DSP0N1GPIO103 (Bit 7)                                 */
38488 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO103_Msk (0x80UL)               /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
38489 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO102_Pos (6UL)                  /*!< DSP0N1GPIO102 (Bit 6)                                 */
38490 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO102_Msk (0x40UL)               /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
38491 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO101_Pos (5UL)                  /*!< DSP0N1GPIO101 (Bit 5)                                 */
38492 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO101_Msk (0x20UL)               /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
38493 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO100_Pos (4UL)                  /*!< DSP0N1GPIO100 (Bit 4)                                 */
38494 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO100_Msk (0x10UL)               /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
38495 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO99_Pos (3UL)                   /*!< DSP0N1GPIO99 (Bit 3)                                  */
38496 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO99_Msk (0x8UL)                 /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
38497 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO98_Pos (2UL)                   /*!< DSP0N1GPIO98 (Bit 2)                                  */
38498 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO98_Msk (0x4UL)                 /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
38499 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO97_Pos (1UL)                   /*!< DSP0N1GPIO97 (Bit 1)                                  */
38500 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO97_Msk (0x2UL)                 /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
38501 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO96_Pos (0UL)                   /*!< DSP0N1GPIO96 (Bit 0)                                  */
38502 #define GPIO_DSP0N1INT3SET_DSP0N1GPIO96_Msk (0x1UL)                 /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
38503 /* =====================================================  DSP1N0INT0EN  ====================================================== */
38504 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO31_Pos (31UL)                   /*!< DSP1N0GPIO31 (Bit 31)                                 */
38505 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO31_Msk (0x80000000UL)           /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
38506 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO30_Pos (30UL)                   /*!< DSP1N0GPIO30 (Bit 30)                                 */
38507 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO30_Msk (0x40000000UL)           /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
38508 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO29_Pos (29UL)                   /*!< DSP1N0GPIO29 (Bit 29)                                 */
38509 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO29_Msk (0x20000000UL)           /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
38510 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO28_Pos (28UL)                   /*!< DSP1N0GPIO28 (Bit 28)                                 */
38511 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO28_Msk (0x10000000UL)           /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
38512 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO27_Pos (27UL)                   /*!< DSP1N0GPIO27 (Bit 27)                                 */
38513 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO27_Msk (0x8000000UL)            /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
38514 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO26_Pos (26UL)                   /*!< DSP1N0GPIO26 (Bit 26)                                 */
38515 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO26_Msk (0x4000000UL)            /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
38516 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO25_Pos (25UL)                   /*!< DSP1N0GPIO25 (Bit 25)                                 */
38517 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO25_Msk (0x2000000UL)            /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
38518 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO24_Pos (24UL)                   /*!< DSP1N0GPIO24 (Bit 24)                                 */
38519 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO24_Msk (0x1000000UL)            /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
38520 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO23_Pos (23UL)                   /*!< DSP1N0GPIO23 (Bit 23)                                 */
38521 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO23_Msk (0x800000UL)             /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
38522 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO22_Pos (22UL)                   /*!< DSP1N0GPIO22 (Bit 22)                                 */
38523 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO22_Msk (0x400000UL)             /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
38524 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO21_Pos (21UL)                   /*!< DSP1N0GPIO21 (Bit 21)                                 */
38525 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO21_Msk (0x200000UL)             /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
38526 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO20_Pos (20UL)                   /*!< DSP1N0GPIO20 (Bit 20)                                 */
38527 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO20_Msk (0x100000UL)             /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
38528 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO19_Pos (19UL)                   /*!< DSP1N0GPIO19 (Bit 19)                                 */
38529 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO19_Msk (0x80000UL)              /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
38530 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO18_Pos (18UL)                   /*!< DSP1N0GPIO18 (Bit 18)                                 */
38531 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO18_Msk (0x40000UL)              /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
38532 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO17_Pos (17UL)                   /*!< DSP1N0GPIO17 (Bit 17)                                 */
38533 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO17_Msk (0x20000UL)              /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
38534 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO16_Pos (16UL)                   /*!< DSP1N0GPIO16 (Bit 16)                                 */
38535 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO16_Msk (0x10000UL)              /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
38536 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO15_Pos (15UL)                   /*!< DSP1N0GPIO15 (Bit 15)                                 */
38537 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO15_Msk (0x8000UL)               /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
38538 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO14_Pos (14UL)                   /*!< DSP1N0GPIO14 (Bit 14)                                 */
38539 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO14_Msk (0x4000UL)               /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
38540 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO13_Pos (13UL)                   /*!< DSP1N0GPIO13 (Bit 13)                                 */
38541 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO13_Msk (0x2000UL)               /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
38542 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO12_Pos (12UL)                   /*!< DSP1N0GPIO12 (Bit 12)                                 */
38543 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO12_Msk (0x1000UL)               /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
38544 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO11_Pos (11UL)                   /*!< DSP1N0GPIO11 (Bit 11)                                 */
38545 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO11_Msk (0x800UL)                /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
38546 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO10_Pos (10UL)                   /*!< DSP1N0GPIO10 (Bit 10)                                 */
38547 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO10_Msk (0x400UL)                /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
38548 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO9_Pos (9UL)                     /*!< DSP1N0GPIO9 (Bit 9)                                   */
38549 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO9_Msk (0x200UL)                 /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
38550 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO8_Pos (8UL)                     /*!< DSP1N0GPIO8 (Bit 8)                                   */
38551 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO8_Msk (0x100UL)                 /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
38552 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO7_Pos (7UL)                     /*!< DSP1N0GPIO7 (Bit 7)                                   */
38553 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO7_Msk (0x80UL)                  /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
38554 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO6_Pos (6UL)                     /*!< DSP1N0GPIO6 (Bit 6)                                   */
38555 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO6_Msk (0x40UL)                  /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
38556 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO5_Pos (5UL)                     /*!< DSP1N0GPIO5 (Bit 5)                                   */
38557 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO5_Msk (0x20UL)                  /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
38558 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO4_Pos (4UL)                     /*!< DSP1N0GPIO4 (Bit 4)                                   */
38559 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO4_Msk (0x10UL)                  /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
38560 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO3_Pos (3UL)                     /*!< DSP1N0GPIO3 (Bit 3)                                   */
38561 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO3_Msk (0x8UL)                   /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
38562 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO2_Pos (2UL)                     /*!< DSP1N0GPIO2 (Bit 2)                                   */
38563 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO2_Msk (0x4UL)                   /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
38564 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO1_Pos (1UL)                     /*!< DSP1N0GPIO1 (Bit 1)                                   */
38565 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO1_Msk (0x2UL)                   /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
38566 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO0_Pos (0UL)                     /*!< DSP1N0GPIO0 (Bit 0)                                   */
38567 #define GPIO_DSP1N0INT0EN_DSP1N0GPIO0_Msk (0x1UL)                   /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
38568 /* ====================================================  DSP1N0INT0STAT  ===================================================== */
38569 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO31_Pos (31UL)                 /*!< DSP1N0GPIO31 (Bit 31)                                 */
38570 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO31_Msk (0x80000000UL)         /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
38571 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO30_Pos (30UL)                 /*!< DSP1N0GPIO30 (Bit 30)                                 */
38572 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO30_Msk (0x40000000UL)         /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
38573 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO29_Pos (29UL)                 /*!< DSP1N0GPIO29 (Bit 29)                                 */
38574 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO29_Msk (0x20000000UL)         /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
38575 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO28_Pos (28UL)                 /*!< DSP1N0GPIO28 (Bit 28)                                 */
38576 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO28_Msk (0x10000000UL)         /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
38577 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO27_Pos (27UL)                 /*!< DSP1N0GPIO27 (Bit 27)                                 */
38578 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO27_Msk (0x8000000UL)          /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
38579 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO26_Pos (26UL)                 /*!< DSP1N0GPIO26 (Bit 26)                                 */
38580 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO26_Msk (0x4000000UL)          /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
38581 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO25_Pos (25UL)                 /*!< DSP1N0GPIO25 (Bit 25)                                 */
38582 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO25_Msk (0x2000000UL)          /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
38583 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO24_Pos (24UL)                 /*!< DSP1N0GPIO24 (Bit 24)                                 */
38584 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO24_Msk (0x1000000UL)          /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
38585 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO23_Pos (23UL)                 /*!< DSP1N0GPIO23 (Bit 23)                                 */
38586 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO23_Msk (0x800000UL)           /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
38587 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO22_Pos (22UL)                 /*!< DSP1N0GPIO22 (Bit 22)                                 */
38588 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO22_Msk (0x400000UL)           /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
38589 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO21_Pos (21UL)                 /*!< DSP1N0GPIO21 (Bit 21)                                 */
38590 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO21_Msk (0x200000UL)           /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
38591 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO20_Pos (20UL)                 /*!< DSP1N0GPIO20 (Bit 20)                                 */
38592 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO20_Msk (0x100000UL)           /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
38593 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO19_Pos (19UL)                 /*!< DSP1N0GPIO19 (Bit 19)                                 */
38594 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO19_Msk (0x80000UL)            /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
38595 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO18_Pos (18UL)                 /*!< DSP1N0GPIO18 (Bit 18)                                 */
38596 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO18_Msk (0x40000UL)            /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
38597 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO17_Pos (17UL)                 /*!< DSP1N0GPIO17 (Bit 17)                                 */
38598 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO17_Msk (0x20000UL)            /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
38599 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO16_Pos (16UL)                 /*!< DSP1N0GPIO16 (Bit 16)                                 */
38600 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO16_Msk (0x10000UL)            /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
38601 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO15_Pos (15UL)                 /*!< DSP1N0GPIO15 (Bit 15)                                 */
38602 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO15_Msk (0x8000UL)             /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
38603 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO14_Pos (14UL)                 /*!< DSP1N0GPIO14 (Bit 14)                                 */
38604 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO14_Msk (0x4000UL)             /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
38605 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO13_Pos (13UL)                 /*!< DSP1N0GPIO13 (Bit 13)                                 */
38606 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO13_Msk (0x2000UL)             /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
38607 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO12_Pos (12UL)                 /*!< DSP1N0GPIO12 (Bit 12)                                 */
38608 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO12_Msk (0x1000UL)             /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
38609 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO11_Pos (11UL)                 /*!< DSP1N0GPIO11 (Bit 11)                                 */
38610 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO11_Msk (0x800UL)              /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
38611 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO10_Pos (10UL)                 /*!< DSP1N0GPIO10 (Bit 10)                                 */
38612 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO10_Msk (0x400UL)              /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
38613 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO9_Pos (9UL)                   /*!< DSP1N0GPIO9 (Bit 9)                                   */
38614 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO9_Msk (0x200UL)               /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
38615 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO8_Pos (8UL)                   /*!< DSP1N0GPIO8 (Bit 8)                                   */
38616 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO8_Msk (0x100UL)               /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
38617 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO7_Pos (7UL)                   /*!< DSP1N0GPIO7 (Bit 7)                                   */
38618 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO7_Msk (0x80UL)                /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
38619 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO6_Pos (6UL)                   /*!< DSP1N0GPIO6 (Bit 6)                                   */
38620 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO6_Msk (0x40UL)                /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
38621 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO5_Pos (5UL)                   /*!< DSP1N0GPIO5 (Bit 5)                                   */
38622 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO5_Msk (0x20UL)                /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
38623 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO4_Pos (4UL)                   /*!< DSP1N0GPIO4 (Bit 4)                                   */
38624 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO4_Msk (0x10UL)                /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
38625 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO3_Pos (3UL)                   /*!< DSP1N0GPIO3 (Bit 3)                                   */
38626 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO3_Msk (0x8UL)                 /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
38627 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO2_Pos (2UL)                   /*!< DSP1N0GPIO2 (Bit 2)                                   */
38628 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO2_Msk (0x4UL)                 /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
38629 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO1_Pos (1UL)                   /*!< DSP1N0GPIO1 (Bit 1)                                   */
38630 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO1_Msk (0x2UL)                 /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
38631 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO0_Pos (0UL)                   /*!< DSP1N0GPIO0 (Bit 0)                                   */
38632 #define GPIO_DSP1N0INT0STAT_DSP1N0GPIO0_Msk (0x1UL)                 /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
38633 /* =====================================================  DSP1N0INT0CLR  ===================================================== */
38634 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO31_Pos (31UL)                  /*!< DSP1N0GPIO31 (Bit 31)                                 */
38635 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO31_Msk (0x80000000UL)          /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
38636 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO30_Pos (30UL)                  /*!< DSP1N0GPIO30 (Bit 30)                                 */
38637 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO30_Msk (0x40000000UL)          /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
38638 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO29_Pos (29UL)                  /*!< DSP1N0GPIO29 (Bit 29)                                 */
38639 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO29_Msk (0x20000000UL)          /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
38640 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO28_Pos (28UL)                  /*!< DSP1N0GPIO28 (Bit 28)                                 */
38641 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO28_Msk (0x10000000UL)          /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
38642 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO27_Pos (27UL)                  /*!< DSP1N0GPIO27 (Bit 27)                                 */
38643 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO27_Msk (0x8000000UL)           /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
38644 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO26_Pos (26UL)                  /*!< DSP1N0GPIO26 (Bit 26)                                 */
38645 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO26_Msk (0x4000000UL)           /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
38646 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO25_Pos (25UL)                  /*!< DSP1N0GPIO25 (Bit 25)                                 */
38647 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO25_Msk (0x2000000UL)           /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
38648 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO24_Pos (24UL)                  /*!< DSP1N0GPIO24 (Bit 24)                                 */
38649 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO24_Msk (0x1000000UL)           /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
38650 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO23_Pos (23UL)                  /*!< DSP1N0GPIO23 (Bit 23)                                 */
38651 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO23_Msk (0x800000UL)            /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
38652 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO22_Pos (22UL)                  /*!< DSP1N0GPIO22 (Bit 22)                                 */
38653 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO22_Msk (0x400000UL)            /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
38654 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO21_Pos (21UL)                  /*!< DSP1N0GPIO21 (Bit 21)                                 */
38655 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO21_Msk (0x200000UL)            /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
38656 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO20_Pos (20UL)                  /*!< DSP1N0GPIO20 (Bit 20)                                 */
38657 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO20_Msk (0x100000UL)            /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
38658 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO19_Pos (19UL)                  /*!< DSP1N0GPIO19 (Bit 19)                                 */
38659 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO19_Msk (0x80000UL)             /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
38660 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO18_Pos (18UL)                  /*!< DSP1N0GPIO18 (Bit 18)                                 */
38661 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO18_Msk (0x40000UL)             /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
38662 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO17_Pos (17UL)                  /*!< DSP1N0GPIO17 (Bit 17)                                 */
38663 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO17_Msk (0x20000UL)             /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
38664 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO16_Pos (16UL)                  /*!< DSP1N0GPIO16 (Bit 16)                                 */
38665 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO16_Msk (0x10000UL)             /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
38666 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO15_Pos (15UL)                  /*!< DSP1N0GPIO15 (Bit 15)                                 */
38667 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO15_Msk (0x8000UL)              /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
38668 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO14_Pos (14UL)                  /*!< DSP1N0GPIO14 (Bit 14)                                 */
38669 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO14_Msk (0x4000UL)              /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
38670 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO13_Pos (13UL)                  /*!< DSP1N0GPIO13 (Bit 13)                                 */
38671 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO13_Msk (0x2000UL)              /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
38672 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO12_Pos (12UL)                  /*!< DSP1N0GPIO12 (Bit 12)                                 */
38673 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO12_Msk (0x1000UL)              /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
38674 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO11_Pos (11UL)                  /*!< DSP1N0GPIO11 (Bit 11)                                 */
38675 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO11_Msk (0x800UL)               /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
38676 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO10_Pos (10UL)                  /*!< DSP1N0GPIO10 (Bit 10)                                 */
38677 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO10_Msk (0x400UL)               /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
38678 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO9_Pos (9UL)                    /*!< DSP1N0GPIO9 (Bit 9)                                   */
38679 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO9_Msk (0x200UL)                /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
38680 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO8_Pos (8UL)                    /*!< DSP1N0GPIO8 (Bit 8)                                   */
38681 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO8_Msk (0x100UL)                /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
38682 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO7_Pos (7UL)                    /*!< DSP1N0GPIO7 (Bit 7)                                   */
38683 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO7_Msk (0x80UL)                 /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
38684 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO6_Pos (6UL)                    /*!< DSP1N0GPIO6 (Bit 6)                                   */
38685 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO6_Msk (0x40UL)                 /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
38686 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO5_Pos (5UL)                    /*!< DSP1N0GPIO5 (Bit 5)                                   */
38687 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO5_Msk (0x20UL)                 /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
38688 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO4_Pos (4UL)                    /*!< DSP1N0GPIO4 (Bit 4)                                   */
38689 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO4_Msk (0x10UL)                 /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
38690 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO3_Pos (3UL)                    /*!< DSP1N0GPIO3 (Bit 3)                                   */
38691 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO3_Msk (0x8UL)                  /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
38692 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO2_Pos (2UL)                    /*!< DSP1N0GPIO2 (Bit 2)                                   */
38693 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO2_Msk (0x4UL)                  /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
38694 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO1_Pos (1UL)                    /*!< DSP1N0GPIO1 (Bit 1)                                   */
38695 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO1_Msk (0x2UL)                  /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
38696 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO0_Pos (0UL)                    /*!< DSP1N0GPIO0 (Bit 0)                                   */
38697 #define GPIO_DSP1N0INT0CLR_DSP1N0GPIO0_Msk (0x1UL)                  /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
38698 /* =====================================================  DSP1N0INT0SET  ===================================================== */
38699 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO31_Pos (31UL)                  /*!< DSP1N0GPIO31 (Bit 31)                                 */
38700 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO31_Msk (0x80000000UL)          /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
38701 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO30_Pos (30UL)                  /*!< DSP1N0GPIO30 (Bit 30)                                 */
38702 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO30_Msk (0x40000000UL)          /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
38703 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO29_Pos (29UL)                  /*!< DSP1N0GPIO29 (Bit 29)                                 */
38704 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO29_Msk (0x20000000UL)          /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
38705 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO28_Pos (28UL)                  /*!< DSP1N0GPIO28 (Bit 28)                                 */
38706 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO28_Msk (0x10000000UL)          /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
38707 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO27_Pos (27UL)                  /*!< DSP1N0GPIO27 (Bit 27)                                 */
38708 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO27_Msk (0x8000000UL)           /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
38709 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO26_Pos (26UL)                  /*!< DSP1N0GPIO26 (Bit 26)                                 */
38710 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO26_Msk (0x4000000UL)           /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
38711 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO25_Pos (25UL)                  /*!< DSP1N0GPIO25 (Bit 25)                                 */
38712 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO25_Msk (0x2000000UL)           /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
38713 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO24_Pos (24UL)                  /*!< DSP1N0GPIO24 (Bit 24)                                 */
38714 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO24_Msk (0x1000000UL)           /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
38715 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO23_Pos (23UL)                  /*!< DSP1N0GPIO23 (Bit 23)                                 */
38716 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO23_Msk (0x800000UL)            /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
38717 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO22_Pos (22UL)                  /*!< DSP1N0GPIO22 (Bit 22)                                 */
38718 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO22_Msk (0x400000UL)            /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
38719 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO21_Pos (21UL)                  /*!< DSP1N0GPIO21 (Bit 21)                                 */
38720 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO21_Msk (0x200000UL)            /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
38721 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO20_Pos (20UL)                  /*!< DSP1N0GPIO20 (Bit 20)                                 */
38722 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO20_Msk (0x100000UL)            /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
38723 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO19_Pos (19UL)                  /*!< DSP1N0GPIO19 (Bit 19)                                 */
38724 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO19_Msk (0x80000UL)             /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
38725 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO18_Pos (18UL)                  /*!< DSP1N0GPIO18 (Bit 18)                                 */
38726 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO18_Msk (0x40000UL)             /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
38727 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO17_Pos (17UL)                  /*!< DSP1N0GPIO17 (Bit 17)                                 */
38728 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO17_Msk (0x20000UL)             /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
38729 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO16_Pos (16UL)                  /*!< DSP1N0GPIO16 (Bit 16)                                 */
38730 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO16_Msk (0x10000UL)             /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
38731 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO15_Pos (15UL)                  /*!< DSP1N0GPIO15 (Bit 15)                                 */
38732 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO15_Msk (0x8000UL)              /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
38733 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO14_Pos (14UL)                  /*!< DSP1N0GPIO14 (Bit 14)                                 */
38734 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO14_Msk (0x4000UL)              /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
38735 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO13_Pos (13UL)                  /*!< DSP1N0GPIO13 (Bit 13)                                 */
38736 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO13_Msk (0x2000UL)              /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
38737 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO12_Pos (12UL)                  /*!< DSP1N0GPIO12 (Bit 12)                                 */
38738 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO12_Msk (0x1000UL)              /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
38739 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO11_Pos (11UL)                  /*!< DSP1N0GPIO11 (Bit 11)                                 */
38740 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO11_Msk (0x800UL)               /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
38741 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO10_Pos (10UL)                  /*!< DSP1N0GPIO10 (Bit 10)                                 */
38742 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO10_Msk (0x400UL)               /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
38743 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO9_Pos (9UL)                    /*!< DSP1N0GPIO9 (Bit 9)                                   */
38744 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO9_Msk (0x200UL)                /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
38745 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO8_Pos (8UL)                    /*!< DSP1N0GPIO8 (Bit 8)                                   */
38746 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO8_Msk (0x100UL)                /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
38747 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO7_Pos (7UL)                    /*!< DSP1N0GPIO7 (Bit 7)                                   */
38748 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO7_Msk (0x80UL)                 /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
38749 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO6_Pos (6UL)                    /*!< DSP1N0GPIO6 (Bit 6)                                   */
38750 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO6_Msk (0x40UL)                 /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
38751 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO5_Pos (5UL)                    /*!< DSP1N0GPIO5 (Bit 5)                                   */
38752 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO5_Msk (0x20UL)                 /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
38753 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO4_Pos (4UL)                    /*!< DSP1N0GPIO4 (Bit 4)                                   */
38754 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO4_Msk (0x10UL)                 /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
38755 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO3_Pos (3UL)                    /*!< DSP1N0GPIO3 (Bit 3)                                   */
38756 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO3_Msk (0x8UL)                  /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
38757 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO2_Pos (2UL)                    /*!< DSP1N0GPIO2 (Bit 2)                                   */
38758 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO2_Msk (0x4UL)                  /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
38759 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO1_Pos (1UL)                    /*!< DSP1N0GPIO1 (Bit 1)                                   */
38760 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO1_Msk (0x2UL)                  /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
38761 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO0_Pos (0UL)                    /*!< DSP1N0GPIO0 (Bit 0)                                   */
38762 #define GPIO_DSP1N0INT0SET_DSP1N0GPIO0_Msk (0x1UL)                  /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
38763 /* =====================================================  DSP1N0INT1EN  ====================================================== */
38764 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO63_Pos (31UL)                   /*!< DSP1N0GPIO63 (Bit 31)                                 */
38765 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO63_Msk (0x80000000UL)           /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
38766 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO62_Pos (30UL)                   /*!< DSP1N0GPIO62 (Bit 30)                                 */
38767 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO62_Msk (0x40000000UL)           /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
38768 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO61_Pos (29UL)                   /*!< DSP1N0GPIO61 (Bit 29)                                 */
38769 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO61_Msk (0x20000000UL)           /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
38770 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO60_Pos (28UL)                   /*!< DSP1N0GPIO60 (Bit 28)                                 */
38771 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO60_Msk (0x10000000UL)           /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
38772 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO59_Pos (27UL)                   /*!< DSP1N0GPIO59 (Bit 27)                                 */
38773 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO59_Msk (0x8000000UL)            /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
38774 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO58_Pos (26UL)                   /*!< DSP1N0GPIO58 (Bit 26)                                 */
38775 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO58_Msk (0x4000000UL)            /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
38776 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO57_Pos (25UL)                   /*!< DSP1N0GPIO57 (Bit 25)                                 */
38777 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO57_Msk (0x2000000UL)            /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
38778 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO56_Pos (24UL)                   /*!< DSP1N0GPIO56 (Bit 24)                                 */
38779 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO56_Msk (0x1000000UL)            /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
38780 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO55_Pos (23UL)                   /*!< DSP1N0GPIO55 (Bit 23)                                 */
38781 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO55_Msk (0x800000UL)             /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
38782 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO54_Pos (22UL)                   /*!< DSP1N0GPIO54 (Bit 22)                                 */
38783 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO54_Msk (0x400000UL)             /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
38784 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO53_Pos (21UL)                   /*!< DSP1N0GPIO53 (Bit 21)                                 */
38785 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO53_Msk (0x200000UL)             /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
38786 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO52_Pos (20UL)                   /*!< DSP1N0GPIO52 (Bit 20)                                 */
38787 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO52_Msk (0x100000UL)             /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
38788 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO51_Pos (19UL)                   /*!< DSP1N0GPIO51 (Bit 19)                                 */
38789 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO51_Msk (0x80000UL)              /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
38790 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO50_Pos (18UL)                   /*!< DSP1N0GPIO50 (Bit 18)                                 */
38791 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO50_Msk (0x40000UL)              /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
38792 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO49_Pos (17UL)                   /*!< DSP1N0GPIO49 (Bit 17)                                 */
38793 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO49_Msk (0x20000UL)              /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
38794 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO48_Pos (16UL)                   /*!< DSP1N0GPIO48 (Bit 16)                                 */
38795 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO48_Msk (0x10000UL)              /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
38796 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO47_Pos (15UL)                   /*!< DSP1N0GPIO47 (Bit 15)                                 */
38797 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO47_Msk (0x8000UL)               /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
38798 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO46_Pos (14UL)                   /*!< DSP1N0GPIO46 (Bit 14)                                 */
38799 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO46_Msk (0x4000UL)               /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
38800 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO45_Pos (13UL)                   /*!< DSP1N0GPIO45 (Bit 13)                                 */
38801 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO45_Msk (0x2000UL)               /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
38802 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO44_Pos (12UL)                   /*!< DSP1N0GPIO44 (Bit 12)                                 */
38803 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO44_Msk (0x1000UL)               /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
38804 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO43_Pos (11UL)                   /*!< DSP1N0GPIO43 (Bit 11)                                 */
38805 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO43_Msk (0x800UL)                /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
38806 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO42_Pos (10UL)                   /*!< DSP1N0GPIO42 (Bit 10)                                 */
38807 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO42_Msk (0x400UL)                /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
38808 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO41_Pos (9UL)                    /*!< DSP1N0GPIO41 (Bit 9)                                  */
38809 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO41_Msk (0x200UL)                /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
38810 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO40_Pos (8UL)                    /*!< DSP1N0GPIO40 (Bit 8)                                  */
38811 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO40_Msk (0x100UL)                /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
38812 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO39_Pos (7UL)                    /*!< DSP1N0GPIO39 (Bit 7)                                  */
38813 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO39_Msk (0x80UL)                 /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
38814 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO38_Pos (6UL)                    /*!< DSP1N0GPIO38 (Bit 6)                                  */
38815 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO38_Msk (0x40UL)                 /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
38816 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO37_Pos (5UL)                    /*!< DSP1N0GPIO37 (Bit 5)                                  */
38817 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO37_Msk (0x20UL)                 /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
38818 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO36_Pos (4UL)                    /*!< DSP1N0GPIO36 (Bit 4)                                  */
38819 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO36_Msk (0x10UL)                 /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
38820 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO35_Pos (3UL)                    /*!< DSP1N0GPIO35 (Bit 3)                                  */
38821 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO35_Msk (0x8UL)                  /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
38822 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO34_Pos (2UL)                    /*!< DSP1N0GPIO34 (Bit 2)                                  */
38823 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO34_Msk (0x4UL)                  /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
38824 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO33_Pos (1UL)                    /*!< DSP1N0GPIO33 (Bit 1)                                  */
38825 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO33_Msk (0x2UL)                  /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
38826 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO32_Pos (0UL)                    /*!< DSP1N0GPIO32 (Bit 0)                                  */
38827 #define GPIO_DSP1N0INT1EN_DSP1N0GPIO32_Msk (0x1UL)                  /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
38828 /* ====================================================  DSP1N0INT1STAT  ===================================================== */
38829 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO63_Pos (31UL)                 /*!< DSP1N0GPIO63 (Bit 31)                                 */
38830 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO63_Msk (0x80000000UL)         /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
38831 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO62_Pos (30UL)                 /*!< DSP1N0GPIO62 (Bit 30)                                 */
38832 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO62_Msk (0x40000000UL)         /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
38833 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO61_Pos (29UL)                 /*!< DSP1N0GPIO61 (Bit 29)                                 */
38834 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO61_Msk (0x20000000UL)         /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
38835 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO60_Pos (28UL)                 /*!< DSP1N0GPIO60 (Bit 28)                                 */
38836 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO60_Msk (0x10000000UL)         /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
38837 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO59_Pos (27UL)                 /*!< DSP1N0GPIO59 (Bit 27)                                 */
38838 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO59_Msk (0x8000000UL)          /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
38839 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO58_Pos (26UL)                 /*!< DSP1N0GPIO58 (Bit 26)                                 */
38840 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO58_Msk (0x4000000UL)          /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
38841 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO57_Pos (25UL)                 /*!< DSP1N0GPIO57 (Bit 25)                                 */
38842 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO57_Msk (0x2000000UL)          /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
38843 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO56_Pos (24UL)                 /*!< DSP1N0GPIO56 (Bit 24)                                 */
38844 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO56_Msk (0x1000000UL)          /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
38845 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO55_Pos (23UL)                 /*!< DSP1N0GPIO55 (Bit 23)                                 */
38846 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO55_Msk (0x800000UL)           /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
38847 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO54_Pos (22UL)                 /*!< DSP1N0GPIO54 (Bit 22)                                 */
38848 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO54_Msk (0x400000UL)           /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
38849 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO53_Pos (21UL)                 /*!< DSP1N0GPIO53 (Bit 21)                                 */
38850 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO53_Msk (0x200000UL)           /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
38851 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO52_Pos (20UL)                 /*!< DSP1N0GPIO52 (Bit 20)                                 */
38852 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO52_Msk (0x100000UL)           /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
38853 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO51_Pos (19UL)                 /*!< DSP1N0GPIO51 (Bit 19)                                 */
38854 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO51_Msk (0x80000UL)            /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
38855 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO50_Pos (18UL)                 /*!< DSP1N0GPIO50 (Bit 18)                                 */
38856 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO50_Msk (0x40000UL)            /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
38857 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO49_Pos (17UL)                 /*!< DSP1N0GPIO49 (Bit 17)                                 */
38858 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO49_Msk (0x20000UL)            /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
38859 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO48_Pos (16UL)                 /*!< DSP1N0GPIO48 (Bit 16)                                 */
38860 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO48_Msk (0x10000UL)            /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
38861 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO47_Pos (15UL)                 /*!< DSP1N0GPIO47 (Bit 15)                                 */
38862 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO47_Msk (0x8000UL)             /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
38863 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO46_Pos (14UL)                 /*!< DSP1N0GPIO46 (Bit 14)                                 */
38864 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO46_Msk (0x4000UL)             /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
38865 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO45_Pos (13UL)                 /*!< DSP1N0GPIO45 (Bit 13)                                 */
38866 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO45_Msk (0x2000UL)             /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
38867 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO44_Pos (12UL)                 /*!< DSP1N0GPIO44 (Bit 12)                                 */
38868 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO44_Msk (0x1000UL)             /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
38869 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO43_Pos (11UL)                 /*!< DSP1N0GPIO43 (Bit 11)                                 */
38870 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO43_Msk (0x800UL)              /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
38871 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO42_Pos (10UL)                 /*!< DSP1N0GPIO42 (Bit 10)                                 */
38872 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO42_Msk (0x400UL)              /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
38873 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO41_Pos (9UL)                  /*!< DSP1N0GPIO41 (Bit 9)                                  */
38874 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO41_Msk (0x200UL)              /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
38875 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO40_Pos (8UL)                  /*!< DSP1N0GPIO40 (Bit 8)                                  */
38876 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO40_Msk (0x100UL)              /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
38877 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO39_Pos (7UL)                  /*!< DSP1N0GPIO39 (Bit 7)                                  */
38878 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO39_Msk (0x80UL)               /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
38879 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO38_Pos (6UL)                  /*!< DSP1N0GPIO38 (Bit 6)                                  */
38880 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO38_Msk (0x40UL)               /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
38881 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO37_Pos (5UL)                  /*!< DSP1N0GPIO37 (Bit 5)                                  */
38882 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO37_Msk (0x20UL)               /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
38883 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO36_Pos (4UL)                  /*!< DSP1N0GPIO36 (Bit 4)                                  */
38884 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO36_Msk (0x10UL)               /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
38885 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO35_Pos (3UL)                  /*!< DSP1N0GPIO35 (Bit 3)                                  */
38886 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO35_Msk (0x8UL)                /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
38887 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO34_Pos (2UL)                  /*!< DSP1N0GPIO34 (Bit 2)                                  */
38888 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO34_Msk (0x4UL)                /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
38889 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO33_Pos (1UL)                  /*!< DSP1N0GPIO33 (Bit 1)                                  */
38890 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO33_Msk (0x2UL)                /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
38891 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO32_Pos (0UL)                  /*!< DSP1N0GPIO32 (Bit 0)                                  */
38892 #define GPIO_DSP1N0INT1STAT_DSP1N0GPIO32_Msk (0x1UL)                /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
38893 /* =====================================================  DSP1N0INT1CLR  ===================================================== */
38894 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO63_Pos (31UL)                  /*!< DSP1N0GPIO63 (Bit 31)                                 */
38895 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO63_Msk (0x80000000UL)          /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
38896 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO62_Pos (30UL)                  /*!< DSP1N0GPIO62 (Bit 30)                                 */
38897 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO62_Msk (0x40000000UL)          /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
38898 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO61_Pos (29UL)                  /*!< DSP1N0GPIO61 (Bit 29)                                 */
38899 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO61_Msk (0x20000000UL)          /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
38900 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO60_Pos (28UL)                  /*!< DSP1N0GPIO60 (Bit 28)                                 */
38901 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO60_Msk (0x10000000UL)          /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
38902 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO59_Pos (27UL)                  /*!< DSP1N0GPIO59 (Bit 27)                                 */
38903 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO59_Msk (0x8000000UL)           /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
38904 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO58_Pos (26UL)                  /*!< DSP1N0GPIO58 (Bit 26)                                 */
38905 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO58_Msk (0x4000000UL)           /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
38906 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO57_Pos (25UL)                  /*!< DSP1N0GPIO57 (Bit 25)                                 */
38907 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO57_Msk (0x2000000UL)           /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
38908 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO56_Pos (24UL)                  /*!< DSP1N0GPIO56 (Bit 24)                                 */
38909 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO56_Msk (0x1000000UL)           /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
38910 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO55_Pos (23UL)                  /*!< DSP1N0GPIO55 (Bit 23)                                 */
38911 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO55_Msk (0x800000UL)            /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
38912 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO54_Pos (22UL)                  /*!< DSP1N0GPIO54 (Bit 22)                                 */
38913 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO54_Msk (0x400000UL)            /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
38914 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO53_Pos (21UL)                  /*!< DSP1N0GPIO53 (Bit 21)                                 */
38915 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO53_Msk (0x200000UL)            /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
38916 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO52_Pos (20UL)                  /*!< DSP1N0GPIO52 (Bit 20)                                 */
38917 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO52_Msk (0x100000UL)            /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
38918 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO51_Pos (19UL)                  /*!< DSP1N0GPIO51 (Bit 19)                                 */
38919 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO51_Msk (0x80000UL)             /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
38920 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO50_Pos (18UL)                  /*!< DSP1N0GPIO50 (Bit 18)                                 */
38921 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO50_Msk (0x40000UL)             /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
38922 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO49_Pos (17UL)                  /*!< DSP1N0GPIO49 (Bit 17)                                 */
38923 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO49_Msk (0x20000UL)             /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
38924 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO48_Pos (16UL)                  /*!< DSP1N0GPIO48 (Bit 16)                                 */
38925 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO48_Msk (0x10000UL)             /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
38926 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO47_Pos (15UL)                  /*!< DSP1N0GPIO47 (Bit 15)                                 */
38927 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO47_Msk (0x8000UL)              /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
38928 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO46_Pos (14UL)                  /*!< DSP1N0GPIO46 (Bit 14)                                 */
38929 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO46_Msk (0x4000UL)              /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
38930 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO45_Pos (13UL)                  /*!< DSP1N0GPIO45 (Bit 13)                                 */
38931 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO45_Msk (0x2000UL)              /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
38932 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO44_Pos (12UL)                  /*!< DSP1N0GPIO44 (Bit 12)                                 */
38933 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO44_Msk (0x1000UL)              /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
38934 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO43_Pos (11UL)                  /*!< DSP1N0GPIO43 (Bit 11)                                 */
38935 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO43_Msk (0x800UL)               /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
38936 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO42_Pos (10UL)                  /*!< DSP1N0GPIO42 (Bit 10)                                 */
38937 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO42_Msk (0x400UL)               /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
38938 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO41_Pos (9UL)                   /*!< DSP1N0GPIO41 (Bit 9)                                  */
38939 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO41_Msk (0x200UL)               /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
38940 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO40_Pos (8UL)                   /*!< DSP1N0GPIO40 (Bit 8)                                  */
38941 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO40_Msk (0x100UL)               /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
38942 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO39_Pos (7UL)                   /*!< DSP1N0GPIO39 (Bit 7)                                  */
38943 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO39_Msk (0x80UL)                /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
38944 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO38_Pos (6UL)                   /*!< DSP1N0GPIO38 (Bit 6)                                  */
38945 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO38_Msk (0x40UL)                /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
38946 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO37_Pos (5UL)                   /*!< DSP1N0GPIO37 (Bit 5)                                  */
38947 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO37_Msk (0x20UL)                /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
38948 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO36_Pos (4UL)                   /*!< DSP1N0GPIO36 (Bit 4)                                  */
38949 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO36_Msk (0x10UL)                /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
38950 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO35_Pos (3UL)                   /*!< DSP1N0GPIO35 (Bit 3)                                  */
38951 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO35_Msk (0x8UL)                 /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
38952 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO34_Pos (2UL)                   /*!< DSP1N0GPIO34 (Bit 2)                                  */
38953 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO34_Msk (0x4UL)                 /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
38954 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO33_Pos (1UL)                   /*!< DSP1N0GPIO33 (Bit 1)                                  */
38955 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO33_Msk (0x2UL)                 /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
38956 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO32_Pos (0UL)                   /*!< DSP1N0GPIO32 (Bit 0)                                  */
38957 #define GPIO_DSP1N0INT1CLR_DSP1N0GPIO32_Msk (0x1UL)                 /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
38958 /* =====================================================  DSP1N0INT1SET  ===================================================== */
38959 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO63_Pos (31UL)                  /*!< DSP1N0GPIO63 (Bit 31)                                 */
38960 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO63_Msk (0x80000000UL)          /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
38961 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO62_Pos (30UL)                  /*!< DSP1N0GPIO62 (Bit 30)                                 */
38962 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO62_Msk (0x40000000UL)          /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
38963 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO61_Pos (29UL)                  /*!< DSP1N0GPIO61 (Bit 29)                                 */
38964 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO61_Msk (0x20000000UL)          /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
38965 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO60_Pos (28UL)                  /*!< DSP1N0GPIO60 (Bit 28)                                 */
38966 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO60_Msk (0x10000000UL)          /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
38967 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO59_Pos (27UL)                  /*!< DSP1N0GPIO59 (Bit 27)                                 */
38968 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO59_Msk (0x8000000UL)           /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
38969 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO58_Pos (26UL)                  /*!< DSP1N0GPIO58 (Bit 26)                                 */
38970 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO58_Msk (0x4000000UL)           /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
38971 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO57_Pos (25UL)                  /*!< DSP1N0GPIO57 (Bit 25)                                 */
38972 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO57_Msk (0x2000000UL)           /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
38973 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO56_Pos (24UL)                  /*!< DSP1N0GPIO56 (Bit 24)                                 */
38974 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO56_Msk (0x1000000UL)           /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
38975 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO55_Pos (23UL)                  /*!< DSP1N0GPIO55 (Bit 23)                                 */
38976 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO55_Msk (0x800000UL)            /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
38977 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO54_Pos (22UL)                  /*!< DSP1N0GPIO54 (Bit 22)                                 */
38978 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO54_Msk (0x400000UL)            /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
38979 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO53_Pos (21UL)                  /*!< DSP1N0GPIO53 (Bit 21)                                 */
38980 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO53_Msk (0x200000UL)            /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
38981 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO52_Pos (20UL)                  /*!< DSP1N0GPIO52 (Bit 20)                                 */
38982 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO52_Msk (0x100000UL)            /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
38983 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO51_Pos (19UL)                  /*!< DSP1N0GPIO51 (Bit 19)                                 */
38984 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO51_Msk (0x80000UL)             /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
38985 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO50_Pos (18UL)                  /*!< DSP1N0GPIO50 (Bit 18)                                 */
38986 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO50_Msk (0x40000UL)             /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
38987 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO49_Pos (17UL)                  /*!< DSP1N0GPIO49 (Bit 17)                                 */
38988 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO49_Msk (0x20000UL)             /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
38989 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO48_Pos (16UL)                  /*!< DSP1N0GPIO48 (Bit 16)                                 */
38990 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO48_Msk (0x10000UL)             /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
38991 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO47_Pos (15UL)                  /*!< DSP1N0GPIO47 (Bit 15)                                 */
38992 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO47_Msk (0x8000UL)              /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
38993 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO46_Pos (14UL)                  /*!< DSP1N0GPIO46 (Bit 14)                                 */
38994 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO46_Msk (0x4000UL)              /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
38995 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO45_Pos (13UL)                  /*!< DSP1N0GPIO45 (Bit 13)                                 */
38996 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO45_Msk (0x2000UL)              /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
38997 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO44_Pos (12UL)                  /*!< DSP1N0GPIO44 (Bit 12)                                 */
38998 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO44_Msk (0x1000UL)              /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
38999 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO43_Pos (11UL)                  /*!< DSP1N0GPIO43 (Bit 11)                                 */
39000 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO43_Msk (0x800UL)               /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
39001 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO42_Pos (10UL)                  /*!< DSP1N0GPIO42 (Bit 10)                                 */
39002 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO42_Msk (0x400UL)               /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
39003 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO41_Pos (9UL)                   /*!< DSP1N0GPIO41 (Bit 9)                                  */
39004 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO41_Msk (0x200UL)               /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
39005 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO40_Pos (8UL)                   /*!< DSP1N0GPIO40 (Bit 8)                                  */
39006 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO40_Msk (0x100UL)               /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
39007 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO39_Pos (7UL)                   /*!< DSP1N0GPIO39 (Bit 7)                                  */
39008 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO39_Msk (0x80UL)                /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
39009 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO38_Pos (6UL)                   /*!< DSP1N0GPIO38 (Bit 6)                                  */
39010 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO38_Msk (0x40UL)                /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
39011 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO37_Pos (5UL)                   /*!< DSP1N0GPIO37 (Bit 5)                                  */
39012 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO37_Msk (0x20UL)                /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
39013 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO36_Pos (4UL)                   /*!< DSP1N0GPIO36 (Bit 4)                                  */
39014 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO36_Msk (0x10UL)                /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
39015 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO35_Pos (3UL)                   /*!< DSP1N0GPIO35 (Bit 3)                                  */
39016 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO35_Msk (0x8UL)                 /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
39017 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO34_Pos (2UL)                   /*!< DSP1N0GPIO34 (Bit 2)                                  */
39018 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO34_Msk (0x4UL)                 /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
39019 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO33_Pos (1UL)                   /*!< DSP1N0GPIO33 (Bit 1)                                  */
39020 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO33_Msk (0x2UL)                 /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
39021 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO32_Pos (0UL)                   /*!< DSP1N0GPIO32 (Bit 0)                                  */
39022 #define GPIO_DSP1N0INT1SET_DSP1N0GPIO32_Msk (0x1UL)                 /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
39023 /* =====================================================  DSP1N0INT2EN  ====================================================== */
39024 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO95_Pos (31UL)                   /*!< DSP1N0GPIO95 (Bit 31)                                 */
39025 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO95_Msk (0x80000000UL)           /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
39026 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO94_Pos (30UL)                   /*!< DSP1N0GPIO94 (Bit 30)                                 */
39027 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO94_Msk (0x40000000UL)           /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
39028 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO93_Pos (29UL)                   /*!< DSP1N0GPIO93 (Bit 29)                                 */
39029 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO93_Msk (0x20000000UL)           /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
39030 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO92_Pos (28UL)                   /*!< DSP1N0GPIO92 (Bit 28)                                 */
39031 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO92_Msk (0x10000000UL)           /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
39032 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO91_Pos (27UL)                   /*!< DSP1N0GPIO91 (Bit 27)                                 */
39033 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO91_Msk (0x8000000UL)            /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
39034 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO90_Pos (26UL)                   /*!< DSP1N0GPIO90 (Bit 26)                                 */
39035 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO90_Msk (0x4000000UL)            /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
39036 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO89_Pos (25UL)                   /*!< DSP1N0GPIO89 (Bit 25)                                 */
39037 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO89_Msk (0x2000000UL)            /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
39038 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO88_Pos (24UL)                   /*!< DSP1N0GPIO88 (Bit 24)                                 */
39039 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO88_Msk (0x1000000UL)            /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
39040 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO87_Pos (23UL)                   /*!< DSP1N0GPIO87 (Bit 23)                                 */
39041 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO87_Msk (0x800000UL)             /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
39042 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO86_Pos (22UL)                   /*!< DSP1N0GPIO86 (Bit 22)                                 */
39043 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO86_Msk (0x400000UL)             /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
39044 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO85_Pos (21UL)                   /*!< DSP1N0GPIO85 (Bit 21)                                 */
39045 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO85_Msk (0x200000UL)             /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
39046 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO84_Pos (20UL)                   /*!< DSP1N0GPIO84 (Bit 20)                                 */
39047 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO84_Msk (0x100000UL)             /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
39048 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO83_Pos (19UL)                   /*!< DSP1N0GPIO83 (Bit 19)                                 */
39049 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO83_Msk (0x80000UL)              /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
39050 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO82_Pos (18UL)                   /*!< DSP1N0GPIO82 (Bit 18)                                 */
39051 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO82_Msk (0x40000UL)              /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
39052 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO81_Pos (17UL)                   /*!< DSP1N0GPIO81 (Bit 17)                                 */
39053 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO81_Msk (0x20000UL)              /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
39054 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO80_Pos (16UL)                   /*!< DSP1N0GPIO80 (Bit 16)                                 */
39055 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO80_Msk (0x10000UL)              /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
39056 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO79_Pos (15UL)                   /*!< DSP1N0GPIO79 (Bit 15)                                 */
39057 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO79_Msk (0x8000UL)               /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
39058 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO78_Pos (14UL)                   /*!< DSP1N0GPIO78 (Bit 14)                                 */
39059 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO78_Msk (0x4000UL)               /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
39060 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO77_Pos (13UL)                   /*!< DSP1N0GPIO77 (Bit 13)                                 */
39061 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO77_Msk (0x2000UL)               /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
39062 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO76_Pos (12UL)                   /*!< DSP1N0GPIO76 (Bit 12)                                 */
39063 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO76_Msk (0x1000UL)               /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
39064 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO75_Pos (11UL)                   /*!< DSP1N0GPIO75 (Bit 11)                                 */
39065 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO75_Msk (0x800UL)                /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
39066 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO74_Pos (10UL)                   /*!< DSP1N0GPIO74 (Bit 10)                                 */
39067 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO74_Msk (0x400UL)                /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
39068 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO73_Pos (9UL)                    /*!< DSP1N0GPIO73 (Bit 9)                                  */
39069 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO73_Msk (0x200UL)                /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
39070 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO72_Pos (8UL)                    /*!< DSP1N0GPIO72 (Bit 8)                                  */
39071 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO72_Msk (0x100UL)                /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
39072 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO71_Pos (7UL)                    /*!< DSP1N0GPIO71 (Bit 7)                                  */
39073 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO71_Msk (0x80UL)                 /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
39074 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO70_Pos (6UL)                    /*!< DSP1N0GPIO70 (Bit 6)                                  */
39075 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO70_Msk (0x40UL)                 /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
39076 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO69_Pos (5UL)                    /*!< DSP1N0GPIO69 (Bit 5)                                  */
39077 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO69_Msk (0x20UL)                 /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
39078 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO68_Pos (4UL)                    /*!< DSP1N0GPIO68 (Bit 4)                                  */
39079 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO68_Msk (0x10UL)                 /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
39080 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO67_Pos (3UL)                    /*!< DSP1N0GPIO67 (Bit 3)                                  */
39081 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO67_Msk (0x8UL)                  /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
39082 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO66_Pos (2UL)                    /*!< DSP1N0GPIO66 (Bit 2)                                  */
39083 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO66_Msk (0x4UL)                  /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
39084 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO65_Pos (1UL)                    /*!< DSP1N0GPIO65 (Bit 1)                                  */
39085 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO65_Msk (0x2UL)                  /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
39086 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO64_Pos (0UL)                    /*!< DSP1N0GPIO64 (Bit 0)                                  */
39087 #define GPIO_DSP1N0INT2EN_DSP1N0GPIO64_Msk (0x1UL)                  /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
39088 /* ====================================================  DSP1N0INT2STAT  ===================================================== */
39089 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO95_Pos (31UL)                 /*!< DSP1N0GPIO95 (Bit 31)                                 */
39090 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO95_Msk (0x80000000UL)         /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
39091 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO94_Pos (30UL)                 /*!< DSP1N0GPIO94 (Bit 30)                                 */
39092 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO94_Msk (0x40000000UL)         /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
39093 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO93_Pos (29UL)                 /*!< DSP1N0GPIO93 (Bit 29)                                 */
39094 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO93_Msk (0x20000000UL)         /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
39095 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO92_Pos (28UL)                 /*!< DSP1N0GPIO92 (Bit 28)                                 */
39096 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO92_Msk (0x10000000UL)         /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
39097 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO91_Pos (27UL)                 /*!< DSP1N0GPIO91 (Bit 27)                                 */
39098 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO91_Msk (0x8000000UL)          /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
39099 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO90_Pos (26UL)                 /*!< DSP1N0GPIO90 (Bit 26)                                 */
39100 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO90_Msk (0x4000000UL)          /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
39101 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO89_Pos (25UL)                 /*!< DSP1N0GPIO89 (Bit 25)                                 */
39102 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO89_Msk (0x2000000UL)          /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
39103 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO88_Pos (24UL)                 /*!< DSP1N0GPIO88 (Bit 24)                                 */
39104 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO88_Msk (0x1000000UL)          /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
39105 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO87_Pos (23UL)                 /*!< DSP1N0GPIO87 (Bit 23)                                 */
39106 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO87_Msk (0x800000UL)           /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
39107 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO86_Pos (22UL)                 /*!< DSP1N0GPIO86 (Bit 22)                                 */
39108 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO86_Msk (0x400000UL)           /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
39109 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO85_Pos (21UL)                 /*!< DSP1N0GPIO85 (Bit 21)                                 */
39110 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO85_Msk (0x200000UL)           /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
39111 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO84_Pos (20UL)                 /*!< DSP1N0GPIO84 (Bit 20)                                 */
39112 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO84_Msk (0x100000UL)           /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
39113 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO83_Pos (19UL)                 /*!< DSP1N0GPIO83 (Bit 19)                                 */
39114 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO83_Msk (0x80000UL)            /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
39115 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO82_Pos (18UL)                 /*!< DSP1N0GPIO82 (Bit 18)                                 */
39116 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO82_Msk (0x40000UL)            /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
39117 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO81_Pos (17UL)                 /*!< DSP1N0GPIO81 (Bit 17)                                 */
39118 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO81_Msk (0x20000UL)            /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
39119 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO80_Pos (16UL)                 /*!< DSP1N0GPIO80 (Bit 16)                                 */
39120 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO80_Msk (0x10000UL)            /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
39121 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO79_Pos (15UL)                 /*!< DSP1N0GPIO79 (Bit 15)                                 */
39122 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO79_Msk (0x8000UL)             /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
39123 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO78_Pos (14UL)                 /*!< DSP1N0GPIO78 (Bit 14)                                 */
39124 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO78_Msk (0x4000UL)             /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
39125 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO77_Pos (13UL)                 /*!< DSP1N0GPIO77 (Bit 13)                                 */
39126 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO77_Msk (0x2000UL)             /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
39127 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO76_Pos (12UL)                 /*!< DSP1N0GPIO76 (Bit 12)                                 */
39128 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO76_Msk (0x1000UL)             /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
39129 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO75_Pos (11UL)                 /*!< DSP1N0GPIO75 (Bit 11)                                 */
39130 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO75_Msk (0x800UL)              /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
39131 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO74_Pos (10UL)                 /*!< DSP1N0GPIO74 (Bit 10)                                 */
39132 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO74_Msk (0x400UL)              /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
39133 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO73_Pos (9UL)                  /*!< DSP1N0GPIO73 (Bit 9)                                  */
39134 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO73_Msk (0x200UL)              /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
39135 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO72_Pos (8UL)                  /*!< DSP1N0GPIO72 (Bit 8)                                  */
39136 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO72_Msk (0x100UL)              /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
39137 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO71_Pos (7UL)                  /*!< DSP1N0GPIO71 (Bit 7)                                  */
39138 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO71_Msk (0x80UL)               /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
39139 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO70_Pos (6UL)                  /*!< DSP1N0GPIO70 (Bit 6)                                  */
39140 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO70_Msk (0x40UL)               /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
39141 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO69_Pos (5UL)                  /*!< DSP1N0GPIO69 (Bit 5)                                  */
39142 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO69_Msk (0x20UL)               /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
39143 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO68_Pos (4UL)                  /*!< DSP1N0GPIO68 (Bit 4)                                  */
39144 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO68_Msk (0x10UL)               /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
39145 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO67_Pos (3UL)                  /*!< DSP1N0GPIO67 (Bit 3)                                  */
39146 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO67_Msk (0x8UL)                /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
39147 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO66_Pos (2UL)                  /*!< DSP1N0GPIO66 (Bit 2)                                  */
39148 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO66_Msk (0x4UL)                /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
39149 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO65_Pos (1UL)                  /*!< DSP1N0GPIO65 (Bit 1)                                  */
39150 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO65_Msk (0x2UL)                /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
39151 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO64_Pos (0UL)                  /*!< DSP1N0GPIO64 (Bit 0)                                  */
39152 #define GPIO_DSP1N0INT2STAT_DSP1N0GPIO64_Msk (0x1UL)                /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
39153 /* =====================================================  DSP1N0INT2CLR  ===================================================== */
39154 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO95_Pos (31UL)                  /*!< DSP1N0GPIO95 (Bit 31)                                 */
39155 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO95_Msk (0x80000000UL)          /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
39156 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO94_Pos (30UL)                  /*!< DSP1N0GPIO94 (Bit 30)                                 */
39157 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO94_Msk (0x40000000UL)          /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
39158 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO93_Pos (29UL)                  /*!< DSP1N0GPIO93 (Bit 29)                                 */
39159 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO93_Msk (0x20000000UL)          /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
39160 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO92_Pos (28UL)                  /*!< DSP1N0GPIO92 (Bit 28)                                 */
39161 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO92_Msk (0x10000000UL)          /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
39162 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO91_Pos (27UL)                  /*!< DSP1N0GPIO91 (Bit 27)                                 */
39163 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO91_Msk (0x8000000UL)           /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
39164 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO90_Pos (26UL)                  /*!< DSP1N0GPIO90 (Bit 26)                                 */
39165 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO90_Msk (0x4000000UL)           /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
39166 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO89_Pos (25UL)                  /*!< DSP1N0GPIO89 (Bit 25)                                 */
39167 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO89_Msk (0x2000000UL)           /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
39168 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO88_Pos (24UL)                  /*!< DSP1N0GPIO88 (Bit 24)                                 */
39169 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO88_Msk (0x1000000UL)           /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
39170 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO87_Pos (23UL)                  /*!< DSP1N0GPIO87 (Bit 23)                                 */
39171 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO87_Msk (0x800000UL)            /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
39172 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO86_Pos (22UL)                  /*!< DSP1N0GPIO86 (Bit 22)                                 */
39173 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO86_Msk (0x400000UL)            /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
39174 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO85_Pos (21UL)                  /*!< DSP1N0GPIO85 (Bit 21)                                 */
39175 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO85_Msk (0x200000UL)            /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
39176 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO84_Pos (20UL)                  /*!< DSP1N0GPIO84 (Bit 20)                                 */
39177 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO84_Msk (0x100000UL)            /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
39178 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO83_Pos (19UL)                  /*!< DSP1N0GPIO83 (Bit 19)                                 */
39179 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO83_Msk (0x80000UL)             /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
39180 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO82_Pos (18UL)                  /*!< DSP1N0GPIO82 (Bit 18)                                 */
39181 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO82_Msk (0x40000UL)             /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
39182 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO81_Pos (17UL)                  /*!< DSP1N0GPIO81 (Bit 17)                                 */
39183 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO81_Msk (0x20000UL)             /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
39184 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO80_Pos (16UL)                  /*!< DSP1N0GPIO80 (Bit 16)                                 */
39185 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO80_Msk (0x10000UL)             /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
39186 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO79_Pos (15UL)                  /*!< DSP1N0GPIO79 (Bit 15)                                 */
39187 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO79_Msk (0x8000UL)              /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
39188 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO78_Pos (14UL)                  /*!< DSP1N0GPIO78 (Bit 14)                                 */
39189 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO78_Msk (0x4000UL)              /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
39190 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO77_Pos (13UL)                  /*!< DSP1N0GPIO77 (Bit 13)                                 */
39191 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO77_Msk (0x2000UL)              /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
39192 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO76_Pos (12UL)                  /*!< DSP1N0GPIO76 (Bit 12)                                 */
39193 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO76_Msk (0x1000UL)              /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
39194 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO75_Pos (11UL)                  /*!< DSP1N0GPIO75 (Bit 11)                                 */
39195 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO75_Msk (0x800UL)               /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
39196 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO74_Pos (10UL)                  /*!< DSP1N0GPIO74 (Bit 10)                                 */
39197 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO74_Msk (0x400UL)               /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
39198 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO73_Pos (9UL)                   /*!< DSP1N0GPIO73 (Bit 9)                                  */
39199 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO73_Msk (0x200UL)               /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
39200 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO72_Pos (8UL)                   /*!< DSP1N0GPIO72 (Bit 8)                                  */
39201 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO72_Msk (0x100UL)               /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
39202 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO71_Pos (7UL)                   /*!< DSP1N0GPIO71 (Bit 7)                                  */
39203 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO71_Msk (0x80UL)                /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
39204 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO70_Pos (6UL)                   /*!< DSP1N0GPIO70 (Bit 6)                                  */
39205 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO70_Msk (0x40UL)                /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
39206 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO69_Pos (5UL)                   /*!< DSP1N0GPIO69 (Bit 5)                                  */
39207 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO69_Msk (0x20UL)                /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
39208 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO68_Pos (4UL)                   /*!< DSP1N0GPIO68 (Bit 4)                                  */
39209 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO68_Msk (0x10UL)                /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
39210 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO67_Pos (3UL)                   /*!< DSP1N0GPIO67 (Bit 3)                                  */
39211 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO67_Msk (0x8UL)                 /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
39212 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO66_Pos (2UL)                   /*!< DSP1N0GPIO66 (Bit 2)                                  */
39213 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO66_Msk (0x4UL)                 /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
39214 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO65_Pos (1UL)                   /*!< DSP1N0GPIO65 (Bit 1)                                  */
39215 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO65_Msk (0x2UL)                 /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
39216 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO64_Pos (0UL)                   /*!< DSP1N0GPIO64 (Bit 0)                                  */
39217 #define GPIO_DSP1N0INT2CLR_DSP1N0GPIO64_Msk (0x1UL)                 /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
39218 /* =====================================================  DSP1N0INT2SET  ===================================================== */
39219 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO95_Pos (31UL)                  /*!< DSP1N0GPIO95 (Bit 31)                                 */
39220 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO95_Msk (0x80000000UL)          /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
39221 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO94_Pos (30UL)                  /*!< DSP1N0GPIO94 (Bit 30)                                 */
39222 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO94_Msk (0x40000000UL)          /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
39223 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO93_Pos (29UL)                  /*!< DSP1N0GPIO93 (Bit 29)                                 */
39224 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO93_Msk (0x20000000UL)          /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
39225 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO92_Pos (28UL)                  /*!< DSP1N0GPIO92 (Bit 28)                                 */
39226 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO92_Msk (0x10000000UL)          /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
39227 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO91_Pos (27UL)                  /*!< DSP1N0GPIO91 (Bit 27)                                 */
39228 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO91_Msk (0x8000000UL)           /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
39229 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO90_Pos (26UL)                  /*!< DSP1N0GPIO90 (Bit 26)                                 */
39230 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO90_Msk (0x4000000UL)           /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
39231 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO89_Pos (25UL)                  /*!< DSP1N0GPIO89 (Bit 25)                                 */
39232 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO89_Msk (0x2000000UL)           /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
39233 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO88_Pos (24UL)                  /*!< DSP1N0GPIO88 (Bit 24)                                 */
39234 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO88_Msk (0x1000000UL)           /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
39235 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO87_Pos (23UL)                  /*!< DSP1N0GPIO87 (Bit 23)                                 */
39236 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO87_Msk (0x800000UL)            /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
39237 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO86_Pos (22UL)                  /*!< DSP1N0GPIO86 (Bit 22)                                 */
39238 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO86_Msk (0x400000UL)            /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
39239 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO85_Pos (21UL)                  /*!< DSP1N0GPIO85 (Bit 21)                                 */
39240 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO85_Msk (0x200000UL)            /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
39241 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO84_Pos (20UL)                  /*!< DSP1N0GPIO84 (Bit 20)                                 */
39242 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO84_Msk (0x100000UL)            /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
39243 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO83_Pos (19UL)                  /*!< DSP1N0GPIO83 (Bit 19)                                 */
39244 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO83_Msk (0x80000UL)             /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
39245 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO82_Pos (18UL)                  /*!< DSP1N0GPIO82 (Bit 18)                                 */
39246 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO82_Msk (0x40000UL)             /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
39247 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO81_Pos (17UL)                  /*!< DSP1N0GPIO81 (Bit 17)                                 */
39248 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO81_Msk (0x20000UL)             /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
39249 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO80_Pos (16UL)                  /*!< DSP1N0GPIO80 (Bit 16)                                 */
39250 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO80_Msk (0x10000UL)             /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
39251 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO79_Pos (15UL)                  /*!< DSP1N0GPIO79 (Bit 15)                                 */
39252 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO79_Msk (0x8000UL)              /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
39253 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO78_Pos (14UL)                  /*!< DSP1N0GPIO78 (Bit 14)                                 */
39254 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO78_Msk (0x4000UL)              /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
39255 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO77_Pos (13UL)                  /*!< DSP1N0GPIO77 (Bit 13)                                 */
39256 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO77_Msk (0x2000UL)              /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
39257 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO76_Pos (12UL)                  /*!< DSP1N0GPIO76 (Bit 12)                                 */
39258 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO76_Msk (0x1000UL)              /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
39259 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO75_Pos (11UL)                  /*!< DSP1N0GPIO75 (Bit 11)                                 */
39260 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO75_Msk (0x800UL)               /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
39261 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO74_Pos (10UL)                  /*!< DSP1N0GPIO74 (Bit 10)                                 */
39262 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO74_Msk (0x400UL)               /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
39263 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO73_Pos (9UL)                   /*!< DSP1N0GPIO73 (Bit 9)                                  */
39264 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO73_Msk (0x200UL)               /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
39265 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO72_Pos (8UL)                   /*!< DSP1N0GPIO72 (Bit 8)                                  */
39266 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO72_Msk (0x100UL)               /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
39267 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO71_Pos (7UL)                   /*!< DSP1N0GPIO71 (Bit 7)                                  */
39268 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO71_Msk (0x80UL)                /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
39269 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO70_Pos (6UL)                   /*!< DSP1N0GPIO70 (Bit 6)                                  */
39270 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO70_Msk (0x40UL)                /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
39271 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO69_Pos (5UL)                   /*!< DSP1N0GPIO69 (Bit 5)                                  */
39272 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO69_Msk (0x20UL)                /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
39273 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO68_Pos (4UL)                   /*!< DSP1N0GPIO68 (Bit 4)                                  */
39274 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO68_Msk (0x10UL)                /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
39275 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO67_Pos (3UL)                   /*!< DSP1N0GPIO67 (Bit 3)                                  */
39276 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO67_Msk (0x8UL)                 /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
39277 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO66_Pos (2UL)                   /*!< DSP1N0GPIO66 (Bit 2)                                  */
39278 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO66_Msk (0x4UL)                 /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
39279 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO65_Pos (1UL)                   /*!< DSP1N0GPIO65 (Bit 1)                                  */
39280 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO65_Msk (0x2UL)                 /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
39281 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO64_Pos (0UL)                   /*!< DSP1N0GPIO64 (Bit 0)                                  */
39282 #define GPIO_DSP1N0INT2SET_DSP1N0GPIO64_Msk (0x1UL)                 /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
39283 /* =====================================================  DSP1N0INT3EN  ====================================================== */
39284 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO127_Pos (31UL)                  /*!< DSP1N0GPIO127 (Bit 31)                                */
39285 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO127_Msk (0x80000000UL)          /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
39286 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO126_Pos (30UL)                  /*!< DSP1N0GPIO126 (Bit 30)                                */
39287 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO126_Msk (0x40000000UL)          /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
39288 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO125_Pos (29UL)                  /*!< DSP1N0GPIO125 (Bit 29)                                */
39289 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO125_Msk (0x20000000UL)          /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
39290 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO124_Pos (28UL)                  /*!< DSP1N0GPIO124 (Bit 28)                                */
39291 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO124_Msk (0x10000000UL)          /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
39292 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO123_Pos (27UL)                  /*!< DSP1N0GPIO123 (Bit 27)                                */
39293 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO123_Msk (0x8000000UL)           /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
39294 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO122_Pos (26UL)                  /*!< DSP1N0GPIO122 (Bit 26)                                */
39295 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO122_Msk (0x4000000UL)           /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
39296 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO121_Pos (25UL)                  /*!< DSP1N0GPIO121 (Bit 25)                                */
39297 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO121_Msk (0x2000000UL)           /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
39298 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO120_Pos (24UL)                  /*!< DSP1N0GPIO120 (Bit 24)                                */
39299 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO120_Msk (0x1000000UL)           /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
39300 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO119_Pos (23UL)                  /*!< DSP1N0GPIO119 (Bit 23)                                */
39301 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO119_Msk (0x800000UL)            /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
39302 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO118_Pos (22UL)                  /*!< DSP1N0GPIO118 (Bit 22)                                */
39303 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO118_Msk (0x400000UL)            /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
39304 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO117_Pos (21UL)                  /*!< DSP1N0GPIO117 (Bit 21)                                */
39305 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO117_Msk (0x200000UL)            /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
39306 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO116_Pos (20UL)                  /*!< DSP1N0GPIO116 (Bit 20)                                */
39307 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO116_Msk (0x100000UL)            /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
39308 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO115_Pos (19UL)                  /*!< DSP1N0GPIO115 (Bit 19)                                */
39309 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO115_Msk (0x80000UL)             /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
39310 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO114_Pos (18UL)                  /*!< DSP1N0GPIO114 (Bit 18)                                */
39311 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO114_Msk (0x40000UL)             /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
39312 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO113_Pos (17UL)                  /*!< DSP1N0GPIO113 (Bit 17)                                */
39313 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO113_Msk (0x20000UL)             /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
39314 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO112_Pos (16UL)                  /*!< DSP1N0GPIO112 (Bit 16)                                */
39315 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO112_Msk (0x10000UL)             /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
39316 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO111_Pos (15UL)                  /*!< DSP1N0GPIO111 (Bit 15)                                */
39317 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO111_Msk (0x8000UL)              /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
39318 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO110_Pos (14UL)                  /*!< DSP1N0GPIO110 (Bit 14)                                */
39319 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO110_Msk (0x4000UL)              /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
39320 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO109_Pos (13UL)                  /*!< DSP1N0GPIO109 (Bit 13)                                */
39321 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO109_Msk (0x2000UL)              /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
39322 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO108_Pos (12UL)                  /*!< DSP1N0GPIO108 (Bit 12)                                */
39323 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO108_Msk (0x1000UL)              /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
39324 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO107_Pos (11UL)                  /*!< DSP1N0GPIO107 (Bit 11)                                */
39325 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO107_Msk (0x800UL)               /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
39326 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO106_Pos (10UL)                  /*!< DSP1N0GPIO106 (Bit 10)                                */
39327 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO106_Msk (0x400UL)               /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
39328 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO105_Pos (9UL)                   /*!< DSP1N0GPIO105 (Bit 9)                                 */
39329 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO105_Msk (0x200UL)               /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
39330 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO104_Pos (8UL)                   /*!< DSP1N0GPIO104 (Bit 8)                                 */
39331 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO104_Msk (0x100UL)               /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
39332 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO103_Pos (7UL)                   /*!< DSP1N0GPIO103 (Bit 7)                                 */
39333 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO103_Msk (0x80UL)                /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
39334 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO102_Pos (6UL)                   /*!< DSP1N0GPIO102 (Bit 6)                                 */
39335 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO102_Msk (0x40UL)                /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
39336 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO101_Pos (5UL)                   /*!< DSP1N0GPIO101 (Bit 5)                                 */
39337 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO101_Msk (0x20UL)                /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
39338 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO100_Pos (4UL)                   /*!< DSP1N0GPIO100 (Bit 4)                                 */
39339 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO100_Msk (0x10UL)                /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
39340 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO99_Pos (3UL)                    /*!< DSP1N0GPIO99 (Bit 3)                                  */
39341 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO99_Msk (0x8UL)                  /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
39342 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO98_Pos (2UL)                    /*!< DSP1N0GPIO98 (Bit 2)                                  */
39343 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO98_Msk (0x4UL)                  /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
39344 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO97_Pos (1UL)                    /*!< DSP1N0GPIO97 (Bit 1)                                  */
39345 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO97_Msk (0x2UL)                  /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
39346 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO96_Pos (0UL)                    /*!< DSP1N0GPIO96 (Bit 0)                                  */
39347 #define GPIO_DSP1N0INT3EN_DSP1N0GPIO96_Msk (0x1UL)                  /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
39348 /* ====================================================  DSP1N0INT3STAT  ===================================================== */
39349 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO127_Pos (31UL)                /*!< DSP1N0GPIO127 (Bit 31)                                */
39350 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO127_Msk (0x80000000UL)        /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
39351 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO126_Pos (30UL)                /*!< DSP1N0GPIO126 (Bit 30)                                */
39352 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO126_Msk (0x40000000UL)        /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
39353 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO125_Pos (29UL)                /*!< DSP1N0GPIO125 (Bit 29)                                */
39354 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO125_Msk (0x20000000UL)        /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
39355 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO124_Pos (28UL)                /*!< DSP1N0GPIO124 (Bit 28)                                */
39356 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO124_Msk (0x10000000UL)        /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
39357 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO123_Pos (27UL)                /*!< DSP1N0GPIO123 (Bit 27)                                */
39358 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO123_Msk (0x8000000UL)         /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
39359 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO122_Pos (26UL)                /*!< DSP1N0GPIO122 (Bit 26)                                */
39360 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO122_Msk (0x4000000UL)         /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
39361 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO121_Pos (25UL)                /*!< DSP1N0GPIO121 (Bit 25)                                */
39362 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO121_Msk (0x2000000UL)         /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
39363 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO120_Pos (24UL)                /*!< DSP1N0GPIO120 (Bit 24)                                */
39364 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO120_Msk (0x1000000UL)         /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
39365 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO119_Pos (23UL)                /*!< DSP1N0GPIO119 (Bit 23)                                */
39366 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO119_Msk (0x800000UL)          /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
39367 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO118_Pos (22UL)                /*!< DSP1N0GPIO118 (Bit 22)                                */
39368 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO118_Msk (0x400000UL)          /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
39369 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO117_Pos (21UL)                /*!< DSP1N0GPIO117 (Bit 21)                                */
39370 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO117_Msk (0x200000UL)          /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
39371 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO116_Pos (20UL)                /*!< DSP1N0GPIO116 (Bit 20)                                */
39372 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO116_Msk (0x100000UL)          /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
39373 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO115_Pos (19UL)                /*!< DSP1N0GPIO115 (Bit 19)                                */
39374 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO115_Msk (0x80000UL)           /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
39375 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO114_Pos (18UL)                /*!< DSP1N0GPIO114 (Bit 18)                                */
39376 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO114_Msk (0x40000UL)           /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
39377 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO113_Pos (17UL)                /*!< DSP1N0GPIO113 (Bit 17)                                */
39378 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO113_Msk (0x20000UL)           /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
39379 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO112_Pos (16UL)                /*!< DSP1N0GPIO112 (Bit 16)                                */
39380 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO112_Msk (0x10000UL)           /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
39381 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO111_Pos (15UL)                /*!< DSP1N0GPIO111 (Bit 15)                                */
39382 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO111_Msk (0x8000UL)            /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
39383 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO110_Pos (14UL)                /*!< DSP1N0GPIO110 (Bit 14)                                */
39384 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO110_Msk (0x4000UL)            /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
39385 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO109_Pos (13UL)                /*!< DSP1N0GPIO109 (Bit 13)                                */
39386 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO109_Msk (0x2000UL)            /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
39387 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO108_Pos (12UL)                /*!< DSP1N0GPIO108 (Bit 12)                                */
39388 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO108_Msk (0x1000UL)            /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
39389 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO107_Pos (11UL)                /*!< DSP1N0GPIO107 (Bit 11)                                */
39390 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO107_Msk (0x800UL)             /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
39391 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO106_Pos (10UL)                /*!< DSP1N0GPIO106 (Bit 10)                                */
39392 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO106_Msk (0x400UL)             /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
39393 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO105_Pos (9UL)                 /*!< DSP1N0GPIO105 (Bit 9)                                 */
39394 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO105_Msk (0x200UL)             /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
39395 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO104_Pos (8UL)                 /*!< DSP1N0GPIO104 (Bit 8)                                 */
39396 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO104_Msk (0x100UL)             /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
39397 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO103_Pos (7UL)                 /*!< DSP1N0GPIO103 (Bit 7)                                 */
39398 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO103_Msk (0x80UL)              /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
39399 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO102_Pos (6UL)                 /*!< DSP1N0GPIO102 (Bit 6)                                 */
39400 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO102_Msk (0x40UL)              /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
39401 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO101_Pos (5UL)                 /*!< DSP1N0GPIO101 (Bit 5)                                 */
39402 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO101_Msk (0x20UL)              /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
39403 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO100_Pos (4UL)                 /*!< DSP1N0GPIO100 (Bit 4)                                 */
39404 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO100_Msk (0x10UL)              /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
39405 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO99_Pos (3UL)                  /*!< DSP1N0GPIO99 (Bit 3)                                  */
39406 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO99_Msk (0x8UL)                /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
39407 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO98_Pos (2UL)                  /*!< DSP1N0GPIO98 (Bit 2)                                  */
39408 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO98_Msk (0x4UL)                /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
39409 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO97_Pos (1UL)                  /*!< DSP1N0GPIO97 (Bit 1)                                  */
39410 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO97_Msk (0x2UL)                /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
39411 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO96_Pos (0UL)                  /*!< DSP1N0GPIO96 (Bit 0)                                  */
39412 #define GPIO_DSP1N0INT3STAT_DSP1N0GPIO96_Msk (0x1UL)                /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
39413 /* =====================================================  DSP1N0INT3CLR  ===================================================== */
39414 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO127_Pos (31UL)                 /*!< DSP1N0GPIO127 (Bit 31)                                */
39415 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO127_Msk (0x80000000UL)         /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
39416 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO126_Pos (30UL)                 /*!< DSP1N0GPIO126 (Bit 30)                                */
39417 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO126_Msk (0x40000000UL)         /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
39418 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO125_Pos (29UL)                 /*!< DSP1N0GPIO125 (Bit 29)                                */
39419 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO125_Msk (0x20000000UL)         /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
39420 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO124_Pos (28UL)                 /*!< DSP1N0GPIO124 (Bit 28)                                */
39421 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO124_Msk (0x10000000UL)         /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
39422 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO123_Pos (27UL)                 /*!< DSP1N0GPIO123 (Bit 27)                                */
39423 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO123_Msk (0x8000000UL)          /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
39424 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO122_Pos (26UL)                 /*!< DSP1N0GPIO122 (Bit 26)                                */
39425 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO122_Msk (0x4000000UL)          /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
39426 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO121_Pos (25UL)                 /*!< DSP1N0GPIO121 (Bit 25)                                */
39427 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO121_Msk (0x2000000UL)          /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
39428 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO120_Pos (24UL)                 /*!< DSP1N0GPIO120 (Bit 24)                                */
39429 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO120_Msk (0x1000000UL)          /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
39430 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO119_Pos (23UL)                 /*!< DSP1N0GPIO119 (Bit 23)                                */
39431 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO119_Msk (0x800000UL)           /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
39432 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO118_Pos (22UL)                 /*!< DSP1N0GPIO118 (Bit 22)                                */
39433 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO118_Msk (0x400000UL)           /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
39434 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO117_Pos (21UL)                 /*!< DSP1N0GPIO117 (Bit 21)                                */
39435 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO117_Msk (0x200000UL)           /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
39436 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO116_Pos (20UL)                 /*!< DSP1N0GPIO116 (Bit 20)                                */
39437 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO116_Msk (0x100000UL)           /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
39438 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO115_Pos (19UL)                 /*!< DSP1N0GPIO115 (Bit 19)                                */
39439 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO115_Msk (0x80000UL)            /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
39440 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO114_Pos (18UL)                 /*!< DSP1N0GPIO114 (Bit 18)                                */
39441 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO114_Msk (0x40000UL)            /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
39442 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO113_Pos (17UL)                 /*!< DSP1N0GPIO113 (Bit 17)                                */
39443 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO113_Msk (0x20000UL)            /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
39444 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO112_Pos (16UL)                 /*!< DSP1N0GPIO112 (Bit 16)                                */
39445 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO112_Msk (0x10000UL)            /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
39446 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO111_Pos (15UL)                 /*!< DSP1N0GPIO111 (Bit 15)                                */
39447 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO111_Msk (0x8000UL)             /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
39448 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO110_Pos (14UL)                 /*!< DSP1N0GPIO110 (Bit 14)                                */
39449 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO110_Msk (0x4000UL)             /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
39450 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO109_Pos (13UL)                 /*!< DSP1N0GPIO109 (Bit 13)                                */
39451 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO109_Msk (0x2000UL)             /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
39452 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO108_Pos (12UL)                 /*!< DSP1N0GPIO108 (Bit 12)                                */
39453 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO108_Msk (0x1000UL)             /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
39454 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO107_Pos (11UL)                 /*!< DSP1N0GPIO107 (Bit 11)                                */
39455 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO107_Msk (0x800UL)              /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
39456 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO106_Pos (10UL)                 /*!< DSP1N0GPIO106 (Bit 10)                                */
39457 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO106_Msk (0x400UL)              /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
39458 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO105_Pos (9UL)                  /*!< DSP1N0GPIO105 (Bit 9)                                 */
39459 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO105_Msk (0x200UL)              /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
39460 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO104_Pos (8UL)                  /*!< DSP1N0GPIO104 (Bit 8)                                 */
39461 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO104_Msk (0x100UL)              /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
39462 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO103_Pos (7UL)                  /*!< DSP1N0GPIO103 (Bit 7)                                 */
39463 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO103_Msk (0x80UL)               /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
39464 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO102_Pos (6UL)                  /*!< DSP1N0GPIO102 (Bit 6)                                 */
39465 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO102_Msk (0x40UL)               /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
39466 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO101_Pos (5UL)                  /*!< DSP1N0GPIO101 (Bit 5)                                 */
39467 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO101_Msk (0x20UL)               /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
39468 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO100_Pos (4UL)                  /*!< DSP1N0GPIO100 (Bit 4)                                 */
39469 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO100_Msk (0x10UL)               /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
39470 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO99_Pos (3UL)                   /*!< DSP1N0GPIO99 (Bit 3)                                  */
39471 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO99_Msk (0x8UL)                 /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
39472 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO98_Pos (2UL)                   /*!< DSP1N0GPIO98 (Bit 2)                                  */
39473 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO98_Msk (0x4UL)                 /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
39474 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO97_Pos (1UL)                   /*!< DSP1N0GPIO97 (Bit 1)                                  */
39475 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO97_Msk (0x2UL)                 /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
39476 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO96_Pos (0UL)                   /*!< DSP1N0GPIO96 (Bit 0)                                  */
39477 #define GPIO_DSP1N0INT3CLR_DSP1N0GPIO96_Msk (0x1UL)                 /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
39478 /* =====================================================  DSP1N0INT3SET  ===================================================== */
39479 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO127_Pos (31UL)                 /*!< DSP1N0GPIO127 (Bit 31)                                */
39480 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO127_Msk (0x80000000UL)         /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
39481 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO126_Pos (30UL)                 /*!< DSP1N0GPIO126 (Bit 30)                                */
39482 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO126_Msk (0x40000000UL)         /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
39483 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO125_Pos (29UL)                 /*!< DSP1N0GPIO125 (Bit 29)                                */
39484 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO125_Msk (0x20000000UL)         /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
39485 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO124_Pos (28UL)                 /*!< DSP1N0GPIO124 (Bit 28)                                */
39486 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO124_Msk (0x10000000UL)         /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
39487 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO123_Pos (27UL)                 /*!< DSP1N0GPIO123 (Bit 27)                                */
39488 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO123_Msk (0x8000000UL)          /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
39489 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO122_Pos (26UL)                 /*!< DSP1N0GPIO122 (Bit 26)                                */
39490 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO122_Msk (0x4000000UL)          /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
39491 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO121_Pos (25UL)                 /*!< DSP1N0GPIO121 (Bit 25)                                */
39492 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO121_Msk (0x2000000UL)          /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
39493 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO120_Pos (24UL)                 /*!< DSP1N0GPIO120 (Bit 24)                                */
39494 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO120_Msk (0x1000000UL)          /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
39495 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO119_Pos (23UL)                 /*!< DSP1N0GPIO119 (Bit 23)                                */
39496 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO119_Msk (0x800000UL)           /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
39497 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO118_Pos (22UL)                 /*!< DSP1N0GPIO118 (Bit 22)                                */
39498 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO118_Msk (0x400000UL)           /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
39499 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO117_Pos (21UL)                 /*!< DSP1N0GPIO117 (Bit 21)                                */
39500 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO117_Msk (0x200000UL)           /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
39501 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO116_Pos (20UL)                 /*!< DSP1N0GPIO116 (Bit 20)                                */
39502 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO116_Msk (0x100000UL)           /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
39503 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO115_Pos (19UL)                 /*!< DSP1N0GPIO115 (Bit 19)                                */
39504 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO115_Msk (0x80000UL)            /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
39505 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO114_Pos (18UL)                 /*!< DSP1N0GPIO114 (Bit 18)                                */
39506 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO114_Msk (0x40000UL)            /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
39507 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO113_Pos (17UL)                 /*!< DSP1N0GPIO113 (Bit 17)                                */
39508 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO113_Msk (0x20000UL)            /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
39509 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO112_Pos (16UL)                 /*!< DSP1N0GPIO112 (Bit 16)                                */
39510 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO112_Msk (0x10000UL)            /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
39511 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO111_Pos (15UL)                 /*!< DSP1N0GPIO111 (Bit 15)                                */
39512 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO111_Msk (0x8000UL)             /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
39513 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO110_Pos (14UL)                 /*!< DSP1N0GPIO110 (Bit 14)                                */
39514 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO110_Msk (0x4000UL)             /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
39515 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO109_Pos (13UL)                 /*!< DSP1N0GPIO109 (Bit 13)                                */
39516 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO109_Msk (0x2000UL)             /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
39517 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO108_Pos (12UL)                 /*!< DSP1N0GPIO108 (Bit 12)                                */
39518 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO108_Msk (0x1000UL)             /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
39519 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO107_Pos (11UL)                 /*!< DSP1N0GPIO107 (Bit 11)                                */
39520 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO107_Msk (0x800UL)              /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
39521 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO106_Pos (10UL)                 /*!< DSP1N0GPIO106 (Bit 10)                                */
39522 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO106_Msk (0x400UL)              /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
39523 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO105_Pos (9UL)                  /*!< DSP1N0GPIO105 (Bit 9)                                 */
39524 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO105_Msk (0x200UL)              /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
39525 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO104_Pos (8UL)                  /*!< DSP1N0GPIO104 (Bit 8)                                 */
39526 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO104_Msk (0x100UL)              /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
39527 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO103_Pos (7UL)                  /*!< DSP1N0GPIO103 (Bit 7)                                 */
39528 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO103_Msk (0x80UL)               /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
39529 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO102_Pos (6UL)                  /*!< DSP1N0GPIO102 (Bit 6)                                 */
39530 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO102_Msk (0x40UL)               /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
39531 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO101_Pos (5UL)                  /*!< DSP1N0GPIO101 (Bit 5)                                 */
39532 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO101_Msk (0x20UL)               /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
39533 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO100_Pos (4UL)                  /*!< DSP1N0GPIO100 (Bit 4)                                 */
39534 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO100_Msk (0x10UL)               /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
39535 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO99_Pos (3UL)                   /*!< DSP1N0GPIO99 (Bit 3)                                  */
39536 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO99_Msk (0x8UL)                 /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
39537 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO98_Pos (2UL)                   /*!< DSP1N0GPIO98 (Bit 2)                                  */
39538 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO98_Msk (0x4UL)                 /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
39539 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO97_Pos (1UL)                   /*!< DSP1N0GPIO97 (Bit 1)                                  */
39540 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO97_Msk (0x2UL)                 /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
39541 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO96_Pos (0UL)                   /*!< DSP1N0GPIO96 (Bit 0)                                  */
39542 #define GPIO_DSP1N0INT3SET_DSP1N0GPIO96_Msk (0x1UL)                 /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
39543 /* =====================================================  DSP1N1INT0EN  ====================================================== */
39544 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO31_Pos (31UL)                   /*!< DSP1N1GPIO31 (Bit 31)                                 */
39545 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO31_Msk (0x80000000UL)           /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
39546 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO30_Pos (30UL)                   /*!< DSP1N1GPIO30 (Bit 30)                                 */
39547 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO30_Msk (0x40000000UL)           /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
39548 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO29_Pos (29UL)                   /*!< DSP1N1GPIO29 (Bit 29)                                 */
39549 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO29_Msk (0x20000000UL)           /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
39550 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO28_Pos (28UL)                   /*!< DSP1N1GPIO28 (Bit 28)                                 */
39551 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO28_Msk (0x10000000UL)           /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
39552 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO27_Pos (27UL)                   /*!< DSP1N1GPIO27 (Bit 27)                                 */
39553 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO27_Msk (0x8000000UL)            /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
39554 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO26_Pos (26UL)                   /*!< DSP1N1GPIO26 (Bit 26)                                 */
39555 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO26_Msk (0x4000000UL)            /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
39556 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO25_Pos (25UL)                   /*!< DSP1N1GPIO25 (Bit 25)                                 */
39557 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO25_Msk (0x2000000UL)            /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
39558 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO24_Pos (24UL)                   /*!< DSP1N1GPIO24 (Bit 24)                                 */
39559 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO24_Msk (0x1000000UL)            /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
39560 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO23_Pos (23UL)                   /*!< DSP1N1GPIO23 (Bit 23)                                 */
39561 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO23_Msk (0x800000UL)             /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
39562 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO22_Pos (22UL)                   /*!< DSP1N1GPIO22 (Bit 22)                                 */
39563 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO22_Msk (0x400000UL)             /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
39564 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO21_Pos (21UL)                   /*!< DSP1N1GPIO21 (Bit 21)                                 */
39565 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO21_Msk (0x200000UL)             /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
39566 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO20_Pos (20UL)                   /*!< DSP1N1GPIO20 (Bit 20)                                 */
39567 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO20_Msk (0x100000UL)             /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
39568 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO19_Pos (19UL)                   /*!< DSP1N1GPIO19 (Bit 19)                                 */
39569 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO19_Msk (0x80000UL)              /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
39570 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO18_Pos (18UL)                   /*!< DSP1N1GPIO18 (Bit 18)                                 */
39571 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO18_Msk (0x40000UL)              /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
39572 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO17_Pos (17UL)                   /*!< DSP1N1GPIO17 (Bit 17)                                 */
39573 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO17_Msk (0x20000UL)              /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
39574 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO16_Pos (16UL)                   /*!< DSP1N1GPIO16 (Bit 16)                                 */
39575 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO16_Msk (0x10000UL)              /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
39576 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO15_Pos (15UL)                   /*!< DSP1N1GPIO15 (Bit 15)                                 */
39577 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO15_Msk (0x8000UL)               /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
39578 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO14_Pos (14UL)                   /*!< DSP1N1GPIO14 (Bit 14)                                 */
39579 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO14_Msk (0x4000UL)               /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
39580 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO13_Pos (13UL)                   /*!< DSP1N1GPIO13 (Bit 13)                                 */
39581 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO13_Msk (0x2000UL)               /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
39582 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO12_Pos (12UL)                   /*!< DSP1N1GPIO12 (Bit 12)                                 */
39583 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO12_Msk (0x1000UL)               /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
39584 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO11_Pos (11UL)                   /*!< DSP1N1GPIO11 (Bit 11)                                 */
39585 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO11_Msk (0x800UL)                /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
39586 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO10_Pos (10UL)                   /*!< DSP1N1GPIO10 (Bit 10)                                 */
39587 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO10_Msk (0x400UL)                /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
39588 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO9_Pos (9UL)                     /*!< DSP1N1GPIO9 (Bit 9)                                   */
39589 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO9_Msk (0x200UL)                 /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
39590 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO8_Pos (8UL)                     /*!< DSP1N1GPIO8 (Bit 8)                                   */
39591 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO8_Msk (0x100UL)                 /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
39592 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO7_Pos (7UL)                     /*!< DSP1N1GPIO7 (Bit 7)                                   */
39593 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO7_Msk (0x80UL)                  /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
39594 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO6_Pos (6UL)                     /*!< DSP1N1GPIO6 (Bit 6)                                   */
39595 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO6_Msk (0x40UL)                  /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
39596 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO5_Pos (5UL)                     /*!< DSP1N1GPIO5 (Bit 5)                                   */
39597 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO5_Msk (0x20UL)                  /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
39598 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO4_Pos (4UL)                     /*!< DSP1N1GPIO4 (Bit 4)                                   */
39599 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO4_Msk (0x10UL)                  /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
39600 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO3_Pos (3UL)                     /*!< DSP1N1GPIO3 (Bit 3)                                   */
39601 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO3_Msk (0x8UL)                   /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
39602 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO2_Pos (2UL)                     /*!< DSP1N1GPIO2 (Bit 2)                                   */
39603 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO2_Msk (0x4UL)                   /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
39604 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO1_Pos (1UL)                     /*!< DSP1N1GPIO1 (Bit 1)                                   */
39605 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO1_Msk (0x2UL)                   /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
39606 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO0_Pos (0UL)                     /*!< DSP1N1GPIO0 (Bit 0)                                   */
39607 #define GPIO_DSP1N1INT0EN_DSP1N1GPIO0_Msk (0x1UL)                   /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
39608 /* ====================================================  DSP1N1INT0STAT  ===================================================== */
39609 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO31_Pos (31UL)                 /*!< DSP1N1GPIO31 (Bit 31)                                 */
39610 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO31_Msk (0x80000000UL)         /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
39611 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO30_Pos (30UL)                 /*!< DSP1N1GPIO30 (Bit 30)                                 */
39612 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO30_Msk (0x40000000UL)         /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
39613 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO29_Pos (29UL)                 /*!< DSP1N1GPIO29 (Bit 29)                                 */
39614 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO29_Msk (0x20000000UL)         /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
39615 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO28_Pos (28UL)                 /*!< DSP1N1GPIO28 (Bit 28)                                 */
39616 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO28_Msk (0x10000000UL)         /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
39617 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO27_Pos (27UL)                 /*!< DSP1N1GPIO27 (Bit 27)                                 */
39618 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO27_Msk (0x8000000UL)          /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
39619 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO26_Pos (26UL)                 /*!< DSP1N1GPIO26 (Bit 26)                                 */
39620 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO26_Msk (0x4000000UL)          /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
39621 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO25_Pos (25UL)                 /*!< DSP1N1GPIO25 (Bit 25)                                 */
39622 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO25_Msk (0x2000000UL)          /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
39623 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO24_Pos (24UL)                 /*!< DSP1N1GPIO24 (Bit 24)                                 */
39624 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO24_Msk (0x1000000UL)          /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
39625 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO23_Pos (23UL)                 /*!< DSP1N1GPIO23 (Bit 23)                                 */
39626 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO23_Msk (0x800000UL)           /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
39627 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO22_Pos (22UL)                 /*!< DSP1N1GPIO22 (Bit 22)                                 */
39628 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO22_Msk (0x400000UL)           /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
39629 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO21_Pos (21UL)                 /*!< DSP1N1GPIO21 (Bit 21)                                 */
39630 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO21_Msk (0x200000UL)           /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
39631 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO20_Pos (20UL)                 /*!< DSP1N1GPIO20 (Bit 20)                                 */
39632 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO20_Msk (0x100000UL)           /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
39633 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO19_Pos (19UL)                 /*!< DSP1N1GPIO19 (Bit 19)                                 */
39634 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO19_Msk (0x80000UL)            /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
39635 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO18_Pos (18UL)                 /*!< DSP1N1GPIO18 (Bit 18)                                 */
39636 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO18_Msk (0x40000UL)            /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
39637 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO17_Pos (17UL)                 /*!< DSP1N1GPIO17 (Bit 17)                                 */
39638 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO17_Msk (0x20000UL)            /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
39639 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO16_Pos (16UL)                 /*!< DSP1N1GPIO16 (Bit 16)                                 */
39640 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO16_Msk (0x10000UL)            /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
39641 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO15_Pos (15UL)                 /*!< DSP1N1GPIO15 (Bit 15)                                 */
39642 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO15_Msk (0x8000UL)             /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
39643 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO14_Pos (14UL)                 /*!< DSP1N1GPIO14 (Bit 14)                                 */
39644 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO14_Msk (0x4000UL)             /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
39645 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO13_Pos (13UL)                 /*!< DSP1N1GPIO13 (Bit 13)                                 */
39646 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO13_Msk (0x2000UL)             /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
39647 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO12_Pos (12UL)                 /*!< DSP1N1GPIO12 (Bit 12)                                 */
39648 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO12_Msk (0x1000UL)             /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
39649 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO11_Pos (11UL)                 /*!< DSP1N1GPIO11 (Bit 11)                                 */
39650 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO11_Msk (0x800UL)              /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
39651 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO10_Pos (10UL)                 /*!< DSP1N1GPIO10 (Bit 10)                                 */
39652 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO10_Msk (0x400UL)              /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
39653 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO9_Pos (9UL)                   /*!< DSP1N1GPIO9 (Bit 9)                                   */
39654 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO9_Msk (0x200UL)               /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
39655 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO8_Pos (8UL)                   /*!< DSP1N1GPIO8 (Bit 8)                                   */
39656 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO8_Msk (0x100UL)               /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
39657 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO7_Pos (7UL)                   /*!< DSP1N1GPIO7 (Bit 7)                                   */
39658 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO7_Msk (0x80UL)                /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
39659 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO6_Pos (6UL)                   /*!< DSP1N1GPIO6 (Bit 6)                                   */
39660 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO6_Msk (0x40UL)                /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
39661 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO5_Pos (5UL)                   /*!< DSP1N1GPIO5 (Bit 5)                                   */
39662 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO5_Msk (0x20UL)                /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
39663 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO4_Pos (4UL)                   /*!< DSP1N1GPIO4 (Bit 4)                                   */
39664 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO4_Msk (0x10UL)                /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
39665 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO3_Pos (3UL)                   /*!< DSP1N1GPIO3 (Bit 3)                                   */
39666 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO3_Msk (0x8UL)                 /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
39667 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO2_Pos (2UL)                   /*!< DSP1N1GPIO2 (Bit 2)                                   */
39668 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO2_Msk (0x4UL)                 /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
39669 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO1_Pos (1UL)                   /*!< DSP1N1GPIO1 (Bit 1)                                   */
39670 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO1_Msk (0x2UL)                 /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
39671 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO0_Pos (0UL)                   /*!< DSP1N1GPIO0 (Bit 0)                                   */
39672 #define GPIO_DSP1N1INT0STAT_DSP1N1GPIO0_Msk (0x1UL)                 /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
39673 /* =====================================================  DSP1N1INT0CLR  ===================================================== */
39674 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO31_Pos (31UL)                  /*!< DSP1N1GPIO31 (Bit 31)                                 */
39675 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO31_Msk (0x80000000UL)          /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
39676 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO30_Pos (30UL)                  /*!< DSP1N1GPIO30 (Bit 30)                                 */
39677 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO30_Msk (0x40000000UL)          /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
39678 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO29_Pos (29UL)                  /*!< DSP1N1GPIO29 (Bit 29)                                 */
39679 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO29_Msk (0x20000000UL)          /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
39680 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO28_Pos (28UL)                  /*!< DSP1N1GPIO28 (Bit 28)                                 */
39681 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO28_Msk (0x10000000UL)          /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
39682 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO27_Pos (27UL)                  /*!< DSP1N1GPIO27 (Bit 27)                                 */
39683 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO27_Msk (0x8000000UL)           /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
39684 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO26_Pos (26UL)                  /*!< DSP1N1GPIO26 (Bit 26)                                 */
39685 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO26_Msk (0x4000000UL)           /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
39686 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO25_Pos (25UL)                  /*!< DSP1N1GPIO25 (Bit 25)                                 */
39687 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO25_Msk (0x2000000UL)           /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
39688 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO24_Pos (24UL)                  /*!< DSP1N1GPIO24 (Bit 24)                                 */
39689 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO24_Msk (0x1000000UL)           /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
39690 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO23_Pos (23UL)                  /*!< DSP1N1GPIO23 (Bit 23)                                 */
39691 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO23_Msk (0x800000UL)            /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
39692 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO22_Pos (22UL)                  /*!< DSP1N1GPIO22 (Bit 22)                                 */
39693 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO22_Msk (0x400000UL)            /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
39694 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO21_Pos (21UL)                  /*!< DSP1N1GPIO21 (Bit 21)                                 */
39695 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO21_Msk (0x200000UL)            /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
39696 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO20_Pos (20UL)                  /*!< DSP1N1GPIO20 (Bit 20)                                 */
39697 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO20_Msk (0x100000UL)            /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
39698 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO19_Pos (19UL)                  /*!< DSP1N1GPIO19 (Bit 19)                                 */
39699 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO19_Msk (0x80000UL)             /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
39700 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO18_Pos (18UL)                  /*!< DSP1N1GPIO18 (Bit 18)                                 */
39701 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO18_Msk (0x40000UL)             /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
39702 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO17_Pos (17UL)                  /*!< DSP1N1GPIO17 (Bit 17)                                 */
39703 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO17_Msk (0x20000UL)             /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
39704 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO16_Pos (16UL)                  /*!< DSP1N1GPIO16 (Bit 16)                                 */
39705 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO16_Msk (0x10000UL)             /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
39706 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO15_Pos (15UL)                  /*!< DSP1N1GPIO15 (Bit 15)                                 */
39707 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO15_Msk (0x8000UL)              /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
39708 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO14_Pos (14UL)                  /*!< DSP1N1GPIO14 (Bit 14)                                 */
39709 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO14_Msk (0x4000UL)              /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
39710 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO13_Pos (13UL)                  /*!< DSP1N1GPIO13 (Bit 13)                                 */
39711 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO13_Msk (0x2000UL)              /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
39712 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO12_Pos (12UL)                  /*!< DSP1N1GPIO12 (Bit 12)                                 */
39713 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO12_Msk (0x1000UL)              /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
39714 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO11_Pos (11UL)                  /*!< DSP1N1GPIO11 (Bit 11)                                 */
39715 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO11_Msk (0x800UL)               /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
39716 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO10_Pos (10UL)                  /*!< DSP1N1GPIO10 (Bit 10)                                 */
39717 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO10_Msk (0x400UL)               /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
39718 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO9_Pos (9UL)                    /*!< DSP1N1GPIO9 (Bit 9)                                   */
39719 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO9_Msk (0x200UL)                /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
39720 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO8_Pos (8UL)                    /*!< DSP1N1GPIO8 (Bit 8)                                   */
39721 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO8_Msk (0x100UL)                /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
39722 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO7_Pos (7UL)                    /*!< DSP1N1GPIO7 (Bit 7)                                   */
39723 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO7_Msk (0x80UL)                 /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
39724 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO6_Pos (6UL)                    /*!< DSP1N1GPIO6 (Bit 6)                                   */
39725 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO6_Msk (0x40UL)                 /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
39726 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO5_Pos (5UL)                    /*!< DSP1N1GPIO5 (Bit 5)                                   */
39727 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO5_Msk (0x20UL)                 /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
39728 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO4_Pos (4UL)                    /*!< DSP1N1GPIO4 (Bit 4)                                   */
39729 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO4_Msk (0x10UL)                 /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
39730 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO3_Pos (3UL)                    /*!< DSP1N1GPIO3 (Bit 3)                                   */
39731 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO3_Msk (0x8UL)                  /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
39732 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO2_Pos (2UL)                    /*!< DSP1N1GPIO2 (Bit 2)                                   */
39733 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO2_Msk (0x4UL)                  /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
39734 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO1_Pos (1UL)                    /*!< DSP1N1GPIO1 (Bit 1)                                   */
39735 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO1_Msk (0x2UL)                  /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
39736 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO0_Pos (0UL)                    /*!< DSP1N1GPIO0 (Bit 0)                                   */
39737 #define GPIO_DSP1N1INT0CLR_DSP1N1GPIO0_Msk (0x1UL)                  /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
39738 /* =====================================================  DSP1N1INT0SET  ===================================================== */
39739 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO31_Pos (31UL)                  /*!< DSP1N1GPIO31 (Bit 31)                                 */
39740 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO31_Msk (0x80000000UL)          /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
39741 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO30_Pos (30UL)                  /*!< DSP1N1GPIO30 (Bit 30)                                 */
39742 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO30_Msk (0x40000000UL)          /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
39743 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO29_Pos (29UL)                  /*!< DSP1N1GPIO29 (Bit 29)                                 */
39744 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO29_Msk (0x20000000UL)          /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
39745 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO28_Pos (28UL)                  /*!< DSP1N1GPIO28 (Bit 28)                                 */
39746 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO28_Msk (0x10000000UL)          /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
39747 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO27_Pos (27UL)                  /*!< DSP1N1GPIO27 (Bit 27)                                 */
39748 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO27_Msk (0x8000000UL)           /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
39749 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO26_Pos (26UL)                  /*!< DSP1N1GPIO26 (Bit 26)                                 */
39750 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO26_Msk (0x4000000UL)           /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
39751 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO25_Pos (25UL)                  /*!< DSP1N1GPIO25 (Bit 25)                                 */
39752 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO25_Msk (0x2000000UL)           /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
39753 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO24_Pos (24UL)                  /*!< DSP1N1GPIO24 (Bit 24)                                 */
39754 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO24_Msk (0x1000000UL)           /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
39755 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO23_Pos (23UL)                  /*!< DSP1N1GPIO23 (Bit 23)                                 */
39756 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO23_Msk (0x800000UL)            /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
39757 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO22_Pos (22UL)                  /*!< DSP1N1GPIO22 (Bit 22)                                 */
39758 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO22_Msk (0x400000UL)            /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
39759 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO21_Pos (21UL)                  /*!< DSP1N1GPIO21 (Bit 21)                                 */
39760 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO21_Msk (0x200000UL)            /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
39761 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO20_Pos (20UL)                  /*!< DSP1N1GPIO20 (Bit 20)                                 */
39762 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO20_Msk (0x100000UL)            /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
39763 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO19_Pos (19UL)                  /*!< DSP1N1GPIO19 (Bit 19)                                 */
39764 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO19_Msk (0x80000UL)             /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
39765 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO18_Pos (18UL)                  /*!< DSP1N1GPIO18 (Bit 18)                                 */
39766 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO18_Msk (0x40000UL)             /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
39767 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO17_Pos (17UL)                  /*!< DSP1N1GPIO17 (Bit 17)                                 */
39768 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO17_Msk (0x20000UL)             /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
39769 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO16_Pos (16UL)                  /*!< DSP1N1GPIO16 (Bit 16)                                 */
39770 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO16_Msk (0x10000UL)             /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
39771 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO15_Pos (15UL)                  /*!< DSP1N1GPIO15 (Bit 15)                                 */
39772 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO15_Msk (0x8000UL)              /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
39773 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO14_Pos (14UL)                  /*!< DSP1N1GPIO14 (Bit 14)                                 */
39774 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO14_Msk (0x4000UL)              /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
39775 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO13_Pos (13UL)                  /*!< DSP1N1GPIO13 (Bit 13)                                 */
39776 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO13_Msk (0x2000UL)              /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
39777 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO12_Pos (12UL)                  /*!< DSP1N1GPIO12 (Bit 12)                                 */
39778 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO12_Msk (0x1000UL)              /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
39779 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO11_Pos (11UL)                  /*!< DSP1N1GPIO11 (Bit 11)                                 */
39780 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO11_Msk (0x800UL)               /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
39781 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO10_Pos (10UL)                  /*!< DSP1N1GPIO10 (Bit 10)                                 */
39782 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO10_Msk (0x400UL)               /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
39783 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO9_Pos (9UL)                    /*!< DSP1N1GPIO9 (Bit 9)                                   */
39784 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO9_Msk (0x200UL)                /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
39785 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO8_Pos (8UL)                    /*!< DSP1N1GPIO8 (Bit 8)                                   */
39786 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO8_Msk (0x100UL)                /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
39787 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO7_Pos (7UL)                    /*!< DSP1N1GPIO7 (Bit 7)                                   */
39788 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO7_Msk (0x80UL)                 /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
39789 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO6_Pos (6UL)                    /*!< DSP1N1GPIO6 (Bit 6)                                   */
39790 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO6_Msk (0x40UL)                 /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
39791 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO5_Pos (5UL)                    /*!< DSP1N1GPIO5 (Bit 5)                                   */
39792 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO5_Msk (0x20UL)                 /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
39793 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO4_Pos (4UL)                    /*!< DSP1N1GPIO4 (Bit 4)                                   */
39794 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO4_Msk (0x10UL)                 /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
39795 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO3_Pos (3UL)                    /*!< DSP1N1GPIO3 (Bit 3)                                   */
39796 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO3_Msk (0x8UL)                  /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
39797 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO2_Pos (2UL)                    /*!< DSP1N1GPIO2 (Bit 2)                                   */
39798 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO2_Msk (0x4UL)                  /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
39799 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO1_Pos (1UL)                    /*!< DSP1N1GPIO1 (Bit 1)                                   */
39800 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO1_Msk (0x2UL)                  /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
39801 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO0_Pos (0UL)                    /*!< DSP1N1GPIO0 (Bit 0)                                   */
39802 #define GPIO_DSP1N1INT0SET_DSP1N1GPIO0_Msk (0x1UL)                  /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
39803 /* =====================================================  DSP1N1INT1EN  ====================================================== */
39804 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO63_Pos (31UL)                   /*!< DSP1N1GPIO63 (Bit 31)                                 */
39805 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO63_Msk (0x80000000UL)           /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
39806 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO62_Pos (30UL)                   /*!< DSP1N1GPIO62 (Bit 30)                                 */
39807 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO62_Msk (0x40000000UL)           /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
39808 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO61_Pos (29UL)                   /*!< DSP1N1GPIO61 (Bit 29)                                 */
39809 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO61_Msk (0x20000000UL)           /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
39810 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO60_Pos (28UL)                   /*!< DSP1N1GPIO60 (Bit 28)                                 */
39811 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO60_Msk (0x10000000UL)           /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
39812 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO59_Pos (27UL)                   /*!< DSP1N1GPIO59 (Bit 27)                                 */
39813 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO59_Msk (0x8000000UL)            /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
39814 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO58_Pos (26UL)                   /*!< DSP1N1GPIO58 (Bit 26)                                 */
39815 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO58_Msk (0x4000000UL)            /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
39816 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO57_Pos (25UL)                   /*!< DSP1N1GPIO57 (Bit 25)                                 */
39817 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO57_Msk (0x2000000UL)            /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
39818 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO56_Pos (24UL)                   /*!< DSP1N1GPIO56 (Bit 24)                                 */
39819 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO56_Msk (0x1000000UL)            /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
39820 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO55_Pos (23UL)                   /*!< DSP1N1GPIO55 (Bit 23)                                 */
39821 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO55_Msk (0x800000UL)             /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
39822 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO54_Pos (22UL)                   /*!< DSP1N1GPIO54 (Bit 22)                                 */
39823 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO54_Msk (0x400000UL)             /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
39824 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO53_Pos (21UL)                   /*!< DSP1N1GPIO53 (Bit 21)                                 */
39825 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO53_Msk (0x200000UL)             /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
39826 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO52_Pos (20UL)                   /*!< DSP1N1GPIO52 (Bit 20)                                 */
39827 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO52_Msk (0x100000UL)             /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
39828 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO51_Pos (19UL)                   /*!< DSP1N1GPIO51 (Bit 19)                                 */
39829 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO51_Msk (0x80000UL)              /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
39830 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO50_Pos (18UL)                   /*!< DSP1N1GPIO50 (Bit 18)                                 */
39831 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO50_Msk (0x40000UL)              /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
39832 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO49_Pos (17UL)                   /*!< DSP1N1GPIO49 (Bit 17)                                 */
39833 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO49_Msk (0x20000UL)              /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
39834 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO48_Pos (16UL)                   /*!< DSP1N1GPIO48 (Bit 16)                                 */
39835 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO48_Msk (0x10000UL)              /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
39836 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO47_Pos (15UL)                   /*!< DSP1N1GPIO47 (Bit 15)                                 */
39837 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO47_Msk (0x8000UL)               /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
39838 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO46_Pos (14UL)                   /*!< DSP1N1GPIO46 (Bit 14)                                 */
39839 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO46_Msk (0x4000UL)               /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
39840 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO45_Pos (13UL)                   /*!< DSP1N1GPIO45 (Bit 13)                                 */
39841 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO45_Msk (0x2000UL)               /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
39842 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO44_Pos (12UL)                   /*!< DSP1N1GPIO44 (Bit 12)                                 */
39843 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO44_Msk (0x1000UL)               /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
39844 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO43_Pos (11UL)                   /*!< DSP1N1GPIO43 (Bit 11)                                 */
39845 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO43_Msk (0x800UL)                /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
39846 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO42_Pos (10UL)                   /*!< DSP1N1GPIO42 (Bit 10)                                 */
39847 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO42_Msk (0x400UL)                /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
39848 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO41_Pos (9UL)                    /*!< DSP1N1GPIO41 (Bit 9)                                  */
39849 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO41_Msk (0x200UL)                /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
39850 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO40_Pos (8UL)                    /*!< DSP1N1GPIO40 (Bit 8)                                  */
39851 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO40_Msk (0x100UL)                /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
39852 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO39_Pos (7UL)                    /*!< DSP1N1GPIO39 (Bit 7)                                  */
39853 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO39_Msk (0x80UL)                 /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
39854 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO38_Pos (6UL)                    /*!< DSP1N1GPIO38 (Bit 6)                                  */
39855 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO38_Msk (0x40UL)                 /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
39856 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO37_Pos (5UL)                    /*!< DSP1N1GPIO37 (Bit 5)                                  */
39857 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO37_Msk (0x20UL)                 /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
39858 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO36_Pos (4UL)                    /*!< DSP1N1GPIO36 (Bit 4)                                  */
39859 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO36_Msk (0x10UL)                 /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
39860 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO35_Pos (3UL)                    /*!< DSP1N1GPIO35 (Bit 3)                                  */
39861 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO35_Msk (0x8UL)                  /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
39862 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO34_Pos (2UL)                    /*!< DSP1N1GPIO34 (Bit 2)                                  */
39863 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO34_Msk (0x4UL)                  /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
39864 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO33_Pos (1UL)                    /*!< DSP1N1GPIO33 (Bit 1)                                  */
39865 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO33_Msk (0x2UL)                  /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
39866 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO32_Pos (0UL)                    /*!< DSP1N1GPIO32 (Bit 0)                                  */
39867 #define GPIO_DSP1N1INT1EN_DSP1N1GPIO32_Msk (0x1UL)                  /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
39868 /* ====================================================  DSP1N1INT1STAT  ===================================================== */
39869 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO63_Pos (31UL)                 /*!< DSP1N1GPIO63 (Bit 31)                                 */
39870 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO63_Msk (0x80000000UL)         /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
39871 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO62_Pos (30UL)                 /*!< DSP1N1GPIO62 (Bit 30)                                 */
39872 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO62_Msk (0x40000000UL)         /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
39873 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO61_Pos (29UL)                 /*!< DSP1N1GPIO61 (Bit 29)                                 */
39874 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO61_Msk (0x20000000UL)         /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
39875 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO60_Pos (28UL)                 /*!< DSP1N1GPIO60 (Bit 28)                                 */
39876 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO60_Msk (0x10000000UL)         /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
39877 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO59_Pos (27UL)                 /*!< DSP1N1GPIO59 (Bit 27)                                 */
39878 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO59_Msk (0x8000000UL)          /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
39879 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO58_Pos (26UL)                 /*!< DSP1N1GPIO58 (Bit 26)                                 */
39880 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO58_Msk (0x4000000UL)          /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
39881 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO57_Pos (25UL)                 /*!< DSP1N1GPIO57 (Bit 25)                                 */
39882 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO57_Msk (0x2000000UL)          /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
39883 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO56_Pos (24UL)                 /*!< DSP1N1GPIO56 (Bit 24)                                 */
39884 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO56_Msk (0x1000000UL)          /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
39885 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO55_Pos (23UL)                 /*!< DSP1N1GPIO55 (Bit 23)                                 */
39886 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO55_Msk (0x800000UL)           /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
39887 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO54_Pos (22UL)                 /*!< DSP1N1GPIO54 (Bit 22)                                 */
39888 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO54_Msk (0x400000UL)           /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
39889 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO53_Pos (21UL)                 /*!< DSP1N1GPIO53 (Bit 21)                                 */
39890 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO53_Msk (0x200000UL)           /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
39891 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO52_Pos (20UL)                 /*!< DSP1N1GPIO52 (Bit 20)                                 */
39892 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO52_Msk (0x100000UL)           /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
39893 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO51_Pos (19UL)                 /*!< DSP1N1GPIO51 (Bit 19)                                 */
39894 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO51_Msk (0x80000UL)            /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
39895 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO50_Pos (18UL)                 /*!< DSP1N1GPIO50 (Bit 18)                                 */
39896 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO50_Msk (0x40000UL)            /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
39897 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO49_Pos (17UL)                 /*!< DSP1N1GPIO49 (Bit 17)                                 */
39898 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO49_Msk (0x20000UL)            /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
39899 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO48_Pos (16UL)                 /*!< DSP1N1GPIO48 (Bit 16)                                 */
39900 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO48_Msk (0x10000UL)            /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
39901 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO47_Pos (15UL)                 /*!< DSP1N1GPIO47 (Bit 15)                                 */
39902 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO47_Msk (0x8000UL)             /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
39903 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO46_Pos (14UL)                 /*!< DSP1N1GPIO46 (Bit 14)                                 */
39904 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO46_Msk (0x4000UL)             /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
39905 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO45_Pos (13UL)                 /*!< DSP1N1GPIO45 (Bit 13)                                 */
39906 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO45_Msk (0x2000UL)             /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
39907 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO44_Pos (12UL)                 /*!< DSP1N1GPIO44 (Bit 12)                                 */
39908 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO44_Msk (0x1000UL)             /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
39909 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO43_Pos (11UL)                 /*!< DSP1N1GPIO43 (Bit 11)                                 */
39910 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO43_Msk (0x800UL)              /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
39911 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO42_Pos (10UL)                 /*!< DSP1N1GPIO42 (Bit 10)                                 */
39912 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO42_Msk (0x400UL)              /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
39913 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO41_Pos (9UL)                  /*!< DSP1N1GPIO41 (Bit 9)                                  */
39914 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO41_Msk (0x200UL)              /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
39915 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO40_Pos (8UL)                  /*!< DSP1N1GPIO40 (Bit 8)                                  */
39916 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO40_Msk (0x100UL)              /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
39917 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO39_Pos (7UL)                  /*!< DSP1N1GPIO39 (Bit 7)                                  */
39918 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO39_Msk (0x80UL)               /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
39919 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO38_Pos (6UL)                  /*!< DSP1N1GPIO38 (Bit 6)                                  */
39920 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO38_Msk (0x40UL)               /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
39921 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO37_Pos (5UL)                  /*!< DSP1N1GPIO37 (Bit 5)                                  */
39922 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO37_Msk (0x20UL)               /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
39923 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO36_Pos (4UL)                  /*!< DSP1N1GPIO36 (Bit 4)                                  */
39924 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO36_Msk (0x10UL)               /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
39925 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO35_Pos (3UL)                  /*!< DSP1N1GPIO35 (Bit 3)                                  */
39926 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO35_Msk (0x8UL)                /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
39927 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO34_Pos (2UL)                  /*!< DSP1N1GPIO34 (Bit 2)                                  */
39928 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO34_Msk (0x4UL)                /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
39929 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO33_Pos (1UL)                  /*!< DSP1N1GPIO33 (Bit 1)                                  */
39930 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO33_Msk (0x2UL)                /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
39931 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO32_Pos (0UL)                  /*!< DSP1N1GPIO32 (Bit 0)                                  */
39932 #define GPIO_DSP1N1INT1STAT_DSP1N1GPIO32_Msk (0x1UL)                /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
39933 /* =====================================================  DSP1N1INT1CLR  ===================================================== */
39934 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO63_Pos (31UL)                  /*!< DSP1N1GPIO63 (Bit 31)                                 */
39935 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO63_Msk (0x80000000UL)          /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
39936 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO62_Pos (30UL)                  /*!< DSP1N1GPIO62 (Bit 30)                                 */
39937 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO62_Msk (0x40000000UL)          /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
39938 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO61_Pos (29UL)                  /*!< DSP1N1GPIO61 (Bit 29)                                 */
39939 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO61_Msk (0x20000000UL)          /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
39940 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO60_Pos (28UL)                  /*!< DSP1N1GPIO60 (Bit 28)                                 */
39941 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO60_Msk (0x10000000UL)          /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
39942 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO59_Pos (27UL)                  /*!< DSP1N1GPIO59 (Bit 27)                                 */
39943 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO59_Msk (0x8000000UL)           /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
39944 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO58_Pos (26UL)                  /*!< DSP1N1GPIO58 (Bit 26)                                 */
39945 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO58_Msk (0x4000000UL)           /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
39946 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO57_Pos (25UL)                  /*!< DSP1N1GPIO57 (Bit 25)                                 */
39947 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO57_Msk (0x2000000UL)           /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
39948 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO56_Pos (24UL)                  /*!< DSP1N1GPIO56 (Bit 24)                                 */
39949 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO56_Msk (0x1000000UL)           /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
39950 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO55_Pos (23UL)                  /*!< DSP1N1GPIO55 (Bit 23)                                 */
39951 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO55_Msk (0x800000UL)            /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
39952 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO54_Pos (22UL)                  /*!< DSP1N1GPIO54 (Bit 22)                                 */
39953 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO54_Msk (0x400000UL)            /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
39954 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO53_Pos (21UL)                  /*!< DSP1N1GPIO53 (Bit 21)                                 */
39955 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO53_Msk (0x200000UL)            /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
39956 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO52_Pos (20UL)                  /*!< DSP1N1GPIO52 (Bit 20)                                 */
39957 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO52_Msk (0x100000UL)            /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
39958 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO51_Pos (19UL)                  /*!< DSP1N1GPIO51 (Bit 19)                                 */
39959 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO51_Msk (0x80000UL)             /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
39960 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO50_Pos (18UL)                  /*!< DSP1N1GPIO50 (Bit 18)                                 */
39961 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO50_Msk (0x40000UL)             /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
39962 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO49_Pos (17UL)                  /*!< DSP1N1GPIO49 (Bit 17)                                 */
39963 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO49_Msk (0x20000UL)             /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
39964 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO48_Pos (16UL)                  /*!< DSP1N1GPIO48 (Bit 16)                                 */
39965 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO48_Msk (0x10000UL)             /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
39966 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO47_Pos (15UL)                  /*!< DSP1N1GPIO47 (Bit 15)                                 */
39967 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO47_Msk (0x8000UL)              /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
39968 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO46_Pos (14UL)                  /*!< DSP1N1GPIO46 (Bit 14)                                 */
39969 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO46_Msk (0x4000UL)              /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
39970 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO45_Pos (13UL)                  /*!< DSP1N1GPIO45 (Bit 13)                                 */
39971 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO45_Msk (0x2000UL)              /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
39972 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO44_Pos (12UL)                  /*!< DSP1N1GPIO44 (Bit 12)                                 */
39973 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO44_Msk (0x1000UL)              /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
39974 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO43_Pos (11UL)                  /*!< DSP1N1GPIO43 (Bit 11)                                 */
39975 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO43_Msk (0x800UL)               /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
39976 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO42_Pos (10UL)                  /*!< DSP1N1GPIO42 (Bit 10)                                 */
39977 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO42_Msk (0x400UL)               /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
39978 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO41_Pos (9UL)                   /*!< DSP1N1GPIO41 (Bit 9)                                  */
39979 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO41_Msk (0x200UL)               /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
39980 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO40_Pos (8UL)                   /*!< DSP1N1GPIO40 (Bit 8)                                  */
39981 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO40_Msk (0x100UL)               /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
39982 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO39_Pos (7UL)                   /*!< DSP1N1GPIO39 (Bit 7)                                  */
39983 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO39_Msk (0x80UL)                /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
39984 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO38_Pos (6UL)                   /*!< DSP1N1GPIO38 (Bit 6)                                  */
39985 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO38_Msk (0x40UL)                /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
39986 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO37_Pos (5UL)                   /*!< DSP1N1GPIO37 (Bit 5)                                  */
39987 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO37_Msk (0x20UL)                /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
39988 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO36_Pos (4UL)                   /*!< DSP1N1GPIO36 (Bit 4)                                  */
39989 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO36_Msk (0x10UL)                /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
39990 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO35_Pos (3UL)                   /*!< DSP1N1GPIO35 (Bit 3)                                  */
39991 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO35_Msk (0x8UL)                 /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
39992 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO34_Pos (2UL)                   /*!< DSP1N1GPIO34 (Bit 2)                                  */
39993 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO34_Msk (0x4UL)                 /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
39994 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO33_Pos (1UL)                   /*!< DSP1N1GPIO33 (Bit 1)                                  */
39995 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO33_Msk (0x2UL)                 /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
39996 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO32_Pos (0UL)                   /*!< DSP1N1GPIO32 (Bit 0)                                  */
39997 #define GPIO_DSP1N1INT1CLR_DSP1N1GPIO32_Msk (0x1UL)                 /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
39998 /* =====================================================  DSP1N1INT1SET  ===================================================== */
39999 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO63_Pos (31UL)                  /*!< DSP1N1GPIO63 (Bit 31)                                 */
40000 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO63_Msk (0x80000000UL)          /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
40001 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO62_Pos (30UL)                  /*!< DSP1N1GPIO62 (Bit 30)                                 */
40002 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO62_Msk (0x40000000UL)          /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
40003 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO61_Pos (29UL)                  /*!< DSP1N1GPIO61 (Bit 29)                                 */
40004 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO61_Msk (0x20000000UL)          /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
40005 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO60_Pos (28UL)                  /*!< DSP1N1GPIO60 (Bit 28)                                 */
40006 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO60_Msk (0x10000000UL)          /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
40007 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO59_Pos (27UL)                  /*!< DSP1N1GPIO59 (Bit 27)                                 */
40008 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO59_Msk (0x8000000UL)           /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
40009 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO58_Pos (26UL)                  /*!< DSP1N1GPIO58 (Bit 26)                                 */
40010 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO58_Msk (0x4000000UL)           /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
40011 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO57_Pos (25UL)                  /*!< DSP1N1GPIO57 (Bit 25)                                 */
40012 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO57_Msk (0x2000000UL)           /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
40013 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO56_Pos (24UL)                  /*!< DSP1N1GPIO56 (Bit 24)                                 */
40014 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO56_Msk (0x1000000UL)           /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
40015 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO55_Pos (23UL)                  /*!< DSP1N1GPIO55 (Bit 23)                                 */
40016 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO55_Msk (0x800000UL)            /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
40017 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO54_Pos (22UL)                  /*!< DSP1N1GPIO54 (Bit 22)                                 */
40018 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO54_Msk (0x400000UL)            /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
40019 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO53_Pos (21UL)                  /*!< DSP1N1GPIO53 (Bit 21)                                 */
40020 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO53_Msk (0x200000UL)            /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
40021 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO52_Pos (20UL)                  /*!< DSP1N1GPIO52 (Bit 20)                                 */
40022 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO52_Msk (0x100000UL)            /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
40023 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO51_Pos (19UL)                  /*!< DSP1N1GPIO51 (Bit 19)                                 */
40024 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO51_Msk (0x80000UL)             /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
40025 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO50_Pos (18UL)                  /*!< DSP1N1GPIO50 (Bit 18)                                 */
40026 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO50_Msk (0x40000UL)             /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
40027 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO49_Pos (17UL)                  /*!< DSP1N1GPIO49 (Bit 17)                                 */
40028 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO49_Msk (0x20000UL)             /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
40029 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO48_Pos (16UL)                  /*!< DSP1N1GPIO48 (Bit 16)                                 */
40030 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO48_Msk (0x10000UL)             /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
40031 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO47_Pos (15UL)                  /*!< DSP1N1GPIO47 (Bit 15)                                 */
40032 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO47_Msk (0x8000UL)              /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
40033 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO46_Pos (14UL)                  /*!< DSP1N1GPIO46 (Bit 14)                                 */
40034 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO46_Msk (0x4000UL)              /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
40035 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO45_Pos (13UL)                  /*!< DSP1N1GPIO45 (Bit 13)                                 */
40036 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO45_Msk (0x2000UL)              /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
40037 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO44_Pos (12UL)                  /*!< DSP1N1GPIO44 (Bit 12)                                 */
40038 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO44_Msk (0x1000UL)              /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
40039 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO43_Pos (11UL)                  /*!< DSP1N1GPIO43 (Bit 11)                                 */
40040 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO43_Msk (0x800UL)               /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
40041 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO42_Pos (10UL)                  /*!< DSP1N1GPIO42 (Bit 10)                                 */
40042 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO42_Msk (0x400UL)               /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
40043 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO41_Pos (9UL)                   /*!< DSP1N1GPIO41 (Bit 9)                                  */
40044 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO41_Msk (0x200UL)               /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
40045 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO40_Pos (8UL)                   /*!< DSP1N1GPIO40 (Bit 8)                                  */
40046 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO40_Msk (0x100UL)               /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
40047 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO39_Pos (7UL)                   /*!< DSP1N1GPIO39 (Bit 7)                                  */
40048 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO39_Msk (0x80UL)                /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
40049 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO38_Pos (6UL)                   /*!< DSP1N1GPIO38 (Bit 6)                                  */
40050 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO38_Msk (0x40UL)                /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
40051 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO37_Pos (5UL)                   /*!< DSP1N1GPIO37 (Bit 5)                                  */
40052 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO37_Msk (0x20UL)                /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
40053 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO36_Pos (4UL)                   /*!< DSP1N1GPIO36 (Bit 4)                                  */
40054 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO36_Msk (0x10UL)                /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
40055 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO35_Pos (3UL)                   /*!< DSP1N1GPIO35 (Bit 3)                                  */
40056 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO35_Msk (0x8UL)                 /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
40057 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO34_Pos (2UL)                   /*!< DSP1N1GPIO34 (Bit 2)                                  */
40058 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO34_Msk (0x4UL)                 /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
40059 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO33_Pos (1UL)                   /*!< DSP1N1GPIO33 (Bit 1)                                  */
40060 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO33_Msk (0x2UL)                 /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
40061 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO32_Pos (0UL)                   /*!< DSP1N1GPIO32 (Bit 0)                                  */
40062 #define GPIO_DSP1N1INT1SET_DSP1N1GPIO32_Msk (0x1UL)                 /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
40063 /* =====================================================  DSP1N1INT2EN  ====================================================== */
40064 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO95_Pos (31UL)                   /*!< DSP1N1GPIO95 (Bit 31)                                 */
40065 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO95_Msk (0x80000000UL)           /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
40066 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO94_Pos (30UL)                   /*!< DSP1N1GPIO94 (Bit 30)                                 */
40067 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO94_Msk (0x40000000UL)           /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
40068 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO93_Pos (29UL)                   /*!< DSP1N1GPIO93 (Bit 29)                                 */
40069 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO93_Msk (0x20000000UL)           /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
40070 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO92_Pos (28UL)                   /*!< DSP1N1GPIO92 (Bit 28)                                 */
40071 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO92_Msk (0x10000000UL)           /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
40072 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO91_Pos (27UL)                   /*!< DSP1N1GPIO91 (Bit 27)                                 */
40073 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO91_Msk (0x8000000UL)            /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
40074 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO90_Pos (26UL)                   /*!< DSP1N1GPIO90 (Bit 26)                                 */
40075 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO90_Msk (0x4000000UL)            /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
40076 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO89_Pos (25UL)                   /*!< DSP1N1GPIO89 (Bit 25)                                 */
40077 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO89_Msk (0x2000000UL)            /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
40078 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO88_Pos (24UL)                   /*!< DSP1N1GPIO88 (Bit 24)                                 */
40079 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO88_Msk (0x1000000UL)            /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
40080 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO87_Pos (23UL)                   /*!< DSP1N1GPIO87 (Bit 23)                                 */
40081 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO87_Msk (0x800000UL)             /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
40082 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO86_Pos (22UL)                   /*!< DSP1N1GPIO86 (Bit 22)                                 */
40083 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO86_Msk (0x400000UL)             /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
40084 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO85_Pos (21UL)                   /*!< DSP1N1GPIO85 (Bit 21)                                 */
40085 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO85_Msk (0x200000UL)             /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
40086 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO84_Pos (20UL)                   /*!< DSP1N1GPIO84 (Bit 20)                                 */
40087 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO84_Msk (0x100000UL)             /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
40088 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO83_Pos (19UL)                   /*!< DSP1N1GPIO83 (Bit 19)                                 */
40089 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO83_Msk (0x80000UL)              /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
40090 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO82_Pos (18UL)                   /*!< DSP1N1GPIO82 (Bit 18)                                 */
40091 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO82_Msk (0x40000UL)              /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
40092 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO81_Pos (17UL)                   /*!< DSP1N1GPIO81 (Bit 17)                                 */
40093 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO81_Msk (0x20000UL)              /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
40094 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO80_Pos (16UL)                   /*!< DSP1N1GPIO80 (Bit 16)                                 */
40095 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO80_Msk (0x10000UL)              /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
40096 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO79_Pos (15UL)                   /*!< DSP1N1GPIO79 (Bit 15)                                 */
40097 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO79_Msk (0x8000UL)               /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
40098 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO78_Pos (14UL)                   /*!< DSP1N1GPIO78 (Bit 14)                                 */
40099 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO78_Msk (0x4000UL)               /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
40100 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO77_Pos (13UL)                   /*!< DSP1N1GPIO77 (Bit 13)                                 */
40101 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO77_Msk (0x2000UL)               /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
40102 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO76_Pos (12UL)                   /*!< DSP1N1GPIO76 (Bit 12)                                 */
40103 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO76_Msk (0x1000UL)               /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
40104 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO75_Pos (11UL)                   /*!< DSP1N1GPIO75 (Bit 11)                                 */
40105 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO75_Msk (0x800UL)                /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
40106 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO74_Pos (10UL)                   /*!< DSP1N1GPIO74 (Bit 10)                                 */
40107 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO74_Msk (0x400UL)                /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
40108 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO73_Pos (9UL)                    /*!< DSP1N1GPIO73 (Bit 9)                                  */
40109 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO73_Msk (0x200UL)                /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
40110 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO72_Pos (8UL)                    /*!< DSP1N1GPIO72 (Bit 8)                                  */
40111 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO72_Msk (0x100UL)                /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
40112 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO71_Pos (7UL)                    /*!< DSP1N1GPIO71 (Bit 7)                                  */
40113 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO71_Msk (0x80UL)                 /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
40114 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO70_Pos (6UL)                    /*!< DSP1N1GPIO70 (Bit 6)                                  */
40115 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO70_Msk (0x40UL)                 /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
40116 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO69_Pos (5UL)                    /*!< DSP1N1GPIO69 (Bit 5)                                  */
40117 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO69_Msk (0x20UL)                 /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
40118 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO68_Pos (4UL)                    /*!< DSP1N1GPIO68 (Bit 4)                                  */
40119 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO68_Msk (0x10UL)                 /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
40120 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO67_Pos (3UL)                    /*!< DSP1N1GPIO67 (Bit 3)                                  */
40121 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO67_Msk (0x8UL)                  /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
40122 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO66_Pos (2UL)                    /*!< DSP1N1GPIO66 (Bit 2)                                  */
40123 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO66_Msk (0x4UL)                  /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
40124 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO65_Pos (1UL)                    /*!< DSP1N1GPIO65 (Bit 1)                                  */
40125 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO65_Msk (0x2UL)                  /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
40126 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO64_Pos (0UL)                    /*!< DSP1N1GPIO64 (Bit 0)                                  */
40127 #define GPIO_DSP1N1INT2EN_DSP1N1GPIO64_Msk (0x1UL)                  /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
40128 /* ====================================================  DSP1N1INT2STAT  ===================================================== */
40129 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO95_Pos (31UL)                 /*!< DSP1N1GPIO95 (Bit 31)                                 */
40130 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO95_Msk (0x80000000UL)         /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
40131 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO94_Pos (30UL)                 /*!< DSP1N1GPIO94 (Bit 30)                                 */
40132 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO94_Msk (0x40000000UL)         /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
40133 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO93_Pos (29UL)                 /*!< DSP1N1GPIO93 (Bit 29)                                 */
40134 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO93_Msk (0x20000000UL)         /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
40135 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO92_Pos (28UL)                 /*!< DSP1N1GPIO92 (Bit 28)                                 */
40136 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO92_Msk (0x10000000UL)         /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
40137 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO91_Pos (27UL)                 /*!< DSP1N1GPIO91 (Bit 27)                                 */
40138 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO91_Msk (0x8000000UL)          /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
40139 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO90_Pos (26UL)                 /*!< DSP1N1GPIO90 (Bit 26)                                 */
40140 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO90_Msk (0x4000000UL)          /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
40141 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO89_Pos (25UL)                 /*!< DSP1N1GPIO89 (Bit 25)                                 */
40142 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO89_Msk (0x2000000UL)          /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
40143 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO88_Pos (24UL)                 /*!< DSP1N1GPIO88 (Bit 24)                                 */
40144 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO88_Msk (0x1000000UL)          /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
40145 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO87_Pos (23UL)                 /*!< DSP1N1GPIO87 (Bit 23)                                 */
40146 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO87_Msk (0x800000UL)           /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
40147 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO86_Pos (22UL)                 /*!< DSP1N1GPIO86 (Bit 22)                                 */
40148 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO86_Msk (0x400000UL)           /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
40149 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO85_Pos (21UL)                 /*!< DSP1N1GPIO85 (Bit 21)                                 */
40150 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO85_Msk (0x200000UL)           /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
40151 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO84_Pos (20UL)                 /*!< DSP1N1GPIO84 (Bit 20)                                 */
40152 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO84_Msk (0x100000UL)           /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
40153 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO83_Pos (19UL)                 /*!< DSP1N1GPIO83 (Bit 19)                                 */
40154 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO83_Msk (0x80000UL)            /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
40155 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO82_Pos (18UL)                 /*!< DSP1N1GPIO82 (Bit 18)                                 */
40156 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO82_Msk (0x40000UL)            /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
40157 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO81_Pos (17UL)                 /*!< DSP1N1GPIO81 (Bit 17)                                 */
40158 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO81_Msk (0x20000UL)            /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
40159 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO80_Pos (16UL)                 /*!< DSP1N1GPIO80 (Bit 16)                                 */
40160 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO80_Msk (0x10000UL)            /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
40161 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO79_Pos (15UL)                 /*!< DSP1N1GPIO79 (Bit 15)                                 */
40162 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO79_Msk (0x8000UL)             /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
40163 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO78_Pos (14UL)                 /*!< DSP1N1GPIO78 (Bit 14)                                 */
40164 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO78_Msk (0x4000UL)             /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
40165 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO77_Pos (13UL)                 /*!< DSP1N1GPIO77 (Bit 13)                                 */
40166 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO77_Msk (0x2000UL)             /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
40167 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO76_Pos (12UL)                 /*!< DSP1N1GPIO76 (Bit 12)                                 */
40168 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO76_Msk (0x1000UL)             /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
40169 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO75_Pos (11UL)                 /*!< DSP1N1GPIO75 (Bit 11)                                 */
40170 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO75_Msk (0x800UL)              /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
40171 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO74_Pos (10UL)                 /*!< DSP1N1GPIO74 (Bit 10)                                 */
40172 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO74_Msk (0x400UL)              /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
40173 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO73_Pos (9UL)                  /*!< DSP1N1GPIO73 (Bit 9)                                  */
40174 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO73_Msk (0x200UL)              /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
40175 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO72_Pos (8UL)                  /*!< DSP1N1GPIO72 (Bit 8)                                  */
40176 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO72_Msk (0x100UL)              /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
40177 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO71_Pos (7UL)                  /*!< DSP1N1GPIO71 (Bit 7)                                  */
40178 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO71_Msk (0x80UL)               /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
40179 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO70_Pos (6UL)                  /*!< DSP1N1GPIO70 (Bit 6)                                  */
40180 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO70_Msk (0x40UL)               /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
40181 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO69_Pos (5UL)                  /*!< DSP1N1GPIO69 (Bit 5)                                  */
40182 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO69_Msk (0x20UL)               /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
40183 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO68_Pos (4UL)                  /*!< DSP1N1GPIO68 (Bit 4)                                  */
40184 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO68_Msk (0x10UL)               /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
40185 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO67_Pos (3UL)                  /*!< DSP1N1GPIO67 (Bit 3)                                  */
40186 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO67_Msk (0x8UL)                /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
40187 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO66_Pos (2UL)                  /*!< DSP1N1GPIO66 (Bit 2)                                  */
40188 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO66_Msk (0x4UL)                /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
40189 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO65_Pos (1UL)                  /*!< DSP1N1GPIO65 (Bit 1)                                  */
40190 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO65_Msk (0x2UL)                /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
40191 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO64_Pos (0UL)                  /*!< DSP1N1GPIO64 (Bit 0)                                  */
40192 #define GPIO_DSP1N1INT2STAT_DSP1N1GPIO64_Msk (0x1UL)                /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
40193 /* =====================================================  DSP1N1INT2CLR  ===================================================== */
40194 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO95_Pos (31UL)                  /*!< DSP1N1GPIO95 (Bit 31)                                 */
40195 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO95_Msk (0x80000000UL)          /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
40196 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO94_Pos (30UL)                  /*!< DSP1N1GPIO94 (Bit 30)                                 */
40197 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO94_Msk (0x40000000UL)          /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
40198 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO93_Pos (29UL)                  /*!< DSP1N1GPIO93 (Bit 29)                                 */
40199 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO93_Msk (0x20000000UL)          /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
40200 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO92_Pos (28UL)                  /*!< DSP1N1GPIO92 (Bit 28)                                 */
40201 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO92_Msk (0x10000000UL)          /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
40202 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO91_Pos (27UL)                  /*!< DSP1N1GPIO91 (Bit 27)                                 */
40203 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO91_Msk (0x8000000UL)           /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
40204 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO90_Pos (26UL)                  /*!< DSP1N1GPIO90 (Bit 26)                                 */
40205 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO90_Msk (0x4000000UL)           /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
40206 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO89_Pos (25UL)                  /*!< DSP1N1GPIO89 (Bit 25)                                 */
40207 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO89_Msk (0x2000000UL)           /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
40208 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO88_Pos (24UL)                  /*!< DSP1N1GPIO88 (Bit 24)                                 */
40209 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO88_Msk (0x1000000UL)           /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
40210 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO87_Pos (23UL)                  /*!< DSP1N1GPIO87 (Bit 23)                                 */
40211 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO87_Msk (0x800000UL)            /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
40212 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO86_Pos (22UL)                  /*!< DSP1N1GPIO86 (Bit 22)                                 */
40213 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO86_Msk (0x400000UL)            /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
40214 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO85_Pos (21UL)                  /*!< DSP1N1GPIO85 (Bit 21)                                 */
40215 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO85_Msk (0x200000UL)            /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
40216 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO84_Pos (20UL)                  /*!< DSP1N1GPIO84 (Bit 20)                                 */
40217 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO84_Msk (0x100000UL)            /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
40218 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO83_Pos (19UL)                  /*!< DSP1N1GPIO83 (Bit 19)                                 */
40219 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO83_Msk (0x80000UL)             /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
40220 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO82_Pos (18UL)                  /*!< DSP1N1GPIO82 (Bit 18)                                 */
40221 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO82_Msk (0x40000UL)             /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
40222 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO81_Pos (17UL)                  /*!< DSP1N1GPIO81 (Bit 17)                                 */
40223 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO81_Msk (0x20000UL)             /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
40224 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO80_Pos (16UL)                  /*!< DSP1N1GPIO80 (Bit 16)                                 */
40225 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO80_Msk (0x10000UL)             /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
40226 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO79_Pos (15UL)                  /*!< DSP1N1GPIO79 (Bit 15)                                 */
40227 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO79_Msk (0x8000UL)              /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
40228 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO78_Pos (14UL)                  /*!< DSP1N1GPIO78 (Bit 14)                                 */
40229 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO78_Msk (0x4000UL)              /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
40230 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO77_Pos (13UL)                  /*!< DSP1N1GPIO77 (Bit 13)                                 */
40231 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO77_Msk (0x2000UL)              /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
40232 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO76_Pos (12UL)                  /*!< DSP1N1GPIO76 (Bit 12)                                 */
40233 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO76_Msk (0x1000UL)              /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
40234 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO75_Pos (11UL)                  /*!< DSP1N1GPIO75 (Bit 11)                                 */
40235 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO75_Msk (0x800UL)               /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
40236 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO74_Pos (10UL)                  /*!< DSP1N1GPIO74 (Bit 10)                                 */
40237 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO74_Msk (0x400UL)               /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
40238 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO73_Pos (9UL)                   /*!< DSP1N1GPIO73 (Bit 9)                                  */
40239 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO73_Msk (0x200UL)               /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
40240 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO72_Pos (8UL)                   /*!< DSP1N1GPIO72 (Bit 8)                                  */
40241 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO72_Msk (0x100UL)               /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
40242 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO71_Pos (7UL)                   /*!< DSP1N1GPIO71 (Bit 7)                                  */
40243 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO71_Msk (0x80UL)                /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
40244 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO70_Pos (6UL)                   /*!< DSP1N1GPIO70 (Bit 6)                                  */
40245 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO70_Msk (0x40UL)                /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
40246 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO69_Pos (5UL)                   /*!< DSP1N1GPIO69 (Bit 5)                                  */
40247 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO69_Msk (0x20UL)                /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
40248 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO68_Pos (4UL)                   /*!< DSP1N1GPIO68 (Bit 4)                                  */
40249 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO68_Msk (0x10UL)                /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
40250 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO67_Pos (3UL)                   /*!< DSP1N1GPIO67 (Bit 3)                                  */
40251 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO67_Msk (0x8UL)                 /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
40252 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO66_Pos (2UL)                   /*!< DSP1N1GPIO66 (Bit 2)                                  */
40253 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO66_Msk (0x4UL)                 /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
40254 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO65_Pos (1UL)                   /*!< DSP1N1GPIO65 (Bit 1)                                  */
40255 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO65_Msk (0x2UL)                 /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
40256 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO64_Pos (0UL)                   /*!< DSP1N1GPIO64 (Bit 0)                                  */
40257 #define GPIO_DSP1N1INT2CLR_DSP1N1GPIO64_Msk (0x1UL)                 /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
40258 /* =====================================================  DSP1N1INT2SET  ===================================================== */
40259 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO95_Pos (31UL)                  /*!< DSP1N1GPIO95 (Bit 31)                                 */
40260 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO95_Msk (0x80000000UL)          /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
40261 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO94_Pos (30UL)                  /*!< DSP1N1GPIO94 (Bit 30)                                 */
40262 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO94_Msk (0x40000000UL)          /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
40263 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO93_Pos (29UL)                  /*!< DSP1N1GPIO93 (Bit 29)                                 */
40264 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO93_Msk (0x20000000UL)          /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
40265 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO92_Pos (28UL)                  /*!< DSP1N1GPIO92 (Bit 28)                                 */
40266 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO92_Msk (0x10000000UL)          /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
40267 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO91_Pos (27UL)                  /*!< DSP1N1GPIO91 (Bit 27)                                 */
40268 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO91_Msk (0x8000000UL)           /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
40269 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO90_Pos (26UL)                  /*!< DSP1N1GPIO90 (Bit 26)                                 */
40270 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO90_Msk (0x4000000UL)           /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
40271 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO89_Pos (25UL)                  /*!< DSP1N1GPIO89 (Bit 25)                                 */
40272 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO89_Msk (0x2000000UL)           /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
40273 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO88_Pos (24UL)                  /*!< DSP1N1GPIO88 (Bit 24)                                 */
40274 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO88_Msk (0x1000000UL)           /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
40275 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO87_Pos (23UL)                  /*!< DSP1N1GPIO87 (Bit 23)                                 */
40276 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO87_Msk (0x800000UL)            /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
40277 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO86_Pos (22UL)                  /*!< DSP1N1GPIO86 (Bit 22)                                 */
40278 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO86_Msk (0x400000UL)            /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
40279 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO85_Pos (21UL)                  /*!< DSP1N1GPIO85 (Bit 21)                                 */
40280 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO85_Msk (0x200000UL)            /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
40281 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO84_Pos (20UL)                  /*!< DSP1N1GPIO84 (Bit 20)                                 */
40282 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO84_Msk (0x100000UL)            /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
40283 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO83_Pos (19UL)                  /*!< DSP1N1GPIO83 (Bit 19)                                 */
40284 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO83_Msk (0x80000UL)             /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
40285 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO82_Pos (18UL)                  /*!< DSP1N1GPIO82 (Bit 18)                                 */
40286 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO82_Msk (0x40000UL)             /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
40287 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO81_Pos (17UL)                  /*!< DSP1N1GPIO81 (Bit 17)                                 */
40288 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO81_Msk (0x20000UL)             /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
40289 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO80_Pos (16UL)                  /*!< DSP1N1GPIO80 (Bit 16)                                 */
40290 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO80_Msk (0x10000UL)             /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
40291 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO79_Pos (15UL)                  /*!< DSP1N1GPIO79 (Bit 15)                                 */
40292 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO79_Msk (0x8000UL)              /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
40293 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO78_Pos (14UL)                  /*!< DSP1N1GPIO78 (Bit 14)                                 */
40294 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO78_Msk (0x4000UL)              /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
40295 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO77_Pos (13UL)                  /*!< DSP1N1GPIO77 (Bit 13)                                 */
40296 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO77_Msk (0x2000UL)              /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
40297 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO76_Pos (12UL)                  /*!< DSP1N1GPIO76 (Bit 12)                                 */
40298 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO76_Msk (0x1000UL)              /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
40299 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO75_Pos (11UL)                  /*!< DSP1N1GPIO75 (Bit 11)                                 */
40300 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO75_Msk (0x800UL)               /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
40301 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO74_Pos (10UL)                  /*!< DSP1N1GPIO74 (Bit 10)                                 */
40302 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO74_Msk (0x400UL)               /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
40303 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO73_Pos (9UL)                   /*!< DSP1N1GPIO73 (Bit 9)                                  */
40304 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO73_Msk (0x200UL)               /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
40305 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO72_Pos (8UL)                   /*!< DSP1N1GPIO72 (Bit 8)                                  */
40306 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO72_Msk (0x100UL)               /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
40307 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO71_Pos (7UL)                   /*!< DSP1N1GPIO71 (Bit 7)                                  */
40308 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO71_Msk (0x80UL)                /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
40309 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO70_Pos (6UL)                   /*!< DSP1N1GPIO70 (Bit 6)                                  */
40310 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO70_Msk (0x40UL)                /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
40311 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO69_Pos (5UL)                   /*!< DSP1N1GPIO69 (Bit 5)                                  */
40312 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO69_Msk (0x20UL)                /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
40313 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO68_Pos (4UL)                   /*!< DSP1N1GPIO68 (Bit 4)                                  */
40314 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO68_Msk (0x10UL)                /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
40315 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO67_Pos (3UL)                   /*!< DSP1N1GPIO67 (Bit 3)                                  */
40316 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO67_Msk (0x8UL)                 /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
40317 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO66_Pos (2UL)                   /*!< DSP1N1GPIO66 (Bit 2)                                  */
40318 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO66_Msk (0x4UL)                 /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
40319 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO65_Pos (1UL)                   /*!< DSP1N1GPIO65 (Bit 1)                                  */
40320 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO65_Msk (0x2UL)                 /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
40321 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO64_Pos (0UL)                   /*!< DSP1N1GPIO64 (Bit 0)                                  */
40322 #define GPIO_DSP1N1INT2SET_DSP1N1GPIO64_Msk (0x1UL)                 /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
40323 /* =====================================================  DSP1N1INT3EN  ====================================================== */
40324 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO127_Pos (31UL)                  /*!< DSP1N1GPIO127 (Bit 31)                                */
40325 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO127_Msk (0x80000000UL)          /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
40326 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO126_Pos (30UL)                  /*!< DSP1N1GPIO126 (Bit 30)                                */
40327 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO126_Msk (0x40000000UL)          /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
40328 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO125_Pos (29UL)                  /*!< DSP1N1GPIO125 (Bit 29)                                */
40329 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO125_Msk (0x20000000UL)          /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
40330 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO124_Pos (28UL)                  /*!< DSP1N1GPIO124 (Bit 28)                                */
40331 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO124_Msk (0x10000000UL)          /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
40332 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO123_Pos (27UL)                  /*!< DSP1N1GPIO123 (Bit 27)                                */
40333 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO123_Msk (0x8000000UL)           /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
40334 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO122_Pos (26UL)                  /*!< DSP1N1GPIO122 (Bit 26)                                */
40335 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO122_Msk (0x4000000UL)           /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
40336 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO121_Pos (25UL)                  /*!< DSP1N1GPIO121 (Bit 25)                                */
40337 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO121_Msk (0x2000000UL)           /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
40338 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO120_Pos (24UL)                  /*!< DSP1N1GPIO120 (Bit 24)                                */
40339 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO120_Msk (0x1000000UL)           /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
40340 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO119_Pos (23UL)                  /*!< DSP1N1GPIO119 (Bit 23)                                */
40341 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO119_Msk (0x800000UL)            /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
40342 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO118_Pos (22UL)                  /*!< DSP1N1GPIO118 (Bit 22)                                */
40343 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO118_Msk (0x400000UL)            /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
40344 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO117_Pos (21UL)                  /*!< DSP1N1GPIO117 (Bit 21)                                */
40345 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO117_Msk (0x200000UL)            /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
40346 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO116_Pos (20UL)                  /*!< DSP1N1GPIO116 (Bit 20)                                */
40347 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO116_Msk (0x100000UL)            /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
40348 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO115_Pos (19UL)                  /*!< DSP1N1GPIO115 (Bit 19)                                */
40349 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO115_Msk (0x80000UL)             /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
40350 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO114_Pos (18UL)                  /*!< DSP1N1GPIO114 (Bit 18)                                */
40351 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO114_Msk (0x40000UL)             /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
40352 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO113_Pos (17UL)                  /*!< DSP1N1GPIO113 (Bit 17)                                */
40353 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO113_Msk (0x20000UL)             /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
40354 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO112_Pos (16UL)                  /*!< DSP1N1GPIO112 (Bit 16)                                */
40355 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO112_Msk (0x10000UL)             /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
40356 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO111_Pos (15UL)                  /*!< DSP1N1GPIO111 (Bit 15)                                */
40357 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO111_Msk (0x8000UL)              /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
40358 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO110_Pos (14UL)                  /*!< DSP1N1GPIO110 (Bit 14)                                */
40359 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO110_Msk (0x4000UL)              /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
40360 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO109_Pos (13UL)                  /*!< DSP1N1GPIO109 (Bit 13)                                */
40361 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO109_Msk (0x2000UL)              /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
40362 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO108_Pos (12UL)                  /*!< DSP1N1GPIO108 (Bit 12)                                */
40363 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO108_Msk (0x1000UL)              /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
40364 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO107_Pos (11UL)                  /*!< DSP1N1GPIO107 (Bit 11)                                */
40365 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO107_Msk (0x800UL)               /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
40366 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO106_Pos (10UL)                  /*!< DSP1N1GPIO106 (Bit 10)                                */
40367 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO106_Msk (0x400UL)               /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
40368 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO105_Pos (9UL)                   /*!< DSP1N1GPIO105 (Bit 9)                                 */
40369 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO105_Msk (0x200UL)               /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
40370 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO104_Pos (8UL)                   /*!< DSP1N1GPIO104 (Bit 8)                                 */
40371 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO104_Msk (0x100UL)               /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
40372 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO103_Pos (7UL)                   /*!< DSP1N1GPIO103 (Bit 7)                                 */
40373 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO103_Msk (0x80UL)                /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
40374 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO102_Pos (6UL)                   /*!< DSP1N1GPIO102 (Bit 6)                                 */
40375 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO102_Msk (0x40UL)                /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
40376 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO101_Pos (5UL)                   /*!< DSP1N1GPIO101 (Bit 5)                                 */
40377 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO101_Msk (0x20UL)                /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
40378 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO100_Pos (4UL)                   /*!< DSP1N1GPIO100 (Bit 4)                                 */
40379 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO100_Msk (0x10UL)                /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
40380 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO99_Pos (3UL)                    /*!< DSP1N1GPIO99 (Bit 3)                                  */
40381 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO99_Msk (0x8UL)                  /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
40382 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO98_Pos (2UL)                    /*!< DSP1N1GPIO98 (Bit 2)                                  */
40383 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO98_Msk (0x4UL)                  /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
40384 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO97_Pos (1UL)                    /*!< DSP1N1GPIO97 (Bit 1)                                  */
40385 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO97_Msk (0x2UL)                  /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
40386 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO96_Pos (0UL)                    /*!< DSP1N1GPIO96 (Bit 0)                                  */
40387 #define GPIO_DSP1N1INT3EN_DSP1N1GPIO96_Msk (0x1UL)                  /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
40388 /* ====================================================  DSP1N1INT3STAT  ===================================================== */
40389 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO127_Pos (31UL)                /*!< DSP1N1GPIO127 (Bit 31)                                */
40390 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO127_Msk (0x80000000UL)        /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
40391 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO126_Pos (30UL)                /*!< DSP1N1GPIO126 (Bit 30)                                */
40392 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO126_Msk (0x40000000UL)        /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
40393 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO125_Pos (29UL)                /*!< DSP1N1GPIO125 (Bit 29)                                */
40394 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO125_Msk (0x20000000UL)        /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
40395 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO124_Pos (28UL)                /*!< DSP1N1GPIO124 (Bit 28)                                */
40396 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO124_Msk (0x10000000UL)        /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
40397 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO123_Pos (27UL)                /*!< DSP1N1GPIO123 (Bit 27)                                */
40398 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO123_Msk (0x8000000UL)         /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
40399 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO122_Pos (26UL)                /*!< DSP1N1GPIO122 (Bit 26)                                */
40400 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO122_Msk (0x4000000UL)         /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
40401 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO121_Pos (25UL)                /*!< DSP1N1GPIO121 (Bit 25)                                */
40402 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO121_Msk (0x2000000UL)         /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
40403 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO120_Pos (24UL)                /*!< DSP1N1GPIO120 (Bit 24)                                */
40404 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO120_Msk (0x1000000UL)         /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
40405 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO119_Pos (23UL)                /*!< DSP1N1GPIO119 (Bit 23)                                */
40406 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO119_Msk (0x800000UL)          /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
40407 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO118_Pos (22UL)                /*!< DSP1N1GPIO118 (Bit 22)                                */
40408 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO118_Msk (0x400000UL)          /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
40409 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO117_Pos (21UL)                /*!< DSP1N1GPIO117 (Bit 21)                                */
40410 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO117_Msk (0x200000UL)          /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
40411 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO116_Pos (20UL)                /*!< DSP1N1GPIO116 (Bit 20)                                */
40412 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO116_Msk (0x100000UL)          /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
40413 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO115_Pos (19UL)                /*!< DSP1N1GPIO115 (Bit 19)                                */
40414 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO115_Msk (0x80000UL)           /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
40415 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO114_Pos (18UL)                /*!< DSP1N1GPIO114 (Bit 18)                                */
40416 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO114_Msk (0x40000UL)           /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
40417 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO113_Pos (17UL)                /*!< DSP1N1GPIO113 (Bit 17)                                */
40418 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO113_Msk (0x20000UL)           /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
40419 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO112_Pos (16UL)                /*!< DSP1N1GPIO112 (Bit 16)                                */
40420 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO112_Msk (0x10000UL)           /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
40421 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO111_Pos (15UL)                /*!< DSP1N1GPIO111 (Bit 15)                                */
40422 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO111_Msk (0x8000UL)            /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
40423 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO110_Pos (14UL)                /*!< DSP1N1GPIO110 (Bit 14)                                */
40424 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO110_Msk (0x4000UL)            /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
40425 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO109_Pos (13UL)                /*!< DSP1N1GPIO109 (Bit 13)                                */
40426 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO109_Msk (0x2000UL)            /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
40427 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO108_Pos (12UL)                /*!< DSP1N1GPIO108 (Bit 12)                                */
40428 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO108_Msk (0x1000UL)            /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
40429 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO107_Pos (11UL)                /*!< DSP1N1GPIO107 (Bit 11)                                */
40430 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO107_Msk (0x800UL)             /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
40431 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO106_Pos (10UL)                /*!< DSP1N1GPIO106 (Bit 10)                                */
40432 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO106_Msk (0x400UL)             /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
40433 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO105_Pos (9UL)                 /*!< DSP1N1GPIO105 (Bit 9)                                 */
40434 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO105_Msk (0x200UL)             /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
40435 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO104_Pos (8UL)                 /*!< DSP1N1GPIO104 (Bit 8)                                 */
40436 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO104_Msk (0x100UL)             /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
40437 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO103_Pos (7UL)                 /*!< DSP1N1GPIO103 (Bit 7)                                 */
40438 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO103_Msk (0x80UL)              /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
40439 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO102_Pos (6UL)                 /*!< DSP1N1GPIO102 (Bit 6)                                 */
40440 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO102_Msk (0x40UL)              /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
40441 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO101_Pos (5UL)                 /*!< DSP1N1GPIO101 (Bit 5)                                 */
40442 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO101_Msk (0x20UL)              /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
40443 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO100_Pos (4UL)                 /*!< DSP1N1GPIO100 (Bit 4)                                 */
40444 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO100_Msk (0x10UL)              /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
40445 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO99_Pos (3UL)                  /*!< DSP1N1GPIO99 (Bit 3)                                  */
40446 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO99_Msk (0x8UL)                /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
40447 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO98_Pos (2UL)                  /*!< DSP1N1GPIO98 (Bit 2)                                  */
40448 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO98_Msk (0x4UL)                /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
40449 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO97_Pos (1UL)                  /*!< DSP1N1GPIO97 (Bit 1)                                  */
40450 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO97_Msk (0x2UL)                /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
40451 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO96_Pos (0UL)                  /*!< DSP1N1GPIO96 (Bit 0)                                  */
40452 #define GPIO_DSP1N1INT3STAT_DSP1N1GPIO96_Msk (0x1UL)                /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
40453 /* =====================================================  DSP1N1INT3CLR  ===================================================== */
40454 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO127_Pos (31UL)                 /*!< DSP1N1GPIO127 (Bit 31)                                */
40455 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO127_Msk (0x80000000UL)         /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
40456 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO126_Pos (30UL)                 /*!< DSP1N1GPIO126 (Bit 30)                                */
40457 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO126_Msk (0x40000000UL)         /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
40458 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO125_Pos (29UL)                 /*!< DSP1N1GPIO125 (Bit 29)                                */
40459 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO125_Msk (0x20000000UL)         /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
40460 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO124_Pos (28UL)                 /*!< DSP1N1GPIO124 (Bit 28)                                */
40461 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO124_Msk (0x10000000UL)         /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
40462 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO123_Pos (27UL)                 /*!< DSP1N1GPIO123 (Bit 27)                                */
40463 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO123_Msk (0x8000000UL)          /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
40464 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO122_Pos (26UL)                 /*!< DSP1N1GPIO122 (Bit 26)                                */
40465 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO122_Msk (0x4000000UL)          /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
40466 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO121_Pos (25UL)                 /*!< DSP1N1GPIO121 (Bit 25)                                */
40467 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO121_Msk (0x2000000UL)          /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
40468 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO120_Pos (24UL)                 /*!< DSP1N1GPIO120 (Bit 24)                                */
40469 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO120_Msk (0x1000000UL)          /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
40470 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO119_Pos (23UL)                 /*!< DSP1N1GPIO119 (Bit 23)                                */
40471 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO119_Msk (0x800000UL)           /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
40472 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO118_Pos (22UL)                 /*!< DSP1N1GPIO118 (Bit 22)                                */
40473 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO118_Msk (0x400000UL)           /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
40474 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO117_Pos (21UL)                 /*!< DSP1N1GPIO117 (Bit 21)                                */
40475 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO117_Msk (0x200000UL)           /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
40476 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO116_Pos (20UL)                 /*!< DSP1N1GPIO116 (Bit 20)                                */
40477 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO116_Msk (0x100000UL)           /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
40478 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO115_Pos (19UL)                 /*!< DSP1N1GPIO115 (Bit 19)                                */
40479 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO115_Msk (0x80000UL)            /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
40480 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO114_Pos (18UL)                 /*!< DSP1N1GPIO114 (Bit 18)                                */
40481 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO114_Msk (0x40000UL)            /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
40482 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO113_Pos (17UL)                 /*!< DSP1N1GPIO113 (Bit 17)                                */
40483 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO113_Msk (0x20000UL)            /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
40484 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO112_Pos (16UL)                 /*!< DSP1N1GPIO112 (Bit 16)                                */
40485 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO112_Msk (0x10000UL)            /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
40486 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO111_Pos (15UL)                 /*!< DSP1N1GPIO111 (Bit 15)                                */
40487 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO111_Msk (0x8000UL)             /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
40488 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO110_Pos (14UL)                 /*!< DSP1N1GPIO110 (Bit 14)                                */
40489 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO110_Msk (0x4000UL)             /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
40490 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO109_Pos (13UL)                 /*!< DSP1N1GPIO109 (Bit 13)                                */
40491 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO109_Msk (0x2000UL)             /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
40492 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO108_Pos (12UL)                 /*!< DSP1N1GPIO108 (Bit 12)                                */
40493 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO108_Msk (0x1000UL)             /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
40494 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO107_Pos (11UL)                 /*!< DSP1N1GPIO107 (Bit 11)                                */
40495 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO107_Msk (0x800UL)              /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
40496 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO106_Pos (10UL)                 /*!< DSP1N1GPIO106 (Bit 10)                                */
40497 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO106_Msk (0x400UL)              /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
40498 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO105_Pos (9UL)                  /*!< DSP1N1GPIO105 (Bit 9)                                 */
40499 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO105_Msk (0x200UL)              /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
40500 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO104_Pos (8UL)                  /*!< DSP1N1GPIO104 (Bit 8)                                 */
40501 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO104_Msk (0x100UL)              /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
40502 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO103_Pos (7UL)                  /*!< DSP1N1GPIO103 (Bit 7)                                 */
40503 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO103_Msk (0x80UL)               /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
40504 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO102_Pos (6UL)                  /*!< DSP1N1GPIO102 (Bit 6)                                 */
40505 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO102_Msk (0x40UL)               /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
40506 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO101_Pos (5UL)                  /*!< DSP1N1GPIO101 (Bit 5)                                 */
40507 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO101_Msk (0x20UL)               /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
40508 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO100_Pos (4UL)                  /*!< DSP1N1GPIO100 (Bit 4)                                 */
40509 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO100_Msk (0x10UL)               /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
40510 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO99_Pos (3UL)                   /*!< DSP1N1GPIO99 (Bit 3)                                  */
40511 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO99_Msk (0x8UL)                 /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
40512 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO98_Pos (2UL)                   /*!< DSP1N1GPIO98 (Bit 2)                                  */
40513 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO98_Msk (0x4UL)                 /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
40514 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO97_Pos (1UL)                   /*!< DSP1N1GPIO97 (Bit 1)                                  */
40515 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO97_Msk (0x2UL)                 /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
40516 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO96_Pos (0UL)                   /*!< DSP1N1GPIO96 (Bit 0)                                  */
40517 #define GPIO_DSP1N1INT3CLR_DSP1N1GPIO96_Msk (0x1UL)                 /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
40518 /* =====================================================  DSP1N1INT3SET  ===================================================== */
40519 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO127_Pos (31UL)                 /*!< DSP1N1GPIO127 (Bit 31)                                */
40520 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO127_Msk (0x80000000UL)         /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
40521 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO126_Pos (30UL)                 /*!< DSP1N1GPIO126 (Bit 30)                                */
40522 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO126_Msk (0x40000000UL)         /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
40523 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO125_Pos (29UL)                 /*!< DSP1N1GPIO125 (Bit 29)                                */
40524 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO125_Msk (0x20000000UL)         /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
40525 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO124_Pos (28UL)                 /*!< DSP1N1GPIO124 (Bit 28)                                */
40526 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO124_Msk (0x10000000UL)         /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
40527 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO123_Pos (27UL)                 /*!< DSP1N1GPIO123 (Bit 27)                                */
40528 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO123_Msk (0x8000000UL)          /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
40529 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO122_Pos (26UL)                 /*!< DSP1N1GPIO122 (Bit 26)                                */
40530 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO122_Msk (0x4000000UL)          /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
40531 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO121_Pos (25UL)                 /*!< DSP1N1GPIO121 (Bit 25)                                */
40532 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO121_Msk (0x2000000UL)          /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
40533 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO120_Pos (24UL)                 /*!< DSP1N1GPIO120 (Bit 24)                                */
40534 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO120_Msk (0x1000000UL)          /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
40535 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO119_Pos (23UL)                 /*!< DSP1N1GPIO119 (Bit 23)                                */
40536 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO119_Msk (0x800000UL)           /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
40537 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO118_Pos (22UL)                 /*!< DSP1N1GPIO118 (Bit 22)                                */
40538 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO118_Msk (0x400000UL)           /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
40539 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO117_Pos (21UL)                 /*!< DSP1N1GPIO117 (Bit 21)                                */
40540 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO117_Msk (0x200000UL)           /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
40541 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO116_Pos (20UL)                 /*!< DSP1N1GPIO116 (Bit 20)                                */
40542 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO116_Msk (0x100000UL)           /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
40543 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO115_Pos (19UL)                 /*!< DSP1N1GPIO115 (Bit 19)                                */
40544 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO115_Msk (0x80000UL)            /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
40545 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO114_Pos (18UL)                 /*!< DSP1N1GPIO114 (Bit 18)                                */
40546 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO114_Msk (0x40000UL)            /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
40547 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO113_Pos (17UL)                 /*!< DSP1N1GPIO113 (Bit 17)                                */
40548 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO113_Msk (0x20000UL)            /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
40549 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO112_Pos (16UL)                 /*!< DSP1N1GPIO112 (Bit 16)                                */
40550 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO112_Msk (0x10000UL)            /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
40551 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO111_Pos (15UL)                 /*!< DSP1N1GPIO111 (Bit 15)                                */
40552 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO111_Msk (0x8000UL)             /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
40553 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO110_Pos (14UL)                 /*!< DSP1N1GPIO110 (Bit 14)                                */
40554 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO110_Msk (0x4000UL)             /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
40555 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO109_Pos (13UL)                 /*!< DSP1N1GPIO109 (Bit 13)                                */
40556 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO109_Msk (0x2000UL)             /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
40557 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO108_Pos (12UL)                 /*!< DSP1N1GPIO108 (Bit 12)                                */
40558 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO108_Msk (0x1000UL)             /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
40559 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO107_Pos (11UL)                 /*!< DSP1N1GPIO107 (Bit 11)                                */
40560 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO107_Msk (0x800UL)              /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
40561 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO106_Pos (10UL)                 /*!< DSP1N1GPIO106 (Bit 10)                                */
40562 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO106_Msk (0x400UL)              /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
40563 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO105_Pos (9UL)                  /*!< DSP1N1GPIO105 (Bit 9)                                 */
40564 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO105_Msk (0x200UL)              /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
40565 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO104_Pos (8UL)                  /*!< DSP1N1GPIO104 (Bit 8)                                 */
40566 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO104_Msk (0x100UL)              /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
40567 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO103_Pos (7UL)                  /*!< DSP1N1GPIO103 (Bit 7)                                 */
40568 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO103_Msk (0x80UL)               /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
40569 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO102_Pos (6UL)                  /*!< DSP1N1GPIO102 (Bit 6)                                 */
40570 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO102_Msk (0x40UL)               /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
40571 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO101_Pos (5UL)                  /*!< DSP1N1GPIO101 (Bit 5)                                 */
40572 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO101_Msk (0x20UL)               /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
40573 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO100_Pos (4UL)                  /*!< DSP1N1GPIO100 (Bit 4)                                 */
40574 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO100_Msk (0x10UL)               /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
40575 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO99_Pos (3UL)                   /*!< DSP1N1GPIO99 (Bit 3)                                  */
40576 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO99_Msk (0x8UL)                 /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
40577 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO98_Pos (2UL)                   /*!< DSP1N1GPIO98 (Bit 2)                                  */
40578 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO98_Msk (0x4UL)                 /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
40579 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO97_Pos (1UL)                   /*!< DSP1N1GPIO97 (Bit 1)                                  */
40580 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO97_Msk (0x2UL)                 /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
40581 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO96_Pos (0UL)                   /*!< DSP1N1GPIO96 (Bit 0)                                  */
40582 #define GPIO_DSP1N1INT3SET_DSP1N1GPIO96_Msk (0x1UL)                 /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
40583 
40584 
40585 /* =========================================================================================================================== */
40586 /* ================                                            GPU                                            ================ */
40587 /* =========================================================================================================================== */
40588 
40589 /* =======================================================  TEX0BASE  ======================================================== */
40590 #define GPU_TEX0BASE_Base_Pos             (0UL)                     /*!< Base (Bit 0)                                          */
40591 #define GPU_TEX0BASE_Base_Msk             (0xffffffffUL)            /*!< Base (Bitfield-Mask: 0xffffffff)                      */
40592 /* ======================================================  TEX0STRIDE  ======================================================= */
40593 #define GPU_TEX0STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
40594 #define GPU_TEX0STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
40595 #define GPU_TEX0STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
40596 #define GPU_TEX0STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
40597 #define GPU_TEX0STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
40598 #define GPU_TEX0STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
40599 /* ========================================================  TEX0RES  ======================================================== */
40600 #define GPU_TEX0RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
40601 #define GPU_TEX0RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
40602 #define GPU_TEX0RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
40603 #define GPU_TEX0RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
40604 /* =======================================================  TEX1BASE  ======================================================== */
40605 #define GPU_TEX1BASE_Base_Pos             (0UL)                     /*!< Base (Bit 0)                                          */
40606 #define GPU_TEX1BASE_Base_Msk             (0xffffffffUL)            /*!< Base (Bitfield-Mask: 0xffffffff)                      */
40607 /* ======================================================  TEX1STRIDE  ======================================================= */
40608 #define GPU_TEX1STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
40609 #define GPU_TEX1STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
40610 #define GPU_TEX1STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
40611 #define GPU_TEX1STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
40612 #define GPU_TEX1STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
40613 #define GPU_TEX1STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
40614 /* ========================================================  TEX1RES  ======================================================== */
40615 #define GPU_TEX1RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
40616 #define GPU_TEX1RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
40617 #define GPU_TEX1RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
40618 #define GPU_TEX1RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
40619 /* =======================================================  TEX1COLOR  ======================================================= */
40620 #define GPU_TEX1COLOR_ALPHA_Pos           (24UL)                    /*!< ALPHA (Bit 24)                                        */
40621 #define GPU_TEX1COLOR_ALPHA_Msk           (0xff000000UL)            /*!< ALPHA (Bitfield-Mask: 0xff)                           */
40622 #define GPU_TEX1COLOR_BLUE_Pos            (16UL)                    /*!< BLUE (Bit 16)                                         */
40623 #define GPU_TEX1COLOR_BLUE_Msk            (0xff0000UL)              /*!< BLUE (Bitfield-Mask: 0xff)                            */
40624 #define GPU_TEX1COLOR_GREEN_Pos           (8UL)                     /*!< GREEN (Bit 8)                                         */
40625 #define GPU_TEX1COLOR_GREEN_Msk           (0xff00UL)                /*!< GREEN (Bitfield-Mask: 0xff)                           */
40626 #define GPU_TEX1COLOR_RED_Pos             (0UL)                     /*!< RED (Bit 0)                                           */
40627 #define GPU_TEX1COLOR_RED_Msk             (0xffUL)                  /*!< RED (Bitfield-Mask: 0xff)                             */
40628 /* =======================================================  TEX2BASE  ======================================================== */
40629 #define GPU_TEX2BASE_Drawing_Pos          (0UL)                     /*!< Drawing (Bit 0)                                       */
40630 #define GPU_TEX2BASE_Drawing_Msk          (0xffffffffUL)            /*!< Drawing (Bitfield-Mask: 0xffffffff)                   */
40631 /* ======================================================  TEX2STRIDE  ======================================================= */
40632 #define GPU_TEX2STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
40633 #define GPU_TEX2STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
40634 #define GPU_TEX2STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
40635 #define GPU_TEX2STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
40636 #define GPU_TEX2STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
40637 #define GPU_TEX2STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
40638 /* ========================================================  TEX2RES  ======================================================== */
40639 #define GPU_TEX2RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
40640 #define GPU_TEX2RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
40641 #define GPU_TEX2RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
40642 #define GPU_TEX2RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
40643 /* =======================================================  TEX3BASE  ======================================================== */
40644 #define GPU_TEX3BASE_Image_Pos            (0UL)                     /*!< Image (Bit 0)                                         */
40645 #define GPU_TEX3BASE_Image_Msk            (0xffffffffUL)            /*!< Image (Bitfield-Mask: 0xffffffff)                     */
40646 /* ======================================================  TEX3STRIDE  ======================================================= */
40647 #define GPU_TEX3STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
40648 #define GPU_TEX3STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
40649 #define GPU_TEX3STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
40650 #define GPU_TEX3STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
40651 #define GPU_TEX3STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
40652 #define GPU_TEX3STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
40653 /* ========================================================  TEX3RES  ======================================================== */
40654 #define GPU_TEX3RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
40655 #define GPU_TEX3RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
40656 #define GPU_TEX3RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
40657 #define GPU_TEX3RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
40658 /* =========================================================  CGCMD  ========================================================= */
40659 #define GPU_CGCMD_START_Pos               (1UL)                     /*!< START (Bit 1)                                         */
40660 #define GPU_CGCMD_START_Msk               (0x2UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
40661 #define GPU_CGCMD_STOP_Pos                (0UL)                     /*!< STOP (Bit 0)                                          */
40662 #define GPU_CGCMD_STOP_Msk                (0x1UL)                   /*!< STOP (Bitfield-Mask: 0x01)                            */
40663 /* ========================================================  CGCTRL  ========================================================= */
40664 #define GPU_CGCTRL_DISCLKMOD_Pos          (30UL)                    /*!< DISCLKMOD (Bit 30)                                    */
40665 #define GPU_CGCTRL_DISCLKMOD_Msk          (0xc0000000UL)            /*!< DISCLKMOD (Bitfield-Mask: 0x03)                       */
40666 #define GPU_CGCTRL_RSVD1_Pos              (24UL)                    /*!< RSVD1 (Bit 24)                                        */
40667 #define GPU_CGCTRL_RSVD1_Msk              (0x3f000000UL)            /*!< RSVD1 (Bitfield-Mask: 0x3f)                           */
40668 #define GPU_CGCTRL_DISCLKCORE_Pos         (23UL)                    /*!< DISCLKCORE (Bit 23)                                   */
40669 #define GPU_CGCTRL_DISCLKCORE_Msk         (0x800000UL)              /*!< DISCLKCORE (Bitfield-Mask: 0x01)                      */
40670 #define GPU_CGCTRL_RSVD0_Pos              (4UL)                     /*!< RSVD0 (Bit 4)                                         */
40671 #define GPU_CGCTRL_RSVD0_Msk              (0x7ffff0UL)              /*!< RSVD0 (Bitfield-Mask: 0x7ffff)                        */
40672 #define GPU_CGCTRL_DISCLKFRAME_Pos        (2UL)                     /*!< DISCLKFRAME (Bit 2)                                   */
40673 #define GPU_CGCTRL_DISCLKFRAME_Msk        (0xcUL)                   /*!< DISCLKFRAME (Bitfield-Mask: 0x03)                     */
40674 #define GPU_CGCTRL_DISCLKCFG_Pos          (1UL)                     /*!< DISCLKCFG (Bit 1)                                     */
40675 #define GPU_CGCTRL_DISCLKCFG_Msk          (0x2UL)                   /*!< DISCLKCFG (Bitfield-Mask: 0x01)                       */
40676 #define GPU_CGCTRL_DISCLKPROC_Pos         (0UL)                     /*!< DISCLKPROC (Bit 0)                                    */
40677 #define GPU_CGCTRL_DISCLKPROC_Msk         (0x1UL)                   /*!< DISCLKPROC (Bitfield-Mask: 0x01)                      */
40678 /* =====================================================  DIRTYTRIGMIN  ====================================================== */
40679 #define GPU_DIRTYTRIGMIN_DRTYREG_Pos      (0UL)                     /*!< DRTYREG (Bit 0)                                       */
40680 #define GPU_DIRTYTRIGMIN_DRTYREG_Msk      (0xffffffffUL)            /*!< DRTYREG (Bitfield-Mask: 0xffffffff)                   */
40681 /* =====================================================  DIRTYTRIGMAX  ====================================================== */
40682 #define GPU_DIRTYTRIGMAX_DRTYREG_Pos      (0UL)                     /*!< DRTYREG (Bit 0)                                       */
40683 #define GPU_DIRTYTRIGMAX_DRTYREG_Msk      (0xffffffffUL)            /*!< DRTYREG (Bitfield-Mask: 0xffffffff)                   */
40684 /* ========================================================  STATUS  ========================================================= */
40685 #define GPU_STATUS_SYSBSY_Pos             (31UL)                    /*!< SYSBSY (Bit 31)                                       */
40686 #define GPU_STATUS_SYSBSY_Msk             (0x80000000UL)            /*!< SYSBSY (Bitfield-Mask: 0x01)                          */
40687 #define GPU_STATUS_MEMBSY_Pos             (30UL)                    /*!< MEMBSY (Bit 30)                                       */
40688 #define GPU_STATUS_MEMBSY_Msk             (0x40000000UL)            /*!< MEMBSY (Bitfield-Mask: 0x01)                          */
40689 #define GPU_STATUS_CLBSY_Pos              (29UL)                    /*!< CLBSY (Bit 29)                                        */
40690 #define GPU_STATUS_CLBSY_Msk              (0x20000000UL)            /*!< CLBSY (Bitfield-Mask: 0x01)                           */
40691 #define GPU_STATUS_CLPBSY_Pos             (28UL)                    /*!< CLPBSY (Bit 28)                                       */
40692 #define GPU_STATUS_CLPBSY_Msk             (0x10000000UL)            /*!< CLPBSY (Bitfield-Mask: 0x01)                          */
40693 #define GPU_STATUS_RASTBSY_Pos            (24UL)                    /*!< RASTBSY (Bit 24)                                      */
40694 #define GPU_STATUS_RASTBSY_Msk            (0xf000000UL)             /*!< RASTBSY (Bitfield-Mask: 0x0f)                         */
40695 #define GPU_STATUS_DEPTHFIFOBSY_Pos       (16UL)                    /*!< DEPTHFIFOBSY (Bit 16)                                 */
40696 #define GPU_STATUS_DEPTHFIFOBSY_Msk       (0xf0000UL)               /*!< DEPTHFIFOBSY (Bitfield-Mask: 0x0f)                    */
40697 #define GPU_STATUS_RENDERBSY_Pos          (12UL)                    /*!< RENDERBSY (Bit 12)                                    */
40698 #define GPU_STATUS_RENDERBSY_Msk          (0xf000UL)                /*!< RENDERBSY (Bitfield-Mask: 0x0f)                       */
40699 #define GPU_STATUS_TEXTMAPBSY_Pos         (8UL)                     /*!< TEXTMAPBSY (Bit 8)                                    */
40700 #define GPU_STATUS_TEXTMAPBSY_Msk         (0xf00UL)                 /*!< TEXTMAPBSY (Bitfield-Mask: 0x0f)                      */
40701 #define GPU_STATUS_PIPEBSY_Pos            (4UL)                     /*!< PIPEBSY (Bit 4)                                       */
40702 #define GPU_STATUS_PIPEBSY_Msk            (0xf0UL)                  /*!< PIPEBSY (Bitfield-Mask: 0x0f)                         */
40703 #define GPU_STATUS_COREBSY_Pos            (0UL)                     /*!< COREBSY (Bit 0)                                       */
40704 #define GPU_STATUS_COREBSY_Msk            (0xfUL)                   /*!< COREBSY (Bitfield-Mask: 0x0f)                         */
40705 /* ========================================================  BUSCTRL  ======================================================== */
40706 #define GPU_BUSCTRL_BUSCTRL_Pos           (0UL)                     /*!< BUSCTRL (Bit 0)                                       */
40707 #define GPU_BUSCTRL_BUSCTRL_Msk           (0xffffffffUL)            /*!< BUSCTRL (Bitfield-Mask: 0xffffffff)                   */
40708 /* ======================================================  IMEMLDIADDR  ====================================================== */
40709 #define GPU_IMEMLDIADDR_IMEM_Pos          (0UL)                     /*!< IMEM (Bit 0)                                          */
40710 #define GPU_IMEMLDIADDR_IMEM_Msk          (0xffffffffUL)            /*!< IMEM (Bitfield-Mask: 0xffffffff)                      */
40711 /* =====================================================  IMEMLDIDATAHL  ===================================================== */
40712 #define GPU_IMEMLDIDATAHL_IMEM_Pos        (0UL)                     /*!< IMEM (Bit 0)                                          */
40713 #define GPU_IMEMLDIDATAHL_IMEM_Msk        (0xffffffffUL)            /*!< IMEM (Bitfield-Mask: 0xffffffff)                      */
40714 /* =====================================================  IMEMLDIDATAHH  ===================================================== */
40715 #define GPU_IMEMLDIDATAHH_IMEM_Pos        (0UL)                     /*!< IMEM (Bit 0)                                          */
40716 #define GPU_IMEMLDIDATAHH_IMEM_Msk        (0xffffffffUL)            /*!< IMEM (Bitfield-Mask: 0xffffffff)                      */
40717 /* =====================================================  CMDLISTSTATUS  ===================================================== */
40718 #define GPU_CMDLISTSTATUS_LIST_Pos        (0UL)                     /*!< LIST (Bit 0)                                          */
40719 #define GPU_CMDLISTSTATUS_LIST_Msk        (0x1UL)                   /*!< LIST (Bitfield-Mask: 0x01)                            */
40720 /* ====================================================  CMDLISTRINGSTOP  ==================================================== */
40721 #define GPU_CMDLISTRINGSTOP_UPDATEPRT_Pos (0UL)                     /*!< UPDATEPRT (Bit 0)                                     */
40722 #define GPU_CMDLISTRINGSTOP_UPDATEPRT_Msk (0xffffffffUL)            /*!< UPDATEPRT (Bitfield-Mask: 0xffffffff)                 */
40723 /* ======================================================  CMDLISTADDR  ====================================================== */
40724 #define GPU_CMDLISTADDR_BASEPTR_Pos       (0UL)                     /*!< BASEPTR (Bit 0)                                       */
40725 #define GPU_CMDLISTADDR_BASEPTR_Msk       (0xffffffffUL)            /*!< BASEPTR (Bitfield-Mask: 0xffffffff)                   */
40726 /* ======================================================  CMDLISTSIZE  ====================================================== */
40727 #define GPU_CMDLISTSIZE_LISTWORDS_Pos     (0UL)                     /*!< LISTWORDS (Bit 0)                                     */
40728 #define GPU_CMDLISTSIZE_LISTWORDS_Msk     (0xffffffffUL)            /*!< LISTWORDS (Bitfield-Mask: 0xffffffff)                 */
40729 /* =====================================================  INTERRUPTCTRL  ===================================================== */
40730 #define GPU_INTERRUPTCTRL_CHANGEFREQ_Pos  (30UL)                    /*!< CHANGEFREQ (Bit 30)                                   */
40731 #define GPU_INTERRUPTCTRL_CHANGEFREQ_Msk  (0xc0000000UL)            /*!< CHANGEFREQ (Bitfield-Mask: 0x03)                      */
40732 #define GPU_INTERRUPTCTRL_RSVD_Pos        (4UL)                     /*!< RSVD (Bit 4)                                          */
40733 #define GPU_INTERRUPTCTRL_RSVD_Msk        (0x3ffffff0UL)            /*!< RSVD (Bitfield-Mask: 0x3ffffff)                       */
40734 #define GPU_INTERRUPTCTRL_AUTOCLR_Pos     (3UL)                     /*!< AUTOCLR (Bit 3)                                       */
40735 #define GPU_INTERRUPTCTRL_AUTOCLR_Msk     (0x8UL)                   /*!< AUTOCLR (Bitfield-Mask: 0x01)                         */
40736 #define GPU_INTERRUPTCTRL_INTDRAWEND_Pos  (2UL)                     /*!< INTDRAWEND (Bit 2)                                    */
40737 #define GPU_INTERRUPTCTRL_INTDRAWEND_Msk  (0x4UL)                   /*!< INTDRAWEND (Bitfield-Mask: 0x01)                      */
40738 #define GPU_INTERRUPTCTRL_INTCMDEND_Pos   (1UL)                     /*!< INTCMDEND (Bit 1)                                     */
40739 #define GPU_INTERRUPTCTRL_INTCMDEND_Msk   (0x2UL)                   /*!< INTCMDEND (Bitfield-Mask: 0x01)                       */
40740 #define GPU_INTERRUPTCTRL_IRQACTIVE_Pos   (0UL)                     /*!< IRQACTIVE (Bit 0)                                     */
40741 #define GPU_INTERRUPTCTRL_IRQACTIVE_Msk   (0x1UL)                   /*!< IRQACTIVE (Bitfield-Mask: 0x01)                       */
40742 /* =======================================================  SYSCLEAR  ======================================================== */
40743 #define GPU_SYSCLEAR_RESETGPU_Pos         (0UL)                     /*!< RESETGPU (Bit 0)                                      */
40744 #define GPU_SYSCLEAR_RESETGPU_Msk         (0xffffffffUL)            /*!< RESETGPU (Bitfield-Mask: 0xffffffff)                  */
40745 /* ========================================================  DRAWCMD  ======================================================== */
40746 #define GPU_DRAWCMD_RSVD_Pos              (3UL)                     /*!< RSVD (Bit 3)                                          */
40747 #define GPU_DRAWCMD_RSVD_Msk              (0xfffffff8UL)            /*!< RSVD (Bitfield-Mask: 0x1fffffff)                      */
40748 #define GPU_DRAWCMD_START_Pos             (0UL)                     /*!< START (Bit 0)                                         */
40749 #define GPU_DRAWCMD_START_Msk             (0x7UL)                   /*!< START (Bitfield-Mask: 0x07)                           */
40750 /* ========================================================  DRAWPT0  ======================================================== */
40751 #define GPU_DRAWPT0_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
40752 #define GPU_DRAWPT0_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
40753 #define GPU_DRAWPT0_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
40754 #define GPU_DRAWPT0_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
40755 /* ========================================================  DRAWPT1  ======================================================== */
40756 #define GPU_DRAWPT1_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
40757 #define GPU_DRAWPT1_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
40758 #define GPU_DRAWPT1_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
40759 #define GPU_DRAWPT1_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
40760 /* ========================================================  CLIPMIN  ======================================================== */
40761 #define GPU_CLIPMIN_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
40762 #define GPU_CLIPMIN_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
40763 #define GPU_CLIPMIN_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
40764 #define GPU_CLIPMIN_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
40765 /* ========================================================  CLIPMAX  ======================================================== */
40766 #define GPU_CLIPMAX_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
40767 #define GPU_CLIPMAX_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
40768 #define GPU_CLIPMAX_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
40769 #define GPU_CLIPMAX_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
40770 /* =======================================================  RASTCTRL  ======================================================== */
40771 #define GPU_RASTCTRL_PERSP_Pos            (30UL)                    /*!< PERSP (Bit 30)                                        */
40772 #define GPU_RASTCTRL_PERSP_Msk            (0xc0000000UL)            /*!< PERSP (Bitfield-Mask: 0x03)                           */
40773 #define GPU_RASTCTRL_ADD_Pos              (29UL)                    /*!< ADD (Bit 29)                                          */
40774 #define GPU_RASTCTRL_ADD_Msk              (0x20000000UL)            /*!< ADD (Bitfield-Mask: 0x01)                             */
40775 #define GPU_RASTCTRL_BYPASS_Pos           (28UL)                    /*!< BYPASS (Bit 28)                                       */
40776 #define GPU_RASTCTRL_BYPASS_Msk           (0x10000000UL)            /*!< BYPASS (Bitfield-Mask: 0x01)                          */
40777 #define GPU_RASTCTRL_RSVD_Pos             (0UL)                     /*!< RSVD (Bit 0)                                          */
40778 #define GPU_RASTCTRL_RSVD_Msk             (0xfffffffUL)             /*!< RSVD (Bitfield-Mask: 0xfffffff)                       */
40779 /* ======================================================  DRAWCODEPTR  ====================================================== */
40780 #define GPU_DRAWCODEPTR_BKGND_Pos         (16UL)                    /*!< BKGND (Bit 16)                                        */
40781 #define GPU_DRAWCODEPTR_BKGND_Msk         (0xffff0000UL)            /*!< BKGND (Bitfield-Mask: 0xffff)                         */
40782 #define GPU_DRAWCODEPTR_FRGND_Pos         (0UL)                     /*!< FRGND (Bit 0)                                         */
40783 #define GPU_DRAWCODEPTR_FRGND_Msk         (0xffffUL)                /*!< FRGND (Bitfield-Mask: 0xffff)                         */
40784 /* =======================================================  DRAWPT0X  ======================================================== */
40785 #define GPU_DRAWPT0X_DRAW0X_Pos           (0UL)                     /*!< DRAW0X (Bit 0)                                        */
40786 #define GPU_DRAWPT0X_DRAW0X_Msk           (0xffffffffUL)            /*!< DRAW0X (Bitfield-Mask: 0xffffffff)                    */
40787 /* =======================================================  DRAWPT0Y  ======================================================== */
40788 #define GPU_DRAWPT0Y_DRAW0Y_Pos           (0UL)                     /*!< DRAW0Y (Bit 0)                                        */
40789 #define GPU_DRAWPT0Y_DRAW0Y_Msk           (0xffffffffUL)            /*!< DRAW0Y (Bitfield-Mask: 0xffffffff)                    */
40790 /* =======================================================  DRAWPT0Z  ======================================================== */
40791 #define GPU_DRAWPT0Z_DRAW0Z_Pos           (0UL)                     /*!< DRAW0Z (Bit 0)                                        */
40792 #define GPU_DRAWPT0Z_DRAW0Z_Msk           (0xffffffffUL)            /*!< DRAW0Z (Bitfield-Mask: 0xffffffff)                    */
40793 /* =======================================================  DRAWCOLOR  ======================================================= */
40794 #define GPU_DRAWCOLOR_RASTPRIM_Pos        (0UL)                     /*!< RASTPRIM (Bit 0)                                      */
40795 #define GPU_DRAWCOLOR_RASTPRIM_Msk        (0xffffffffUL)            /*!< RASTPRIM (Bitfield-Mask: 0xffffffff)                  */
40796 /* =======================================================  DRAWPT1X  ======================================================== */
40797 #define GPU_DRAWPT1X_DRAW1X_Pos           (0UL)                     /*!< DRAW1X (Bit 0)                                        */
40798 #define GPU_DRAWPT1X_DRAW1X_Msk           (0xffffffffUL)            /*!< DRAW1X (Bitfield-Mask: 0xffffffff)                    */
40799 /* =======================================================  DRAWPT1Y  ======================================================== */
40800 #define GPU_DRAWPT1Y_DRAW1Y_Pos           (0UL)                     /*!< DRAW1Y (Bit 0)                                        */
40801 #define GPU_DRAWPT1Y_DRAW1Y_Msk           (0xffffffffUL)            /*!< DRAW1Y (Bitfield-Mask: 0xffffffff)                    */
40802 /* =======================================================  DRAWPT1Z  ======================================================== */
40803 #define GPU_DRAWPT1Z_DRAW1Z_Pos           (0UL)                     /*!< DRAW1Z (Bit 0)                                        */
40804 #define GPU_DRAWPT1Z_DRAW1Z_Msk           (0xffffffffUL)            /*!< DRAW1Z (Bitfield-Mask: 0xffffffff)                    */
40805 /* =======================================================  DRAWPT2X  ======================================================== */
40806 #define GPU_DRAWPT2X_DRAW2X_Pos           (0UL)                     /*!< DRAW2X (Bit 0)                                        */
40807 #define GPU_DRAWPT2X_DRAW2X_Msk           (0xffffffffUL)            /*!< DRAW2X (Bitfield-Mask: 0xffffffff)                    */
40808 /* =======================================================  DRAWPT2Y  ======================================================== */
40809 #define GPU_DRAWPT2Y_DRAW2Y_Pos           (0UL)                     /*!< DRAW2Y (Bit 0)                                        */
40810 #define GPU_DRAWPT2Y_DRAW2Y_Msk           (0xffffffffUL)            /*!< DRAW2Y (Bitfield-Mask: 0xffffffff)                    */
40811 /* =======================================================  DRAWPT2Z  ======================================================== */
40812 #define GPU_DRAWPT2Z_RSVD_Pos             (0UL)                     /*!< RSVD (Bit 0)                                          */
40813 #define GPU_DRAWPT2Z_RSVD_Msk             (0xffffffffUL)            /*!< RSVD (Bitfield-Mask: 0xffffffff)                      */
40814 /* =======================================================  DRAWPT3X  ======================================================== */
40815 #define GPU_DRAWPT3X_DRAW3X_Pos           (0UL)                     /*!< DRAW3X (Bit 0)                                        */
40816 #define GPU_DRAWPT3X_DRAW3X_Msk           (0xffffffffUL)            /*!< DRAW3X (Bitfield-Mask: 0xffffffff)                    */
40817 /* =======================================================  DRAWPT3Y  ======================================================== */
40818 #define GPU_DRAWPT3Y_DRAW3Y_Pos           (0UL)                     /*!< DRAW3Y (Bit 0)                                        */
40819 #define GPU_DRAWPT3Y_DRAW3Y_Msk           (0xffffffffUL)            /*!< DRAW3Y (Bitfield-Mask: 0xffffffff)                    */
40820 /* =======================================================  DRAWPT3Z  ======================================================== */
40821 #define GPU_DRAWPT3Z_DRAW3Z_Pos           (0UL)                     /*!< DRAW3Z (Bit 0)                                        */
40822 #define GPU_DRAWPT3Z_DRAW3Z_Msk           (0xffffffffUL)            /*!< DRAW3Z (Bitfield-Mask: 0xffffffff)                    */
40823 /* =========================================================  MM00  ========================================================== */
40824 #define GPU_MM00_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40825 #define GPU_MM00_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40826 /* =========================================================  MM01  ========================================================== */
40827 #define GPU_MM01_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40828 #define GPU_MM01_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40829 /* =========================================================  MM02  ========================================================== */
40830 #define GPU_MM02_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40831 #define GPU_MM02_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40832 /* =========================================================  MM10  ========================================================== */
40833 #define GPU_MM10_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40834 #define GPU_MM10_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40835 /* =========================================================  MM11  ========================================================== */
40836 #define GPU_MM11_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40837 #define GPU_MM11_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40838 /* =========================================================  MM12  ========================================================== */
40839 #define GPU_MM12_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40840 #define GPU_MM12_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40841 /* =========================================================  MM20  ========================================================== */
40842 #define GPU_MM20_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40843 #define GPU_MM20_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40844 /* =========================================================  MM21  ========================================================== */
40845 #define GPU_MM21_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40846 #define GPU_MM21_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40847 /* =========================================================  MM22  ========================================================== */
40848 #define GPU_MM22_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
40849 #define GPU_MM22_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
40850 /* ======================================================  DEPTHSTARTL  ====================================================== */
40851 #define GPU_DEPTHSTARTL_DEPTH32LO_Pos     (0UL)                     /*!< DEPTH32LO (Bit 0)                                     */
40852 #define GPU_DEPTHSTARTL_DEPTH32LO_Msk     (0xffffffffUL)            /*!< DEPTH32LO (Bitfield-Mask: 0xffffffff)                 */
40853 /* ======================================================  DEPTHSTARTH  ====================================================== */
40854 #define GPU_DEPTHSTARTH_DEPTH32HI_Pos     (0UL)                     /*!< DEPTH32HI (Bit 0)                                     */
40855 #define GPU_DEPTHSTARTH_DEPTH32HI_Msk     (0xffffffffUL)            /*!< DEPTH32HI (Bitfield-Mask: 0xffffffff)                 */
40856 /* =======================================================  DEPTHDXL  ======================================================== */
40857 #define GPU_DEPTHDXL_XAXISLO_Pos          (0UL)                     /*!< XAXISLO (Bit 0)                                       */
40858 #define GPU_DEPTHDXL_XAXISLO_Msk          (0xffffffffUL)            /*!< XAXISLO (Bitfield-Mask: 0xffffffff)                   */
40859 /* =======================================================  DEPTHDXH  ======================================================== */
40860 #define GPU_DEPTHDXH_XAXISHI_Pos          (0UL)                     /*!< XAXISHI (Bit 0)                                       */
40861 #define GPU_DEPTHDXH_XAXISHI_Msk          (0xffffffffUL)            /*!< XAXISHI (Bitfield-Mask: 0xffffffff)                   */
40862 /* =======================================================  DEPTHDYL  ======================================================== */
40863 #define GPU_DEPTHDYL_YAXISLO_Pos          (0UL)                     /*!< YAXISLO (Bit 0)                                       */
40864 #define GPU_DEPTHDYL_YAXISLO_Msk          (0xffffffffUL)            /*!< YAXISLO (Bitfield-Mask: 0xffffffff)                   */
40865 /* =======================================================  DEPTHDYH  ======================================================== */
40866 #define GPU_DEPTHDYH_YAXISHI_Pos          (0UL)                     /*!< YAXISHI (Bit 0)                                       */
40867 #define GPU_DEPTHDYH_YAXISHI_Msk          (0xffffffffUL)            /*!< YAXISHI (Bitfield-Mask: 0xffffffff)                   */
40868 /* =========================================================  REDX  ========================================================== */
40869 #define GPU_REDX_REDX_Pos                 (0UL)                     /*!< REDX (Bit 0)                                          */
40870 #define GPU_REDX_REDX_Msk                 (0xffffffffUL)            /*!< REDX (Bitfield-Mask: 0xffffffff)                      */
40871 /* =========================================================  REDY  ========================================================== */
40872 #define GPU_REDY_REDY_Pos                 (0UL)                     /*!< REDY (Bit 0)                                          */
40873 #define GPU_REDY_REDY_Msk                 (0xffffffffUL)            /*!< REDY (Bitfield-Mask: 0xffffffff)                      */
40874 /* ========================================================  GREENX  ========================================================= */
40875 #define GPU_GREENX_GREENX_Pos             (0UL)                     /*!< GREENX (Bit 0)                                        */
40876 #define GPU_GREENX_GREENX_Msk             (0xffffffffUL)            /*!< GREENX (Bitfield-Mask: 0xffffffff)                    */
40877 /* ========================================================  GREENY  ========================================================= */
40878 #define GPU_GREENY_GREENY_Pos             (0UL)                     /*!< GREENY (Bit 0)                                        */
40879 #define GPU_GREENY_GREENY_Msk             (0xffffffffUL)            /*!< GREENY (Bitfield-Mask: 0xffffffff)                    */
40880 /* =========================================================  BLUEX  ========================================================= */
40881 #define GPU_BLUEX_BLUEX_Pos               (0UL)                     /*!< BLUEX (Bit 0)                                         */
40882 #define GPU_BLUEX_BLUEX_Msk               (0xffffffffUL)            /*!< BLUEX (Bitfield-Mask: 0xffffffff)                     */
40883 /* =========================================================  BLUEY  ========================================================= */
40884 #define GPU_BLUEY_BLUEY_Pos               (0UL)                     /*!< BLUEY (Bit 0)                                         */
40885 #define GPU_BLUEY_BLUEY_Msk               (0xffffffffUL)            /*!< BLUEY (Bitfield-Mask: 0xffffffff)                     */
40886 /* =========================================================  ALFX  ========================================================== */
40887 #define GPU_ALFX_ALFX_Pos                 (0UL)                     /*!< ALFX (Bit 0)                                          */
40888 #define GPU_ALFX_ALFX_Msk                 (0xffffffffUL)            /*!< ALFX (Bitfield-Mask: 0xffffffff)                      */
40889 /* =========================================================  ALFY  ========================================================== */
40890 #define GPU_ALFY_ALFY_Pos                 (0UL)                     /*!< ALFY (Bit 0)                                          */
40891 #define GPU_ALFY_ALFY_Msk                 (0xffffffffUL)            /*!< ALFY (Bitfield-Mask: 0xffffffff)                      */
40892 /* ========================================================  REDINIT  ======================================================== */
40893 #define GPU_REDINIT_REDXY_Pos             (0UL)                     /*!< REDXY (Bit 0)                                         */
40894 #define GPU_REDINIT_REDXY_Msk             (0xffffffffUL)            /*!< REDXY (Bitfield-Mask: 0xffffffff)                     */
40895 /* ========================================================  GREINIT  ======================================================== */
40896 #define GPU_GREINIT_GREENXY_Pos           (0UL)                     /*!< GREENXY (Bit 0)                                       */
40897 #define GPU_GREINIT_GREENXY_Msk           (0xffffffffUL)            /*!< GREENXY (Bitfield-Mask: 0xffffffff)                   */
40898 /* ========================================================  BLUINIT  ======================================================== */
40899 #define GPU_BLUINIT_BLUEXY_Pos            (0UL)                     /*!< BLUEXY (Bit 0)                                        */
40900 #define GPU_BLUINIT_BLUEXY_Msk            (0xffffffffUL)            /*!< BLUEXY (Bitfield-Mask: 0xffffffff)                    */
40901 /* ========================================================  ALFINIT  ======================================================== */
40902 #define GPU_ALFINIT_ALFXY_Pos             (0UL)                     /*!< ALFXY (Bit 0)                                         */
40903 #define GPU_ALFINIT_ALFXY_Msk             (0xffffffffUL)            /*!< ALFXY (Bitfield-Mask: 0xffffffff)                     */
40904 /* =========================================================  IDREG  ========================================================= */
40905 #define GPU_IDREG_GPUID_Pos               (0UL)                     /*!< GPUID (Bit 0)                                         */
40906 #define GPU_IDREG_GPUID_Msk               (0xffffffffUL)            /*!< GPUID (Bitfield-Mask: 0xffffffff)                     */
40907 /* =======================================================  LOADCTRL  ======================================================== */
40908 #define GPU_LOADCTRL_LOADCTRL_Pos         (0UL)                     /*!< LOADCTRL (Bit 0)                                      */
40909 #define GPU_LOADCTRL_LOADCTRL_Msk         (0xffffffffUL)            /*!< LOADCTRL (Bitfield-Mask: 0xffffffff)                  */
40910 /* =========================================================  C0REG  ========================================================= */
40911 #define GPU_C0REG_C0SHADER_Pos            (0UL)                     /*!< C0SHADER (Bit 0)                                      */
40912 #define GPU_C0REG_C0SHADER_Msk            (0xffffffffUL)            /*!< C0SHADER (Bitfield-Mask: 0xffffffff)                  */
40913 /* =========================================================  C1REG  ========================================================= */
40914 #define GPU_C1REG_C1SHADER_Pos            (0UL)                     /*!< C1SHADER (Bit 0)                                      */
40915 #define GPU_C1REG_C1SHADER_Msk            (0xffffffffUL)            /*!< C1SHADER (Bitfield-Mask: 0xffffffff)                  */
40916 /* =========================================================  C2REG  ========================================================= */
40917 #define GPU_C2REG_C2SHADER_Pos            (0UL)                     /*!< C2SHADER (Bit 0)                                      */
40918 #define GPU_C2REG_C2SHADER_Msk            (0xffffffffUL)            /*!< C2SHADER (Bitfield-Mask: 0xffffffff)                  */
40919 /* =========================================================  C3REG  ========================================================= */
40920 #define GPU_C3REG_C3SHADER_Pos            (0UL)                     /*!< C3SHADER (Bit 0)                                      */
40921 #define GPU_C3REG_C3SHADER_Msk            (0xffffffffUL)            /*!< C3SHADER (Bitfield-Mask: 0xffffffff)                  */
40922 /* =========================================================  IRQID  ========================================================= */
40923 #define GPU_IRQID_IRQID_Pos               (0UL)                     /*!< IRQID (Bit 0)                                         */
40924 #define GPU_IRQID_IRQID_Msk               (0xffffffffUL)            /*!< IRQID (Bitfield-Mask: 0xffffffff)                     */
40925 
40926 
40927 /* =========================================================================================================================== */
40928 /* ================                                           I2S0                                            ================ */
40929 /* =========================================================================================================================== */
40930 
40931 /* ========================================================  RXDATA  ========================================================= */
40932 #define I2S0_RXDATA_RXSAMPLE_Pos          (0UL)                     /*!< RXSAMPLE (Bit 0)                                      */
40933 #define I2S0_RXDATA_RXSAMPLE_Msk          (0xffffffffUL)            /*!< RXSAMPLE (Bitfield-Mask: 0xffffffff)                  */
40934 /* =======================================================  RXCHANID  ======================================================== */
40935 #define I2S0_RXCHANID_RXCHANID_Pos        (0UL)                     /*!< RXCHANID (Bit 0)                                      */
40936 #define I2S0_RXCHANID_RXCHANID_Msk        (0xffUL)                  /*!< RXCHANID (Bitfield-Mask: 0xff)                        */
40937 /* =====================================================  RXFIFOSTATUS  ====================================================== */
40938 #define I2S0_RXFIFOSTATUS_RXEMPTY_Pos     (28UL)                    /*!< RXEMPTY (Bit 28)                                      */
40939 #define I2S0_RXFIFOSTATUS_RXEMPTY_Msk     (0x10000000UL)            /*!< RXEMPTY (Bitfield-Mask: 0x01)                         */
40940 #define I2S0_RXFIFOSTATUS_RXSAMPLECNT_Pos (0UL)                     /*!< RXSAMPLECNT (Bit 0)                                   */
40941 #define I2S0_RXFIFOSTATUS_RXSAMPLECNT_Msk (0xfffffffUL)             /*!< RXSAMPLECNT (Bitfield-Mask: 0xfffffff)                */
40942 /* ======================================================  RXFIFOSIZE  ======================================================= */
40943 #define I2S0_RXFIFOSIZE_SIZE_Pos          (0UL)                     /*!< SIZE (Bit 0)                                          */
40944 #define I2S0_RXFIFOSIZE_SIZE_Msk          (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
40945 /* =====================================================  RXUPPERLIMIT  ====================================================== */
40946 #define I2S0_RXUPPERLIMIT_SIZE_Pos        (0UL)                     /*!< SIZE (Bit 0)                                          */
40947 #define I2S0_RXUPPERLIMIT_SIZE_Msk        (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
40948 /* ========================================================  TXDATA  ========================================================= */
40949 #define I2S0_TXDATA_TXSAMPLE_Pos          (0UL)                     /*!< TXSAMPLE (Bit 0)                                      */
40950 #define I2S0_TXDATA_TXSAMPLE_Msk          (0xffffffffUL)            /*!< TXSAMPLE (Bitfield-Mask: 0xffffffff)                  */
40951 /* =======================================================  TXCHANID  ======================================================== */
40952 #define I2S0_TXCHANID_TXCHANID_Pos        (0UL)                     /*!< TXCHANID (Bit 0)                                      */
40953 #define I2S0_TXCHANID_TXCHANID_Msk        (0xffUL)                  /*!< TXCHANID (Bitfield-Mask: 0xff)                        */
40954 /* =====================================================  TXFIFOSTATUS  ====================================================== */
40955 #define I2S0_TXFIFOSTATUS_TXFIFOFULL_Pos  (28UL)                    /*!< TXFIFOFULL (Bit 28)                                   */
40956 #define I2S0_TXFIFOSTATUS_TXFIFOFULL_Msk  (0x10000000UL)            /*!< TXFIFOFULL (Bitfield-Mask: 0x01)                      */
40957 #define I2S0_TXFIFOSTATUS_TXFIFOCNT_Pos   (0UL)                     /*!< TXFIFOCNT (Bit 0)                                     */
40958 #define I2S0_TXFIFOSTATUS_TXFIFOCNT_Msk   (0xfffffffUL)             /*!< TXFIFOCNT (Bitfield-Mask: 0xfffffff)                  */
40959 /* ======================================================  TXFIFOSIZE  ======================================================= */
40960 #define I2S0_TXFIFOSIZE_SIZE_Pos          (0UL)                     /*!< SIZE (Bit 0)                                          */
40961 #define I2S0_TXFIFOSIZE_SIZE_Msk          (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
40962 /* =====================================================  TXLOWERLIMIT  ====================================================== */
40963 #define I2S0_TXLOWERLIMIT_SIZE_Pos        (0UL)                     /*!< SIZE (Bit 0)                                          */
40964 #define I2S0_TXLOWERLIMIT_SIZE_Msk        (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
40965 /* ======================================================  I2SDATACFG  ======================================================= */
40966 #define I2S0_I2SDATACFG_PH_Pos            (31UL)                    /*!< PH (Bit 31)                                           */
40967 #define I2S0_I2SDATACFG_PH_Msk            (0x80000000UL)            /*!< PH (Bitfield-Mask: 0x01)                              */
40968 #define I2S0_I2SDATACFG_FRLEN2_Pos        (24UL)                    /*!< FRLEN2 (Bit 24)                                       */
40969 #define I2S0_I2SDATACFG_FRLEN2_Msk        (0x7f000000UL)            /*!< FRLEN2 (Bitfield-Mask: 0x7f)                          */
40970 #define I2S0_I2SDATACFG_WDLEN2_Pos        (21UL)                    /*!< WDLEN2 (Bit 21)                                       */
40971 #define I2S0_I2SDATACFG_WDLEN2_Msk        (0xe00000UL)              /*!< WDLEN2 (Bitfield-Mask: 0x07)                          */
40972 #define I2S0_I2SDATACFG_DATADLY_Pos       (19UL)                    /*!< DATADLY (Bit 19)                                      */
40973 #define I2S0_I2SDATACFG_DATADLY_Msk       (0x180000UL)              /*!< DATADLY (Bitfield-Mask: 0x03)                         */
40974 #define I2S0_I2SDATACFG_SSZ2_Pos          (16UL)                    /*!< SSZ2 (Bit 16)                                         */
40975 #define I2S0_I2SDATACFG_SSZ2_Msk          (0x70000UL)               /*!< SSZ2 (Bitfield-Mask: 0x07)                            */
40976 #define I2S0_I2SDATACFG_FRLEN1_Pos        (8UL)                     /*!< FRLEN1 (Bit 8)                                        */
40977 #define I2S0_I2SDATACFG_FRLEN1_Msk        (0x7f00UL)                /*!< FRLEN1 (Bitfield-Mask: 0x7f)                          */
40978 #define I2S0_I2SDATACFG_WDLEN1_Pos        (5UL)                     /*!< WDLEN1 (Bit 5)                                        */
40979 #define I2S0_I2SDATACFG_WDLEN1_Msk        (0xe0UL)                  /*!< WDLEN1 (Bitfield-Mask: 0x07)                          */
40980 #define I2S0_I2SDATACFG_JUST_Pos          (3UL)                     /*!< JUST (Bit 3)                                          */
40981 #define I2S0_I2SDATACFG_JUST_Msk          (0x8UL)                   /*!< JUST (Bitfield-Mask: 0x01)                            */
40982 #define I2S0_I2SDATACFG_SSZ1_Pos          (0UL)                     /*!< SSZ1 (Bit 0)                                          */
40983 #define I2S0_I2SDATACFG_SSZ1_Msk          (0x7UL)                   /*!< SSZ1 (Bitfield-Mask: 0x07)                            */
40984 /* =======================================================  I2SIOCFG  ======================================================== */
40985 #define I2S0_I2SIOCFG_FWID_Pos            (20UL)                    /*!< FWID (Bit 20)                                         */
40986 #define I2S0_I2SIOCFG_FWID_Msk            (0xff00000UL)             /*!< FWID (Bitfield-Mask: 0xff)                            */
40987 #define I2S0_I2SIOCFG_PRx_Pos             (19UL)                    /*!< PRx (Bit 19)                                          */
40988 #define I2S0_I2SIOCFG_PRx_Msk             (0x80000UL)               /*!< PRx (Bitfield-Mask: 0x01)                             */
40989 #define I2S0_I2SIOCFG_MSL_Pos             (18UL)                    /*!< MSL (Bit 18)                                          */
40990 #define I2S0_I2SIOCFG_MSL_Msk             (0x40000UL)               /*!< MSL (Bitfield-Mask: 0x01)                             */
40991 #define I2S0_I2SIOCFG_PRTX_Pos            (17UL)                    /*!< PRTX (Bit 17)                                         */
40992 #define I2S0_I2SIOCFG_PRTX_Msk            (0x20000UL)               /*!< PRTX (Bitfield-Mask: 0x01)                            */
40993 #define I2S0_I2SIOCFG_FSP_Pos             (16UL)                    /*!< FSP (Bit 16)                                          */
40994 #define I2S0_I2SIOCFG_FSP_Msk             (0x10000UL)               /*!< FSP (Bitfield-Mask: 0x01)                             */
40995 #define I2S0_I2SIOCFG_FPER_Pos            (4UL)                     /*!< FPER (Bit 4)                                          */
40996 #define I2S0_I2SIOCFG_FPER_Msk            (0xfff0UL)                /*!< FPER (Bitfield-Mask: 0xfff)                           */
40997 #define I2S0_I2SIOCFG_OEN_Pos             (0UL)                     /*!< OEN (Bit 0)                                           */
40998 #define I2S0_I2SIOCFG_OEN_Msk             (0x1UL)                   /*!< OEN (Bitfield-Mask: 0x01)                             */
40999 /* ========================================================  I2SCTL  ========================================================= */
41000 #define I2S0_I2SCTL_I2SVAL_Pos            (31UL)                    /*!< I2SVAL (Bit 31)                                       */
41001 #define I2S0_I2SCTL_I2SVAL_Msk            (0x80000000UL)            /*!< I2SVAL (Bitfield-Mask: 0x01)                          */
41002 #define I2S0_I2SCTL_RXRST_Pos             (5UL)                     /*!< RXRST (Bit 5)                                         */
41003 #define I2S0_I2SCTL_RXRST_Msk             (0x20UL)                  /*!< RXRST (Bitfield-Mask: 0x01)                           */
41004 #define I2S0_I2SCTL_RXEN_Pos              (4UL)                     /*!< RXEN (Bit 4)                                          */
41005 #define I2S0_I2SCTL_RXEN_Msk              (0x10UL)                  /*!< RXEN (Bitfield-Mask: 0x01)                            */
41006 #define I2S0_I2SCTL_TXRST_Pos             (1UL)                     /*!< TXRST (Bit 1)                                         */
41007 #define I2S0_I2SCTL_TXRST_Msk             (0x2UL)                   /*!< TXRST (Bitfield-Mask: 0x01)                           */
41008 #define I2S0_I2SCTL_TXEN_Pos              (0UL)                     /*!< TXEN (Bit 0)                                          */
41009 #define I2S0_I2SCTL_TXEN_Msk              (0x1UL)                   /*!< TXEN (Bitfield-Mask: 0x01)                            */
41010 /* ========================================================  IPBIRPT  ======================================================== */
41011 #define I2S0_IPBIRPT_TXDMAI_Pos           (21UL)                    /*!< TXDMAI (Bit 21)                                       */
41012 #define I2S0_IPBIRPT_TXDMAI_Msk           (0x200000UL)              /*!< TXDMAI (Bitfield-Mask: 0x01)                          */
41013 #define I2S0_IPBIRPT_RXDMAI_Pos           (20UL)                    /*!< RXDMAI (Bit 20)                                       */
41014 #define I2S0_IPBIRPT_RXDMAI_Msk           (0x100000UL)              /*!< RXDMAI (Bitfield-Mask: 0x01)                          */
41015 #define I2S0_IPBIRPT_TXEI_Pos             (19UL)                    /*!< TXEI (Bit 19)                                         */
41016 #define I2S0_IPBIRPT_TXEI_Msk             (0x80000UL)               /*!< TXEI (Bitfield-Mask: 0x01)                            */
41017 #define I2S0_IPBIRPT_RXFI_Pos             (18UL)                    /*!< RXFI (Bit 18)                                         */
41018 #define I2S0_IPBIRPT_RXFI_Msk             (0x40000UL)               /*!< RXFI (Bitfield-Mask: 0x01)                            */
41019 #define I2S0_IPBIRPT_TXFFI_Pos            (17UL)                    /*!< TXFFI (Bit 17)                                        */
41020 #define I2S0_IPBIRPT_TXFFI_Msk            (0x20000UL)               /*!< TXFFI (Bitfield-Mask: 0x01)                           */
41021 #define I2S0_IPBIRPT_RXFFI_Pos            (16UL)                    /*!< RXFFI (Bit 16)                                        */
41022 #define I2S0_IPBIRPT_RXFFI_Msk            (0x10000UL)               /*!< RXFFI (Bitfield-Mask: 0x01)                           */
41023 #define I2S0_IPBIRPT_TXDMAM_Pos           (5UL)                     /*!< TXDMAM (Bit 5)                                        */
41024 #define I2S0_IPBIRPT_TXDMAM_Msk           (0x20UL)                  /*!< TXDMAM (Bitfield-Mask: 0x01)                          */
41025 #define I2S0_IPBIRPT_RXDMAM_Pos           (4UL)                     /*!< RXDMAM (Bit 4)                                        */
41026 #define I2S0_IPBIRPT_RXDMAM_Msk           (0x10UL)                  /*!< RXDMAM (Bitfield-Mask: 0x01)                          */
41027 #define I2S0_IPBIRPT_TXEM_Pos             (3UL)                     /*!< TXEM (Bit 3)                                          */
41028 #define I2S0_IPBIRPT_TXEM_Msk             (0x8UL)                   /*!< TXEM (Bitfield-Mask: 0x01)                            */
41029 #define I2S0_IPBIRPT_RXFM_Pos             (2UL)                     /*!< RXFM (Bit 2)                                          */
41030 #define I2S0_IPBIRPT_RXFM_Msk             (0x4UL)                   /*!< RXFM (Bitfield-Mask: 0x01)                            */
41031 #define I2S0_IPBIRPT_TXFFM_Pos            (1UL)                     /*!< TXFFM (Bit 1)                                         */
41032 #define I2S0_IPBIRPT_TXFFM_Msk            (0x2UL)                   /*!< TXFFM (Bitfield-Mask: 0x01)                           */
41033 #define I2S0_IPBIRPT_RXFFM_Pos            (0UL)                     /*!< RXFFM (Bit 0)                                         */
41034 #define I2S0_IPBIRPT_RXFFM_Msk            (0x1UL)                   /*!< RXFFM (Bitfield-Mask: 0x01)                           */
41035 /* =======================================================  IPCOREID  ======================================================== */
41036 #define I2S0_IPCOREID_COREFAM_Pos         (24UL)                    /*!< COREFAM (Bit 24)                                      */
41037 #define I2S0_IPCOREID_COREFAM_Msk         (0xff000000UL)            /*!< COREFAM (Bitfield-Mask: 0xff)                         */
41038 #define I2S0_IPCOREID_COREID_Pos          (16UL)                    /*!< COREID (Bit 16)                                       */
41039 #define I2S0_IPCOREID_COREID_Msk          (0xff0000UL)              /*!< COREID (Bitfield-Mask: 0xff)                          */
41040 /* ========================================================  AMQCFG  ========================================================= */
41041 #define I2S0_AMQCFG_ASRCEN_Pos            (1UL)                     /*!< ASRCEN (Bit 1)                                        */
41042 #define I2S0_AMQCFG_ASRCEN_Msk            (0x2UL)                   /*!< ASRCEN (Bitfield-Mask: 0x01)                          */
41043 #define I2S0_AMQCFG_MCLKSRC_Pos           (0UL)                     /*!< MCLKSRC (Bit 0)                                       */
41044 #define I2S0_AMQCFG_MCLKSRC_Msk           (0x1UL)                   /*!< MCLKSRC (Bitfield-Mask: 0x01)                         */
41045 /* ========================================================  INTDIV  ========================================================= */
41046 #define I2S0_INTDIV_INTDIV_Pos            (0UL)                     /*!< INTDIV (Bit 0)                                        */
41047 #define I2S0_INTDIV_INTDIV_Msk            (0xffffffffUL)            /*!< INTDIV (Bitfield-Mask: 0xffffffff)                    */
41048 /* ========================================================  FRACDIV  ======================================================== */
41049 #define I2S0_FRACDIV_FRACDIV_Pos          (0UL)                     /*!< FRACDIV (Bit 0)                                       */
41050 #define I2S0_FRACDIV_FRACDIV_Msk          (0xffffffffUL)            /*!< FRACDIV (Bitfield-Mask: 0xffffffff)                   */
41051 /* ========================================================  CLKCFG  ========================================================= */
41052 #define I2S0_CLKCFG_DIV3_Pos              (20UL)                    /*!< DIV3 (Bit 20)                                         */
41053 #define I2S0_CLKCFG_DIV3_Msk              (0x100000UL)              /*!< DIV3 (Bitfield-Mask: 0x01)                            */
41054 #define I2S0_CLKCFG_REFFSEL_Pos           (16UL)                    /*!< REFFSEL (Bit 16)                                      */
41055 #define I2S0_CLKCFG_REFFSEL_Msk           (0x30000UL)               /*!< REFFSEL (Bitfield-Mask: 0x03)                         */
41056 #define I2S0_CLKCFG_REFCLKEN_Pos          (12UL)                    /*!< REFCLKEN (Bit 12)                                     */
41057 #define I2S0_CLKCFG_REFCLKEN_Msk          (0x1000UL)                /*!< REFCLKEN (Bitfield-Mask: 0x01)                        */
41058 #define I2S0_CLKCFG_FSEL_Pos              (4UL)                     /*!< FSEL (Bit 4)                                          */
41059 #define I2S0_CLKCFG_FSEL_Msk              (0x1f0UL)                 /*!< FSEL (Bitfield-Mask: 0x1f)                            */
41060 #define I2S0_CLKCFG_MCLKEN_Pos            (0UL)                     /*!< MCLKEN (Bit 0)                                        */
41061 #define I2S0_CLKCFG_MCLKEN_Msk            (0x1UL)                   /*!< MCLKEN (Bitfield-Mask: 0x01)                          */
41062 /* ========================================================  DMACFG  ========================================================= */
41063 #define I2S0_DMACFG_RXREQCNT_Pos          (16UL)                    /*!< RXREQCNT (Bit 16)                                     */
41064 #define I2S0_DMACFG_RXREQCNT_Msk          (0xff0000UL)              /*!< RXREQCNT (Bitfield-Mask: 0xff)                        */
41065 #define I2S0_DMACFG_TXREQCNT_Pos          (8UL)                     /*!< TXREQCNT (Bit 8)                                      */
41066 #define I2S0_DMACFG_TXREQCNT_Msk          (0xff00UL)                /*!< TXREQCNT (Bitfield-Mask: 0xff)                        */
41067 #define I2S0_DMACFG_TXDMAPRI_Pos          (5UL)                     /*!< TXDMAPRI (Bit 5)                                      */
41068 #define I2S0_DMACFG_TXDMAPRI_Msk          (0x20UL)                  /*!< TXDMAPRI (Bitfield-Mask: 0x01)                        */
41069 #define I2S0_DMACFG_TXDMAEN_Pos           (4UL)                     /*!< TXDMAEN (Bit 4)                                       */
41070 #define I2S0_DMACFG_TXDMAEN_Msk           (0x10UL)                  /*!< TXDMAEN (Bitfield-Mask: 0x01)                         */
41071 #define I2S0_DMACFG_RXDMAPRI_Pos          (1UL)                     /*!< RXDMAPRI (Bit 1)                                      */
41072 #define I2S0_DMACFG_RXDMAPRI_Msk          (0x2UL)                   /*!< RXDMAPRI (Bitfield-Mask: 0x01)                        */
41073 #define I2S0_DMACFG_RXDMAEN_Pos           (0UL)                     /*!< RXDMAEN (Bit 0)                                       */
41074 #define I2S0_DMACFG_RXDMAEN_Msk           (0x1UL)                   /*!< RXDMAEN (Bitfield-Mask: 0x01)                         */
41075 /* ======================================================  RXDMATOTCNT  ====================================================== */
41076 #define I2S0_RXDMATOTCNT_RXTOTCNT_Pos     (0UL)                     /*!< RXTOTCNT (Bit 0)                                      */
41077 #define I2S0_RXDMATOTCNT_RXTOTCNT_Msk     (0xfffUL)                 /*!< RXTOTCNT (Bitfield-Mask: 0xfff)                       */
41078 /* =======================================================  RXDMAADDR  ======================================================= */
41079 #define I2S0_RXDMAADDR_RXTARGADDR_Pos     (0UL)                     /*!< RXTARGADDR (Bit 0)                                    */
41080 #define I2S0_RXDMAADDR_RXTARGADDR_Msk     (0xffffffffUL)            /*!< RXTARGADDR (Bitfield-Mask: 0xffffffff)                */
41081 /* =======================================================  RXDMASTAT  ======================================================= */
41082 #define I2S0_RXDMASTAT_RXDMAERR_Pos       (2UL)                     /*!< RXDMAERR (Bit 2)                                      */
41083 #define I2S0_RXDMASTAT_RXDMAERR_Msk       (0x4UL)                   /*!< RXDMAERR (Bitfield-Mask: 0x01)                        */
41084 #define I2S0_RXDMASTAT_RXDMACPL_Pos       (1UL)                     /*!< RXDMACPL (Bit 1)                                      */
41085 #define I2S0_RXDMASTAT_RXDMACPL_Msk       (0x2UL)                   /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
41086 #define I2S0_RXDMASTAT_RXDMATIP_Pos       (0UL)                     /*!< RXDMATIP (Bit 0)                                      */
41087 #define I2S0_RXDMASTAT_RXDMATIP_Msk       (0x1UL)                   /*!< RXDMATIP (Bitfield-Mask: 0x01)                        */
41088 /* ======================================================  TXDMATOTCNT  ====================================================== */
41089 #define I2S0_TXDMATOTCNT_TXTOTCNT_Pos     (0UL)                     /*!< TXTOTCNT (Bit 0)                                      */
41090 #define I2S0_TXDMATOTCNT_TXTOTCNT_Msk     (0xfffUL)                 /*!< TXTOTCNT (Bitfield-Mask: 0xfff)                       */
41091 /* =======================================================  TXDMAADDR  ======================================================= */
41092 #define I2S0_TXDMAADDR_TXTARGADDR_Pos     (0UL)                     /*!< TXTARGADDR (Bit 0)                                    */
41093 #define I2S0_TXDMAADDR_TXTARGADDR_Msk     (0xffffffffUL)            /*!< TXTARGADDR (Bitfield-Mask: 0xffffffff)                */
41094 /* =======================================================  TXDMASTAT  ======================================================= */
41095 #define I2S0_TXDMASTAT_TXDMAERR_Pos       (2UL)                     /*!< TXDMAERR (Bit 2)                                      */
41096 #define I2S0_TXDMASTAT_TXDMAERR_Msk       (0x4UL)                   /*!< TXDMAERR (Bitfield-Mask: 0x01)                        */
41097 #define I2S0_TXDMASTAT_TXDMACPL_Pos       (1UL)                     /*!< TXDMACPL (Bit 1)                                      */
41098 #define I2S0_TXDMASTAT_TXDMACPL_Msk       (0x2UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
41099 #define I2S0_TXDMASTAT_TXDMATIP_Pos       (0UL)                     /*!< TXDMATIP (Bit 0)                                      */
41100 #define I2S0_TXDMASTAT_TXDMATIP_Msk       (0x1UL)                   /*!< TXDMATIP (Bitfield-Mask: 0x01)                        */
41101 /* ========================================================  STATUS  ========================================================= */
41102 #define I2S0_STATUS_TBD_Pos               (0UL)                     /*!< TBD (Bit 0)                                           */
41103 #define I2S0_STATUS_TBD_Msk               (0x1UL)                   /*!< TBD (Bitfield-Mask: 0x01)                             */
41104 /* =========================================================  INTEN  ========================================================= */
41105 #define I2S0_INTEN_RXDMACPL_Pos           (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
41106 #define I2S0_INTEN_RXDMACPL_Msk           (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
41107 #define I2S0_INTEN_TXDMACPL_Pos           (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
41108 #define I2S0_INTEN_TXDMACPL_Msk           (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
41109 #define I2S0_INTEN_TXREQCNT_Pos           (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
41110 #define I2S0_INTEN_TXREQCNT_Msk           (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
41111 #define I2S0_INTEN_RXREQCNT_Pos           (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
41112 #define I2S0_INTEN_RXREQCNT_Msk           (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
41113 #define I2S0_INTEN_IPB_Pos                (0UL)                     /*!< IPB (Bit 0)                                           */
41114 #define I2S0_INTEN_IPB_Msk                (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
41115 /* ========================================================  INTSTAT  ======================================================== */
41116 #define I2S0_INTSTAT_RXDMACPL_Pos         (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
41117 #define I2S0_INTSTAT_RXDMACPL_Msk         (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
41118 #define I2S0_INTSTAT_TXDMACPL_Pos         (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
41119 #define I2S0_INTSTAT_TXDMACPL_Msk         (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
41120 #define I2S0_INTSTAT_TXREQCNT_Pos         (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
41121 #define I2S0_INTSTAT_TXREQCNT_Msk         (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
41122 #define I2S0_INTSTAT_RXREQCNT_Pos         (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
41123 #define I2S0_INTSTAT_RXREQCNT_Msk         (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
41124 #define I2S0_INTSTAT_IPB_Pos              (0UL)                     /*!< IPB (Bit 0)                                           */
41125 #define I2S0_INTSTAT_IPB_Msk              (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
41126 /* ========================================================  INTCLR  ========================================================= */
41127 #define I2S0_INTCLR_RXDMACPL_Pos          (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
41128 #define I2S0_INTCLR_RXDMACPL_Msk          (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
41129 #define I2S0_INTCLR_TXDMACPL_Pos          (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
41130 #define I2S0_INTCLR_TXDMACPL_Msk          (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
41131 #define I2S0_INTCLR_TXREQCNT_Pos          (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
41132 #define I2S0_INTCLR_TXREQCNT_Msk          (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
41133 #define I2S0_INTCLR_RXREQCNT_Pos          (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
41134 #define I2S0_INTCLR_RXREQCNT_Msk          (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
41135 #define I2S0_INTCLR_IPB_Pos               (0UL)                     /*!< IPB (Bit 0)                                           */
41136 #define I2S0_INTCLR_IPB_Msk               (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
41137 /* ========================================================  INTSET  ========================================================= */
41138 #define I2S0_INTSET_RXDMACPL_Pos          (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
41139 #define I2S0_INTSET_RXDMACPL_Msk          (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
41140 #define I2S0_INTSET_TXDMACPL_Pos          (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
41141 #define I2S0_INTSET_TXDMACPL_Msk          (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
41142 #define I2S0_INTSET_TXREQCNT_Pos          (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
41143 #define I2S0_INTSET_TXREQCNT_Msk          (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
41144 #define I2S0_INTSET_RXREQCNT_Pos          (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
41145 #define I2S0_INTSET_RXREQCNT_Msk          (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
41146 #define I2S0_INTSET_IPB_Pos               (0UL)                     /*!< IPB (Bit 0)                                           */
41147 #define I2S0_INTSET_IPB_Msk               (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
41148 /* ========================================================  I2SDBG  ========================================================= */
41149 #define I2S0_I2SDBG_DBGDATA_Pos           (3UL)                     /*!< DBGDATA (Bit 3)                                       */
41150 #define I2S0_I2SDBG_DBGDATA_Msk           (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
41151 #define I2S0_I2SDBG_APBCLKON_Pos          (2UL)                     /*!< APBCLKON (Bit 2)                                      */
41152 #define I2S0_I2SDBG_APBCLKON_Msk          (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
41153 #define I2S0_I2SDBG_MCLKON_Pos            (1UL)                     /*!< MCLKON (Bit 1)                                        */
41154 #define I2S0_I2SDBG_MCLKON_Msk            (0x2UL)                   /*!< MCLKON (Bitfield-Mask: 0x01)                          */
41155 #define I2S0_I2SDBG_DBGEN_Pos             (0UL)                     /*!< DBGEN (Bit 0)                                         */
41156 #define I2S0_I2SDBG_DBGEN_Msk             (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */
41157 
41158 
41159 /* =========================================================================================================================== */
41160 /* ================                                           IOM0                                            ================ */
41161 /* =========================================================================================================================== */
41162 
41163 /* =========================================================  FIFO  ========================================================== */
41164 #define IOM0_FIFO_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
41165 #define IOM0_FIFO_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
41166 /* ========================================================  FIFOPTR  ======================================================== */
41167 #define IOM0_FIFOPTR_FIFO1REM_Pos         (24UL)                    /*!< FIFO1REM (Bit 24)                                     */
41168 #define IOM0_FIFOPTR_FIFO1REM_Msk         (0xff000000UL)            /*!< FIFO1REM (Bitfield-Mask: 0xff)                        */
41169 #define IOM0_FIFOPTR_FIFO1SIZ_Pos         (16UL)                    /*!< FIFO1SIZ (Bit 16)                                     */
41170 #define IOM0_FIFOPTR_FIFO1SIZ_Msk         (0xff0000UL)              /*!< FIFO1SIZ (Bitfield-Mask: 0xff)                        */
41171 #define IOM0_FIFOPTR_FIFO0REM_Pos         (8UL)                     /*!< FIFO0REM (Bit 8)                                      */
41172 #define IOM0_FIFOPTR_FIFO0REM_Msk         (0xff00UL)                /*!< FIFO0REM (Bitfield-Mask: 0xff)                        */
41173 #define IOM0_FIFOPTR_FIFO0SIZ_Pos         (0UL)                     /*!< FIFO0SIZ (Bit 0)                                      */
41174 #define IOM0_FIFOPTR_FIFO0SIZ_Msk         (0xffUL)                  /*!< FIFO0SIZ (Bitfield-Mask: 0xff)                        */
41175 /* ========================================================  FIFOTHR  ======================================================== */
41176 #define IOM0_FIFOTHR_FIFOWTHR_Pos         (8UL)                     /*!< FIFOWTHR (Bit 8)                                      */
41177 #define IOM0_FIFOTHR_FIFOWTHR_Msk         (0x3f00UL)                /*!< FIFOWTHR (Bitfield-Mask: 0x3f)                        */
41178 #define IOM0_FIFOTHR_FIFORTHR_Pos         (0UL)                     /*!< FIFORTHR (Bit 0)                                      */
41179 #define IOM0_FIFOTHR_FIFORTHR_Msk         (0x3fUL)                  /*!< FIFORTHR (Bitfield-Mask: 0x3f)                        */
41180 /* ========================================================  FIFOPOP  ======================================================== */
41181 #define IOM0_FIFOPOP_FIFODOUT_Pos         (0UL)                     /*!< FIFODOUT (Bit 0)                                      */
41182 #define IOM0_FIFOPOP_FIFODOUT_Msk         (0xffffffffUL)            /*!< FIFODOUT (Bitfield-Mask: 0xffffffff)                  */
41183 /* =======================================================  FIFOPUSH  ======================================================== */
41184 #define IOM0_FIFOPUSH_FIFODIN_Pos         (0UL)                     /*!< FIFODIN (Bit 0)                                       */
41185 #define IOM0_FIFOPUSH_FIFODIN_Msk         (0xffffffffUL)            /*!< FIFODIN (Bitfield-Mask: 0xffffffff)                   */
41186 /* =======================================================  FIFOCTRL  ======================================================== */
41187 #define IOM0_FIFOCTRL_FIFORSTN_Pos        (1UL)                     /*!< FIFORSTN (Bit 1)                                      */
41188 #define IOM0_FIFOCTRL_FIFORSTN_Msk        (0x2UL)                   /*!< FIFORSTN (Bitfield-Mask: 0x01)                        */
41189 #define IOM0_FIFOCTRL_POPWR_Pos           (0UL)                     /*!< POPWR (Bit 0)                                         */
41190 #define IOM0_FIFOCTRL_POPWR_Msk           (0x1UL)                   /*!< POPWR (Bitfield-Mask: 0x01)                           */
41191 /* ========================================================  FIFOLOC  ======================================================== */
41192 #define IOM0_FIFOLOC_FIFORPTR_Pos         (8UL)                     /*!< FIFORPTR (Bit 8)                                      */
41193 #define IOM0_FIFOLOC_FIFORPTR_Msk         (0xf00UL)                 /*!< FIFORPTR (Bitfield-Mask: 0x0f)                        */
41194 #define IOM0_FIFOLOC_FIFOWPTR_Pos         (0UL)                     /*!< FIFOWPTR (Bit 0)                                      */
41195 #define IOM0_FIFOLOC_FIFOWPTR_Msk         (0xfUL)                   /*!< FIFOWPTR (Bitfield-Mask: 0x0f)                        */
41196 /* ========================================================  CLKCFG  ========================================================= */
41197 #define IOM0_CLKCFG_TOTPER_Pos            (24UL)                    /*!< TOTPER (Bit 24)                                       */
41198 #define IOM0_CLKCFG_TOTPER_Msk            (0xff000000UL)            /*!< TOTPER (Bitfield-Mask: 0xff)                          */
41199 #define IOM0_CLKCFG_LOWPER_Pos            (16UL)                    /*!< LOWPER (Bit 16)                                       */
41200 #define IOM0_CLKCFG_LOWPER_Msk            (0xff0000UL)              /*!< LOWPER (Bitfield-Mask: 0xff)                          */
41201 #define IOM0_CLKCFG_DIVEN_Pos             (12UL)                    /*!< DIVEN (Bit 12)                                        */
41202 #define IOM0_CLKCFG_DIVEN_Msk             (0x1000UL)                /*!< DIVEN (Bitfield-Mask: 0x01)                           */
41203 #define IOM0_CLKCFG_DIV3_Pos              (11UL)                    /*!< DIV3 (Bit 11)                                         */
41204 #define IOM0_CLKCFG_DIV3_Msk              (0x800UL)                 /*!< DIV3 (Bitfield-Mask: 0x01)                            */
41205 #define IOM0_CLKCFG_FSEL_Pos              (8UL)                     /*!< FSEL (Bit 8)                                          */
41206 #define IOM0_CLKCFG_FSEL_Msk              (0x700UL)                 /*!< FSEL (Bitfield-Mask: 0x07)                            */
41207 #define IOM0_CLKCFG_IOCLKEN_Pos           (0UL)                     /*!< IOCLKEN (Bit 0)                                       */
41208 #define IOM0_CLKCFG_IOCLKEN_Msk           (0x1UL)                   /*!< IOCLKEN (Bitfield-Mask: 0x01)                         */
41209 /* ======================================================  SUBMODCTRL  ======================================================= */
41210 #define IOM0_SUBMODCTRL_SMOD2TYPE_Pos     (9UL)                     /*!< SMOD2TYPE (Bit 9)                                     */
41211 #define IOM0_SUBMODCTRL_SMOD2TYPE_Msk     (0xe00UL)                 /*!< SMOD2TYPE (Bitfield-Mask: 0x07)                       */
41212 #define IOM0_SUBMODCTRL_SMOD2EN_Pos       (8UL)                     /*!< SMOD2EN (Bit 8)                                       */
41213 #define IOM0_SUBMODCTRL_SMOD2EN_Msk       (0x100UL)                 /*!< SMOD2EN (Bitfield-Mask: 0x01)                         */
41214 #define IOM0_SUBMODCTRL_SMOD1TYPE_Pos     (5UL)                     /*!< SMOD1TYPE (Bit 5)                                     */
41215 #define IOM0_SUBMODCTRL_SMOD1TYPE_Msk     (0xe0UL)                  /*!< SMOD1TYPE (Bitfield-Mask: 0x07)                       */
41216 #define IOM0_SUBMODCTRL_SMOD1EN_Pos       (4UL)                     /*!< SMOD1EN (Bit 4)                                       */
41217 #define IOM0_SUBMODCTRL_SMOD1EN_Msk       (0x10UL)                  /*!< SMOD1EN (Bitfield-Mask: 0x01)                         */
41218 #define IOM0_SUBMODCTRL_SMOD0TYPE_Pos     (1UL)                     /*!< SMOD0TYPE (Bit 1)                                     */
41219 #define IOM0_SUBMODCTRL_SMOD0TYPE_Msk     (0xeUL)                   /*!< SMOD0TYPE (Bitfield-Mask: 0x07)                       */
41220 #define IOM0_SUBMODCTRL_SMOD0EN_Pos       (0UL)                     /*!< SMOD0EN (Bit 0)                                       */
41221 #define IOM0_SUBMODCTRL_SMOD0EN_Msk       (0x1UL)                   /*!< SMOD0EN (Bitfield-Mask: 0x01)                         */
41222 /* ==========================================================  CMD  ========================================================== */
41223 #define IOM0_CMD_OFFSETLO_Pos             (24UL)                    /*!< OFFSETLO (Bit 24)                                     */
41224 #define IOM0_CMD_OFFSETLO_Msk             (0xff000000UL)            /*!< OFFSETLO (Bitfield-Mask: 0xff)                        */
41225 #define IOM0_CMD_CMDSEL_Pos               (20UL)                    /*!< CMDSEL (Bit 20)                                       */
41226 #define IOM0_CMD_CMDSEL_Msk               (0x300000UL)              /*!< CMDSEL (Bitfield-Mask: 0x03)                          */
41227 #define IOM0_CMD_TSIZE_Pos                (8UL)                     /*!< TSIZE (Bit 8)                                         */
41228 #define IOM0_CMD_TSIZE_Msk                (0xfff00UL)               /*!< TSIZE (Bitfield-Mask: 0xfff)                          */
41229 #define IOM0_CMD_CONT_Pos                 (7UL)                     /*!< CONT (Bit 7)                                          */
41230 #define IOM0_CMD_CONT_Msk                 (0x80UL)                  /*!< CONT (Bitfield-Mask: 0x01)                            */
41231 #define IOM0_CMD_OFFSETCNT_Pos            (4UL)                     /*!< OFFSETCNT (Bit 4)                                     */
41232 #define IOM0_CMD_OFFSETCNT_Msk            (0x70UL)                  /*!< OFFSETCNT (Bitfield-Mask: 0x07)                       */
41233 #define IOM0_CMD_CMD_Pos                  (0UL)                     /*!< CMD (Bit 0)                                           */
41234 #define IOM0_CMD_CMD_Msk                  (0xfUL)                   /*!< CMD (Bitfield-Mask: 0x0f)                             */
41235 /* ========================================================  DCXCTRL  ======================================================== */
41236 #define IOM0_DCXCTRL_DCXEN_Pos            (4UL)                     /*!< DCXEN (Bit 4)                                         */
41237 #define IOM0_DCXCTRL_DCXEN_Msk            (0x10UL)                  /*!< DCXEN (Bitfield-Mask: 0x01)                           */
41238 #define IOM0_DCXCTRL_DCXSEL_Pos           (0UL)                     /*!< DCXSEL (Bit 0)                                        */
41239 #define IOM0_DCXCTRL_DCXSEL_Msk           (0xfUL)                   /*!< DCXSEL (Bitfield-Mask: 0x0f)                          */
41240 /* =======================================================  OFFSETHI  ======================================================== */
41241 #define IOM0_OFFSETHI_OFFSETHI_Pos        (0UL)                     /*!< OFFSETHI (Bit 0)                                      */
41242 #define IOM0_OFFSETHI_OFFSETHI_Msk        (0xffffffffUL)            /*!< OFFSETHI (Bitfield-Mask: 0xffffffff)                  */
41243 /* ========================================================  CMDSTAT  ======================================================== */
41244 #define IOM0_CMDSTAT_CTSIZE_Pos           (8UL)                     /*!< CTSIZE (Bit 8)                                        */
41245 #define IOM0_CMDSTAT_CTSIZE_Msk           (0xfff00UL)               /*!< CTSIZE (Bitfield-Mask: 0xfff)                         */
41246 #define IOM0_CMDSTAT_CMDSTAT_Pos          (5UL)                     /*!< CMDSTAT (Bit 5)                                       */
41247 #define IOM0_CMDSTAT_CMDSTAT_Msk          (0xe0UL)                  /*!< CMDSTAT (Bitfield-Mask: 0x07)                         */
41248 #define IOM0_CMDSTAT_CCMD_Pos             (0UL)                     /*!< CCMD (Bit 0)                                          */
41249 #define IOM0_CMDSTAT_CCMD_Msk             (0x1fUL)                  /*!< CCMD (Bitfield-Mask: 0x1f)                            */
41250 /* =========================================================  INTEN  ========================================================= */
41251 #define IOM0_INTEN_CQERR_Pos              (14UL)                    /*!< CQERR (Bit 14)                                        */
41252 #define IOM0_INTEN_CQERR_Msk              (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
41253 #define IOM0_INTEN_CQUPD_Pos              (13UL)                    /*!< CQUPD (Bit 13)                                        */
41254 #define IOM0_INTEN_CQUPD_Msk              (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
41255 #define IOM0_INTEN_CQPAUSED_Pos           (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
41256 #define IOM0_INTEN_CQPAUSED_Msk           (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
41257 #define IOM0_INTEN_DERR_Pos               (11UL)                    /*!< DERR (Bit 11)                                         */
41258 #define IOM0_INTEN_DERR_Msk               (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
41259 #define IOM0_INTEN_DCMP_Pos               (10UL)                    /*!< DCMP (Bit 10)                                         */
41260 #define IOM0_INTEN_DCMP_Msk               (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
41261 #define IOM0_INTEN_ARB_Pos                (9UL)                     /*!< ARB (Bit 9)                                           */
41262 #define IOM0_INTEN_ARB_Msk                (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
41263 #define IOM0_INTEN_STOP_Pos               (8UL)                     /*!< STOP (Bit 8)                                          */
41264 #define IOM0_INTEN_STOP_Msk               (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
41265 #define IOM0_INTEN_START_Pos              (7UL)                     /*!< START (Bit 7)                                         */
41266 #define IOM0_INTEN_START_Msk              (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
41267 #define IOM0_INTEN_ICMD_Pos               (6UL)                     /*!< ICMD (Bit 6)                                          */
41268 #define IOM0_INTEN_ICMD_Msk               (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
41269 #define IOM0_INTEN_IACC_Pos               (5UL)                     /*!< IACC (Bit 5)                                          */
41270 #define IOM0_INTEN_IACC_Msk               (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
41271 #define IOM0_INTEN_NAK_Pos                (4UL)                     /*!< NAK (Bit 4)                                           */
41272 #define IOM0_INTEN_NAK_Msk                (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
41273 #define IOM0_INTEN_FOVFL_Pos              (3UL)                     /*!< FOVFL (Bit 3)                                         */
41274 #define IOM0_INTEN_FOVFL_Msk              (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41275 #define IOM0_INTEN_FUNDFL_Pos             (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41276 #define IOM0_INTEN_FUNDFL_Msk             (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41277 #define IOM0_INTEN_THR_Pos                (1UL)                     /*!< THR (Bit 1)                                           */
41278 #define IOM0_INTEN_THR_Msk                (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
41279 #define IOM0_INTEN_CMDCMP_Pos             (0UL)                     /*!< CMDCMP (Bit 0)                                        */
41280 #define IOM0_INTEN_CMDCMP_Msk             (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
41281 /* ========================================================  INTSTAT  ======================================================== */
41282 #define IOM0_INTSTAT_CQERR_Pos            (14UL)                    /*!< CQERR (Bit 14)                                        */
41283 #define IOM0_INTSTAT_CQERR_Msk            (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
41284 #define IOM0_INTSTAT_CQUPD_Pos            (13UL)                    /*!< CQUPD (Bit 13)                                        */
41285 #define IOM0_INTSTAT_CQUPD_Msk            (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
41286 #define IOM0_INTSTAT_CQPAUSED_Pos         (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
41287 #define IOM0_INTSTAT_CQPAUSED_Msk         (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
41288 #define IOM0_INTSTAT_DERR_Pos             (11UL)                    /*!< DERR (Bit 11)                                         */
41289 #define IOM0_INTSTAT_DERR_Msk             (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
41290 #define IOM0_INTSTAT_DCMP_Pos             (10UL)                    /*!< DCMP (Bit 10)                                         */
41291 #define IOM0_INTSTAT_DCMP_Msk             (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
41292 #define IOM0_INTSTAT_ARB_Pos              (9UL)                     /*!< ARB (Bit 9)                                           */
41293 #define IOM0_INTSTAT_ARB_Msk              (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
41294 #define IOM0_INTSTAT_STOP_Pos             (8UL)                     /*!< STOP (Bit 8)                                          */
41295 #define IOM0_INTSTAT_STOP_Msk             (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
41296 #define IOM0_INTSTAT_START_Pos            (7UL)                     /*!< START (Bit 7)                                         */
41297 #define IOM0_INTSTAT_START_Msk            (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
41298 #define IOM0_INTSTAT_ICMD_Pos             (6UL)                     /*!< ICMD (Bit 6)                                          */
41299 #define IOM0_INTSTAT_ICMD_Msk             (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
41300 #define IOM0_INTSTAT_IACC_Pos             (5UL)                     /*!< IACC (Bit 5)                                          */
41301 #define IOM0_INTSTAT_IACC_Msk             (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
41302 #define IOM0_INTSTAT_NAK_Pos              (4UL)                     /*!< NAK (Bit 4)                                           */
41303 #define IOM0_INTSTAT_NAK_Msk              (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
41304 #define IOM0_INTSTAT_FOVFL_Pos            (3UL)                     /*!< FOVFL (Bit 3)                                         */
41305 #define IOM0_INTSTAT_FOVFL_Msk            (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41306 #define IOM0_INTSTAT_FUNDFL_Pos           (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41307 #define IOM0_INTSTAT_FUNDFL_Msk           (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41308 #define IOM0_INTSTAT_THR_Pos              (1UL)                     /*!< THR (Bit 1)                                           */
41309 #define IOM0_INTSTAT_THR_Msk              (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
41310 #define IOM0_INTSTAT_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
41311 #define IOM0_INTSTAT_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
41312 /* ========================================================  INTCLR  ========================================================= */
41313 #define IOM0_INTCLR_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
41314 #define IOM0_INTCLR_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
41315 #define IOM0_INTCLR_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
41316 #define IOM0_INTCLR_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
41317 #define IOM0_INTCLR_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
41318 #define IOM0_INTCLR_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
41319 #define IOM0_INTCLR_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
41320 #define IOM0_INTCLR_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
41321 #define IOM0_INTCLR_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
41322 #define IOM0_INTCLR_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
41323 #define IOM0_INTCLR_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
41324 #define IOM0_INTCLR_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
41325 #define IOM0_INTCLR_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
41326 #define IOM0_INTCLR_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
41327 #define IOM0_INTCLR_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
41328 #define IOM0_INTCLR_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
41329 #define IOM0_INTCLR_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
41330 #define IOM0_INTCLR_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
41331 #define IOM0_INTCLR_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
41332 #define IOM0_INTCLR_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
41333 #define IOM0_INTCLR_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
41334 #define IOM0_INTCLR_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
41335 #define IOM0_INTCLR_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
41336 #define IOM0_INTCLR_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41337 #define IOM0_INTCLR_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41338 #define IOM0_INTCLR_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41339 #define IOM0_INTCLR_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
41340 #define IOM0_INTCLR_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
41341 #define IOM0_INTCLR_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
41342 #define IOM0_INTCLR_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
41343 /* ========================================================  INTSET  ========================================================= */
41344 #define IOM0_INTSET_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
41345 #define IOM0_INTSET_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
41346 #define IOM0_INTSET_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
41347 #define IOM0_INTSET_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
41348 #define IOM0_INTSET_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
41349 #define IOM0_INTSET_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
41350 #define IOM0_INTSET_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
41351 #define IOM0_INTSET_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
41352 #define IOM0_INTSET_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
41353 #define IOM0_INTSET_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
41354 #define IOM0_INTSET_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
41355 #define IOM0_INTSET_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
41356 #define IOM0_INTSET_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
41357 #define IOM0_INTSET_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
41358 #define IOM0_INTSET_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
41359 #define IOM0_INTSET_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
41360 #define IOM0_INTSET_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
41361 #define IOM0_INTSET_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
41362 #define IOM0_INTSET_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
41363 #define IOM0_INTSET_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
41364 #define IOM0_INTSET_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
41365 #define IOM0_INTSET_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
41366 #define IOM0_INTSET_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
41367 #define IOM0_INTSET_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41368 #define IOM0_INTSET_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41369 #define IOM0_INTSET_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41370 #define IOM0_INTSET_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
41371 #define IOM0_INTSET_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
41372 #define IOM0_INTSET_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
41373 #define IOM0_INTSET_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
41374 /* =======================================================  DMATRIGEN  ======================================================= */
41375 #define IOM0_DMATRIGEN_DTHREN_Pos         (1UL)                     /*!< DTHREN (Bit 1)                                        */
41376 #define IOM0_DMATRIGEN_DTHREN_Msk         (0x2UL)                   /*!< DTHREN (Bitfield-Mask: 0x01)                          */
41377 #define IOM0_DMATRIGEN_DCMDCMPEN_Pos      (0UL)                     /*!< DCMDCMPEN (Bit 0)                                     */
41378 #define IOM0_DMATRIGEN_DCMDCMPEN_Msk      (0x1UL)                   /*!< DCMDCMPEN (Bitfield-Mask: 0x01)                       */
41379 /* ======================================================  DMATRIGSTAT  ====================================================== */
41380 #define IOM0_DMATRIGSTAT_DTOTCMP_Pos      (2UL)                     /*!< DTOTCMP (Bit 2)                                       */
41381 #define IOM0_DMATRIGSTAT_DTOTCMP_Msk      (0x4UL)                   /*!< DTOTCMP (Bitfield-Mask: 0x01)                         */
41382 #define IOM0_DMATRIGSTAT_DTHR_Pos         (1UL)                     /*!< DTHR (Bit 1)                                          */
41383 #define IOM0_DMATRIGSTAT_DTHR_Msk         (0x2UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
41384 #define IOM0_DMATRIGSTAT_DCMDCMP_Pos      (0UL)                     /*!< DCMDCMP (Bit 0)                                       */
41385 #define IOM0_DMATRIGSTAT_DCMDCMP_Msk      (0x1UL)                   /*!< DCMDCMP (Bitfield-Mask: 0x01)                         */
41386 /* ========================================================  DMACFG  ========================================================= */
41387 #define IOM0_DMACFG_DPWROFF_Pos           (9UL)                     /*!< DPWROFF (Bit 9)                                       */
41388 #define IOM0_DMACFG_DPWROFF_Msk           (0x200UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
41389 #define IOM0_DMACFG_DMAPRI_Pos            (8UL)                     /*!< DMAPRI (Bit 8)                                        */
41390 #define IOM0_DMACFG_DMAPRI_Msk            (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
41391 #define IOM0_DMACFG_DMADIR_Pos            (1UL)                     /*!< DMADIR (Bit 1)                                        */
41392 #define IOM0_DMACFG_DMADIR_Msk            (0x2UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
41393 #define IOM0_DMACFG_DMAEN_Pos             (0UL)                     /*!< DMAEN (Bit 0)                                         */
41394 #define IOM0_DMACFG_DMAEN_Msk             (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
41395 /* ======================================================  DMATOTCOUNT  ====================================================== */
41396 #define IOM0_DMATOTCOUNT_TOTCOUNT_Pos     (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
41397 #define IOM0_DMATOTCOUNT_TOTCOUNT_Msk     (0xfffUL)                 /*!< TOTCOUNT (Bitfield-Mask: 0xfff)                       */
41398 /* ======================================================  DMATARGADDR  ====================================================== */
41399 #define IOM0_DMATARGADDR_TARGADDR_Pos     (0UL)                     /*!< TARGADDR (Bit 0)                                      */
41400 #define IOM0_DMATARGADDR_TARGADDR_Msk     (0x1fffffffUL)            /*!< TARGADDR (Bitfield-Mask: 0x1fffffff)                  */
41401 /* ========================================================  DMASTAT  ======================================================== */
41402 #define IOM0_DMASTAT_DMAERR_Pos           (2UL)                     /*!< DMAERR (Bit 2)                                        */
41403 #define IOM0_DMASTAT_DMAERR_Msk           (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
41404 #define IOM0_DMASTAT_DMACPL_Pos           (1UL)                     /*!< DMACPL (Bit 1)                                        */
41405 #define IOM0_DMASTAT_DMACPL_Msk           (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
41406 #define IOM0_DMASTAT_DMATIP_Pos           (0UL)                     /*!< DMATIP (Bit 0)                                        */
41407 #define IOM0_DMASTAT_DMATIP_Msk           (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
41408 /* =========================================================  CQCFG  ========================================================= */
41409 #define IOM0_CQCFG_MSPIFLGSEL_Pos         (2UL)                     /*!< MSPIFLGSEL (Bit 2)                                    */
41410 #define IOM0_CQCFG_MSPIFLGSEL_Msk         (0xcUL)                   /*!< MSPIFLGSEL (Bitfield-Mask: 0x03)                      */
41411 #define IOM0_CQCFG_CQPRI_Pos              (1UL)                     /*!< CQPRI (Bit 1)                                         */
41412 #define IOM0_CQCFG_CQPRI_Msk              (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
41413 #define IOM0_CQCFG_CQEN_Pos               (0UL)                     /*!< CQEN (Bit 0)                                          */
41414 #define IOM0_CQCFG_CQEN_Msk               (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
41415 /* ========================================================  CQADDR  ========================================================= */
41416 #define IOM0_CQADDR_CQADDR_Pos            (2UL)                     /*!< CQADDR (Bit 2)                                        */
41417 #define IOM0_CQADDR_CQADDR_Msk            (0x1ffffffcUL)            /*!< CQADDR (Bitfield-Mask: 0x7ffffff)                     */
41418 /* ========================================================  CQSTAT  ========================================================= */
41419 #define IOM0_CQSTAT_CQERR_Pos             (2UL)                     /*!< CQERR (Bit 2)                                         */
41420 #define IOM0_CQSTAT_CQERR_Msk             (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
41421 #define IOM0_CQSTAT_CQPAUSED_Pos          (1UL)                     /*!< CQPAUSED (Bit 1)                                      */
41422 #define IOM0_CQSTAT_CQPAUSED_Msk          (0x2UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
41423 #define IOM0_CQSTAT_CQTIP_Pos             (0UL)                     /*!< CQTIP (Bit 0)                                         */
41424 #define IOM0_CQSTAT_CQTIP_Msk             (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
41425 /* ========================================================  CQFLAGS  ======================================================== */
41426 #define IOM0_CQFLAGS_CQIRQMASK_Pos        (16UL)                    /*!< CQIRQMASK (Bit 16)                                    */
41427 #define IOM0_CQFLAGS_CQIRQMASK_Msk        (0xffff0000UL)            /*!< CQIRQMASK (Bitfield-Mask: 0xffff)                     */
41428 #define IOM0_CQFLAGS_CQFLAGS_Pos          (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
41429 #define IOM0_CQFLAGS_CQFLAGS_Msk          (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
41430 /* ======================================================  CQSETCLEAR  ======================================================= */
41431 #define IOM0_CQSETCLEAR_CQFCLR_Pos        (16UL)                    /*!< CQFCLR (Bit 16)                                       */
41432 #define IOM0_CQSETCLEAR_CQFCLR_Msk        (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
41433 #define IOM0_CQSETCLEAR_CQFTGL_Pos        (8UL)                     /*!< CQFTGL (Bit 8)                                        */
41434 #define IOM0_CQSETCLEAR_CQFTGL_Msk        (0xff00UL)                /*!< CQFTGL (Bitfield-Mask: 0xff)                          */
41435 #define IOM0_CQSETCLEAR_CQFSET_Pos        (0UL)                     /*!< CQFSET (Bit 0)                                        */
41436 #define IOM0_CQSETCLEAR_CQFSET_Msk        (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
41437 /* =======================================================  CQPAUSEEN  ======================================================= */
41438 #define IOM0_CQPAUSEEN_CQPEN_Pos          (0UL)                     /*!< CQPEN (Bit 0)                                         */
41439 #define IOM0_CQPAUSEEN_CQPEN_Msk          (0xffffUL)                /*!< CQPEN (Bitfield-Mask: 0xffff)                         */
41440 /* =======================================================  CQCURIDX  ======================================================== */
41441 #define IOM0_CQCURIDX_CQCURIDX_Pos        (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
41442 #define IOM0_CQCURIDX_CQCURIDX_Msk        (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
41443 /* =======================================================  CQENDIDX  ======================================================== */
41444 #define IOM0_CQENDIDX_CQENDIDX_Pos        (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
41445 #define IOM0_CQENDIDX_CQENDIDX_Msk        (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
41446 /* ========================================================  STATUS  ========================================================= */
41447 #define IOM0_STATUS_IDLEST_Pos            (2UL)                     /*!< IDLEST (Bit 2)                                        */
41448 #define IOM0_STATUS_IDLEST_Msk            (0x4UL)                   /*!< IDLEST (Bitfield-Mask: 0x01)                          */
41449 #define IOM0_STATUS_CMDACT_Pos            (1UL)                     /*!< CMDACT (Bit 1)                                        */
41450 #define IOM0_STATUS_CMDACT_Msk            (0x2UL)                   /*!< CMDACT (Bitfield-Mask: 0x01)                          */
41451 #define IOM0_STATUS_ERR_Pos               (0UL)                     /*!< ERR (Bit 0)                                           */
41452 #define IOM0_STATUS_ERR_Msk               (0x1UL)                   /*!< ERR (Bitfield-Mask: 0x01)                             */
41453 /* ========================================================  MSPICFG  ======================================================== */
41454 #define IOM0_MSPICFG_MSPIRST_Pos          (30UL)                    /*!< MSPIRST (Bit 30)                                      */
41455 #define IOM0_MSPICFG_MSPIRST_Msk          (0x40000000UL)            /*!< MSPIRST (Bitfield-Mask: 0x01)                         */
41456 #define IOM0_MSPICFG_DOUTDLY_Pos          (27UL)                    /*!< DOUTDLY (Bit 27)                                      */
41457 #define IOM0_MSPICFG_DOUTDLY_Msk          (0x38000000UL)            /*!< DOUTDLY (Bitfield-Mask: 0x07)                         */
41458 #define IOM0_MSPICFG_DINDLY_Pos           (24UL)                    /*!< DINDLY (Bit 24)                                       */
41459 #define IOM0_MSPICFG_DINDLY_Msk           (0x7000000UL)             /*!< DINDLY (Bitfield-Mask: 0x07)                          */
41460 #define IOM0_MSPICFG_SPILSB_Pos           (23UL)                    /*!< SPILSB (Bit 23)                                       */
41461 #define IOM0_MSPICFG_SPILSB_Msk           (0x800000UL)              /*!< SPILSB (Bitfield-Mask: 0x01)                          */
41462 #define IOM0_MSPICFG_RDFCPOL_Pos          (22UL)                    /*!< RDFCPOL (Bit 22)                                      */
41463 #define IOM0_MSPICFG_RDFCPOL_Msk          (0x400000UL)              /*!< RDFCPOL (Bitfield-Mask: 0x01)                         */
41464 #define IOM0_MSPICFG_WTFCPOL_Pos          (21UL)                    /*!< WTFCPOL (Bit 21)                                      */
41465 #define IOM0_MSPICFG_WTFCPOL_Msk          (0x200000UL)              /*!< WTFCPOL (Bitfield-Mask: 0x01)                         */
41466 #define IOM0_MSPICFG_WTFCIRQ_Pos          (20UL)                    /*!< WTFCIRQ (Bit 20)                                      */
41467 #define IOM0_MSPICFG_WTFCIRQ_Msk          (0x100000UL)              /*!< WTFCIRQ (Bitfield-Mask: 0x01)                         */
41468 #define IOM0_MSPICFG_MOSIINV_Pos          (18UL)                    /*!< MOSIINV (Bit 18)                                      */
41469 #define IOM0_MSPICFG_MOSIINV_Msk          (0x40000UL)               /*!< MOSIINV (Bitfield-Mask: 0x01)                         */
41470 #define IOM0_MSPICFG_RDFC_Pos             (17UL)                    /*!< RDFC (Bit 17)                                         */
41471 #define IOM0_MSPICFG_RDFC_Msk             (0x20000UL)               /*!< RDFC (Bitfield-Mask: 0x01)                            */
41472 #define IOM0_MSPICFG_WTFC_Pos             (16UL)                    /*!< WTFC (Bit 16)                                         */
41473 #define IOM0_MSPICFG_WTFC_Msk             (0x10000UL)               /*!< WTFC (Bitfield-Mask: 0x01)                            */
41474 #define IOM0_MSPICFG_FULLDUP_Pos          (2UL)                     /*!< FULLDUP (Bit 2)                                       */
41475 #define IOM0_MSPICFG_FULLDUP_Msk          (0x4UL)                   /*!< FULLDUP (Bitfield-Mask: 0x01)                         */
41476 #define IOM0_MSPICFG_SPHA_Pos             (1UL)                     /*!< SPHA (Bit 1)                                          */
41477 #define IOM0_MSPICFG_SPHA_Msk             (0x2UL)                   /*!< SPHA (Bitfield-Mask: 0x01)                            */
41478 #define IOM0_MSPICFG_SPOL_Pos             (0UL)                     /*!< SPOL (Bit 0)                                          */
41479 #define IOM0_MSPICFG_SPOL_Msk             (0x1UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
41480 /* ========================================================  MI2CCFG  ======================================================== */
41481 #define IOM0_MI2CCFG_STRDIS_Pos           (24UL)                    /*!< STRDIS (Bit 24)                                       */
41482 #define IOM0_MI2CCFG_STRDIS_Msk           (0x1000000UL)             /*!< STRDIS (Bitfield-Mask: 0x01)                          */
41483 #define IOM0_MI2CCFG_SMPCNT_Pos           (16UL)                    /*!< SMPCNT (Bit 16)                                       */
41484 #define IOM0_MI2CCFG_SMPCNT_Msk           (0xff0000UL)              /*!< SMPCNT (Bitfield-Mask: 0xff)                          */
41485 #define IOM0_MI2CCFG_SDAENDLY_Pos         (12UL)                    /*!< SDAENDLY (Bit 12)                                     */
41486 #define IOM0_MI2CCFG_SDAENDLY_Msk         (0xf000UL)                /*!< SDAENDLY (Bitfield-Mask: 0x0f)                        */
41487 #define IOM0_MI2CCFG_SCLENDLY_Pos         (8UL)                     /*!< SCLENDLY (Bit 8)                                      */
41488 #define IOM0_MI2CCFG_SCLENDLY_Msk         (0xf00UL)                 /*!< SCLENDLY (Bitfield-Mask: 0x0f)                        */
41489 #define IOM0_MI2CCFG_MI2CRST_Pos          (6UL)                     /*!< MI2CRST (Bit 6)                                       */
41490 #define IOM0_MI2CCFG_MI2CRST_Msk          (0x40UL)                  /*!< MI2CRST (Bitfield-Mask: 0x01)                         */
41491 #define IOM0_MI2CCFG_SDADLY_Pos           (4UL)                     /*!< SDADLY (Bit 4)                                        */
41492 #define IOM0_MI2CCFG_SDADLY_Msk           (0x30UL)                  /*!< SDADLY (Bitfield-Mask: 0x03)                          */
41493 #define IOM0_MI2CCFG_ARBEN_Pos            (2UL)                     /*!< ARBEN (Bit 2)                                         */
41494 #define IOM0_MI2CCFG_ARBEN_Msk            (0x4UL)                   /*!< ARBEN (Bitfield-Mask: 0x01)                           */
41495 #define IOM0_MI2CCFG_I2CLSB_Pos           (1UL)                     /*!< I2CLSB (Bit 1)                                        */
41496 #define IOM0_MI2CCFG_I2CLSB_Msk           (0x2UL)                   /*!< I2CLSB (Bitfield-Mask: 0x01)                          */
41497 #define IOM0_MI2CCFG_ADDRSZ_Pos           (0UL)                     /*!< ADDRSZ (Bit 0)                                        */
41498 #define IOM0_MI2CCFG_ADDRSZ_Msk           (0x1UL)                   /*!< ADDRSZ (Bitfield-Mask: 0x01)                          */
41499 /* ========================================================  DEVCFG  ========================================================= */
41500 #define IOM0_DEVCFG_DEVADDR_Pos           (0UL)                     /*!< DEVADDR (Bit 0)                                       */
41501 #define IOM0_DEVCFG_DEVADDR_Msk           (0x3ffUL)                 /*!< DEVADDR (Bitfield-Mask: 0x3ff)                        */
41502 /* ========================================================  IOMDBG  ========================================================= */
41503 #define IOM0_IOMDBG_DBGDATA_Pos           (3UL)                     /*!< DBGDATA (Bit 3)                                       */
41504 #define IOM0_IOMDBG_DBGDATA_Msk           (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
41505 #define IOM0_IOMDBG_APBCLKON_Pos          (2UL)                     /*!< APBCLKON (Bit 2)                                      */
41506 #define IOM0_IOMDBG_APBCLKON_Msk          (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
41507 #define IOM0_IOMDBG_IOCLKON_Pos           (1UL)                     /*!< IOCLKON (Bit 1)                                       */
41508 #define IOM0_IOMDBG_IOCLKON_Msk           (0x2UL)                   /*!< IOCLKON (Bitfield-Mask: 0x01)                         */
41509 #define IOM0_IOMDBG_DBGEN_Pos             (0UL)                     /*!< DBGEN (Bit 0)                                         */
41510 #define IOM0_IOMDBG_DBGEN_Msk             (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */
41511 
41512 
41513 /* =========================================================================================================================== */
41514 /* ================                                          IOSLAVE                                          ================ */
41515 /* =========================================================================================================================== */
41516 
41517 /* ========================================================  FIFOPTR  ======================================================== */
41518 #define IOSLAVE_FIFOPTR_FIFOSIZ_Pos       (8UL)                     /*!< FIFOSIZ (Bit 8)                                       */
41519 #define IOSLAVE_FIFOPTR_FIFOSIZ_Msk       (0xff00UL)                /*!< FIFOSIZ (Bitfield-Mask: 0xff)                         */
41520 #define IOSLAVE_FIFOPTR_FIFOPTR_Pos       (0UL)                     /*!< FIFOPTR (Bit 0)                                       */
41521 #define IOSLAVE_FIFOPTR_FIFOPTR_Msk       (0xffUL)                  /*!< FIFOPTR (Bitfield-Mask: 0xff)                         */
41522 /* ========================================================  FIFOCFG  ======================================================== */
41523 #define IOSLAVE_FIFOCFG_ROBASE_Pos        (24UL)                    /*!< ROBASE (Bit 24)                                       */
41524 #define IOSLAVE_FIFOCFG_ROBASE_Msk        (0x3f000000UL)            /*!< ROBASE (Bitfield-Mask: 0x3f)                          */
41525 #define IOSLAVE_FIFOCFG_FIFOMAX_Pos       (8UL)                     /*!< FIFOMAX (Bit 8)                                       */
41526 #define IOSLAVE_FIFOCFG_FIFOMAX_Msk       (0x3f00UL)                /*!< FIFOMAX (Bitfield-Mask: 0x3f)                         */
41527 #define IOSLAVE_FIFOCFG_FIFOBASE_Pos      (0UL)                     /*!< FIFOBASE (Bit 0)                                      */
41528 #define IOSLAVE_FIFOCFG_FIFOBASE_Msk      (0x1fUL)                  /*!< FIFOBASE (Bitfield-Mask: 0x1f)                        */
41529 /* ========================================================  FIFOTHR  ======================================================== */
41530 #define IOSLAVE_FIFOTHR_FIFOTHR_Pos       (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
41531 #define IOSLAVE_FIFOTHR_FIFOTHR_Msk       (0xffUL)                  /*!< FIFOTHR (Bitfield-Mask: 0xff)                         */
41532 /* =========================================================  FUPD  ========================================================== */
41533 #define IOSLAVE_FUPD_IOREAD_Pos           (1UL)                     /*!< IOREAD (Bit 1)                                        */
41534 #define IOSLAVE_FUPD_IOREAD_Msk           (0x2UL)                   /*!< IOREAD (Bitfield-Mask: 0x01)                          */
41535 #define IOSLAVE_FUPD_FIFOUPD_Pos          (0UL)                     /*!< FIFOUPD (Bit 0)                                       */
41536 #define IOSLAVE_FUPD_FIFOUPD_Msk          (0x1UL)                   /*!< FIFOUPD (Bitfield-Mask: 0x01)                         */
41537 /* ========================================================  FIFOCTR  ======================================================== */
41538 #define IOSLAVE_FIFOCTR_FIFOCTR_Pos       (0UL)                     /*!< FIFOCTR (Bit 0)                                       */
41539 #define IOSLAVE_FIFOCTR_FIFOCTR_Msk       (0x3ffUL)                 /*!< FIFOCTR (Bitfield-Mask: 0x3ff)                        */
41540 /* ========================================================  FIFOINC  ======================================================== */
41541 #define IOSLAVE_FIFOINC_FIFOINC_Pos       (0UL)                     /*!< FIFOINC (Bit 0)                                       */
41542 #define IOSLAVE_FIFOINC_FIFOINC_Msk       (0x3ffUL)                 /*!< FIFOINC (Bitfield-Mask: 0x3ff)                        */
41543 /* ==========================================================  CFG  ========================================================== */
41544 #define IOSLAVE_CFG_IFCEN_Pos             (31UL)                    /*!< IFCEN (Bit 31)                                        */
41545 #define IOSLAVE_CFG_IFCEN_Msk             (0x80000000UL)            /*!< IFCEN (Bitfield-Mask: 0x01)                           */
41546 #define IOSLAVE_CFG_WRAPPTR_Pos           (20UL)                    /*!< WRAPPTR (Bit 20)                                      */
41547 #define IOSLAVE_CFG_WRAPPTR_Msk           (0x100000UL)              /*!< WRAPPTR (Bitfield-Mask: 0x01)                         */
41548 #define IOSLAVE_CFG_I2CADDR_Pos           (8UL)                     /*!< I2CADDR (Bit 8)                                       */
41549 #define IOSLAVE_CFG_I2CADDR_Msk           (0xfff00UL)               /*!< I2CADDR (Bitfield-Mask: 0xfff)                        */
41550 #define IOSLAVE_CFG_STARTRD_Pos           (4UL)                     /*!< STARTRD (Bit 4)                                       */
41551 #define IOSLAVE_CFG_STARTRD_Msk           (0x10UL)                  /*!< STARTRD (Bitfield-Mask: 0x01)                         */
41552 #define IOSLAVE_CFG_LSB_Pos               (2UL)                     /*!< LSB (Bit 2)                                           */
41553 #define IOSLAVE_CFG_LSB_Msk               (0x4UL)                   /*!< LSB (Bitfield-Mask: 0x01)                             */
41554 #define IOSLAVE_CFG_SPOL_Pos              (1UL)                     /*!< SPOL (Bit 1)                                          */
41555 #define IOSLAVE_CFG_SPOL_Msk              (0x2UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
41556 #define IOSLAVE_CFG_IFCSEL_Pos            (0UL)                     /*!< IFCSEL (Bit 0)                                        */
41557 #define IOSLAVE_CFG_IFCSEL_Msk            (0x1UL)                   /*!< IFCSEL (Bitfield-Mask: 0x01)                          */
41558 /* =========================================================  PRENC  ========================================================= */
41559 #define IOSLAVE_PRENC_PRENC_Pos           (0UL)                     /*!< PRENC (Bit 0)                                         */
41560 #define IOSLAVE_PRENC_PRENC_Msk           (0x1fUL)                  /*!< PRENC (Bitfield-Mask: 0x1f)                           */
41561 /* =======================================================  IOINTCTL  ======================================================== */
41562 #define IOSLAVE_IOINTCTL_IOINTSET_Pos     (24UL)                    /*!< IOINTSET (Bit 24)                                     */
41563 #define IOSLAVE_IOINTCTL_IOINTSET_Msk     (0xff000000UL)            /*!< IOINTSET (Bitfield-Mask: 0xff)                        */
41564 #define IOSLAVE_IOINTCTL_IOINTCLR_Pos     (16UL)                    /*!< IOINTCLR (Bit 16)                                     */
41565 #define IOSLAVE_IOINTCTL_IOINTCLR_Msk     (0x10000UL)               /*!< IOINTCLR (Bitfield-Mask: 0x01)                        */
41566 #define IOSLAVE_IOINTCTL_IOINT_Pos        (8UL)                     /*!< IOINT (Bit 8)                                         */
41567 #define IOSLAVE_IOINTCTL_IOINT_Msk        (0xff00UL)                /*!< IOINT (Bitfield-Mask: 0xff)                           */
41568 #define IOSLAVE_IOINTCTL_IOINTEN_Pos      (0UL)                     /*!< IOINTEN (Bit 0)                                       */
41569 #define IOSLAVE_IOINTCTL_IOINTEN_Msk      (0xffUL)                  /*!< IOINTEN (Bitfield-Mask: 0xff)                         */
41570 /* ========================================================  GENADD  ========================================================= */
41571 #define IOSLAVE_GENADD_GADATA_Pos         (0UL)                     /*!< GADATA (Bit 0)                                        */
41572 #define IOSLAVE_GENADD_GADATA_Msk         (0xffUL)                  /*!< GADATA (Bitfield-Mask: 0xff)                          */
41573 /* ========================================================  ADDPTR  ========================================================= */
41574 #define IOSLAVE_ADDPTR_ADDPTR_Pos         (0UL)                     /*!< ADDPTR (Bit 0)                                        */
41575 #define IOSLAVE_ADDPTR_ADDPTR_Msk         (0xffUL)                  /*!< ADDPTR (Bitfield-Mask: 0xff)                          */
41576 /* =========================================================  INTEN  ========================================================= */
41577 #define IOSLAVE_INTEN_XCMPWR_Pos          (9UL)                     /*!< XCMPWR (Bit 9)                                        */
41578 #define IOSLAVE_INTEN_XCMPWR_Msk          (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
41579 #define IOSLAVE_INTEN_XCMPWF_Pos          (8UL)                     /*!< XCMPWF (Bit 8)                                        */
41580 #define IOSLAVE_INTEN_XCMPWF_Msk          (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
41581 #define IOSLAVE_INTEN_XCMPRR_Pos          (7UL)                     /*!< XCMPRR (Bit 7)                                        */
41582 #define IOSLAVE_INTEN_XCMPRR_Msk          (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
41583 #define IOSLAVE_INTEN_XCMPRF_Pos          (6UL)                     /*!< XCMPRF (Bit 6)                                        */
41584 #define IOSLAVE_INTEN_XCMPRF_Msk          (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
41585 #define IOSLAVE_INTEN_IOINTW_Pos          (5UL)                     /*!< IOINTW (Bit 5)                                        */
41586 #define IOSLAVE_INTEN_IOINTW_Msk          (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
41587 #define IOSLAVE_INTEN_GENAD_Pos           (4UL)                     /*!< GENAD (Bit 4)                                         */
41588 #define IOSLAVE_INTEN_GENAD_Msk           (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
41589 #define IOSLAVE_INTEN_FRDERR_Pos          (3UL)                     /*!< FRDERR (Bit 3)                                        */
41590 #define IOSLAVE_INTEN_FRDERR_Msk          (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
41591 #define IOSLAVE_INTEN_FUNDFL_Pos          (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41592 #define IOSLAVE_INTEN_FUNDFL_Msk          (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41593 #define IOSLAVE_INTEN_FOVFL_Pos           (1UL)                     /*!< FOVFL (Bit 1)                                         */
41594 #define IOSLAVE_INTEN_FOVFL_Msk           (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41595 #define IOSLAVE_INTEN_FSIZE_Pos           (0UL)                     /*!< FSIZE (Bit 0)                                         */
41596 #define IOSLAVE_INTEN_FSIZE_Msk           (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
41597 /* ========================================================  INTSTAT  ======================================================== */
41598 #define IOSLAVE_INTSTAT_XCMPWR_Pos        (9UL)                     /*!< XCMPWR (Bit 9)                                        */
41599 #define IOSLAVE_INTSTAT_XCMPWR_Msk        (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
41600 #define IOSLAVE_INTSTAT_XCMPWF_Pos        (8UL)                     /*!< XCMPWF (Bit 8)                                        */
41601 #define IOSLAVE_INTSTAT_XCMPWF_Msk        (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
41602 #define IOSLAVE_INTSTAT_XCMPRR_Pos        (7UL)                     /*!< XCMPRR (Bit 7)                                        */
41603 #define IOSLAVE_INTSTAT_XCMPRR_Msk        (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
41604 #define IOSLAVE_INTSTAT_XCMPRF_Pos        (6UL)                     /*!< XCMPRF (Bit 6)                                        */
41605 #define IOSLAVE_INTSTAT_XCMPRF_Msk        (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
41606 #define IOSLAVE_INTSTAT_IOINTW_Pos        (5UL)                     /*!< IOINTW (Bit 5)                                        */
41607 #define IOSLAVE_INTSTAT_IOINTW_Msk        (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
41608 #define IOSLAVE_INTSTAT_GENAD_Pos         (4UL)                     /*!< GENAD (Bit 4)                                         */
41609 #define IOSLAVE_INTSTAT_GENAD_Msk         (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
41610 #define IOSLAVE_INTSTAT_FRDERR_Pos        (3UL)                     /*!< FRDERR (Bit 3)                                        */
41611 #define IOSLAVE_INTSTAT_FRDERR_Msk        (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
41612 #define IOSLAVE_INTSTAT_FUNDFL_Pos        (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41613 #define IOSLAVE_INTSTAT_FUNDFL_Msk        (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41614 #define IOSLAVE_INTSTAT_FOVFL_Pos         (1UL)                     /*!< FOVFL (Bit 1)                                         */
41615 #define IOSLAVE_INTSTAT_FOVFL_Msk         (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41616 #define IOSLAVE_INTSTAT_FSIZE_Pos         (0UL)                     /*!< FSIZE (Bit 0)                                         */
41617 #define IOSLAVE_INTSTAT_FSIZE_Msk         (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
41618 /* ========================================================  INTCLR  ========================================================= */
41619 #define IOSLAVE_INTCLR_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
41620 #define IOSLAVE_INTCLR_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
41621 #define IOSLAVE_INTCLR_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
41622 #define IOSLAVE_INTCLR_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
41623 #define IOSLAVE_INTCLR_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
41624 #define IOSLAVE_INTCLR_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
41625 #define IOSLAVE_INTCLR_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
41626 #define IOSLAVE_INTCLR_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
41627 #define IOSLAVE_INTCLR_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
41628 #define IOSLAVE_INTCLR_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
41629 #define IOSLAVE_INTCLR_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
41630 #define IOSLAVE_INTCLR_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
41631 #define IOSLAVE_INTCLR_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
41632 #define IOSLAVE_INTCLR_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
41633 #define IOSLAVE_INTCLR_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41634 #define IOSLAVE_INTCLR_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41635 #define IOSLAVE_INTCLR_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
41636 #define IOSLAVE_INTCLR_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41637 #define IOSLAVE_INTCLR_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
41638 #define IOSLAVE_INTCLR_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
41639 /* ========================================================  INTSET  ========================================================= */
41640 #define IOSLAVE_INTSET_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
41641 #define IOSLAVE_INTSET_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
41642 #define IOSLAVE_INTSET_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
41643 #define IOSLAVE_INTSET_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
41644 #define IOSLAVE_INTSET_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
41645 #define IOSLAVE_INTSET_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
41646 #define IOSLAVE_INTSET_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
41647 #define IOSLAVE_INTSET_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
41648 #define IOSLAVE_INTSET_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
41649 #define IOSLAVE_INTSET_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
41650 #define IOSLAVE_INTSET_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
41651 #define IOSLAVE_INTSET_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
41652 #define IOSLAVE_INTSET_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
41653 #define IOSLAVE_INTSET_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
41654 #define IOSLAVE_INTSET_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
41655 #define IOSLAVE_INTSET_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
41656 #define IOSLAVE_INTSET_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
41657 #define IOSLAVE_INTSET_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
41658 #define IOSLAVE_INTSET_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
41659 #define IOSLAVE_INTSET_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
41660 /* ======================================================  REGACCINTEN  ====================================================== */
41661 #define IOSLAVE_REGACCINTEN_REGACC_Pos    (0UL)                     /*!< REGACC (Bit 0)                                        */
41662 #define IOSLAVE_REGACCINTEN_REGACC_Msk    (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
41663 /* =====================================================  REGACCINTSTAT  ===================================================== */
41664 #define IOSLAVE_REGACCINTSTAT_REGACC_Pos  (0UL)                     /*!< REGACC (Bit 0)                                        */
41665 #define IOSLAVE_REGACCINTSTAT_REGACC_Msk  (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
41666 /* =====================================================  REGACCINTCLR  ====================================================== */
41667 #define IOSLAVE_REGACCINTCLR_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
41668 #define IOSLAVE_REGACCINTCLR_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
41669 /* =====================================================  REGACCINTSET  ====================================================== */
41670 #define IOSLAVE_REGACCINTSET_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
41671 #define IOSLAVE_REGACCINTSET_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
41672 
41673 
41674 /* =========================================================================================================================== */
41675 /* ================                                          MCUCTRL                                          ================ */
41676 /* =========================================================================================================================== */
41677 
41678 /* ========================================================  CHIPPN  ========================================================= */
41679 #define MCUCTRL_CHIPPN_PN_Pos             (24UL)                    /*!< PN (Bit 24)                                           */
41680 #define MCUCTRL_CHIPPN_PN_Msk             (0xff000000UL)            /*!< PN (Bitfield-Mask: 0xff)                              */
41681 #define MCUCTRL_CHIPPN_MRAMSIZE_Pos       (20UL)                    /*!< MRAMSIZE (Bit 20)                                     */
41682 #define MCUCTRL_CHIPPN_MRAMSIZE_Msk       (0xf00000UL)              /*!< MRAMSIZE (Bitfield-Mask: 0x0f)                        */
41683 #define MCUCTRL_CHIPPN_SRAMSIZE_Pos       (16UL)                    /*!< SRAMSIZE (Bit 16)                                     */
41684 #define MCUCTRL_CHIPPN_SRAMSIZE_Msk       (0xf0000UL)               /*!< SRAMSIZE (Bitfield-Mask: 0x0f)                        */
41685 #define MCUCTRL_CHIPPN_REVMAJ_Pos         (12UL)                    /*!< REVMAJ (Bit 12)                                       */
41686 #define MCUCTRL_CHIPPN_REVMAJ_Msk         (0xf000UL)                /*!< REVMAJ (Bitfield-Mask: 0x0f)                          */
41687 #define MCUCTRL_CHIPPN_REVMIN_Pos         (8UL)                     /*!< REVMIN (Bit 8)                                        */
41688 #define MCUCTRL_CHIPPN_REVMIN_Msk         (0xf00UL)                 /*!< REVMIN (Bitfield-Mask: 0x0f)                          */
41689 #define MCUCTRL_CHIPPN_PKG_Pos            (6UL)                     /*!< PKG (Bit 6)                                           */
41690 #define MCUCTRL_CHIPPN_PKG_Msk            (0xc0UL)                  /*!< PKG (Bitfield-Mask: 0x03)                             */
41691 #define MCUCTRL_CHIPPN_PINS_Pos           (3UL)                     /*!< PINS (Bit 3)                                          */
41692 #define MCUCTRL_CHIPPN_PINS_Msk           (0x38UL)                  /*!< PINS (Bitfield-Mask: 0x07)                            */
41693 #define MCUCTRL_CHIPPN_TEMP_Pos           (1UL)                     /*!< TEMP (Bit 1)                                          */
41694 #define MCUCTRL_CHIPPN_TEMP_Msk           (0x6UL)                   /*!< TEMP (Bitfield-Mask: 0x03)                            */
41695 /* ========================================================  CHIPID0  ======================================================== */
41696 #define MCUCTRL_CHIPID0_CHIPID0_Pos       (0UL)                     /*!< CHIPID0 (Bit 0)                                       */
41697 #define MCUCTRL_CHIPID0_CHIPID0_Msk       (0xffffffffUL)            /*!< CHIPID0 (Bitfield-Mask: 0xffffffff)                   */
41698 /* ========================================================  CHIPID1  ======================================================== */
41699 #define MCUCTRL_CHIPID1_CHIPID1_Pos       (0UL)                     /*!< CHIPID1 (Bit 0)                                       */
41700 #define MCUCTRL_CHIPID1_CHIPID1_Msk       (0xffffffffUL)            /*!< CHIPID1 (Bitfield-Mask: 0xffffffff)                   */
41701 /* ========================================================  CHIPREV  ======================================================== */
41702 #define MCUCTRL_CHIPREV_SIPART_Pos        (8UL)                     /*!< SIPART (Bit 8)                                        */
41703 #define MCUCTRL_CHIPREV_SIPART_Msk        (0xfff00UL)               /*!< SIPART (Bitfield-Mask: 0xfff)                         */
41704 #define MCUCTRL_CHIPREV_REVMAJ_Pos        (4UL)                     /*!< REVMAJ (Bit 4)                                        */
41705 #define MCUCTRL_CHIPREV_REVMAJ_Msk        (0xf0UL)                  /*!< REVMAJ (Bitfield-Mask: 0x0f)                          */
41706 #define MCUCTRL_CHIPREV_REVMIN_Pos        (0UL)                     /*!< REVMIN (Bit 0)                                        */
41707 #define MCUCTRL_CHIPREV_REVMIN_Msk        (0xfUL)                   /*!< REVMIN (Bitfield-Mask: 0x0f)                          */
41708 /* =======================================================  VENDORID  ======================================================== */
41709 #define MCUCTRL_VENDORID_VENDORID_Pos     (0UL)                     /*!< VENDORID (Bit 0)                                      */
41710 #define MCUCTRL_VENDORID_VENDORID_Msk     (0xffffffffUL)            /*!< VENDORID (Bitfield-Mask: 0xffffffff)                  */
41711 /* ==========================================================  SKU  ========================================================== */
41712 #define MCUCTRL_SKU_SKUSECURESPOT_Pos     (10UL)                    /*!< SKUSECURESPOT (Bit 10)                                */
41713 #define MCUCTRL_SKU_SKUSECURESPOT_Msk     (0x400UL)                 /*!< SKUSECURESPOT (Bitfield-Mask: 0x01)                   */
41714 #define MCUCTRL_SKU_SKUUSB_Pos            (9UL)                     /*!< SKUUSB (Bit 9)                                        */
41715 #define MCUCTRL_SKU_SKUUSB_Msk            (0x200UL)                 /*!< SKUUSB (Bitfield-Mask: 0x01)                          */
41716 #define MCUCTRL_SKU_SKUGFX_Pos            (8UL)                     /*!< SKUGFX (Bit 8)                                        */
41717 #define MCUCTRL_SKU_SKUGFX_Msk            (0x100UL)                 /*!< SKUGFX (Bitfield-Mask: 0x01)                          */
41718 #define MCUCTRL_SKU_SKUMIPIDSI_Pos        (7UL)                     /*!< SKUMIPIDSI (Bit 7)                                    */
41719 #define MCUCTRL_SKU_SKUMIPIDSI_Msk        (0x80UL)                  /*!< SKUMIPIDSI (Bitfield-Mask: 0x01)                      */
41720 #define MCUCTRL_SKU_SKUTURBOSPOT_Pos      (6UL)                     /*!< SKUTURBOSPOT (Bit 6)                                  */
41721 #define MCUCTRL_SKU_SKUTURBOSPOT_Msk      (0x40UL)                  /*!< SKUTURBOSPOT (Bitfield-Mask: 0x01)                    */
41722 #define MCUCTRL_SKU_SKUDSP_Pos            (4UL)                     /*!< SKUDSP (Bit 4)                                        */
41723 #define MCUCTRL_SKU_SKUDSP_Msk            (0x30UL)                  /*!< SKUDSP (Bitfield-Mask: 0x03)                          */
41724 #define MCUCTRL_SKU_SKUMRAMSIZE_Pos       (2UL)                     /*!< SKUMRAMSIZE (Bit 2)                                   */
41725 #define MCUCTRL_SKU_SKUMRAMSIZE_Msk       (0xcUL)                   /*!< SKUMRAMSIZE (Bitfield-Mask: 0x03)                     */
41726 #define MCUCTRL_SKU_SKUSRAMSIZE_Pos       (0UL)                     /*!< SKUSRAMSIZE (Bit 0)                                   */
41727 #define MCUCTRL_SKU_SKUSRAMSIZE_Msk       (0x3UL)                   /*!< SKUSRAMSIZE (Bitfield-Mask: 0x03)                     */
41728 /* =======================================================  DEBUGGER  ======================================================== */
41729 #define MCUCTRL_DEBUGGER_LOCKOUT_Pos      (0UL)                     /*!< LOCKOUT (Bit 0)                                       */
41730 #define MCUCTRL_DEBUGGER_LOCKOUT_Msk      (0xffffffffUL)            /*!< LOCKOUT (Bitfield-Mask: 0xffffffff)                   */
41731 /* =========================================================  ACRG  ========================================================== */
41732 #define MCUCTRL_ACRG_ACRGTRIM_Pos         (3UL)                     /*!< ACRGTRIM (Bit 3)                                      */
41733 #define MCUCTRL_ACRG_ACRGTRIM_Msk         (0xf8UL)                  /*!< ACRGTRIM (Bitfield-Mask: 0x1f)                        */
41734 #define MCUCTRL_ACRG_ACRGIBIASSEL_Pos     (2UL)                     /*!< ACRGIBIASSEL (Bit 2)                                  */
41735 #define MCUCTRL_ACRG_ACRGIBIASSEL_Msk     (0x4UL)                   /*!< ACRGIBIASSEL (Bitfield-Mask: 0x01)                    */
41736 #define MCUCTRL_ACRG_ACRGPWD_Pos          (1UL)                     /*!< ACRGPWD (Bit 1)                                       */
41737 #define MCUCTRL_ACRG_ACRGPWD_Msk          (0x2UL)                   /*!< ACRGPWD (Bitfield-Mask: 0x01)                         */
41738 #define MCUCTRL_ACRG_ACRGSWE_Pos          (0UL)                     /*!< ACRGSWE (Bit 0)                                       */
41739 #define MCUCTRL_ACRG_ACRGSWE_Msk          (0x1UL)                   /*!< ACRGSWE (Bitfield-Mask: 0x01)                         */
41740 /* =======================================================  VREFGEN2  ======================================================== */
41741 #define MCUCTRL_VREFGEN2_TVRG2SELVREF_Pos (29UL)                    /*!< TVRG2SELVREF (Bit 29)                                 */
41742 #define MCUCTRL_VREFGEN2_TVRG2SELVREF_Msk (0x20000000UL)            /*!< TVRG2SELVREF (Bitfield-Mask: 0x01)                    */
41743 #define MCUCTRL_VREFGEN2_TVRGSELVREF_Pos  (28UL)                    /*!< TVRGSELVREF (Bit 28)                                  */
41744 #define MCUCTRL_VREFGEN2_TVRGSELVREF_Msk  (0x10000000UL)            /*!< TVRGSELVREF (Bitfield-Mask: 0x01)                     */
41745 #define MCUCTRL_VREFGEN2_TVRG2VREFTRIM_Pos (21UL)                   /*!< TVRG2VREFTRIM (Bit 21)                                */
41746 #define MCUCTRL_VREFGEN2_TVRG2VREFTRIM_Msk (0xfe00000UL)            /*!< TVRG2VREFTRIM (Bitfield-Mask: 0x7f)                   */
41747 #define MCUCTRL_VREFGEN2_TVRG2CURRENTTRIM_Pos (20UL)                /*!< TVRG2CURRENTTRIM (Bit 20)                             */
41748 #define MCUCTRL_VREFGEN2_TVRG2CURRENTTRIM_Msk (0x100000UL)          /*!< TVRG2CURRENTTRIM (Bitfield-Mask: 0x01)                */
41749 #define MCUCTRL_VREFGEN2_TVRG2PWD_Pos     (19UL)                    /*!< TVRG2PWD (Bit 19)                                     */
41750 #define MCUCTRL_VREFGEN2_TVRG2PWD_Msk     (0x80000UL)               /*!< TVRG2PWD (Bitfield-Mask: 0x01)                        */
41751 #define MCUCTRL_VREFGEN2_TVRG2TEMPCOTRIM_Pos (14UL)                 /*!< TVRG2TEMPCOTRIM (Bit 14)                              */
41752 #define MCUCTRL_VREFGEN2_TVRG2TEMPCOTRIM_Msk (0x7c000UL)            /*!< TVRG2TEMPCOTRIM (Bitfield-Mask: 0x1f)                 */
41753 #define MCUCTRL_VREFGEN2_TVRGVREFTRIM_Pos (7UL)                     /*!< TVRGVREFTRIM (Bit 7)                                  */
41754 #define MCUCTRL_VREFGEN2_TVRGVREFTRIM_Msk (0x3f80UL)                /*!< TVRGVREFTRIM (Bitfield-Mask: 0x7f)                    */
41755 #define MCUCTRL_VREFGEN2_TVRGCURRENTTRIM_Pos (6UL)                  /*!< TVRGCURRENTTRIM (Bit 6)                               */
41756 #define MCUCTRL_VREFGEN2_TVRGCURRENTTRIM_Msk (0x40UL)               /*!< TVRGCURRENTTRIM (Bitfield-Mask: 0x01)                 */
41757 #define MCUCTRL_VREFGEN2_TVRGPWD_Pos      (5UL)                     /*!< TVRGPWD (Bit 5)                                       */
41758 #define MCUCTRL_VREFGEN2_TVRGPWD_Msk      (0x20UL)                  /*!< TVRGPWD (Bitfield-Mask: 0x01)                         */
41759 #define MCUCTRL_VREFGEN2_TVRGTEMPCOTRIM_Pos (0UL)                   /*!< TVRGTEMPCOTRIM (Bit 0)                                */
41760 #define MCUCTRL_VREFGEN2_TVRGTEMPCOTRIM_Msk (0x1fUL)                /*!< TVRGTEMPCOTRIM (Bitfield-Mask: 0x1f)                  */
41761 /* ========================================================  VRCTRL  ========================================================= */
41762 #define MCUCTRL_VRCTRL_SIMOBUCKACTIVE_Pos (19UL)                    /*!< SIMOBUCKACTIVE (Bit 19)                               */
41763 #define MCUCTRL_VRCTRL_SIMOBUCKACTIVE_Msk (0x80000UL)               /*!< SIMOBUCKACTIVE (Bitfield-Mask: 0x01)                  */
41764 #define MCUCTRL_VRCTRL_SIMOBUCKRSTB_Pos   (18UL)                    /*!< SIMOBUCKRSTB (Bit 18)                                 */
41765 #define MCUCTRL_VRCTRL_SIMOBUCKRSTB_Msk   (0x40000UL)               /*!< SIMOBUCKRSTB (Bitfield-Mask: 0x01)                    */
41766 #define MCUCTRL_VRCTRL_SIMOBUCKPDNB_Pos   (17UL)                    /*!< SIMOBUCKPDNB (Bit 17)                                 */
41767 #define MCUCTRL_VRCTRL_SIMOBUCKPDNB_Msk   (0x20000UL)               /*!< SIMOBUCKPDNB (Bitfield-Mask: 0x01)                    */
41768 #define MCUCTRL_VRCTRL_SIMOBUCKOVER_Pos   (16UL)                    /*!< SIMOBUCKOVER (Bit 16)                                 */
41769 #define MCUCTRL_VRCTRL_SIMOBUCKOVER_Msk   (0x10000UL)               /*!< SIMOBUCKOVER (Bitfield-Mask: 0x01)                    */
41770 #define MCUCTRL_VRCTRL_ANALDOACTIVE_Pos   (15UL)                    /*!< ANALDOACTIVE (Bit 15)                                 */
41771 #define MCUCTRL_VRCTRL_ANALDOACTIVE_Msk   (0x8000UL)                /*!< ANALDOACTIVE (Bitfield-Mask: 0x01)                    */
41772 #define MCUCTRL_VRCTRL_ANALDOPDNB_Pos     (14UL)                    /*!< ANALDOPDNB (Bit 14)                                   */
41773 #define MCUCTRL_VRCTRL_ANALDOPDNB_Msk     (0x4000UL)                /*!< ANALDOPDNB (Bitfield-Mask: 0x01)                      */
41774 #define MCUCTRL_VRCTRL_ANALDOOVER_Pos     (13UL)                    /*!< ANALDOOVER (Bit 13)                                   */
41775 #define MCUCTRL_VRCTRL_ANALDOOVER_Msk     (0x2000UL)                /*!< ANALDOOVER (Bitfield-Mask: 0x01)                      */
41776 #define MCUCTRL_VRCTRL_MEMLPLDOACTIVE_Pos (12UL)                    /*!< MEMLPLDOACTIVE (Bit 12)                               */
41777 #define MCUCTRL_VRCTRL_MEMLPLDOACTIVE_Msk (0x1000UL)                /*!< MEMLPLDOACTIVE (Bitfield-Mask: 0x01)                  */
41778 #define MCUCTRL_VRCTRL_MEMLPLDOPDNB_Pos   (11UL)                    /*!< MEMLPLDOPDNB (Bit 11)                                 */
41779 #define MCUCTRL_VRCTRL_MEMLPLDOPDNB_Msk   (0x800UL)                 /*!< MEMLPLDOPDNB (Bitfield-Mask: 0x01)                    */
41780 #define MCUCTRL_VRCTRL_MEMLPLDOOVER_Pos   (10UL)                    /*!< MEMLPLDOOVER (Bit 10)                                 */
41781 #define MCUCTRL_VRCTRL_MEMLPLDOOVER_Msk   (0x400UL)                 /*!< MEMLPLDOOVER (Bitfield-Mask: 0x01)                    */
41782 #define MCUCTRL_VRCTRL_MEMLDOCOLDSTARTEN_Pos (9UL)                  /*!< MEMLDOCOLDSTARTEN (Bit 9)                             */
41783 #define MCUCTRL_VRCTRL_MEMLDOCOLDSTARTEN_Msk (0x200UL)              /*!< MEMLDOCOLDSTARTEN (Bitfield-Mask: 0x01)               */
41784 #define MCUCTRL_VRCTRL_MEMLDOACTIVE_Pos   (8UL)                     /*!< MEMLDOACTIVE (Bit 8)                                  */
41785 #define MCUCTRL_VRCTRL_MEMLDOACTIVE_Msk   (0x100UL)                 /*!< MEMLDOACTIVE (Bitfield-Mask: 0x01)                    */
41786 #define MCUCTRL_VRCTRL_MEMLDOACTIVEEARLY_Pos (7UL)                  /*!< MEMLDOACTIVEEARLY (Bit 7)                             */
41787 #define MCUCTRL_VRCTRL_MEMLDOACTIVEEARLY_Msk (0x80UL)               /*!< MEMLDOACTIVEEARLY (Bitfield-Mask: 0x01)               */
41788 #define MCUCTRL_VRCTRL_MEMLDOPDNB_Pos     (6UL)                     /*!< MEMLDOPDNB (Bit 6)                                    */
41789 #define MCUCTRL_VRCTRL_MEMLDOPDNB_Msk     (0x40UL)                  /*!< MEMLDOPDNB (Bitfield-Mask: 0x01)                      */
41790 #define MCUCTRL_VRCTRL_MEMLDOOVER_Pos     (5UL)                     /*!< MEMLDOOVER (Bit 5)                                    */
41791 #define MCUCTRL_VRCTRL_MEMLDOOVER_Msk     (0x20UL)                  /*!< MEMLDOOVER (Bitfield-Mask: 0x01)                      */
41792 #define MCUCTRL_VRCTRL_CORELDOCOLDSTARTEN_Pos (4UL)                 /*!< CORELDOCOLDSTARTEN (Bit 4)                            */
41793 #define MCUCTRL_VRCTRL_CORELDOCOLDSTARTEN_Msk (0x10UL)              /*!< CORELDOCOLDSTARTEN (Bitfield-Mask: 0x01)              */
41794 #define MCUCTRL_VRCTRL_CORELDOACTIVE_Pos  (3UL)                     /*!< CORELDOACTIVE (Bit 3)                                 */
41795 #define MCUCTRL_VRCTRL_CORELDOACTIVE_Msk  (0x8UL)                   /*!< CORELDOACTIVE (Bitfield-Mask: 0x01)                   */
41796 #define MCUCTRL_VRCTRL_CORELDOACTIVEEARLY_Pos (2UL)                 /*!< CORELDOACTIVEEARLY (Bit 2)                            */
41797 #define MCUCTRL_VRCTRL_CORELDOACTIVEEARLY_Msk (0x4UL)               /*!< CORELDOACTIVEEARLY (Bitfield-Mask: 0x01)              */
41798 #define MCUCTRL_VRCTRL_CORELDOPDNB_Pos    (1UL)                     /*!< CORELDOPDNB (Bit 1)                                   */
41799 #define MCUCTRL_VRCTRL_CORELDOPDNB_Msk    (0x2UL)                   /*!< CORELDOPDNB (Bitfield-Mask: 0x01)                     */
41800 #define MCUCTRL_VRCTRL_CORELDOOVER_Pos    (0UL)                     /*!< CORELDOOVER (Bit 0)                                   */
41801 #define MCUCTRL_VRCTRL_CORELDOOVER_Msk    (0x1UL)                   /*!< CORELDOOVER (Bitfield-Mask: 0x01)                     */
41802 /* ========================================================  LDOREG1  ======================================================== */
41803 #define MCUCTRL_LDOREG1_CORELDOIBIASSEL_Pos (21UL)                  /*!< CORELDOIBIASSEL (Bit 21)                              */
41804 #define MCUCTRL_LDOREG1_CORELDOIBIASSEL_Msk (0x200000UL)            /*!< CORELDOIBIASSEL (Bitfield-Mask: 0x01)                 */
41805 #define MCUCTRL_LDOREG1_CORELDOIBIASTRIM_Pos (20UL)                 /*!< CORELDOIBIASTRIM (Bit 20)                             */
41806 #define MCUCTRL_LDOREG1_CORELDOIBIASTRIM_Msk (0x100000UL)           /*!< CORELDOIBIASTRIM (Bitfield-Mask: 0x01)                */
41807 #define MCUCTRL_LDOREG1_CORELDOLPTRIM_Pos (14UL)                    /*!< CORELDOLPTRIM (Bit 14)                                */
41808 #define MCUCTRL_LDOREG1_CORELDOLPTRIM_Msk (0xfc000UL)               /*!< CORELDOLPTRIM (Bitfield-Mask: 0x3f)                   */
41809 #define MCUCTRL_LDOREG1_CORELDOTEMPCOTRIM_Pos (10UL)                /*!< CORELDOTEMPCOTRIM (Bit 10)                            */
41810 #define MCUCTRL_LDOREG1_CORELDOTEMPCOTRIM_Msk (0x3c00UL)            /*!< CORELDOTEMPCOTRIM (Bitfield-Mask: 0x0f)               */
41811 #define MCUCTRL_LDOREG1_CORELDOACTIVETRIM_Pos (0UL)                 /*!< CORELDOACTIVETRIM (Bit 0)                             */
41812 #define MCUCTRL_LDOREG1_CORELDOACTIVETRIM_Msk (0x3ffUL)             /*!< CORELDOACTIVETRIM (Bitfield-Mask: 0x3ff)              */
41813 /* ========================================================  LDOREG2  ======================================================== */
41814 #define MCUCTRL_LDOREG2_TRIMANALDO_Pos    (26UL)                    /*!< TRIMANALDO (Bit 26)                                   */
41815 #define MCUCTRL_LDOREG2_TRIMANALDO_Msk    (0x3c000000UL)            /*!< TRIMANALDO (Bitfield-Mask: 0x0f)                      */
41816 #define MCUCTRL_LDOREG2_MEMLDOIBIASSEL_Pos (25UL)                   /*!< MEMLDOIBIASSEL (Bit 25)                               */
41817 #define MCUCTRL_LDOREG2_MEMLDOIBIASSEL_Msk (0x2000000UL)            /*!< MEMLDOIBIASSEL (Bitfield-Mask: 0x01)                  */
41818 #define MCUCTRL_LDOREG2_MEMLPLDOIBIASTRIM_Pos (24UL)                /*!< MEMLPLDOIBIASTRIM (Bit 24)                            */
41819 #define MCUCTRL_LDOREG2_MEMLPLDOIBIASTRIM_Msk (0x1000000UL)         /*!< MEMLPLDOIBIASTRIM (Bitfield-Mask: 0x01)               */
41820 #define MCUCTRL_LDOREG2_MEMLPLDOTRIM_Pos  (18UL)                    /*!< MEMLPLDOTRIM (Bit 18)                                 */
41821 #define MCUCTRL_LDOREG2_MEMLPLDOTRIM_Msk  (0xfc0000UL)              /*!< MEMLPLDOTRIM (Bitfield-Mask: 0x3f)                    */
41822 #define MCUCTRL_LDOREG2_MEMLDOLPALTTRIM_Pos (12UL)                  /*!< MEMLDOLPALTTRIM (Bit 12)                              */
41823 #define MCUCTRL_LDOREG2_MEMLDOLPALTTRIM_Msk (0x3f000UL)             /*!< MEMLDOLPALTTRIM (Bitfield-Mask: 0x3f)                 */
41824 #define MCUCTRL_LDOREG2_MEMLDOLPTRIM_Pos  (6UL)                     /*!< MEMLDOLPTRIM (Bit 6)                                  */
41825 #define MCUCTRL_LDOREG2_MEMLDOLPTRIM_Msk  (0xfc0UL)                 /*!< MEMLDOLPTRIM (Bitfield-Mask: 0x3f)                    */
41826 #define MCUCTRL_LDOREG2_MEMLDOACTIVETRIM_Pos (0UL)                  /*!< MEMLDOACTIVETRIM (Bit 0)                              */
41827 #define MCUCTRL_LDOREG2_MEMLDOACTIVETRIM_Msk (0x3fUL)               /*!< MEMLDOACTIVETRIM (Bitfield-Mask: 0x3f)                */
41828 /* =========================================================  LFRC  ========================================================== */
41829 #define MCUCTRL_LFRC_LFRCSIMOCLKDIV_Pos   (10UL)                    /*!< LFRCSIMOCLKDIV (Bit 10)                               */
41830 #define MCUCTRL_LFRC_LFRCSIMOCLKDIV_Msk   (0x1c00UL)                /*!< LFRCSIMOCLKDIV (Bitfield-Mask: 0x07)                  */
41831 #define MCUCTRL_LFRC_LFRCITAILTRIM_Pos    (8UL)                     /*!< LFRCITAILTRIM (Bit 8)                                 */
41832 #define MCUCTRL_LFRC_LFRCITAILTRIM_Msk    (0x300UL)                 /*!< LFRCITAILTRIM (Bitfield-Mask: 0x03)                   */
41833 #define MCUCTRL_LFRC_RESETLFRC_Pos        (7UL)                     /*!< RESETLFRC (Bit 7)                                     */
41834 #define MCUCTRL_LFRC_RESETLFRC_Msk        (0x80UL)                  /*!< RESETLFRC (Bitfield-Mask: 0x01)                       */
41835 #define MCUCTRL_LFRC_PWDLFRC_Pos          (6UL)                     /*!< PWDLFRC (Bit 6)                                       */
41836 #define MCUCTRL_LFRC_PWDLFRC_Msk          (0x40UL)                  /*!< PWDLFRC (Bitfield-Mask: 0x01)                         */
41837 #define MCUCTRL_LFRC_TRIMTUNELFRC_Pos     (1UL)                     /*!< TRIMTUNELFRC (Bit 1)                                  */
41838 #define MCUCTRL_LFRC_TRIMTUNELFRC_Msk     (0x3eUL)                  /*!< TRIMTUNELFRC (Bitfield-Mask: 0x1f)                    */
41839 #define MCUCTRL_LFRC_LFRCSWE_Pos          (0UL)                     /*!< LFRCSWE (Bit 0)                                       */
41840 #define MCUCTRL_LFRC_LFRCSWE_Msk          (0x1UL)                   /*!< LFRCSWE (Bitfield-Mask: 0x01)                         */
41841 /* ========================================================  BODCTRL  ======================================================== */
41842 #define MCUCTRL_BODCTRL_BODHVREFSEL_Pos   (7UL)                     /*!< BODHVREFSEL (Bit 7)                                   */
41843 #define MCUCTRL_BODCTRL_BODHVREFSEL_Msk   (0x80UL)                  /*!< BODHVREFSEL (Bitfield-Mask: 0x01)                     */
41844 #define MCUCTRL_BODCTRL_BODLVREFSEL_Pos   (6UL)                     /*!< BODLVREFSEL (Bit 6)                                   */
41845 #define MCUCTRL_BODCTRL_BODLVREFSEL_Msk   (0x40UL)                  /*!< BODLVREFSEL (Bitfield-Mask: 0x01)                     */
41846 #define MCUCTRL_BODCTRL_BODCLVPWD_Pos     (5UL)                     /*!< BODCLVPWD (Bit 5)                                     */
41847 #define MCUCTRL_BODCTRL_BODCLVPWD_Msk     (0x20UL)                  /*!< BODCLVPWD (Bitfield-Mask: 0x01)                       */
41848 #define MCUCTRL_BODCTRL_BODSPWD_Pos       (4UL)                     /*!< BODSPWD (Bit 4)                                       */
41849 #define MCUCTRL_BODCTRL_BODSPWD_Msk       (0x10UL)                  /*!< BODSPWD (Bitfield-Mask: 0x01)                         */
41850 #define MCUCTRL_BODCTRL_BODFPWD_Pos       (3UL)                     /*!< BODFPWD (Bit 3)                                       */
41851 #define MCUCTRL_BODCTRL_BODFPWD_Msk       (0x8UL)                   /*!< BODFPWD (Bitfield-Mask: 0x01)                         */
41852 #define MCUCTRL_BODCTRL_BODCPWD_Pos       (2UL)                     /*!< BODCPWD (Bit 2)                                       */
41853 #define MCUCTRL_BODCTRL_BODCPWD_Msk       (0x4UL)                   /*!< BODCPWD (Bitfield-Mask: 0x01)                         */
41854 #define MCUCTRL_BODCTRL_BODHPWD_Pos       (1UL)                     /*!< BODHPWD (Bit 1)                                       */
41855 #define MCUCTRL_BODCTRL_BODHPWD_Msk       (0x2UL)                   /*!< BODHPWD (Bitfield-Mask: 0x01)                         */
41856 #define MCUCTRL_BODCTRL_BODLPWD_Pos       (0UL)                     /*!< BODLPWD (Bit 0)                                       */
41857 #define MCUCTRL_BODCTRL_BODLPWD_Msk       (0x1UL)                   /*!< BODLPWD (Bitfield-Mask: 0x01)                         */
41858 /* =======================================================  ADCPWRDLY  ======================================================= */
41859 #define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos     (8UL)                     /*!< ADCPWR1 (Bit 8)                                       */
41860 #define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk     (0xff00UL)                /*!< ADCPWR1 (Bitfield-Mask: 0xff)                         */
41861 #define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos     (0UL)                     /*!< ADCPWR0 (Bit 0)                                       */
41862 #define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk     (0xffUL)                  /*!< ADCPWR0 (Bitfield-Mask: 0xff)                         */
41863 /* ======================================================  ADCPWRCTRL  ======================================================= */
41864 #define MCUCTRL_ADCPWRCTRL_ADCKEEPOUTEN_Pos (16UL)                  /*!< ADCKEEPOUTEN (Bit 16)                                 */
41865 #define MCUCTRL_ADCPWRCTRL_ADCKEEPOUTEN_Msk (0x10000UL)             /*!< ADCKEEPOUTEN (Bitfield-Mask: 0x01)                    */
41866 #define MCUCTRL_ADCPWRCTRL_ADCRFBUFSLWEN_Pos (15UL)                 /*!< ADCRFBUFSLWEN (Bit 15)                                */
41867 #define MCUCTRL_ADCPWRCTRL_ADCRFBUFSLWEN_Msk (0x8000UL)             /*!< ADCRFBUFSLWEN (Bitfield-Mask: 0x01)                   */
41868 #define MCUCTRL_ADCPWRCTRL_ADCINBUFEN_Pos (14UL)                    /*!< ADCINBUFEN (Bit 14)                                   */
41869 #define MCUCTRL_ADCPWRCTRL_ADCINBUFEN_Msk (0x4000UL)                /*!< ADCINBUFEN (Bitfield-Mask: 0x01)                      */
41870 #define MCUCTRL_ADCPWRCTRL_ADCINBUFSEL_Pos (12UL)                   /*!< ADCINBUFSEL (Bit 12)                                  */
41871 #define MCUCTRL_ADCPWRCTRL_ADCINBUFSEL_Msk (0x3000UL)               /*!< ADCINBUFSEL (Bitfield-Mask: 0x03)                     */
41872 #define MCUCTRL_ADCPWRCTRL_ADCVBATDIVEN_Pos (11UL)                  /*!< ADCVBATDIVEN (Bit 11)                                 */
41873 #define MCUCTRL_ADCPWRCTRL_ADCVBATDIVEN_Msk (0x800UL)               /*!< ADCVBATDIVEN (Bitfield-Mask: 0x01)                    */
41874 #define MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Pos (9UL)                   /*!< VDDADCRESETN (Bit 9)                                  */
41875 #define MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Msk (0x200UL)               /*!< VDDADCRESETN (Bitfield-Mask: 0x01)                    */
41876 #define MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Pos (8UL)               /*!< VDDADCDIGISOLATE (Bit 8)                              */
41877 #define MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Msk (0x100UL)           /*!< VDDADCDIGISOLATE (Bitfield-Mask: 0x01)                */
41878 #define MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Pos (7UL)               /*!< VDDADCSARISOLATE (Bit 7)                              */
41879 #define MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Msk (0x80UL)            /*!< VDDADCSARISOLATE (Bitfield-Mask: 0x01)                */
41880 #define MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Pos (6UL)                     /*!< REFKEEPPEN (Bit 6)                                    */
41881 #define MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Msk (0x40UL)                  /*!< REFKEEPPEN (Bitfield-Mask: 0x01)                      */
41882 #define MCUCTRL_ADCPWRCTRL_REFBUFPEN_Pos  (5UL)                     /*!< REFBUFPEN (Bit 5)                                     */
41883 #define MCUCTRL_ADCPWRCTRL_REFBUFPEN_Msk  (0x20UL)                  /*!< REFBUFPEN (Bitfield-Mask: 0x01)                       */
41884 #define MCUCTRL_ADCPWRCTRL_BGTLPPEN_Pos   (4UL)                     /*!< BGTLPPEN (Bit 4)                                      */
41885 #define MCUCTRL_ADCPWRCTRL_BGTLPPEN_Msk   (0x10UL)                  /*!< BGTLPPEN (Bitfield-Mask: 0x01)                        */
41886 #define MCUCTRL_ADCPWRCTRL_BGTPEN_Pos     (3UL)                     /*!< BGTPEN (Bit 3)                                        */
41887 #define MCUCTRL_ADCPWRCTRL_BGTPEN_Msk     (0x8UL)                   /*!< BGTPEN (Bitfield-Mask: 0x01)                          */
41888 #define MCUCTRL_ADCPWRCTRL_ADCBPSEN_Pos   (2UL)                     /*!< ADCBPSEN (Bit 2)                                      */
41889 #define MCUCTRL_ADCPWRCTRL_ADCBPSEN_Msk   (0x4UL)                   /*!< ADCBPSEN (Bitfield-Mask: 0x01)                        */
41890 #define MCUCTRL_ADCPWRCTRL_ADCAPSEN_Pos   (1UL)                     /*!< ADCAPSEN (Bit 1)                                      */
41891 #define MCUCTRL_ADCPWRCTRL_ADCAPSEN_Msk   (0x2UL)                   /*!< ADCAPSEN (Bitfield-Mask: 0x01)                        */
41892 #define MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Pos (0UL)                  /*!< ADCPWRCTRLSWE (Bit 0)                                 */
41893 #define MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Msk (0x1UL)                /*!< ADCPWRCTRLSWE (Bitfield-Mask: 0x01)                   */
41894 /* ========================================================  ADCCAL  ========================================================= */
41895 #define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos  (1UL)                     /*!< ADCCALIBRATED (Bit 1)                                 */
41896 #define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk  (0x2UL)                   /*!< ADCCALIBRATED (Bitfield-Mask: 0x01)                   */
41897 #define MCUCTRL_ADCCAL_CALONPWRUP_Pos     (0UL)                     /*!< CALONPWRUP (Bit 0)                                    */
41898 #define MCUCTRL_ADCCAL_CALONPWRUP_Msk     (0x1UL)                   /*!< CALONPWRUP (Bitfield-Mask: 0x01)                      */
41899 /* ======================================================  ADCBATTLOAD  ====================================================== */
41900 #define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos  (0UL)                     /*!< BATTLOAD (Bit 0)                                      */
41901 #define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk  (0x1UL)                   /*!< BATTLOAD (Bitfield-Mask: 0x01)                        */
41902 /* =======================================================  XTALCTRL  ======================================================== */
41903 #define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Pos (7UL)                    /*!< XTALICOMPTRIM (Bit 7)                                 */
41904 #define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Msk (0x180UL)                /*!< XTALICOMPTRIM (Bitfield-Mask: 0x03)                   */
41905 #define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Pos (5UL)                     /*!< XTALIBUFTRIM (Bit 5)                                  */
41906 #define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Msk (0x60UL)                  /*!< XTALIBUFTRIM (Bitfield-Mask: 0x03)                    */
41907 #define MCUCTRL_XTALCTRL_XTALCOMPPDNB_Pos (4UL)                     /*!< XTALCOMPPDNB (Bit 4)                                  */
41908 #define MCUCTRL_XTALCTRL_XTALCOMPPDNB_Msk (0x10UL)                  /*!< XTALCOMPPDNB (Bitfield-Mask: 0x01)                    */
41909 #define MCUCTRL_XTALCTRL_XTALPDNB_Pos     (3UL)                     /*!< XTALPDNB (Bit 3)                                      */
41910 #define MCUCTRL_XTALCTRL_XTALPDNB_Msk     (0x8UL)                   /*!< XTALPDNB (Bitfield-Mask: 0x01)                        */
41911 #define MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Pos (2UL)                   /*!< XTALCOMPBYPASS (Bit 2)                                */
41912 #define MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Msk (0x4UL)                 /*!< XTALCOMPBYPASS (Bitfield-Mask: 0x01)                  */
41913 #define MCUCTRL_XTALCTRL_XTALCOREDISFB_Pos (1UL)                    /*!< XTALCOREDISFB (Bit 1)                                 */
41914 #define MCUCTRL_XTALCTRL_XTALCOREDISFB_Msk (0x2UL)                  /*!< XTALCOREDISFB (Bitfield-Mask: 0x01)                   */
41915 #define MCUCTRL_XTALCTRL_XTALSWE_Pos      (0UL)                     /*!< XTALSWE (Bit 0)                                       */
41916 #define MCUCTRL_XTALCTRL_XTALSWE_Msk      (0x1UL)                   /*!< XTALSWE (Bitfield-Mask: 0x01)                         */
41917 /* ======================================================  XTALGENCTRL  ====================================================== */
41918 #define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL)                /*!< XTALKSBIASTRIM (Bit 8)                                */
41919 #define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL)           /*!< XTALKSBIASTRIM (Bitfield-Mask: 0x3f)                  */
41920 #define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL)                  /*!< XTALBIASTRIM (Bit 2)                                  */
41921 #define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL)               /*!< XTALBIASTRIM (Bitfield-Mask: 0x3f)                    */
41922 #define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos  (0UL)                     /*!< ACWARMUP (Bit 0)                                      */
41923 #define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk  (0x3UL)                   /*!< ACWARMUP (Bitfield-Mask: 0x03)                        */
41924 /* ======================================================  XTALHSTRIMS  ====================================================== */
41925 #define MCUCTRL_XTALHSTRIMS_XTALHSSPARE_Pos (29UL)                  /*!< XTALHSSPARE (Bit 29)                                  */
41926 #define MCUCTRL_XTALHSTRIMS_XTALHSSPARE_Msk (0x20000000UL)          /*!< XTALHSSPARE (Bitfield-Mask: 0x01)                     */
41927 #define MCUCTRL_XTALHSTRIMS_XTALHSRSTRIM_Pos (28UL)                 /*!< XTALHSRSTRIM (Bit 28)                                 */
41928 #define MCUCTRL_XTALHSTRIMS_XTALHSRSTRIM_Msk (0x10000000UL)         /*!< XTALHSRSTRIM (Bitfield-Mask: 0x01)                    */
41929 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASTRIM_Pos (21UL)              /*!< XTALHSIBIASTRIM (Bit 21)                              */
41930 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASTRIM_Msk (0xfe00000UL)       /*!< XTALHSIBIASTRIM (Bitfield-Mask: 0x7f)                 */
41931 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMPTRIM_Pos (17UL)          /*!< XTALHSIBIASCOMPTRIM (Bit 17)                          */
41932 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMPTRIM_Msk (0x1e0000UL)    /*!< XTALHSIBIASCOMPTRIM (Bitfield-Mask: 0x0f)             */
41933 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMP2TRIM_Pos (15UL)         /*!< XTALHSIBIASCOMP2TRIM (Bit 15)                         */
41934 #define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMP2TRIM_Msk (0x18000UL)    /*!< XTALHSIBIASCOMP2TRIM (Bitfield-Mask: 0x03)            */
41935 #define MCUCTRL_XTALHSTRIMS_XTALHSDRIVERSTRENGTH_Pos (12UL)         /*!< XTALHSDRIVERSTRENGTH (Bit 12)                         */
41936 #define MCUCTRL_XTALHSTRIMS_XTALHSDRIVERSTRENGTH_Msk (0x7000UL)     /*!< XTALHSDRIVERSTRENGTH (Bitfield-Mask: 0x07)            */
41937 #define MCUCTRL_XTALHSTRIMS_XTALHSDRIVETRIM_Pos (10UL)              /*!< XTALHSDRIVETRIM (Bit 10)                              */
41938 #define MCUCTRL_XTALHSTRIMS_XTALHSDRIVETRIM_Msk (0xc00UL)           /*!< XTALHSDRIVETRIM (Bitfield-Mask: 0x03)                 */
41939 #define MCUCTRL_XTALHSTRIMS_XTALHSCAPTRIM_Pos (6UL)                 /*!< XTALHSCAPTRIM (Bit 6)                                 */
41940 #define MCUCTRL_XTALHSTRIMS_XTALHSCAPTRIM_Msk (0x3c0UL)             /*!< XTALHSCAPTRIM (Bitfield-Mask: 0x0f)                   */
41941 #define MCUCTRL_XTALHSTRIMS_XTALHSCAP2TRIM_Pos (0UL)                /*!< XTALHSCAP2TRIM (Bit 0)                                */
41942 #define MCUCTRL_XTALHSTRIMS_XTALHSCAP2TRIM_Msk (0x3fUL)             /*!< XTALHSCAP2TRIM (Bitfield-Mask: 0x3f)                  */
41943 /* ======================================================  XTALHSCTRL  ======================================================= */
41944 #define MCUCTRL_XTALHSCTRL_XTALHSEXTERNALCLOCK_Pos (8UL)            /*!< XTALHSEXTERNALCLOCK (Bit 8)                           */
41945 #define MCUCTRL_XTALHSCTRL_XTALHSEXTERNALCLOCK_Msk (0x100UL)        /*!< XTALHSEXTERNALCLOCK (Bitfield-Mask: 0x01)             */
41946 #define MCUCTRL_XTALHSCTRL_XTALHSPADOUTEN_Pos (7UL)                 /*!< XTALHSPADOUTEN (Bit 7)                                */
41947 #define MCUCTRL_XTALHSCTRL_XTALHSPADOUTEN_Msk (0x80UL)              /*!< XTALHSPADOUTEN (Bitfield-Mask: 0x01)                  */
41948 #define MCUCTRL_XTALHSCTRL_XTALHSSELRCOM_Pos (6UL)                  /*!< XTALHSSELRCOM (Bit 6)                                 */
41949 #define MCUCTRL_XTALHSCTRL_XTALHSSELRCOM_Msk (0x40UL)               /*!< XTALHSSELRCOM (Bitfield-Mask: 0x01)                   */
41950 #define MCUCTRL_XTALHSCTRL_XTALHSPDNPNIMPROVE_Pos (5UL)             /*!< XTALHSPDNPNIMPROVE (Bit 5)                            */
41951 #define MCUCTRL_XTALHSCTRL_XTALHSPDNPNIMPROVE_Msk (0x20UL)          /*!< XTALHSPDNPNIMPROVE (Bitfield-Mask: 0x01)              */
41952 #define MCUCTRL_XTALHSCTRL_XTALHSINJECTIONENABLE_Pos (4UL)          /*!< XTALHSINJECTIONENABLE (Bit 4)                         */
41953 #define MCUCTRL_XTALHSCTRL_XTALHSINJECTIONENABLE_Msk (0x10UL)       /*!< XTALHSINJECTIONENABLE (Bitfield-Mask: 0x01)           */
41954 #define MCUCTRL_XTALHSCTRL_XTALHSIBSTENABLE_Pos (3UL)               /*!< XTALHSIBSTENABLE (Bit 3)                              */
41955 #define MCUCTRL_XTALHSCTRL_XTALHSIBSTENABLE_Msk (0x8UL)             /*!< XTALHSIBSTENABLE (Bitfield-Mask: 0x01)                */
41956 #define MCUCTRL_XTALHSCTRL_XTALHSCOMPSEL_Pos (2UL)                  /*!< XTALHSCOMPSEL (Bit 2)                                 */
41957 #define MCUCTRL_XTALHSCTRL_XTALHSCOMPSEL_Msk (0x4UL)                /*!< XTALHSCOMPSEL (Bitfield-Mask: 0x01)                   */
41958 #define MCUCTRL_XTALHSCTRL_XTALHSCOMPPDNB_Pos (1UL)                 /*!< XTALHSCOMPPDNB (Bit 1)                                */
41959 #define MCUCTRL_XTALHSCTRL_XTALHSCOMPPDNB_Msk (0x2UL)               /*!< XTALHSCOMPPDNB (Bitfield-Mask: 0x01)                  */
41960 #define MCUCTRL_XTALHSCTRL_XTALHSPDNB_Pos (0UL)                     /*!< XTALHSPDNB (Bit 0)                                    */
41961 #define MCUCTRL_XTALHSCTRL_XTALHSPDNB_Msk (0x1UL)                   /*!< XTALHSPDNB (Bitfield-Mask: 0x01)                      */
41962 /* ======================================================  MRAMPWRCTRL  ====================================================== */
41963 #define MCUCTRL_MRAMPWRCTRL_MRAMPWRCTRL_Pos (2UL)                   /*!< MRAMPWRCTRL (Bit 2)                                   */
41964 #define MCUCTRL_MRAMPWRCTRL_MRAMPWRCTRL_Msk (0x4UL)                 /*!< MRAMPWRCTRL (Bitfield-Mask: 0x01)                     */
41965 #define MCUCTRL_MRAMPWRCTRL_MRAMSLPEN_Pos (1UL)                     /*!< MRAMSLPEN (Bit 1)                                     */
41966 #define MCUCTRL_MRAMPWRCTRL_MRAMSLPEN_Msk (0x2UL)                   /*!< MRAMSLPEN (Bitfield-Mask: 0x01)                       */
41967 #define MCUCTRL_MRAMPWRCTRL_MRAMLPREN_Pos (0UL)                     /*!< MRAMLPREN (Bit 0)                                     */
41968 #define MCUCTRL_MRAMPWRCTRL_MRAMLPREN_Msk (0x1UL)                   /*!< MRAMLPREN (Bitfield-Mask: 0x01)                       */
41969 /* =======================================================  BODISABLE  ======================================================= */
41970 #define MCUCTRL_BODISABLE_BODCLVREN_Pos   (4UL)                     /*!< BODCLVREN (Bit 4)                                     */
41971 #define MCUCTRL_BODISABLE_BODCLVREN_Msk   (0x10UL)                  /*!< BODCLVREN (Bitfield-Mask: 0x01)                       */
41972 #define MCUCTRL_BODISABLE_BODSREN_Pos     (3UL)                     /*!< BODSREN (Bit 3)                                       */
41973 #define MCUCTRL_BODISABLE_BODSREN_Msk     (0x8UL)                   /*!< BODSREN (Bitfield-Mask: 0x01)                         */
41974 #define MCUCTRL_BODISABLE_BODFREN_Pos     (2UL)                     /*!< BODFREN (Bit 2)                                       */
41975 #define MCUCTRL_BODISABLE_BODFREN_Msk     (0x4UL)                   /*!< BODFREN (Bitfield-Mask: 0x01)                         */
41976 #define MCUCTRL_BODISABLE_BODCREN_Pos     (1UL)                     /*!< BODCREN (Bit 1)                                       */
41977 #define MCUCTRL_BODISABLE_BODCREN_Msk     (0x2UL)                   /*!< BODCREN (Bitfield-Mask: 0x01)                         */
41978 #define MCUCTRL_BODISABLE_BODLRDE_Pos     (0UL)                     /*!< BODLRDE (Bit 0)                                       */
41979 #define MCUCTRL_BODISABLE_BODLRDE_Msk     (0x1UL)                   /*!< BODLRDE (Bitfield-Mask: 0x01)                         */
41980 /* =======================================================  D2ASPARE  ======================================================== */
41981 #define MCUCTRL_D2ASPARE_VDDCAOROVERRIDE_Pos (4UL)                  /*!< VDDCAOROVERRIDE (Bit 4)                               */
41982 #define MCUCTRL_D2ASPARE_VDDCAOROVERRIDE_Msk (0x10UL)               /*!< VDDCAOROVERRIDE (Bitfield-Mask: 0x01)                 */
41983 #define MCUCTRL_D2ASPARE_VDDCPUOVERRIDE_Pos (3UL)                   /*!< VDDCPUOVERRIDE (Bit 3)                                */
41984 #define MCUCTRL_D2ASPARE_VDDCPUOVERRIDE_Msk (0x8UL)                 /*!< VDDCPUOVERRIDE (Bitfield-Mask: 0x01)                  */
41985 /* ======================================================  BOOTLOADER  ======================================================= */
41986 #define MCUCTRL_BOOTLOADER_SECBOOTONRST_Pos (30UL)                  /*!< SECBOOTONRST (Bit 30)                                 */
41987 #define MCUCTRL_BOOTLOADER_SECBOOTONRST_Msk (0xc0000000UL)          /*!< SECBOOTONRST (Bitfield-Mask: 0x03)                    */
41988 #define MCUCTRL_BOOTLOADER_SECBOOT_Pos    (28UL)                    /*!< SECBOOT (Bit 28)                                      */
41989 #define MCUCTRL_BOOTLOADER_SECBOOT_Msk    (0x30000000UL)            /*!< SECBOOT (Bitfield-Mask: 0x03)                         */
41990 #define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Pos (26UL)                /*!< SECBOOTFEATURE (Bit 26)                               */
41991 #define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Msk (0xc000000UL)         /*!< SECBOOTFEATURE (Bitfield-Mask: 0x03)                  */
41992 #define MCUCTRL_BOOTLOADER_SBLLOCK_Pos    (3UL)                     /*!< SBLLOCK (Bit 3)                                       */
41993 #define MCUCTRL_BOOTLOADER_SBLLOCK_Msk    (0x8UL)                   /*!< SBLLOCK (Bitfield-Mask: 0x01)                         */
41994 #define MCUCTRL_BOOTLOADER_PROTLOCK_Pos   (2UL)                     /*!< PROTLOCK (Bit 2)                                      */
41995 #define MCUCTRL_BOOTLOADER_PROTLOCK_Msk   (0x4UL)                   /*!< PROTLOCK (Bitfield-Mask: 0x01)                        */
41996 #define MCUCTRL_BOOTLOADER_SBRLOCK_Pos    (1UL)                     /*!< SBRLOCK (Bit 1)                                       */
41997 #define MCUCTRL_BOOTLOADER_SBRLOCK_Msk    (0x2UL)                   /*!< SBRLOCK (Bitfield-Mask: 0x01)                         */
41998 #define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Pos (0UL)                  /*!< BOOTLOADERLOW (Bit 0)                                 */
41999 #define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Msk (0x1UL)                /*!< BOOTLOADERLOW (Bitfield-Mask: 0x01)                   */
42000 /* ======================================================  SHADOWVALID  ====================================================== */
42001 #define MCUCTRL_SHADOWVALID_INFO0VALID_Pos (2UL)                    /*!< INFO0VALID (Bit 2)                                    */
42002 #define MCUCTRL_SHADOWVALID_INFO0VALID_Msk (0x4UL)                  /*!< INFO0VALID (Bitfield-Mask: 0x01)                      */
42003 #define MCUCTRL_SHADOWVALID_BLDSLEEP_Pos  (1UL)                     /*!< BLDSLEEP (Bit 1)                                      */
42004 #define MCUCTRL_SHADOWVALID_BLDSLEEP_Msk  (0x2UL)                   /*!< BLDSLEEP (Bitfield-Mask: 0x01)                        */
42005 #define MCUCTRL_SHADOWVALID_VALID_Pos     (0UL)                     /*!< VALID (Bit 0)                                         */
42006 #define MCUCTRL_SHADOWVALID_VALID_Msk     (0x1UL)                   /*!< VALID (Bitfield-Mask: 0x01)                           */
42007 /* =======================================================  SCRATCH0  ======================================================== */
42008 #define MCUCTRL_SCRATCH0_SCRATCH0_Pos     (0UL)                     /*!< SCRATCH0 (Bit 0)                                      */
42009 #define MCUCTRL_SCRATCH0_SCRATCH0_Msk     (0xffffffffUL)            /*!< SCRATCH0 (Bitfield-Mask: 0xffffffff)                  */
42010 /* =======================================================  SCRATCH1  ======================================================== */
42011 #define MCUCTRL_SCRATCH1_SCRATCH1_Pos     (0UL)                     /*!< SCRATCH1 (Bit 0)                                      */
42012 #define MCUCTRL_SCRATCH1_SCRATCH1_Msk     (0xffffffffUL)            /*!< SCRATCH1 (Bitfield-Mask: 0xffffffff)                  */
42013 /* =========================================================  DBGR1  ========================================================= */
42014 #define MCUCTRL_DBGR1_ONETO8_Pos          (0UL)                     /*!< ONETO8 (Bit 0)                                        */
42015 #define MCUCTRL_DBGR1_ONETO8_Msk          (0xffffffffUL)            /*!< ONETO8 (Bitfield-Mask: 0xffffffff)                    */
42016 /* =========================================================  DBGR2  ========================================================= */
42017 #define MCUCTRL_DBGR2_COOLCODE_Pos        (0UL)                     /*!< COOLCODE (Bit 0)                                      */
42018 #define MCUCTRL_DBGR2_COOLCODE_Msk        (0xffffffffUL)            /*!< COOLCODE (Bitfield-Mask: 0xffffffff)                  */
42019 /* =======================================================  PMUENABLE  ======================================================= */
42020 #define MCUCTRL_PMUENABLE_ENABLE_Pos      (0UL)                     /*!< ENABLE (Bit 0)                                        */
42021 #define MCUCTRL_PMUENABLE_ENABLE_Msk      (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
42022 /* ========================================================  DBGCTRL  ======================================================== */
42023 #define MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Pos (17UL)              /*!< DBGDSP1OCDHALTONRST (Bit 17)                          */
42024 #define MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Msk (0x20000UL)         /*!< DBGDSP1OCDHALTONRST (Bitfield-Mask: 0x01)             */
42025 #define MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Pos (16UL)              /*!< DBGDSP0OCDHALTONRST (Bit 16)                          */
42026 #define MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Msk (0x10000UL)         /*!< DBGDSP0OCDHALTONRST (Bitfield-Mask: 0x01)             */
42027 #define MCUCTRL_DBGCTRL_DBGTSCLKSEL_Pos   (12UL)                    /*!< DBGTSCLKSEL (Bit 12)                                  */
42028 #define MCUCTRL_DBGCTRL_DBGTSCLKSEL_Msk   (0x7000UL)                /*!< DBGTSCLKSEL (Bitfield-Mask: 0x07)                     */
42029 #define MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Pos (11UL)                   /*!< DBGDSP1TRACEEN (Bit 11)                               */
42030 #define MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Msk (0x800UL)                /*!< DBGDSP1TRACEEN (Bitfield-Mask: 0x01)                  */
42031 #define MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Pos (10UL)                   /*!< DBGDSP0TRACEEN (Bit 10)                               */
42032 #define MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Msk (0x400UL)                /*!< DBGDSP0TRACEEN (Bitfield-Mask: 0x01)                  */
42033 #define MCUCTRL_DBGCTRL_DBGETMTRACEEN_Pos (9UL)                     /*!< DBGETMTRACEEN (Bit 9)                                 */
42034 #define MCUCTRL_DBGCTRL_DBGETMTRACEEN_Msk (0x200UL)                 /*!< DBGETMTRACEEN (Bitfield-Mask: 0x01)                   */
42035 #define MCUCTRL_DBGCTRL_DBGETBENABLE_Pos  (8UL)                     /*!< DBGETBENABLE (Bit 8)                                  */
42036 #define MCUCTRL_DBGCTRL_DBGETBENABLE_Msk  (0x100UL)                 /*!< DBGETBENABLE (Bitfield-Mask: 0x01)                    */
42037 #define MCUCTRL_DBGCTRL_CM4CLKSEL_Pos     (1UL)                     /*!< CM4CLKSEL (Bit 1)                                     */
42038 #define MCUCTRL_DBGCTRL_CM4CLKSEL_Msk     (0xeUL)                   /*!< CM4CLKSEL (Bitfield-Mask: 0x07)                       */
42039 #define MCUCTRL_DBGCTRL_CM4TPIUENABLE_Pos (0UL)                     /*!< CM4TPIUENABLE (Bit 0)                                 */
42040 #define MCUCTRL_DBGCTRL_CM4TPIUENABLE_Msk (0x1UL)                   /*!< CM4TPIUENABLE (Bitfield-Mask: 0x01)                   */
42041 /* ======================================================  OTAPOINTER  ======================================================= */
42042 #define MCUCTRL_OTAPOINTER_OTAPOINTER_Pos (2UL)                     /*!< OTAPOINTER (Bit 2)                                    */
42043 #define MCUCTRL_OTAPOINTER_OTAPOINTER_Msk (0xfffffffcUL)            /*!< OTAPOINTER (Bitfield-Mask: 0x3fffffff)                */
42044 #define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Pos (1UL)                   /*!< OTASBLUPDATE (Bit 1)                                  */
42045 #define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Msk (0x2UL)                 /*!< OTASBLUPDATE (Bitfield-Mask: 0x01)                    */
42046 #define MCUCTRL_OTAPOINTER_OTAVALID_Pos   (0UL)                     /*!< OTAVALID (Bit 0)                                      */
42047 #define MCUCTRL_OTAPOINTER_OTAVALID_Msk   (0x1UL)                   /*!< OTAVALID (Bitfield-Mask: 0x01)                        */
42048 /* ======================================================  APBDMACTRL  ======================================================= */
42049 #define MCUCTRL_APBDMACTRL_HYSTERESIS_Pos (8UL)                     /*!< HYSTERESIS (Bit 8)                                    */
42050 #define MCUCTRL_APBDMACTRL_HYSTERESIS_Msk (0xff00UL)                /*!< HYSTERESIS (Bitfield-Mask: 0xff)                      */
42051 #define MCUCTRL_APBDMACTRL_DECODEABORT_Pos (1UL)                    /*!< DECODEABORT (Bit 1)                                   */
42052 #define MCUCTRL_APBDMACTRL_DECODEABORT_Msk (0x2UL)                  /*!< DECODEABORT (Bitfield-Mask: 0x01)                     */
42053 #define MCUCTRL_APBDMACTRL_DMAENABLE_Pos  (0UL)                     /*!< DMAENABLE (Bit 0)                                     */
42054 #define MCUCTRL_APBDMACTRL_DMAENABLE_Msk  (0x1UL)                   /*!< DMAENABLE (Bitfield-Mask: 0x01)                       */
42055 /* ======================================================  KEXTCLKSEL  ======================================================= */
42056 #define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Pos (0UL)                     /*!< KEXTCLKSEL (Bit 0)                                    */
42057 #define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Msk (0xffffffffUL)            /*!< KEXTCLKSEL (Bitfield-Mask: 0xffffffff)                */
42058 /* =======================================================  SIMOBUCK0  ======================================================= */
42059 #define MCUCTRL_SIMOBUCK0_TONTOFFNODEGLITCH_Pos (4UL)               /*!< TONTOFFNODEGLITCH (Bit 4)                             */
42060 #define MCUCTRL_SIMOBUCK0_TONTOFFNODEGLITCH_Msk (0x10UL)            /*!< TONTOFFNODEGLITCH (Bitfield-Mask: 0x01)               */
42061 #define MCUCTRL_SIMOBUCK0_VDDCLVRXCOMPEN_Pos (3UL)                  /*!< VDDCLVRXCOMPEN (Bit 3)                                */
42062 #define MCUCTRL_SIMOBUCK0_VDDCLVRXCOMPEN_Msk (0x8UL)                /*!< VDDCLVRXCOMPEN (Bitfield-Mask: 0x01)                  */
42063 #define MCUCTRL_SIMOBUCK0_VDDSRXCOMPEN_Pos (2UL)                    /*!< VDDSRXCOMPEN (Bit 2)                                  */
42064 #define MCUCTRL_SIMOBUCK0_VDDSRXCOMPEN_Msk (0x4UL)                  /*!< VDDSRXCOMPEN (Bitfield-Mask: 0x01)                    */
42065 #define MCUCTRL_SIMOBUCK0_VDDFRXCOMPEN_Pos (1UL)                    /*!< VDDFRXCOMPEN (Bit 1)                                  */
42066 #define MCUCTRL_SIMOBUCK0_VDDFRXCOMPEN_Msk (0x2UL)                  /*!< VDDFRXCOMPEN (Bitfield-Mask: 0x01)                    */
42067 #define MCUCTRL_SIMOBUCK0_VDDCRXCOMPEN_Pos (0UL)                    /*!< VDDCRXCOMPEN (Bit 0)                                  */
42068 #define MCUCTRL_SIMOBUCK0_VDDCRXCOMPEN_Msk (0x1UL)                  /*!< VDDCRXCOMPEN (Bitfield-Mask: 0x01)                    */
42069 /* =======================================================  SIMOBUCK1  ======================================================= */
42070 #define MCUCTRL_SIMOBUCK1_TONCLKTRIM_Pos  (22UL)                    /*!< TONCLKTRIM (Bit 22)                                   */
42071 #define MCUCTRL_SIMOBUCK1_TONCLKTRIM_Msk  (0x3c00000UL)             /*!< TONCLKTRIM (Bitfield-Mask: 0x0f)                      */
42072 #define MCUCTRL_SIMOBUCK1_RXCLKACTTRIM_Pos (6UL)                    /*!< RXCLKACTTRIM (Bit 6)                                  */
42073 #define MCUCTRL_SIMOBUCK1_RXCLKACTTRIM_Msk (0x7c0UL)                /*!< RXCLKACTTRIM (Bitfield-Mask: 0x1f)                    */
42074 /* =======================================================  SIMOBUCK2  ======================================================= */
42075 #define MCUCTRL_SIMOBUCK2_VDDCACTLOWTONTRIM_Pos (24UL)              /*!< VDDCACTLOWTONTRIM (Bit 24)                            */
42076 #define MCUCTRL_SIMOBUCK2_VDDCACTLOWTONTRIM_Msk (0x1f000000UL)      /*!< VDDCACTLOWTONTRIM (Bitfield-Mask: 0x1f)               */
42077 #define MCUCTRL_SIMOBUCK2_VDDCACTHIGHTONTRIM_Pos (11UL)             /*!< VDDCACTHIGHTONTRIM (Bit 11)                           */
42078 #define MCUCTRL_SIMOBUCK2_VDDCACTHIGHTONTRIM_Msk (0x7800UL)         /*!< VDDCACTHIGHTONTRIM (Bitfield-Mask: 0x0f)              */
42079 /* =======================================================  SIMOBUCK3  ======================================================= */
42080 #define MCUCTRL_SIMOBUCK3_VDDCLPLOWTONTRIM_Pos (26UL)               /*!< VDDCLPLOWTONTRIM (Bit 26)                             */
42081 #define MCUCTRL_SIMOBUCK3_VDDCLPLOWTONTRIM_Msk (0x3c000000UL)       /*!< VDDCLPLOWTONTRIM (Bitfield-Mask: 0x0f)                */
42082 #define MCUCTRL_SIMOBUCK3_VDDCLPHIGHTONTRIM_Pos (13UL)              /*!< VDDCLPHIGHTONTRIM (Bit 13)                            */
42083 #define MCUCTRL_SIMOBUCK3_VDDCLPHIGHTONTRIM_Msk (0x1e000UL)         /*!< VDDCLPHIGHTONTRIM (Bitfield-Mask: 0x0f)               */
42084 /* =======================================================  SIMOBUCK6  ======================================================= */
42085 #define MCUCTRL_SIMOBUCK6_VDDFACTHIGHTONTRIM_Pos (17UL)             /*!< VDDFACTHIGHTONTRIM (Bit 17)                           */
42086 #define MCUCTRL_SIMOBUCK6_VDDFACTHIGHTONTRIM_Msk (0x1e0000UL)       /*!< VDDFACTHIGHTONTRIM (Bitfield-Mask: 0x0f)              */
42087 /* =======================================================  SIMOBUCK7  ======================================================= */
42088 #define MCUCTRL_SIMOBUCK7_ZXCOMPZXTRIM_Pos (18UL)                   /*!< ZXCOMPZXTRIM (Bit 18)                                 */
42089 #define MCUCTRL_SIMOBUCK7_ZXCOMPZXTRIM_Msk (0x7c0000UL)             /*!< ZXCOMPZXTRIM (Bitfield-Mask: 0x1f)                    */
42090 #define MCUCTRL_SIMOBUCK7_VDDFACTLOWTONTRIM_Pos (8UL)               /*!< VDDFACTLOWTONTRIM (Bit 8)                             */
42091 #define MCUCTRL_SIMOBUCK7_VDDFACTLOWTONTRIM_Msk (0x1f00UL)          /*!< VDDFACTLOWTONTRIM (Bitfield-Mask: 0x1f)               */
42092 /* =======================================================  SIMOBUCK8  ======================================================= */
42093 #define MCUCTRL_SIMOBUCK8_VDDFLPLOWTONTRIM_Pos (22UL)               /*!< VDDFLPLOWTONTRIM (Bit 22)                             */
42094 #define MCUCTRL_SIMOBUCK8_VDDFLPLOWTONTRIM_Msk (0x3c00000UL)        /*!< VDDFLPLOWTONTRIM (Bitfield-Mask: 0x0f)                */
42095 #define MCUCTRL_SIMOBUCK8_VDDFLPHIGHTONTRIM_Pos (9UL)               /*!< VDDFLPHIGHTONTRIM (Bit 9)                             */
42096 #define MCUCTRL_SIMOBUCK8_VDDFLPHIGHTONTRIM_Msk (0x1e00UL)          /*!< VDDFLPHIGHTONTRIM (Bitfield-Mask: 0x0f)               */
42097 /* =======================================================  SIMOBUCK9  ======================================================= */
42098 #define MCUCTRL_SIMOBUCK9_VDDSACTLOWTONTRIM_Pos (22UL)              /*!< VDDSACTLOWTONTRIM (Bit 22)                            */
42099 #define MCUCTRL_SIMOBUCK9_VDDSACTLOWTONTRIM_Msk (0x7c00000UL)       /*!< VDDSACTLOWTONTRIM (Bitfield-Mask: 0x1f)               */
42100 #define MCUCTRL_SIMOBUCK9_VDDSACTHIGHTONTRIM_Pos (17UL)             /*!< VDDSACTHIGHTONTRIM (Bit 17)                           */
42101 #define MCUCTRL_SIMOBUCK9_VDDSACTHIGHTONTRIM_Msk (0x1e0000UL)       /*!< VDDSACTHIGHTONTRIM (Bitfield-Mask: 0x0f)              */
42102 /* ======================================================  SIMOBUCK12  ======================================================= */
42103 #define MCUCTRL_SIMOBUCK12_LPTRIMVDDF_Pos (26UL)                    /*!< LPTRIMVDDF (Bit 26)                                   */
42104 #define MCUCTRL_SIMOBUCK12_LPTRIMVDDF_Msk (0xfc000000UL)            /*!< LPTRIMVDDF (Bitfield-Mask: 0x3f)                      */
42105 #define MCUCTRL_SIMOBUCK12_ACTTRIMVDDF_Pos (20UL)                   /*!< ACTTRIMVDDF (Bit 20)                                  */
42106 #define MCUCTRL_SIMOBUCK12_ACTTRIMVDDF_Msk (0x3f00000UL)            /*!< ACTTRIMVDDF (Bitfield-Mask: 0x3f)                     */
42107 /* ======================================================  SIMOBUCK13  ======================================================= */
42108 #define MCUCTRL_SIMOBUCK13_LPTRIMVDDS_Pos (26UL)                    /*!< LPTRIMVDDS (Bit 26)                                   */
42109 #define MCUCTRL_SIMOBUCK13_LPTRIMVDDS_Msk (0xfc000000UL)            /*!< LPTRIMVDDS (Bitfield-Mask: 0x3f)                      */
42110 #define MCUCTRL_SIMOBUCK13_ACTTRIMVDDS_Pos (20UL)                   /*!< ACTTRIMVDDS (Bit 20)                                  */
42111 #define MCUCTRL_SIMOBUCK13_ACTTRIMVDDS_Msk (0x3f00000UL)            /*!< ACTTRIMVDDS (Bitfield-Mask: 0x3f)                     */
42112 /* ======================================================  SIMOBUCK15  ======================================================= */
42113 #define MCUCTRL_SIMOBUCK15_TRIMLATCHOVER_Pos (31UL)                 /*!< TRIMLATCHOVER (Bit 31)                                */
42114 #define MCUCTRL_SIMOBUCK15_TRIMLATCHOVER_Msk (0x80000000UL)         /*!< TRIMLATCHOVER (Bitfield-Mask: 0x01)                   */
42115 #define MCUCTRL_SIMOBUCK15_ZXCOMPOFFSETTRIM_Pos (24UL)              /*!< ZXCOMPOFFSETTRIM (Bit 24)                             */
42116 #define MCUCTRL_SIMOBUCK15_ZXCOMPOFFSETTRIM_Msk (0x1f000000UL)      /*!< ZXCOMPOFFSETTRIM (Bitfield-Mask: 0x1f)                */
42117 /* ========================================================  PWRSW0  ========================================================= */
42118 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUOVERRIDE_Pos (31UL)              /*!< PWRSWVDDRCPUOVERRIDE (Bit 31)                         */
42119 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUOVERRIDE_Msk (0x80000000UL)      /*!< PWRSWVDDRCPUOVERRIDE (Bitfield-Mask: 0x01)            */
42120 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Pos (30UL)               /*!< PWRSWVDDRCPUSTATSEL (Bit 30)                          */
42121 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Msk (0x40000000UL)       /*!< PWRSWVDDRCPUSTATSEL (Bitfield-Mask: 0x01)             */
42122 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUPGN_Pos (29UL)                   /*!< PWRSWVDDRCPUPGN (Bit 29)                              */
42123 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUPGN_Msk (0x20000000UL)           /*!< PWRSWVDDRCPUPGN (Bitfield-Mask: 0x01)                 */
42124 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUDYNSEL_Pos (27UL)                /*!< PWRSWVDDRCPUDYNSEL (Bit 27)                           */
42125 #define MCUCTRL_PWRSW0_PWRSWVDDRCPUDYNSEL_Msk (0x18000000UL)        /*!< PWRSWVDDRCPUDYNSEL (Bitfield-Mask: 0x03)              */
42126 #define MCUCTRL_PWRSW0_PWRSWVDDMLOVERRIDE_Pos (26UL)                /*!< PWRSWVDDMLOVERRIDE (Bit 26)                           */
42127 #define MCUCTRL_PWRSW0_PWRSWVDDMLOVERRIDE_Msk (0x4000000UL)         /*!< PWRSWVDDMLOVERRIDE (Bitfield-Mask: 0x01)              */
42128 #define MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_Pos (25UL)                 /*!< PWRSWVDDMLSTATSEL (Bit 25)                            */
42129 #define MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_Msk (0x2000000UL)          /*!< PWRSWVDDMLSTATSEL (Bitfield-Mask: 0x01)               */
42130 #define MCUCTRL_PWRSW0_PWRSWVDDMLDYNSEL_Pos (24UL)                  /*!< PWRSWVDDMLDYNSEL (Bit 24)                             */
42131 #define MCUCTRL_PWRSW0_PWRSWVDDMLDYNSEL_Msk (0x1000000UL)           /*!< PWRSWVDDMLDYNSEL (Bitfield-Mask: 0x01)                */
42132 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1OVERRIDE_Pos (23UL)             /*!< PWRSWVDDMDSP1OVERRIDE (Bit 23)                        */
42133 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1OVERRIDE_Msk (0x800000UL)       /*!< PWRSWVDDMDSP1OVERRIDE (Bitfield-Mask: 0x01)           */
42134 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Pos (22UL)              /*!< PWRSWVDDMDSP1STATSEL (Bit 22)                         */
42135 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Msk (0x400000UL)        /*!< PWRSWVDDMDSP1STATSEL (Bitfield-Mask: 0x01)            */
42136 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1DYNSEL_Pos (21UL)               /*!< PWRSWVDDMDSP1DYNSEL (Bit 21)                          */
42137 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP1DYNSEL_Msk (0x200000UL)         /*!< PWRSWVDDMDSP1DYNSEL (Bitfield-Mask: 0x01)             */
42138 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0OVERRIDE_Pos (20UL)             /*!< PWRSWVDDMDSP0OVERRIDE (Bit 20)                        */
42139 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0OVERRIDE_Msk (0x100000UL)       /*!< PWRSWVDDMDSP0OVERRIDE (Bitfield-Mask: 0x01)           */
42140 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Pos (19UL)              /*!< PWRSWVDDMDSP0STATSEL (Bit 19)                         */
42141 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Msk (0x80000UL)         /*!< PWRSWVDDMDSP0STATSEL (Bitfield-Mask: 0x01)            */
42142 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0DYNSEL_Pos (18UL)               /*!< PWRSWVDDMDSP0DYNSEL (Bit 18)                          */
42143 #define MCUCTRL_PWRSW0_PWRSWVDDMDSP0DYNSEL_Msk (0x40000UL)          /*!< PWRSWVDDMDSP0DYNSEL (Bitfield-Mask: 0x01)             */
42144 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUOVERRIDE_Pos (17UL)              /*!< PWRSWVDDMCPUOVERRIDE (Bit 17)                         */
42145 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUOVERRIDE_Msk (0x20000UL)         /*!< PWRSWVDDMCPUOVERRIDE (Bitfield-Mask: 0x01)            */
42146 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Pos (16UL)               /*!< PWRSWVDDMCPUSTATSEL (Bit 16)                          */
42147 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Msk (0x10000UL)          /*!< PWRSWVDDMCPUSTATSEL (Bitfield-Mask: 0x01)             */
42148 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUDYNSEL_Pos (15UL)                /*!< PWRSWVDDMCPUDYNSEL (Bit 15)                           */
42149 #define MCUCTRL_PWRSW0_PWRSWVDDMCPUDYNSEL_Msk (0x8000UL)            /*!< PWRSWVDDMCPUDYNSEL (Bitfield-Mask: 0x01)              */
42150 #define MCUCTRL_PWRSW0_PWRSWVDDDSP1OVERRIDE_Pos (14UL)              /*!< PWRSWVDDDSP1OVERRIDE (Bit 14)                         */
42151 #define MCUCTRL_PWRSW0_PWRSWVDDDSP1OVERRIDE_Msk (0x4000UL)          /*!< PWRSWVDDDSP1OVERRIDE (Bitfield-Mask: 0x01)            */
42152 #define MCUCTRL_PWRSW0_PWRSWVDDDSP1PGN_Pos (13UL)                   /*!< PWRSWVDDDSP1PGN (Bit 13)                              */
42153 #define MCUCTRL_PWRSW0_PWRSWVDDDSP1PGN_Msk (0x2000UL)               /*!< PWRSWVDDDSP1PGN (Bitfield-Mask: 0x01)                 */
42154 #define MCUCTRL_PWRSW0_PWRSWVDDDSP1DYNSEL_Pos (11UL)                /*!< PWRSWVDDDSP1DYNSEL (Bit 11)                           */
42155 #define MCUCTRL_PWRSW0_PWRSWVDDDSP1DYNSEL_Msk (0x1800UL)            /*!< PWRSWVDDDSP1DYNSEL (Bitfield-Mask: 0x03)              */
42156 #define MCUCTRL_PWRSW0_PWRSWVDDDSP0OVERRIDE_Pos (10UL)              /*!< PWRSWVDDDSP0OVERRIDE (Bit 10)                         */
42157 #define MCUCTRL_PWRSW0_PWRSWVDDDSP0OVERRIDE_Msk (0x400UL)           /*!< PWRSWVDDDSP0OVERRIDE (Bitfield-Mask: 0x01)            */
42158 #define MCUCTRL_PWRSW0_PWRSWVDDDSP0PGN_Pos (9UL)                    /*!< PWRSWVDDDSP0PGN (Bit 9)                               */
42159 #define MCUCTRL_PWRSW0_PWRSWVDDDSP0PGN_Msk (0x200UL)                /*!< PWRSWVDDDSP0PGN (Bitfield-Mask: 0x01)                 */
42160 #define MCUCTRL_PWRSW0_PWRSWVDDDSP0DYNSEL_Pos (7UL)                 /*!< PWRSWVDDDSP0DYNSEL (Bit 7)                            */
42161 #define MCUCTRL_PWRSW0_PWRSWVDDDSP0DYNSEL_Msk (0x180UL)             /*!< PWRSWVDDDSP0DYNSEL (Bitfield-Mask: 0x03)              */
42162 #define MCUCTRL_PWRSW0_PWRSWVDDCAOROVERRIDE_Pos (6UL)               /*!< PWRSWVDDCAOROVERRIDE (Bit 6)                          */
42163 #define MCUCTRL_PWRSW0_PWRSWVDDCAOROVERRIDE_Msk (0x40UL)            /*!< PWRSWVDDCAOROVERRIDE (Bitfield-Mask: 0x01)            */
42164 #define MCUCTRL_PWRSW0_PWRSWVDDCAORDYNSEL_Pos (4UL)                 /*!< PWRSWVDDCAORDYNSEL (Bit 4)                            */
42165 #define MCUCTRL_PWRSW0_PWRSWVDDCAORDYNSEL_Msk (0x30UL)              /*!< PWRSWVDDCAORDYNSEL (Bitfield-Mask: 0x03)              */
42166 #define MCUCTRL_PWRSW0_PWRSWVDDCPUOVERRIDE_Pos (3UL)                /*!< PWRSWVDDCPUOVERRIDE (Bit 3)                           */
42167 #define MCUCTRL_PWRSW0_PWRSWVDDCPUOVERRIDE_Msk (0x8UL)              /*!< PWRSWVDDCPUOVERRIDE (Bitfield-Mask: 0x01)             */
42168 #define MCUCTRL_PWRSW0_PWRSWVDDCPUPGN_Pos (2UL)                     /*!< PWRSWVDDCPUPGN (Bit 2)                                */
42169 #define MCUCTRL_PWRSW0_PWRSWVDDCPUPGN_Msk (0x4UL)                   /*!< PWRSWVDDCPUPGN (Bitfield-Mask: 0x01)                  */
42170 #define MCUCTRL_PWRSW0_PWRSWVDDCPUDYNSEL_Pos (0UL)                  /*!< PWRSWVDDCPUDYNSEL (Bit 0)                             */
42171 #define MCUCTRL_PWRSW0_PWRSWVDDCPUDYNSEL_Msk (0x3UL)                /*!< PWRSWVDDCPUDYNSEL (Bitfield-Mask: 0x03)               */
42172 /* ========================================================  PWRSW1  ========================================================= */
42173 #define MCUCTRL_PWRSW1_SHORTVDDFVDDSORVAL_Pos (31UL)                /*!< SHORTVDDFVDDSORVAL (Bit 31)                           */
42174 #define MCUCTRL_PWRSW1_SHORTVDDFVDDSORVAL_Msk (0x80000000UL)        /*!< SHORTVDDFVDDSORVAL (Bitfield-Mask: 0x01)              */
42175 #define MCUCTRL_PWRSW1_SHORTVDDFVDDSOREN_Pos (30UL)                 /*!< SHORTVDDFVDDSOREN (Bit 30)                            */
42176 #define MCUCTRL_PWRSW1_SHORTVDDFVDDSOREN_Msk (0x40000000UL)         /*!< SHORTVDDFVDDSOREN (Bitfield-Mask: 0x01)               */
42177 #define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVORVAL_Pos (29UL)              /*!< SHORTVDDCVDDCLVORVAL (Bit 29)                         */
42178 #define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVORVAL_Msk (0x20000000UL)      /*!< SHORTVDDCVDDCLVORVAL (Bitfield-Mask: 0x01)            */
42179 #define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVOREN_Pos (28UL)               /*!< SHORTVDDCVDDCLVOREN (Bit 28)                          */
42180 #define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVOREN_Msk (0x10000000UL)       /*!< SHORTVDDCVDDCLVOREN (Bitfield-Mask: 0x01)             */
42181 #define MCUCTRL_PWRSW1_FORCEVDDRMOFF_Pos  (27UL)                    /*!< FORCEVDDRMOFF (Bit 27)                                */
42182 #define MCUCTRL_PWRSW1_FORCEVDDRMOFF_Msk  (0x8000000UL)             /*!< FORCEVDDRMOFF (Bitfield-Mask: 0x01)                   */
42183 #define MCUCTRL_PWRSW1_FORCEVDDRMVDDS_Pos (26UL)                    /*!< FORCEVDDRMVDDS (Bit 26)                               */
42184 #define MCUCTRL_PWRSW1_FORCEVDDRMVDDS_Msk (0x4000000UL)             /*!< FORCEVDDRMVDDS (Bitfield-Mask: 0x01)                  */
42185 #define MCUCTRL_PWRSW1_USEVDDF4VDDRCPUINHP_Pos (25UL)               /*!< USEVDDF4VDDRCPUINHP (Bit 25)                          */
42186 #define MCUCTRL_PWRSW1_USEVDDF4VDDRCPUINHP_Msk (0x2000000UL)        /*!< USEVDDF4VDDRCPUINHP (Bitfield-Mask: 0x01)             */
42187 #define MCUCTRL_PWRSW1_DIGPWRSWOVRDRVSEL_Pos (23UL)                 /*!< DIGPWRSWOVRDRVSEL (Bit 23)                            */
42188 #define MCUCTRL_PWRSW1_DIGPWRSWOVRDRVSEL_Msk (0x1800000UL)          /*!< DIGPWRSWOVRDRVSEL (Bitfield-Mask: 0x03)               */
42189 #define MCUCTRL_PWRSW1_DIGPWRSWOVRDRVEN_Pos (22UL)                  /*!< DIGPWRSWOVRDRVEN (Bit 22)                             */
42190 #define MCUCTRL_PWRSW1_DIGPWRSWOVRDRVEN_Msk (0x400000UL)            /*!< DIGPWRSWOVRDRVEN (Bitfield-Mask: 0x01)                */
42191 #define MCUCTRL_PWRSW1_PWRSWOVRDRVEN_Pos  (21UL)                    /*!< PWRSWOVRDRVEN (Bit 21)                                */
42192 #define MCUCTRL_PWRSW1_PWRSWOVRDRVEN_Msk  (0x200000UL)              /*!< PWRSWOVRDRVEN (Bitfield-Mask: 0x01)                   */
42193 #define MCUCTRL_PWRSW1_PWRSWCOMPPDNB_Pos  (20UL)                    /*!< PWRSWCOMPPDNB (Bit 20)                                */
42194 #define MCUCTRL_PWRSW1_PWRSWCOMPPDNB_Msk  (0x100000UL)              /*!< PWRSWCOMPPDNB (Bitfield-Mask: 0x01)                   */
42195 #define MCUCTRL_PWRSW1_PWRSWVDDLOVERRIDE_Pos (19UL)                 /*!< PWRSWVDDLOVERRIDE (Bit 19)                            */
42196 #define MCUCTRL_PWRSW1_PWRSWVDDLOVERRIDE_Msk (0x80000UL)            /*!< PWRSWVDDLOVERRIDE (Bitfield-Mask: 0x01)               */
42197 #define MCUCTRL_PWRSW1_PWRSWVDDLPGN_Pos   (18UL)                    /*!< PWRSWVDDLPGN (Bit 18)                                 */
42198 #define MCUCTRL_PWRSW1_PWRSWVDDLPGN_Msk   (0x40000UL)               /*!< PWRSWVDDLPGN (Bitfield-Mask: 0x01)                    */
42199 #define MCUCTRL_PWRSW1_PWRSWVDDRMOVERRIDE_Pos (17UL)                /*!< PWRSWVDDRMOVERRIDE (Bit 17)                           */
42200 #define MCUCTRL_PWRSW1_PWRSWVDDRMOVERRIDE_Msk (0x20000UL)           /*!< PWRSWVDDRMOVERRIDE (Bitfield-Mask: 0x01)              */
42201 #define MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_Pos (16UL)                 /*!< PWRSWVDDRMSTATSEL (Bit 16)                            */
42202 #define MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_Msk (0x10000UL)            /*!< PWRSWVDDRMSTATSEL (Bitfield-Mask: 0x01)               */
42203 #define MCUCTRL_PWRSW1_PWRSWVDDRMPGN_Pos  (15UL)                    /*!< PWRSWVDDRMPGN (Bit 15)                                */
42204 #define MCUCTRL_PWRSW1_PWRSWVDDRMPGN_Msk  (0x8000UL)                /*!< PWRSWVDDRMPGN (Bitfield-Mask: 0x01)                   */
42205 #define MCUCTRL_PWRSW1_PWRSWVDDRMDYNSEL_Pos (14UL)                  /*!< PWRSWVDDRMDYNSEL (Bit 14)                             */
42206 #define MCUCTRL_PWRSW1_PWRSWVDDRMDYNSEL_Msk (0x4000UL)              /*!< PWRSWVDDRMDYNSEL (Bitfield-Mask: 0x01)                */
42207 #define MCUCTRL_PWRSW1_PWRSWVDDRLOVERRIDE_Pos (13UL)                /*!< PWRSWVDDRLOVERRIDE (Bit 13)                           */
42208 #define MCUCTRL_PWRSW1_PWRSWVDDRLOVERRIDE_Msk (0x2000UL)            /*!< PWRSWVDDRLOVERRIDE (Bitfield-Mask: 0x01)              */
42209 #define MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_Pos (12UL)                 /*!< PWRSWVDDRLSTATSEL (Bit 12)                            */
42210 #define MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_Msk (0x1000UL)             /*!< PWRSWVDDRLSTATSEL (Bitfield-Mask: 0x01)               */
42211 #define MCUCTRL_PWRSW1_PWRSWVDDRLPGN_Pos  (11UL)                    /*!< PWRSWVDDRLPGN (Bit 11)                                */
42212 #define MCUCTRL_PWRSW1_PWRSWVDDRLPGN_Msk  (0x800UL)                 /*!< PWRSWVDDRLPGN (Bitfield-Mask: 0x01)                   */
42213 #define MCUCTRL_PWRSW1_PWRSWVDDRLDYNSEL_Pos (10UL)                  /*!< PWRSWVDDRLDYNSEL (Bit 10)                             */
42214 #define MCUCTRL_PWRSW1_PWRSWVDDRLDYNSEL_Msk (0x400UL)               /*!< PWRSWVDDRLDYNSEL (Bitfield-Mask: 0x01)                */
42215 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP1OVERRIDE_Pos (9UL)              /*!< PWRSWVDDRDSP1OVERRIDE (Bit 9)                         */
42216 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP1OVERRIDE_Msk (0x200UL)          /*!< PWRSWVDDRDSP1OVERRIDE (Bitfield-Mask: 0x01)           */
42217 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_Pos (8UL)               /*!< PWRSWVDDRDSP1STATSEL (Bit 8)                          */
42218 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_Msk (0x100UL)           /*!< PWRSWVDDRDSP1STATSEL (Bitfield-Mask: 0x01)            */
42219 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP1PGN_Pos (7UL)                   /*!< PWRSWVDDRDSP1PGN (Bit 7)                              */
42220 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP1PGN_Msk (0x80UL)                /*!< PWRSWVDDRDSP1PGN (Bitfield-Mask: 0x01)                */
42221 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP1DYNSEL_Pos (5UL)                /*!< PWRSWVDDRDSP1DYNSEL (Bit 5)                           */
42222 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP1DYNSEL_Msk (0x60UL)             /*!< PWRSWVDDRDSP1DYNSEL (Bitfield-Mask: 0x03)             */
42223 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP0OVERRIDE_Pos (4UL)              /*!< PWRSWVDDRDSP0OVERRIDE (Bit 4)                         */
42224 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP0OVERRIDE_Msk (0x10UL)           /*!< PWRSWVDDRDSP0OVERRIDE (Bitfield-Mask: 0x01)           */
42225 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_Pos (3UL)               /*!< PWRSWVDDRDSP0STATSEL (Bit 3)                          */
42226 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_Msk (0x8UL)             /*!< PWRSWVDDRDSP0STATSEL (Bitfield-Mask: 0x01)            */
42227 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP0PGN_Pos (2UL)                   /*!< PWRSWVDDRDSP0PGN (Bit 2)                              */
42228 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP0PGN_Msk (0x4UL)                 /*!< PWRSWVDDRDSP0PGN (Bitfield-Mask: 0x01)                */
42229 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP0DYNSEL_Pos (0UL)                /*!< PWRSWVDDRDSP0DYNSEL (Bit 0)                           */
42230 #define MCUCTRL_PWRSW1_PWRSWVDDRDSP0DYNSEL_Msk (0x3UL)              /*!< PWRSWVDDRDSP0DYNSEL (Bitfield-Mask: 0x03)             */
42231 /* ======================================================  USBRSTCTRL  ======================================================= */
42232 #define MCUCTRL_USBRSTCTRL_USBUTMIRSTRELEASE_Pos (2UL)              /*!< USBUTMIRSTRELEASE (Bit 2)                             */
42233 #define MCUCTRL_USBRSTCTRL_USBUTMIRSTRELEASE_Msk (0x4UL)            /*!< USBUTMIRSTRELEASE (Bitfield-Mask: 0x01)               */
42234 #define MCUCTRL_USBRSTCTRL_USBPORRSTRELEASE_Pos (1UL)               /*!< USBPORRSTRELEASE (Bit 1)                              */
42235 #define MCUCTRL_USBRSTCTRL_USBPORRSTRELEASE_Msk (0x2UL)             /*!< USBPORRSTRELEASE (Bitfield-Mask: 0x01)                */
42236 #define MCUCTRL_USBRSTCTRL_USBRSTENABLE_Pos (0UL)                   /*!< USBRSTENABLE (Bit 0)                                  */
42237 #define MCUCTRL_USBRSTCTRL_USBRSTENABLE_Msk (0x1UL)                 /*!< USBRSTENABLE (Bitfield-Mask: 0x01)                    */
42238 /* ======================================================  FLASHWPROT0  ====================================================== */
42239 #define MCUCTRL_FLASHWPROT0_FW0BITS_Pos   (0UL)                     /*!< FW0BITS (Bit 0)                                       */
42240 #define MCUCTRL_FLASHWPROT0_FW0BITS_Msk   (0xffffffffUL)            /*!< FW0BITS (Bitfield-Mask: 0xffffffff)                   */
42241 /* ======================================================  FLASHWPROT1  ====================================================== */
42242 #define MCUCTRL_FLASHWPROT1_FW1BITS_Pos   (0UL)                     /*!< FW1BITS (Bit 0)                                       */
42243 #define MCUCTRL_FLASHWPROT1_FW1BITS_Msk   (0xffffffffUL)            /*!< FW1BITS (Bitfield-Mask: 0xffffffff)                   */
42244 /* ======================================================  FLASHWPROT2  ====================================================== */
42245 #define MCUCTRL_FLASHWPROT2_FW2BITS_Pos   (0UL)                     /*!< FW2BITS (Bit 0)                                       */
42246 #define MCUCTRL_FLASHWPROT2_FW2BITS_Msk   (0xffffffffUL)            /*!< FW2BITS (Bitfield-Mask: 0xffffffff)                   */
42247 /* ======================================================  FLASHWPROT3  ====================================================== */
42248 #define MCUCTRL_FLASHWPROT3_FW3BITS_Pos   (0UL)                     /*!< FW3BITS (Bit 0)                                       */
42249 #define MCUCTRL_FLASHWPROT3_FW3BITS_Msk   (0xffffffffUL)            /*!< FW3BITS (Bitfield-Mask: 0xffffffff)                   */
42250 /* ======================================================  FLASHRPROT0  ====================================================== */
42251 #define MCUCTRL_FLASHRPROT0_FR0BITS_Pos   (0UL)                     /*!< FR0BITS (Bit 0)                                       */
42252 #define MCUCTRL_FLASHRPROT0_FR0BITS_Msk   (0xffffffffUL)            /*!< FR0BITS (Bitfield-Mask: 0xffffffff)                   */
42253 /* ======================================================  FLASHRPROT1  ====================================================== */
42254 #define MCUCTRL_FLASHRPROT1_FR1BITS_Pos   (0UL)                     /*!< FR1BITS (Bit 0)                                       */
42255 #define MCUCTRL_FLASHRPROT1_FR1BITS_Msk   (0xffffffffUL)            /*!< FR1BITS (Bitfield-Mask: 0xffffffff)                   */
42256 /* ======================================================  FLASHRPROT2  ====================================================== */
42257 #define MCUCTRL_FLASHRPROT2_FR2BITS_Pos   (0UL)                     /*!< FR2BITS (Bit 0)                                       */
42258 #define MCUCTRL_FLASHRPROT2_FR2BITS_Msk   (0xffffffffUL)            /*!< FR2BITS (Bitfield-Mask: 0xffffffff)                   */
42259 /* ======================================================  FLASHRPROT3  ====================================================== */
42260 #define MCUCTRL_FLASHRPROT3_FR3BITS_Pos   (0UL)                     /*!< FR3BITS (Bit 0)                                       */
42261 #define MCUCTRL_FLASHRPROT3_FR3BITS_Msk   (0xffffffffUL)            /*!< FR3BITS (Bitfield-Mask: 0xffffffff)                   */
42262 /* =====================================================  DMASRAMWPROT0  ===================================================== */
42263 #define MCUCTRL_DMASRAMWPROT0_DMAWPROT0_Pos (0UL)                   /*!< DMAWPROT0 (Bit 0)                                     */
42264 #define MCUCTRL_DMASRAMWPROT0_DMAWPROT0_Msk (0xffffffffUL)          /*!< DMAWPROT0 (Bitfield-Mask: 0xffffffff)                 */
42265 /* =====================================================  DMASRAMWPROT1  ===================================================== */
42266 #define MCUCTRL_DMASRAMWPROT1_DMAWPROT1_Pos (0UL)                   /*!< DMAWPROT1 (Bit 0)                                     */
42267 #define MCUCTRL_DMASRAMWPROT1_DMAWPROT1_Msk (0xffffUL)              /*!< DMAWPROT1 (Bitfield-Mask: 0xffff)                     */
42268 /* =====================================================  DMASRAMRPROT0  ===================================================== */
42269 #define MCUCTRL_DMASRAMRPROT0_DMARPROT0_Pos (0UL)                   /*!< DMARPROT0 (Bit 0)                                     */
42270 #define MCUCTRL_DMASRAMRPROT0_DMARPROT0_Msk (0xffffffffUL)          /*!< DMARPROT0 (Bitfield-Mask: 0xffffffff)                 */
42271 /* =====================================================  DMASRAMRPROT1  ===================================================== */
42272 #define MCUCTRL_DMASRAMRPROT1_DMARPROT1_Pos (0UL)                   /*!< DMARPROT1 (Bit 0)                                     */
42273 #define MCUCTRL_DMASRAMRPROT1_DMARPROT1_Msk (0xffffUL)              /*!< DMARPROT1 (Bitfield-Mask: 0xffff)                     */
42274 /* ======================================================  USBPHYRESET  ====================================================== */
42275 #define MCUCTRL_USBPHYRESET_RESERVED18_Pos (31UL)                   /*!< RESERVED18 (Bit 31)                                   */
42276 #define MCUCTRL_USBPHYRESET_RESERVED18_Msk (0x80000000UL)           /*!< RESERVED18 (Bitfield-Mask: 0x01)                      */
42277 #define MCUCTRL_USBPHYRESET_RESERVED17_Pos (28UL)                   /*!< RESERVED17 (Bit 28)                                   */
42278 #define MCUCTRL_USBPHYRESET_RESERVED17_Msk (0x70000000UL)           /*!< RESERVED17 (Bitfield-Mask: 0x07)                      */
42279 #define MCUCTRL_USBPHYRESET_RESERVED16_Pos (27UL)                   /*!< RESERVED16 (Bit 27)                                   */
42280 #define MCUCTRL_USBPHYRESET_RESERVED16_Msk (0x8000000UL)            /*!< RESERVED16 (Bitfield-Mask: 0x01)                      */
42281 #define MCUCTRL_USBPHYRESET_RESERVED15_Pos (25UL)                   /*!< RESERVED15 (Bit 25)                                   */
42282 #define MCUCTRL_USBPHYRESET_RESERVED15_Msk (0x6000000UL)            /*!< RESERVED15 (Bitfield-Mask: 0x03)                      */
42283 #define MCUCTRL_USBPHYRESET_RESERVED14_Pos (24UL)                   /*!< RESERVED14 (Bit 24)                                   */
42284 #define MCUCTRL_USBPHYRESET_RESERVED14_Msk (0x1000000UL)            /*!< RESERVED14 (Bitfield-Mask: 0x01)                      */
42285 #define MCUCTRL_USBPHYRESET_RESERVED13_Pos (22UL)                   /*!< RESERVED13 (Bit 22)                                   */
42286 #define MCUCTRL_USBPHYRESET_RESERVED13_Msk (0xc00000UL)             /*!< RESERVED13 (Bitfield-Mask: 0x03)                      */
42287 #define MCUCTRL_USBPHYRESET_RESERVED12_Pos (21UL)                   /*!< RESERVED12 (Bit 21)                                   */
42288 #define MCUCTRL_USBPHYRESET_RESERVED12_Msk (0x200000UL)             /*!< RESERVED12 (Bitfield-Mask: 0x01)                      */
42289 #define MCUCTRL_USBPHYRESET_RESERVED11_Pos (18UL)                   /*!< RESERVED11 (Bit 18)                                   */
42290 #define MCUCTRL_USBPHYRESET_RESERVED11_Msk (0x1c0000UL)             /*!< RESERVED11 (Bitfield-Mask: 0x07)                      */
42291 #define MCUCTRL_USBPHYRESET_RESERVED10_Pos (17UL)                   /*!< RESERVED10 (Bit 17)                                   */
42292 #define MCUCTRL_USBPHYRESET_RESERVED10_Msk (0x20000UL)              /*!< RESERVED10 (Bitfield-Mask: 0x01)                      */
42293 #define MCUCTRL_USBPHYRESET_RESERVED09_Pos (16UL)                   /*!< RESERVED09 (Bit 16)                                   */
42294 #define MCUCTRL_USBPHYRESET_RESERVED09_Msk (0x10000UL)              /*!< RESERVED09 (Bitfield-Mask: 0x01)                      */
42295 #define MCUCTRL_USBPHYRESET_RESERVED07_Pos (12UL)                   /*!< RESERVED07 (Bit 12)                                   */
42296 #define MCUCTRL_USBPHYRESET_RESERVED07_Msk (0x7000UL)               /*!< RESERVED07 (Bitfield-Mask: 0x07)                      */
42297 #define MCUCTRL_USBPHYRESET_RESERVED06_Pos (11UL)                   /*!< RESERVED06 (Bit 11)                                   */
42298 #define MCUCTRL_USBPHYRESET_RESERVED06_Msk (0x800UL)                /*!< RESERVED06 (Bitfield-Mask: 0x01)                      */
42299 #define MCUCTRL_USBPHYRESET_RESERVED05_Pos (9UL)                    /*!< RESERVED05 (Bit 9)                                    */
42300 #define MCUCTRL_USBPHYRESET_RESERVED05_Msk (0x600UL)                /*!< RESERVED05 (Bitfield-Mask: 0x03)                      */
42301 #define MCUCTRL_USBPHYRESET_RESERVED04_Pos (8UL)                    /*!< RESERVED04 (Bit 8)                                    */
42302 #define MCUCTRL_USBPHYRESET_RESERVED04_Msk (0x100UL)                /*!< RESERVED04 (Bitfield-Mask: 0x01)                      */
42303 #define MCUCTRL_USBPHYRESET_RESERVED03_Pos (6UL)                    /*!< RESERVED03 (Bit 6)                                    */
42304 #define MCUCTRL_USBPHYRESET_RESERVED03_Msk (0xc0UL)                 /*!< RESERVED03 (Bitfield-Mask: 0x03)                      */
42305 #define MCUCTRL_USBPHYRESET_RESERVED02_Pos (5UL)                    /*!< RESERVED02 (Bit 5)                                    */
42306 #define MCUCTRL_USBPHYRESET_RESERVED02_Msk (0x20UL)                 /*!< RESERVED02 (Bitfield-Mask: 0x01)                      */
42307 #define MCUCTRL_USBPHYRESET_RESERVED01_Pos (2UL)                    /*!< RESERVED01 (Bit 2)                                    */
42308 #define MCUCTRL_USBPHYRESET_RESERVED01_Msk (0x1cUL)                 /*!< RESERVED01 (Bitfield-Mask: 0x07)                      */
42309 #define MCUCTRL_USBPHYRESET_USBPHYUTMIRSTDIS_Pos (1UL)              /*!< USBPHYUTMIRSTDIS (Bit 1)                              */
42310 #define MCUCTRL_USBPHYRESET_USBPHYUTMIRSTDIS_Msk (0x2UL)            /*!< USBPHYUTMIRSTDIS (Bitfield-Mask: 0x01)                */
42311 #define MCUCTRL_USBPHYRESET_USBPHYPORRSTDIS_Pos (0UL)               /*!< USBPHYPORRSTDIS (Bit 0)                               */
42312 #define MCUCTRL_USBPHYRESET_USBPHYPORRSTDIS_Msk (0x1UL)             /*!< USBPHYPORRSTDIS (Bitfield-Mask: 0x01)                 */
42313 /* =====================================================  AUDADCPWRCTRL  ===================================================== */
42314 #define MCUCTRL_AUDADCPWRCTRL_AUDADCKEEPOUTEN_Pos (18UL)            /*!< AUDADCKEEPOUTEN (Bit 18)                              */
42315 #define MCUCTRL_AUDADCPWRCTRL_AUDADCKEEPOUTEN_Msk (0x40000UL)       /*!< AUDADCKEEPOUTEN (Bitfield-Mask: 0x01)                 */
42316 #define MCUCTRL_AUDADCPWRCTRL_AUDADCRFBUFSLWEN_Pos (17UL)           /*!< AUDADCRFBUFSLWEN (Bit 17)                             */
42317 #define MCUCTRL_AUDADCPWRCTRL_AUDADCRFBUFSLWEN_Msk (0x20000UL)      /*!< AUDADCRFBUFSLWEN (Bitfield-Mask: 0x01)                */
42318 #define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFEN_Pos (16UL)              /*!< AUDADCINBUFEN (Bit 16)                                */
42319 #define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFEN_Msk (0x10000UL)         /*!< AUDADCINBUFEN (Bitfield-Mask: 0x01)                   */
42320 #define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFSEL_Pos (14UL)             /*!< AUDADCINBUFSEL (Bit 14)                               */
42321 #define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFSEL_Msk (0xc000UL)         /*!< AUDADCINBUFSEL (Bitfield-Mask: 0x03)                  */
42322 #define MCUCTRL_AUDADCPWRCTRL_AUDADCVBATDIVEN_Pos (12UL)            /*!< AUDADCVBATDIVEN (Bit 12)                              */
42323 #define MCUCTRL_AUDADCPWRCTRL_AUDADCVBATDIVEN_Msk (0x1000UL)        /*!< AUDADCVBATDIVEN (Bitfield-Mask: 0x01)                 */
42324 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Pos (10UL)            /*!< VDDAUDADCRESETN (Bit 10)                              */
42325 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Msk (0x400UL)         /*!< VDDAUDADCRESETN (Bitfield-Mask: 0x01)                 */
42326 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Pos (9UL)         /*!< VDDAUDADCDIGISOLATE (Bit 9)                           */
42327 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Msk (0x200UL)     /*!< VDDAUDADCDIGISOLATE (Bitfield-Mask: 0x01)             */
42328 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Pos (8UL)         /*!< VDDAUDADCSARISOLATE (Bit 8)                           */
42329 #define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Msk (0x100UL)     /*!< VDDAUDADCSARISOLATE (Bitfield-Mask: 0x01)             */
42330 #define MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Pos (5UL)               /*!< AUDREFKEEPPEN (Bit 5)                                 */
42331 #define MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Msk (0x20UL)            /*!< AUDREFKEEPPEN (Bitfield-Mask: 0x01)                   */
42332 #define MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Pos (4UL)                /*!< AUDREFBUFPEN (Bit 4)                                  */
42333 #define MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Msk (0x10UL)             /*!< AUDREFBUFPEN (Bitfield-Mask: 0x01)                    */
42334 #define MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Pos (3UL)                   /*!< AUDBGTPEN (Bit 3)                                     */
42335 #define MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Msk (0x8UL)                 /*!< AUDBGTPEN (Bitfield-Mask: 0x01)                       */
42336 #define MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Pos (2UL)                 /*!< AUDADCBPSEN (Bit 2)                                   */
42337 #define MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Msk (0x4UL)               /*!< AUDADCBPSEN (Bitfield-Mask: 0x01)                     */
42338 #define MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Pos (1UL)                 /*!< AUDADCAPSEN (Bit 1)                                   */
42339 #define MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Msk (0x2UL)               /*!< AUDADCAPSEN (Bitfield-Mask: 0x01)                     */
42340 #define MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Pos (0UL)            /*!< AUDADCPWRCTRLSWE (Bit 0)                              */
42341 #define MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Msk (0x1UL)          /*!< AUDADCPWRCTRLSWE (Bitfield-Mask: 0x01)                */
42342 /* ========================================================  AUDIO1  ========================================================= */
42343 #define MCUCTRL_AUDIO1_MICBIASPDNB_Pos    (12UL)                    /*!< MICBIASPDNB (Bit 12)                                  */
42344 #define MCUCTRL_AUDIO1_MICBIASPDNB_Msk    (0x1000UL)                /*!< MICBIASPDNB (Bitfield-Mask: 0x01)                     */
42345 #define MCUCTRL_AUDIO1_MICBIASVOLTAGETRIM_Pos (6UL)                 /*!< MICBIASVOLTAGETRIM (Bit 6)                            */
42346 #define MCUCTRL_AUDIO1_MICBIASVOLTAGETRIM_Msk (0xfc0UL)             /*!< MICBIASVOLTAGETRIM (Bitfield-Mask: 0x3f)              */
42347 /* =====================================================  PGAADCIFCTRL  ====================================================== */
42348 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPSEL_Pos (13UL)            /*!< PGAADCIFVCOMPSEL (Bit 13)                             */
42349 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPSEL_Msk (0x6000UL)        /*!< PGAADCIFVCOMPSEL (Bitfield-Mask: 0x03)                */
42350 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPEN_Pos (12UL)             /*!< PGAADCIFVCOMPEN (Bit 12)                              */
42351 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPEN_Msk (0x1000UL)         /*!< PGAADCIFVCOMPEN (Bitfield-Mask: 0x01)                 */
42352 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBPDNB_Pos (6UL)              /*!< PGAADCIFCHBPDNB (Bit 6)                               */
42353 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBPDNB_Msk (0xc0UL)           /*!< PGAADCIFCHBPDNB (Bitfield-Mask: 0x03)                 */
42354 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBACTIVE_Pos (4UL)            /*!< PGAADCIFCHBACTIVE (Bit 4)                             */
42355 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBACTIVE_Msk (0x30UL)         /*!< PGAADCIFCHBACTIVE (Bitfield-Mask: 0x03)               */
42356 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAPDNB_Pos (2UL)              /*!< PGAADCIFCHAPDNB (Bit 2)                               */
42357 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAPDNB_Msk (0xcUL)            /*!< PGAADCIFCHAPDNB (Bitfield-Mask: 0x03)                 */
42358 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAACTIVE_Pos (0UL)            /*!< PGAADCIFCHAACTIVE (Bit 0)                             */
42359 #define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAACTIVE_Msk (0x3UL)          /*!< PGAADCIFCHAACTIVE (Bitfield-Mask: 0x03)               */
42360 /* =======================================================  PGACTRL1  ======================================================== */
42361 #define MCUCTRL_PGACTRL1_PGAGAINAOVRD_Pos (31UL)                    /*!< PGAGAINAOVRD (Bit 31)                                 */
42362 #define MCUCTRL_PGACTRL1_PGAGAINAOVRD_Msk (0x80000000UL)            /*!< PGAGAINAOVRD (Bitfield-Mask: 0x01)                    */
42363 #define MCUCTRL_PGACTRL1_VCOMPSELPGA_Pos  (29UL)                    /*!< VCOMPSELPGA (Bit 29)                                  */
42364 #define MCUCTRL_PGACTRL1_VCOMPSELPGA_Msk  (0x20000000UL)            /*!< VCOMPSELPGA (Bitfield-Mask: 0x01)                     */
42365 #define MCUCTRL_PGACTRL1_PGAVREFGENQUICKSTARTEN_Pos (28UL)          /*!< PGAVREFGENQUICKSTARTEN (Bit 28)                       */
42366 #define MCUCTRL_PGACTRL1_PGAVREFGENQUICKSTARTEN_Msk (0x10000000UL)  /*!< PGAVREFGENQUICKSTARTEN (Bitfield-Mask: 0x01)          */
42367 #define MCUCTRL_PGACTRL1_PGAVREFGENPDNB_Pos (27UL)                  /*!< PGAVREFGENPDNB (Bit 27)                               */
42368 #define MCUCTRL_PGACTRL1_PGAVREFGENPDNB_Msk (0x8000000UL)           /*!< PGAVREFGENPDNB (Bitfield-Mask: 0x01)                  */
42369 #define MCUCTRL_PGACTRL1_PGAIREFGENPDNB_Pos (26UL)                  /*!< PGAIREFGENPDNB (Bit 26)                               */
42370 #define MCUCTRL_PGACTRL1_PGAIREFGENPDNB_Msk (0x4000000UL)           /*!< PGAIREFGENPDNB (Bitfield-Mask: 0x01)                  */
42371 #define MCUCTRL_PGACTRL1_PGACHAVCMGENQCHARGEEN_Pos (25UL)           /*!< PGACHAVCMGENQCHARGEEN (Bit 25)                        */
42372 #define MCUCTRL_PGACTRL1_PGACHAVCMGENQCHARGEEN_Msk (0x2000000UL)    /*!< PGACHAVCMGENQCHARGEEN (Bitfield-Mask: 0x01)           */
42373 #define MCUCTRL_PGACTRL1_PGACHAVCMGENPDNB_Pos (24UL)                /*!< PGACHAVCMGENPDNB (Bit 24)                             */
42374 #define MCUCTRL_PGACTRL1_PGACHAVCMGENPDNB_Msk (0x1000000UL)         /*!< PGACHAVCMGENPDNB (Bitfield-Mask: 0x01)                */
42375 #define MCUCTRL_PGACTRL1_PGACHAOPAMPOUTPDNB_Pos (22UL)              /*!< PGACHAOPAMPOUTPDNB (Bit 22)                           */
42376 #define MCUCTRL_PGACTRL1_PGACHAOPAMPOUTPDNB_Msk (0xc00000UL)        /*!< PGACHAOPAMPOUTPDNB (Bitfield-Mask: 0x03)              */
42377 #define MCUCTRL_PGACTRL1_PGACHAOPAMPINPDNB_Pos (20UL)               /*!< PGACHAOPAMPINPDNB (Bit 20)                            */
42378 #define MCUCTRL_PGACTRL1_PGACHAOPAMPINPDNB_Msk (0x300000UL)         /*!< PGACHAOPAMPINPDNB (Bitfield-Mask: 0x03)               */
42379 #define MCUCTRL_PGACTRL1_PGACHABYPASSEN_Pos (18UL)                  /*!< PGACHABYPASSEN (Bit 18)                               */
42380 #define MCUCTRL_PGACTRL1_PGACHABYPASSEN_Msk (0xc0000UL)             /*!< PGACHABYPASSEN (Bitfield-Mask: 0x03)                  */
42381 #define MCUCTRL_PGACTRL1_PGACHA1GAIN2SEL_Pos (13UL)                 /*!< PGACHA1GAIN2SEL (Bit 13)                              */
42382 #define MCUCTRL_PGACTRL1_PGACHA1GAIN2SEL_Msk (0x3e000UL)            /*!< PGACHA1GAIN2SEL (Bitfield-Mask: 0x1f)                 */
42383 #define MCUCTRL_PGACTRL1_PGACHA1GAIN2DIV2SEL_Pos (12UL)             /*!< PGACHA1GAIN2DIV2SEL (Bit 12)                          */
42384 #define MCUCTRL_PGACTRL1_PGACHA1GAIN2DIV2SEL_Msk (0x1000UL)         /*!< PGACHA1GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
42385 #define MCUCTRL_PGACTRL1_PGACHA1GAIN1SEL_Pos (9UL)                  /*!< PGACHA1GAIN1SEL (Bit 9)                               */
42386 #define MCUCTRL_PGACTRL1_PGACHA1GAIN1SEL_Msk (0xe00UL)              /*!< PGACHA1GAIN1SEL (Bitfield-Mask: 0x07)                 */
42387 #define MCUCTRL_PGACTRL1_PGACHA0GAIN2SEL_Pos (4UL)                  /*!< PGACHA0GAIN2SEL (Bit 4)                               */
42388 #define MCUCTRL_PGACTRL1_PGACHA0GAIN2SEL_Msk (0x1f0UL)              /*!< PGACHA0GAIN2SEL (Bitfield-Mask: 0x1f)                 */
42389 #define MCUCTRL_PGACTRL1_PGACHA0GAIN2DIV2SEL_Pos (3UL)              /*!< PGACHA0GAIN2DIV2SEL (Bit 3)                           */
42390 #define MCUCTRL_PGACTRL1_PGACHA0GAIN2DIV2SEL_Msk (0x8UL)            /*!< PGACHA0GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
42391 #define MCUCTRL_PGACTRL1_PGACHA0GAIN1SEL_Pos (0UL)                  /*!< PGACHA0GAIN1SEL (Bit 0)                               */
42392 #define MCUCTRL_PGACTRL1_PGACHA0GAIN1SEL_Msk (0x7UL)                /*!< PGACHA0GAIN1SEL (Bitfield-Mask: 0x07)                 */
42393 /* =======================================================  PGACTRL2  ======================================================== */
42394 #define MCUCTRL_PGACTRL2_PGAGAINBOVRD_Pos (31UL)                    /*!< PGAGAINBOVRD (Bit 31)                                 */
42395 #define MCUCTRL_PGACTRL2_PGAGAINBOVRD_Msk (0x80000000UL)            /*!< PGAGAINBOVRD (Bitfield-Mask: 0x01)                    */
42396 #define MCUCTRL_PGACTRL2_PGACHBVCMGENQCHARGEEN_Pos (25UL)           /*!< PGACHBVCMGENQCHARGEEN (Bit 25)                        */
42397 #define MCUCTRL_PGACTRL2_PGACHBVCMGENQCHARGEEN_Msk (0x2000000UL)    /*!< PGACHBVCMGENQCHARGEEN (Bitfield-Mask: 0x01)           */
42398 #define MCUCTRL_PGACTRL2_PGACHBVCMGENPDNB_Pos (24UL)                /*!< PGACHBVCMGENPDNB (Bit 24)                             */
42399 #define MCUCTRL_PGACTRL2_PGACHBVCMGENPDNB_Msk (0x1000000UL)         /*!< PGACHBVCMGENPDNB (Bitfield-Mask: 0x01)                */
42400 #define MCUCTRL_PGACTRL2_PGACHBOPAMPOUTPDNB_Pos (22UL)              /*!< PGACHBOPAMPOUTPDNB (Bit 22)                           */
42401 #define MCUCTRL_PGACTRL2_PGACHBOPAMPOUTPDNB_Msk (0xc00000UL)        /*!< PGACHBOPAMPOUTPDNB (Bitfield-Mask: 0x03)              */
42402 #define MCUCTRL_PGACTRL2_PGACHBOPAMPINPDNB_Pos (20UL)               /*!< PGACHBOPAMPINPDNB (Bit 20)                            */
42403 #define MCUCTRL_PGACTRL2_PGACHBOPAMPINPDNB_Msk (0x300000UL)         /*!< PGACHBOPAMPINPDNB (Bitfield-Mask: 0x03)               */
42404 #define MCUCTRL_PGACTRL2_PGACHBBYPASSEN_Pos (18UL)                  /*!< PGACHBBYPASSEN (Bit 18)                               */
42405 #define MCUCTRL_PGACTRL2_PGACHBBYPASSEN_Msk (0xc0000UL)             /*!< PGACHBBYPASSEN (Bitfield-Mask: 0x03)                  */
42406 #define MCUCTRL_PGACTRL2_PGACHB1GAIN2SEL_Pos (13UL)                 /*!< PGACHB1GAIN2SEL (Bit 13)                              */
42407 #define MCUCTRL_PGACTRL2_PGACHB1GAIN2SEL_Msk (0x3e000UL)            /*!< PGACHB1GAIN2SEL (Bitfield-Mask: 0x1f)                 */
42408 #define MCUCTRL_PGACTRL2_PGACHB1GAIN2DIV2SEL_Pos (12UL)             /*!< PGACHB1GAIN2DIV2SEL (Bit 12)                          */
42409 #define MCUCTRL_PGACTRL2_PGACHB1GAIN2DIV2SEL_Msk (0x1000UL)         /*!< PGACHB1GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
42410 #define MCUCTRL_PGACTRL2_PGACHB1GAIN1SEL_Pos (9UL)                  /*!< PGACHB1GAIN1SEL (Bit 9)                               */
42411 #define MCUCTRL_PGACTRL2_PGACHB1GAIN1SEL_Msk (0xe00UL)              /*!< PGACHB1GAIN1SEL (Bitfield-Mask: 0x07)                 */
42412 #define MCUCTRL_PGACTRL2_PGACHB0GAIN2SEL_Pos (4UL)                  /*!< PGACHB0GAIN2SEL (Bit 4)                               */
42413 #define MCUCTRL_PGACTRL2_PGACHB0GAIN2SEL_Msk (0x1f0UL)              /*!< PGACHB0GAIN2SEL (Bitfield-Mask: 0x1f)                 */
42414 #define MCUCTRL_PGACTRL2_PGACHB0GAIN2DIV2SEL_Pos (3UL)              /*!< PGACHB0GAIN2DIV2SEL (Bit 3)                           */
42415 #define MCUCTRL_PGACTRL2_PGACHB0GAIN2DIV2SEL_Msk (0x8UL)            /*!< PGACHB0GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
42416 #define MCUCTRL_PGACTRL2_PGACHB0GAIN1SEL_Pos (0UL)                  /*!< PGACHB0GAIN1SEL (Bit 0)                               */
42417 #define MCUCTRL_PGACTRL2_PGACHB0GAIN1SEL_Msk (0x7UL)                /*!< PGACHB0GAIN1SEL (Bitfield-Mask: 0x07)                 */
42418 /* =====================================================  AUDADCPWRDLY  ====================================================== */
42419 #define MCUCTRL_AUDADCPWRDLY_AUDADCPWR1_Pos (8UL)                   /*!< AUDADCPWR1 (Bit 8)                                    */
42420 #define MCUCTRL_AUDADCPWRDLY_AUDADCPWR1_Msk (0xff00UL)              /*!< AUDADCPWR1 (Bitfield-Mask: 0xff)                      */
42421 #define MCUCTRL_AUDADCPWRDLY_AUDADCPWR0_Pos (0UL)                   /*!< AUDADCPWR0 (Bit 0)                                    */
42422 #define MCUCTRL_AUDADCPWRDLY_AUDADCPWR0_Msk (0xffUL)                /*!< AUDADCPWR0 (Bitfield-Mask: 0xff)                      */
42423 /* =======================================================  SDIOCTRL  ======================================================== */
42424 #define MCUCTRL_SDIOCTRL_SDIODATOPENDRAINEN_Pos (18UL)              /*!< SDIODATOPENDRAINEN (Bit 18)                           */
42425 #define MCUCTRL_SDIOCTRL_SDIODATOPENDRAINEN_Msk (0x40000UL)         /*!< SDIODATOPENDRAINEN (Bitfield-Mask: 0x01)              */
42426 #define MCUCTRL_SDIOCTRL_SDIOCMDOPENDRAINEN_Pos (17UL)              /*!< SDIOCMDOPENDRAINEN (Bit 17)                           */
42427 #define MCUCTRL_SDIOCTRL_SDIOCMDOPENDRAINEN_Msk (0x20000UL)         /*!< SDIOCMDOPENDRAINEN (Bitfield-Mask: 0x01)              */
42428 #define MCUCTRL_SDIOCTRL_SDIOXINCLKSEL_Pos (15UL)                   /*!< SDIOXINCLKSEL (Bit 15)                                */
42429 #define MCUCTRL_SDIOCTRL_SDIOXINCLKSEL_Msk (0x18000UL)              /*!< SDIOXINCLKSEL (Bitfield-Mask: 0x03)                   */
42430 #define MCUCTRL_SDIOCTRL_SDIOASYNCWKUPENA_Pos (14UL)                /*!< SDIOASYNCWKUPENA (Bit 14)                             */
42431 #define MCUCTRL_SDIOCTRL_SDIOASYNCWKUPENA_Msk (0x4000UL)            /*!< SDIOASYNCWKUPENA (Bitfield-Mask: 0x01)                */
42432 #define MCUCTRL_SDIOCTRL_SDIOOTAPDLYSEL_Pos (10UL)                  /*!< SDIOOTAPDLYSEL (Bit 10)                               */
42433 #define MCUCTRL_SDIOCTRL_SDIOOTAPDLYSEL_Msk (0x3c00UL)              /*!< SDIOOTAPDLYSEL (Bitfield-Mask: 0x0f)                  */
42434 #define MCUCTRL_SDIOCTRL_SDIOOTAPDLYENA_Pos (9UL)                   /*!< SDIOOTAPDLYENA (Bit 9)                                */
42435 #define MCUCTRL_SDIOCTRL_SDIOOTAPDLYENA_Msk (0x200UL)               /*!< SDIOOTAPDLYENA (Bitfield-Mask: 0x01)                  */
42436 #define MCUCTRL_SDIOCTRL_SDIOITAPDLYSEL_Pos (4UL)                   /*!< SDIOITAPDLYSEL (Bit 4)                                */
42437 #define MCUCTRL_SDIOCTRL_SDIOITAPDLYSEL_Msk (0x1f0UL)               /*!< SDIOITAPDLYSEL (Bitfield-Mask: 0x1f)                  */
42438 #define MCUCTRL_SDIOCTRL_SDIOITAPDLYENA_Pos (3UL)                   /*!< SDIOITAPDLYENA (Bit 3)                                */
42439 #define MCUCTRL_SDIOCTRL_SDIOITAPDLYENA_Msk (0x8UL)                 /*!< SDIOITAPDLYENA (Bitfield-Mask: 0x01)                  */
42440 #define MCUCTRL_SDIOCTRL_SDIOITAPCHGWIN_Pos (2UL)                   /*!< SDIOITAPCHGWIN (Bit 2)                                */
42441 #define MCUCTRL_SDIOCTRL_SDIOITAPCHGWIN_Msk (0x4UL)                 /*!< SDIOITAPCHGWIN (Bitfield-Mask: 0x01)                  */
42442 #define MCUCTRL_SDIOCTRL_SDIOXINCLKEN_Pos (1UL)                     /*!< SDIOXINCLKEN (Bit 1)                                  */
42443 #define MCUCTRL_SDIOCTRL_SDIOXINCLKEN_Msk (0x2UL)                   /*!< SDIOXINCLKEN (Bitfield-Mask: 0x01)                    */
42444 #define MCUCTRL_SDIOCTRL_SDIOSYSCLKEN_Pos (0UL)                     /*!< SDIOSYSCLKEN (Bit 0)                                  */
42445 #define MCUCTRL_SDIOCTRL_SDIOSYSCLKEN_Msk (0x1UL)                   /*!< SDIOSYSCLKEN (Bitfield-Mask: 0x01)                    */
42446 /* ========================================================  PDMCTRL  ======================================================== */
42447 #define MCUCTRL_PDMCTRL_PDMGLOBALEN_Pos   (0UL)                     /*!< PDMGLOBALEN (Bit 0)                                   */
42448 #define MCUCTRL_PDMCTRL_PDMGLOBALEN_Msk   (0x1UL)                   /*!< PDMGLOBALEN (Bitfield-Mask: 0x01)                     */
42449 
42450 
42451 /* =========================================================================================================================== */
42452 /* ================                                           MSPI0                                           ================ */
42453 /* =========================================================================================================================== */
42454 
42455 /* =========================================================  CTRL  ========================================================== */
42456 #define MSPI0_CTRL_XFERBYTES_Pos          (16UL)                    /*!< XFERBYTES (Bit 16)                                    */
42457 #define MSPI0_CTRL_XFERBYTES_Msk          (0xffff0000UL)            /*!< XFERBYTES (Bitfield-Mask: 0xffff)                     */
42458 #define MSPI0_CTRL_ENWLAT_Pos             (12UL)                    /*!< ENWLAT (Bit 12)                                       */
42459 #define MSPI0_CTRL_ENWLAT_Msk             (0x1000UL)                /*!< ENWLAT (Bitfield-Mask: 0x01)                          */
42460 #define MSPI0_CTRL_ENDCX_Pos              (11UL)                    /*!< ENDCX (Bit 11)                                        */
42461 #define MSPI0_CTRL_ENDCX_Msk              (0x800UL)                 /*!< ENDCX (Bitfield-Mask: 0x01)                           */
42462 #define MSPI0_CTRL_ENTURN_Pos             (10UL)                    /*!< ENTURN (Bit 10)                                       */
42463 #define MSPI0_CTRL_ENTURN_Msk             (0x400UL)                 /*!< ENTURN (Bitfield-Mask: 0x01)                          */
42464 #define MSPI0_CTRL_PIOSCRAMBLE_Pos        (9UL)                     /*!< PIOSCRAMBLE (Bit 9)                                   */
42465 #define MSPI0_CTRL_PIOSCRAMBLE_Msk        (0x200UL)                 /*!< PIOSCRAMBLE (Bitfield-Mask: 0x01)                     */
42466 #define MSPI0_CTRL_BIGENDIAN_Pos          (8UL)                     /*!< BIGENDIAN (Bit 8)                                     */
42467 #define MSPI0_CTRL_BIGENDIAN_Msk          (0x100UL)                 /*!< BIGENDIAN (Bitfield-Mask: 0x01)                       */
42468 #define MSPI0_CTRL_TXRX_Pos               (7UL)                     /*!< TXRX (Bit 7)                                          */
42469 #define MSPI0_CTRL_TXRX_Msk               (0x80UL)                  /*!< TXRX (Bitfield-Mask: 0x01)                            */
42470 #define MSPI0_CTRL_SENDI_Pos              (6UL)                     /*!< SENDI (Bit 6)                                         */
42471 #define MSPI0_CTRL_SENDI_Msk              (0x40UL)                  /*!< SENDI (Bitfield-Mask: 0x01)                           */
42472 #define MSPI0_CTRL_SENDA_Pos              (5UL)                     /*!< SENDA (Bit 5)                                         */
42473 #define MSPI0_CTRL_SENDA_Msk              (0x20UL)                  /*!< SENDA (Bitfield-Mask: 0x01)                           */
42474 #define MSPI0_CTRL_PIODEV_Pos             (4UL)                     /*!< PIODEV (Bit 4)                                        */
42475 #define MSPI0_CTRL_PIODEV_Msk             (0x10UL)                  /*!< PIODEV (Bitfield-Mask: 0x01)                          */
42476 #define MSPI0_CTRL_BUSY_Pos               (2UL)                     /*!< BUSY (Bit 2)                                          */
42477 #define MSPI0_CTRL_BUSY_Msk               (0x4UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
42478 #define MSPI0_CTRL_STATUS_Pos             (1UL)                     /*!< STATUS (Bit 1)                                        */
42479 #define MSPI0_CTRL_STATUS_Msk             (0x2UL)                   /*!< STATUS (Bitfield-Mask: 0x01)                          */
42480 #define MSPI0_CTRL_START_Pos              (0UL)                     /*!< START (Bit 0)                                         */
42481 #define MSPI0_CTRL_START_Msk              (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
42482 /* =========================================================  CTRL1  ========================================================= */
42483 #define MSPI0_CTRL1_PIOMIXED_Pos          (0UL)                     /*!< PIOMIXED (Bit 0)                                      */
42484 #define MSPI0_CTRL1_PIOMIXED_Msk          (0xfUL)                   /*!< PIOMIXED (Bitfield-Mask: 0x0f)                        */
42485 /* =========================================================  ADDR  ========================================================== */
42486 #define MSPI0_ADDR_ADDR_Pos               (0UL)                     /*!< ADDR (Bit 0)                                          */
42487 #define MSPI0_ADDR_ADDR_Msk               (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
42488 /* =========================================================  INSTR  ========================================================= */
42489 #define MSPI0_INSTR_INSTR_Pos             (0UL)                     /*!< INSTR (Bit 0)                                         */
42490 #define MSPI0_INSTR_INSTR_Msk             (0xffffUL)                /*!< INSTR (Bitfield-Mask: 0xffff)                         */
42491 /* ========================================================  TXFIFO  ========================================================= */
42492 #define MSPI0_TXFIFO_TXFIFO_Pos           (0UL)                     /*!< TXFIFO (Bit 0)                                        */
42493 #define MSPI0_TXFIFO_TXFIFO_Msk           (0xffffffffUL)            /*!< TXFIFO (Bitfield-Mask: 0xffffffff)                    */
42494 /* ========================================================  RXFIFO  ========================================================= */
42495 #define MSPI0_RXFIFO_RXFIFO_Pos           (0UL)                     /*!< RXFIFO (Bit 0)                                        */
42496 #define MSPI0_RXFIFO_RXFIFO_Msk           (0xffffffffUL)            /*!< RXFIFO (Bitfield-Mask: 0xffffffff)                    */
42497 /* =======================================================  TXENTRIES  ======================================================= */
42498 #define MSPI0_TXENTRIES_TXENTRIES_Pos     (0UL)                     /*!< TXENTRIES (Bit 0)                                     */
42499 #define MSPI0_TXENTRIES_TXENTRIES_Msk     (0x3fUL)                  /*!< TXENTRIES (Bitfield-Mask: 0x3f)                       */
42500 /* =======================================================  RXENTRIES  ======================================================= */
42501 #define MSPI0_RXENTRIES_RXENTRIES_Pos     (0UL)                     /*!< RXENTRIES (Bit 0)                                     */
42502 #define MSPI0_RXENTRIES_RXENTRIES_Msk     (0x3fUL)                  /*!< RXENTRIES (Bitfield-Mask: 0x3f)                       */
42503 /* =======================================================  THRESHOLD  ======================================================= */
42504 #define MSPI0_THRESHOLD_RXTHRESH_Pos      (8UL)                     /*!< RXTHRESH (Bit 8)                                      */
42505 #define MSPI0_THRESHOLD_RXTHRESH_Msk      (0x3f00UL)                /*!< RXTHRESH (Bitfield-Mask: 0x3f)                        */
42506 #define MSPI0_THRESHOLD_TXTHRESH_Pos      (0UL)                     /*!< TXTHRESH (Bit 0)                                      */
42507 #define MSPI0_THRESHOLD_TXTHRESH_Msk      (0x3fUL)                  /*!< TXTHRESH (Bitfield-Mask: 0x3f)                        */
42508 /* ========================================================  MSPICFG  ======================================================== */
42509 #define MSPI0_MSPICFG_PRSTN_Pos           (31UL)                    /*!< PRSTN (Bit 31)                                        */
42510 #define MSPI0_MSPICFG_PRSTN_Msk           (0x80000000UL)            /*!< PRSTN (Bitfield-Mask: 0x01)                           */
42511 #define MSPI0_MSPICFG_IPRSTN_Pos          (30UL)                    /*!< IPRSTN (Bit 30)                                       */
42512 #define MSPI0_MSPICFG_IPRSTN_Msk          (0x40000000UL)            /*!< IPRSTN (Bitfield-Mask: 0x01)                          */
42513 #define MSPI0_MSPICFG_FIFORESET_Pos       (29UL)                    /*!< FIFORESET (Bit 29)                                    */
42514 #define MSPI0_MSPICFG_FIFORESET_Msk       (0x20000000UL)            /*!< FIFORESET (Bitfield-Mask: 0x01)                       */
42515 #define MSPI0_MSPICFG_IOMSEL_Pos          (4UL)                     /*!< IOMSEL (Bit 4)                                        */
42516 #define MSPI0_MSPICFG_IOMSEL_Msk          (0xf0UL)                  /*!< IOMSEL (Bitfield-Mask: 0x0f)                          */
42517 #define MSPI0_MSPICFG_APBCLK_Pos          (0UL)                     /*!< APBCLK (Bit 0)                                        */
42518 #define MSPI0_MSPICFG_APBCLK_Msk          (0x1UL)                   /*!< APBCLK (Bitfield-Mask: 0x01)                          */
42519 /* =======================================================  PADOUTEN  ======================================================== */
42520 #define MSPI0_PADOUTEN_CLKOND4_Pos        (31UL)                    /*!< CLKOND4 (Bit 31)                                      */
42521 #define MSPI0_PADOUTEN_CLKOND4_Msk        (0x80000000UL)            /*!< CLKOND4 (Bitfield-Mask: 0x01)                         */
42522 #define MSPI0_PADOUTEN_PADSET1_Pos        (30UL)                    /*!< PADSET1 (Bit 30)                                      */
42523 #define MSPI0_PADOUTEN_PADSET1_Msk        (0x40000000UL)            /*!< PADSET1 (Bitfield-Mask: 0x01)                         */
42524 #define MSPI0_PADOUTEN_OUTEN_Pos          (0UL)                     /*!< OUTEN (Bit 0)                                         */
42525 #define MSPI0_PADOUTEN_OUTEN_Msk          (0xfffffUL)               /*!< OUTEN (Bitfield-Mask: 0xfffff)                        */
42526 /* =======================================================  PADOVEREN  ======================================================= */
42527 #define MSPI0_PADOVEREN_OVERRIDEEN_Pos    (0UL)                     /*!< OVERRIDEEN (Bit 0)                                    */
42528 #define MSPI0_PADOVEREN_OVERRIDEEN_Msk    (0xfffffUL)               /*!< OVERRIDEEN (Bitfield-Mask: 0xfffff)                   */
42529 /* ========================================================  PADOVER  ======================================================== */
42530 #define MSPI0_PADOVER_OVERRIDE_Pos        (0UL)                     /*!< OVERRIDE (Bit 0)                                      */
42531 #define MSPI0_PADOVER_OVERRIDE_Msk        (0xfffffUL)               /*!< OVERRIDE (Bitfield-Mask: 0xfffff)                     */
42532 /* ========================================================  DEV0AXI  ======================================================== */
42533 #define MSPI0_DEV0AXI_BASE0_Pos           (16UL)                    /*!< BASE0 (Bit 16)                                        */
42534 #define MSPI0_DEV0AXI_BASE0_Msk           (0x3ff0000UL)             /*!< BASE0 (Bitfield-Mask: 0x3ff)                          */
42535 #define MSPI0_DEV0AXI_READONLY0_Pos       (4UL)                     /*!< READONLY0 (Bit 4)                                     */
42536 #define MSPI0_DEV0AXI_READONLY0_Msk       (0x10UL)                  /*!< READONLY0 (Bitfield-Mask: 0x01)                       */
42537 #define MSPI0_DEV0AXI_SIZE0_Pos           (0UL)                     /*!< SIZE0 (Bit 0)                                         */
42538 #define MSPI0_DEV0AXI_SIZE0_Msk           (0xfUL)                   /*!< SIZE0 (Bitfield-Mask: 0x0f)                           */
42539 /* ========================================================  DEV0CFG  ======================================================== */
42540 #define MSPI0_DEV0CFG_WRITELATENCY0_Pos   (26UL)                    /*!< WRITELATENCY0 (Bit 26)                                */
42541 #define MSPI0_DEV0CFG_WRITELATENCY0_Msk   (0xfc000000UL)            /*!< WRITELATENCY0 (Bitfield-Mask: 0x3f)                   */
42542 #define MSPI0_DEV0CFG_SEPIO0_Pos          (25UL)                    /*!< SEPIO0 (Bit 25)                                       */
42543 #define MSPI0_DEV0CFG_SEPIO0_Msk          (0x2000000UL)             /*!< SEPIO0 (Bitfield-Mask: 0x01)                          */
42544 #define MSPI0_DEV0CFG_TXNEG0_Pos          (24UL)                    /*!< TXNEG0 (Bit 24)                                       */
42545 #define MSPI0_DEV0CFG_TXNEG0_Msk          (0x1000000UL)             /*!< TXNEG0 (Bitfield-Mask: 0x01)                          */
42546 #define MSPI0_DEV0CFG_RXNEG0_Pos          (23UL)                    /*!< RXNEG0 (Bit 23)                                       */
42547 #define MSPI0_DEV0CFG_RXNEG0_Msk          (0x800000UL)              /*!< RXNEG0 (Bitfield-Mask: 0x01)                          */
42548 #define MSPI0_DEV0CFG_RXCAP0_Pos          (22UL)                    /*!< RXCAP0 (Bit 22)                                       */
42549 #define MSPI0_DEV0CFG_RXCAP0_Msk          (0x400000UL)              /*!< RXCAP0 (Bitfield-Mask: 0x01)                          */
42550 #define MSPI0_DEV0CFG_CLKDIV0_Pos         (16UL)                    /*!< CLKDIV0 (Bit 16)                                      */
42551 #define MSPI0_DEV0CFG_CLKDIV0_Msk         (0x3f0000UL)              /*!< CLKDIV0 (Bitfield-Mask: 0x3f)                         */
42552 #define MSPI0_DEV0CFG_CPOL0_Pos           (15UL)                    /*!< CPOL0 (Bit 15)                                        */
42553 #define MSPI0_DEV0CFG_CPOL0_Msk           (0x8000UL)                /*!< CPOL0 (Bitfield-Mask: 0x01)                           */
42554 #define MSPI0_DEV0CFG_CPHA0_Pos           (14UL)                    /*!< CPHA0 (Bit 14)                                        */
42555 #define MSPI0_DEV0CFG_CPHA0_Msk           (0x4000UL)                /*!< CPHA0 (Bitfield-Mask: 0x01)                           */
42556 #define MSPI0_DEV0CFG_TURNAROUND0_Pos     (8UL)                     /*!< TURNAROUND0 (Bit 8)                                   */
42557 #define MSPI0_DEV0CFG_TURNAROUND0_Msk     (0x3f00UL)                /*!< TURNAROUND0 (Bitfield-Mask: 0x3f)                     */
42558 #define MSPI0_DEV0CFG_ISIZE0_Pos          (7UL)                     /*!< ISIZE0 (Bit 7)                                        */
42559 #define MSPI0_DEV0CFG_ISIZE0_Msk          (0x80UL)                  /*!< ISIZE0 (Bitfield-Mask: 0x01)                          */
42560 #define MSPI0_DEV0CFG_ASIZE0_Pos          (5UL)                     /*!< ASIZE0 (Bit 5)                                        */
42561 #define MSPI0_DEV0CFG_ASIZE0_Msk          (0x60UL)                  /*!< ASIZE0 (Bitfield-Mask: 0x03)                          */
42562 #define MSPI0_DEV0CFG_DEVCFG0_Pos         (0UL)                     /*!< DEVCFG0 (Bit 0)                                       */
42563 #define MSPI0_DEV0CFG_DEVCFG0_Msk         (0x1fUL)                  /*!< DEVCFG0 (Bitfield-Mask: 0x1f)                         */
42564 /* ========================================================  DEV0DDR  ======================================================== */
42565 #define MSPI0_DEV0DDR_RXDQSDELAYHIEN0_Pos (31UL)                    /*!< RXDQSDELAYHIEN0 (Bit 31)                              */
42566 #define MSPI0_DEV0DDR_RXDQSDELAYHIEN0_Msk (0x80000000UL)            /*!< RXDQSDELAYHIEN0 (Bitfield-Mask: 0x01)                 */
42567 #define MSPI0_DEV0DDR_RXDQSDELAYNEGHI0_Pos (26UL)                   /*!< RXDQSDELAYNEGHI0 (Bit 26)                             */
42568 #define MSPI0_DEV0DDR_RXDQSDELAYNEGHI0_Msk (0x7c000000UL)           /*!< RXDQSDELAYNEGHI0 (Bitfield-Mask: 0x1f)                */
42569 #define MSPI0_DEV0DDR_RXDQSDELAYHI0_Pos   (21UL)                    /*!< RXDQSDELAYHI0 (Bit 21)                                */
42570 #define MSPI0_DEV0DDR_RXDQSDELAYHI0_Msk   (0x3e00000UL)             /*!< RXDQSDELAYHI0 (Bitfield-Mask: 0x1f)                   */
42571 #define MSPI0_DEV0DDR_RXDQSDELAYNEGEN0_Pos (20UL)                   /*!< RXDQSDELAYNEGEN0 (Bit 20)                             */
42572 #define MSPI0_DEV0DDR_RXDQSDELAYNEGEN0_Msk (0x100000UL)             /*!< RXDQSDELAYNEGEN0 (Bitfield-Mask: 0x01)                */
42573 #define MSPI0_DEV0DDR_RXDQSDELAYNEG0_Pos  (15UL)                    /*!< RXDQSDELAYNEG0 (Bit 15)                               */
42574 #define MSPI0_DEV0DDR_RXDQSDELAYNEG0_Msk  (0xf8000UL)               /*!< RXDQSDELAYNEG0 (Bitfield-Mask: 0x1f)                  */
42575 #define MSPI0_DEV0DDR_RXDQSDELAY0_Pos     (10UL)                    /*!< RXDQSDELAY0 (Bit 10)                                  */
42576 #define MSPI0_DEV0DDR_RXDQSDELAY0_Msk     (0x7c00UL)                /*!< RXDQSDELAY0 (Bitfield-Mask: 0x1f)                     */
42577 #define MSPI0_DEV0DDR_TXDQSDELAY0_Pos     (5UL)                     /*!< TXDQSDELAY0 (Bit 5)                                   */
42578 #define MSPI0_DEV0DDR_TXDQSDELAY0_Msk     (0x3e0UL)                 /*!< TXDQSDELAY0 (Bitfield-Mask: 0x1f)                     */
42579 #define MSPI0_DEV0DDR_ENABLEFINEDELAY0_Pos (4UL)                    /*!< ENABLEFINEDELAY0 (Bit 4)                              */
42580 #define MSPI0_DEV0DDR_ENABLEFINEDELAY0_Msk (0x10UL)                 /*!< ENABLEFINEDELAY0 (Bitfield-Mask: 0x01)                */
42581 #define MSPI0_DEV0DDR_DQSSYNCNEG0_Pos     (3UL)                     /*!< DQSSYNCNEG0 (Bit 3)                                   */
42582 #define MSPI0_DEV0DDR_DQSSYNCNEG0_Msk     (0x8UL)                   /*!< DQSSYNCNEG0 (Bitfield-Mask: 0x01)                     */
42583 #define MSPI0_DEV0DDR_ENABLEDQS0_Pos      (2UL)                     /*!< ENABLEDQS0 (Bit 2)                                    */
42584 #define MSPI0_DEV0DDR_ENABLEDQS0_Msk      (0x4UL)                   /*!< ENABLEDQS0 (Bitfield-Mask: 0x01)                      */
42585 #define MSPI0_DEV0DDR_QUADDDR0_Pos        (1UL)                     /*!< QUADDDR0 (Bit 1)                                      */
42586 #define MSPI0_DEV0DDR_QUADDDR0_Msk        (0x2UL)                   /*!< QUADDDR0 (Bitfield-Mask: 0x01)                        */
42587 #define MSPI0_DEV0DDR_EMULATEDDR0_Pos     (0UL)                     /*!< EMULATEDDR0 (Bit 0)                                   */
42588 #define MSPI0_DEV0DDR_EMULATEDDR0_Msk     (0x1UL)                   /*!< EMULATEDDR0 (Bitfield-Mask: 0x01)                     */
42589 /* =======================================================  DEV0CFG1  ======================================================== */
42590 #define MSPI0_DEV0CFG1_DQSTURN0_Pos       (14UL)                    /*!< DQSTURN0 (Bit 14)                                     */
42591 #define MSPI0_DEV0CFG1_DQSTURN0_Msk       (0x1c000UL)               /*!< DQSTURN0 (Bitfield-Mask: 0x07)                        */
42592 #define MSPI0_DEV0CFG1_RXHI0_Pos          (13UL)                    /*!< RXHI0 (Bit 13)                                        */
42593 #define MSPI0_DEV0CFG1_RXHI0_Msk          (0x2000UL)                /*!< RXHI0 (Bitfield-Mask: 0x01)                           */
42594 #define MSPI0_DEV0CFG1_TAFOURTH0_Pos      (12UL)                    /*!< TAFOURTH0 (Bit 12)                                    */
42595 #define MSPI0_DEV0CFG1_TAFOURTH0_Msk      (0x1000UL)                /*!< TAFOURTH0 (Bitfield-Mask: 0x01)                       */
42596 #define MSPI0_DEV0CFG1_HYPERIO0_Pos       (11UL)                    /*!< HYPERIO0 (Bit 11)                                     */
42597 #define MSPI0_DEV0CFG1_HYPERIO0_Msk       (0x800UL)                 /*!< HYPERIO0 (Bitfield-Mask: 0x01)                        */
42598 #define MSPI0_DEV0CFG1_RXSMP0_Pos         (9UL)                     /*!< RXSMP0 (Bit 9)                                        */
42599 #define MSPI0_DEV0CFG1_RXSMP0_Msk         (0x600UL)                 /*!< RXSMP0 (Bitfield-Mask: 0x03)                          */
42600 #define MSPI0_DEV0CFG1_RBX0_Pos           (8UL)                     /*!< RBX0 (Bit 8)                                          */
42601 #define MSPI0_DEV0CFG1_RBX0_Msk           (0x100UL)                 /*!< RBX0 (Bitfield-Mask: 0x01)                            */
42602 #define MSPI0_DEV0CFG1_WBX0_Pos           (7UL)                     /*!< WBX0 (Bit 7)                                          */
42603 #define MSPI0_DEV0CFG1_WBX0_Msk           (0x80UL)                  /*!< WBX0 (Bitfield-Mask: 0x01)                            */
42604 #define MSPI0_DEV0CFG1_SCLKRXHALT0_Pos    (5UL)                     /*!< SCLKRXHALT0 (Bit 5)                                   */
42605 #define MSPI0_DEV0CFG1_SCLKRXHALT0_Msk    (0x20UL)                  /*!< SCLKRXHALT0 (Bitfield-Mask: 0x01)                     */
42606 #define MSPI0_DEV0CFG1_RXCAPEXT0_Pos      (4UL)                     /*!< RXCAPEXT0 (Bit 4)                                     */
42607 #define MSPI0_DEV0CFG1_RXCAPEXT0_Msk      (0x10UL)                  /*!< RXCAPEXT0 (Bitfield-Mask: 0x01)                       */
42608 #define MSPI0_DEV0CFG1_SFTURN0_Pos        (0UL)                     /*!< SFTURN0 (Bit 0)                                       */
42609 #define MSPI0_DEV0CFG1_SFTURN0_Msk        (0xfUL)                   /*!< SFTURN0 (Bitfield-Mask: 0x0f)                         */
42610 /* ========================================================  DEV0XIP  ======================================================== */
42611 #define MSPI0_DEV0XIP_XIPWRITELATENCY0_Pos (20UL)                   /*!< XIPWRITELATENCY0 (Bit 20)                             */
42612 #define MSPI0_DEV0XIP_XIPWRITELATENCY0_Msk (0x3f00000UL)            /*!< XIPWRITELATENCY0 (Bitfield-Mask: 0x3f)                */
42613 #define MSPI0_DEV0XIP_XIPTURNAROUND0_Pos  (14UL)                    /*!< XIPTURNAROUND0 (Bit 14)                               */
42614 #define MSPI0_DEV0XIP_XIPTURNAROUND0_Msk  (0xfc000UL)               /*!< XIPTURNAROUND0 (Bitfield-Mask: 0x3f)                  */
42615 #define MSPI0_DEV0XIP_XIPENWLAT0_Pos      (13UL)                    /*!< XIPENWLAT0 (Bit 13)                                   */
42616 #define MSPI0_DEV0XIP_XIPENWLAT0_Msk      (0x2000UL)                /*!< XIPENWLAT0 (Bitfield-Mask: 0x01)                      */
42617 #define MSPI0_DEV0XIP_XIPENDCX0_Pos       (12UL)                    /*!< XIPENDCX0 (Bit 12)                                    */
42618 #define MSPI0_DEV0XIP_XIPENDCX0_Msk       (0x1000UL)                /*!< XIPENDCX0 (Bitfield-Mask: 0x01)                       */
42619 #define MSPI0_DEV0XIP_XIPMIXED0_Pos       (8UL)                     /*!< XIPMIXED0 (Bit 8)                                     */
42620 #define MSPI0_DEV0XIP_XIPMIXED0_Msk       (0xf00UL)                 /*!< XIPMIXED0 (Bitfield-Mask: 0x0f)                       */
42621 #define MSPI0_DEV0XIP_XIPSENDI0_Pos       (7UL)                     /*!< XIPSENDI0 (Bit 7)                                     */
42622 #define MSPI0_DEV0XIP_XIPSENDI0_Msk       (0x80UL)                  /*!< XIPSENDI0 (Bitfield-Mask: 0x01)                       */
42623 #define MSPI0_DEV0XIP_XIPSENDA0_Pos       (6UL)                     /*!< XIPSENDA0 (Bit 6)                                     */
42624 #define MSPI0_DEV0XIP_XIPSENDA0_Msk       (0x40UL)                  /*!< XIPSENDA0 (Bitfield-Mask: 0x01)                       */
42625 #define MSPI0_DEV0XIP_XIPENTURN0_Pos      (5UL)                     /*!< XIPENTURN0 (Bit 5)                                    */
42626 #define MSPI0_DEV0XIP_XIPENTURN0_Msk      (0x20UL)                  /*!< XIPENTURN0 (Bitfield-Mask: 0x01)                      */
42627 #define MSPI0_DEV0XIP_XIPBIGENDIAN0_Pos   (4UL)                     /*!< XIPBIGENDIAN0 (Bit 4)                                 */
42628 #define MSPI0_DEV0XIP_XIPBIGENDIAN0_Msk   (0x10UL)                  /*!< XIPBIGENDIAN0 (Bitfield-Mask: 0x01)                   */
42629 #define MSPI0_DEV0XIP_XIPACK0_Pos         (2UL)                     /*!< XIPACK0 (Bit 2)                                       */
42630 #define MSPI0_DEV0XIP_XIPACK0_Msk         (0xcUL)                   /*!< XIPACK0 (Bitfield-Mask: 0x03)                         */
42631 #define MSPI0_DEV0XIP_XIPEN0_Pos          (0UL)                     /*!< XIPEN0 (Bit 0)                                        */
42632 #define MSPI0_DEV0XIP_XIPEN0_Msk          (0x1UL)                   /*!< XIPEN0 (Bitfield-Mask: 0x01)                          */
42633 /* =======================================================  DEV0INSTR  ======================================================= */
42634 #define MSPI0_DEV0INSTR_READINSTR0_Pos    (16UL)                    /*!< READINSTR0 (Bit 16)                                   */
42635 #define MSPI0_DEV0INSTR_READINSTR0_Msk    (0xffff0000UL)            /*!< READINSTR0 (Bitfield-Mask: 0xffff)                    */
42636 #define MSPI0_DEV0INSTR_WRITEINSTR0_Pos   (0UL)                     /*!< WRITEINSTR0 (Bit 0)                                   */
42637 #define MSPI0_DEV0INSTR_WRITEINSTR0_Msk   (0xffffUL)                /*!< WRITEINSTR0 (Bitfield-Mask: 0xffff)                   */
42638 /* =====================================================  DEV0BOUNDARY  ====================================================== */
42639 #define MSPI0_DEV0BOUNDARY_DMABOUND0_Pos  (12UL)                    /*!< DMABOUND0 (Bit 12)                                    */
42640 #define MSPI0_DEV0BOUNDARY_DMABOUND0_Msk  (0xf000UL)                /*!< DMABOUND0 (Bitfield-Mask: 0x0f)                       */
42641 #define MSPI0_DEV0BOUNDARY_DMATIMELIMIT0_Pos (0UL)                  /*!< DMATIMELIMIT0 (Bit 0)                                 */
42642 #define MSPI0_DEV0BOUNDARY_DMATIMELIMIT0_Msk (0xfffUL)              /*!< DMATIMELIMIT0 (Bitfield-Mask: 0xfff)                  */
42643 /* ====================================================  DEV0SCRAMBLING  ===================================================== */
42644 #define MSPI0_DEV0SCRAMBLING_SCRENABLE0_Pos (31UL)                  /*!< SCRENABLE0 (Bit 31)                                   */
42645 #define MSPI0_DEV0SCRAMBLING_SCRENABLE0_Msk (0x80000000UL)          /*!< SCRENABLE0 (Bitfield-Mask: 0x01)                      */
42646 #define MSPI0_DEV0SCRAMBLING_SCREND0_Pos  (16UL)                    /*!< SCREND0 (Bit 16)                                      */
42647 #define MSPI0_DEV0SCRAMBLING_SCREND0_Msk  (0x3ff0000UL)             /*!< SCREND0 (Bitfield-Mask: 0x3ff)                        */
42648 #define MSPI0_DEV0SCRAMBLING_SCRSTART0_Pos (0UL)                    /*!< SCRSTART0 (Bit 0)                                     */
42649 #define MSPI0_DEV0SCRAMBLING_SCRSTART0_Msk (0x3ffUL)                /*!< SCRSTART0 (Bitfield-Mask: 0x3ff)                      */
42650 /* ======================================================  DEV0XIPMISC  ====================================================== */
42651 #define MSPI0_DEV0XIPMISC_APNDODD0_Pos    (21UL)                    /*!< APNDODD0 (Bit 21)                                     */
42652 #define MSPI0_DEV0XIPMISC_APNDODD0_Msk    (0x200000UL)              /*!< APNDODD0 (Bitfield-Mask: 0x01)                        */
42653 #define MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Pos (15UL)                   /*!< XIPBOUNDARY0 (Bit 15)                                 */
42654 #define MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Msk (0x8000UL)               /*!< XIPBOUNDARY0 (Bitfield-Mask: 0x01)                    */
42655 #define MSPI0_DEV0XIPMISC_BEON0_Pos       (14UL)                    /*!< BEON0 (Bit 14)                                        */
42656 #define MSPI0_DEV0XIPMISC_BEON0_Msk       (0x4000UL)                /*!< BEON0 (Bitfield-Mask: 0x01)                           */
42657 #define MSPI0_DEV0XIPMISC_BEPOL0_Pos      (13UL)                    /*!< BEPOL0 (Bit 13)                                       */
42658 #define MSPI0_DEV0XIPMISC_BEPOL0_Msk      (0x2000UL)                /*!< BEPOL0 (Bitfield-Mask: 0x01)                          */
42659 #define MSPI0_DEV0XIPMISC_XIPODD0_Pos     (12UL)                    /*!< XIPODD0 (Bit 12)                                      */
42660 #define MSPI0_DEV0XIPMISC_XIPODD0_Msk     (0x1000UL)                /*!< XIPODD0 (Bitfield-Mask: 0x01)                         */
42661 #define MSPI0_DEV0XIPMISC_CEBREAK0_Pos    (0UL)                     /*!< CEBREAK0 (Bit 0)                                      */
42662 #define MSPI0_DEV0XIPMISC_CEBREAK0_Msk    (0xfffUL)                 /*!< CEBREAK0 (Bitfield-Mask: 0xfff)                       */
42663 /* ========================================================  DMACFG  ========================================================= */
42664 #define MSPI0_DMACFG_DMAPWROFF_Pos        (18UL)                    /*!< DMAPWROFF (Bit 18)                                    */
42665 #define MSPI0_DMACFG_DMAPWROFF_Msk        (0x40000UL)               /*!< DMAPWROFF (Bitfield-Mask: 0x01)                       */
42666 #define MSPI0_DMACFG_DMATXEMPT_Pos        (17UL)                    /*!< DMATXEMPT (Bit 17)                                    */
42667 #define MSPI0_DMACFG_DMATXEMPT_Msk        (0x20000UL)               /*!< DMATXEMPT (Bitfield-Mask: 0x01)                       */
42668 #define MSPI0_DMACFG_DMAPRI_Pos           (4UL)                     /*!< DMAPRI (Bit 4)                                        */
42669 #define MSPI0_DMACFG_DMAPRI_Msk           (0x30UL)                  /*!< DMAPRI (Bitfield-Mask: 0x03)                          */
42670 #define MSPI0_DMACFG_DMADEV_Pos           (3UL)                     /*!< DMADEV (Bit 3)                                        */
42671 #define MSPI0_DMACFG_DMADEV_Msk           (0x8UL)                   /*!< DMADEV (Bitfield-Mask: 0x01)                          */
42672 #define MSPI0_DMACFG_DMADIR_Pos           (2UL)                     /*!< DMADIR (Bit 2)                                        */
42673 #define MSPI0_DMACFG_DMADIR_Msk           (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
42674 #define MSPI0_DMACFG_DMAEN_Pos            (0UL)                     /*!< DMAEN (Bit 0)                                         */
42675 #define MSPI0_DMACFG_DMAEN_Msk            (0x3UL)                   /*!< DMAEN (Bitfield-Mask: 0x03)                           */
42676 /* ========================================================  DMASTAT  ======================================================== */
42677 #define MSPI0_DMASTAT_SCRERR_Pos          (3UL)                     /*!< SCRERR (Bit 3)                                        */
42678 #define MSPI0_DMASTAT_SCRERR_Msk          (0x8UL)                   /*!< SCRERR (Bitfield-Mask: 0x01)                          */
42679 #define MSPI0_DMASTAT_DMAERR_Pos          (2UL)                     /*!< DMAERR (Bit 2)                                        */
42680 #define MSPI0_DMASTAT_DMAERR_Msk          (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
42681 #define MSPI0_DMASTAT_DMACPL_Pos          (1UL)                     /*!< DMACPL (Bit 1)                                        */
42682 #define MSPI0_DMASTAT_DMACPL_Msk          (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
42683 #define MSPI0_DMASTAT_DMATIP_Pos          (0UL)                     /*!< DMATIP (Bit 0)                                        */
42684 #define MSPI0_DMASTAT_DMATIP_Msk          (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
42685 /* ======================================================  DMATARGADDR  ====================================================== */
42686 #define MSPI0_DMATARGADDR_TARGADDR_Pos    (0UL)                     /*!< TARGADDR (Bit 0)                                      */
42687 #define MSPI0_DMATARGADDR_TARGADDR_Msk    (0xffffffffUL)            /*!< TARGADDR (Bitfield-Mask: 0xffffffff)                  */
42688 /* ======================================================  DMADEVADDR  ======================================================= */
42689 #define MSPI0_DMADEVADDR_DEVADDR_Pos      (0UL)                     /*!< DEVADDR (Bit 0)                                       */
42690 #define MSPI0_DMADEVADDR_DEVADDR_Msk      (0xffffffffUL)            /*!< DEVADDR (Bitfield-Mask: 0xffffffff)                   */
42691 /* ======================================================  DMATOTCOUNT  ====================================================== */
42692 #define MSPI0_DMATOTCOUNT_TOTCOUNT_Pos    (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
42693 #define MSPI0_DMATOTCOUNT_TOTCOUNT_Msk    (0xffffffUL)              /*!< TOTCOUNT (Bitfield-Mask: 0xffffff)                    */
42694 /* =======================================================  DMABCOUNT  ======================================================= */
42695 #define MSPI0_DMABCOUNT_BCOUNT_Pos        (0UL)                     /*!< BCOUNT (Bit 0)                                        */
42696 #define MSPI0_DMABCOUNT_BCOUNT_Msk        (0xffUL)                  /*!< BCOUNT (Bitfield-Mask: 0xff)                          */
42697 /* =======================================================  DMATHRESH  ======================================================= */
42698 #define MSPI0_DMATHRESH_DMARXTHRESH_Pos   (8UL)                     /*!< DMARXTHRESH (Bit 8)                                   */
42699 #define MSPI0_DMATHRESH_DMARXTHRESH_Msk   (0x1f00UL)                /*!< DMARXTHRESH (Bitfield-Mask: 0x1f)                     */
42700 #define MSPI0_DMATHRESH_DMATXTHRESH_Pos   (0UL)                     /*!< DMATXTHRESH (Bit 0)                                   */
42701 #define MSPI0_DMATHRESH_DMATXTHRESH_Msk   (0x1fUL)                  /*!< DMATXTHRESH (Bitfield-Mask: 0x1f)                     */
42702 /* =========================================================  INTEN  ========================================================= */
42703 #define MSPI0_INTEN_APBDMAERR_Pos         (13UL)                    /*!< APBDMAERR (Bit 13)                                    */
42704 #define MSPI0_INTEN_APBDMAERR_Msk         (0x2000UL)                /*!< APBDMAERR (Bitfield-Mask: 0x01)                       */
42705 #define MSPI0_INTEN_SCRERR_Pos            (12UL)                    /*!< SCRERR (Bit 12)                                       */
42706 #define MSPI0_INTEN_SCRERR_Msk            (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
42707 #define MSPI0_INTEN_CQERR_Pos             (11UL)                    /*!< CQERR (Bit 11)                                        */
42708 #define MSPI0_INTEN_CQERR_Msk             (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
42709 #define MSPI0_INTEN_CQPAUSED_Pos          (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
42710 #define MSPI0_INTEN_CQPAUSED_Msk          (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
42711 #define MSPI0_INTEN_CQUPD_Pos             (9UL)                     /*!< CQUPD (Bit 9)                                         */
42712 #define MSPI0_INTEN_CQUPD_Msk             (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
42713 #define MSPI0_INTEN_CQCMP_Pos             (8UL)                     /*!< CQCMP (Bit 8)                                         */
42714 #define MSPI0_INTEN_CQCMP_Msk             (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
42715 #define MSPI0_INTEN_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
42716 #define MSPI0_INTEN_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42717 #define MSPI0_INTEN_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
42718 #define MSPI0_INTEN_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
42719 #define MSPI0_INTEN_RXF_Pos               (5UL)                     /*!< RXF (Bit 5)                                           */
42720 #define MSPI0_INTEN_RXF_Msk               (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
42721 #define MSPI0_INTEN_RXO_Pos               (4UL)                     /*!< RXO (Bit 4)                                           */
42722 #define MSPI0_INTEN_RXO_Msk               (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
42723 #define MSPI0_INTEN_RXU_Pos               (3UL)                     /*!< RXU (Bit 3)                                           */
42724 #define MSPI0_INTEN_RXU_Msk               (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
42725 #define MSPI0_INTEN_TXO_Pos               (2UL)                     /*!< TXO (Bit 2)                                           */
42726 #define MSPI0_INTEN_TXO_Msk               (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
42727 #define MSPI0_INTEN_TXE_Pos               (1UL)                     /*!< TXE (Bit 1)                                           */
42728 #define MSPI0_INTEN_TXE_Msk               (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
42729 #define MSPI0_INTEN_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
42730 #define MSPI0_INTEN_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
42731 /* ========================================================  INTSTAT  ======================================================== */
42732 #define MSPI0_INTSTAT_APBDMAERR_Pos       (13UL)                    /*!< APBDMAERR (Bit 13)                                    */
42733 #define MSPI0_INTSTAT_APBDMAERR_Msk       (0x2000UL)                /*!< APBDMAERR (Bitfield-Mask: 0x01)                       */
42734 #define MSPI0_INTSTAT_SCRERR_Pos          (12UL)                    /*!< SCRERR (Bit 12)                                       */
42735 #define MSPI0_INTSTAT_SCRERR_Msk          (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
42736 #define MSPI0_INTSTAT_CQERR_Pos           (11UL)                    /*!< CQERR (Bit 11)                                        */
42737 #define MSPI0_INTSTAT_CQERR_Msk           (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
42738 #define MSPI0_INTSTAT_CQPAUSED_Pos        (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
42739 #define MSPI0_INTSTAT_CQPAUSED_Msk        (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
42740 #define MSPI0_INTSTAT_CQUPD_Pos           (9UL)                     /*!< CQUPD (Bit 9)                                         */
42741 #define MSPI0_INTSTAT_CQUPD_Msk           (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
42742 #define MSPI0_INTSTAT_CQCMP_Pos           (8UL)                     /*!< CQCMP (Bit 8)                                         */
42743 #define MSPI0_INTSTAT_CQCMP_Msk           (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
42744 #define MSPI0_INTSTAT_DERR_Pos            (7UL)                     /*!< DERR (Bit 7)                                          */
42745 #define MSPI0_INTSTAT_DERR_Msk            (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42746 #define MSPI0_INTSTAT_DCMP_Pos            (6UL)                     /*!< DCMP (Bit 6)                                          */
42747 #define MSPI0_INTSTAT_DCMP_Msk            (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
42748 #define MSPI0_INTSTAT_RXF_Pos             (5UL)                     /*!< RXF (Bit 5)                                           */
42749 #define MSPI0_INTSTAT_RXF_Msk             (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
42750 #define MSPI0_INTSTAT_RXO_Pos             (4UL)                     /*!< RXO (Bit 4)                                           */
42751 #define MSPI0_INTSTAT_RXO_Msk             (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
42752 #define MSPI0_INTSTAT_RXU_Pos             (3UL)                     /*!< RXU (Bit 3)                                           */
42753 #define MSPI0_INTSTAT_RXU_Msk             (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
42754 #define MSPI0_INTSTAT_TXO_Pos             (2UL)                     /*!< TXO (Bit 2)                                           */
42755 #define MSPI0_INTSTAT_TXO_Msk             (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
42756 #define MSPI0_INTSTAT_TXE_Pos             (1UL)                     /*!< TXE (Bit 1)                                           */
42757 #define MSPI0_INTSTAT_TXE_Msk             (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
42758 #define MSPI0_INTSTAT_CMDCMP_Pos          (0UL)                     /*!< CMDCMP (Bit 0)                                        */
42759 #define MSPI0_INTSTAT_CMDCMP_Msk          (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
42760 /* ========================================================  INTCLR  ========================================================= */
42761 #define MSPI0_INTCLR_APBDMAERR_Pos        (13UL)                    /*!< APBDMAERR (Bit 13)                                    */
42762 #define MSPI0_INTCLR_APBDMAERR_Msk        (0x2000UL)                /*!< APBDMAERR (Bitfield-Mask: 0x01)                       */
42763 #define MSPI0_INTCLR_SCRERR_Pos           (12UL)                    /*!< SCRERR (Bit 12)                                       */
42764 #define MSPI0_INTCLR_SCRERR_Msk           (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
42765 #define MSPI0_INTCLR_CQERR_Pos            (11UL)                    /*!< CQERR (Bit 11)                                        */
42766 #define MSPI0_INTCLR_CQERR_Msk            (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
42767 #define MSPI0_INTCLR_CQPAUSED_Pos         (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
42768 #define MSPI0_INTCLR_CQPAUSED_Msk         (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
42769 #define MSPI0_INTCLR_CQUPD_Pos            (9UL)                     /*!< CQUPD (Bit 9)                                         */
42770 #define MSPI0_INTCLR_CQUPD_Msk            (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
42771 #define MSPI0_INTCLR_CQCMP_Pos            (8UL)                     /*!< CQCMP (Bit 8)                                         */
42772 #define MSPI0_INTCLR_CQCMP_Msk            (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
42773 #define MSPI0_INTCLR_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
42774 #define MSPI0_INTCLR_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42775 #define MSPI0_INTCLR_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
42776 #define MSPI0_INTCLR_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
42777 #define MSPI0_INTCLR_RXF_Pos              (5UL)                     /*!< RXF (Bit 5)                                           */
42778 #define MSPI0_INTCLR_RXF_Msk              (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
42779 #define MSPI0_INTCLR_RXO_Pos              (4UL)                     /*!< RXO (Bit 4)                                           */
42780 #define MSPI0_INTCLR_RXO_Msk              (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
42781 #define MSPI0_INTCLR_RXU_Pos              (3UL)                     /*!< RXU (Bit 3)                                           */
42782 #define MSPI0_INTCLR_RXU_Msk              (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
42783 #define MSPI0_INTCLR_TXO_Pos              (2UL)                     /*!< TXO (Bit 2)                                           */
42784 #define MSPI0_INTCLR_TXO_Msk              (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
42785 #define MSPI0_INTCLR_TXE_Pos              (1UL)                     /*!< TXE (Bit 1)                                           */
42786 #define MSPI0_INTCLR_TXE_Msk              (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
42787 #define MSPI0_INTCLR_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
42788 #define MSPI0_INTCLR_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
42789 /* ========================================================  INTSET  ========================================================= */
42790 #define MSPI0_INTSET_APBDMAERR_Pos        (13UL)                    /*!< APBDMAERR (Bit 13)                                    */
42791 #define MSPI0_INTSET_APBDMAERR_Msk        (0x2000UL)                /*!< APBDMAERR (Bitfield-Mask: 0x01)                       */
42792 #define MSPI0_INTSET_SCRERR_Pos           (12UL)                    /*!< SCRERR (Bit 12)                                       */
42793 #define MSPI0_INTSET_SCRERR_Msk           (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
42794 #define MSPI0_INTSET_CQERR_Pos            (11UL)                    /*!< CQERR (Bit 11)                                        */
42795 #define MSPI0_INTSET_CQERR_Msk            (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
42796 #define MSPI0_INTSET_CQPAUSED_Pos         (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
42797 #define MSPI0_INTSET_CQPAUSED_Msk         (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
42798 #define MSPI0_INTSET_CQUPD_Pos            (9UL)                     /*!< CQUPD (Bit 9)                                         */
42799 #define MSPI0_INTSET_CQUPD_Msk            (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
42800 #define MSPI0_INTSET_CQCMP_Pos            (8UL)                     /*!< CQCMP (Bit 8)                                         */
42801 #define MSPI0_INTSET_CQCMP_Msk            (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
42802 #define MSPI0_INTSET_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
42803 #define MSPI0_INTSET_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42804 #define MSPI0_INTSET_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
42805 #define MSPI0_INTSET_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
42806 #define MSPI0_INTSET_RXF_Pos              (5UL)                     /*!< RXF (Bit 5)                                           */
42807 #define MSPI0_INTSET_RXF_Msk              (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
42808 #define MSPI0_INTSET_RXO_Pos              (4UL)                     /*!< RXO (Bit 4)                                           */
42809 #define MSPI0_INTSET_RXO_Msk              (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
42810 #define MSPI0_INTSET_RXU_Pos              (3UL)                     /*!< RXU (Bit 3)                                           */
42811 #define MSPI0_INTSET_RXU_Msk              (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
42812 #define MSPI0_INTSET_TXO_Pos              (2UL)                     /*!< TXO (Bit 2)                                           */
42813 #define MSPI0_INTSET_TXO_Msk              (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
42814 #define MSPI0_INTSET_TXE_Pos              (1UL)                     /*!< TXE (Bit 1)                                           */
42815 #define MSPI0_INTSET_TXE_Msk              (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
42816 #define MSPI0_INTSET_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
42817 #define MSPI0_INTSET_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
42818 /* =========================================================  CQCFG  ========================================================= */
42819 #define MSPI0_CQCFG_CQPAUSEOP_Pos         (4UL)                     /*!< CQPAUSEOP (Bit 4)                                     */
42820 #define MSPI0_CQCFG_CQPAUSEOP_Msk         (0x10UL)                  /*!< CQPAUSEOP (Bitfield-Mask: 0x01)                       */
42821 #define MSPI0_CQCFG_CQAUTOCLEARMASK_Pos   (3UL)                     /*!< CQAUTOCLEARMASK (Bit 3)                               */
42822 #define MSPI0_CQCFG_CQAUTOCLEARMASK_Msk   (0x8UL)                   /*!< CQAUTOCLEARMASK (Bitfield-Mask: 0x01)                 */
42823 #define MSPI0_CQCFG_CQPWROFF_Pos          (2UL)                     /*!< CQPWROFF (Bit 2)                                      */
42824 #define MSPI0_CQCFG_CQPWROFF_Msk          (0x4UL)                   /*!< CQPWROFF (Bitfield-Mask: 0x01)                        */
42825 #define MSPI0_CQCFG_CQPRI_Pos             (1UL)                     /*!< CQPRI (Bit 1)                                         */
42826 #define MSPI0_CQCFG_CQPRI_Msk             (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
42827 #define MSPI0_CQCFG_CQEN_Pos              (0UL)                     /*!< CQEN (Bit 0)                                          */
42828 #define MSPI0_CQCFG_CQEN_Msk              (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
42829 /* ========================================================  CQADDR  ========================================================= */
42830 #define MSPI0_CQADDR_CQADDR_Pos           (0UL)                     /*!< CQADDR (Bit 0)                                        */
42831 #define MSPI0_CQADDR_CQADDR_Msk           (0x1fffffffUL)            /*!< CQADDR (Bitfield-Mask: 0x1fffffff)                    */
42832 /* ========================================================  CQSTAT  ========================================================= */
42833 #define MSPI0_CQSTAT_CQPAUSED_Pos         (3UL)                     /*!< CQPAUSED (Bit 3)                                      */
42834 #define MSPI0_CQSTAT_CQPAUSED_Msk         (0x8UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
42835 #define MSPI0_CQSTAT_CQERR_Pos            (2UL)                     /*!< CQERR (Bit 2)                                         */
42836 #define MSPI0_CQSTAT_CQERR_Msk            (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
42837 #define MSPI0_CQSTAT_CQCPL_Pos            (1UL)                     /*!< CQCPL (Bit 1)                                         */
42838 #define MSPI0_CQSTAT_CQCPL_Msk            (0x2UL)                   /*!< CQCPL (Bitfield-Mask: 0x01)                           */
42839 #define MSPI0_CQSTAT_CQTIP_Pos            (0UL)                     /*!< CQTIP (Bit 0)                                         */
42840 #define MSPI0_CQSTAT_CQTIP_Msk            (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
42841 /* ========================================================  CQFLAGS  ======================================================== */
42842 #define MSPI0_CQFLAGS_CQFLAGS_Pos         (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
42843 #define MSPI0_CQFLAGS_CQFLAGS_Msk         (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
42844 /* ======================================================  CQSETCLEAR  ======================================================= */
42845 #define MSPI0_CQSETCLEAR_CQFCLR_Pos       (16UL)                    /*!< CQFCLR (Bit 16)                                       */
42846 #define MSPI0_CQSETCLEAR_CQFCLR_Msk       (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
42847 #define MSPI0_CQSETCLEAR_CQFTOGGLE_Pos    (8UL)                     /*!< CQFTOGGLE (Bit 8)                                     */
42848 #define MSPI0_CQSETCLEAR_CQFTOGGLE_Msk    (0xff00UL)                /*!< CQFTOGGLE (Bitfield-Mask: 0xff)                       */
42849 #define MSPI0_CQSETCLEAR_CQFSET_Pos       (0UL)                     /*!< CQFSET (Bit 0)                                        */
42850 #define MSPI0_CQSETCLEAR_CQFSET_Msk       (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
42851 /* ========================================================  CQPAUSE  ======================================================== */
42852 #define MSPI0_CQPAUSE_CQMASK_Pos          (0UL)                     /*!< CQMASK (Bit 0)                                        */
42853 #define MSPI0_CQPAUSE_CQMASK_Msk          (0xffffUL)                /*!< CQMASK (Bitfield-Mask: 0xffff)                        */
42854 /* =======================================================  CQCURIDX  ======================================================== */
42855 #define MSPI0_CQCURIDX_CQCURIDX_Pos       (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
42856 #define MSPI0_CQCURIDX_CQCURIDX_Msk       (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
42857 /* =======================================================  CQENDIDX  ======================================================== */
42858 #define MSPI0_CQENDIDX_CQENDIDX_Pos       (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
42859 #define MSPI0_CQENDIDX_CQENDIDX_Msk       (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
42860 /* ======================================================  STATXIPDMA  ======================================================= */
42861 #define MSPI0_STATXIPDMA_FLD32_Pos        (0UL)                     /*!< FLD32 (Bit 0)                                         */
42862 #define MSPI0_STATXIPDMA_FLD32_Msk        (0xffffffffUL)            /*!< FLD32 (Bitfield-Mask: 0xffffffff)                     */
42863 
42864 
42865 /* =========================================================================================================================== */
42866 /* ================                                           PDM0                                            ================ */
42867 /* =========================================================================================================================== */
42868 
42869 /* =========================================================  CTRL  ========================================================== */
42870 #define PDM0_CTRL_EN_Pos                  (6UL)                     /*!< EN (Bit 6)                                            */
42871 #define PDM0_CTRL_EN_Msk                  (0x40UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
42872 #define PDM0_CTRL_PCMPACK_Pos             (5UL)                     /*!< PCMPACK (Bit 5)                                       */
42873 #define PDM0_CTRL_PCMPACK_Msk             (0x20UL)                  /*!< PCMPACK (Bitfield-Mask: 0x01)                         */
42874 #define PDM0_CTRL_RSTB_Pos                (4UL)                     /*!< RSTB (Bit 4)                                          */
42875 #define PDM0_CTRL_RSTB_Msk                (0x10UL)                  /*!< RSTB (Bitfield-Mask: 0x01)                            */
42876 #define PDM0_CTRL_CLKSEL_Pos              (1UL)                     /*!< CLKSEL (Bit 1)                                        */
42877 #define PDM0_CTRL_CLKSEL_Msk              (0x6UL)                   /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
42878 #define PDM0_CTRL_CLKEN_Pos               (0UL)                     /*!< CLKEN (Bit 0)                                         */
42879 #define PDM0_CTRL_CLKEN_Msk               (0x1UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
42880 /* =======================================================  CORECFG0  ======================================================== */
42881 #define PDM0_CORECFG0_PGAR_Pos            (26UL)                    /*!< PGAR (Bit 26)                                         */
42882 #define PDM0_CORECFG0_PGAR_Msk            (0x7c000000UL)            /*!< PGAR (Bitfield-Mask: 0x1f)                            */
42883 #define PDM0_CORECFG0_PGAL_Pos            (21UL)                    /*!< PGAL (Bit 21)                                         */
42884 #define PDM0_CORECFG0_PGAL_Msk            (0x3e00000UL)             /*!< PGAL (Bitfield-Mask: 0x1f)                            */
42885 #define PDM0_CORECFG0_SINCRATE_Pos        (14UL)                    /*!< SINCRATE (Bit 14)                                     */
42886 #define PDM0_CORECFG0_SINCRATE_Msk        (0x1fc000UL)              /*!< SINCRATE (Bitfield-Mask: 0x7f)                        */
42887 #define PDM0_CORECFG0_MCLKDIV_Pos         (10UL)                    /*!< MCLKDIV (Bit 10)                                      */
42888 #define PDM0_CORECFG0_MCLKDIV_Msk         (0x3c00UL)                /*!< MCLKDIV (Bitfield-Mask: 0x0f)                         */
42889 #define PDM0_CORECFG0_ADCHPD_Pos          (9UL)                     /*!< ADCHPD (Bit 9)                                        */
42890 #define PDM0_CORECFG0_ADCHPD_Msk          (0x200UL)                 /*!< ADCHPD (Bitfield-Mask: 0x01)                          */
42891 #define PDM0_CORECFG0_HPGAIN_Pos          (5UL)                     /*!< HPGAIN (Bit 5)                                        */
42892 #define PDM0_CORECFG0_HPGAIN_Msk          (0x1e0UL)                 /*!< HPGAIN (Bitfield-Mask: 0x0f)                          */
42893 #define PDM0_CORECFG0_SCYCLES_Pos         (2UL)                     /*!< SCYCLES (Bit 2)                                       */
42894 #define PDM0_CORECFG0_SCYCLES_Msk         (0x1cUL)                  /*!< SCYCLES (Bitfield-Mask: 0x07)                         */
42895 #define PDM0_CORECFG0_SOFTMUTE_Pos        (1UL)                     /*!< SOFTMUTE (Bit 1)                                      */
42896 #define PDM0_CORECFG0_SOFTMUTE_Msk        (0x2UL)                   /*!< SOFTMUTE (Bitfield-Mask: 0x01)                        */
42897 #define PDM0_CORECFG0_LRSWAP_Pos          (0UL)                     /*!< LRSWAP (Bit 0)                                        */
42898 #define PDM0_CORECFG0_LRSWAP_Msk          (0x1UL)                   /*!< LRSWAP (Bitfield-Mask: 0x01)                          */
42899 /* =======================================================  CORECFG1  ======================================================== */
42900 #define PDM0_CORECFG1_SELSTEP_Pos         (7UL)                     /*!< SELSTEP (Bit 7)                                       */
42901 #define PDM0_CORECFG1_SELSTEP_Msk         (0x80UL)                  /*!< SELSTEP (Bitfield-Mask: 0x01)                         */
42902 #define PDM0_CORECFG1_CKODLY_Pos          (4UL)                     /*!< CKODLY (Bit 4)                                        */
42903 #define PDM0_CORECFG1_CKODLY_Msk          (0x70UL)                  /*!< CKODLY (Bitfield-Mask: 0x07)                          */
42904 #define PDM0_CORECFG1_DIVMCLKQ_Pos        (2UL)                     /*!< DIVMCLKQ (Bit 2)                                      */
42905 #define PDM0_CORECFG1_DIVMCLKQ_Msk        (0xcUL)                   /*!< DIVMCLKQ (Bitfield-Mask: 0x03)                        */
42906 #define PDM0_CORECFG1_PCMCHSET_Pos        (0UL)                     /*!< PCMCHSET (Bit 0)                                      */
42907 #define PDM0_CORECFG1_PCMCHSET_Msk        (0x3UL)                   /*!< PCMCHSET (Bitfield-Mask: 0x03)                        */
42908 /* =======================================================  CORECTRL  ======================================================== */
42909 #define PDM0_CORECTRL_CORECTRL_Pos        (0UL)                     /*!< CORECTRL (Bit 0)                                      */
42910 #define PDM0_CORECTRL_CORECTRL_Msk        (0xffffffffUL)            /*!< CORECTRL (Bitfield-Mask: 0xffffffff)                  */
42911 /* ========================================================  FIFOCNT  ======================================================== */
42912 #define PDM0_FIFOCNT_FIFOCNT_Pos          (0UL)                     /*!< FIFOCNT (Bit 0)                                       */
42913 #define PDM0_FIFOCNT_FIFOCNT_Msk          (0x3fUL)                  /*!< FIFOCNT (Bitfield-Mask: 0x3f)                         */
42914 /* =======================================================  FIFOREAD  ======================================================== */
42915 #define PDM0_FIFOREAD_FIFOREAD_Pos        (0UL)                     /*!< FIFOREAD (Bit 0)                                      */
42916 #define PDM0_FIFOREAD_FIFOREAD_Msk        (0xffffffffUL)            /*!< FIFOREAD (Bitfield-Mask: 0xffffffff)                  */
42917 /* =======================================================  FIFOFLUSH  ======================================================= */
42918 #define PDM0_FIFOFLUSH_FIFOFLUSH_Pos      (0UL)                     /*!< FIFOFLUSH (Bit 0)                                     */
42919 #define PDM0_FIFOFLUSH_FIFOFLUSH_Msk      (0x1UL)                   /*!< FIFOFLUSH (Bitfield-Mask: 0x01)                       */
42920 /* ========================================================  FIFOTHR  ======================================================== */
42921 #define PDM0_FIFOTHR_FIFOTHR_Pos          (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
42922 #define PDM0_FIFOTHR_FIFOTHR_Msk          (0x1fUL)                  /*!< FIFOTHR (Bitfield-Mask: 0x1f)                         */
42923 /* =========================================================  INTEN  ========================================================= */
42924 #define PDM0_INTEN_DERR_Pos               (4UL)                     /*!< DERR (Bit 4)                                          */
42925 #define PDM0_INTEN_DERR_Msk               (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42926 #define PDM0_INTEN_DCMP_Pos               (3UL)                     /*!< DCMP (Bit 3)                                          */
42927 #define PDM0_INTEN_DCMP_Msk               (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
42928 #define PDM0_INTEN_UNDFL_Pos              (2UL)                     /*!< UNDFL (Bit 2)                                         */
42929 #define PDM0_INTEN_UNDFL_Msk              (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
42930 #define PDM0_INTEN_OVF_Pos                (1UL)                     /*!< OVF (Bit 1)                                           */
42931 #define PDM0_INTEN_OVF_Msk                (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
42932 #define PDM0_INTEN_THR_Pos                (0UL)                     /*!< THR (Bit 0)                                           */
42933 #define PDM0_INTEN_THR_Msk                (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
42934 /* ========================================================  INTSTAT  ======================================================== */
42935 #define PDM0_INTSTAT_DERR_Pos             (4UL)                     /*!< DERR (Bit 4)                                          */
42936 #define PDM0_INTSTAT_DERR_Msk             (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42937 #define PDM0_INTSTAT_DCMP_Pos             (3UL)                     /*!< DCMP (Bit 3)                                          */
42938 #define PDM0_INTSTAT_DCMP_Msk             (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
42939 #define PDM0_INTSTAT_UNDFL_Pos            (2UL)                     /*!< UNDFL (Bit 2)                                         */
42940 #define PDM0_INTSTAT_UNDFL_Msk            (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
42941 #define PDM0_INTSTAT_OVF_Pos              (1UL)                     /*!< OVF (Bit 1)                                           */
42942 #define PDM0_INTSTAT_OVF_Msk              (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
42943 #define PDM0_INTSTAT_THR_Pos              (0UL)                     /*!< THR (Bit 0)                                           */
42944 #define PDM0_INTSTAT_THR_Msk              (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
42945 /* ========================================================  INTCLR  ========================================================= */
42946 #define PDM0_INTCLR_DERR_Pos              (4UL)                     /*!< DERR (Bit 4)                                          */
42947 #define PDM0_INTCLR_DERR_Msk              (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42948 #define PDM0_INTCLR_DCMP_Pos              (3UL)                     /*!< DCMP (Bit 3)                                          */
42949 #define PDM0_INTCLR_DCMP_Msk              (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
42950 #define PDM0_INTCLR_UNDFL_Pos             (2UL)                     /*!< UNDFL (Bit 2)                                         */
42951 #define PDM0_INTCLR_UNDFL_Msk             (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
42952 #define PDM0_INTCLR_OVF_Pos               (1UL)                     /*!< OVF (Bit 1)                                           */
42953 #define PDM0_INTCLR_OVF_Msk               (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
42954 #define PDM0_INTCLR_THR_Pos               (0UL)                     /*!< THR (Bit 0)                                           */
42955 #define PDM0_INTCLR_THR_Msk               (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
42956 /* ========================================================  INTSET  ========================================================= */
42957 #define PDM0_INTSET_DERR_Pos              (4UL)                     /*!< DERR (Bit 4)                                          */
42958 #define PDM0_INTSET_DERR_Msk              (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
42959 #define PDM0_INTSET_DCMP_Pos              (3UL)                     /*!< DCMP (Bit 3)                                          */
42960 #define PDM0_INTSET_DCMP_Msk              (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
42961 #define PDM0_INTSET_UNDFL_Pos             (2UL)                     /*!< UNDFL (Bit 2)                                         */
42962 #define PDM0_INTSET_UNDFL_Msk             (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
42963 #define PDM0_INTSET_OVF_Pos               (1UL)                     /*!< OVF (Bit 1)                                           */
42964 #define PDM0_INTSET_OVF_Msk               (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
42965 #define PDM0_INTSET_THR_Pos               (0UL)                     /*!< THR (Bit 0)                                           */
42966 #define PDM0_INTSET_THR_Msk               (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
42967 /* =======================================================  DMATRIGEN  ======================================================= */
42968 #define PDM0_DMATRIGEN_DTHR90_Pos         (1UL)                     /*!< DTHR90 (Bit 1)                                        */
42969 #define PDM0_DMATRIGEN_DTHR90_Msk         (0x2UL)                   /*!< DTHR90 (Bitfield-Mask: 0x01)                          */
42970 #define PDM0_DMATRIGEN_DTHR_Pos           (0UL)                     /*!< DTHR (Bit 0)                                          */
42971 #define PDM0_DMATRIGEN_DTHR_Msk           (0x1UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
42972 /* ======================================================  DMATRIGSTAT  ====================================================== */
42973 #define PDM0_DMATRIGSTAT_DTHR90STAT_Pos   (1UL)                     /*!< DTHR90STAT (Bit 1)                                    */
42974 #define PDM0_DMATRIGSTAT_DTHR90STAT_Msk   (0x2UL)                   /*!< DTHR90STAT (Bitfield-Mask: 0x01)                      */
42975 #define PDM0_DMATRIGSTAT_DTHRSTAT_Pos     (0UL)                     /*!< DTHRSTAT (Bit 0)                                      */
42976 #define PDM0_DMATRIGSTAT_DTHRSTAT_Msk     (0x1UL)                   /*!< DTHRSTAT (Bitfield-Mask: 0x01)                        */
42977 /* ========================================================  DMACFG  ========================================================= */
42978 #define PDM0_DMACFG_DPWROFF_Pos           (10UL)                    /*!< DPWROFF (Bit 10)                                      */
42979 #define PDM0_DMACFG_DPWROFF_Msk           (0x400UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
42980 #define PDM0_DMACFG_DAUTOHIP_Pos          (9UL)                     /*!< DAUTOHIP (Bit 9)                                      */
42981 #define PDM0_DMACFG_DAUTOHIP_Msk          (0x200UL)                 /*!< DAUTOHIP (Bitfield-Mask: 0x01)                        */
42982 #define PDM0_DMACFG_DMAPRI_Pos            (8UL)                     /*!< DMAPRI (Bit 8)                                        */
42983 #define PDM0_DMACFG_DMAPRI_Msk            (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
42984 #define PDM0_DMACFG_DMADIR_Pos            (2UL)                     /*!< DMADIR (Bit 2)                                        */
42985 #define PDM0_DMACFG_DMADIR_Msk            (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
42986 #define PDM0_DMACFG_DMAEN_Pos             (0UL)                     /*!< DMAEN (Bit 0)                                         */
42987 #define PDM0_DMACFG_DMAEN_Msk             (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
42988 /* ======================================================  DMATARGADDR  ====================================================== */
42989 #define PDM0_DMATARGADDR_UTARGADDR_Pos    (28UL)                    /*!< UTARGADDR (Bit 28)                                    */
42990 #define PDM0_DMATARGADDR_UTARGADDR_Msk    (0xf0000000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x0f)                       */
42991 #define PDM0_DMATARGADDR_LTARGADDR_Pos    (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
42992 #define PDM0_DMATARGADDR_LTARGADDR_Msk    (0xfffffffUL)             /*!< LTARGADDR (Bitfield-Mask: 0xfffffff)                  */
42993 /* ========================================================  DMASTAT  ======================================================== */
42994 #define PDM0_DMASTAT_DMAERR_Pos           (2UL)                     /*!< DMAERR (Bit 2)                                        */
42995 #define PDM0_DMASTAT_DMAERR_Msk           (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
42996 #define PDM0_DMASTAT_DMACPL_Pos           (1UL)                     /*!< DMACPL (Bit 1)                                        */
42997 #define PDM0_DMASTAT_DMACPL_Msk           (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
42998 #define PDM0_DMASTAT_DMATIP_Pos           (0UL)                     /*!< DMATIP (Bit 0)                                        */
42999 #define PDM0_DMASTAT_DMATIP_Msk           (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
43000 /* ======================================================  DMATOTCOUNT  ====================================================== */
43001 #define PDM0_DMATOTCOUNT_TOTCOUNT_Pos     (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
43002 #define PDM0_DMATOTCOUNT_TOTCOUNT_Msk     (0xfffffUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xfffff)                     */
43003 
43004 
43005 /* =========================================================================================================================== */
43006 /* ================                                          PWRCTRL                                          ================ */
43007 /* =========================================================================================================================== */
43008 
43009 /* ======================================================  MCUPERFREQ  ======================================================= */
43010 #define PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Pos (3UL)                  /*!< MCUPERFSTATUS (Bit 3)                                 */
43011 #define PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Msk (0x18UL)               /*!< MCUPERFSTATUS (Bitfield-Mask: 0x03)                   */
43012 #define PWRCTRL_MCUPERFREQ_MCUPERFACK_Pos (2UL)                     /*!< MCUPERFACK (Bit 2)                                    */
43013 #define PWRCTRL_MCUPERFREQ_MCUPERFACK_Msk (0x4UL)                   /*!< MCUPERFACK (Bitfield-Mask: 0x01)                      */
43014 #define PWRCTRL_MCUPERFREQ_MCUPERFREQ_Pos (0UL)                     /*!< MCUPERFREQ (Bit 0)                                    */
43015 #define PWRCTRL_MCUPERFREQ_MCUPERFREQ_Msk (0x3UL)                   /*!< MCUPERFREQ (Bitfield-Mask: 0x03)                      */
43016 /* =======================================================  DEVPWREN  ======================================================== */
43017 #define PWRCTRL_DEVPWREN_PWRENI3C1_Pos    (26UL)                    /*!< PWRENI3C1 (Bit 26)                                    */
43018 #define PWRCTRL_DEVPWREN_PWRENI3C1_Msk    (0x4000000UL)             /*!< PWRENI3C1 (Bitfield-Mask: 0x01)                       */
43019 #define PWRCTRL_DEVPWREN_PWRENI3C0_Pos    (25UL)                    /*!< PWRENI3C0 (Bit 25)                                    */
43020 #define PWRCTRL_DEVPWREN_PWRENI3C0_Msk    (0x2000000UL)             /*!< PWRENI3C0 (Bitfield-Mask: 0x01)                       */
43021 #define PWRCTRL_DEVPWREN_PWRENDBG_Pos     (24UL)                    /*!< PWRENDBG (Bit 24)                                     */
43022 #define PWRCTRL_DEVPWREN_PWRENDBG_Msk     (0x1000000UL)             /*!< PWRENDBG (Bitfield-Mask: 0x01)                        */
43023 #define PWRCTRL_DEVPWREN_PWRENUSBPHY_Pos  (23UL)                    /*!< PWRENUSBPHY (Bit 23)                                  */
43024 #define PWRCTRL_DEVPWREN_PWRENUSBPHY_Msk  (0x800000UL)              /*!< PWRENUSBPHY (Bitfield-Mask: 0x01)                     */
43025 #define PWRCTRL_DEVPWREN_PWRENUSB_Pos     (22UL)                    /*!< PWRENUSB (Bit 22)                                     */
43026 #define PWRCTRL_DEVPWREN_PWRENUSB_Msk     (0x400000UL)              /*!< PWRENUSB (Bitfield-Mask: 0x01)                        */
43027 #define PWRCTRL_DEVPWREN_PWRENSDIO_Pos    (21UL)                    /*!< PWRENSDIO (Bit 21)                                    */
43028 #define PWRCTRL_DEVPWREN_PWRENSDIO_Msk    (0x200000UL)              /*!< PWRENSDIO (Bitfield-Mask: 0x01)                       */
43029 #define PWRCTRL_DEVPWREN_PWRENCRYPTO_Pos  (20UL)                    /*!< PWRENCRYPTO (Bit 20)                                  */
43030 #define PWRCTRL_DEVPWREN_PWRENCRYPTO_Msk  (0x100000UL)              /*!< PWRENCRYPTO (Bitfield-Mask: 0x01)                     */
43031 #define PWRCTRL_DEVPWREN_PWRENDISPPHY_Pos (19UL)                    /*!< PWRENDISPPHY (Bit 19)                                 */
43032 #define PWRCTRL_DEVPWREN_PWRENDISPPHY_Msk (0x80000UL)               /*!< PWRENDISPPHY (Bitfield-Mask: 0x01)                    */
43033 #define PWRCTRL_DEVPWREN_PWRENDISP_Pos    (18UL)                    /*!< PWRENDISP (Bit 18)                                    */
43034 #define PWRCTRL_DEVPWREN_PWRENDISP_Msk    (0x40000UL)               /*!< PWRENDISP (Bitfield-Mask: 0x01)                       */
43035 #define PWRCTRL_DEVPWREN_PWRENGFX_Pos     (17UL)                    /*!< PWRENGFX (Bit 17)                                     */
43036 #define PWRCTRL_DEVPWREN_PWRENGFX_Msk     (0x20000UL)               /*!< PWRENGFX (Bitfield-Mask: 0x01)                        */
43037 #define PWRCTRL_DEVPWREN_PWRENMSPI2_Pos   (16UL)                    /*!< PWRENMSPI2 (Bit 16)                                   */
43038 #define PWRCTRL_DEVPWREN_PWRENMSPI2_Msk   (0x10000UL)               /*!< PWRENMSPI2 (Bitfield-Mask: 0x01)                      */
43039 #define PWRCTRL_DEVPWREN_PWRENMSPI1_Pos   (15UL)                    /*!< PWRENMSPI1 (Bit 15)                                   */
43040 #define PWRCTRL_DEVPWREN_PWRENMSPI1_Msk   (0x8000UL)                /*!< PWRENMSPI1 (Bitfield-Mask: 0x01)                      */
43041 #define PWRCTRL_DEVPWREN_PWRENMSPI0_Pos   (14UL)                    /*!< PWRENMSPI0 (Bit 14)                                   */
43042 #define PWRCTRL_DEVPWREN_PWRENMSPI0_Msk   (0x4000UL)                /*!< PWRENMSPI0 (Bitfield-Mask: 0x01)                      */
43043 #define PWRCTRL_DEVPWREN_PWRENADC_Pos     (13UL)                    /*!< PWRENADC (Bit 13)                                     */
43044 #define PWRCTRL_DEVPWREN_PWRENADC_Msk     (0x2000UL)                /*!< PWRENADC (Bitfield-Mask: 0x01)                        */
43045 #define PWRCTRL_DEVPWREN_PWRENUART3_Pos   (12UL)                    /*!< PWRENUART3 (Bit 12)                                   */
43046 #define PWRCTRL_DEVPWREN_PWRENUART3_Msk   (0x1000UL)                /*!< PWRENUART3 (Bitfield-Mask: 0x01)                      */
43047 #define PWRCTRL_DEVPWREN_PWRENUART2_Pos   (11UL)                    /*!< PWRENUART2 (Bit 11)                                   */
43048 #define PWRCTRL_DEVPWREN_PWRENUART2_Msk   (0x800UL)                 /*!< PWRENUART2 (Bitfield-Mask: 0x01)                      */
43049 #define PWRCTRL_DEVPWREN_PWRENUART1_Pos   (10UL)                    /*!< PWRENUART1 (Bit 10)                                   */
43050 #define PWRCTRL_DEVPWREN_PWRENUART1_Msk   (0x400UL)                 /*!< PWRENUART1 (Bitfield-Mask: 0x01)                      */
43051 #define PWRCTRL_DEVPWREN_PWRENUART0_Pos   (9UL)                     /*!< PWRENUART0 (Bit 9)                                    */
43052 #define PWRCTRL_DEVPWREN_PWRENUART0_Msk   (0x200UL)                 /*!< PWRENUART0 (Bitfield-Mask: 0x01)                      */
43053 #define PWRCTRL_DEVPWREN_PWRENIOM7_Pos    (8UL)                     /*!< PWRENIOM7 (Bit 8)                                     */
43054 #define PWRCTRL_DEVPWREN_PWRENIOM7_Msk    (0x100UL)                 /*!< PWRENIOM7 (Bitfield-Mask: 0x01)                       */
43055 #define PWRCTRL_DEVPWREN_PWRENIOM6_Pos    (7UL)                     /*!< PWRENIOM6 (Bit 7)                                     */
43056 #define PWRCTRL_DEVPWREN_PWRENIOM6_Msk    (0x80UL)                  /*!< PWRENIOM6 (Bitfield-Mask: 0x01)                       */
43057 #define PWRCTRL_DEVPWREN_PWRENIOM5_Pos    (6UL)                     /*!< PWRENIOM5 (Bit 6)                                     */
43058 #define PWRCTRL_DEVPWREN_PWRENIOM5_Msk    (0x40UL)                  /*!< PWRENIOM5 (Bitfield-Mask: 0x01)                       */
43059 #define PWRCTRL_DEVPWREN_PWRENIOM4_Pos    (5UL)                     /*!< PWRENIOM4 (Bit 5)                                     */
43060 #define PWRCTRL_DEVPWREN_PWRENIOM4_Msk    (0x20UL)                  /*!< PWRENIOM4 (Bitfield-Mask: 0x01)                       */
43061 #define PWRCTRL_DEVPWREN_PWRENIOM3_Pos    (4UL)                     /*!< PWRENIOM3 (Bit 4)                                     */
43062 #define PWRCTRL_DEVPWREN_PWRENIOM3_Msk    (0x10UL)                  /*!< PWRENIOM3 (Bitfield-Mask: 0x01)                       */
43063 #define PWRCTRL_DEVPWREN_PWRENIOM2_Pos    (3UL)                     /*!< PWRENIOM2 (Bit 3)                                     */
43064 #define PWRCTRL_DEVPWREN_PWRENIOM2_Msk    (0x8UL)                   /*!< PWRENIOM2 (Bitfield-Mask: 0x01)                       */
43065 #define PWRCTRL_DEVPWREN_PWRENIOM1_Pos    (2UL)                     /*!< PWRENIOM1 (Bit 2)                                     */
43066 #define PWRCTRL_DEVPWREN_PWRENIOM1_Msk    (0x4UL)                   /*!< PWRENIOM1 (Bitfield-Mask: 0x01)                       */
43067 #define PWRCTRL_DEVPWREN_PWRENIOM0_Pos    (1UL)                     /*!< PWRENIOM0 (Bit 1)                                     */
43068 #define PWRCTRL_DEVPWREN_PWRENIOM0_Msk    (0x2UL)                   /*!< PWRENIOM0 (Bitfield-Mask: 0x01)                       */
43069 #define PWRCTRL_DEVPWREN_PWRENIOS_Pos     (0UL)                     /*!< PWRENIOS (Bit 0)                                      */
43070 #define PWRCTRL_DEVPWREN_PWRENIOS_Msk     (0x1UL)                   /*!< PWRENIOS (Bitfield-Mask: 0x01)                        */
43071 /* =====================================================  DEVPWRSTATUS  ====================================================== */
43072 #define PWRCTRL_DEVPWRSTATUS_PWRSTI3C1_Pos (26UL)                   /*!< PWRSTI3C1 (Bit 26)                                    */
43073 #define PWRCTRL_DEVPWRSTATUS_PWRSTI3C1_Msk (0x4000000UL)            /*!< PWRSTI3C1 (Bitfield-Mask: 0x01)                       */
43074 #define PWRCTRL_DEVPWRSTATUS_PWRSTI3C0_Pos (25UL)                   /*!< PWRSTI3C0 (Bit 25)                                    */
43075 #define PWRCTRL_DEVPWRSTATUS_PWRSTI3C0_Msk (0x2000000UL)            /*!< PWRSTI3C0 (Bitfield-Mask: 0x01)                       */
43076 #define PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Pos (24UL)                    /*!< PWRSTDBG (Bit 24)                                     */
43077 #define PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Msk (0x1000000UL)             /*!< PWRSTDBG (Bitfield-Mask: 0x01)                        */
43078 #define PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_Pos (23UL)                 /*!< PWRSTUSBPHY (Bit 23)                                  */
43079 #define PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_Msk (0x800000UL)           /*!< PWRSTUSBPHY (Bitfield-Mask: 0x01)                     */
43080 #define PWRCTRL_DEVPWRSTATUS_PWRSTUSB_Pos (22UL)                    /*!< PWRSTUSB (Bit 22)                                     */
43081 #define PWRCTRL_DEVPWRSTATUS_PWRSTUSB_Msk (0x400000UL)              /*!< PWRSTUSB (Bitfield-Mask: 0x01)                        */
43082 #define PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Pos (21UL)                   /*!< PWRSTSDIO (Bit 21)                                    */
43083 #define PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Msk (0x200000UL)             /*!< PWRSTSDIO (Bitfield-Mask: 0x01)                       */
43084 #define PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Pos (20UL)                 /*!< PWRSTCRYPTO (Bit 20)                                  */
43085 #define PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Msk (0x100000UL)           /*!< PWRSTCRYPTO (Bitfield-Mask: 0x01)                     */
43086 #define PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_Pos (19UL)                /*!< PWRSTDISPPHY (Bit 19)                                 */
43087 #define PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_Msk (0x80000UL)           /*!< PWRSTDISPPHY (Bitfield-Mask: 0x01)                    */
43088 #define PWRCTRL_DEVPWRSTATUS_PWRSTDISP_Pos (18UL)                   /*!< PWRSTDISP (Bit 18)                                    */
43089 #define PWRCTRL_DEVPWRSTATUS_PWRSTDISP_Msk (0x40000UL)              /*!< PWRSTDISP (Bitfield-Mask: 0x01)                       */
43090 #define PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Pos (17UL)                    /*!< PWRSTGFX (Bit 17)                                     */
43091 #define PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Msk (0x20000UL)               /*!< PWRSTGFX (Bitfield-Mask: 0x01)                        */
43092 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Pos (16UL)                  /*!< PWRSTMSPI2 (Bit 16)                                   */
43093 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Msk (0x10000UL)             /*!< PWRSTMSPI2 (Bitfield-Mask: 0x01)                      */
43094 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Pos (15UL)                  /*!< PWRSTMSPI1 (Bit 15)                                   */
43095 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Msk (0x8000UL)              /*!< PWRSTMSPI1 (Bitfield-Mask: 0x01)                      */
43096 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Pos (14UL)                  /*!< PWRSTMSPI0 (Bit 14)                                   */
43097 #define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Msk (0x4000UL)              /*!< PWRSTMSPI0 (Bitfield-Mask: 0x01)                      */
43098 #define PWRCTRL_DEVPWRSTATUS_PWRSTADC_Pos (13UL)                    /*!< PWRSTADC (Bit 13)                                     */
43099 #define PWRCTRL_DEVPWRSTATUS_PWRSTADC_Msk (0x2000UL)                /*!< PWRSTADC (Bitfield-Mask: 0x01)                        */
43100 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Pos (12UL)                  /*!< PWRSTUART3 (Bit 12)                                   */
43101 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Msk (0x1000UL)              /*!< PWRSTUART3 (Bitfield-Mask: 0x01)                      */
43102 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Pos (11UL)                  /*!< PWRSTUART2 (Bit 11)                                   */
43103 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Msk (0x800UL)               /*!< PWRSTUART2 (Bitfield-Mask: 0x01)                      */
43104 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Pos (10UL)                  /*!< PWRSTUART1 (Bit 10)                                   */
43105 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Msk (0x400UL)               /*!< PWRSTUART1 (Bitfield-Mask: 0x01)                      */
43106 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Pos (9UL)                   /*!< PWRSTUART0 (Bit 9)                                    */
43107 #define PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Msk (0x200UL)               /*!< PWRSTUART0 (Bitfield-Mask: 0x01)                      */
43108 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Pos (8UL)                    /*!< PWRSTIOM7 (Bit 8)                                     */
43109 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Msk (0x100UL)                /*!< PWRSTIOM7 (Bitfield-Mask: 0x01)                       */
43110 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Pos (7UL)                    /*!< PWRSTIOM6 (Bit 7)                                     */
43111 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Msk (0x80UL)                 /*!< PWRSTIOM6 (Bitfield-Mask: 0x01)                       */
43112 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Pos (6UL)                    /*!< PWRSTIOM5 (Bit 6)                                     */
43113 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Msk (0x40UL)                 /*!< PWRSTIOM5 (Bitfield-Mask: 0x01)                       */
43114 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Pos (5UL)                    /*!< PWRSTIOM4 (Bit 5)                                     */
43115 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Msk (0x20UL)                 /*!< PWRSTIOM4 (Bitfield-Mask: 0x01)                       */
43116 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Pos (4UL)                    /*!< PWRSTIOM3 (Bit 4)                                     */
43117 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Msk (0x10UL)                 /*!< PWRSTIOM3 (Bitfield-Mask: 0x01)                       */
43118 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Pos (3UL)                    /*!< PWRSTIOM2 (Bit 3)                                     */
43119 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Msk (0x8UL)                  /*!< PWRSTIOM2 (Bitfield-Mask: 0x01)                       */
43120 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Pos (2UL)                    /*!< PWRSTIOM1 (Bit 2)                                     */
43121 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Msk (0x4UL)                  /*!< PWRSTIOM1 (Bitfield-Mask: 0x01)                       */
43122 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Pos (1UL)                    /*!< PWRSTIOM0 (Bit 1)                                     */
43123 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Msk (0x2UL)                  /*!< PWRSTIOM0 (Bitfield-Mask: 0x01)                       */
43124 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Pos (0UL)                     /*!< PWRSTIOS (Bit 0)                                      */
43125 #define PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Msk (0x1UL)                   /*!< PWRSTIOS (Bitfield-Mask: 0x01)                        */
43126 /* ======================================================  AUDSSPWREN  ======================================================= */
43127 #define PWRCTRL_AUDSSPWREN_PWRENDSPA_Pos  (11UL)                    /*!< PWRENDSPA (Bit 11)                                    */
43128 #define PWRCTRL_AUDSSPWREN_PWRENDSPA_Msk  (0x800UL)                 /*!< PWRENDSPA (Bitfield-Mask: 0x01)                       */
43129 #define PWRCTRL_AUDSSPWREN_PWRENAUDADC_Pos (10UL)                   /*!< PWRENAUDADC (Bit 10)                                  */
43130 #define PWRCTRL_AUDSSPWREN_PWRENAUDADC_Msk (0x400UL)                /*!< PWRENAUDADC (Bitfield-Mask: 0x01)                     */
43131 #define PWRCTRL_AUDSSPWREN_PWRENI2S1_Pos  (7UL)                     /*!< PWRENI2S1 (Bit 7)                                     */
43132 #define PWRCTRL_AUDSSPWREN_PWRENI2S1_Msk  (0x80UL)                  /*!< PWRENI2S1 (Bitfield-Mask: 0x01)                       */
43133 #define PWRCTRL_AUDSSPWREN_PWRENI2S0_Pos  (6UL)                     /*!< PWRENI2S0 (Bit 6)                                     */
43134 #define PWRCTRL_AUDSSPWREN_PWRENI2S0_Msk  (0x40UL)                  /*!< PWRENI2S0 (Bitfield-Mask: 0x01)                       */
43135 #define PWRCTRL_AUDSSPWREN_PWRENPDM3_Pos  (5UL)                     /*!< PWRENPDM3 (Bit 5)                                     */
43136 #define PWRCTRL_AUDSSPWREN_PWRENPDM3_Msk  (0x20UL)                  /*!< PWRENPDM3 (Bitfield-Mask: 0x01)                       */
43137 #define PWRCTRL_AUDSSPWREN_PWRENPDM2_Pos  (4UL)                     /*!< PWRENPDM2 (Bit 4)                                     */
43138 #define PWRCTRL_AUDSSPWREN_PWRENPDM2_Msk  (0x10UL)                  /*!< PWRENPDM2 (Bitfield-Mask: 0x01)                       */
43139 #define PWRCTRL_AUDSSPWREN_PWRENPDM1_Pos  (3UL)                     /*!< PWRENPDM1 (Bit 3)                                     */
43140 #define PWRCTRL_AUDSSPWREN_PWRENPDM1_Msk  (0x8UL)                   /*!< PWRENPDM1 (Bitfield-Mask: 0x01)                       */
43141 #define PWRCTRL_AUDSSPWREN_PWRENPDM0_Pos  (2UL)                     /*!< PWRENPDM0 (Bit 2)                                     */
43142 #define PWRCTRL_AUDSSPWREN_PWRENPDM0_Msk  (0x4UL)                   /*!< PWRENPDM0 (Bitfield-Mask: 0x01)                       */
43143 #define PWRCTRL_AUDSSPWREN_PWRENAUDPB_Pos (1UL)                     /*!< PWRENAUDPB (Bit 1)                                    */
43144 #define PWRCTRL_AUDSSPWREN_PWRENAUDPB_Msk (0x2UL)                   /*!< PWRENAUDPB (Bitfield-Mask: 0x01)                      */
43145 #define PWRCTRL_AUDSSPWREN_PWRENAUDREC_Pos (0UL)                    /*!< PWRENAUDREC (Bit 0)                                   */
43146 #define PWRCTRL_AUDSSPWREN_PWRENAUDREC_Msk (0x1UL)                  /*!< PWRENAUDREC (Bitfield-Mask: 0x01)                     */
43147 /* ====================================================  AUDSSPWRSTATUS  ===================================================== */
43148 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_Pos (11UL)                 /*!< PWRSTDSPA (Bit 11)                                    */
43149 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_Msk (0x800UL)              /*!< PWRSTDSPA (Bitfield-Mask: 0x01)                       */
43150 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_Pos (10UL)               /*!< PWRSTAUDADC (Bit 10)                                  */
43151 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_Msk (0x400UL)            /*!< PWRSTAUDADC (Bitfield-Mask: 0x01)                     */
43152 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Pos (7UL)                  /*!< PWRSTI2S1 (Bit 7)                                     */
43153 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Msk (0x80UL)               /*!< PWRSTI2S1 (Bitfield-Mask: 0x01)                       */
43154 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Pos (6UL)                  /*!< PWRSTI2S0 (Bit 6)                                     */
43155 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Msk (0x40UL)               /*!< PWRSTI2S0 (Bitfield-Mask: 0x01)                       */
43156 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_Pos (5UL)                  /*!< PWRSTPDM3 (Bit 5)                                     */
43157 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_Msk (0x20UL)               /*!< PWRSTPDM3 (Bitfield-Mask: 0x01)                       */
43158 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_Pos (4UL)                  /*!< PWRSTPDM2 (Bit 4)                                     */
43159 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_Msk (0x10UL)               /*!< PWRSTPDM2 (Bitfield-Mask: 0x01)                       */
43160 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_Pos (3UL)                  /*!< PWRSTPDM1 (Bit 3)                                     */
43161 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_Msk (0x8UL)                /*!< PWRSTPDM1 (Bitfield-Mask: 0x01)                       */
43162 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Pos (2UL)                  /*!< PWRSTPDM0 (Bit 2)                                     */
43163 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Msk (0x4UL)                /*!< PWRSTPDM0 (Bitfield-Mask: 0x01)                       */
43164 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Pos (1UL)                 /*!< PWRSTAUDPB (Bit 1)                                    */
43165 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Msk (0x2UL)               /*!< PWRSTAUDPB (Bitfield-Mask: 0x01)                      */
43166 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Pos (0UL)                /*!< PWRSTAUDREC (Bit 0)                                   */
43167 #define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Msk (0x1UL)              /*!< PWRSTAUDREC (Bitfield-Mask: 0x01)                     */
43168 /* =======================================================  MEMPWREN  ======================================================== */
43169 #define PWRCTRL_MEMPWREN_PWRENCACHEB2_Pos (5UL)                     /*!< PWRENCACHEB2 (Bit 5)                                  */
43170 #define PWRCTRL_MEMPWREN_PWRENCACHEB2_Msk (0x20UL)                  /*!< PWRENCACHEB2 (Bitfield-Mask: 0x01)                    */
43171 #define PWRCTRL_MEMPWREN_PWRENCACHEB0_Pos (4UL)                     /*!< PWRENCACHEB0 (Bit 4)                                  */
43172 #define PWRCTRL_MEMPWREN_PWRENCACHEB0_Msk (0x10UL)                  /*!< PWRENCACHEB0 (Bitfield-Mask: 0x01)                    */
43173 #define PWRCTRL_MEMPWREN_PWRENNVM0_Pos    (3UL)                     /*!< PWRENNVM0 (Bit 3)                                     */
43174 #define PWRCTRL_MEMPWREN_PWRENNVM0_Msk    (0x8UL)                   /*!< PWRENNVM0 (Bitfield-Mask: 0x01)                       */
43175 #define PWRCTRL_MEMPWREN_PWRENDTCM_Pos    (0UL)                     /*!< PWRENDTCM (Bit 0)                                     */
43176 #define PWRCTRL_MEMPWREN_PWRENDTCM_Msk    (0x7UL)                   /*!< PWRENDTCM (Bitfield-Mask: 0x07)                       */
43177 /* =====================================================  MEMPWRSTATUS  ====================================================== */
43178 #define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB2_Pos (5UL)                 /*!< PWRSTCACHEB2 (Bit 5)                                  */
43179 #define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB2_Msk (0x20UL)              /*!< PWRSTCACHEB2 (Bitfield-Mask: 0x01)                    */
43180 #define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB0_Pos (4UL)                 /*!< PWRSTCACHEB0 (Bit 4)                                  */
43181 #define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB0_Msk (0x10UL)              /*!< PWRSTCACHEB0 (Bitfield-Mask: 0x01)                    */
43182 #define PWRCTRL_MEMPWRSTATUS_PWRSTNVM0_Pos (3UL)                    /*!< PWRSTNVM0 (Bit 3)                                     */
43183 #define PWRCTRL_MEMPWRSTATUS_PWRSTNVM0_Msk (0x8UL)                  /*!< PWRSTNVM0 (Bitfield-Mask: 0x01)                       */
43184 #define PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Pos (0UL)                    /*!< PWRSTDTCM (Bit 0)                                     */
43185 #define PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Msk (0x7UL)                  /*!< PWRSTDTCM (Bitfield-Mask: 0x07)                       */
43186 /* =======================================================  MEMRETCFG  ======================================================= */
43187 #define PWRCTRL_MEMRETCFG_CACHEPWDSLP_Pos (4UL)                     /*!< CACHEPWDSLP (Bit 4)                                   */
43188 #define PWRCTRL_MEMRETCFG_CACHEPWDSLP_Msk (0x10UL)                  /*!< CACHEPWDSLP (Bitfield-Mask: 0x01)                     */
43189 #define PWRCTRL_MEMRETCFG_NVM0PWDSLP_Pos  (3UL)                     /*!< NVM0PWDSLP (Bit 3)                                    */
43190 #define PWRCTRL_MEMRETCFG_NVM0PWDSLP_Msk  (0x8UL)                   /*!< NVM0PWDSLP (Bitfield-Mask: 0x01)                      */
43191 #define PWRCTRL_MEMRETCFG_DTCMPWDSLP_Pos  (0UL)                     /*!< DTCMPWDSLP (Bit 0)                                    */
43192 #define PWRCTRL_MEMRETCFG_DTCMPWDSLP_Msk  (0x7UL)                   /*!< DTCMPWDSLP (Bitfield-Mask: 0x07)                      */
43193 /* =====================================================  SYSPWRSTATUS  ====================================================== */
43194 #define PWRCTRL_SYSPWRSTATUS_SYSDEEPSLEEP_Pos (31UL)                /*!< SYSDEEPSLEEP (Bit 31)                                 */
43195 #define PWRCTRL_SYSPWRSTATUS_SYSDEEPSLEEP_Msk (0x80000000UL)        /*!< SYSDEEPSLEEP (Bitfield-Mask: 0x01)                    */
43196 #define PWRCTRL_SYSPWRSTATUS_COREDEEPSLEEP_Pos (30UL)               /*!< COREDEEPSLEEP (Bit 30)                                */
43197 #define PWRCTRL_SYSPWRSTATUS_COREDEEPSLEEP_Msk (0x40000000UL)       /*!< COREDEEPSLEEP (Bitfield-Mask: 0x01)                   */
43198 #define PWRCTRL_SYSPWRSTATUS_CORESLEEP_Pos (29UL)                   /*!< CORESLEEP (Bit 29)                                    */
43199 #define PWRCTRL_SYSPWRSTATUS_CORESLEEP_Msk (0x20000000UL)           /*!< CORESLEEP (Bitfield-Mask: 0x01)                       */
43200 #define PWRCTRL_SYSPWRSTATUS_PWRSTDSP1H_Pos (3UL)                   /*!< PWRSTDSP1H (Bit 3)                                    */
43201 #define PWRCTRL_SYSPWRSTATUS_PWRSTDSP1H_Msk (0x8UL)                 /*!< PWRSTDSP1H (Bitfield-Mask: 0x01)                      */
43202 #define PWRCTRL_SYSPWRSTATUS_PWRSTDSP0H_Pos (2UL)                   /*!< PWRSTDSP0H (Bit 2)                                    */
43203 #define PWRCTRL_SYSPWRSTATUS_PWRSTDSP0H_Msk (0x4UL)                 /*!< PWRSTDSP0H (Bitfield-Mask: 0x01)                      */
43204 #define PWRCTRL_SYSPWRSTATUS_PWRSTMCUH_Pos (1UL)                    /*!< PWRSTMCUH (Bit 1)                                     */
43205 #define PWRCTRL_SYSPWRSTATUS_PWRSTMCUH_Msk (0x2UL)                  /*!< PWRSTMCUH (Bitfield-Mask: 0x01)                       */
43206 #define PWRCTRL_SYSPWRSTATUS_PWRSTMCUL_Pos (0UL)                    /*!< PWRSTMCUL (Bit 0)                                     */
43207 #define PWRCTRL_SYSPWRSTATUS_PWRSTMCUL_Msk (0x1UL)                  /*!< PWRSTMCUL (Bitfield-Mask: 0x01)                       */
43208 /* ======================================================  SSRAMPWREN  ======================================================= */
43209 #define PWRCTRL_SSRAMPWREN_PWRENSSRAM_Pos (0UL)                     /*!< PWRENSSRAM (Bit 0)                                    */
43210 #define PWRCTRL_SSRAMPWREN_PWRENSSRAM_Msk (0x3UL)                   /*!< PWRENSSRAM (Bitfield-Mask: 0x03)                      */
43211 /* ======================================================  SSRAMPWRST  ======================================================= */
43212 #define PWRCTRL_SSRAMPWRST_SSRAMPWRST_Pos (0UL)                     /*!< SSRAMPWRST (Bit 0)                                    */
43213 #define PWRCTRL_SSRAMPWRST_SSRAMPWRST_Msk (0x3UL)                   /*!< SSRAMPWRST (Bitfield-Mask: 0x03)                      */
43214 /* ======================================================  SSRAMRETCFG  ====================================================== */
43215 #define PWRCTRL_SSRAMRETCFG_SSRAMACTDISP_Pos (8UL)                  /*!< SSRAMACTDISP (Bit 8)                                  */
43216 #define PWRCTRL_SSRAMRETCFG_SSRAMACTDISP_Msk (0x300UL)              /*!< SSRAMACTDISP (Bitfield-Mask: 0x03)                    */
43217 #define PWRCTRL_SSRAMRETCFG_SSRAMACTGFX_Pos (6UL)                   /*!< SSRAMACTGFX (Bit 6)                                   */
43218 #define PWRCTRL_SSRAMRETCFG_SSRAMACTGFX_Msk (0xc0UL)                /*!< SSRAMACTGFX (Bitfield-Mask: 0x03)                     */
43219 #define PWRCTRL_SSRAMRETCFG_SSRAMACTDSP_Pos (4UL)                   /*!< SSRAMACTDSP (Bit 4)                                   */
43220 #define PWRCTRL_SSRAMRETCFG_SSRAMACTDSP_Msk (0x30UL)                /*!< SSRAMACTDSP (Bitfield-Mask: 0x03)                     */
43221 #define PWRCTRL_SSRAMRETCFG_SSRAMACTMCU_Pos (2UL)                   /*!< SSRAMACTMCU (Bit 2)                                   */
43222 #define PWRCTRL_SSRAMRETCFG_SSRAMACTMCU_Msk (0xcUL)                 /*!< SSRAMACTMCU (Bitfield-Mask: 0x03)                     */
43223 #define PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Pos (0UL)                   /*!< SSRAMPWDSLP (Bit 0)                                   */
43224 #define PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Msk (0x3UL)                 /*!< SSRAMPWDSLP (Bitfield-Mask: 0x03)                     */
43225 /* =====================================================  DEVPWREVENTEN  ===================================================== */
43226 #define PWRCTRL_DEVPWREVENTEN_AUDEVEN_Pos (7UL)                     /*!< AUDEVEN (Bit 7)                                       */
43227 #define PWRCTRL_DEVPWREVENTEN_AUDEVEN_Msk (0x80UL)                  /*!< AUDEVEN (Bitfield-Mask: 0x01)                         */
43228 #define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Pos (6UL)                    /*!< MSPIEVEN (Bit 6)                                      */
43229 #define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Msk (0x40UL)                 /*!< MSPIEVEN (Bitfield-Mask: 0x01)                        */
43230 #define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Pos (5UL)                     /*!< ADCEVEN (Bit 5)                                       */
43231 #define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Msk (0x20UL)                  /*!< ADCEVEN (Bitfield-Mask: 0x01)                         */
43232 #define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Pos (4UL)                    /*!< HCPCEVEN (Bit 4)                                      */
43233 #define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Msk (0x10UL)                 /*!< HCPCEVEN (Bitfield-Mask: 0x01)                        */
43234 #define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Pos (3UL)                    /*!< HCPBEVEN (Bit 3)                                      */
43235 #define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Msk (0x8UL)                  /*!< HCPBEVEN (Bitfield-Mask: 0x01)                        */
43236 #define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Pos (2UL)                    /*!< HCPAEVEN (Bit 2)                                      */
43237 #define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Msk (0x4UL)                  /*!< HCPAEVEN (Bitfield-Mask: 0x01)                        */
43238 #define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Pos (1UL)                    /*!< MCUHEVEN (Bit 1)                                      */
43239 #define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Msk (0x2UL)                  /*!< MCUHEVEN (Bitfield-Mask: 0x01)                        */
43240 #define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Pos (0UL)                    /*!< MCULEVEN (Bit 0)                                      */
43241 #define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Msk (0x1UL)                  /*!< MCULEVEN (Bitfield-Mask: 0x01)                        */
43242 /* =====================================================  MEMPWREVENTEN  ===================================================== */
43243 #define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Pos (5UL)                   /*!< CACHEB2EN (Bit 5)                                     */
43244 #define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Msk (0x20UL)                /*!< CACHEB2EN (Bitfield-Mask: 0x01)                       */
43245 #define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Pos (4UL)                   /*!< CACHEB0EN (Bit 4)                                     */
43246 #define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Msk (0x10UL)                /*!< CACHEB0EN (Bitfield-Mask: 0x01)                       */
43247 #define PWRCTRL_MEMPWREVENTEN_NVM0EN_Pos  (3UL)                     /*!< NVM0EN (Bit 3)                                        */
43248 #define PWRCTRL_MEMPWREVENTEN_NVM0EN_Msk  (0x8UL)                   /*!< NVM0EN (Bitfield-Mask: 0x01)                          */
43249 #define PWRCTRL_MEMPWREVENTEN_DTCMEN_Pos  (0UL)                     /*!< DTCMEN (Bit 0)                                        */
43250 #define PWRCTRL_MEMPWREVENTEN_DTCMEN_Msk  (0x7UL)                   /*!< DTCMEN (Bitfield-Mask: 0x07)                          */
43251 /* ======================================================  MMSOVERRIDE  ====================================================== */
43252 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Pos (10UL)            /*!< MMSOVRSSRAMRETGFX (Bit 10)                            */
43253 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Msk (0xc00UL)         /*!< MMSOVRSSRAMRETGFX (Bitfield-Mask: 0x03)               */
43254 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Pos (8UL)            /*!< MMSOVRSSRAMRETDISP (Bit 8)                            */
43255 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Msk (0x300UL)        /*!< MMSOVRSSRAMRETDISP (Bitfield-Mask: 0x03)              */
43256 #define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Pos (6UL)            /*!< MMSOVRDSPRAMRETGFX (Bit 6)                            */
43257 #define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Msk (0xc0UL)         /*!< MMSOVRDSPRAMRETGFX (Bitfield-Mask: 0x03)              */
43258 #define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Pos (4UL)           /*!< MMSOVRDSPRAMRETDISP (Bit 4)                           */
43259 #define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Msk (0x30UL)        /*!< MMSOVRDSPRAMRETDISP (Bitfield-Mask: 0x03)             */
43260 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Pos (3UL)                /*!< MMSOVRSSRAMGFX (Bit 3)                                */
43261 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Msk (0x8UL)              /*!< MMSOVRSSRAMGFX (Bitfield-Mask: 0x01)                  */
43262 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Pos (2UL)               /*!< MMSOVRSSRAMDISP (Bit 2)                               */
43263 #define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Msk (0x4UL)             /*!< MMSOVRSSRAMDISP (Bitfield-Mask: 0x01)                 */
43264 #define PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Pos (1UL)                 /*!< MMSOVRMCULGFX (Bit 1)                                 */
43265 #define PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Msk (0x2UL)               /*!< MMSOVRMCULGFX (Bitfield-Mask: 0x01)                   */
43266 #define PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Pos (0UL)                /*!< MMSOVRMCULDISP (Bit 0)                                */
43267 #define PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Msk (0x1UL)              /*!< MMSOVRMCULDISP (Bitfield-Mask: 0x01)                  */
43268 /* ======================================================  DSP0PWRCTRL  ====================================================== */
43269 #define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Pos (4UL)                  /*!< DSP0PCMRSTOR (Bit 4)                                  */
43270 #define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Msk (0x10UL)               /*!< DSP0PCMRSTOR (Bitfield-Mask: 0x01)                    */
43271 #define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTDLY_Pos (0UL)                 /*!< DSP0PCMRSTDLY (Bit 0)                                 */
43272 #define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTDLY_Msk (0xfUL)               /*!< DSP0PCMRSTDLY (Bitfield-Mask: 0x0f)                   */
43273 /* ======================================================  DSP0PERFREQ  ====================================================== */
43274 #define PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Pos (3UL)                /*!< DSP0PERFSTATUS (Bit 3)                                */
43275 #define PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Msk (0x18UL)             /*!< DSP0PERFSTATUS (Bitfield-Mask: 0x03)                  */
43276 #define PWRCTRL_DSP0PERFREQ_DSP0PERFACK_Pos (2UL)                   /*!< DSP0PERFACK (Bit 2)                                   */
43277 #define PWRCTRL_DSP0PERFREQ_DSP0PERFACK_Msk (0x4UL)                 /*!< DSP0PERFACK (Bitfield-Mask: 0x01)                     */
43278 #define PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Pos (0UL)                   /*!< DSP0PERFREQ (Bit 0)                                   */
43279 #define PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Msk (0x3UL)                 /*!< DSP0PERFREQ (Bitfield-Mask: 0x03)                     */
43280 /* =====================================================  DSP0MEMPWREN  ====================================================== */
43281 #define PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Pos (1UL)              /*!< PWRENDSP0ICACHE (Bit 1)                               */
43282 #define PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Msk (0x2UL)            /*!< PWRENDSP0ICACHE (Bitfield-Mask: 0x01)                 */
43283 #define PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Pos (0UL)                 /*!< PWRENDSP0RAM (Bit 0)                                  */
43284 #define PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Msk (0x1UL)               /*!< PWRENDSP0RAM (Bitfield-Mask: 0x01)                    */
43285 /* =====================================================  DSP0MEMPWRST  ====================================================== */
43286 #define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0ICACHE_Pos (1UL)              /*!< PWRSTDSP0ICACHE (Bit 1)                               */
43287 #define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0ICACHE_Msk (0x2UL)            /*!< PWRSTDSP0ICACHE (Bitfield-Mask: 0x01)                 */
43288 #define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0RAM_Pos (0UL)                 /*!< PWRSTDSP0RAM (Bit 0)                                  */
43289 #define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0RAM_Msk (0x1UL)               /*!< PWRSTDSP0RAM (Bitfield-Mask: 0x01)                    */
43290 /* =====================================================  DSP0MEMRETCFG  ===================================================== */
43291 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Pos (4UL)               /*!< DSP0RAMACTGFX (Bit 4)                                 */
43292 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Msk (0x10UL)            /*!< DSP0RAMACTGFX (Bitfield-Mask: 0x01)                   */
43293 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Pos (3UL)              /*!< DSP0RAMACTDISP (Bit 3)                                */
43294 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Msk (0x8UL)            /*!< DSP0RAMACTDISP (Bitfield-Mask: 0x01)                  */
43295 #define PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Pos (2UL)            /*!< ICACHEPWDDSP0OFF (Bit 2)                              */
43296 #define PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Msk (0x4UL)          /*!< ICACHEPWDDSP0OFF (Bitfield-Mask: 0x01)                */
43297 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Pos (1UL)               /*!< DSP0RAMACTMCU (Bit 1)                                 */
43298 #define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Msk (0x2UL)             /*!< DSP0RAMACTMCU (Bitfield-Mask: 0x01)                   */
43299 #define PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Pos (0UL)               /*!< RAMPWDDSP0OFF (Bit 0)                                 */
43300 #define PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Msk (0x1UL)             /*!< RAMPWDDSP0OFF (Bitfield-Mask: 0x01)                   */
43301 /* ======================================================  DSP1PWRCTRL  ====================================================== */
43302 #define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Pos (4UL)                  /*!< DSP1PCMRSTOR (Bit 4)                                  */
43303 #define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Msk (0x10UL)               /*!< DSP1PCMRSTOR (Bitfield-Mask: 0x01)                    */
43304 #define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTDLY_Pos (0UL)                 /*!< DSP1PCMRSTDLY (Bit 0)                                 */
43305 #define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTDLY_Msk (0xfUL)               /*!< DSP1PCMRSTDLY (Bitfield-Mask: 0x0f)                   */
43306 /* ======================================================  DSP1PERFREQ  ====================================================== */
43307 #define PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Pos (3UL)                /*!< DSP1PERFSTATUS (Bit 3)                                */
43308 #define PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Msk (0x18UL)             /*!< DSP1PERFSTATUS (Bitfield-Mask: 0x03)                  */
43309 #define PWRCTRL_DSP1PERFREQ_DSP1PERFACK_Pos (2UL)                   /*!< DSP1PERFACK (Bit 2)                                   */
43310 #define PWRCTRL_DSP1PERFREQ_DSP1PERFACK_Msk (0x4UL)                 /*!< DSP1PERFACK (Bitfield-Mask: 0x01)                     */
43311 #define PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Pos (0UL)                   /*!< DSP1PERFREQ (Bit 0)                                   */
43312 #define PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Msk (0x3UL)                 /*!< DSP1PERFREQ (Bitfield-Mask: 0x03)                     */
43313 /* =====================================================  DSP1MEMPWREN  ====================================================== */
43314 #define PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Pos (1UL)              /*!< PWRENDSP1ICACHE (Bit 1)                               */
43315 #define PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Msk (0x2UL)            /*!< PWRENDSP1ICACHE (Bitfield-Mask: 0x01)                 */
43316 #define PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Pos (0UL)                 /*!< PWRENDSP1RAM (Bit 0)                                  */
43317 #define PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Msk (0x1UL)               /*!< PWRENDSP1RAM (Bitfield-Mask: 0x01)                    */
43318 /* =====================================================  DSP1MEMPWRST  ====================================================== */
43319 #define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1ICACHE_Pos (1UL)              /*!< PWRSTDSP1ICACHE (Bit 1)                               */
43320 #define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1ICACHE_Msk (0x2UL)            /*!< PWRSTDSP1ICACHE (Bitfield-Mask: 0x01)                 */
43321 #define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1RAM_Pos (0UL)                 /*!< PWRSTDSP1RAM (Bit 0)                                  */
43322 #define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1RAM_Msk (0x1UL)               /*!< PWRSTDSP1RAM (Bitfield-Mask: 0x01)                    */
43323 /* =====================================================  DSP1MEMRETCFG  ===================================================== */
43324 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Pos (4UL)               /*!< DSP1RAMACTGFX (Bit 4)                                 */
43325 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Msk (0x10UL)            /*!< DSP1RAMACTGFX (Bitfield-Mask: 0x01)                   */
43326 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Pos (3UL)              /*!< DSP1RAMACTDISP (Bit 3)                                */
43327 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Msk (0x8UL)            /*!< DSP1RAMACTDISP (Bitfield-Mask: 0x01)                  */
43328 #define PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Pos (2UL)            /*!< ICACHEPWDDSP1OFF (Bit 2)                              */
43329 #define PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Msk (0x4UL)          /*!< ICACHEPWDDSP1OFF (Bitfield-Mask: 0x01)                */
43330 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Pos (1UL)               /*!< DSP1RAMACTMCU (Bit 1)                                 */
43331 #define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Msk (0x2UL)             /*!< DSP1RAMACTMCU (Bitfield-Mask: 0x01)                   */
43332 #define PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Pos (0UL)               /*!< RAMPWDDSP1OFF (Bit 0)                                 */
43333 #define PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Msk (0x1UL)             /*!< RAMPWDDSP1OFF (Bitfield-Mask: 0x01)                   */
43334 /* =======================================================  PWRACKOVR  ======================================================= */
43335 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_Pos (17UL)             /*!< PWRACKOVERRIDEDSPA (Bit 17)                           */
43336 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_Msk (0x20000UL)        /*!< PWRACKOVERRIDEDSPA (Bitfield-Mask: 0x01)              */
43337 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_Pos (16UL)           /*!< PWRACKOVERRIDEUSBPHY (Bit 16)                         */
43338 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_Msk (0x10000UL)      /*!< PWRACKOVERRIDEUSBPHY (Bitfield-Mask: 0x01)            */
43339 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_Pos (15UL)              /*!< PWRACKOVERRIDEUSB (Bit 15)                            */
43340 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_Msk (0x8000UL)          /*!< PWRACKOVERRIDEUSB (Bitfield-Mask: 0x01)               */
43341 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_Pos (14UL)             /*!< PWRACKOVERRIDESDIO (Bit 14)                           */
43342 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_Msk (0x4000UL)         /*!< PWRACKOVERRIDESDIO (Bitfield-Mask: 0x01)              */
43343 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_Pos (13UL)             /*!< PWRACKOVERRIDEMSPI (Bit 13)                           */
43344 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_Msk (0x2000UL)         /*!< PWRACKOVERRIDEMSPI (Bitfield-Mask: 0x01)              */
43345 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_Pos (12UL)             /*!< PWRACKOVERRIDEMCUL (Bit 12)                           */
43346 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_Msk (0x1000UL)         /*!< PWRACKOVERRIDEMCUL (Bitfield-Mask: 0x01)              */
43347 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_Pos (11UL)              /*!< PWRACKOVERRIDEIOS (Bit 11)                            */
43348 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_Msk (0x800UL)           /*!< PWRACKOVERRIDEIOS (Bitfield-Mask: 0x01)               */
43349 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_Pos (10UL)             /*!< PWRACKOVERRIDEHCPC (Bit 10)                           */
43350 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_Msk (0x400UL)          /*!< PWRACKOVERRIDEHCPC (Bitfield-Mask: 0x01)              */
43351 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_Pos (9UL)              /*!< PWRACKOVERRIDEHCPB (Bit 9)                            */
43352 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_Msk (0x200UL)          /*!< PWRACKOVERRIDEHCPB (Bitfield-Mask: 0x01)              */
43353 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_Pos (8UL)              /*!< PWRACKOVERRIDEHCPA (Bit 8)                            */
43354 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_Msk (0x100UL)          /*!< PWRACKOVERRIDEHCPA (Bitfield-Mask: 0x01)              */
43355 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_Pos (7UL)               /*!< PWRACKOVERRIDEGFX (Bit 7)                             */
43356 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_Msk (0x80UL)            /*!< PWRACKOVERRIDEGFX (Bitfield-Mask: 0x01)               */
43357 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_Pos (6UL)           /*!< PWRACKOVERRIDEDISPPHY (Bit 6)                         */
43358 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_Msk (0x40UL)        /*!< PWRACKOVERRIDEDISPPHY (Bitfield-Mask: 0x01)           */
43359 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_Pos (5UL)              /*!< PWRACKOVERRIDEDISP (Bit 5)                            */
43360 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_Msk (0x20UL)           /*!< PWRACKOVERRIDEDISP (Bitfield-Mask: 0x01)              */
43361 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_Pos (4UL)               /*!< PWRACKOVERRIDEDBG (Bit 4)                             */
43362 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_Msk (0x10UL)            /*!< PWRACKOVERRIDEDBG (Bitfield-Mask: 0x01)               */
43363 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_Pos (3UL)            /*!< PWRACKOVERRIDECRYPTO (Bit 3)                          */
43364 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_Msk (0x8UL)          /*!< PWRACKOVERRIDECRYPTO (Bitfield-Mask: 0x01)            */
43365 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_Pos (2UL)            /*!< PWRACKOVERRIDEAUDADC (Bit 2)                          */
43366 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_Msk (0x4UL)          /*!< PWRACKOVERRIDEAUDADC (Bitfield-Mask: 0x01)            */
43367 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_Pos (1UL)               /*!< PWRACKOVERRIDEAUD (Bit 1)                             */
43368 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_Msk (0x2UL)             /*!< PWRACKOVERRIDEAUD (Bitfield-Mask: 0x01)               */
43369 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_Pos (0UL)               /*!< PWRACKOVERRIDEADC (Bit 0)                             */
43370 #define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_Msk (0x1UL)             /*!< PWRACKOVERRIDEADC (Bitfield-Mask: 0x01)               */
43371 /* =====================================================  PWRCNTDEFVAL  ====================================================== */
43372 #define PWRCTRL_PWRCNTDEFVAL_PWRACKWAITDELSIMOSTMC_Pos (6UL)        /*!< PWRACKWAITDELSIMOSTMC (Bit 6)                         */
43373 #define PWRCTRL_PWRCNTDEFVAL_PWRACKWAITDELSIMOSTMC_Msk (0xffc0UL)   /*!< PWRACKWAITDELSIMOSTMC (Bitfield-Mask: 0x3ff)          */
43374 #define PWRCTRL_PWRCNTDEFVAL_PWRDEFVALDEVSTMC_Pos (0UL)             /*!< PWRDEFVALDEVSTMC (Bit 0)                              */
43375 #define PWRCTRL_PWRCNTDEFVAL_PWRDEFVALDEVSTMC_Msk (0x3fUL)          /*!< PWRDEFVALDEVSTMC (Bitfield-Mask: 0x3f)                */
43376 /* ========================================================  VRCTRL  ========================================================= */
43377 #define PWRCTRL_VRCTRL_SIMOBUCKEN_Pos     (0UL)                     /*!< SIMOBUCKEN (Bit 0)                                    */
43378 #define PWRCTRL_VRCTRL_SIMOBUCKEN_Msk     (0x1UL)                   /*!< SIMOBUCKEN (Bitfield-Mask: 0x01)                      */
43379 /* =====================================================  LEGACYVRLPOVR  ===================================================== */
43380 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDBG_Pos (18UL)                  /*!< IGNOREDBG (Bit 18)                                    */
43381 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDBG_Msk (0x40000UL)             /*!< IGNOREDBG (Bitfield-Mask: 0x01)                       */
43382 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSP1H_Pos (17UL)                /*!< IGNOREDSP1H (Bit 17)                                  */
43383 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSP1H_Msk (0x20000UL)           /*!< IGNOREDSP1H (Bitfield-Mask: 0x01)                     */
43384 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSP0H_Pos (16UL)                /*!< IGNOREDSP0H (Bit 16)                                  */
43385 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSP0H_Msk (0x10000UL)           /*!< IGNOREDSP0H (Bitfield-Mask: 0x01)                     */
43386 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSPA_Pos (15UL)                 /*!< IGNOREDSPA (Bit 15)                                   */
43387 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDSPA_Msk (0x8000UL)             /*!< IGNOREDSPA (Bitfield-Mask: 0x01)                      */
43388 #define PWRCTRL_LEGACYVRLPOVR_IGNOREAUD_Pos (14UL)                  /*!< IGNOREAUD (Bit 14)                                    */
43389 #define PWRCTRL_LEGACYVRLPOVR_IGNOREAUD_Msk (0x4000UL)              /*!< IGNOREAUD (Bitfield-Mask: 0x01)                       */
43390 #define PWRCTRL_LEGACYVRLPOVR_IGNOREUSBPHY_Pos (13UL)               /*!< IGNOREUSBPHY (Bit 13)                                 */
43391 #define PWRCTRL_LEGACYVRLPOVR_IGNOREUSBPHY_Msk (0x2000UL)           /*!< IGNOREUSBPHY (Bitfield-Mask: 0x01)                    */
43392 #define PWRCTRL_LEGACYVRLPOVR_IGNOREUSB_Pos (12UL)                  /*!< IGNOREUSB (Bit 12)                                    */
43393 #define PWRCTRL_LEGACYVRLPOVR_IGNOREUSB_Msk (0x1000UL)              /*!< IGNOREUSB (Bitfield-Mask: 0x01)                       */
43394 #define PWRCTRL_LEGACYVRLPOVR_IGNORESDIO_Pos (11UL)                 /*!< IGNORESDIO (Bit 11)                                   */
43395 #define PWRCTRL_LEGACYVRLPOVR_IGNORESDIO_Msk (0x800UL)              /*!< IGNORESDIO (Bitfield-Mask: 0x01)                      */
43396 #define PWRCTRL_LEGACYVRLPOVR_IGNORECRYPTO_Pos (10UL)               /*!< IGNORECRYPTO (Bit 10)                                 */
43397 #define PWRCTRL_LEGACYVRLPOVR_IGNORECRYPTO_Msk (0x400UL)            /*!< IGNORECRYPTO (Bitfield-Mask: 0x01)                    */
43398 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDISPPHY_Pos (9UL)               /*!< IGNOREDISPPHY (Bit 9)                                 */
43399 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDISPPHY_Msk (0x200UL)           /*!< IGNOREDISPPHY (Bitfield-Mask: 0x01)                   */
43400 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDISP_Pos (8UL)                  /*!< IGNOREDISP (Bit 8)                                    */
43401 #define PWRCTRL_LEGACYVRLPOVR_IGNOREDISP_Msk (0x100UL)              /*!< IGNOREDISP (Bitfield-Mask: 0x01)                      */
43402 #define PWRCTRL_LEGACYVRLPOVR_IGNOREGFX_Pos (7UL)                   /*!< IGNOREGFX (Bit 7)                                     */
43403 #define PWRCTRL_LEGACYVRLPOVR_IGNOREGFX_Msk (0x80UL)                /*!< IGNOREGFX (Bitfield-Mask: 0x01)                       */
43404 #define PWRCTRL_LEGACYVRLPOVR_IGNOREMSPI_Pos (6UL)                  /*!< IGNOREMSPI (Bit 6)                                    */
43405 #define PWRCTRL_LEGACYVRLPOVR_IGNOREMSPI_Msk (0x40UL)               /*!< IGNOREMSPI (Bitfield-Mask: 0x01)                      */
43406 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPE_Pos (5UL)                  /*!< IGNOREHCPE (Bit 5)                                    */
43407 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPE_Msk (0x20UL)               /*!< IGNOREHCPE (Bitfield-Mask: 0x01)                      */
43408 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPD_Pos (4UL)                  /*!< IGNOREHCPD (Bit 4)                                    */
43409 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPD_Msk (0x10UL)               /*!< IGNOREHCPD (Bitfield-Mask: 0x01)                      */
43410 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPC_Pos (3UL)                  /*!< IGNOREHCPC (Bit 3)                                    */
43411 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPC_Msk (0x8UL)                /*!< IGNOREHCPC (Bitfield-Mask: 0x01)                      */
43412 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPB_Pos (2UL)                  /*!< IGNOREHCPB (Bit 2)                                    */
43413 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPB_Msk (0x4UL)                /*!< IGNOREHCPB (Bitfield-Mask: 0x01)                      */
43414 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPA_Pos (1UL)                  /*!< IGNOREHCPA (Bit 1)                                    */
43415 #define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPA_Msk (0x2UL)                /*!< IGNOREHCPA (Bitfield-Mask: 0x01)                      */
43416 #define PWRCTRL_LEGACYVRLPOVR_IGNOREIOS_Pos (0UL)                   /*!< IGNOREIOS (Bit 0)                                     */
43417 #define PWRCTRL_LEGACYVRLPOVR_IGNOREIOS_Msk (0x1UL)                 /*!< IGNOREIOS (Bitfield-Mask: 0x01)                       */
43418 /* =======================================================  VRSTATUS  ======================================================== */
43419 #define PWRCTRL_VRSTATUS_SIMOBUCKST_Pos   (4UL)                     /*!< SIMOBUCKST (Bit 4)                                    */
43420 #define PWRCTRL_VRSTATUS_SIMOBUCKST_Msk   (0x30UL)                  /*!< SIMOBUCKST (Bitfield-Mask: 0x03)                      */
43421 #define PWRCTRL_VRSTATUS_MEMLDOST_Pos     (2UL)                     /*!< MEMLDOST (Bit 2)                                      */
43422 #define PWRCTRL_VRSTATUS_MEMLDOST_Msk     (0xcUL)                   /*!< MEMLDOST (Bitfield-Mask: 0x03)                        */
43423 #define PWRCTRL_VRSTATUS_CORELDOST_Pos    (0UL)                     /*!< CORELDOST (Bit 0)                                     */
43424 #define PWRCTRL_VRSTATUS_CORELDOST_Msk    (0x3UL)                   /*!< CORELDOST (Bitfield-Mask: 0x03)                       */
43425 /* =====================================================  PWRWEIGHTULP0  ===================================================== */
43426 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART3_Pos (28UL)                 /*!< WTULPUART3 (Bit 28)                                   */
43427 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART3_Msk (0xf0000000UL)         /*!< WTULPUART3 (Bitfield-Mask: 0x0f)                      */
43428 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART2_Pos (24UL)                 /*!< WTULPUART2 (Bit 24)                                   */
43429 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART2_Msk (0xf000000UL)          /*!< WTULPUART2 (Bitfield-Mask: 0x0f)                      */
43430 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART1_Pos (20UL)                 /*!< WTULPUART1 (Bit 20)                                   */
43431 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART1_Msk (0xf00000UL)           /*!< WTULPUART1 (Bitfield-Mask: 0x0f)                      */
43432 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART0_Pos (16UL)                 /*!< WTULPUART0 (Bit 16)                                   */
43433 #define PWRCTRL_PWRWEIGHTULP0_WTULPUART0_Msk (0xf0000UL)            /*!< WTULPUART0 (Bitfield-Mask: 0x0f)                      */
43434 #define PWRCTRL_PWRWEIGHTULP0_WTULPIOS_Pos (12UL)                   /*!< WTULPIOS (Bit 12)                                     */
43435 #define PWRCTRL_PWRWEIGHTULP0_WTULPIOS_Msk (0xf000UL)               /*!< WTULPIOS (Bitfield-Mask: 0x0f)                        */
43436 #define PWRCTRL_PWRWEIGHTULP0_WTULPDSP1_Pos (8UL)                   /*!< WTULPDSP1 (Bit 8)                                     */
43437 #define PWRCTRL_PWRWEIGHTULP0_WTULPDSP1_Msk (0xf00UL)               /*!< WTULPDSP1 (Bitfield-Mask: 0x0f)                       */
43438 #define PWRCTRL_PWRWEIGHTULP0_WTULPDSP0_Pos (4UL)                   /*!< WTULPDSP0 (Bit 4)                                     */
43439 #define PWRCTRL_PWRWEIGHTULP0_WTULPDSP0_Msk (0xf0UL)                /*!< WTULPDSP0 (Bitfield-Mask: 0x0f)                       */
43440 #define PWRCTRL_PWRWEIGHTULP0_WTULPMCU_Pos (0UL)                    /*!< WTULPMCU (Bit 0)                                      */
43441 #define PWRCTRL_PWRWEIGHTULP0_WTULPMCU_Msk (0xfUL)                  /*!< WTULPMCU (Bitfield-Mask: 0x0f)                        */
43442 /* =====================================================  PWRWEIGHTULP1  ===================================================== */
43443 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM7_Pos (28UL)                  /*!< WTULPIOM7 (Bit 28)                                    */
43444 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM7_Msk (0xf0000000UL)          /*!< WTULPIOM7 (Bitfield-Mask: 0x0f)                       */
43445 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM6_Pos (24UL)                  /*!< WTULPIOM6 (Bit 24)                                    */
43446 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM6_Msk (0xf000000UL)           /*!< WTULPIOM6 (Bitfield-Mask: 0x0f)                       */
43447 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM5_Pos (20UL)                  /*!< WTULPIOM5 (Bit 20)                                    */
43448 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM5_Msk (0xf00000UL)            /*!< WTULPIOM5 (Bitfield-Mask: 0x0f)                       */
43449 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM4_Pos (16UL)                  /*!< WTULPIOM4 (Bit 16)                                    */
43450 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM4_Msk (0xf0000UL)             /*!< WTULPIOM4 (Bitfield-Mask: 0x0f)                       */
43451 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM3_Pos (12UL)                  /*!< WTULPIOM3 (Bit 12)                                    */
43452 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM3_Msk (0xf000UL)              /*!< WTULPIOM3 (Bitfield-Mask: 0x0f)                       */
43453 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM2_Pos (8UL)                   /*!< WTULPIOM2 (Bit 8)                                     */
43454 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM2_Msk (0xf00UL)               /*!< WTULPIOM2 (Bitfield-Mask: 0x0f)                       */
43455 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM1_Pos (4UL)                   /*!< WTULPIOM1 (Bit 4)                                     */
43456 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM1_Msk (0xf0UL)                /*!< WTULPIOM1 (Bitfield-Mask: 0x0f)                       */
43457 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM0_Pos (0UL)                   /*!< WTULPIOM0 (Bit 0)                                     */
43458 #define PWRCTRL_PWRWEIGHTULP1_WTULPIOM0_Msk (0xfUL)                 /*!< WTULPIOM0 (Bitfield-Mask: 0x0f)                       */
43459 /* =====================================================  PWRWEIGHTULP2  ===================================================== */
43460 #define PWRCTRL_PWRWEIGHTULP2_WTULPUSB_Pos (28UL)                   /*!< WTULPUSB (Bit 28)                                     */
43461 #define PWRCTRL_PWRWEIGHTULP2_WTULPUSB_Msk (0xf0000000UL)           /*!< WTULPUSB (Bitfield-Mask: 0x0f)                        */
43462 #define PWRCTRL_PWRWEIGHTULP2_WTULPSDIO_Pos (24UL)                  /*!< WTULPSDIO (Bit 24)                                    */
43463 #define PWRCTRL_PWRWEIGHTULP2_WTULPSDIO_Msk (0xf000000UL)           /*!< WTULPSDIO (Bitfield-Mask: 0x0f)                       */
43464 #define PWRCTRL_PWRWEIGHTULP2_WTULPCRYPTO_Pos (20UL)                /*!< WTULPCRYPTO (Bit 20)                                  */
43465 #define PWRCTRL_PWRWEIGHTULP2_WTULPCRYPTO_Msk (0xf00000UL)          /*!< WTULPCRYPTO (Bitfield-Mask: 0x0f)                     */
43466 #define PWRCTRL_PWRWEIGHTULP2_WTULPDISP_Pos (16UL)                  /*!< WTULPDISP (Bit 16)                                    */
43467 #define PWRCTRL_PWRWEIGHTULP2_WTULPDISP_Msk (0xf0000UL)             /*!< WTULPDISP (Bitfield-Mask: 0x0f)                       */
43468 #define PWRCTRL_PWRWEIGHTULP2_WTULPGFX_Pos (12UL)                   /*!< WTULPGFX (Bit 12)                                     */
43469 #define PWRCTRL_PWRWEIGHTULP2_WTULPGFX_Msk (0xf000UL)               /*!< WTULPGFX (Bitfield-Mask: 0x0f)                        */
43470 #define PWRCTRL_PWRWEIGHTULP2_WTULPMSPI1_Pos (8UL)                  /*!< WTULPMSPI1 (Bit 8)                                    */
43471 #define PWRCTRL_PWRWEIGHTULP2_WTULPMSPI1_Msk (0xf00UL)              /*!< WTULPMSPI1 (Bitfield-Mask: 0x0f)                      */
43472 #define PWRCTRL_PWRWEIGHTULP2_WTULPMSPI0_Pos (4UL)                  /*!< WTULPMSPI0 (Bit 4)                                    */
43473 #define PWRCTRL_PWRWEIGHTULP2_WTULPMSPI0_Msk (0xf0UL)               /*!< WTULPMSPI0 (Bitfield-Mask: 0x0f)                      */
43474 #define PWRCTRL_PWRWEIGHTULP2_WTULPADC_Pos (0UL)                    /*!< WTULPADC (Bit 0)                                      */
43475 #define PWRCTRL_PWRWEIGHTULP2_WTULPADC_Msk (0xfUL)                  /*!< WTULPADC (Bitfield-Mask: 0x0f)                        */
43476 /* =====================================================  PWRWEIGHTULP3  ===================================================== */
43477 #define PWRCTRL_PWRWEIGHTULP3_WTULPMSPI2_Pos (28UL)                 /*!< WTULPMSPI2 (Bit 28)                                   */
43478 #define PWRCTRL_PWRWEIGHTULP3_WTULPMSPI2_Msk (0xf0000000UL)         /*!< WTULPMSPI2 (Bitfield-Mask: 0x0f)                      */
43479 #define PWRCTRL_PWRWEIGHTULP3_WTULPI3C1_Pos (24UL)                  /*!< WTULPI3C1 (Bit 24)                                    */
43480 #define PWRCTRL_PWRWEIGHTULP3_WTULPI3C1_Msk (0xf000000UL)           /*!< WTULPI3C1 (Bitfield-Mask: 0x0f)                       */
43481 #define PWRCTRL_PWRWEIGHTULP3_WTULPI3C0_Pos (20UL)                  /*!< WTULPI3C0 (Bit 20)                                    */
43482 #define PWRCTRL_PWRWEIGHTULP3_WTULPI3C0_Msk (0xf00000UL)            /*!< WTULPI3C0 (Bitfield-Mask: 0x0f)                       */
43483 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDADC_Pos (16UL)                /*!< WTULPAUDADC (Bit 16)                                  */
43484 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDADC_Msk (0xf0000UL)           /*!< WTULPAUDADC (Bitfield-Mask: 0x0f)                     */
43485 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDPB_Pos (12UL)                 /*!< WTULPAUDPB (Bit 12)                                   */
43486 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDPB_Msk (0xf000UL)             /*!< WTULPAUDPB (Bitfield-Mask: 0x0f)                      */
43487 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDREC_Pos (8UL)                 /*!< WTULPAUDREC (Bit 8)                                   */
43488 #define PWRCTRL_PWRWEIGHTULP3_WTULPAUDREC_Msk (0xf00UL)             /*!< WTULPAUDREC (Bitfield-Mask: 0x0f)                     */
43489 #define PWRCTRL_PWRWEIGHTULP3_WTULPDBG_Pos (4UL)                    /*!< WTULPDBG (Bit 4)                                      */
43490 #define PWRCTRL_PWRWEIGHTULP3_WTULPDBG_Msk (0xf0UL)                 /*!< WTULPDBG (Bitfield-Mask: 0x0f)                        */
43491 #define PWRCTRL_PWRWEIGHTULP3_WTULPDSPA_Pos (0UL)                   /*!< WTULPDSPA (Bit 0)                                     */
43492 #define PWRCTRL_PWRWEIGHTULP3_WTULPDSPA_Msk (0xfUL)                 /*!< WTULPDSPA (Bitfield-Mask: 0x0f)                       */
43493 /* =====================================================  PWRWEIGHTULP4  ===================================================== */
43494 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM3_Pos (28UL)                  /*!< WTULPPDM3 (Bit 28)                                    */
43495 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM3_Msk (0xf0000000UL)          /*!< WTULPPDM3 (Bitfield-Mask: 0x0f)                       */
43496 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM2_Pos (24UL)                  /*!< WTULPPDM2 (Bit 24)                                    */
43497 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM2_Msk (0xf000000UL)           /*!< WTULPPDM2 (Bitfield-Mask: 0x0f)                       */
43498 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM1_Pos (20UL)                  /*!< WTULPPDM1 (Bit 20)                                    */
43499 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM1_Msk (0xf00000UL)            /*!< WTULPPDM1 (Bitfield-Mask: 0x0f)                       */
43500 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM0_Pos (16UL)                  /*!< WTULPPDM0 (Bit 16)                                    */
43501 #define PWRCTRL_PWRWEIGHTULP4_WTULPPDM0_Msk (0xf0000UL)             /*!< WTULPPDM0 (Bitfield-Mask: 0x0f)                       */
43502 #define PWRCTRL_PWRWEIGHTULP4_WTULPI2S1_Pos (4UL)                   /*!< WTULPI2S1 (Bit 4)                                     */
43503 #define PWRCTRL_PWRWEIGHTULP4_WTULPI2S1_Msk (0xf0UL)                /*!< WTULPI2S1 (Bitfield-Mask: 0x0f)                       */
43504 #define PWRCTRL_PWRWEIGHTULP4_WTULPI2S0_Pos (0UL)                   /*!< WTULPI2S0 (Bit 0)                                     */
43505 #define PWRCTRL_PWRWEIGHTULP4_WTULPI2S0_Msk (0xfUL)                 /*!< WTULPI2S0 (Bitfield-Mask: 0x0f)                       */
43506 /* =====================================================  PWRWEIGHTULP5  ===================================================== */
43507 #define PWRCTRL_PWRWEIGHTULP5_WTULPUSBPHY_Pos (4UL)                 /*!< WTULPUSBPHY (Bit 4)                                   */
43508 #define PWRCTRL_PWRWEIGHTULP5_WTULPUSBPHY_Msk (0xf0UL)              /*!< WTULPUSBPHY (Bitfield-Mask: 0x0f)                     */
43509 #define PWRCTRL_PWRWEIGHTULP5_WTULPDISPPHY_Pos (0UL)                /*!< WTULPDISPPHY (Bit 0)                                  */
43510 #define PWRCTRL_PWRWEIGHTULP5_WTULPDISPPHY_Msk (0xfUL)              /*!< WTULPDISPPHY (Bitfield-Mask: 0x0f)                    */
43511 /* =====================================================  PWRWEIGHTLP0  ====================================================== */
43512 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART3_Pos (28UL)                   /*!< WTLPUART3 (Bit 28)                                    */
43513 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART3_Msk (0xf0000000UL)           /*!< WTLPUART3 (Bitfield-Mask: 0x0f)                       */
43514 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART2_Pos (24UL)                   /*!< WTLPUART2 (Bit 24)                                    */
43515 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART2_Msk (0xf000000UL)            /*!< WTLPUART2 (Bitfield-Mask: 0x0f)                       */
43516 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART1_Pos (20UL)                   /*!< WTLPUART1 (Bit 20)                                    */
43517 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART1_Msk (0xf00000UL)             /*!< WTLPUART1 (Bitfield-Mask: 0x0f)                       */
43518 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART0_Pos (16UL)                   /*!< WTLPUART0 (Bit 16)                                    */
43519 #define PWRCTRL_PWRWEIGHTLP0_WTLPUART0_Msk (0xf0000UL)              /*!< WTLPUART0 (Bitfield-Mask: 0x0f)                       */
43520 #define PWRCTRL_PWRWEIGHTLP0_WTLPIOS_Pos  (12UL)                    /*!< WTLPIOS (Bit 12)                                      */
43521 #define PWRCTRL_PWRWEIGHTLP0_WTLPIOS_Msk  (0xf000UL)                /*!< WTLPIOS (Bitfield-Mask: 0x0f)                         */
43522 #define PWRCTRL_PWRWEIGHTLP0_WTLPDSP1_Pos (8UL)                     /*!< WTLPDSP1 (Bit 8)                                      */
43523 #define PWRCTRL_PWRWEIGHTLP0_WTLPDSP1_Msk (0xf00UL)                 /*!< WTLPDSP1 (Bitfield-Mask: 0x0f)                        */
43524 #define PWRCTRL_PWRWEIGHTLP0_WTLPDSP0_Pos (4UL)                     /*!< WTLPDSP0 (Bit 4)                                      */
43525 #define PWRCTRL_PWRWEIGHTLP0_WTLPDSP0_Msk (0xf0UL)                  /*!< WTLPDSP0 (Bitfield-Mask: 0x0f)                        */
43526 #define PWRCTRL_PWRWEIGHTLP0_WTLPMCU_Pos  (0UL)                     /*!< WTLPMCU (Bit 0)                                       */
43527 #define PWRCTRL_PWRWEIGHTLP0_WTLPMCU_Msk  (0xfUL)                   /*!< WTLPMCU (Bitfield-Mask: 0x0f)                         */
43528 /* =====================================================  PWRWEIGHTLP1  ====================================================== */
43529 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM7_Pos (28UL)                    /*!< WTLPIOM7 (Bit 28)                                     */
43530 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM7_Msk (0xf0000000UL)            /*!< WTLPIOM7 (Bitfield-Mask: 0x0f)                        */
43531 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM6_Pos (24UL)                    /*!< WTLPIOM6 (Bit 24)                                     */
43532 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM6_Msk (0xf000000UL)             /*!< WTLPIOM6 (Bitfield-Mask: 0x0f)                        */
43533 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM5_Pos (20UL)                    /*!< WTLPIOM5 (Bit 20)                                     */
43534 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM5_Msk (0xf00000UL)              /*!< WTLPIOM5 (Bitfield-Mask: 0x0f)                        */
43535 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM4_Pos (16UL)                    /*!< WTLPIOM4 (Bit 16)                                     */
43536 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM4_Msk (0xf0000UL)               /*!< WTLPIOM4 (Bitfield-Mask: 0x0f)                        */
43537 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM3_Pos (12UL)                    /*!< WTLPIOM3 (Bit 12)                                     */
43538 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM3_Msk (0xf000UL)                /*!< WTLPIOM3 (Bitfield-Mask: 0x0f)                        */
43539 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM2_Pos (8UL)                     /*!< WTLPIOM2 (Bit 8)                                      */
43540 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM2_Msk (0xf00UL)                 /*!< WTLPIOM2 (Bitfield-Mask: 0x0f)                        */
43541 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM1_Pos (4UL)                     /*!< WTLPIOM1 (Bit 4)                                      */
43542 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM1_Msk (0xf0UL)                  /*!< WTLPIOM1 (Bitfield-Mask: 0x0f)                        */
43543 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM0_Pos (0UL)                     /*!< WTLPIOM0 (Bit 0)                                      */
43544 #define PWRCTRL_PWRWEIGHTLP1_WTLPIOM0_Msk (0xfUL)                   /*!< WTLPIOM0 (Bitfield-Mask: 0x0f)                        */
43545 /* =====================================================  PWRWEIGHTLP2  ====================================================== */
43546 #define PWRCTRL_PWRWEIGHTLP2_WTLPUSB_Pos  (28UL)                    /*!< WTLPUSB (Bit 28)                                      */
43547 #define PWRCTRL_PWRWEIGHTLP2_WTLPUSB_Msk  (0xf0000000UL)            /*!< WTLPUSB (Bitfield-Mask: 0x0f)                         */
43548 #define PWRCTRL_PWRWEIGHTLP2_WTLPSDIO_Pos (24UL)                    /*!< WTLPSDIO (Bit 24)                                     */
43549 #define PWRCTRL_PWRWEIGHTLP2_WTLPSDIO_Msk (0xf000000UL)             /*!< WTLPSDIO (Bitfield-Mask: 0x0f)                        */
43550 #define PWRCTRL_PWRWEIGHTLP2_WTLPCRYPTO_Pos (20UL)                  /*!< WTLPCRYPTO (Bit 20)                                   */
43551 #define PWRCTRL_PWRWEIGHTLP2_WTLPCRYPTO_Msk (0xf00000UL)            /*!< WTLPCRYPTO (Bitfield-Mask: 0x0f)                      */
43552 #define PWRCTRL_PWRWEIGHTLP2_WTLPDISP_Pos (16UL)                    /*!< WTLPDISP (Bit 16)                                     */
43553 #define PWRCTRL_PWRWEIGHTLP2_WTLPDISP_Msk (0xf0000UL)               /*!< WTLPDISP (Bitfield-Mask: 0x0f)                        */
43554 #define PWRCTRL_PWRWEIGHTLP2_WTLPGFX_Pos  (12UL)                    /*!< WTLPGFX (Bit 12)                                      */
43555 #define PWRCTRL_PWRWEIGHTLP2_WTLPGFX_Msk  (0xf000UL)                /*!< WTLPGFX (Bitfield-Mask: 0x0f)                         */
43556 #define PWRCTRL_PWRWEIGHTLP2_WTLPMSPI1_Pos (8UL)                    /*!< WTLPMSPI1 (Bit 8)                                     */
43557 #define PWRCTRL_PWRWEIGHTLP2_WTLPMSPI1_Msk (0xf00UL)                /*!< WTLPMSPI1 (Bitfield-Mask: 0x0f)                       */
43558 #define PWRCTRL_PWRWEIGHTLP2_WTLPMSPI0_Pos (4UL)                    /*!< WTLPMSPI0 (Bit 4)                                     */
43559 #define PWRCTRL_PWRWEIGHTLP2_WTLPMSPI0_Msk (0xf0UL)                 /*!< WTLPMSPI0 (Bitfield-Mask: 0x0f)                       */
43560 #define PWRCTRL_PWRWEIGHTLP2_WTLPADC_Pos  (0UL)                     /*!< WTLPADC (Bit 0)                                       */
43561 #define PWRCTRL_PWRWEIGHTLP2_WTLPADC_Msk  (0xfUL)                   /*!< WTLPADC (Bitfield-Mask: 0x0f)                         */
43562 /* =====================================================  PWRWEIGHTLP3  ====================================================== */
43563 #define PWRCTRL_PWRWEIGHTLP3_WTLPMSPI2_Pos (28UL)                   /*!< WTLPMSPI2 (Bit 28)                                    */
43564 #define PWRCTRL_PWRWEIGHTLP3_WTLPMSPI2_Msk (0xf0000000UL)           /*!< WTLPMSPI2 (Bitfield-Mask: 0x0f)                       */
43565 #define PWRCTRL_PWRWEIGHTLP3_WTLPI3C1_Pos (24UL)                    /*!< WTLPI3C1 (Bit 24)                                     */
43566 #define PWRCTRL_PWRWEIGHTLP3_WTLPI3C1_Msk (0xf000000UL)             /*!< WTLPI3C1 (Bitfield-Mask: 0x0f)                        */
43567 #define PWRCTRL_PWRWEIGHTLP3_WTLPI3C0_Pos (20UL)                    /*!< WTLPI3C0 (Bit 20)                                     */
43568 #define PWRCTRL_PWRWEIGHTLP3_WTLPI3C0_Msk (0xf00000UL)              /*!< WTLPI3C0 (Bitfield-Mask: 0x0f)                        */
43569 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDADC_Pos (16UL)                  /*!< WTLPAUDADC (Bit 16)                                   */
43570 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDADC_Msk (0xf0000UL)             /*!< WTLPAUDADC (Bitfield-Mask: 0x0f)                      */
43571 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDPB_Pos (12UL)                   /*!< WTLPAUDPB (Bit 12)                                    */
43572 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDPB_Msk (0xf000UL)               /*!< WTLPAUDPB (Bitfield-Mask: 0x0f)                       */
43573 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDREC_Pos (8UL)                   /*!< WTLPAUDREC (Bit 8)                                    */
43574 #define PWRCTRL_PWRWEIGHTLP3_WTLPAUDREC_Msk (0xf00UL)               /*!< WTLPAUDREC (Bitfield-Mask: 0x0f)                      */
43575 #define PWRCTRL_PWRWEIGHTLP3_WTLPDBG_Pos  (4UL)                     /*!< WTLPDBG (Bit 4)                                       */
43576 #define PWRCTRL_PWRWEIGHTLP3_WTLPDBG_Msk  (0xf0UL)                  /*!< WTLPDBG (Bitfield-Mask: 0x0f)                         */
43577 #define PWRCTRL_PWRWEIGHTLP3_WTLPDSPA_Pos (0UL)                     /*!< WTLPDSPA (Bit 0)                                      */
43578 #define PWRCTRL_PWRWEIGHTLP3_WTLPDSPA_Msk (0xfUL)                   /*!< WTLPDSPA (Bitfield-Mask: 0x0f)                        */
43579 /* =====================================================  PWRWEIGHTLP4  ====================================================== */
43580 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM3_Pos (28UL)                    /*!< WTLPPDM3 (Bit 28)                                     */
43581 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM3_Msk (0xf0000000UL)            /*!< WTLPPDM3 (Bitfield-Mask: 0x0f)                        */
43582 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM2_Pos (24UL)                    /*!< WTLPPDM2 (Bit 24)                                     */
43583 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM2_Msk (0xf000000UL)             /*!< WTLPPDM2 (Bitfield-Mask: 0x0f)                        */
43584 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM1_Pos (20UL)                    /*!< WTLPPDM1 (Bit 20)                                     */
43585 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM1_Msk (0xf00000UL)              /*!< WTLPPDM1 (Bitfield-Mask: 0x0f)                        */
43586 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM0_Pos (16UL)                    /*!< WTLPPDM0 (Bit 16)                                     */
43587 #define PWRCTRL_PWRWEIGHTLP4_WTLPPDM0_Msk (0xf0000UL)               /*!< WTLPPDM0 (Bitfield-Mask: 0x0f)                        */
43588 #define PWRCTRL_PWRWEIGHTLP4_WTLPI2S1_Pos (4UL)                     /*!< WTLPI2S1 (Bit 4)                                      */
43589 #define PWRCTRL_PWRWEIGHTLP4_WTLPI2S1_Msk (0xf0UL)                  /*!< WTLPI2S1 (Bitfield-Mask: 0x0f)                        */
43590 #define PWRCTRL_PWRWEIGHTLP4_WTLPI2S0_Pos (0UL)                     /*!< WTLPI2S0 (Bit 0)                                      */
43591 #define PWRCTRL_PWRWEIGHTLP4_WTLPI2S0_Msk (0xfUL)                   /*!< WTLPI2S0 (Bitfield-Mask: 0x0f)                        */
43592 /* =====================================================  PWRWEIGHTLP5  ====================================================== */
43593 #define PWRCTRL_PWRWEIGHTLP5_WTLPUSBPHY_Pos (4UL)                   /*!< WTLPUSBPHY (Bit 4)                                    */
43594 #define PWRCTRL_PWRWEIGHTLP5_WTLPUSBPHY_Msk (0xf0UL)                /*!< WTLPUSBPHY (Bitfield-Mask: 0x0f)                      */
43595 #define PWRCTRL_PWRWEIGHTLP5_WTLPDISPPHY_Pos (0UL)                  /*!< WTLPDISPPHY (Bit 0)                                   */
43596 #define PWRCTRL_PWRWEIGHTLP5_WTLPDISPPHY_Msk (0xfUL)                /*!< WTLPDISPPHY (Bitfield-Mask: 0x0f)                     */
43597 /* =====================================================  PWRWEIGHTHP0  ====================================================== */
43598 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART3_Pos (28UL)                   /*!< WTHPUART3 (Bit 28)                                    */
43599 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART3_Msk (0xf0000000UL)           /*!< WTHPUART3 (Bitfield-Mask: 0x0f)                       */
43600 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART2_Pos (24UL)                   /*!< WTHPUART2 (Bit 24)                                    */
43601 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART2_Msk (0xf000000UL)            /*!< WTHPUART2 (Bitfield-Mask: 0x0f)                       */
43602 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART1_Pos (20UL)                   /*!< WTHPUART1 (Bit 20)                                    */
43603 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART1_Msk (0xf00000UL)             /*!< WTHPUART1 (Bitfield-Mask: 0x0f)                       */
43604 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART0_Pos (16UL)                   /*!< WTHPUART0 (Bit 16)                                    */
43605 #define PWRCTRL_PWRWEIGHTHP0_WTHPUART0_Msk (0xf0000UL)              /*!< WTHPUART0 (Bitfield-Mask: 0x0f)                       */
43606 #define PWRCTRL_PWRWEIGHTHP0_WTHPIOS_Pos  (12UL)                    /*!< WTHPIOS (Bit 12)                                      */
43607 #define PWRCTRL_PWRWEIGHTHP0_WTHPIOS_Msk  (0xf000UL)                /*!< WTHPIOS (Bitfield-Mask: 0x0f)                         */
43608 #define PWRCTRL_PWRWEIGHTHP0_WTHPDSP1_Pos (8UL)                     /*!< WTHPDSP1 (Bit 8)                                      */
43609 #define PWRCTRL_PWRWEIGHTHP0_WTHPDSP1_Msk (0xf00UL)                 /*!< WTHPDSP1 (Bitfield-Mask: 0x0f)                        */
43610 #define PWRCTRL_PWRWEIGHTHP0_WTHPDSP0_Pos (4UL)                     /*!< WTHPDSP0 (Bit 4)                                      */
43611 #define PWRCTRL_PWRWEIGHTHP0_WTHPDSP0_Msk (0xf0UL)                  /*!< WTHPDSP0 (Bitfield-Mask: 0x0f)                        */
43612 #define PWRCTRL_PWRWEIGHTHP0_WTHPMCU_Pos  (0UL)                     /*!< WTHPMCU (Bit 0)                                       */
43613 #define PWRCTRL_PWRWEIGHTHP0_WTHPMCU_Msk  (0xfUL)                   /*!< WTHPMCU (Bitfield-Mask: 0x0f)                         */
43614 /* =====================================================  PWRWEIGHTHP1  ====================================================== */
43615 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM7_Pos (28UL)                    /*!< WTHPIOM7 (Bit 28)                                     */
43616 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM7_Msk (0xf0000000UL)            /*!< WTHPIOM7 (Bitfield-Mask: 0x0f)                        */
43617 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM6_Pos (24UL)                    /*!< WTHPIOM6 (Bit 24)                                     */
43618 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM6_Msk (0xf000000UL)             /*!< WTHPIOM6 (Bitfield-Mask: 0x0f)                        */
43619 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM5_Pos (20UL)                    /*!< WTHPIOM5 (Bit 20)                                     */
43620 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM5_Msk (0xf00000UL)              /*!< WTHPIOM5 (Bitfield-Mask: 0x0f)                        */
43621 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM4_Pos (16UL)                    /*!< WTHPIOM4 (Bit 16)                                     */
43622 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM4_Msk (0xf0000UL)               /*!< WTHPIOM4 (Bitfield-Mask: 0x0f)                        */
43623 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM3_Pos (12UL)                    /*!< WTHPIOM3 (Bit 12)                                     */
43624 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM3_Msk (0xf000UL)                /*!< WTHPIOM3 (Bitfield-Mask: 0x0f)                        */
43625 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM2_Pos (8UL)                     /*!< WTHPIOM2 (Bit 8)                                      */
43626 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM2_Msk (0xf00UL)                 /*!< WTHPIOM2 (Bitfield-Mask: 0x0f)                        */
43627 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM1_Pos (4UL)                     /*!< WTHPIOM1 (Bit 4)                                      */
43628 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM1_Msk (0xf0UL)                  /*!< WTHPIOM1 (Bitfield-Mask: 0x0f)                        */
43629 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM0_Pos (0UL)                     /*!< WTHPIOM0 (Bit 0)                                      */
43630 #define PWRCTRL_PWRWEIGHTHP1_WTHPIOM0_Msk (0xfUL)                   /*!< WTHPIOM0 (Bitfield-Mask: 0x0f)                        */
43631 /* =====================================================  PWRWEIGHTHP2  ====================================================== */
43632 #define PWRCTRL_PWRWEIGHTHP2_WTHPUSB_Pos  (28UL)                    /*!< WTHPUSB (Bit 28)                                      */
43633 #define PWRCTRL_PWRWEIGHTHP2_WTHPUSB_Msk  (0xf0000000UL)            /*!< WTHPUSB (Bitfield-Mask: 0x0f)                         */
43634 #define PWRCTRL_PWRWEIGHTHP2_WTHPSDIO_Pos (24UL)                    /*!< WTHPSDIO (Bit 24)                                     */
43635 #define PWRCTRL_PWRWEIGHTHP2_WTHPSDIO_Msk (0xf000000UL)             /*!< WTHPSDIO (Bitfield-Mask: 0x0f)                        */
43636 #define PWRCTRL_PWRWEIGHTHP2_WTHPCRYPTO_Pos (20UL)                  /*!< WTHPCRYPTO (Bit 20)                                   */
43637 #define PWRCTRL_PWRWEIGHTHP2_WTHPCRYPTO_Msk (0xf00000UL)            /*!< WTHPCRYPTO (Bitfield-Mask: 0x0f)                      */
43638 #define PWRCTRL_PWRWEIGHTHP2_WTHPDISP_Pos (16UL)                    /*!< WTHPDISP (Bit 16)                                     */
43639 #define PWRCTRL_PWRWEIGHTHP2_WTHPDISP_Msk (0xf0000UL)               /*!< WTHPDISP (Bitfield-Mask: 0x0f)                        */
43640 #define PWRCTRL_PWRWEIGHTHP2_WTHPGFX_Pos  (12UL)                    /*!< WTHPGFX (Bit 12)                                      */
43641 #define PWRCTRL_PWRWEIGHTHP2_WTHPGFX_Msk  (0xf000UL)                /*!< WTHPGFX (Bitfield-Mask: 0x0f)                         */
43642 #define PWRCTRL_PWRWEIGHTHP2_WTHPMSPI1_Pos (8UL)                    /*!< WTHPMSPI1 (Bit 8)                                     */
43643 #define PWRCTRL_PWRWEIGHTHP2_WTHPMSPI1_Msk (0xf00UL)                /*!< WTHPMSPI1 (Bitfield-Mask: 0x0f)                       */
43644 #define PWRCTRL_PWRWEIGHTHP2_WTHPMSPI0_Pos (4UL)                    /*!< WTHPMSPI0 (Bit 4)                                     */
43645 #define PWRCTRL_PWRWEIGHTHP2_WTHPMSPI0_Msk (0xf0UL)                 /*!< WTHPMSPI0 (Bitfield-Mask: 0x0f)                       */
43646 #define PWRCTRL_PWRWEIGHTHP2_WTHPADC_Pos  (0UL)                     /*!< WTHPADC (Bit 0)                                       */
43647 #define PWRCTRL_PWRWEIGHTHP2_WTHPADC_Msk  (0xfUL)                   /*!< WTHPADC (Bitfield-Mask: 0x0f)                         */
43648 /* =====================================================  PWRWEIGHTHP3  ====================================================== */
43649 #define PWRCTRL_PWRWEIGHTHP3_WTHPMSPI2_Pos (28UL)                   /*!< WTHPMSPI2 (Bit 28)                                    */
43650 #define PWRCTRL_PWRWEIGHTHP3_WTHPMSPI2_Msk (0xf0000000UL)           /*!< WTHPMSPI2 (Bitfield-Mask: 0x0f)                       */
43651 #define PWRCTRL_PWRWEIGHTHP3_WTHPI3C1_Pos (24UL)                    /*!< WTHPI3C1 (Bit 24)                                     */
43652 #define PWRCTRL_PWRWEIGHTHP3_WTHPI3C1_Msk (0xf000000UL)             /*!< WTHPI3C1 (Bitfield-Mask: 0x0f)                        */
43653 #define PWRCTRL_PWRWEIGHTHP3_WTHPI3C0_Pos (20UL)                    /*!< WTHPI3C0 (Bit 20)                                     */
43654 #define PWRCTRL_PWRWEIGHTHP3_WTHPI3C0_Msk (0xf00000UL)              /*!< WTHPI3C0 (Bitfield-Mask: 0x0f)                        */
43655 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDADC_Pos (16UL)                  /*!< WTHPAUDADC (Bit 16)                                   */
43656 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDADC_Msk (0xf0000UL)             /*!< WTHPAUDADC (Bitfield-Mask: 0x0f)                      */
43657 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDPB_Pos (12UL)                   /*!< WTHPAUDPB (Bit 12)                                    */
43658 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDPB_Msk (0xf000UL)               /*!< WTHPAUDPB (Bitfield-Mask: 0x0f)                       */
43659 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDREC_Pos (8UL)                   /*!< WTHPAUDREC (Bit 8)                                    */
43660 #define PWRCTRL_PWRWEIGHTHP3_WTHPAUDREC_Msk (0xf00UL)               /*!< WTHPAUDREC (Bitfield-Mask: 0x0f)                      */
43661 #define PWRCTRL_PWRWEIGHTHP3_WTHPDBG_Pos  (4UL)                     /*!< WTHPDBG (Bit 4)                                       */
43662 #define PWRCTRL_PWRWEIGHTHP3_WTHPDBG_Msk  (0xf0UL)                  /*!< WTHPDBG (Bitfield-Mask: 0x0f)                         */
43663 #define PWRCTRL_PWRWEIGHTHP3_WTHPDSPA_Pos (0UL)                     /*!< WTHPDSPA (Bit 0)                                      */
43664 #define PWRCTRL_PWRWEIGHTHP3_WTHPDSPA_Msk (0xfUL)                   /*!< WTHPDSPA (Bitfield-Mask: 0x0f)                        */
43665 /* =====================================================  PWRWEIGHTHP4  ====================================================== */
43666 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM3_Pos (28UL)                    /*!< WTHPPDM3 (Bit 28)                                     */
43667 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM3_Msk (0xf0000000UL)            /*!< WTHPPDM3 (Bitfield-Mask: 0x0f)                        */
43668 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM2_Pos (24UL)                    /*!< WTHPPDM2 (Bit 24)                                     */
43669 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM2_Msk (0xf000000UL)             /*!< WTHPPDM2 (Bitfield-Mask: 0x0f)                        */
43670 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM1_Pos (20UL)                    /*!< WTHPPDM1 (Bit 20)                                     */
43671 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM1_Msk (0xf00000UL)              /*!< WTHPPDM1 (Bitfield-Mask: 0x0f)                        */
43672 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM0_Pos (16UL)                    /*!< WTHPPDM0 (Bit 16)                                     */
43673 #define PWRCTRL_PWRWEIGHTHP4_WTHPPDM0_Msk (0xf0000UL)               /*!< WTHPPDM0 (Bitfield-Mask: 0x0f)                        */
43674 #define PWRCTRL_PWRWEIGHTHP4_WTHPI2S1_Pos (4UL)                     /*!< WTHPI2S1 (Bit 4)                                      */
43675 #define PWRCTRL_PWRWEIGHTHP4_WTHPI2S1_Msk (0xf0UL)                  /*!< WTHPI2S1 (Bitfield-Mask: 0x0f)                        */
43676 #define PWRCTRL_PWRWEIGHTHP4_WTHPI2S0_Pos (0UL)                     /*!< WTHPI2S0 (Bit 0)                                      */
43677 #define PWRCTRL_PWRWEIGHTHP4_WTHPI2S0_Msk (0xfUL)                   /*!< WTHPI2S0 (Bitfield-Mask: 0x0f)                        */
43678 /* =====================================================  PWRWEIGHTHP5  ====================================================== */
43679 #define PWRCTRL_PWRWEIGHTHP5_WTHPUSBPHY_Pos (4UL)                   /*!< WTHPUSBPHY (Bit 4)                                    */
43680 #define PWRCTRL_PWRWEIGHTHP5_WTHPUSBPHY_Msk (0xf0UL)                /*!< WTHPUSBPHY (Bitfield-Mask: 0x0f)                      */
43681 #define PWRCTRL_PWRWEIGHTHP5_WTHPDISPPHY_Pos (0UL)                  /*!< WTHPDISPPHY (Bit 0)                                   */
43682 #define PWRCTRL_PWRWEIGHTHP5_WTHPDISPPHY_Msk (0xfUL)                /*!< WTHPDISPPHY (Bitfield-Mask: 0x0f)                     */
43683 /* =====================================================  PWRWEIGHTSLP  ====================================================== */
43684 #define PWRCTRL_PWRWEIGHTSLP_WTDSMCU_Pos  (0UL)                     /*!< WTDSMCU (Bit 0)                                       */
43685 #define PWRCTRL_PWRWEIGHTSLP_WTDSMCU_Msk  (0xfUL)                   /*!< WTDSMCU (Bitfield-Mask: 0x0f)                         */
43686 /* =====================================================  VRDEMOTIONTHR  ===================================================== */
43687 #define PWRCTRL_VRDEMOTIONTHR_VRDEMOTIONTHR_Pos (0UL)               /*!< VRDEMOTIONTHR (Bit 0)                                 */
43688 #define PWRCTRL_VRDEMOTIONTHR_VRDEMOTIONTHR_Msk (0xffffffffUL)      /*!< VRDEMOTIONTHR (Bitfield-Mask: 0xffffffff)             */
43689 /* =======================================================  SRAMCTRL  ======================================================== */
43690 #define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Pos (8UL)                   /*!< SRAMLIGHTSLEEP (Bit 8)                                */
43691 #define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Msk (0xfff00UL)             /*!< SRAMLIGHTSLEEP (Bitfield-Mask: 0xfff)                 */
43692 #define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Pos (2UL)                /*!< SRAMMASTERCLKGATE (Bit 2)                             */
43693 #define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Msk (0x4UL)              /*!< SRAMMASTERCLKGATE (Bitfield-Mask: 0x01)               */
43694 #define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Pos  (1UL)                     /*!< SRAMCLKGATE (Bit 1)                                   */
43695 #define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Msk  (0x2UL)                   /*!< SRAMCLKGATE (Bitfield-Mask: 0x01)                     */
43696 /* =======================================================  ADCSTATUS  ======================================================= */
43697 #define PWRCTRL_ADCSTATUS_REFBUFPWD_Pos   (5UL)                     /*!< REFBUFPWD (Bit 5)                                     */
43698 #define PWRCTRL_ADCSTATUS_REFBUFPWD_Msk   (0x20UL)                  /*!< REFBUFPWD (Bitfield-Mask: 0x01)                       */
43699 #define PWRCTRL_ADCSTATUS_REFKEEPPWD_Pos  (4UL)                     /*!< REFKEEPPWD (Bit 4)                                    */
43700 #define PWRCTRL_ADCSTATUS_REFKEEPPWD_Msk  (0x10UL)                  /*!< REFKEEPPWD (Bitfield-Mask: 0x01)                      */
43701 #define PWRCTRL_ADCSTATUS_VBATPWD_Pos     (3UL)                     /*!< VBATPWD (Bit 3)                                       */
43702 #define PWRCTRL_ADCSTATUS_VBATPWD_Msk     (0x8UL)                   /*!< VBATPWD (Bitfield-Mask: 0x01)                         */
43703 #define PWRCTRL_ADCSTATUS_VPTATPWD_Pos    (2UL)                     /*!< VPTATPWD (Bit 2)                                      */
43704 #define PWRCTRL_ADCSTATUS_VPTATPWD_Msk    (0x4UL)                   /*!< VPTATPWD (Bitfield-Mask: 0x01)                        */
43705 #define PWRCTRL_ADCSTATUS_BGTPWD_Pos      (1UL)                     /*!< BGTPWD (Bit 1)                                        */
43706 #define PWRCTRL_ADCSTATUS_BGTPWD_Msk      (0x2UL)                   /*!< BGTPWD (Bitfield-Mask: 0x01)                          */
43707 #define PWRCTRL_ADCSTATUS_ADCPWD_Pos      (0UL)                     /*!< ADCPWD (Bit 0)                                        */
43708 #define PWRCTRL_ADCSTATUS_ADCPWD_Msk      (0x1UL)                   /*!< ADCPWD (Bitfield-Mask: 0x01)                          */
43709 /* =====================================================  AUDADCSTATUS  ====================================================== */
43710 #define PWRCTRL_AUDADCSTATUS_AUDREFBUFPWD_Pos (5UL)                 /*!< AUDREFBUFPWD (Bit 5)                                  */
43711 #define PWRCTRL_AUDADCSTATUS_AUDREFBUFPWD_Msk (0x20UL)              /*!< AUDREFBUFPWD (Bitfield-Mask: 0x01)                    */
43712 #define PWRCTRL_AUDADCSTATUS_AUDREFKEEPPWD_Pos (4UL)                /*!< AUDREFKEEPPWD (Bit 4)                                 */
43713 #define PWRCTRL_AUDADCSTATUS_AUDREFKEEPPWD_Msk (0x10UL)             /*!< AUDREFKEEPPWD (Bitfield-Mask: 0x01)                   */
43714 #define PWRCTRL_AUDADCSTATUS_AUDVBATPWD_Pos (3UL)                   /*!< AUDVBATPWD (Bit 3)                                    */
43715 #define PWRCTRL_AUDADCSTATUS_AUDVBATPWD_Msk (0x8UL)                 /*!< AUDVBATPWD (Bitfield-Mask: 0x01)                      */
43716 #define PWRCTRL_AUDADCSTATUS_AUDVPTATPWD_Pos (2UL)                  /*!< AUDVPTATPWD (Bit 2)                                   */
43717 #define PWRCTRL_AUDADCSTATUS_AUDVPTATPWD_Msk (0x4UL)                /*!< AUDVPTATPWD (Bitfield-Mask: 0x01)                     */
43718 #define PWRCTRL_AUDADCSTATUS_AUDBGTPWD_Pos (1UL)                    /*!< AUDBGTPWD (Bit 1)                                     */
43719 #define PWRCTRL_AUDADCSTATUS_AUDBGTPWD_Msk (0x2UL)                  /*!< AUDBGTPWD (Bitfield-Mask: 0x01)                       */
43720 #define PWRCTRL_AUDADCSTATUS_AUDADCPWD_Pos (0UL)                    /*!< AUDADCPWD (Bit 0)                                     */
43721 #define PWRCTRL_AUDADCSTATUS_AUDADCPWD_Msk (0x1UL)                  /*!< AUDADCPWD (Bitfield-Mask: 0x01)                       */
43722 /* =======================================================  EMONCTRL  ======================================================== */
43723 #define PWRCTRL_EMONCTRL_CLEAR_Pos        (8UL)                     /*!< CLEAR (Bit 8)                                         */
43724 #define PWRCTRL_EMONCTRL_CLEAR_Msk        (0xff00UL)                /*!< CLEAR (Bitfield-Mask: 0xff)                           */
43725 #define PWRCTRL_EMONCTRL_FREEZE_Pos       (0UL)                     /*!< FREEZE (Bit 0)                                        */
43726 #define PWRCTRL_EMONCTRL_FREEZE_Msk       (0xffUL)                  /*!< FREEZE (Bitfield-Mask: 0xff)                          */
43727 /* =======================================================  EMONCFG0  ======================================================== */
43728 #define PWRCTRL_EMONCFG0_EMONSEL0_Pos     (0UL)                     /*!< EMONSEL0 (Bit 0)                                      */
43729 #define PWRCTRL_EMONCFG0_EMONSEL0_Msk     (0xffUL)                  /*!< EMONSEL0 (Bitfield-Mask: 0xff)                        */
43730 /* =======================================================  EMONCFG1  ======================================================== */
43731 #define PWRCTRL_EMONCFG1_EMONSEL1_Pos     (0UL)                     /*!< EMONSEL1 (Bit 0)                                      */
43732 #define PWRCTRL_EMONCFG1_EMONSEL1_Msk     (0xffUL)                  /*!< EMONSEL1 (Bitfield-Mask: 0xff)                        */
43733 /* =======================================================  EMONCFG2  ======================================================== */
43734 #define PWRCTRL_EMONCFG2_EMONSEL2_Pos     (0UL)                     /*!< EMONSEL2 (Bit 0)                                      */
43735 #define PWRCTRL_EMONCFG2_EMONSEL2_Msk     (0xffUL)                  /*!< EMONSEL2 (Bitfield-Mask: 0xff)                        */
43736 /* =======================================================  EMONCFG3  ======================================================== */
43737 #define PWRCTRL_EMONCFG3_EMONSEL3_Pos     (0UL)                     /*!< EMONSEL3 (Bit 0)                                      */
43738 #define PWRCTRL_EMONCFG3_EMONSEL3_Msk     (0xffUL)                  /*!< EMONSEL3 (Bitfield-Mask: 0xff)                        */
43739 /* =======================================================  EMONCFG4  ======================================================== */
43740 #define PWRCTRL_EMONCFG4_EMONSEL4_Pos     (0UL)                     /*!< EMONSEL4 (Bit 0)                                      */
43741 #define PWRCTRL_EMONCFG4_EMONSEL4_Msk     (0xffUL)                  /*!< EMONSEL4 (Bitfield-Mask: 0xff)                        */
43742 /* =======================================================  EMONCFG5  ======================================================== */
43743 #define PWRCTRL_EMONCFG5_EMONSEL5_Pos     (0UL)                     /*!< EMONSEL5 (Bit 0)                                      */
43744 #define PWRCTRL_EMONCFG5_EMONSEL5_Msk     (0xffUL)                  /*!< EMONSEL5 (Bitfield-Mask: 0xff)                        */
43745 /* =======================================================  EMONCFG6  ======================================================== */
43746 #define PWRCTRL_EMONCFG6_EMONSEL6_Pos     (0UL)                     /*!< EMONSEL6 (Bit 0)                                      */
43747 #define PWRCTRL_EMONCFG6_EMONSEL6_Msk     (0xffUL)                  /*!< EMONSEL6 (Bitfield-Mask: 0xff)                        */
43748 /* =======================================================  EMONCFG7  ======================================================== */
43749 #define PWRCTRL_EMONCFG7_EMONSEL7_Pos     (0UL)                     /*!< EMONSEL7 (Bit 0)                                      */
43750 #define PWRCTRL_EMONCFG7_EMONSEL7_Msk     (0xffUL)                  /*!< EMONSEL7 (Bitfield-Mask: 0xff)                        */
43751 /* ======================================================  EMONCOUNT0  ======================================================= */
43752 #define PWRCTRL_EMONCOUNT0_EMONCOUNT0_Pos (0UL)                     /*!< EMONCOUNT0 (Bit 0)                                    */
43753 #define PWRCTRL_EMONCOUNT0_EMONCOUNT0_Msk (0xffffffffUL)            /*!< EMONCOUNT0 (Bitfield-Mask: 0xffffffff)                */
43754 /* ======================================================  EMONCOUNT1  ======================================================= */
43755 #define PWRCTRL_EMONCOUNT1_EMONCOUNT1_Pos (0UL)                     /*!< EMONCOUNT1 (Bit 0)                                    */
43756 #define PWRCTRL_EMONCOUNT1_EMONCOUNT1_Msk (0xffffffffUL)            /*!< EMONCOUNT1 (Bitfield-Mask: 0xffffffff)                */
43757 /* ======================================================  EMONCOUNT2  ======================================================= */
43758 #define PWRCTRL_EMONCOUNT2_EMONCOUNT2_Pos (0UL)                     /*!< EMONCOUNT2 (Bit 0)                                    */
43759 #define PWRCTRL_EMONCOUNT2_EMONCOUNT2_Msk (0xffffffffUL)            /*!< EMONCOUNT2 (Bitfield-Mask: 0xffffffff)                */
43760 /* ======================================================  EMONCOUNT3  ======================================================= */
43761 #define PWRCTRL_EMONCOUNT3_EMONCOUNT3_Pos (0UL)                     /*!< EMONCOUNT3 (Bit 0)                                    */
43762 #define PWRCTRL_EMONCOUNT3_EMONCOUNT3_Msk (0xffffffffUL)            /*!< EMONCOUNT3 (Bitfield-Mask: 0xffffffff)                */
43763 /* ======================================================  EMONCOUNT4  ======================================================= */
43764 #define PWRCTRL_EMONCOUNT4_EMONCOUNT4_Pos (0UL)                     /*!< EMONCOUNT4 (Bit 0)                                    */
43765 #define PWRCTRL_EMONCOUNT4_EMONCOUNT4_Msk (0xffffffffUL)            /*!< EMONCOUNT4 (Bitfield-Mask: 0xffffffff)                */
43766 /* ======================================================  EMONCOUNT5  ======================================================= */
43767 #define PWRCTRL_EMONCOUNT5_EMONCOUNT5_Pos (0UL)                     /*!< EMONCOUNT5 (Bit 0)                                    */
43768 #define PWRCTRL_EMONCOUNT5_EMONCOUNT5_Msk (0xffffffffUL)            /*!< EMONCOUNT5 (Bitfield-Mask: 0xffffffff)                */
43769 /* ======================================================  EMONCOUNT6  ======================================================= */
43770 #define PWRCTRL_EMONCOUNT6_EMONCOUNT6_Pos (0UL)                     /*!< EMONCOUNT6 (Bit 0)                                    */
43771 #define PWRCTRL_EMONCOUNT6_EMONCOUNT6_Msk (0xffffffffUL)            /*!< EMONCOUNT6 (Bitfield-Mask: 0xffffffff)                */
43772 /* ======================================================  EMONCOUNT7  ======================================================= */
43773 #define PWRCTRL_EMONCOUNT7_EMONCOUNT7_Pos (0UL)                     /*!< EMONCOUNT7 (Bit 0)                                    */
43774 #define PWRCTRL_EMONCOUNT7_EMONCOUNT7_Msk (0xffffffffUL)            /*!< EMONCOUNT7 (Bitfield-Mask: 0xffffffff)                */
43775 /* ======================================================  EMONSTATUS  ======================================================= */
43776 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW7_Pos (7UL)                  /*!< EMONOVERFLOW7 (Bit 7)                                 */
43777 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW7_Msk (0x80UL)               /*!< EMONOVERFLOW7 (Bitfield-Mask: 0x01)                   */
43778 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW6_Pos (6UL)                  /*!< EMONOVERFLOW6 (Bit 6)                                 */
43779 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW6_Msk (0x40UL)               /*!< EMONOVERFLOW6 (Bitfield-Mask: 0x01)                   */
43780 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW5_Pos (5UL)                  /*!< EMONOVERFLOW5 (Bit 5)                                 */
43781 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW5_Msk (0x20UL)               /*!< EMONOVERFLOW5 (Bitfield-Mask: 0x01)                   */
43782 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW4_Pos (4UL)                  /*!< EMONOVERFLOW4 (Bit 4)                                 */
43783 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW4_Msk (0x10UL)               /*!< EMONOVERFLOW4 (Bitfield-Mask: 0x01)                   */
43784 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW3_Pos (3UL)                  /*!< EMONOVERFLOW3 (Bit 3)                                 */
43785 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW3_Msk (0x8UL)                /*!< EMONOVERFLOW3 (Bitfield-Mask: 0x01)                   */
43786 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW2_Pos (2UL)                  /*!< EMONOVERFLOW2 (Bit 2)                                 */
43787 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW2_Msk (0x4UL)                /*!< EMONOVERFLOW2 (Bitfield-Mask: 0x01)                   */
43788 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW1_Pos (1UL)                  /*!< EMONOVERFLOW1 (Bit 1)                                 */
43789 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW1_Msk (0x2UL)                /*!< EMONOVERFLOW1 (Bitfield-Mask: 0x01)                   */
43790 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW0_Pos (0UL)                  /*!< EMONOVERFLOW0 (Bit 0)                                 */
43791 #define PWRCTRL_EMONSTATUS_EMONOVERFLOW0_Msk (0x1UL)                /*!< EMONOVERFLOW0 (Bitfield-Mask: 0x01)                   */
43792 
43793 
43794 /* =========================================================================================================================== */
43795 /* ================                                          RSTGEN                                           ================ */
43796 /* =========================================================================================================================== */
43797 
43798 /* ==========================================================  CFG  ========================================================== */
43799 #define RSTGEN_CFG_WDREN_Pos              (1UL)                     /*!< WDREN (Bit 1)                                         */
43800 #define RSTGEN_CFG_WDREN_Msk              (0x2UL)                   /*!< WDREN (Bitfield-Mask: 0x01)                           */
43801 #define RSTGEN_CFG_BODHREN_Pos            (0UL)                     /*!< BODHREN (Bit 0)                                       */
43802 #define RSTGEN_CFG_BODHREN_Msk            (0x1UL)                   /*!< BODHREN (Bitfield-Mask: 0x01)                         */
43803 /* =========================================================  SWPOI  ========================================================= */
43804 #define RSTGEN_SWPOI_SWPOIKEY_Pos         (0UL)                     /*!< SWPOIKEY (Bit 0)                                      */
43805 #define RSTGEN_SWPOI_SWPOIKEY_Msk         (0xffUL)                  /*!< SWPOIKEY (Bitfield-Mask: 0xff)                        */
43806 /* =========================================================  SWPOR  ========================================================= */
43807 #define RSTGEN_SWPOR_SWPORKEY_Pos         (0UL)                     /*!< SWPORKEY (Bit 0)                                      */
43808 #define RSTGEN_SWPOR_SWPORKEY_Msk         (0xffUL)                  /*!< SWPORKEY (Bitfield-Mask: 0xff)                        */
43809 /* =======================================================  SIMOBODM  ======================================================== */
43810 #define RSTGEN_SIMOBODM_DIGBOECLV_Pos     (3UL)                     /*!< DIGBOECLV (Bit 3)                                     */
43811 #define RSTGEN_SIMOBODM_DIGBOECLV_Msk     (0x8UL)                   /*!< DIGBOECLV (Bitfield-Mask: 0x01)                       */
43812 #define RSTGEN_SIMOBODM_DIGBOES_Pos       (2UL)                     /*!< DIGBOES (Bit 2)                                       */
43813 #define RSTGEN_SIMOBODM_DIGBOES_Msk       (0x4UL)                   /*!< DIGBOES (Bitfield-Mask: 0x01)                         */
43814 #define RSTGEN_SIMOBODM_DIGBOEF_Pos       (1UL)                     /*!< DIGBOEF (Bit 1)                                       */
43815 #define RSTGEN_SIMOBODM_DIGBOEF_Msk       (0x2UL)                   /*!< DIGBOEF (Bitfield-Mask: 0x01)                         */
43816 #define RSTGEN_SIMOBODM_DIGBOEC_Pos       (0UL)                     /*!< DIGBOEC (Bit 0)                                       */
43817 #define RSTGEN_SIMOBODM_DIGBOEC_Msk       (0x1UL)                   /*!< DIGBOEC (Bitfield-Mask: 0x01)                         */
43818 /* =========================================================  INTEN  ========================================================= */
43819 #define RSTGEN_INTEN_BODDIGCLV_Pos        (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
43820 #define RSTGEN_INTEN_BODDIGCLV_Msk        (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
43821 #define RSTGEN_INTEN_BODDIGS_Pos          (3UL)                     /*!< BODDIGS (Bit 3)                                       */
43822 #define RSTGEN_INTEN_BODDIGS_Msk          (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
43823 #define RSTGEN_INTEN_BODDIGF_Pos          (2UL)                     /*!< BODDIGF (Bit 2)                                       */
43824 #define RSTGEN_INTEN_BODDIGF_Msk          (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
43825 #define RSTGEN_INTEN_BODDIGC_Pos          (1UL)                     /*!< BODDIGC (Bit 1)                                       */
43826 #define RSTGEN_INTEN_BODDIGC_Msk          (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
43827 #define RSTGEN_INTEN_BODH_Pos             (0UL)                     /*!< BODH (Bit 0)                                          */
43828 #define RSTGEN_INTEN_BODH_Msk             (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
43829 /* ========================================================  INTSTAT  ======================================================== */
43830 #define RSTGEN_INTSTAT_BODDIGCLV_Pos      (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
43831 #define RSTGEN_INTSTAT_BODDIGCLV_Msk      (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
43832 #define RSTGEN_INTSTAT_BODDIGS_Pos        (3UL)                     /*!< BODDIGS (Bit 3)                                       */
43833 #define RSTGEN_INTSTAT_BODDIGS_Msk        (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
43834 #define RSTGEN_INTSTAT_BODDIGF_Pos        (2UL)                     /*!< BODDIGF (Bit 2)                                       */
43835 #define RSTGEN_INTSTAT_BODDIGF_Msk        (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
43836 #define RSTGEN_INTSTAT_BODDIGC_Pos        (1UL)                     /*!< BODDIGC (Bit 1)                                       */
43837 #define RSTGEN_INTSTAT_BODDIGC_Msk        (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
43838 #define RSTGEN_INTSTAT_BODH_Pos           (0UL)                     /*!< BODH (Bit 0)                                          */
43839 #define RSTGEN_INTSTAT_BODH_Msk           (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
43840 /* ========================================================  INTCLR  ========================================================= */
43841 #define RSTGEN_INTCLR_BODDIGCLV_Pos       (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
43842 #define RSTGEN_INTCLR_BODDIGCLV_Msk       (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
43843 #define RSTGEN_INTCLR_BODDIGS_Pos         (3UL)                     /*!< BODDIGS (Bit 3)                                       */
43844 #define RSTGEN_INTCLR_BODDIGS_Msk         (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
43845 #define RSTGEN_INTCLR_BODDIGF_Pos         (2UL)                     /*!< BODDIGF (Bit 2)                                       */
43846 #define RSTGEN_INTCLR_BODDIGF_Msk         (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
43847 #define RSTGEN_INTCLR_BODDIGC_Pos         (1UL)                     /*!< BODDIGC (Bit 1)                                       */
43848 #define RSTGEN_INTCLR_BODDIGC_Msk         (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
43849 #define RSTGEN_INTCLR_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
43850 #define RSTGEN_INTCLR_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
43851 /* ========================================================  INTSET  ========================================================= */
43852 #define RSTGEN_INTSET_BODDIGCLV_Pos       (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
43853 #define RSTGEN_INTSET_BODDIGCLV_Msk       (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
43854 #define RSTGEN_INTSET_BODDIGS_Pos         (3UL)                     /*!< BODDIGS (Bit 3)                                       */
43855 #define RSTGEN_INTSET_BODDIGS_Msk         (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
43856 #define RSTGEN_INTSET_BODDIGF_Pos         (2UL)                     /*!< BODDIGF (Bit 2)                                       */
43857 #define RSTGEN_INTSET_BODDIGF_Msk         (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
43858 #define RSTGEN_INTSET_BODDIGC_Pos         (1UL)                     /*!< BODDIGC (Bit 1)                                       */
43859 #define RSTGEN_INTSET_BODDIGC_Msk         (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
43860 #define RSTGEN_INTSET_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
43861 #define RSTGEN_INTSET_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
43862 /* =========================================================  STAT  ========================================================== */
43863 #define RSTGEN_STAT_BOSSTAT_Pos           (10UL)                    /*!< BOSSTAT (Bit 10)                                      */
43864 #define RSTGEN_STAT_BOSSTAT_Msk           (0x400UL)                 /*!< BOSSTAT (Bitfield-Mask: 0x01)                         */
43865 #define RSTGEN_STAT_BOFSTAT_Pos           (9UL)                     /*!< BOFSTAT (Bit 9)                                       */
43866 #define RSTGEN_STAT_BOFSTAT_Msk           (0x200UL)                 /*!< BOFSTAT (Bitfield-Mask: 0x01)                         */
43867 #define RSTGEN_STAT_BOCSTAT_Pos           (8UL)                     /*!< BOCSTAT (Bit 8)                                       */
43868 #define RSTGEN_STAT_BOCSTAT_Msk           (0x100UL)                 /*!< BOCSTAT (Bitfield-Mask: 0x01)                         */
43869 #define RSTGEN_STAT_BOUSTAT_Pos           (7UL)                     /*!< BOUSTAT (Bit 7)                                       */
43870 #define RSTGEN_STAT_BOUSTAT_Msk           (0x80UL)                  /*!< BOUSTAT (Bitfield-Mask: 0x01)                         */
43871 #define RSTGEN_STAT_WDRSTAT_Pos           (6UL)                     /*!< WDRSTAT (Bit 6)                                       */
43872 #define RSTGEN_STAT_WDRSTAT_Msk           (0x40UL)                  /*!< WDRSTAT (Bitfield-Mask: 0x01)                         */
43873 #define RSTGEN_STAT_DBGRSTAT_Pos          (5UL)                     /*!< DBGRSTAT (Bit 5)                                      */
43874 #define RSTGEN_STAT_DBGRSTAT_Msk          (0x20UL)                  /*!< DBGRSTAT (Bitfield-Mask: 0x01)                        */
43875 #define RSTGEN_STAT_POIRSTAT_Pos          (4UL)                     /*!< POIRSTAT (Bit 4)                                      */
43876 #define RSTGEN_STAT_POIRSTAT_Msk          (0x10UL)                  /*!< POIRSTAT (Bitfield-Mask: 0x01)                        */
43877 #define RSTGEN_STAT_SWRSTAT_Pos           (3UL)                     /*!< SWRSTAT (Bit 3)                                       */
43878 #define RSTGEN_STAT_SWRSTAT_Msk           (0x8UL)                   /*!< SWRSTAT (Bitfield-Mask: 0x01)                         */
43879 #define RSTGEN_STAT_BORSTAT_Pos           (2UL)                     /*!< BORSTAT (Bit 2)                                       */
43880 #define RSTGEN_STAT_BORSTAT_Msk           (0x4UL)                   /*!< BORSTAT (Bitfield-Mask: 0x01)                         */
43881 #define RSTGEN_STAT_PORSTAT_Pos           (1UL)                     /*!< PORSTAT (Bit 1)                                       */
43882 #define RSTGEN_STAT_PORSTAT_Msk           (0x2UL)                   /*!< PORSTAT (Bitfield-Mask: 0x01)                         */
43883 #define RSTGEN_STAT_EXRSTAT_Pos           (0UL)                     /*!< EXRSTAT (Bit 0)                                       */
43884 #define RSTGEN_STAT_EXRSTAT_Msk           (0x1UL)                   /*!< EXRSTAT (Bitfield-Mask: 0x01)                         */
43885 
43886 
43887 /* =========================================================================================================================== */
43888 /* ================                                            RTC                                            ================ */
43889 /* =========================================================================================================================== */
43890 
43891 /* ========================================================  RTCCTL  ========================================================= */
43892 #define RTC_RTCCTL_HR1224_Pos             (5UL)                     /*!< HR1224 (Bit 5)                                        */
43893 #define RTC_RTCCTL_HR1224_Msk             (0x20UL)                  /*!< HR1224 (Bitfield-Mask: 0x01)                          */
43894 #define RTC_RTCCTL_RSTOP_Pos              (4UL)                     /*!< RSTOP (Bit 4)                                         */
43895 #define RTC_RTCCTL_RSTOP_Msk              (0x10UL)                  /*!< RSTOP (Bitfield-Mask: 0x01)                           */
43896 #define RTC_RTCCTL_RPT_Pos                (1UL)                     /*!< RPT (Bit 1)                                           */
43897 #define RTC_RTCCTL_RPT_Msk                (0xeUL)                   /*!< RPT (Bitfield-Mask: 0x07)                             */
43898 #define RTC_RTCCTL_WRTC_Pos               (0UL)                     /*!< WRTC (Bit 0)                                          */
43899 #define RTC_RTCCTL_WRTC_Msk               (0x1UL)                   /*!< WRTC (Bitfield-Mask: 0x01)                            */
43900 /* ========================================================  RTCSTAT  ======================================================== */
43901 #define RTC_RTCSTAT_WRITEBUSY_Pos         (0UL)                     /*!< WRITEBUSY (Bit 0)                                     */
43902 #define RTC_RTCSTAT_WRITEBUSY_Msk         (0x1UL)                   /*!< WRITEBUSY (Bitfield-Mask: 0x01)                       */
43903 /* ========================================================  CTRLOW  ========================================================= */
43904 #define RTC_CTRLOW_CTRHR_Pos              (24UL)                    /*!< CTRHR (Bit 24)                                        */
43905 #define RTC_CTRLOW_CTRHR_Msk              (0x3f000000UL)            /*!< CTRHR (Bitfield-Mask: 0x3f)                           */
43906 #define RTC_CTRLOW_CTRMIN_Pos             (16UL)                    /*!< CTRMIN (Bit 16)                                       */
43907 #define RTC_CTRLOW_CTRMIN_Msk             (0x7f0000UL)              /*!< CTRMIN (Bitfield-Mask: 0x7f)                          */
43908 #define RTC_CTRLOW_CTRSEC_Pos             (8UL)                     /*!< CTRSEC (Bit 8)                                        */
43909 #define RTC_CTRLOW_CTRSEC_Msk             (0x7f00UL)                /*!< CTRSEC (Bitfield-Mask: 0x7f)                          */
43910 #define RTC_CTRLOW_CTR100_Pos             (0UL)                     /*!< CTR100 (Bit 0)                                        */
43911 #define RTC_CTRLOW_CTR100_Msk             (0xffUL)                  /*!< CTR100 (Bitfield-Mask: 0xff)                          */
43912 /* =========================================================  CTRUP  ========================================================= */
43913 #define RTC_CTRUP_CTERR_Pos               (31UL)                    /*!< CTERR (Bit 31)                                        */
43914 #define RTC_CTRUP_CTERR_Msk               (0x80000000UL)            /*!< CTERR (Bitfield-Mask: 0x01)                           */
43915 #define RTC_CTRUP_CEB_Pos                 (29UL)                    /*!< CEB (Bit 29)                                          */
43916 #define RTC_CTRUP_CEB_Msk                 (0x20000000UL)            /*!< CEB (Bitfield-Mask: 0x01)                             */
43917 #define RTC_CTRUP_CB_Pos                  (28UL)                    /*!< CB (Bit 28)                                           */
43918 #define RTC_CTRUP_CB_Msk                  (0x10000000UL)            /*!< CB (Bitfield-Mask: 0x01)                              */
43919 #define RTC_CTRUP_CTRWKDY_Pos             (24UL)                    /*!< CTRWKDY (Bit 24)                                      */
43920 #define RTC_CTRUP_CTRWKDY_Msk             (0x7000000UL)             /*!< CTRWKDY (Bitfield-Mask: 0x07)                         */
43921 #define RTC_CTRUP_CTRYR_Pos               (16UL)                    /*!< CTRYR (Bit 16)                                        */
43922 #define RTC_CTRUP_CTRYR_Msk               (0xff0000UL)              /*!< CTRYR (Bitfield-Mask: 0xff)                           */
43923 #define RTC_CTRUP_CTRMO_Pos               (8UL)                     /*!< CTRMO (Bit 8)                                         */
43924 #define RTC_CTRUP_CTRMO_Msk               (0x1f00UL)                /*!< CTRMO (Bitfield-Mask: 0x1f)                           */
43925 #define RTC_CTRUP_CTRDATE_Pos             (0UL)                     /*!< CTRDATE (Bit 0)                                       */
43926 #define RTC_CTRUP_CTRDATE_Msk             (0x3fUL)                  /*!< CTRDATE (Bitfield-Mask: 0x3f)                         */
43927 /* ========================================================  ALMLOW  ========================================================= */
43928 #define RTC_ALMLOW_ALMHR_Pos              (24UL)                    /*!< ALMHR (Bit 24)                                        */
43929 #define RTC_ALMLOW_ALMHR_Msk              (0x3f000000UL)            /*!< ALMHR (Bitfield-Mask: 0x3f)                           */
43930 #define RTC_ALMLOW_ALMMIN_Pos             (16UL)                    /*!< ALMMIN (Bit 16)                                       */
43931 #define RTC_ALMLOW_ALMMIN_Msk             (0x7f0000UL)              /*!< ALMMIN (Bitfield-Mask: 0x7f)                          */
43932 #define RTC_ALMLOW_ALMSEC_Pos             (8UL)                     /*!< ALMSEC (Bit 8)                                        */
43933 #define RTC_ALMLOW_ALMSEC_Msk             (0x7f00UL)                /*!< ALMSEC (Bitfield-Mask: 0x7f)                          */
43934 #define RTC_ALMLOW_ALM100_Pos             (0UL)                     /*!< ALM100 (Bit 0)                                        */
43935 #define RTC_ALMLOW_ALM100_Msk             (0xffUL)                  /*!< ALM100 (Bitfield-Mask: 0xff)                          */
43936 /* =========================================================  ALMUP  ========================================================= */
43937 #define RTC_ALMUP_ALMWKDY_Pos             (16UL)                    /*!< ALMWKDY (Bit 16)                                      */
43938 #define RTC_ALMUP_ALMWKDY_Msk             (0x70000UL)               /*!< ALMWKDY (Bitfield-Mask: 0x07)                         */
43939 #define RTC_ALMUP_ALMMO_Pos               (8UL)                     /*!< ALMMO (Bit 8)                                         */
43940 #define RTC_ALMUP_ALMMO_Msk               (0x1f00UL)                /*!< ALMMO (Bitfield-Mask: 0x1f)                           */
43941 #define RTC_ALMUP_ALMDATE_Pos             (0UL)                     /*!< ALMDATE (Bit 0)                                       */
43942 #define RTC_ALMUP_ALMDATE_Msk             (0x3fUL)                  /*!< ALMDATE (Bitfield-Mask: 0x3f)                         */
43943 /* =========================================================  INTEN  ========================================================= */
43944 #define RTC_INTEN_ALM_Pos                 (0UL)                     /*!< ALM (Bit 0)                                           */
43945 #define RTC_INTEN_ALM_Msk                 (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
43946 /* ========================================================  INTSTAT  ======================================================== */
43947 #define RTC_INTSTAT_ALM_Pos               (0UL)                     /*!< ALM (Bit 0)                                           */
43948 #define RTC_INTSTAT_ALM_Msk               (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
43949 /* ========================================================  INTCLR  ========================================================= */
43950 #define RTC_INTCLR_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
43951 #define RTC_INTCLR_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
43952 /* ========================================================  INTSET  ========================================================= */
43953 #define RTC_INTSET_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
43954 #define RTC_INTSET_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
43955 
43956 
43957 /* =========================================================================================================================== */
43958 /* ================                                           SDIO                                            ================ */
43959 /* =========================================================================================================================== */
43960 
43961 /* =========================================================  SDMA  ========================================================== */
43962 #define SDIO_SDMA_SDMASYSTEMADDRESS_Pos   (0UL)                     /*!< SDMASYSTEMADDRESS (Bit 0)                             */
43963 #define SDIO_SDMA_SDMASYSTEMADDRESS_Msk   (0xffffffffUL)            /*!< SDMASYSTEMADDRESS (Bitfield-Mask: 0xffffffff)         */
43964 /* =========================================================  BLOCK  ========================================================= */
43965 #define SDIO_BLOCK_BLKCNT_Pos             (16UL)                    /*!< BLKCNT (Bit 16)                                       */
43966 #define SDIO_BLOCK_BLKCNT_Msk             (0xffff0000UL)            /*!< BLKCNT (Bitfield-Mask: 0xffff)                        */
43967 #define SDIO_BLOCK_HOSTSDMABUFSZ_Pos      (12UL)                    /*!< HOSTSDMABUFSZ (Bit 12)                                */
43968 #define SDIO_BLOCK_HOSTSDMABUFSZ_Msk      (0x7000UL)                /*!< HOSTSDMABUFSZ (Bitfield-Mask: 0x07)                   */
43969 #define SDIO_BLOCK_TRANSFERBLOCKSIZE_Pos  (0UL)                     /*!< TRANSFERBLOCKSIZE (Bit 0)                             */
43970 #define SDIO_BLOCK_TRANSFERBLOCKSIZE_Msk  (0xfffUL)                 /*!< TRANSFERBLOCKSIZE (Bitfield-Mask: 0xfff)              */
43971 /* =======================================================  ARGUMENT1  ======================================================= */
43972 #define SDIO_ARGUMENT1_CMDARG1_Pos        (0UL)                     /*!< CMDARG1 (Bit 0)                                       */
43973 #define SDIO_ARGUMENT1_CMDARG1_Msk        (0xffffffffUL)            /*!< CMDARG1 (Bitfield-Mask: 0xffffffff)                   */
43974 /* =======================================================  TRANSFER  ======================================================== */
43975 #define SDIO_TRANSFER_CMDIDX_Pos          (24UL)                    /*!< CMDIDX (Bit 24)                                       */
43976 #define SDIO_TRANSFER_CMDIDX_Msk          (0x3f000000UL)            /*!< CMDIDX (Bitfield-Mask: 0x3f)                          */
43977 #define SDIO_TRANSFER_CMDTYPE_Pos         (22UL)                    /*!< CMDTYPE (Bit 22)                                      */
43978 #define SDIO_TRANSFER_CMDTYPE_Msk         (0xc00000UL)              /*!< CMDTYPE (Bitfield-Mask: 0x03)                         */
43979 #define SDIO_TRANSFER_DATAPRSNTSEL_Pos    (21UL)                    /*!< DATAPRSNTSEL (Bit 21)                                 */
43980 #define SDIO_TRANSFER_DATAPRSNTSEL_Msk    (0x200000UL)              /*!< DATAPRSNTSEL (Bitfield-Mask: 0x01)                    */
43981 #define SDIO_TRANSFER_CMDIDXCHKEN_Pos     (20UL)                    /*!< CMDIDXCHKEN (Bit 20)                                  */
43982 #define SDIO_TRANSFER_CMDIDXCHKEN_Msk     (0x100000UL)              /*!< CMDIDXCHKEN (Bitfield-Mask: 0x01)                     */
43983 #define SDIO_TRANSFER_CMDCRCCHKEN_Pos     (19UL)                    /*!< CMDCRCCHKEN (Bit 19)                                  */
43984 #define SDIO_TRANSFER_CMDCRCCHKEN_Msk     (0x80000UL)               /*!< CMDCRCCHKEN (Bitfield-Mask: 0x01)                     */
43985 #define SDIO_TRANSFER_RESPTYPESEL_Pos     (16UL)                    /*!< RESPTYPESEL (Bit 16)                                  */
43986 #define SDIO_TRANSFER_RESPTYPESEL_Msk     (0x30000UL)               /*!< RESPTYPESEL (Bitfield-Mask: 0x03)                     */
43987 #define SDIO_TRANSFER_BLKSEL_Pos          (5UL)                     /*!< BLKSEL (Bit 5)                                        */
43988 #define SDIO_TRANSFER_BLKSEL_Msk          (0x20UL)                  /*!< BLKSEL (Bitfield-Mask: 0x01)                          */
43989 #define SDIO_TRANSFER_DXFERDIRSEL_Pos     (4UL)                     /*!< DXFERDIRSEL (Bit 4)                                   */
43990 #define SDIO_TRANSFER_DXFERDIRSEL_Msk     (0x10UL)                  /*!< DXFERDIRSEL (Bitfield-Mask: 0x01)                     */
43991 #define SDIO_TRANSFER_ACMDEN_Pos          (2UL)                     /*!< ACMDEN (Bit 2)                                        */
43992 #define SDIO_TRANSFER_ACMDEN_Msk          (0xcUL)                   /*!< ACMDEN (Bitfield-Mask: 0x03)                          */
43993 #define SDIO_TRANSFER_BLKCNTEN_Pos        (1UL)                     /*!< BLKCNTEN (Bit 1)                                      */
43994 #define SDIO_TRANSFER_BLKCNTEN_Msk        (0x2UL)                   /*!< BLKCNTEN (Bitfield-Mask: 0x01)                        */
43995 #define SDIO_TRANSFER_DMAEN_Pos           (0UL)                     /*!< DMAEN (Bit 0)                                         */
43996 #define SDIO_TRANSFER_DMAEN_Msk           (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
43997 /* =======================================================  RESPONSE0  ======================================================= */
43998 #define SDIO_RESPONSE0_CMDRESP0_Pos       (0UL)                     /*!< CMDRESP0 (Bit 0)                                      */
43999 #define SDIO_RESPONSE0_CMDRESP0_Msk       (0xffffffffUL)            /*!< CMDRESP0 (Bitfield-Mask: 0xffffffff)                  */
44000 /* =======================================================  RESPONSE1  ======================================================= */
44001 #define SDIO_RESPONSE1_CMDRESP1_Pos       (0UL)                     /*!< CMDRESP1 (Bit 0)                                      */
44002 #define SDIO_RESPONSE1_CMDRESP1_Msk       (0xffffffffUL)            /*!< CMDRESP1 (Bitfield-Mask: 0xffffffff)                  */
44003 /* =======================================================  RESPONSE2  ======================================================= */
44004 #define SDIO_RESPONSE2_CMDRESP2_Pos       (0UL)                     /*!< CMDRESP2 (Bit 0)                                      */
44005 #define SDIO_RESPONSE2_CMDRESP2_Msk       (0xffffffffUL)            /*!< CMDRESP2 (Bitfield-Mask: 0xffffffff)                  */
44006 /* =======================================================  RESPONSE3  ======================================================= */
44007 #define SDIO_RESPONSE3_CMDRESP3_Pos       (0UL)                     /*!< CMDRESP3 (Bit 0)                                      */
44008 #define SDIO_RESPONSE3_CMDRESP3_Msk       (0xffffffffUL)            /*!< CMDRESP3 (Bitfield-Mask: 0xffffffff)                  */
44009 /* ========================================================  BUFFER  ========================================================= */
44010 #define SDIO_BUFFER_BUFFERDATA_Pos        (0UL)                     /*!< BUFFERDATA (Bit 0)                                    */
44011 #define SDIO_BUFFER_BUFFERDATA_Msk        (0xffffffffUL)            /*!< BUFFERDATA (Bitfield-Mask: 0xffffffff)                */
44012 /* ========================================================  PRESENT  ======================================================== */
44013 #define SDIO_PRESENT_DAT74LINE_Pos        (25UL)                    /*!< DAT74LINE (Bit 25)                                    */
44014 #define SDIO_PRESENT_DAT74LINE_Msk        (0x1e000000UL)            /*!< DAT74LINE (Bitfield-Mask: 0x0f)                       */
44015 #define SDIO_PRESENT_CMDLINE_Pos          (24UL)                    /*!< CMDLINE (Bit 24)                                      */
44016 #define SDIO_PRESENT_CMDLINE_Msk          (0x1000000UL)             /*!< CMDLINE (Bitfield-Mask: 0x01)                         */
44017 #define SDIO_PRESENT_DAT30LINE_Pos        (20UL)                    /*!< DAT30LINE (Bit 20)                                    */
44018 #define SDIO_PRESENT_DAT30LINE_Msk        (0xf00000UL)              /*!< DAT30LINE (Bitfield-Mask: 0x0f)                       */
44019 #define SDIO_PRESENT_WRPROTSW_Pos         (19UL)                    /*!< WRPROTSW (Bit 19)                                     */
44020 #define SDIO_PRESENT_WRPROTSW_Msk         (0x80000UL)               /*!< WRPROTSW (Bitfield-Mask: 0x01)                        */
44021 #define SDIO_PRESENT_CARDDET_Pos          (18UL)                    /*!< CARDDET (Bit 18)                                      */
44022 #define SDIO_PRESENT_CARDDET_Msk          (0x40000UL)               /*!< CARDDET (Bitfield-Mask: 0x01)                         */
44023 #define SDIO_PRESENT_CARDSTABLE_Pos       (17UL)                    /*!< CARDSTABLE (Bit 17)                                   */
44024 #define SDIO_PRESENT_CARDSTABLE_Msk       (0x20000UL)               /*!< CARDSTABLE (Bitfield-Mask: 0x01)                      */
44025 #define SDIO_PRESENT_CARDINSERTED_Pos     (16UL)                    /*!< CARDINSERTED (Bit 16)                                 */
44026 #define SDIO_PRESENT_CARDINSERTED_Msk     (0x10000UL)               /*!< CARDINSERTED (Bitfield-Mask: 0x01)                    */
44027 #define SDIO_PRESENT_BUFRDEN_Pos          (11UL)                    /*!< BUFRDEN (Bit 11)                                      */
44028 #define SDIO_PRESENT_BUFRDEN_Msk          (0x800UL)                 /*!< BUFRDEN (Bitfield-Mask: 0x01)                         */
44029 #define SDIO_PRESENT_BUFWREN_Pos          (10UL)                    /*!< BUFWREN (Bit 10)                                      */
44030 #define SDIO_PRESENT_BUFWREN_Msk          (0x400UL)                 /*!< BUFWREN (Bitfield-Mask: 0x01)                         */
44031 #define SDIO_PRESENT_RDXFERACT_Pos        (9UL)                     /*!< RDXFERACT (Bit 9)                                     */
44032 #define SDIO_PRESENT_RDXFERACT_Msk        (0x200UL)                 /*!< RDXFERACT (Bitfield-Mask: 0x01)                       */
44033 #define SDIO_PRESENT_WRXFERACT_Pos        (8UL)                     /*!< WRXFERACT (Bit 8)                                     */
44034 #define SDIO_PRESENT_WRXFERACT_Msk        (0x100UL)                 /*!< WRXFERACT (Bitfield-Mask: 0x01)                       */
44035 #define SDIO_PRESENT_RETUNINGREQUEST_Pos  (3UL)                     /*!< RETUNINGREQUEST (Bit 3)                               */
44036 #define SDIO_PRESENT_RETUNINGREQUEST_Msk  (0x8UL)                   /*!< RETUNINGREQUEST (Bitfield-Mask: 0x01)                 */
44037 #define SDIO_PRESENT_DLINEACT_Pos         (2UL)                     /*!< DLINEACT (Bit 2)                                      */
44038 #define SDIO_PRESENT_DLINEACT_Msk         (0x4UL)                   /*!< DLINEACT (Bitfield-Mask: 0x01)                        */
44039 #define SDIO_PRESENT_CMDINHDAT_Pos        (1UL)                     /*!< CMDINHDAT (Bit 1)                                     */
44040 #define SDIO_PRESENT_CMDINHDAT_Msk        (0x2UL)                   /*!< CMDINHDAT (Bitfield-Mask: 0x01)                       */
44041 #define SDIO_PRESENT_CMDINHCMD_Pos        (0UL)                     /*!< CMDINHCMD (Bit 0)                                     */
44042 #define SDIO_PRESENT_CMDINHCMD_Msk        (0x1UL)                   /*!< CMDINHCMD (Bitfield-Mask: 0x01)                       */
44043 /* =======================================================  HOSTCTRL1  ======================================================= */
44044 #define SDIO_HOSTCTRL1_WUENCARDREMOVL_Pos (26UL)                    /*!< WUENCARDREMOVL (Bit 26)                               */
44045 #define SDIO_HOSTCTRL1_WUENCARDREMOVL_Msk (0x4000000UL)             /*!< WUENCARDREMOVL (Bitfield-Mask: 0x01)                  */
44046 #define SDIO_HOSTCTRL1_WUENCARDINSERT_Pos (25UL)                    /*!< WUENCARDINSERT (Bit 25)                               */
44047 #define SDIO_HOSTCTRL1_WUENCARDINSERT_Msk (0x2000000UL)             /*!< WUENCARDINSERT (Bitfield-Mask: 0x01)                  */
44048 #define SDIO_HOSTCTRL1_WUENCARDINT_Pos    (24UL)                    /*!< WUENCARDINT (Bit 24)                                  */
44049 #define SDIO_HOSTCTRL1_WUENCARDINT_Msk    (0x1000000UL)             /*!< WUENCARDINT (Bitfield-Mask: 0x01)                     */
44050 #define SDIO_HOSTCTRL1_BOOTACKCHK_Pos     (23UL)                    /*!< BOOTACKCHK (Bit 23)                                   */
44051 #define SDIO_HOSTCTRL1_BOOTACKCHK_Msk     (0x800000UL)              /*!< BOOTACKCHK (Bitfield-Mask: 0x01)                      */
44052 #define SDIO_HOSTCTRL1_ALTBOOTEN_Pos      (22UL)                    /*!< ALTBOOTEN (Bit 22)                                    */
44053 #define SDIO_HOSTCTRL1_ALTBOOTEN_Msk      (0x400000UL)              /*!< ALTBOOTEN (Bitfield-Mask: 0x01)                       */
44054 #define SDIO_HOSTCTRL1_BOOTEN_Pos         (21UL)                    /*!< BOOTEN (Bit 21)                                       */
44055 #define SDIO_HOSTCTRL1_BOOTEN_Msk         (0x200000UL)              /*!< BOOTEN (Bitfield-Mask: 0x01)                          */
44056 #define SDIO_HOSTCTRL1_SPIMODE_Pos        (20UL)                    /*!< SPIMODE (Bit 20)                                      */
44057 #define SDIO_HOSTCTRL1_SPIMODE_Msk        (0x100000UL)              /*!< SPIMODE (Bitfield-Mask: 0x01)                         */
44058 #define SDIO_HOSTCTRL1_GAP_Pos            (19UL)                    /*!< GAP (Bit 19)                                          */
44059 #define SDIO_HOSTCTRL1_GAP_Msk            (0x80000UL)               /*!< GAP (Bitfield-Mask: 0x01)                             */
44060 #define SDIO_HOSTCTRL1_READWAITCTRL_Pos   (18UL)                    /*!< READWAITCTRL (Bit 18)                                 */
44061 #define SDIO_HOSTCTRL1_READWAITCTRL_Msk   (0x40000UL)               /*!< READWAITCTRL (Bitfield-Mask: 0x01)                    */
44062 #define SDIO_HOSTCTRL1_CONTREQ_Pos        (17UL)                    /*!< CONTREQ (Bit 17)                                      */
44063 #define SDIO_HOSTCTRL1_CONTREQ_Msk        (0x20000UL)               /*!< CONTREQ (Bitfield-Mask: 0x01)                         */
44064 #define SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Pos (16UL)             /*!< STOPATBLOCKGAPREQUEST (Bit 16)                        */
44065 #define SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Msk (0x10000UL)        /*!< STOPATBLOCKGAPREQUEST (Bitfield-Mask: 0x01)           */
44066 #define SDIO_HOSTCTRL1_HWRESET_Pos        (12UL)                    /*!< HWRESET (Bit 12)                                      */
44067 #define SDIO_HOSTCTRL1_HWRESET_Msk        (0x1000UL)                /*!< HWRESET (Bitfield-Mask: 0x01)                         */
44068 #define SDIO_HOSTCTRL1_VOLTSELECT_Pos     (9UL)                     /*!< VOLTSELECT (Bit 9)                                    */
44069 #define SDIO_HOSTCTRL1_VOLTSELECT_Msk     (0xe00UL)                 /*!< VOLTSELECT (Bitfield-Mask: 0x07)                      */
44070 #define SDIO_HOSTCTRL1_SDBUSPOWER_Pos     (8UL)                     /*!< SDBUSPOWER (Bit 8)                                    */
44071 #define SDIO_HOSTCTRL1_SDBUSPOWER_Msk     (0x100UL)                 /*!< SDBUSPOWER (Bitfield-Mask: 0x01)                      */
44072 #define SDIO_HOSTCTRL1_CARDSRC_Pos        (7UL)                     /*!< CARDSRC (Bit 7)                                       */
44073 #define SDIO_HOSTCTRL1_CARDSRC_Msk        (0x80UL)                  /*!< CARDSRC (Bitfield-Mask: 0x01)                         */
44074 #define SDIO_HOSTCTRL1_TESTLEVEL_Pos      (6UL)                     /*!< TESTLEVEL (Bit 6)                                     */
44075 #define SDIO_HOSTCTRL1_TESTLEVEL_Msk      (0x40UL)                  /*!< TESTLEVEL (Bitfield-Mask: 0x01)                       */
44076 #define SDIO_HOSTCTRL1_XFERWIDTH_Pos      (5UL)                     /*!< XFERWIDTH (Bit 5)                                     */
44077 #define SDIO_HOSTCTRL1_XFERWIDTH_Msk      (0x20UL)                  /*!< XFERWIDTH (Bitfield-Mask: 0x01)                       */
44078 #define SDIO_HOSTCTRL1_DMASELECT_Pos      (3UL)                     /*!< DMASELECT (Bit 3)                                     */
44079 #define SDIO_HOSTCTRL1_DMASELECT_Msk      (0x18UL)                  /*!< DMASELECT (Bitfield-Mask: 0x03)                       */
44080 #define SDIO_HOSTCTRL1_HISPEEDEN_Pos      (2UL)                     /*!< HISPEEDEN (Bit 2)                                     */
44081 #define SDIO_HOSTCTRL1_HISPEEDEN_Msk      (0x4UL)                   /*!< HISPEEDEN (Bitfield-Mask: 0x01)                       */
44082 #define SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Pos (1UL)                  /*!< DATATRANSFERWIDTH (Bit 1)                             */
44083 #define SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Msk (0x2UL)                /*!< DATATRANSFERWIDTH (Bitfield-Mask: 0x01)               */
44084 #define SDIO_HOSTCTRL1_LEDCONTROL_Pos     (0UL)                     /*!< LEDCONTROL (Bit 0)                                    */
44085 #define SDIO_HOSTCTRL1_LEDCONTROL_Msk     (0x1UL)                   /*!< LEDCONTROL (Bitfield-Mask: 0x01)                      */
44086 /* =======================================================  CLOCKCTRL  ======================================================= */
44087 #define SDIO_CLOCKCTRL_SWRSTDAT_Pos       (26UL)                    /*!< SWRSTDAT (Bit 26)                                     */
44088 #define SDIO_CLOCKCTRL_SWRSTDAT_Msk       (0x4000000UL)             /*!< SWRSTDAT (Bitfield-Mask: 0x01)                        */
44089 #define SDIO_CLOCKCTRL_SWRSTCMD_Pos       (25UL)                    /*!< SWRSTCMD (Bit 25)                                     */
44090 #define SDIO_CLOCKCTRL_SWRSTCMD_Msk       (0x2000000UL)             /*!< SWRSTCMD (Bitfield-Mask: 0x01)                        */
44091 #define SDIO_CLOCKCTRL_SWRSTALL_Pos       (24UL)                    /*!< SWRSTALL (Bit 24)                                     */
44092 #define SDIO_CLOCKCTRL_SWRSTALL_Msk       (0x1000000UL)             /*!< SWRSTALL (Bitfield-Mask: 0x01)                        */
44093 #define SDIO_CLOCKCTRL_TIMEOUTCNT_Pos     (16UL)                    /*!< TIMEOUTCNT (Bit 16)                                   */
44094 #define SDIO_CLOCKCTRL_TIMEOUTCNT_Msk     (0xf0000UL)               /*!< TIMEOUTCNT (Bitfield-Mask: 0x0f)                      */
44095 #define SDIO_CLOCKCTRL_FREQSEL_Pos        (8UL)                     /*!< FREQSEL (Bit 8)                                       */
44096 #define SDIO_CLOCKCTRL_FREQSEL_Msk        (0xff00UL)                /*!< FREQSEL (Bitfield-Mask: 0xff)                         */
44097 #define SDIO_CLOCKCTRL_UPRCLKDIV_Pos      (6UL)                     /*!< UPRCLKDIV (Bit 6)                                     */
44098 #define SDIO_CLOCKCTRL_UPRCLKDIV_Msk      (0xc0UL)                  /*!< UPRCLKDIV (Bitfield-Mask: 0x03)                       */
44099 #define SDIO_CLOCKCTRL_CLKGENSEL_Pos      (5UL)                     /*!< CLKGENSEL (Bit 5)                                     */
44100 #define SDIO_CLOCKCTRL_CLKGENSEL_Msk      (0x20UL)                  /*!< CLKGENSEL (Bitfield-Mask: 0x01)                       */
44101 #define SDIO_CLOCKCTRL_SDCLKEN_Pos        (2UL)                     /*!< SDCLKEN (Bit 2)                                       */
44102 #define SDIO_CLOCKCTRL_SDCLKEN_Msk        (0x4UL)                   /*!< SDCLKEN (Bitfield-Mask: 0x01)                         */
44103 #define SDIO_CLOCKCTRL_CLKSTABLE_Pos      (1UL)                     /*!< CLKSTABLE (Bit 1)                                     */
44104 #define SDIO_CLOCKCTRL_CLKSTABLE_Msk      (0x2UL)                   /*!< CLKSTABLE (Bitfield-Mask: 0x01)                       */
44105 #define SDIO_CLOCKCTRL_CLKEN_Pos          (0UL)                     /*!< CLKEN (Bit 0)                                         */
44106 #define SDIO_CLOCKCTRL_CLKEN_Msk          (0x1UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
44107 /* ========================================================  INTSTAT  ======================================================== */
44108 #define SDIO_INTSTAT_VNDERRSTAT_Pos       (29UL)                    /*!< VNDERRSTAT (Bit 29)                                   */
44109 #define SDIO_INTSTAT_VNDERRSTAT_Msk       (0xe0000000UL)            /*!< VNDERRSTAT (Bitfield-Mask: 0x07)                      */
44110 #define SDIO_INTSTAT_TGTRESPERR_Pos       (28UL)                    /*!< TGTRESPERR (Bit 28)                                   */
44111 #define SDIO_INTSTAT_TGTRESPERR_Msk       (0x10000000UL)            /*!< TGTRESPERR (Bitfield-Mask: 0x01)                      */
44112 #define SDIO_INTSTAT_ADMAERROR_Pos        (25UL)                    /*!< ADMAERROR (Bit 25)                                    */
44113 #define SDIO_INTSTAT_ADMAERROR_Msk        (0x2000000UL)             /*!< ADMAERROR (Bitfield-Mask: 0x01)                       */
44114 #define SDIO_INTSTAT_AUTOCMDERROR_Pos     (24UL)                    /*!< AUTOCMDERROR (Bit 24)                                 */
44115 #define SDIO_INTSTAT_AUTOCMDERROR_Msk     (0x1000000UL)             /*!< AUTOCMDERROR (Bitfield-Mask: 0x01)                    */
44116 #define SDIO_INTSTAT_CURRENTLIMITERROR_Pos (23UL)                   /*!< CURRENTLIMITERROR (Bit 23)                            */
44117 #define SDIO_INTSTAT_CURRENTLIMITERROR_Msk (0x800000UL)             /*!< CURRENTLIMITERROR (Bitfield-Mask: 0x01)               */
44118 #define SDIO_INTSTAT_DATAENDBITERROR_Pos  (22UL)                    /*!< DATAENDBITERROR (Bit 22)                              */
44119 #define SDIO_INTSTAT_DATAENDBITERROR_Msk  (0x400000UL)              /*!< DATAENDBITERROR (Bitfield-Mask: 0x01)                 */
44120 #define SDIO_INTSTAT_DATACRCERROR_Pos     (21UL)                    /*!< DATACRCERROR (Bit 21)                                 */
44121 #define SDIO_INTSTAT_DATACRCERROR_Msk     (0x200000UL)              /*!< DATACRCERROR (Bitfield-Mask: 0x01)                    */
44122 #define SDIO_INTSTAT_DATATIMEOUTERROR_Pos (20UL)                    /*!< DATATIMEOUTERROR (Bit 20)                             */
44123 #define SDIO_INTSTAT_DATATIMEOUTERROR_Msk (0x100000UL)              /*!< DATATIMEOUTERROR (Bitfield-Mask: 0x01)                */
44124 #define SDIO_INTSTAT_COMMANDINDEXERROR_Pos (19UL)                   /*!< COMMANDINDEXERROR (Bit 19)                            */
44125 #define SDIO_INTSTAT_COMMANDINDEXERROR_Msk (0x80000UL)              /*!< COMMANDINDEXERROR (Bitfield-Mask: 0x01)               */
44126 #define SDIO_INTSTAT_COMMANDENDBITERROR_Pos (18UL)                  /*!< COMMANDENDBITERROR (Bit 18)                           */
44127 #define SDIO_INTSTAT_COMMANDENDBITERROR_Msk (0x40000UL)             /*!< COMMANDENDBITERROR (Bitfield-Mask: 0x01)              */
44128 #define SDIO_INTSTAT_COMMANDCRCERROR_Pos  (17UL)                    /*!< COMMANDCRCERROR (Bit 17)                              */
44129 #define SDIO_INTSTAT_COMMANDCRCERROR_Msk  (0x20000UL)               /*!< COMMANDCRCERROR (Bitfield-Mask: 0x01)                 */
44130 #define SDIO_INTSTAT_COMMANDTIMEOUTERROR_Pos (16UL)                 /*!< COMMANDTIMEOUTERROR (Bit 16)                          */
44131 #define SDIO_INTSTAT_COMMANDTIMEOUTERROR_Msk (0x10000UL)            /*!< COMMANDTIMEOUTERROR (Bitfield-Mask: 0x01)             */
44132 #define SDIO_INTSTAT_ERRORINTERRUPT_Pos   (15UL)                    /*!< ERRORINTERRUPT (Bit 15)                               */
44133 #define SDIO_INTSTAT_ERRORINTERRUPT_Msk   (0x8000UL)                /*!< ERRORINTERRUPT (Bitfield-Mask: 0x01)                  */
44134 #define SDIO_INTSTAT_BOOTTERMINATE_Pos    (14UL)                    /*!< BOOTTERMINATE (Bit 14)                                */
44135 #define SDIO_INTSTAT_BOOTTERMINATE_Msk    (0x4000UL)                /*!< BOOTTERMINATE (Bitfield-Mask: 0x01)                   */
44136 #define SDIO_INTSTAT_BOOTACKRCV_Pos       (13UL)                    /*!< BOOTACKRCV (Bit 13)                                   */
44137 #define SDIO_INTSTAT_BOOTACKRCV_Msk       (0x2000UL)                /*!< BOOTACKRCV (Bitfield-Mask: 0x01)                      */
44138 #define SDIO_INTSTAT_RETUNINGEVENT_Pos    (12UL)                    /*!< RETUNINGEVENT (Bit 12)                                */
44139 #define SDIO_INTSTAT_RETUNINGEVENT_Msk    (0x1000UL)                /*!< RETUNINGEVENT (Bitfield-Mask: 0x01)                   */
44140 #define SDIO_INTSTAT_INTC_Pos             (11UL)                    /*!< INTC (Bit 11)                                         */
44141 #define SDIO_INTSTAT_INTC_Msk             (0x800UL)                 /*!< INTC (Bitfield-Mask: 0x01)                            */
44142 #define SDIO_INTSTAT_INTB_Pos             (10UL)                    /*!< INTB (Bit 10)                                         */
44143 #define SDIO_INTSTAT_INTB_Msk             (0x400UL)                 /*!< INTB (Bitfield-Mask: 0x01)                            */
44144 #define SDIO_INTSTAT_INTA_Pos             (9UL)                     /*!< INTA (Bit 9)                                          */
44145 #define SDIO_INTSTAT_INTA_Msk             (0x200UL)                 /*!< INTA (Bitfield-Mask: 0x01)                            */
44146 #define SDIO_INTSTAT_CARDINTERRUPT_Pos    (8UL)                     /*!< CARDINTERRUPT (Bit 8)                                 */
44147 #define SDIO_INTSTAT_CARDINTERRUPT_Msk    (0x100UL)                 /*!< CARDINTERRUPT (Bitfield-Mask: 0x01)                   */
44148 #define SDIO_INTSTAT_CARDREMOVAL_Pos      (7UL)                     /*!< CARDREMOVAL (Bit 7)                                   */
44149 #define SDIO_INTSTAT_CARDREMOVAL_Msk      (0x80UL)                  /*!< CARDREMOVAL (Bitfield-Mask: 0x01)                     */
44150 #define SDIO_INTSTAT_CARDINSERTION_Pos    (6UL)                     /*!< CARDINSERTION (Bit 6)                                 */
44151 #define SDIO_INTSTAT_CARDINSERTION_Msk    (0x40UL)                  /*!< CARDINSERTION (Bitfield-Mask: 0x01)                   */
44152 #define SDIO_INTSTAT_BUFFERREADREADY_Pos  (5UL)                     /*!< BUFFERREADREADY (Bit 5)                               */
44153 #define SDIO_INTSTAT_BUFFERREADREADY_Msk  (0x20UL)                  /*!< BUFFERREADREADY (Bitfield-Mask: 0x01)                 */
44154 #define SDIO_INTSTAT_BUFFERWRITEREADY_Pos (4UL)                     /*!< BUFFERWRITEREADY (Bit 4)                              */
44155 #define SDIO_INTSTAT_BUFFERWRITEREADY_Msk (0x10UL)                  /*!< BUFFERWRITEREADY (Bitfield-Mask: 0x01)                */
44156 #define SDIO_INTSTAT_DMAINTERRUPT_Pos     (3UL)                     /*!< DMAINTERRUPT (Bit 3)                                  */
44157 #define SDIO_INTSTAT_DMAINTERRUPT_Msk     (0x8UL)                   /*!< DMAINTERRUPT (Bitfield-Mask: 0x01)                    */
44158 #define SDIO_INTSTAT_BLOCKGAPEVENT_Pos    (2UL)                     /*!< BLOCKGAPEVENT (Bit 2)                                 */
44159 #define SDIO_INTSTAT_BLOCKGAPEVENT_Msk    (0x4UL)                   /*!< BLOCKGAPEVENT (Bitfield-Mask: 0x01)                   */
44160 #define SDIO_INTSTAT_TRANSFERCOMPLETE_Pos (1UL)                     /*!< TRANSFERCOMPLETE (Bit 1)                              */
44161 #define SDIO_INTSTAT_TRANSFERCOMPLETE_Msk (0x2UL)                   /*!< TRANSFERCOMPLETE (Bitfield-Mask: 0x01)                */
44162 #define SDIO_INTSTAT_COMMANDCOMPLETE_Pos  (0UL)                     /*!< COMMANDCOMPLETE (Bit 0)                               */
44163 #define SDIO_INTSTAT_COMMANDCOMPLETE_Msk  (0x1UL)                   /*!< COMMANDCOMPLETE (Bitfield-Mask: 0x01)                 */
44164 /* =======================================================  INTENABLE  ======================================================= */
44165 #define SDIO_INTENABLE_VENDORSPECIFICERRORSTATUSENABLE_Pos (29UL)   /*!< VENDORSPECIFICERRORSTATUSENABLE (Bit 29)              */
44166 #define SDIO_INTENABLE_VENDORSPECIFICERRORSTATUSENABLE_Msk (0xe0000000UL) /*!< VENDORSPECIFICERRORSTATUSENABLE (Bitfield-Mask: 0x07) */
44167 #define SDIO_INTENABLE_TGTRESPERRHOSTERRSTATEN_Pos (28UL)           /*!< TGTRESPERRHOSTERRSTATEN (Bit 28)                      */
44168 #define SDIO_INTENABLE_TGTRESPERRHOSTERRSTATEN_Msk (0x10000000UL)   /*!< TGTRESPERRHOSTERRSTATEN (Bitfield-Mask: 0x01)         */
44169 #define SDIO_INTENABLE_TUNINGERRORSTATUS_Pos (26UL)                 /*!< TUNINGERRORSTATUS (Bit 26)                            */
44170 #define SDIO_INTENABLE_TUNINGERRORSTATUS_Msk (0x4000000UL)          /*!< TUNINGERRORSTATUS (Bitfield-Mask: 0x01)               */
44171 #define SDIO_INTENABLE_ADMAERRORSTATUSENABLE_Pos (25UL)             /*!< ADMAERRORSTATUSENABLE (Bit 25)                        */
44172 #define SDIO_INTENABLE_ADMAERRORSTATUSENABLE_Msk (0x2000000UL)      /*!< ADMAERRORSTATUSENABLE (Bitfield-Mask: 0x01)           */
44173 #define SDIO_INTENABLE_AUTOCMD12ERRORSTATUSENABLE_Pos (24UL)        /*!< AUTOCMD12ERRORSTATUSENABLE (Bit 24)                   */
44174 #define SDIO_INTENABLE_AUTOCMD12ERRORSTATUSENABLE_Msk (0x1000000UL) /*!< AUTOCMD12ERRORSTATUSENABLE (Bitfield-Mask: 0x01)      */
44175 #define SDIO_INTENABLE_CURRENTLIMITERRORSTATUSENABLE_Pos (23UL)     /*!< CURRENTLIMITERRORSTATUSENABLE (Bit 23)                */
44176 #define SDIO_INTENABLE_CURRENTLIMITERRORSTATUSENABLE_Msk (0x800000UL) /*!< CURRENTLIMITERRORSTATUSENABLE (Bitfield-Mask: 0x01) */
44177 #define SDIO_INTENABLE_DATAENDBITERRORSTATUSENABLE_Pos (22UL)       /*!< DATAENDBITERRORSTATUSENABLE (Bit 22)                  */
44178 #define SDIO_INTENABLE_DATAENDBITERRORSTATUSENABLE_Msk (0x400000UL) /*!< DATAENDBITERRORSTATUSENABLE (Bitfield-Mask: 0x01)     */
44179 #define SDIO_INTENABLE_DATACRCERRORSTATUSENABLE_Pos (21UL)          /*!< DATACRCERRORSTATUSENABLE (Bit 21)                     */
44180 #define SDIO_INTENABLE_DATACRCERRORSTATUSENABLE_Msk (0x200000UL)    /*!< DATACRCERRORSTATUSENABLE (Bitfield-Mask: 0x01)        */
44181 #define SDIO_INTENABLE_DATATIMEOUTERRORSTATUSENABLE_Pos (20UL)      /*!< DATATIMEOUTERRORSTATUSENABLE (Bit 20)                 */
44182 #define SDIO_INTENABLE_DATATIMEOUTERRORSTATUSENABLE_Msk (0x100000UL) /*!< DATATIMEOUTERRORSTATUSENABLE (Bitfield-Mask: 0x01)   */
44183 #define SDIO_INTENABLE_COMMANDINDEXERRORSTATUSENABLE_Pos (19UL)     /*!< COMMANDINDEXERRORSTATUSENABLE (Bit 19)                */
44184 #define SDIO_INTENABLE_COMMANDINDEXERRORSTATUSENABLE_Msk (0x80000UL) /*!< COMMANDINDEXERRORSTATUSENABLE (Bitfield-Mask: 0x01)  */
44185 #define SDIO_INTENABLE_COMMANDENDBITERRORSTATUSENABLE_Pos (18UL)    /*!< COMMANDENDBITERRORSTATUSENABLE (Bit 18)               */
44186 #define SDIO_INTENABLE_COMMANDENDBITERRORSTATUSENABLE_Msk (0x40000UL) /*!< COMMANDENDBITERRORSTATUSENABLE (Bitfield-Mask: 0x01) */
44187 #define SDIO_INTENABLE_COMMANDCRCERRORSTATUSENABLE_Pos (17UL)       /*!< COMMANDCRCERRORSTATUSENABLE (Bit 17)                  */
44188 #define SDIO_INTENABLE_COMMANDCRCERRORSTATUSENABLE_Msk (0x20000UL)  /*!< COMMANDCRCERRORSTATUSENABLE (Bitfield-Mask: 0x01)     */
44189 #define SDIO_INTENABLE_COMMANDTIMEOUTERRORSTATUSENABLE_Pos (16UL)   /*!< COMMANDTIMEOUTERRORSTATUSENABLE (Bit 16)              */
44190 #define SDIO_INTENABLE_COMMANDTIMEOUTERRORSTATUSENABLE_Msk (0x10000UL) /*!< COMMANDTIMEOUTERRORSTATUSENABLE (Bitfield-Mask: 0x01) */
44191 #define SDIO_INTENABLE_FIXEDTO0_Pos       (15UL)                    /*!< FIXEDTO0 (Bit 15)                                     */
44192 #define SDIO_INTENABLE_FIXEDTO0_Msk       (0x8000UL)                /*!< FIXEDTO0 (Bitfield-Mask: 0x01)                        */
44193 #define SDIO_INTENABLE_BOOTTERMINATE_Pos  (14UL)                    /*!< BOOTTERMINATE (Bit 14)                                */
44194 #define SDIO_INTENABLE_BOOTTERMINATE_Msk  (0x4000UL)                /*!< BOOTTERMINATE (Bitfield-Mask: 0x01)                   */
44195 #define SDIO_INTENABLE_BOOTACKRCVENABLE_Pos (13UL)                  /*!< BOOTACKRCVENABLE (Bit 13)                             */
44196 #define SDIO_INTENABLE_BOOTACKRCVENABLE_Msk (0x2000UL)              /*!< BOOTACKRCVENABLE (Bitfield-Mask: 0x01)                */
44197 #define SDIO_INTENABLE_RETUNINGEVENTSTATUSENABLE_Pos (12UL)         /*!< RETUNINGEVENTSTATUSENABLE (Bit 12)                    */
44198 #define SDIO_INTENABLE_RETUNINGEVENTSTATUSENABLE_Msk (0x1000UL)     /*!< RETUNINGEVENTSTATUSENABLE (Bitfield-Mask: 0x01)       */
44199 #define SDIO_INTENABLE_INTCSTATUSENABLE_Pos (11UL)                  /*!< INTCSTATUSENABLE (Bit 11)                             */
44200 #define SDIO_INTENABLE_INTCSTATUSENABLE_Msk (0x800UL)               /*!< INTCSTATUSENABLE (Bitfield-Mask: 0x01)                */
44201 #define SDIO_INTENABLE_INTBSTATUSENABLE_Pos (10UL)                  /*!< INTBSTATUSENABLE (Bit 10)                             */
44202 #define SDIO_INTENABLE_INTBSTATUSENABLE_Msk (0x400UL)               /*!< INTBSTATUSENABLE (Bitfield-Mask: 0x01)                */
44203 #define SDIO_INTENABLE_INTASTATUSENABLE_Pos (9UL)                   /*!< INTASTATUSENABLE (Bit 9)                              */
44204 #define SDIO_INTENABLE_INTASTATUSENABLE_Msk (0x200UL)               /*!< INTASTATUSENABLE (Bitfield-Mask: 0x01)                */
44205 #define SDIO_INTENABLE_CARDINTERRUPTSTATUSENABLE_Pos (8UL)          /*!< CARDINTERRUPTSTATUSENABLE (Bit 8)                     */
44206 #define SDIO_INTENABLE_CARDINTERRUPTSTATUSENABLE_Msk (0x100UL)      /*!< CARDINTERRUPTSTATUSENABLE (Bitfield-Mask: 0x01)       */
44207 #define SDIO_INTENABLE_CARDREMOVALSTATUSENABLE_Pos (7UL)            /*!< CARDREMOVALSTATUSENABLE (Bit 7)                       */
44208 #define SDIO_INTENABLE_CARDREMOVALSTATUSENABLE_Msk (0x80UL)         /*!< CARDREMOVALSTATUSENABLE (Bitfield-Mask: 0x01)         */
44209 #define SDIO_INTENABLE_CARDINSERTIONSTATUSENABLE_Pos (6UL)          /*!< CARDINSERTIONSTATUSENABLE (Bit 6)                     */
44210 #define SDIO_INTENABLE_CARDINSERTIONSTATUSENABLE_Msk (0x40UL)       /*!< CARDINSERTIONSTATUSENABLE (Bitfield-Mask: 0x01)       */
44211 #define SDIO_INTENABLE_BUFFERREADREADYSTATUSENABLE_Pos (5UL)        /*!< BUFFERREADREADYSTATUSENABLE (Bit 5)                   */
44212 #define SDIO_INTENABLE_BUFFERREADREADYSTATUSENABLE_Msk (0x20UL)     /*!< BUFFERREADREADYSTATUSENABLE (Bitfield-Mask: 0x01)     */
44213 #define SDIO_INTENABLE_BUFFERWRITEREADYSTATUSENABLE_Pos (4UL)       /*!< BUFFERWRITEREADYSTATUSENABLE (Bit 4)                  */
44214 #define SDIO_INTENABLE_BUFFERWRITEREADYSTATUSENABLE_Msk (0x10UL)    /*!< BUFFERWRITEREADYSTATUSENABLE (Bitfield-Mask: 0x01)    */
44215 #define SDIO_INTENABLE_DMAINTERRUPTSTATUSENABLE_Pos (3UL)           /*!< DMAINTERRUPTSTATUSENABLE (Bit 3)                      */
44216 #define SDIO_INTENABLE_DMAINTERRUPTSTATUSENABLE_Msk (0x8UL)         /*!< DMAINTERRUPTSTATUSENABLE (Bitfield-Mask: 0x01)        */
44217 #define SDIO_INTENABLE_BLOCKGAPEVENTSTATUSENABLE_Pos (2UL)          /*!< BLOCKGAPEVENTSTATUSENABLE (Bit 2)                     */
44218 #define SDIO_INTENABLE_BLOCKGAPEVENTSTATUSENABLE_Msk (0x4UL)        /*!< BLOCKGAPEVENTSTATUSENABLE (Bitfield-Mask: 0x01)       */
44219 #define SDIO_INTENABLE_TRANSFERCOMPLETESTATUSENABLE_Pos (1UL)       /*!< TRANSFERCOMPLETESTATUSENABLE (Bit 1)                  */
44220 #define SDIO_INTENABLE_TRANSFERCOMPLETESTATUSENABLE_Msk (0x2UL)     /*!< TRANSFERCOMPLETESTATUSENABLE (Bitfield-Mask: 0x01)    */
44221 #define SDIO_INTENABLE_COMMANDCOMPLETESTATUSENABLE_Pos (0UL)        /*!< COMMANDCOMPLETESTATUSENABLE (Bit 0)                   */
44222 #define SDIO_INTENABLE_COMMANDCOMPLETESTATUSENABLE_Msk (0x1UL)      /*!< COMMANDCOMPLETESTATUSENABLE (Bitfield-Mask: 0x01)     */
44223 /* ========================================================  INTSIG  ========================================================= */
44224 #define SDIO_INTSIG_VNDERREN_Pos          (29UL)                    /*!< VNDERREN (Bit 29)                                     */
44225 #define SDIO_INTSIG_VNDERREN_Msk          (0xe0000000UL)            /*!< VNDERREN (Bitfield-Mask: 0x07)                        */
44226 #define SDIO_INTSIG_TGTRESPEN_Pos         (28UL)                    /*!< TGTRESPEN (Bit 28)                                    */
44227 #define SDIO_INTSIG_TGTRESPEN_Msk         (0x10000000UL)            /*!< TGTRESPEN (Bitfield-Mask: 0x01)                       */
44228 #define SDIO_INTSIG_TUNINGERREN_Pos       (26UL)                    /*!< TUNINGERREN (Bit 26)                                  */
44229 #define SDIO_INTSIG_TUNINGERREN_Msk       (0x4000000UL)             /*!< TUNINGERREN (Bitfield-Mask: 0x01)                     */
44230 #define SDIO_INTSIG_ADMAERREN_Pos         (25UL)                    /*!< ADMAERREN (Bit 25)                                    */
44231 #define SDIO_INTSIG_ADMAERREN_Msk         (0x2000000UL)             /*!< ADMAERREN (Bitfield-Mask: 0x01)                       */
44232 #define SDIO_INTSIG_AUTOCMD12ERREN_Pos    (24UL)                    /*!< AUTOCMD12ERREN (Bit 24)                               */
44233 #define SDIO_INTSIG_AUTOCMD12ERREN_Msk    (0x1000000UL)             /*!< AUTOCMD12ERREN (Bitfield-Mask: 0x01)                  */
44234 #define SDIO_INTSIG_CURRLMTERREN_Pos      (23UL)                    /*!< CURRLMTERREN (Bit 23)                                 */
44235 #define SDIO_INTSIG_CURRLMTERREN_Msk      (0x800000UL)              /*!< CURRLMTERREN (Bitfield-Mask: 0x01)                    */
44236 #define SDIO_INTSIG_DATAENDERREN_Pos      (22UL)                    /*!< DATAENDERREN (Bit 22)                                 */
44237 #define SDIO_INTSIG_DATAENDERREN_Msk      (0x400000UL)              /*!< DATAENDERREN (Bitfield-Mask: 0x01)                    */
44238 #define SDIO_INTSIG_DATACRCERREN_Pos      (21UL)                    /*!< DATACRCERREN (Bit 21)                                 */
44239 #define SDIO_INTSIG_DATACRCERREN_Msk      (0x200000UL)              /*!< DATACRCERREN (Bitfield-Mask: 0x01)                    */
44240 #define SDIO_INTSIG_DATATOERROREN_Pos     (20UL)                    /*!< DATATOERROREN (Bit 20)                                */
44241 #define SDIO_INTSIG_DATATOERROREN_Msk     (0x100000UL)              /*!< DATATOERROREN (Bitfield-Mask: 0x01)                   */
44242 #define SDIO_INTSIG_CMDIDXERREN_Pos       (19UL)                    /*!< CMDIDXERREN (Bit 19)                                  */
44243 #define SDIO_INTSIG_CMDIDXERREN_Msk       (0x80000UL)               /*!< CMDIDXERREN (Bitfield-Mask: 0x01)                     */
44244 #define SDIO_INTSIG_CMDENDBITERREN_Pos    (18UL)                    /*!< CMDENDBITERREN (Bit 18)                               */
44245 #define SDIO_INTSIG_CMDENDBITERREN_Msk    (0x40000UL)               /*!< CMDENDBITERREN (Bitfield-Mask: 0x01)                  */
44246 #define SDIO_INTSIG_CMDCRCERREN_Pos       (17UL)                    /*!< CMDCRCERREN (Bit 17)                                  */
44247 #define SDIO_INTSIG_CMDCRCERREN_Msk       (0x20000UL)               /*!< CMDCRCERREN (Bitfield-Mask: 0x01)                     */
44248 #define SDIO_INTSIG_CMDTOERREN_Pos        (16UL)                    /*!< CMDTOERREN (Bit 16)                                   */
44249 #define SDIO_INTSIG_CMDTOERREN_Msk        (0x10000UL)               /*!< CMDTOERREN (Bitfield-Mask: 0x01)                      */
44250 #define SDIO_INTSIG_FIXED0_Pos            (15UL)                    /*!< FIXED0 (Bit 15)                                       */
44251 #define SDIO_INTSIG_FIXED0_Msk            (0x8000UL)                /*!< FIXED0 (Bitfield-Mask: 0x01)                          */
44252 #define SDIO_INTSIG_BOOTTERM_Pos          (14UL)                    /*!< BOOTTERM (Bit 14)                                     */
44253 #define SDIO_INTSIG_BOOTTERM_Msk          (0x4000UL)                /*!< BOOTTERM (Bitfield-Mask: 0x01)                        */
44254 #define SDIO_INTSIG_BOOTACKEN_Pos         (13UL)                    /*!< BOOTACKEN (Bit 13)                                    */
44255 #define SDIO_INTSIG_BOOTACKEN_Msk         (0x2000UL)                /*!< BOOTACKEN (Bitfield-Mask: 0x01)                       */
44256 #define SDIO_INTSIG_RETUNEEVENTEN_Pos     (12UL)                    /*!< RETUNEEVENTEN (Bit 12)                                */
44257 #define SDIO_INTSIG_RETUNEEVENTEN_Msk     (0x1000UL)                /*!< RETUNEEVENTEN (Bitfield-Mask: 0x01)                   */
44258 #define SDIO_INTSIG_INTCEN_Pos            (11UL)                    /*!< INTCEN (Bit 11)                                       */
44259 #define SDIO_INTSIG_INTCEN_Msk            (0x800UL)                 /*!< INTCEN (Bitfield-Mask: 0x01)                          */
44260 #define SDIO_INTSIG_INTBEN_Pos            (10UL)                    /*!< INTBEN (Bit 10)                                       */
44261 #define SDIO_INTSIG_INTBEN_Msk            (0x400UL)                 /*!< INTBEN (Bitfield-Mask: 0x01)                          */
44262 #define SDIO_INTSIG_INTAEN_Pos            (9UL)                     /*!< INTAEN (Bit 9)                                        */
44263 #define SDIO_INTSIG_INTAEN_Msk            (0x200UL)                 /*!< INTAEN (Bitfield-Mask: 0x01)                          */
44264 #define SDIO_INTSIG_CARDINTEN_Pos         (8UL)                     /*!< CARDINTEN (Bit 8)                                     */
44265 #define SDIO_INTSIG_CARDINTEN_Msk         (0x100UL)                 /*!< CARDINTEN (Bitfield-Mask: 0x01)                       */
44266 #define SDIO_INTSIG_CARDREMOVALEN_Pos     (7UL)                     /*!< CARDREMOVALEN (Bit 7)                                 */
44267 #define SDIO_INTSIG_CARDREMOVALEN_Msk     (0x80UL)                  /*!< CARDREMOVALEN (Bitfield-Mask: 0x01)                   */
44268 #define SDIO_INTSIG_CARDINSERTEN_Pos      (6UL)                     /*!< CARDINSERTEN (Bit 6)                                  */
44269 #define SDIO_INTSIG_CARDINSERTEN_Msk      (0x40UL)                  /*!< CARDINSERTEN (Bitfield-Mask: 0x01)                    */
44270 #define SDIO_INTSIG_BUFFERRDEN_Pos        (5UL)                     /*!< BUFFERRDEN (Bit 5)                                    */
44271 #define SDIO_INTSIG_BUFFERRDEN_Msk        (0x20UL)                  /*!< BUFFERRDEN (Bitfield-Mask: 0x01)                      */
44272 #define SDIO_INTSIG_BUFFERWREN_Pos        (4UL)                     /*!< BUFFERWREN (Bit 4)                                    */
44273 #define SDIO_INTSIG_BUFFERWREN_Msk        (0x10UL)                  /*!< BUFFERWREN (Bitfield-Mask: 0x01)                      */
44274 #define SDIO_INTSIG_DMAINTEN_Pos          (3UL)                     /*!< DMAINTEN (Bit 3)                                      */
44275 #define SDIO_INTSIG_DMAINTEN_Msk          (0x8UL)                   /*!< DMAINTEN (Bitfield-Mask: 0x01)                        */
44276 #define SDIO_INTSIG_BLOCKGAPEN_Pos        (2UL)                     /*!< BLOCKGAPEN (Bit 2)                                    */
44277 #define SDIO_INTSIG_BLOCKGAPEN_Msk        (0x4UL)                   /*!< BLOCKGAPEN (Bitfield-Mask: 0x01)                      */
44278 #define SDIO_INTSIG_XFERCMPEN_Pos         (1UL)                     /*!< XFERCMPEN (Bit 1)                                     */
44279 #define SDIO_INTSIG_XFERCMPEN_Msk         (0x2UL)                   /*!< XFERCMPEN (Bitfield-Mask: 0x01)                       */
44280 #define SDIO_INTSIG_CMDCMPEN_Pos          (0UL)                     /*!< CMDCMPEN (Bit 0)                                      */
44281 #define SDIO_INTSIG_CMDCMPEN_Msk          (0x1UL)                   /*!< CMDCMPEN (Bitfield-Mask: 0x01)                        */
44282 /* =========================================================  AUTO  ========================================================== */
44283 #define SDIO_AUTO_PRESETEN_Pos            (31UL)                    /*!< PRESETEN (Bit 31)                                     */
44284 #define SDIO_AUTO_PRESETEN_Msk            (0x80000000UL)            /*!< PRESETEN (Bitfield-Mask: 0x01)                        */
44285 #define SDIO_AUTO_ASYNCINTEN_Pos          (30UL)                    /*!< ASYNCINTEN (Bit 30)                                   */
44286 #define SDIO_AUTO_ASYNCINTEN_Msk          (0x40000000UL)            /*!< ASYNCINTEN (Bitfield-Mask: 0x01)                      */
44287 #define SDIO_AUTO_SAMPLCLKSEL_Pos         (23UL)                    /*!< SAMPLCLKSEL (Bit 23)                                  */
44288 #define SDIO_AUTO_SAMPLCLKSEL_Msk         (0x800000UL)              /*!< SAMPLCLKSEL (Bitfield-Mask: 0x01)                     */
44289 #define SDIO_AUTO_STARTTUNING_Pos         (22UL)                    /*!< STARTTUNING (Bit 22)                                  */
44290 #define SDIO_AUTO_STARTTUNING_Msk         (0x400000UL)              /*!< STARTTUNING (Bitfield-Mask: 0x01)                     */
44291 #define SDIO_AUTO_DRVRSTRSEL_Pos          (20UL)                    /*!< DRVRSTRSEL (Bit 20)                                   */
44292 #define SDIO_AUTO_DRVRSTRSEL_Msk          (0x300000UL)              /*!< DRVRSTRSEL (Bitfield-Mask: 0x03)                      */
44293 #define SDIO_AUTO_SIGNALVOLT_Pos          (19UL)                    /*!< SIGNALVOLT (Bit 19)                                   */
44294 #define SDIO_AUTO_SIGNALVOLT_Msk          (0x80000UL)               /*!< SIGNALVOLT (Bitfield-Mask: 0x01)                      */
44295 #define SDIO_AUTO_UHSMODESEL_Pos          (16UL)                    /*!< UHSMODESEL (Bit 16)                                   */
44296 #define SDIO_AUTO_UHSMODESEL_Msk          (0x70000UL)               /*!< UHSMODESEL (Bitfield-Mask: 0x07)                      */
44297 #define SDIO_AUTO_NOTAUTOCMD12ERR_Pos     (7UL)                     /*!< NOTAUTOCMD12ERR (Bit 7)                               */
44298 #define SDIO_AUTO_NOTAUTOCMD12ERR_Msk     (0x80UL)                  /*!< NOTAUTOCMD12ERR (Bitfield-Mask: 0x01)                 */
44299 #define SDIO_AUTO_CMDIDXERR_Pos           (4UL)                     /*!< CMDIDXERR (Bit 4)                                     */
44300 #define SDIO_AUTO_CMDIDXERR_Msk           (0x10UL)                  /*!< CMDIDXERR (Bitfield-Mask: 0x01)                       */
44301 #define SDIO_AUTO_CMDENDERR_Pos           (3UL)                     /*!< CMDENDERR (Bit 3)                                     */
44302 #define SDIO_AUTO_CMDENDERR_Msk           (0x8UL)                   /*!< CMDENDERR (Bitfield-Mask: 0x01)                       */
44303 #define SDIO_AUTO_CMDCRCERR_Pos           (2UL)                     /*!< CMDCRCERR (Bit 2)                                     */
44304 #define SDIO_AUTO_CMDCRCERR_Msk           (0x4UL)                   /*!< CMDCRCERR (Bitfield-Mask: 0x01)                       */
44305 #define SDIO_AUTO_CMDTOERR_Pos            (1UL)                     /*!< CMDTOERR (Bit 1)                                      */
44306 #define SDIO_AUTO_CMDTOERR_Msk            (0x2UL)                   /*!< CMDTOERR (Bitfield-Mask: 0x01)                        */
44307 #define SDIO_AUTO_CMD12NOTEXEC_Pos        (0UL)                     /*!< CMD12NOTEXEC (Bit 0)                                  */
44308 #define SDIO_AUTO_CMD12NOTEXEC_Msk        (0x1UL)                   /*!< CMD12NOTEXEC (Bitfield-Mask: 0x01)                    */
44309 /* =====================================================  CAPABILITIES0  ===================================================== */
44310 #define SDIO_CAPABILITIES0_SLOTTYPE_Pos   (30UL)                    /*!< SLOTTYPE (Bit 30)                                     */
44311 #define SDIO_CAPABILITIES0_SLOTTYPE_Msk   (0xc0000000UL)            /*!< SLOTTYPE (Bitfield-Mask: 0x03)                        */
44312 #define SDIO_CAPABILITIES0_ASYNCINT_Pos   (29UL)                    /*!< ASYNCINT (Bit 29)                                     */
44313 #define SDIO_CAPABILITIES0_ASYNCINT_Msk   (0x20000000UL)            /*!< ASYNCINT (Bitfield-Mask: 0x01)                        */
44314 #define SDIO_CAPABILITIES0_SYSBUS64_Pos   (28UL)                    /*!< SYSBUS64 (Bit 28)                                     */
44315 #define SDIO_CAPABILITIES0_SYSBUS64_Msk   (0x10000000UL)            /*!< SYSBUS64 (Bitfield-Mask: 0x01)                        */
44316 #define SDIO_CAPABILITIES0_VOLT18V_Pos    (26UL)                    /*!< VOLT18V (Bit 26)                                      */
44317 #define SDIO_CAPABILITIES0_VOLT18V_Msk    (0x4000000UL)             /*!< VOLT18V (Bitfield-Mask: 0x01)                         */
44318 #define SDIO_CAPABILITIES0_VOLT30V_Pos    (25UL)                    /*!< VOLT30V (Bit 25)                                      */
44319 #define SDIO_CAPABILITIES0_VOLT30V_Msk    (0x2000000UL)             /*!< VOLT30V (Bitfield-Mask: 0x01)                         */
44320 #define SDIO_CAPABILITIES0_VOLT33V_Pos    (24UL)                    /*!< VOLT33V (Bit 24)                                      */
44321 #define SDIO_CAPABILITIES0_VOLT33V_Msk    (0x1000000UL)             /*!< VOLT33V (Bitfield-Mask: 0x01)                         */
44322 #define SDIO_CAPABILITIES0_SUSPRES_Pos    (23UL)                    /*!< SUSPRES (Bit 23)                                      */
44323 #define SDIO_CAPABILITIES0_SUSPRES_Msk    (0x800000UL)              /*!< SUSPRES (Bitfield-Mask: 0x01)                         */
44324 #define SDIO_CAPABILITIES0_SDMA_Pos       (22UL)                    /*!< SDMA (Bit 22)                                         */
44325 #define SDIO_CAPABILITIES0_SDMA_Msk       (0x400000UL)              /*!< SDMA (Bitfield-Mask: 0x01)                            */
44326 #define SDIO_CAPABILITIES0_HIGHSPEED_Pos  (21UL)                    /*!< HIGHSPEED (Bit 21)                                    */
44327 #define SDIO_CAPABILITIES0_HIGHSPEED_Msk  (0x200000UL)              /*!< HIGHSPEED (Bitfield-Mask: 0x01)                       */
44328 #define SDIO_CAPABILITIES0_ADMA2_Pos      (19UL)                    /*!< ADMA2 (Bit 19)                                        */
44329 #define SDIO_CAPABILITIES0_ADMA2_Msk      (0x80000UL)               /*!< ADMA2 (Bitfield-Mask: 0x01)                           */
44330 #define SDIO_CAPABILITIES0_EXTMEDIA_Pos   (18UL)                    /*!< EXTMEDIA (Bit 18)                                     */
44331 #define SDIO_CAPABILITIES0_EXTMEDIA_Msk   (0x40000UL)               /*!< EXTMEDIA (Bitfield-Mask: 0x01)                        */
44332 #define SDIO_CAPABILITIES0_MAXBLKLEN_Pos  (16UL)                    /*!< MAXBLKLEN (Bit 16)                                    */
44333 #define SDIO_CAPABILITIES0_MAXBLKLEN_Msk  (0x30000UL)               /*!< MAXBLKLEN (Bitfield-Mask: 0x03)                       */
44334 #define SDIO_CAPABILITIES0_SDCLKFREQ_Pos  (8UL)                     /*!< SDCLKFREQ (Bit 8)                                     */
44335 #define SDIO_CAPABILITIES0_SDCLKFREQ_Msk  (0xff00UL)                /*!< SDCLKFREQ (Bitfield-Mask: 0xff)                       */
44336 #define SDIO_CAPABILITIES0_TOCLKUNIT_Pos  (7UL)                     /*!< TOCLKUNIT (Bit 7)                                     */
44337 #define SDIO_CAPABILITIES0_TOCLKUNIT_Msk  (0x80UL)                  /*!< TOCLKUNIT (Bitfield-Mask: 0x01)                       */
44338 #define SDIO_CAPABILITIES0_TOCLKFREQ_Pos  (0UL)                     /*!< TOCLKFREQ (Bit 0)                                     */
44339 #define SDIO_CAPABILITIES0_TOCLKFREQ_Msk  (0x3fUL)                  /*!< TOCLKFREQ (Bitfield-Mask: 0x3f)                       */
44340 /* =====================================================  CAPABILITIES1  ===================================================== */
44341 #define SDIO_CAPABILITIES1_SPIBLOCKMODE_Pos (25UL)                  /*!< SPIBLOCKMODE (Bit 25)                                 */
44342 #define SDIO_CAPABILITIES1_SPIBLOCKMODE_Msk (0x2000000UL)           /*!< SPIBLOCKMODE (Bitfield-Mask: 0x01)                    */
44343 #define SDIO_CAPABILITIES1_SPIMODE_Pos    (24UL)                    /*!< SPIMODE (Bit 24)                                      */
44344 #define SDIO_CAPABILITIES1_SPIMODE_Msk    (0x1000000UL)             /*!< SPIMODE (Bitfield-Mask: 0x01)                         */
44345 #define SDIO_CAPABILITIES1_CLKMULT_Pos    (16UL)                    /*!< CLKMULT (Bit 16)                                      */
44346 #define SDIO_CAPABILITIES1_CLKMULT_Msk    (0xff0000UL)              /*!< CLKMULT (Bitfield-Mask: 0xff)                         */
44347 #define SDIO_CAPABILITIES1_RETUNINGMODES_Pos (14UL)                 /*!< RETUNINGMODES (Bit 14)                                */
44348 #define SDIO_CAPABILITIES1_RETUNINGMODES_Msk (0xc000UL)             /*!< RETUNINGMODES (Bitfield-Mask: 0x03)                   */
44349 #define SDIO_CAPABILITIES1_TUNINGSDR50_Pos (13UL)                   /*!< TUNINGSDR50 (Bit 13)                                  */
44350 #define SDIO_CAPABILITIES1_TUNINGSDR50_Msk (0x2000UL)               /*!< TUNINGSDR50 (Bitfield-Mask: 0x01)                     */
44351 #define SDIO_CAPABILITIES1_RETUNINGTMRCNT_Pos (8UL)                 /*!< RETUNINGTMRCNT (Bit 8)                                */
44352 #define SDIO_CAPABILITIES1_RETUNINGTMRCNT_Msk (0xf00UL)             /*!< RETUNINGTMRCNT (Bitfield-Mask: 0x0f)                  */
44353 #define SDIO_CAPABILITIES1_TYPED_Pos      (6UL)                     /*!< TYPED (Bit 6)                                         */
44354 #define SDIO_CAPABILITIES1_TYPED_Msk      (0x40UL)                  /*!< TYPED (Bitfield-Mask: 0x01)                           */
44355 #define SDIO_CAPABILITIES1_TYPEC_Pos      (5UL)                     /*!< TYPEC (Bit 5)                                         */
44356 #define SDIO_CAPABILITIES1_TYPEC_Msk      (0x20UL)                  /*!< TYPEC (Bitfield-Mask: 0x01)                           */
44357 #define SDIO_CAPABILITIES1_TYPEA_Pos      (4UL)                     /*!< TYPEA (Bit 4)                                         */
44358 #define SDIO_CAPABILITIES1_TYPEA_Msk      (0x10UL)                  /*!< TYPEA (Bitfield-Mask: 0x01)                           */
44359 #define SDIO_CAPABILITIES1_DDR50_Pos      (2UL)                     /*!< DDR50 (Bit 2)                                         */
44360 #define SDIO_CAPABILITIES1_DDR50_Msk      (0x4UL)                   /*!< DDR50 (Bitfield-Mask: 0x01)                           */
44361 #define SDIO_CAPABILITIES1_SDR104_Pos     (1UL)                     /*!< SDR104 (Bit 1)                                        */
44362 #define SDIO_CAPABILITIES1_SDR104_Msk     (0x2UL)                   /*!< SDR104 (Bitfield-Mask: 0x01)                          */
44363 #define SDIO_CAPABILITIES1_SDR50_Pos      (0UL)                     /*!< SDR50 (Bit 0)                                         */
44364 #define SDIO_CAPABILITIES1_SDR50_Msk      (0x1UL)                   /*!< SDR50 (Bitfield-Mask: 0x01)                           */
44365 /* =======================================================  MAXIMUM0  ======================================================== */
44366 #define SDIO_MAXIMUM0_ALLBITSRSVD_Pos     (0UL)                     /*!< ALLBITSRSVD (Bit 0)                                   */
44367 #define SDIO_MAXIMUM0_ALLBITSRSVD_Msk     (0xffffffffUL)            /*!< ALLBITSRSVD (Bitfield-Mask: 0xffffffff)               */
44368 /* =======================================================  MAXIMUM1  ======================================================== */
44369 #define SDIO_MAXIMUM1_MAXCURR18V_Pos      (16UL)                    /*!< MAXCURR18V (Bit 16)                                   */
44370 #define SDIO_MAXIMUM1_MAXCURR18V_Msk      (0xff0000UL)              /*!< MAXCURR18V (Bitfield-Mask: 0xff)                      */
44371 #define SDIO_MAXIMUM1_MAXCURR30V_Pos      (8UL)                     /*!< MAXCURR30V (Bit 8)                                    */
44372 #define SDIO_MAXIMUM1_MAXCURR30V_Msk      (0xff00UL)                /*!< MAXCURR30V (Bitfield-Mask: 0xff)                      */
44373 #define SDIO_MAXIMUM1_MAXCURR33V_Pos      (0UL)                     /*!< MAXCURR33V (Bit 0)                                    */
44374 #define SDIO_MAXIMUM1_MAXCURR33V_Msk      (0xffUL)                  /*!< MAXCURR33V (Bitfield-Mask: 0xff)                      */
44375 /* =========================================================  FORCE  ========================================================= */
44376 #define SDIO_FORCE_FORCEADMAERR_Pos       (25UL)                    /*!< FORCEADMAERR (Bit 25)                                 */
44377 #define SDIO_FORCE_FORCEADMAERR_Msk       (0x2000000UL)             /*!< FORCEADMAERR (Bitfield-Mask: 0x01)                    */
44378 #define SDIO_FORCE_FORCEACMDERR_Pos       (24UL)                    /*!< FORCEACMDERR (Bit 24)                                 */
44379 #define SDIO_FORCE_FORCEACMDERR_Msk       (0x1000000UL)             /*!< FORCEACMDERR (Bitfield-Mask: 0x01)                    */
44380 #define SDIO_FORCE_FORCECURRLIMITERR_Pos  (23UL)                    /*!< FORCECURRLIMITERR (Bit 23)                            */
44381 #define SDIO_FORCE_FORCECURRLIMITERR_Msk  (0x800000UL)              /*!< FORCECURRLIMITERR (Bitfield-Mask: 0x01)               */
44382 #define SDIO_FORCE_FORCEDATAENDERR_Pos    (22UL)                    /*!< FORCEDATAENDERR (Bit 22)                              */
44383 #define SDIO_FORCE_FORCEDATAENDERR_Msk    (0x400000UL)              /*!< FORCEDATAENDERR (Bitfield-Mask: 0x01)                 */
44384 #define SDIO_FORCE_FORCEDATACRCERR_Pos    (21UL)                    /*!< FORCEDATACRCERR (Bit 21)                              */
44385 #define SDIO_FORCE_FORCEDATACRCERR_Msk    (0x200000UL)              /*!< FORCEDATACRCERR (Bitfield-Mask: 0x01)                 */
44386 #define SDIO_FORCE_FORCEDATATOERR_Pos     (20UL)                    /*!< FORCEDATATOERR (Bit 20)                               */
44387 #define SDIO_FORCE_FORCEDATATOERR_Msk     (0x100000UL)              /*!< FORCEDATATOERR (Bitfield-Mask: 0x01)                  */
44388 #define SDIO_FORCE_FORCECMDIDXERR_Pos     (19UL)                    /*!< FORCECMDIDXERR (Bit 19)                               */
44389 #define SDIO_FORCE_FORCECMDIDXERR_Msk     (0x80000UL)               /*!< FORCECMDIDXERR (Bitfield-Mask: 0x01)                  */
44390 #define SDIO_FORCE_FORCECMDENDERR_Pos     (18UL)                    /*!< FORCECMDENDERR (Bit 18)                               */
44391 #define SDIO_FORCE_FORCECMDENDERR_Msk     (0x40000UL)               /*!< FORCECMDENDERR (Bitfield-Mask: 0x01)                  */
44392 #define SDIO_FORCE_FORCECMDCRCERR_Pos     (17UL)                    /*!< FORCECMDCRCERR (Bit 17)                               */
44393 #define SDIO_FORCE_FORCECMDCRCERR_Msk     (0x20000UL)               /*!< FORCECMDCRCERR (Bitfield-Mask: 0x01)                  */
44394 #define SDIO_FORCE_FORCECMDTOERR_Pos      (16UL)                    /*!< FORCECMDTOERR (Bit 16)                                */
44395 #define SDIO_FORCE_FORCECMDTOERR_Msk      (0x10000UL)               /*!< FORCECMDTOERR (Bitfield-Mask: 0x01)                   */
44396 #define SDIO_FORCE_FORCEACMDISSUEDERR_Pos (7UL)                     /*!< FORCEACMDISSUEDERR (Bit 7)                            */
44397 #define SDIO_FORCE_FORCEACMDISSUEDERR_Msk (0x80UL)                  /*!< FORCEACMDISSUEDERR (Bitfield-Mask: 0x01)              */
44398 #define SDIO_FORCE_FORCEACMDIDXERR_Pos    (4UL)                     /*!< FORCEACMDIDXERR (Bit 4)                               */
44399 #define SDIO_FORCE_FORCEACMDIDXERR_Msk    (0x10UL)                  /*!< FORCEACMDIDXERR (Bitfield-Mask: 0x01)                 */
44400 #define SDIO_FORCE_FORCEACMDENDERR_Pos    (3UL)                     /*!< FORCEACMDENDERR (Bit 3)                               */
44401 #define SDIO_FORCE_FORCEACMDENDERR_Msk    (0x8UL)                   /*!< FORCEACMDENDERR (Bitfield-Mask: 0x01)                 */
44402 #define SDIO_FORCE_FORCEACMDCRCERR_Pos    (2UL)                     /*!< FORCEACMDCRCERR (Bit 2)                               */
44403 #define SDIO_FORCE_FORCEACMDCRCERR_Msk    (0x4UL)                   /*!< FORCEACMDCRCERR (Bitfield-Mask: 0x01)                 */
44404 #define SDIO_FORCE_FORCEACMDTOERR_Pos     (1UL)                     /*!< FORCEACMDTOERR (Bit 1)                                */
44405 #define SDIO_FORCE_FORCEACMDTOERR_Msk     (0x2UL)                   /*!< FORCEACMDTOERR (Bitfield-Mask: 0x01)                  */
44406 #define SDIO_FORCE_FORCEACMD12NOT_Pos     (0UL)                     /*!< FORCEACMD12NOT (Bit 0)                                */
44407 #define SDIO_FORCE_FORCEACMD12NOT_Msk     (0x1UL)                   /*!< FORCEACMD12NOT (Bitfield-Mask: 0x01)                  */
44408 /* =========================================================  ADMA  ========================================================== */
44409 #define SDIO_ADMA_ADMALENMISMATCHERR_Pos  (2UL)                     /*!< ADMALENMISMATCHERR (Bit 2)                            */
44410 #define SDIO_ADMA_ADMALENMISMATCHERR_Msk  (0x4UL)                   /*!< ADMALENMISMATCHERR (Bitfield-Mask: 0x01)              */
44411 #define SDIO_ADMA_ADMAERRORSTATE_Pos      (0UL)                     /*!< ADMAERRORSTATE (Bit 0)                                */
44412 #define SDIO_ADMA_ADMAERRORSTATE_Msk      (0x3UL)                   /*!< ADMAERRORSTATE (Bitfield-Mask: 0x03)                  */
44413 /* =======================================================  ADMALOWD  ======================================================== */
44414 #define SDIO_ADMALOWD_LOWD_Pos            (0UL)                     /*!< LOWD (Bit 0)                                          */
44415 #define SDIO_ADMALOWD_LOWD_Msk            (0xffffffffUL)            /*!< LOWD (Bitfield-Mask: 0xffffffff)                      */
44416 /* =======================================================  ADMAHIWD  ======================================================== */
44417 #define SDIO_ADMAHIWD_HIWD_Pos            (0UL)                     /*!< HIWD (Bit 0)                                          */
44418 #define SDIO_ADMAHIWD_HIWD_Msk            (0xffffffffUL)            /*!< HIWD (Bitfield-Mask: 0xffffffff)                      */
44419 /* ========================================================  PRESET0  ======================================================== */
44420 #define SDIO_PRESET0_DEFSPDRVRSTRSEL_Pos  (30UL)                    /*!< DEFSPDRVRSTRSEL (Bit 30)                              */
44421 #define SDIO_PRESET0_DEFSPDRVRSTRSEL_Msk  (0xc0000000UL)            /*!< DEFSPDRVRSTRSEL (Bitfield-Mask: 0x03)                 */
44422 #define SDIO_PRESET0_DEFSPCLKGENSEL_Pos   (26UL)                    /*!< DEFSPCLKGENSEL (Bit 26)                               */
44423 #define SDIO_PRESET0_DEFSPCLKGENSEL_Msk   (0x4000000UL)             /*!< DEFSPCLKGENSEL (Bitfield-Mask: 0x01)                  */
44424 #define SDIO_PRESET0_DEFSPSDCLKFREQSEL_Pos (16UL)                   /*!< DEFSPSDCLKFREQSEL (Bit 16)                            */
44425 #define SDIO_PRESET0_DEFSPSDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< DEFSPSDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
44426 #define SDIO_PRESET0_HISPDRVRSTRSEL_Pos   (14UL)                    /*!< HISPDRVRSTRSEL (Bit 14)                               */
44427 #define SDIO_PRESET0_HISPDRVRSTRSEL_Msk   (0xc000UL)                /*!< HISPDRVRSTRSEL (Bitfield-Mask: 0x03)                  */
44428 #define SDIO_PRESET0_HISPCLKGENSEL_Pos    (10UL)                    /*!< HISPCLKGENSEL (Bit 10)                                */
44429 #define SDIO_PRESET0_HISPCLKGENSEL_Msk    (0x400UL)                 /*!< HISPCLKGENSEL (Bitfield-Mask: 0x01)                   */
44430 #define SDIO_PRESET0_HISPSDCLKFREQSEL_Pos (0UL)                     /*!< HISPSDCLKFREQSEL (Bit 0)                              */
44431 #define SDIO_PRESET0_HISPSDCLKFREQSEL_Msk (0x3ffUL)                 /*!< HISPSDCLKFREQSEL (Bitfield-Mask: 0x3ff)               */
44432 /* ========================================================  PRESET1  ======================================================== */
44433 #define SDIO_PRESET1_SDR12DRVRSTRSEL_Pos  (30UL)                    /*!< SDR12DRVRSTRSEL (Bit 30)                              */
44434 #define SDIO_PRESET1_SDR12DRVRSTRSEL_Msk  (0xc0000000UL)            /*!< SDR12DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
44435 #define SDIO_PRESET1_SDR12CLKGENSEL_Pos   (26UL)                    /*!< SDR12CLKGENSEL (Bit 26)                               */
44436 #define SDIO_PRESET1_SDR12CLKGENSEL_Msk   (0x4000000UL)             /*!< SDR12CLKGENSEL (Bitfield-Mask: 0x01)                  */
44437 #define SDIO_PRESET1_SDR12SDCLKFREQSEL_Pos (16UL)                   /*!< SDR12SDCLKFREQSEL (Bit 16)                            */
44438 #define SDIO_PRESET1_SDR12SDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< SDR12SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
44439 #define SDIO_PRESET1_HSDRVRSTRSEL_Pos     (14UL)                    /*!< HSDRVRSTRSEL (Bit 14)                                 */
44440 #define SDIO_PRESET1_HSDRVRSTRSEL_Msk     (0xc000UL)                /*!< HSDRVRSTRSEL (Bitfield-Mask: 0x03)                    */
44441 #define SDIO_PRESET1_HSCLKGENSEL_Pos      (10UL)                    /*!< HSCLKGENSEL (Bit 10)                                  */
44442 #define SDIO_PRESET1_HSCLKGENSEL_Msk      (0x400UL)                 /*!< HSCLKGENSEL (Bitfield-Mask: 0x01)                     */
44443 #define SDIO_PRESET1_HSSDCLKFREQSEL_Pos   (0UL)                     /*!< HSSDCLKFREQSEL (Bit 0)                                */
44444 #define SDIO_PRESET1_HSSDCLKFREQSEL_Msk   (0x3ffUL)                 /*!< HSSDCLKFREQSEL (Bitfield-Mask: 0x3ff)                 */
44445 /* ========================================================  PRESET2  ======================================================== */
44446 #define SDIO_PRESET2_SDR50DRVRSTRSEL_Pos  (30UL)                    /*!< SDR50DRVRSTRSEL (Bit 30)                              */
44447 #define SDIO_PRESET2_SDR50DRVRSTRSEL_Msk  (0xc0000000UL)            /*!< SDR50DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
44448 #define SDIO_PRESET2_SDR50CLKGENSEL_Pos   (26UL)                    /*!< SDR50CLKGENSEL (Bit 26)                               */
44449 #define SDIO_PRESET2_SDR50CLKGENSEL_Msk   (0x4000000UL)             /*!< SDR50CLKGENSEL (Bitfield-Mask: 0x01)                  */
44450 #define SDIO_PRESET2_SDR50SDCLKFREQSEL_Pos (16UL)                   /*!< SDR50SDCLKFREQSEL (Bit 16)                            */
44451 #define SDIO_PRESET2_SDR50SDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< SDR50SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
44452 #define SDIO_PRESET2_SDR25DRVRSTRSEL_Pos  (14UL)                    /*!< SDR25DRVRSTRSEL (Bit 14)                              */
44453 #define SDIO_PRESET2_SDR25DRVRSTRSEL_Msk  (0xc000UL)                /*!< SDR25DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
44454 #define SDIO_PRESET2_SDR25CLKGENSEL_Pos   (10UL)                    /*!< SDR25CLKGENSEL (Bit 10)                               */
44455 #define SDIO_PRESET2_SDR25CLKGENSEL_Msk   (0x400UL)                 /*!< SDR25CLKGENSEL (Bitfield-Mask: 0x01)                  */
44456 #define SDIO_PRESET2_SDR25SDCLKFREQSEL_Pos (0UL)                    /*!< SDR25SDCLKFREQSEL (Bit 0)                             */
44457 #define SDIO_PRESET2_SDR25SDCLKFREQSEL_Msk (0x3ffUL)                /*!< SDR25SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
44458 /* ========================================================  PRESET3  ======================================================== */
44459 #define SDIO_PRESET3_DDR50DRVRSTRSEL_Pos  (30UL)                    /*!< DDR50DRVRSTRSEL (Bit 30)                              */
44460 #define SDIO_PRESET3_DDR50DRVRSTRSEL_Msk  (0xc0000000UL)            /*!< DDR50DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
44461 #define SDIO_PRESET3_DDR50CLKGENSEL_Pos   (26UL)                    /*!< DDR50CLKGENSEL (Bit 26)                               */
44462 #define SDIO_PRESET3_DDR50CLKGENSEL_Msk   (0x4000000UL)             /*!< DDR50CLKGENSEL (Bitfield-Mask: 0x01)                  */
44463 #define SDIO_PRESET3_DDR50SDCLKFREQSEL_Pos (16UL)                   /*!< DDR50SDCLKFREQSEL (Bit 16)                            */
44464 #define SDIO_PRESET3_DDR50SDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< DDR50SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
44465 #define SDIO_PRESET3_SDR104DRVRSTRSEL_Pos (14UL)                    /*!< SDR104DRVRSTRSEL (Bit 14)                             */
44466 #define SDIO_PRESET3_SDR104DRVRSTRSEL_Msk (0xc000UL)                /*!< SDR104DRVRSTRSEL (Bitfield-Mask: 0x03)                */
44467 #define SDIO_PRESET3_SDR104CLKGENSEL_Pos  (10UL)                    /*!< SDR104CLKGENSEL (Bit 10)                              */
44468 #define SDIO_PRESET3_SDR104CLKGENSEL_Msk  (0x400UL)                 /*!< SDR104CLKGENSEL (Bitfield-Mask: 0x01)                 */
44469 #define SDIO_PRESET3_SDR104SDCLKFREQSEL_Pos (0UL)                   /*!< SDR104SDCLKFREQSEL (Bit 0)                            */
44470 #define SDIO_PRESET3_SDR104SDCLKFREQSEL_Msk (0x3ffUL)               /*!< SDR104SDCLKFREQSEL (Bitfield-Mask: 0x3ff)             */
44471 /* ======================================================  BOOTTOCTRL  ======================================================= */
44472 #define SDIO_BOOTTOCTRL_BOOTDATATO_Pos    (0UL)                     /*!< BOOTDATATO (Bit 0)                                    */
44473 #define SDIO_BOOTTOCTRL_BOOTDATATO_Msk    (0xffffffffUL)            /*!< BOOTDATATO (Bitfield-Mask: 0xffffffff)                */
44474 /* ========================================================  VENDOR  ========================================================= */
44475 #define SDIO_VENDOR_DLYDIS_Pos            (1UL)                     /*!< DLYDIS (Bit 1)                                        */
44476 #define SDIO_VENDOR_DLYDIS_Msk            (0x2UL)                   /*!< DLYDIS (Bitfield-Mask: 0x01)                          */
44477 #define SDIO_VENDOR_GATESDCLKEN_Pos       (0UL)                     /*!< GATESDCLKEN (Bit 0)                                   */
44478 #define SDIO_VENDOR_GATESDCLKEN_Msk       (0x1UL)                   /*!< GATESDCLKEN (Bitfield-Mask: 0x01)                     */
44479 /* =======================================================  SLOTSTAT  ======================================================== */
44480 #define SDIO_SLOTSTAT_VENDORVER_Pos       (24UL)                    /*!< VENDORVER (Bit 24)                                    */
44481 #define SDIO_SLOTSTAT_VENDORVER_Msk       (0xff000000UL)            /*!< VENDORVER (Bitfield-Mask: 0xff)                       */
44482 #define SDIO_SLOTSTAT_SPECVER_Pos         (16UL)                    /*!< SPECVER (Bit 16)                                      */
44483 #define SDIO_SLOTSTAT_SPECVER_Msk         (0xff0000UL)              /*!< SPECVER (Bitfield-Mask: 0xff)                         */
44484 #define SDIO_SLOTSTAT_INTSLOT0_Pos        (0UL)                     /*!< INTSLOT0 (Bit 0)                                      */
44485 #define SDIO_SLOTSTAT_INTSLOT0_Msk        (0x1UL)                   /*!< INTSLOT0 (Bitfield-Mask: 0x01)                        */
44486 
44487 
44488 /* =========================================================================================================================== */
44489 /* ================                                         SECURITY                                          ================ */
44490 /* =========================================================================================================================== */
44491 
44492 /* =========================================================  CTRL  ========================================================== */
44493 #define SECURITY_CTRL_CRCERROR_Pos        (31UL)                    /*!< CRCERROR (Bit 31)                                     */
44494 #define SECURITY_CTRL_CRCERROR_Msk        (0x80000000UL)            /*!< CRCERROR (Bitfield-Mask: 0x01)                        */
44495 #define SECURITY_CTRL_FUNCTION_Pos        (4UL)                     /*!< FUNCTION (Bit 4)                                      */
44496 #define SECURITY_CTRL_FUNCTION_Msk        (0xf0UL)                  /*!< FUNCTION (Bitfield-Mask: 0x0f)                        */
44497 #define SECURITY_CTRL_ENABLE_Pos          (0UL)                     /*!< ENABLE (Bit 0)                                        */
44498 #define SECURITY_CTRL_ENABLE_Msk          (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
44499 /* ========================================================  SRCADDR  ======================================================== */
44500 #define SECURITY_SRCADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
44501 #define SECURITY_SRCADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
44502 /* ==========================================================  LEN  ========================================================== */
44503 #define SECURITY_LEN_LEN_Pos              (2UL)                     /*!< LEN (Bit 2)                                           */
44504 #define SECURITY_LEN_LEN_Msk              (0xfffffcUL)              /*!< LEN (Bitfield-Mask: 0x3fffff)                         */
44505 /* ========================================================  RESULT  ========================================================= */
44506 #define SECURITY_RESULT_CRC_Pos           (0UL)                     /*!< CRC (Bit 0)                                           */
44507 #define SECURITY_RESULT_CRC_Msk           (0xffffffffUL)            /*!< CRC (Bitfield-Mask: 0xffffffff)                       */
44508 /* =======================================================  LOCKCTRL  ======================================================== */
44509 #define SECURITY_LOCKCTRL_SELECT_Pos      (0UL)                     /*!< SELECT (Bit 0)                                        */
44510 #define SECURITY_LOCKCTRL_SELECT_Msk      (0xffUL)                  /*!< SELECT (Bitfield-Mask: 0xff)                          */
44511 /* =======================================================  LOCKSTAT  ======================================================== */
44512 #define SECURITY_LOCKSTAT_STATUS_Pos      (0UL)                     /*!< STATUS (Bit 0)                                        */
44513 #define SECURITY_LOCKSTAT_STATUS_Msk      (0xffffffffUL)            /*!< STATUS (Bitfield-Mask: 0xffffffff)                    */
44514 /* =========================================================  KEY0  ========================================================== */
44515 #define SECURITY_KEY0_KEY0_Pos            (0UL)                     /*!< KEY0 (Bit 0)                                          */
44516 #define SECURITY_KEY0_KEY0_Msk            (0xffffffffUL)            /*!< KEY0 (Bitfield-Mask: 0xffffffff)                      */
44517 /* =========================================================  KEY1  ========================================================== */
44518 #define SECURITY_KEY1_KEY1_Pos            (0UL)                     /*!< KEY1 (Bit 0)                                          */
44519 #define SECURITY_KEY1_KEY1_Msk            (0xffffffffUL)            /*!< KEY1 (Bitfield-Mask: 0xffffffff)                      */
44520 /* =========================================================  KEY2  ========================================================== */
44521 #define SECURITY_KEY2_KEY2_Pos            (0UL)                     /*!< KEY2 (Bit 0)                                          */
44522 #define SECURITY_KEY2_KEY2_Msk            (0xffffffffUL)            /*!< KEY2 (Bitfield-Mask: 0xffffffff)                      */
44523 /* =========================================================  KEY3  ========================================================== */
44524 #define SECURITY_KEY3_KEY3_Pos            (0UL)                     /*!< KEY3 (Bit 0)                                          */
44525 #define SECURITY_KEY3_KEY3_Msk            (0xffffffffUL)            /*!< KEY3 (Bitfield-Mask: 0xffffffff)                      */
44526 
44527 
44528 /* =========================================================================================================================== */
44529 /* ================                                          STIMER                                           ================ */
44530 /* =========================================================================================================================== */
44531 
44532 /* =========================================================  STCFG  ========================================================= */
44533 #define STIMER_STCFG_FREEZE_Pos           (31UL)                    /*!< FREEZE (Bit 31)                                       */
44534 #define STIMER_STCFG_FREEZE_Msk           (0x80000000UL)            /*!< FREEZE (Bitfield-Mask: 0x01)                          */
44535 #define STIMER_STCFG_CLEAR_Pos            (30UL)                    /*!< CLEAR (Bit 30)                                        */
44536 #define STIMER_STCFG_CLEAR_Msk            (0x40000000UL)            /*!< CLEAR (Bitfield-Mask: 0x01)                           */
44537 #define STIMER_STCFG_COMPAREHEN_Pos       (15UL)                    /*!< COMPAREHEN (Bit 15)                                   */
44538 #define STIMER_STCFG_COMPAREHEN_Msk       (0x8000UL)                /*!< COMPAREHEN (Bitfield-Mask: 0x01)                      */
44539 #define STIMER_STCFG_COMPAREGEN_Pos       (14UL)                    /*!< COMPAREGEN (Bit 14)                                   */
44540 #define STIMER_STCFG_COMPAREGEN_Msk       (0x4000UL)                /*!< COMPAREGEN (Bitfield-Mask: 0x01)                      */
44541 #define STIMER_STCFG_COMPAREFEN_Pos       (13UL)                    /*!< COMPAREFEN (Bit 13)                                   */
44542 #define STIMER_STCFG_COMPAREFEN_Msk       (0x2000UL)                /*!< COMPAREFEN (Bitfield-Mask: 0x01)                      */
44543 #define STIMER_STCFG_COMPAREEEN_Pos       (12UL)                    /*!< COMPAREEEN (Bit 12)                                   */
44544 #define STIMER_STCFG_COMPAREEEN_Msk       (0x1000UL)                /*!< COMPAREEEN (Bitfield-Mask: 0x01)                      */
44545 #define STIMER_STCFG_COMPAREDEN_Pos       (11UL)                    /*!< COMPAREDEN (Bit 11)                                   */
44546 #define STIMER_STCFG_COMPAREDEN_Msk       (0x800UL)                 /*!< COMPAREDEN (Bitfield-Mask: 0x01)                      */
44547 #define STIMER_STCFG_COMPARECEN_Pos       (10UL)                    /*!< COMPARECEN (Bit 10)                                   */
44548 #define STIMER_STCFG_COMPARECEN_Msk       (0x400UL)                 /*!< COMPARECEN (Bitfield-Mask: 0x01)                      */
44549 #define STIMER_STCFG_COMPAREBEN_Pos       (9UL)                     /*!< COMPAREBEN (Bit 9)                                    */
44550 #define STIMER_STCFG_COMPAREBEN_Msk       (0x200UL)                 /*!< COMPAREBEN (Bitfield-Mask: 0x01)                      */
44551 #define STIMER_STCFG_COMPAREAEN_Pos       (8UL)                     /*!< COMPAREAEN (Bit 8)                                    */
44552 #define STIMER_STCFG_COMPAREAEN_Msk       (0x100UL)                 /*!< COMPAREAEN (Bitfield-Mask: 0x01)                      */
44553 #define STIMER_STCFG_CLKSEL_Pos           (0UL)                     /*!< CLKSEL (Bit 0)                                        */
44554 #define STIMER_STCFG_CLKSEL_Msk           (0xfUL)                   /*!< CLKSEL (Bitfield-Mask: 0x0f)                          */
44555 /* =========================================================  STTMR  ========================================================= */
44556 #define STIMER_STTMR_STTMR_Pos            (0UL)                     /*!< STTMR (Bit 0)                                         */
44557 #define STIMER_STTMR_STTMR_Msk            (0xffffffffUL)            /*!< STTMR (Bitfield-Mask: 0xffffffff)                     */
44558 /* =======================================================  SCAPCTRL0  ======================================================= */
44559 #define STIMER_SCAPCTRL0_CAPTURE0_Pos     (9UL)                     /*!< CAPTURE0 (Bit 9)                                      */
44560 #define STIMER_SCAPCTRL0_CAPTURE0_Msk     (0x200UL)                 /*!< CAPTURE0 (Bitfield-Mask: 0x01)                        */
44561 #define STIMER_SCAPCTRL0_STPOL0_Pos       (8UL)                     /*!< STPOL0 (Bit 8)                                        */
44562 #define STIMER_SCAPCTRL0_STPOL0_Msk       (0x100UL)                 /*!< STPOL0 (Bitfield-Mask: 0x01)                          */
44563 #define STIMER_SCAPCTRL0_STSEL0_Pos       (0UL)                     /*!< STSEL0 (Bit 0)                                        */
44564 #define STIMER_SCAPCTRL0_STSEL0_Msk       (0x7fUL)                  /*!< STSEL0 (Bitfield-Mask: 0x7f)                          */
44565 /* =======================================================  SCAPCTRL1  ======================================================= */
44566 #define STIMER_SCAPCTRL1_CAPTURE1_Pos     (9UL)                     /*!< CAPTURE1 (Bit 9)                                      */
44567 #define STIMER_SCAPCTRL1_CAPTURE1_Msk     (0x200UL)                 /*!< CAPTURE1 (Bitfield-Mask: 0x01)                        */
44568 #define STIMER_SCAPCTRL1_STPOL1_Pos       (8UL)                     /*!< STPOL1 (Bit 8)                                        */
44569 #define STIMER_SCAPCTRL1_STPOL1_Msk       (0x100UL)                 /*!< STPOL1 (Bitfield-Mask: 0x01)                          */
44570 #define STIMER_SCAPCTRL1_STSEL1_Pos       (0UL)                     /*!< STSEL1 (Bit 0)                                        */
44571 #define STIMER_SCAPCTRL1_STSEL1_Msk       (0x7fUL)                  /*!< STSEL1 (Bitfield-Mask: 0x7f)                          */
44572 /* =======================================================  SCAPCTRL2  ======================================================= */
44573 #define STIMER_SCAPCTRL2_CAPTURE2_Pos     (9UL)                     /*!< CAPTURE2 (Bit 9)                                      */
44574 #define STIMER_SCAPCTRL2_CAPTURE2_Msk     (0x200UL)                 /*!< CAPTURE2 (Bitfield-Mask: 0x01)                        */
44575 #define STIMER_SCAPCTRL2_STPOL2_Pos       (8UL)                     /*!< STPOL2 (Bit 8)                                        */
44576 #define STIMER_SCAPCTRL2_STPOL2_Msk       (0x100UL)                 /*!< STPOL2 (Bitfield-Mask: 0x01)                          */
44577 #define STIMER_SCAPCTRL2_STSEL2_Pos       (0UL)                     /*!< STSEL2 (Bit 0)                                        */
44578 #define STIMER_SCAPCTRL2_STSEL2_Msk       (0x7fUL)                  /*!< STSEL2 (Bitfield-Mask: 0x7f)                          */
44579 /* =======================================================  SCAPCTRL3  ======================================================= */
44580 #define STIMER_SCAPCTRL3_CAPTURE3_Pos     (9UL)                     /*!< CAPTURE3 (Bit 9)                                      */
44581 #define STIMER_SCAPCTRL3_CAPTURE3_Msk     (0x200UL)                 /*!< CAPTURE3 (Bitfield-Mask: 0x01)                        */
44582 #define STIMER_SCAPCTRL3_STPOL3_Pos       (8UL)                     /*!< STPOL3 (Bit 8)                                        */
44583 #define STIMER_SCAPCTRL3_STPOL3_Msk       (0x100UL)                 /*!< STPOL3 (Bitfield-Mask: 0x01)                          */
44584 #define STIMER_SCAPCTRL3_STSEL3_Pos       (0UL)                     /*!< STSEL3 (Bit 0)                                        */
44585 #define STIMER_SCAPCTRL3_STSEL3_Msk       (0x7fUL)                  /*!< STSEL3 (Bitfield-Mask: 0x7f)                          */
44586 /* ========================================================  SCMPR0  ========================================================= */
44587 #define STIMER_SCMPR0_SCMPR0_Pos          (0UL)                     /*!< SCMPR0 (Bit 0)                                        */
44588 #define STIMER_SCMPR0_SCMPR0_Msk          (0xffffffffUL)            /*!< SCMPR0 (Bitfield-Mask: 0xffffffff)                    */
44589 /* ========================================================  SCMPR1  ========================================================= */
44590 #define STIMER_SCMPR1_SCMPR1_Pos          (0UL)                     /*!< SCMPR1 (Bit 0)                                        */
44591 #define STIMER_SCMPR1_SCMPR1_Msk          (0xffffffffUL)            /*!< SCMPR1 (Bitfield-Mask: 0xffffffff)                    */
44592 /* ========================================================  SCMPR2  ========================================================= */
44593 #define STIMER_SCMPR2_SCMPR2_Pos          (0UL)                     /*!< SCMPR2 (Bit 0)                                        */
44594 #define STIMER_SCMPR2_SCMPR2_Msk          (0xffffffffUL)            /*!< SCMPR2 (Bitfield-Mask: 0xffffffff)                    */
44595 /* ========================================================  SCMPR3  ========================================================= */
44596 #define STIMER_SCMPR3_SCMPR3_Pos          (0UL)                     /*!< SCMPR3 (Bit 0)                                        */
44597 #define STIMER_SCMPR3_SCMPR3_Msk          (0xffffffffUL)            /*!< SCMPR3 (Bitfield-Mask: 0xffffffff)                    */
44598 /* ========================================================  SCMPR4  ========================================================= */
44599 #define STIMER_SCMPR4_SCMPR4_Pos          (0UL)                     /*!< SCMPR4 (Bit 0)                                        */
44600 #define STIMER_SCMPR4_SCMPR4_Msk          (0xffffffffUL)            /*!< SCMPR4 (Bitfield-Mask: 0xffffffff)                    */
44601 /* ========================================================  SCMPR5  ========================================================= */
44602 #define STIMER_SCMPR5_SCMPR5_Pos          (0UL)                     /*!< SCMPR5 (Bit 0)                                        */
44603 #define STIMER_SCMPR5_SCMPR5_Msk          (0xffffffffUL)            /*!< SCMPR5 (Bitfield-Mask: 0xffffffff)                    */
44604 /* ========================================================  SCMPR6  ========================================================= */
44605 #define STIMER_SCMPR6_SCMPR6_Pos          (0UL)                     /*!< SCMPR6 (Bit 0)                                        */
44606 #define STIMER_SCMPR6_SCMPR6_Msk          (0xffffffffUL)            /*!< SCMPR6 (Bitfield-Mask: 0xffffffff)                    */
44607 /* ========================================================  SCMPR7  ========================================================= */
44608 #define STIMER_SCMPR7_SCMPR7_Pos          (0UL)                     /*!< SCMPR7 (Bit 0)                                        */
44609 #define STIMER_SCMPR7_SCMPR7_Msk          (0xffffffffUL)            /*!< SCMPR7 (Bitfield-Mask: 0xffffffff)                    */
44610 /* ========================================================  SCAPT0  ========================================================= */
44611 #define STIMER_SCAPT0_SCAPT0_Pos          (0UL)                     /*!< SCAPT0 (Bit 0)                                        */
44612 #define STIMER_SCAPT0_SCAPT0_Msk          (0xffffffffUL)            /*!< SCAPT0 (Bitfield-Mask: 0xffffffff)                    */
44613 /* ========================================================  SCAPT1  ========================================================= */
44614 #define STIMER_SCAPT1_SCAPT1_Pos          (0UL)                     /*!< SCAPT1 (Bit 0)                                        */
44615 #define STIMER_SCAPT1_SCAPT1_Msk          (0xffffffffUL)            /*!< SCAPT1 (Bitfield-Mask: 0xffffffff)                    */
44616 /* ========================================================  SCAPT2  ========================================================= */
44617 #define STIMER_SCAPT2_SCAPT2_Pos          (0UL)                     /*!< SCAPT2 (Bit 0)                                        */
44618 #define STIMER_SCAPT2_SCAPT2_Msk          (0xffffffffUL)            /*!< SCAPT2 (Bitfield-Mask: 0xffffffff)                    */
44619 /* ========================================================  SCAPT3  ========================================================= */
44620 #define STIMER_SCAPT3_SCAPT3_Pos          (0UL)                     /*!< SCAPT3 (Bit 0)                                        */
44621 #define STIMER_SCAPT3_SCAPT3_Msk          (0xffffffffUL)            /*!< SCAPT3 (Bitfield-Mask: 0xffffffff)                    */
44622 /* =========================================================  SNVR0  ========================================================= */
44623 #define STIMER_SNVR0_SNVR0_Pos            (0UL)                     /*!< SNVR0 (Bit 0)                                         */
44624 #define STIMER_SNVR0_SNVR0_Msk            (0xffffffffUL)            /*!< SNVR0 (Bitfield-Mask: 0xffffffff)                     */
44625 /* =========================================================  SNVR1  ========================================================= */
44626 #define STIMER_SNVR1_SNVR1_Pos            (0UL)                     /*!< SNVR1 (Bit 0)                                         */
44627 #define STIMER_SNVR1_SNVR1_Msk            (0xffffffffUL)            /*!< SNVR1 (Bitfield-Mask: 0xffffffff)                     */
44628 /* =========================================================  SNVR2  ========================================================= */
44629 #define STIMER_SNVR2_SNVR2_Pos            (0UL)                     /*!< SNVR2 (Bit 0)                                         */
44630 #define STIMER_SNVR2_SNVR2_Msk            (0xffffffffUL)            /*!< SNVR2 (Bitfield-Mask: 0xffffffff)                     */
44631 /* =======================================================  STMINTEN  ======================================================== */
44632 #define STIMER_STMINTEN_CAPTURED_Pos      (12UL)                    /*!< CAPTURED (Bit 12)                                     */
44633 #define STIMER_STMINTEN_CAPTURED_Msk      (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
44634 #define STIMER_STMINTEN_CAPTUREC_Pos      (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
44635 #define STIMER_STMINTEN_CAPTUREC_Msk      (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
44636 #define STIMER_STMINTEN_CAPTUREB_Pos      (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
44637 #define STIMER_STMINTEN_CAPTUREB_Msk      (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
44638 #define STIMER_STMINTEN_CAPTUREA_Pos      (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
44639 #define STIMER_STMINTEN_CAPTUREA_Msk      (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
44640 #define STIMER_STMINTEN_OVERFLOW_Pos      (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
44641 #define STIMER_STMINTEN_OVERFLOW_Msk      (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
44642 #define STIMER_STMINTEN_COMPAREH_Pos      (7UL)                     /*!< COMPAREH (Bit 7)                                      */
44643 #define STIMER_STMINTEN_COMPAREH_Msk      (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
44644 #define STIMER_STMINTEN_COMPAREG_Pos      (6UL)                     /*!< COMPAREG (Bit 6)                                      */
44645 #define STIMER_STMINTEN_COMPAREG_Msk      (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
44646 #define STIMER_STMINTEN_COMPAREF_Pos      (5UL)                     /*!< COMPAREF (Bit 5)                                      */
44647 #define STIMER_STMINTEN_COMPAREF_Msk      (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
44648 #define STIMER_STMINTEN_COMPAREE_Pos      (4UL)                     /*!< COMPAREE (Bit 4)                                      */
44649 #define STIMER_STMINTEN_COMPAREE_Msk      (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
44650 #define STIMER_STMINTEN_COMPARED_Pos      (3UL)                     /*!< COMPARED (Bit 3)                                      */
44651 #define STIMER_STMINTEN_COMPARED_Msk      (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
44652 #define STIMER_STMINTEN_COMPAREC_Pos      (2UL)                     /*!< COMPAREC (Bit 2)                                      */
44653 #define STIMER_STMINTEN_COMPAREC_Msk      (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
44654 #define STIMER_STMINTEN_COMPAREB_Pos      (1UL)                     /*!< COMPAREB (Bit 1)                                      */
44655 #define STIMER_STMINTEN_COMPAREB_Msk      (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
44656 #define STIMER_STMINTEN_COMPAREA_Pos      (0UL)                     /*!< COMPAREA (Bit 0)                                      */
44657 #define STIMER_STMINTEN_COMPAREA_Msk      (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
44658 /* ======================================================  STMINTSTAT  ======================================================= */
44659 #define STIMER_STMINTSTAT_CAPTURED_Pos    (12UL)                    /*!< CAPTURED (Bit 12)                                     */
44660 #define STIMER_STMINTSTAT_CAPTURED_Msk    (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
44661 #define STIMER_STMINTSTAT_CAPTUREC_Pos    (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
44662 #define STIMER_STMINTSTAT_CAPTUREC_Msk    (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
44663 #define STIMER_STMINTSTAT_CAPTUREB_Pos    (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
44664 #define STIMER_STMINTSTAT_CAPTUREB_Msk    (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
44665 #define STIMER_STMINTSTAT_CAPTUREA_Pos    (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
44666 #define STIMER_STMINTSTAT_CAPTUREA_Msk    (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
44667 #define STIMER_STMINTSTAT_OVERFLOW_Pos    (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
44668 #define STIMER_STMINTSTAT_OVERFLOW_Msk    (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
44669 #define STIMER_STMINTSTAT_COMPAREH_Pos    (7UL)                     /*!< COMPAREH (Bit 7)                                      */
44670 #define STIMER_STMINTSTAT_COMPAREH_Msk    (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
44671 #define STIMER_STMINTSTAT_COMPAREG_Pos    (6UL)                     /*!< COMPAREG (Bit 6)                                      */
44672 #define STIMER_STMINTSTAT_COMPAREG_Msk    (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
44673 #define STIMER_STMINTSTAT_COMPAREF_Pos    (5UL)                     /*!< COMPAREF (Bit 5)                                      */
44674 #define STIMER_STMINTSTAT_COMPAREF_Msk    (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
44675 #define STIMER_STMINTSTAT_COMPAREE_Pos    (4UL)                     /*!< COMPAREE (Bit 4)                                      */
44676 #define STIMER_STMINTSTAT_COMPAREE_Msk    (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
44677 #define STIMER_STMINTSTAT_COMPARED_Pos    (3UL)                     /*!< COMPARED (Bit 3)                                      */
44678 #define STIMER_STMINTSTAT_COMPARED_Msk    (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
44679 #define STIMER_STMINTSTAT_COMPAREC_Pos    (2UL)                     /*!< COMPAREC (Bit 2)                                      */
44680 #define STIMER_STMINTSTAT_COMPAREC_Msk    (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
44681 #define STIMER_STMINTSTAT_COMPAREB_Pos    (1UL)                     /*!< COMPAREB (Bit 1)                                      */
44682 #define STIMER_STMINTSTAT_COMPAREB_Msk    (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
44683 #define STIMER_STMINTSTAT_COMPAREA_Pos    (0UL)                     /*!< COMPAREA (Bit 0)                                      */
44684 #define STIMER_STMINTSTAT_COMPAREA_Msk    (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
44685 /* =======================================================  STMINTCLR  ======================================================= */
44686 #define STIMER_STMINTCLR_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
44687 #define STIMER_STMINTCLR_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
44688 #define STIMER_STMINTCLR_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
44689 #define STIMER_STMINTCLR_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
44690 #define STIMER_STMINTCLR_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
44691 #define STIMER_STMINTCLR_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
44692 #define STIMER_STMINTCLR_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
44693 #define STIMER_STMINTCLR_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
44694 #define STIMER_STMINTCLR_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
44695 #define STIMER_STMINTCLR_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
44696 #define STIMER_STMINTCLR_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
44697 #define STIMER_STMINTCLR_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
44698 #define STIMER_STMINTCLR_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
44699 #define STIMER_STMINTCLR_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
44700 #define STIMER_STMINTCLR_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
44701 #define STIMER_STMINTCLR_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
44702 #define STIMER_STMINTCLR_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
44703 #define STIMER_STMINTCLR_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
44704 #define STIMER_STMINTCLR_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
44705 #define STIMER_STMINTCLR_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
44706 #define STIMER_STMINTCLR_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
44707 #define STIMER_STMINTCLR_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
44708 #define STIMER_STMINTCLR_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
44709 #define STIMER_STMINTCLR_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
44710 #define STIMER_STMINTCLR_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
44711 #define STIMER_STMINTCLR_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
44712 /* =======================================================  STMINTSET  ======================================================= */
44713 #define STIMER_STMINTSET_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
44714 #define STIMER_STMINTSET_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
44715 #define STIMER_STMINTSET_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
44716 #define STIMER_STMINTSET_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
44717 #define STIMER_STMINTSET_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
44718 #define STIMER_STMINTSET_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
44719 #define STIMER_STMINTSET_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
44720 #define STIMER_STMINTSET_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
44721 #define STIMER_STMINTSET_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
44722 #define STIMER_STMINTSET_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
44723 #define STIMER_STMINTSET_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
44724 #define STIMER_STMINTSET_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
44725 #define STIMER_STMINTSET_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
44726 #define STIMER_STMINTSET_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
44727 #define STIMER_STMINTSET_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
44728 #define STIMER_STMINTSET_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
44729 #define STIMER_STMINTSET_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
44730 #define STIMER_STMINTSET_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
44731 #define STIMER_STMINTSET_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
44732 #define STIMER_STMINTSET_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
44733 #define STIMER_STMINTSET_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
44734 #define STIMER_STMINTSET_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
44735 #define STIMER_STMINTSET_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
44736 #define STIMER_STMINTSET_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
44737 #define STIMER_STMINTSET_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
44738 #define STIMER_STMINTSET_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
44739 
44740 
44741 /* =========================================================================================================================== */
44742 /* ================                                           TIMER                                           ================ */
44743 /* =========================================================================================================================== */
44744 
44745 /* =========================================================  CTRL  ========================================================== */
44746 #define TIMER_CTRL_RESET_Pos              (31UL)                    /*!< RESET (Bit 31)                                        */
44747 #define TIMER_CTRL_RESET_Msk              (0x80000000UL)            /*!< RESET (Bitfield-Mask: 0x01)                           */
44748 /* ========================================================  STATUS  ========================================================= */
44749 #define TIMER_STATUS_NTIMERS_Pos          (16UL)                    /*!< NTIMERS (Bit 16)                                      */
44750 #define TIMER_STATUS_NTIMERS_Msk          (0x1f0000UL)              /*!< NTIMERS (Bitfield-Mask: 0x1f)                         */
44751 #define TIMER_STATUS_ACTIVE_Pos           (0UL)                     /*!< ACTIVE (Bit 0)                                        */
44752 #define TIMER_STATUS_ACTIVE_Msk           (0xffffUL)                /*!< ACTIVE (Bitfield-Mask: 0xffff)                        */
44753 /* ========================================================  GLOBEN  ========================================================= */
44754 #define TIMER_GLOBEN_ADCEN_Pos            (31UL)                    /*!< ADCEN (Bit 31)                                        */
44755 #define TIMER_GLOBEN_ADCEN_Msk            (0x80000000UL)            /*!< ADCEN (Bitfield-Mask: 0x01)                           */
44756 #define TIMER_GLOBEN_AUDADCEN_Pos         (30UL)                    /*!< AUDADCEN (Bit 30)                                     */
44757 #define TIMER_GLOBEN_AUDADCEN_Msk         (0x40000000UL)            /*!< AUDADCEN (Bitfield-Mask: 0x01)                        */
44758 #define TIMER_GLOBEN_ENABLEALLINPUTS_Pos  (29UL)                    /*!< ENABLEALLINPUTS (Bit 29)                              */
44759 #define TIMER_GLOBEN_ENABLEALLINPUTS_Msk  (0x20000000UL)            /*!< ENABLEALLINPUTS (Bitfield-Mask: 0x01)                 */
44760 #define TIMER_GLOBEN_ENB15_Pos            (15UL)                    /*!< ENB15 (Bit 15)                                        */
44761 #define TIMER_GLOBEN_ENB15_Msk            (0x8000UL)                /*!< ENB15 (Bitfield-Mask: 0x01)                           */
44762 #define TIMER_GLOBEN_ENB14_Pos            (14UL)                    /*!< ENB14 (Bit 14)                                        */
44763 #define TIMER_GLOBEN_ENB14_Msk            (0x4000UL)                /*!< ENB14 (Bitfield-Mask: 0x01)                           */
44764 #define TIMER_GLOBEN_ENB13_Pos            (13UL)                    /*!< ENB13 (Bit 13)                                        */
44765 #define TIMER_GLOBEN_ENB13_Msk            (0x2000UL)                /*!< ENB13 (Bitfield-Mask: 0x01)                           */
44766 #define TIMER_GLOBEN_ENB12_Pos            (12UL)                    /*!< ENB12 (Bit 12)                                        */
44767 #define TIMER_GLOBEN_ENB12_Msk            (0x1000UL)                /*!< ENB12 (Bitfield-Mask: 0x01)                           */
44768 #define TIMER_GLOBEN_ENB11_Pos            (11UL)                    /*!< ENB11 (Bit 11)                                        */
44769 #define TIMER_GLOBEN_ENB11_Msk            (0x800UL)                 /*!< ENB11 (Bitfield-Mask: 0x01)                           */
44770 #define TIMER_GLOBEN_ENB10_Pos            (10UL)                    /*!< ENB10 (Bit 10)                                        */
44771 #define TIMER_GLOBEN_ENB10_Msk            (0x400UL)                 /*!< ENB10 (Bitfield-Mask: 0x01)                           */
44772 #define TIMER_GLOBEN_ENB9_Pos             (9UL)                     /*!< ENB9 (Bit 9)                                          */
44773 #define TIMER_GLOBEN_ENB9_Msk             (0x200UL)                 /*!< ENB9 (Bitfield-Mask: 0x01)                            */
44774 #define TIMER_GLOBEN_ENB8_Pos             (8UL)                     /*!< ENB8 (Bit 8)                                          */
44775 #define TIMER_GLOBEN_ENB8_Msk             (0x100UL)                 /*!< ENB8 (Bitfield-Mask: 0x01)                            */
44776 #define TIMER_GLOBEN_ENB7_Pos             (7UL)                     /*!< ENB7 (Bit 7)                                          */
44777 #define TIMER_GLOBEN_ENB7_Msk             (0x80UL)                  /*!< ENB7 (Bitfield-Mask: 0x01)                            */
44778 #define TIMER_GLOBEN_ENB6_Pos             (6UL)                     /*!< ENB6 (Bit 6)                                          */
44779 #define TIMER_GLOBEN_ENB6_Msk             (0x40UL)                  /*!< ENB6 (Bitfield-Mask: 0x01)                            */
44780 #define TIMER_GLOBEN_ENB5_Pos             (5UL)                     /*!< ENB5 (Bit 5)                                          */
44781 #define TIMER_GLOBEN_ENB5_Msk             (0x20UL)                  /*!< ENB5 (Bitfield-Mask: 0x01)                            */
44782 #define TIMER_GLOBEN_ENB4_Pos             (4UL)                     /*!< ENB4 (Bit 4)                                          */
44783 #define TIMER_GLOBEN_ENB4_Msk             (0x10UL)                  /*!< ENB4 (Bitfield-Mask: 0x01)                            */
44784 #define TIMER_GLOBEN_ENB3_Pos             (3UL)                     /*!< ENB3 (Bit 3)                                          */
44785 #define TIMER_GLOBEN_ENB3_Msk             (0x8UL)                   /*!< ENB3 (Bitfield-Mask: 0x01)                            */
44786 #define TIMER_GLOBEN_ENB2_Pos             (2UL)                     /*!< ENB2 (Bit 2)                                          */
44787 #define TIMER_GLOBEN_ENB2_Msk             (0x4UL)                   /*!< ENB2 (Bitfield-Mask: 0x01)                            */
44788 #define TIMER_GLOBEN_ENB1_Pos             (1UL)                     /*!< ENB1 (Bit 1)                                          */
44789 #define TIMER_GLOBEN_ENB1_Msk             (0x2UL)                   /*!< ENB1 (Bitfield-Mask: 0x01)                            */
44790 #define TIMER_GLOBEN_ENB0_Pos             (0UL)                     /*!< ENB0 (Bit 0)                                          */
44791 #define TIMER_GLOBEN_ENB0_Msk             (0x1UL)                   /*!< ENB0 (Bitfield-Mask: 0x01)                            */
44792 /* =========================================================  INTEN  ========================================================= */
44793 #define TIMER_INTEN_TMR151INT_Pos         (31UL)                    /*!< TMR151INT (Bit 31)                                    */
44794 #define TIMER_INTEN_TMR151INT_Msk         (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
44795 #define TIMER_INTEN_TMR150INT_Pos         (30UL)                    /*!< TMR150INT (Bit 30)                                    */
44796 #define TIMER_INTEN_TMR150INT_Msk         (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
44797 #define TIMER_INTEN_TMR141INT_Pos         (29UL)                    /*!< TMR141INT (Bit 29)                                    */
44798 #define TIMER_INTEN_TMR141INT_Msk         (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
44799 #define TIMER_INTEN_TMR140INT_Pos         (28UL)                    /*!< TMR140INT (Bit 28)                                    */
44800 #define TIMER_INTEN_TMR140INT_Msk         (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
44801 #define TIMER_INTEN_TMR131INT_Pos         (27UL)                    /*!< TMR131INT (Bit 27)                                    */
44802 #define TIMER_INTEN_TMR131INT_Msk         (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
44803 #define TIMER_INTEN_TMR130INT_Pos         (26UL)                    /*!< TMR130INT (Bit 26)                                    */
44804 #define TIMER_INTEN_TMR130INT_Msk         (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
44805 #define TIMER_INTEN_TMR121INT_Pos         (25UL)                    /*!< TMR121INT (Bit 25)                                    */
44806 #define TIMER_INTEN_TMR121INT_Msk         (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
44807 #define TIMER_INTEN_TMR120INT_Pos         (24UL)                    /*!< TMR120INT (Bit 24)                                    */
44808 #define TIMER_INTEN_TMR120INT_Msk         (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
44809 #define TIMER_INTEN_TMR111INT_Pos         (23UL)                    /*!< TMR111INT (Bit 23)                                    */
44810 #define TIMER_INTEN_TMR111INT_Msk         (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
44811 #define TIMER_INTEN_TMR110INT_Pos         (22UL)                    /*!< TMR110INT (Bit 22)                                    */
44812 #define TIMER_INTEN_TMR110INT_Msk         (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
44813 #define TIMER_INTEN_TMR101INT_Pos         (21UL)                    /*!< TMR101INT (Bit 21)                                    */
44814 #define TIMER_INTEN_TMR101INT_Msk         (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
44815 #define TIMER_INTEN_TMR100INT_Pos         (20UL)                    /*!< TMR100INT (Bit 20)                                    */
44816 #define TIMER_INTEN_TMR100INT_Msk         (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
44817 #define TIMER_INTEN_TMR91INT_Pos          (19UL)                    /*!< TMR91INT (Bit 19)                                     */
44818 #define TIMER_INTEN_TMR91INT_Msk          (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
44819 #define TIMER_INTEN_TMR90INT_Pos          (18UL)                    /*!< TMR90INT (Bit 18)                                     */
44820 #define TIMER_INTEN_TMR90INT_Msk          (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
44821 #define TIMER_INTEN_TMR81INT_Pos          (17UL)                    /*!< TMR81INT (Bit 17)                                     */
44822 #define TIMER_INTEN_TMR81INT_Msk          (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
44823 #define TIMER_INTEN_TMR80INT_Pos          (16UL)                    /*!< TMR80INT (Bit 16)                                     */
44824 #define TIMER_INTEN_TMR80INT_Msk          (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
44825 #define TIMER_INTEN_TMR71INT_Pos          (15UL)                    /*!< TMR71INT (Bit 15)                                     */
44826 #define TIMER_INTEN_TMR71INT_Msk          (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
44827 #define TIMER_INTEN_TMR70INT_Pos          (14UL)                    /*!< TMR70INT (Bit 14)                                     */
44828 #define TIMER_INTEN_TMR70INT_Msk          (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
44829 #define TIMER_INTEN_TMR61INT_Pos          (13UL)                    /*!< TMR61INT (Bit 13)                                     */
44830 #define TIMER_INTEN_TMR61INT_Msk          (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
44831 #define TIMER_INTEN_TMR60INT_Pos          (12UL)                    /*!< TMR60INT (Bit 12)                                     */
44832 #define TIMER_INTEN_TMR60INT_Msk          (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
44833 #define TIMER_INTEN_TMR51INT_Pos          (11UL)                    /*!< TMR51INT (Bit 11)                                     */
44834 #define TIMER_INTEN_TMR51INT_Msk          (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
44835 #define TIMER_INTEN_TMR50INT_Pos          (10UL)                    /*!< TMR50INT (Bit 10)                                     */
44836 #define TIMER_INTEN_TMR50INT_Msk          (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
44837 #define TIMER_INTEN_TMR41INT_Pos          (9UL)                     /*!< TMR41INT (Bit 9)                                      */
44838 #define TIMER_INTEN_TMR41INT_Msk          (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
44839 #define TIMER_INTEN_TMR40INT_Pos          (8UL)                     /*!< TMR40INT (Bit 8)                                      */
44840 #define TIMER_INTEN_TMR40INT_Msk          (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
44841 #define TIMER_INTEN_TMR31INT_Pos          (7UL)                     /*!< TMR31INT (Bit 7)                                      */
44842 #define TIMER_INTEN_TMR31INT_Msk          (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
44843 #define TIMER_INTEN_TMR30INT_Pos          (6UL)                     /*!< TMR30INT (Bit 6)                                      */
44844 #define TIMER_INTEN_TMR30INT_Msk          (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
44845 #define TIMER_INTEN_TMR21INT_Pos          (5UL)                     /*!< TMR21INT (Bit 5)                                      */
44846 #define TIMER_INTEN_TMR21INT_Msk          (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
44847 #define TIMER_INTEN_TMR20INT_Pos          (4UL)                     /*!< TMR20INT (Bit 4)                                      */
44848 #define TIMER_INTEN_TMR20INT_Msk          (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
44849 #define TIMER_INTEN_TMR11INT_Pos          (3UL)                     /*!< TMR11INT (Bit 3)                                      */
44850 #define TIMER_INTEN_TMR11INT_Msk          (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
44851 #define TIMER_INTEN_TMR10INT_Pos          (2UL)                     /*!< TMR10INT (Bit 2)                                      */
44852 #define TIMER_INTEN_TMR10INT_Msk          (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
44853 #define TIMER_INTEN_TMR01INT_Pos          (1UL)                     /*!< TMR01INT (Bit 1)                                      */
44854 #define TIMER_INTEN_TMR01INT_Msk          (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
44855 #define TIMER_INTEN_TMR00INT_Pos          (0UL)                     /*!< TMR00INT (Bit 0)                                      */
44856 #define TIMER_INTEN_TMR00INT_Msk          (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
44857 /* ========================================================  INTSTAT  ======================================================== */
44858 #define TIMER_INTSTAT_TMR151INT_Pos       (31UL)                    /*!< TMR151INT (Bit 31)                                    */
44859 #define TIMER_INTSTAT_TMR151INT_Msk       (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
44860 #define TIMER_INTSTAT_TMR150INT_Pos       (30UL)                    /*!< TMR150INT (Bit 30)                                    */
44861 #define TIMER_INTSTAT_TMR150INT_Msk       (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
44862 #define TIMER_INTSTAT_TMR141INT_Pos       (29UL)                    /*!< TMR141INT (Bit 29)                                    */
44863 #define TIMER_INTSTAT_TMR141INT_Msk       (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
44864 #define TIMER_INTSTAT_TMR140INT_Pos       (28UL)                    /*!< TMR140INT (Bit 28)                                    */
44865 #define TIMER_INTSTAT_TMR140INT_Msk       (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
44866 #define TIMER_INTSTAT_TMR131INT_Pos       (27UL)                    /*!< TMR131INT (Bit 27)                                    */
44867 #define TIMER_INTSTAT_TMR131INT_Msk       (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
44868 #define TIMER_INTSTAT_TMR130INT_Pos       (26UL)                    /*!< TMR130INT (Bit 26)                                    */
44869 #define TIMER_INTSTAT_TMR130INT_Msk       (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
44870 #define TIMER_INTSTAT_TMR121INT_Pos       (25UL)                    /*!< TMR121INT (Bit 25)                                    */
44871 #define TIMER_INTSTAT_TMR121INT_Msk       (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
44872 #define TIMER_INTSTAT_TMR120INT_Pos       (24UL)                    /*!< TMR120INT (Bit 24)                                    */
44873 #define TIMER_INTSTAT_TMR120INT_Msk       (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
44874 #define TIMER_INTSTAT_TMR111INT_Pos       (23UL)                    /*!< TMR111INT (Bit 23)                                    */
44875 #define TIMER_INTSTAT_TMR111INT_Msk       (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
44876 #define TIMER_INTSTAT_TMR110INT_Pos       (22UL)                    /*!< TMR110INT (Bit 22)                                    */
44877 #define TIMER_INTSTAT_TMR110INT_Msk       (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
44878 #define TIMER_INTSTAT_TMR101INT_Pos       (21UL)                    /*!< TMR101INT (Bit 21)                                    */
44879 #define TIMER_INTSTAT_TMR101INT_Msk       (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
44880 #define TIMER_INTSTAT_TMR100INT_Pos       (20UL)                    /*!< TMR100INT (Bit 20)                                    */
44881 #define TIMER_INTSTAT_TMR100INT_Msk       (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
44882 #define TIMER_INTSTAT_TMR91INT_Pos        (19UL)                    /*!< TMR91INT (Bit 19)                                     */
44883 #define TIMER_INTSTAT_TMR91INT_Msk        (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
44884 #define TIMER_INTSTAT_TMR90INT_Pos        (18UL)                    /*!< TMR90INT (Bit 18)                                     */
44885 #define TIMER_INTSTAT_TMR90INT_Msk        (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
44886 #define TIMER_INTSTAT_TMR81INT_Pos        (17UL)                    /*!< TMR81INT (Bit 17)                                     */
44887 #define TIMER_INTSTAT_TMR81INT_Msk        (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
44888 #define TIMER_INTSTAT_TMR80INT_Pos        (16UL)                    /*!< TMR80INT (Bit 16)                                     */
44889 #define TIMER_INTSTAT_TMR80INT_Msk        (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
44890 #define TIMER_INTSTAT_TMR71INT_Pos        (15UL)                    /*!< TMR71INT (Bit 15)                                     */
44891 #define TIMER_INTSTAT_TMR71INT_Msk        (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
44892 #define TIMER_INTSTAT_TMR70INT_Pos        (14UL)                    /*!< TMR70INT (Bit 14)                                     */
44893 #define TIMER_INTSTAT_TMR70INT_Msk        (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
44894 #define TIMER_INTSTAT_TMR61INT_Pos        (13UL)                    /*!< TMR61INT (Bit 13)                                     */
44895 #define TIMER_INTSTAT_TMR61INT_Msk        (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
44896 #define TIMER_INTSTAT_TMR60INT_Pos        (12UL)                    /*!< TMR60INT (Bit 12)                                     */
44897 #define TIMER_INTSTAT_TMR60INT_Msk        (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
44898 #define TIMER_INTSTAT_TMR51INT_Pos        (11UL)                    /*!< TMR51INT (Bit 11)                                     */
44899 #define TIMER_INTSTAT_TMR51INT_Msk        (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
44900 #define TIMER_INTSTAT_TMR50INT_Pos        (10UL)                    /*!< TMR50INT (Bit 10)                                     */
44901 #define TIMER_INTSTAT_TMR50INT_Msk        (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
44902 #define TIMER_INTSTAT_TMR41INT_Pos        (9UL)                     /*!< TMR41INT (Bit 9)                                      */
44903 #define TIMER_INTSTAT_TMR41INT_Msk        (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
44904 #define TIMER_INTSTAT_TMR40INT_Pos        (8UL)                     /*!< TMR40INT (Bit 8)                                      */
44905 #define TIMER_INTSTAT_TMR40INT_Msk        (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
44906 #define TIMER_INTSTAT_TMR31INT_Pos        (7UL)                     /*!< TMR31INT (Bit 7)                                      */
44907 #define TIMER_INTSTAT_TMR31INT_Msk        (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
44908 #define TIMER_INTSTAT_TMR30INT_Pos        (6UL)                     /*!< TMR30INT (Bit 6)                                      */
44909 #define TIMER_INTSTAT_TMR30INT_Msk        (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
44910 #define TIMER_INTSTAT_TMR21INT_Pos        (5UL)                     /*!< TMR21INT (Bit 5)                                      */
44911 #define TIMER_INTSTAT_TMR21INT_Msk        (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
44912 #define TIMER_INTSTAT_TMR20INT_Pos        (4UL)                     /*!< TMR20INT (Bit 4)                                      */
44913 #define TIMER_INTSTAT_TMR20INT_Msk        (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
44914 #define TIMER_INTSTAT_TMR11INT_Pos        (3UL)                     /*!< TMR11INT (Bit 3)                                      */
44915 #define TIMER_INTSTAT_TMR11INT_Msk        (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
44916 #define TIMER_INTSTAT_TMR10INT_Pos        (2UL)                     /*!< TMR10INT (Bit 2)                                      */
44917 #define TIMER_INTSTAT_TMR10INT_Msk        (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
44918 #define TIMER_INTSTAT_TMR01INT_Pos        (1UL)                     /*!< TMR01INT (Bit 1)                                      */
44919 #define TIMER_INTSTAT_TMR01INT_Msk        (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
44920 #define TIMER_INTSTAT_TMR00INT_Pos        (0UL)                     /*!< TMR00INT (Bit 0)                                      */
44921 #define TIMER_INTSTAT_TMR00INT_Msk        (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
44922 /* ========================================================  INTCLR  ========================================================= */
44923 #define TIMER_INTCLR_TMR151INT_Pos        (31UL)                    /*!< TMR151INT (Bit 31)                                    */
44924 #define TIMER_INTCLR_TMR151INT_Msk        (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
44925 #define TIMER_INTCLR_TMR150INT_Pos        (30UL)                    /*!< TMR150INT (Bit 30)                                    */
44926 #define TIMER_INTCLR_TMR150INT_Msk        (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
44927 #define TIMER_INTCLR_TMR141INT_Pos        (29UL)                    /*!< TMR141INT (Bit 29)                                    */
44928 #define TIMER_INTCLR_TMR141INT_Msk        (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
44929 #define TIMER_INTCLR_TMR140INT_Pos        (28UL)                    /*!< TMR140INT (Bit 28)                                    */
44930 #define TIMER_INTCLR_TMR140INT_Msk        (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
44931 #define TIMER_INTCLR_TMR131INT_Pos        (27UL)                    /*!< TMR131INT (Bit 27)                                    */
44932 #define TIMER_INTCLR_TMR131INT_Msk        (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
44933 #define TIMER_INTCLR_TMR130INT_Pos        (26UL)                    /*!< TMR130INT (Bit 26)                                    */
44934 #define TIMER_INTCLR_TMR130INT_Msk        (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
44935 #define TIMER_INTCLR_TMR121INT_Pos        (25UL)                    /*!< TMR121INT (Bit 25)                                    */
44936 #define TIMER_INTCLR_TMR121INT_Msk        (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
44937 #define TIMER_INTCLR_TMR120INT_Pos        (24UL)                    /*!< TMR120INT (Bit 24)                                    */
44938 #define TIMER_INTCLR_TMR120INT_Msk        (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
44939 #define TIMER_INTCLR_TMR111INT_Pos        (23UL)                    /*!< TMR111INT (Bit 23)                                    */
44940 #define TIMER_INTCLR_TMR111INT_Msk        (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
44941 #define TIMER_INTCLR_TMR110INT_Pos        (22UL)                    /*!< TMR110INT (Bit 22)                                    */
44942 #define TIMER_INTCLR_TMR110INT_Msk        (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
44943 #define TIMER_INTCLR_TMR101INT_Pos        (21UL)                    /*!< TMR101INT (Bit 21)                                    */
44944 #define TIMER_INTCLR_TMR101INT_Msk        (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
44945 #define TIMER_INTCLR_TMR100INT_Pos        (20UL)                    /*!< TMR100INT (Bit 20)                                    */
44946 #define TIMER_INTCLR_TMR100INT_Msk        (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
44947 #define TIMER_INTCLR_TMR91INT_Pos         (19UL)                    /*!< TMR91INT (Bit 19)                                     */
44948 #define TIMER_INTCLR_TMR91INT_Msk         (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
44949 #define TIMER_INTCLR_TMR90INT_Pos         (18UL)                    /*!< TMR90INT (Bit 18)                                     */
44950 #define TIMER_INTCLR_TMR90INT_Msk         (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
44951 #define TIMER_INTCLR_TMR81INT_Pos         (17UL)                    /*!< TMR81INT (Bit 17)                                     */
44952 #define TIMER_INTCLR_TMR81INT_Msk         (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
44953 #define TIMER_INTCLR_TMR80INT_Pos         (16UL)                    /*!< TMR80INT (Bit 16)                                     */
44954 #define TIMER_INTCLR_TMR80INT_Msk         (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
44955 #define TIMER_INTCLR_TMR71INT_Pos         (15UL)                    /*!< TMR71INT (Bit 15)                                     */
44956 #define TIMER_INTCLR_TMR71INT_Msk         (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
44957 #define TIMER_INTCLR_TMR70INT_Pos         (14UL)                    /*!< TMR70INT (Bit 14)                                     */
44958 #define TIMER_INTCLR_TMR70INT_Msk         (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
44959 #define TIMER_INTCLR_TMR61INT_Pos         (13UL)                    /*!< TMR61INT (Bit 13)                                     */
44960 #define TIMER_INTCLR_TMR61INT_Msk         (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
44961 #define TIMER_INTCLR_TMR60INT_Pos         (12UL)                    /*!< TMR60INT (Bit 12)                                     */
44962 #define TIMER_INTCLR_TMR60INT_Msk         (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
44963 #define TIMER_INTCLR_TMR51INT_Pos         (11UL)                    /*!< TMR51INT (Bit 11)                                     */
44964 #define TIMER_INTCLR_TMR51INT_Msk         (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
44965 #define TIMER_INTCLR_TMR50INT_Pos         (10UL)                    /*!< TMR50INT (Bit 10)                                     */
44966 #define TIMER_INTCLR_TMR50INT_Msk         (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
44967 #define TIMER_INTCLR_TMR41INT_Pos         (9UL)                     /*!< TMR41INT (Bit 9)                                      */
44968 #define TIMER_INTCLR_TMR41INT_Msk         (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
44969 #define TIMER_INTCLR_TMR40INT_Pos         (8UL)                     /*!< TMR40INT (Bit 8)                                      */
44970 #define TIMER_INTCLR_TMR40INT_Msk         (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
44971 #define TIMER_INTCLR_TMR31INT_Pos         (7UL)                     /*!< TMR31INT (Bit 7)                                      */
44972 #define TIMER_INTCLR_TMR31INT_Msk         (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
44973 #define TIMER_INTCLR_TMR30INT_Pos         (6UL)                     /*!< TMR30INT (Bit 6)                                      */
44974 #define TIMER_INTCLR_TMR30INT_Msk         (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
44975 #define TIMER_INTCLR_TMR21INT_Pos         (5UL)                     /*!< TMR21INT (Bit 5)                                      */
44976 #define TIMER_INTCLR_TMR21INT_Msk         (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
44977 #define TIMER_INTCLR_TMR20INT_Pos         (4UL)                     /*!< TMR20INT (Bit 4)                                      */
44978 #define TIMER_INTCLR_TMR20INT_Msk         (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
44979 #define TIMER_INTCLR_TMR11INT_Pos         (3UL)                     /*!< TMR11INT (Bit 3)                                      */
44980 #define TIMER_INTCLR_TMR11INT_Msk         (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
44981 #define TIMER_INTCLR_TMR10INT_Pos         (2UL)                     /*!< TMR10INT (Bit 2)                                      */
44982 #define TIMER_INTCLR_TMR10INT_Msk         (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
44983 #define TIMER_INTCLR_TMR01INT_Pos         (1UL)                     /*!< TMR01INT (Bit 1)                                      */
44984 #define TIMER_INTCLR_TMR01INT_Msk         (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
44985 #define TIMER_INTCLR_TMR00INT_Pos         (0UL)                     /*!< TMR00INT (Bit 0)                                      */
44986 #define TIMER_INTCLR_TMR00INT_Msk         (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
44987 /* ========================================================  INTSET  ========================================================= */
44988 #define TIMER_INTSET_TMR151INT_Pos        (31UL)                    /*!< TMR151INT (Bit 31)                                    */
44989 #define TIMER_INTSET_TMR151INT_Msk        (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
44990 #define TIMER_INTSET_TMR150INT_Pos        (30UL)                    /*!< TMR150INT (Bit 30)                                    */
44991 #define TIMER_INTSET_TMR150INT_Msk        (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
44992 #define TIMER_INTSET_TMR141INT_Pos        (29UL)                    /*!< TMR141INT (Bit 29)                                    */
44993 #define TIMER_INTSET_TMR141INT_Msk        (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
44994 #define TIMER_INTSET_TMR140INT_Pos        (28UL)                    /*!< TMR140INT (Bit 28)                                    */
44995 #define TIMER_INTSET_TMR140INT_Msk        (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
44996 #define TIMER_INTSET_TMR131INT_Pos        (27UL)                    /*!< TMR131INT (Bit 27)                                    */
44997 #define TIMER_INTSET_TMR131INT_Msk        (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
44998 #define TIMER_INTSET_TMR130INT_Pos        (26UL)                    /*!< TMR130INT (Bit 26)                                    */
44999 #define TIMER_INTSET_TMR130INT_Msk        (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
45000 #define TIMER_INTSET_TMR121INT_Pos        (25UL)                    /*!< TMR121INT (Bit 25)                                    */
45001 #define TIMER_INTSET_TMR121INT_Msk        (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
45002 #define TIMER_INTSET_TMR120INT_Pos        (24UL)                    /*!< TMR120INT (Bit 24)                                    */
45003 #define TIMER_INTSET_TMR120INT_Msk        (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
45004 #define TIMER_INTSET_TMR111INT_Pos        (23UL)                    /*!< TMR111INT (Bit 23)                                    */
45005 #define TIMER_INTSET_TMR111INT_Msk        (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
45006 #define TIMER_INTSET_TMR110INT_Pos        (22UL)                    /*!< TMR110INT (Bit 22)                                    */
45007 #define TIMER_INTSET_TMR110INT_Msk        (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
45008 #define TIMER_INTSET_TMR101INT_Pos        (21UL)                    /*!< TMR101INT (Bit 21)                                    */
45009 #define TIMER_INTSET_TMR101INT_Msk        (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
45010 #define TIMER_INTSET_TMR100INT_Pos        (20UL)                    /*!< TMR100INT (Bit 20)                                    */
45011 #define TIMER_INTSET_TMR100INT_Msk        (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
45012 #define TIMER_INTSET_TMR91INT_Pos         (19UL)                    /*!< TMR91INT (Bit 19)                                     */
45013 #define TIMER_INTSET_TMR91INT_Msk         (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
45014 #define TIMER_INTSET_TMR90INT_Pos         (18UL)                    /*!< TMR90INT (Bit 18)                                     */
45015 #define TIMER_INTSET_TMR90INT_Msk         (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
45016 #define TIMER_INTSET_TMR81INT_Pos         (17UL)                    /*!< TMR81INT (Bit 17)                                     */
45017 #define TIMER_INTSET_TMR81INT_Msk         (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
45018 #define TIMER_INTSET_TMR80INT_Pos         (16UL)                    /*!< TMR80INT (Bit 16)                                     */
45019 #define TIMER_INTSET_TMR80INT_Msk         (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
45020 #define TIMER_INTSET_TMR71INT_Pos         (15UL)                    /*!< TMR71INT (Bit 15)                                     */
45021 #define TIMER_INTSET_TMR71INT_Msk         (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
45022 #define TIMER_INTSET_TMR70INT_Pos         (14UL)                    /*!< TMR70INT (Bit 14)                                     */
45023 #define TIMER_INTSET_TMR70INT_Msk         (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
45024 #define TIMER_INTSET_TMR61INT_Pos         (13UL)                    /*!< TMR61INT (Bit 13)                                     */
45025 #define TIMER_INTSET_TMR61INT_Msk         (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
45026 #define TIMER_INTSET_TMR60INT_Pos         (12UL)                    /*!< TMR60INT (Bit 12)                                     */
45027 #define TIMER_INTSET_TMR60INT_Msk         (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
45028 #define TIMER_INTSET_TMR51INT_Pos         (11UL)                    /*!< TMR51INT (Bit 11)                                     */
45029 #define TIMER_INTSET_TMR51INT_Msk         (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
45030 #define TIMER_INTSET_TMR50INT_Pos         (10UL)                    /*!< TMR50INT (Bit 10)                                     */
45031 #define TIMER_INTSET_TMR50INT_Msk         (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
45032 #define TIMER_INTSET_TMR41INT_Pos         (9UL)                     /*!< TMR41INT (Bit 9)                                      */
45033 #define TIMER_INTSET_TMR41INT_Msk         (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
45034 #define TIMER_INTSET_TMR40INT_Pos         (8UL)                     /*!< TMR40INT (Bit 8)                                      */
45035 #define TIMER_INTSET_TMR40INT_Msk         (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
45036 #define TIMER_INTSET_TMR31INT_Pos         (7UL)                     /*!< TMR31INT (Bit 7)                                      */
45037 #define TIMER_INTSET_TMR31INT_Msk         (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
45038 #define TIMER_INTSET_TMR30INT_Pos         (6UL)                     /*!< TMR30INT (Bit 6)                                      */
45039 #define TIMER_INTSET_TMR30INT_Msk         (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
45040 #define TIMER_INTSET_TMR21INT_Pos         (5UL)                     /*!< TMR21INT (Bit 5)                                      */
45041 #define TIMER_INTSET_TMR21INT_Msk         (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
45042 #define TIMER_INTSET_TMR20INT_Pos         (4UL)                     /*!< TMR20INT (Bit 4)                                      */
45043 #define TIMER_INTSET_TMR20INT_Msk         (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
45044 #define TIMER_INTSET_TMR11INT_Pos         (3UL)                     /*!< TMR11INT (Bit 3)                                      */
45045 #define TIMER_INTSET_TMR11INT_Msk         (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
45046 #define TIMER_INTSET_TMR10INT_Pos         (2UL)                     /*!< TMR10INT (Bit 2)                                      */
45047 #define TIMER_INTSET_TMR10INT_Msk         (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
45048 #define TIMER_INTSET_TMR01INT_Pos         (1UL)                     /*!< TMR01INT (Bit 1)                                      */
45049 #define TIMER_INTSET_TMR01INT_Msk         (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
45050 #define TIMER_INTSET_TMR00INT_Pos         (0UL)                     /*!< TMR00INT (Bit 0)                                      */
45051 #define TIMER_INTSET_TMR00INT_Msk         (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
45052 /* ========================================================  OUTCFG0  ======================================================== */
45053 #define TIMER_OUTCFG0_OUTCFG3_Pos         (24UL)                    /*!< OUTCFG3 (Bit 24)                                      */
45054 #define TIMER_OUTCFG0_OUTCFG3_Msk         (0x3f000000UL)            /*!< OUTCFG3 (Bitfield-Mask: 0x3f)                         */
45055 #define TIMER_OUTCFG0_OUTCFG2_Pos         (16UL)                    /*!< OUTCFG2 (Bit 16)                                      */
45056 #define TIMER_OUTCFG0_OUTCFG2_Msk         (0x3f0000UL)              /*!< OUTCFG2 (Bitfield-Mask: 0x3f)                         */
45057 #define TIMER_OUTCFG0_OUTCFG1_Pos         (8UL)                     /*!< OUTCFG1 (Bit 8)                                       */
45058 #define TIMER_OUTCFG0_OUTCFG1_Msk         (0x3f00UL)                /*!< OUTCFG1 (Bitfield-Mask: 0x3f)                         */
45059 #define TIMER_OUTCFG0_OUTCFG0_Pos         (0UL)                     /*!< OUTCFG0 (Bit 0)                                       */
45060 #define TIMER_OUTCFG0_OUTCFG0_Msk         (0x3fUL)                  /*!< OUTCFG0 (Bitfield-Mask: 0x3f)                         */
45061 /* ========================================================  OUTCFG1  ======================================================== */
45062 #define TIMER_OUTCFG1_OUTCFG7_Pos         (24UL)                    /*!< OUTCFG7 (Bit 24)                                      */
45063 #define TIMER_OUTCFG1_OUTCFG7_Msk         (0x3f000000UL)            /*!< OUTCFG7 (Bitfield-Mask: 0x3f)                         */
45064 #define TIMER_OUTCFG1_OUTCFG6_Pos         (16UL)                    /*!< OUTCFG6 (Bit 16)                                      */
45065 #define TIMER_OUTCFG1_OUTCFG6_Msk         (0x3f0000UL)              /*!< OUTCFG6 (Bitfield-Mask: 0x3f)                         */
45066 #define TIMER_OUTCFG1_OUTCFG5_Pos         (8UL)                     /*!< OUTCFG5 (Bit 8)                                       */
45067 #define TIMER_OUTCFG1_OUTCFG5_Msk         (0x3f00UL)                /*!< OUTCFG5 (Bitfield-Mask: 0x3f)                         */
45068 #define TIMER_OUTCFG1_OUTCFG4_Pos         (0UL)                     /*!< OUTCFG4 (Bit 0)                                       */
45069 #define TIMER_OUTCFG1_OUTCFG4_Msk         (0x3fUL)                  /*!< OUTCFG4 (Bitfield-Mask: 0x3f)                         */
45070 /* ========================================================  OUTCFG2  ======================================================== */
45071 #define TIMER_OUTCFG2_OUTCFG11_Pos        (24UL)                    /*!< OUTCFG11 (Bit 24)                                     */
45072 #define TIMER_OUTCFG2_OUTCFG11_Msk        (0x3f000000UL)            /*!< OUTCFG11 (Bitfield-Mask: 0x3f)                        */
45073 #define TIMER_OUTCFG2_OUTCFG10_Pos        (16UL)                    /*!< OUTCFG10 (Bit 16)                                     */
45074 #define TIMER_OUTCFG2_OUTCFG10_Msk        (0x3f0000UL)              /*!< OUTCFG10 (Bitfield-Mask: 0x3f)                        */
45075 #define TIMER_OUTCFG2_OUTCFG9_Pos         (8UL)                     /*!< OUTCFG9 (Bit 8)                                       */
45076 #define TIMER_OUTCFG2_OUTCFG9_Msk         (0x3f00UL)                /*!< OUTCFG9 (Bitfield-Mask: 0x3f)                         */
45077 #define TIMER_OUTCFG2_OUTCFG8_Pos         (0UL)                     /*!< OUTCFG8 (Bit 0)                                       */
45078 #define TIMER_OUTCFG2_OUTCFG8_Msk         (0x3fUL)                  /*!< OUTCFG8 (Bitfield-Mask: 0x3f)                         */
45079 /* ========================================================  OUTCFG3  ======================================================== */
45080 #define TIMER_OUTCFG3_OUTCFG15_Pos        (24UL)                    /*!< OUTCFG15 (Bit 24)                                     */
45081 #define TIMER_OUTCFG3_OUTCFG15_Msk        (0x3f000000UL)            /*!< OUTCFG15 (Bitfield-Mask: 0x3f)                        */
45082 #define TIMER_OUTCFG3_OUTCFG14_Pos        (16UL)                    /*!< OUTCFG14 (Bit 16)                                     */
45083 #define TIMER_OUTCFG3_OUTCFG14_Msk        (0x3f0000UL)              /*!< OUTCFG14 (Bitfield-Mask: 0x3f)                        */
45084 #define TIMER_OUTCFG3_OUTCFG13_Pos        (8UL)                     /*!< OUTCFG13 (Bit 8)                                      */
45085 #define TIMER_OUTCFG3_OUTCFG13_Msk        (0x3f00UL)                /*!< OUTCFG13 (Bitfield-Mask: 0x3f)                        */
45086 #define TIMER_OUTCFG3_OUTCFG12_Pos        (0UL)                     /*!< OUTCFG12 (Bit 0)                                      */
45087 #define TIMER_OUTCFG3_OUTCFG12_Msk        (0x3fUL)                  /*!< OUTCFG12 (Bitfield-Mask: 0x3f)                        */
45088 /* ========================================================  OUTCFG4  ======================================================== */
45089 #define TIMER_OUTCFG4_OUTCFG19_Pos        (24UL)                    /*!< OUTCFG19 (Bit 24)                                     */
45090 #define TIMER_OUTCFG4_OUTCFG19_Msk        (0x3f000000UL)            /*!< OUTCFG19 (Bitfield-Mask: 0x3f)                        */
45091 #define TIMER_OUTCFG4_OUTCFG18_Pos        (16UL)                    /*!< OUTCFG18 (Bit 16)                                     */
45092 #define TIMER_OUTCFG4_OUTCFG18_Msk        (0x3f0000UL)              /*!< OUTCFG18 (Bitfield-Mask: 0x3f)                        */
45093 #define TIMER_OUTCFG4_OUTCFG17_Pos        (8UL)                     /*!< OUTCFG17 (Bit 8)                                      */
45094 #define TIMER_OUTCFG4_OUTCFG17_Msk        (0x3f00UL)                /*!< OUTCFG17 (Bitfield-Mask: 0x3f)                        */
45095 #define TIMER_OUTCFG4_OUTCFG16_Pos        (0UL)                     /*!< OUTCFG16 (Bit 0)                                      */
45096 #define TIMER_OUTCFG4_OUTCFG16_Msk        (0x3fUL)                  /*!< OUTCFG16 (Bitfield-Mask: 0x3f)                        */
45097 /* ========================================================  OUTCFG5  ======================================================== */
45098 #define TIMER_OUTCFG5_OUTCFG23_Pos        (24UL)                    /*!< OUTCFG23 (Bit 24)                                     */
45099 #define TIMER_OUTCFG5_OUTCFG23_Msk        (0x3f000000UL)            /*!< OUTCFG23 (Bitfield-Mask: 0x3f)                        */
45100 #define TIMER_OUTCFG5_OUTCFG22_Pos        (16UL)                    /*!< OUTCFG22 (Bit 16)                                     */
45101 #define TIMER_OUTCFG5_OUTCFG22_Msk        (0x3f0000UL)              /*!< OUTCFG22 (Bitfield-Mask: 0x3f)                        */
45102 #define TIMER_OUTCFG5_OUTCFG21_Pos        (8UL)                     /*!< OUTCFG21 (Bit 8)                                      */
45103 #define TIMER_OUTCFG5_OUTCFG21_Msk        (0x3f00UL)                /*!< OUTCFG21 (Bitfield-Mask: 0x3f)                        */
45104 #define TIMER_OUTCFG5_OUTCFG20_Pos        (0UL)                     /*!< OUTCFG20 (Bit 0)                                      */
45105 #define TIMER_OUTCFG5_OUTCFG20_Msk        (0x3fUL)                  /*!< OUTCFG20 (Bitfield-Mask: 0x3f)                        */
45106 /* ========================================================  OUTCFG6  ======================================================== */
45107 #define TIMER_OUTCFG6_OUTCFG27_Pos        (24UL)                    /*!< OUTCFG27 (Bit 24)                                     */
45108 #define TIMER_OUTCFG6_OUTCFG27_Msk        (0x3f000000UL)            /*!< OUTCFG27 (Bitfield-Mask: 0x3f)                        */
45109 #define TIMER_OUTCFG6_OUTCFG26_Pos        (16UL)                    /*!< OUTCFG26 (Bit 16)                                     */
45110 #define TIMER_OUTCFG6_OUTCFG26_Msk        (0x3f0000UL)              /*!< OUTCFG26 (Bitfield-Mask: 0x3f)                        */
45111 #define TIMER_OUTCFG6_OUTCFG25_Pos        (8UL)                     /*!< OUTCFG25 (Bit 8)                                      */
45112 #define TIMER_OUTCFG6_OUTCFG25_Msk        (0x3f00UL)                /*!< OUTCFG25 (Bitfield-Mask: 0x3f)                        */
45113 #define TIMER_OUTCFG6_OUTCFG24_Pos        (0UL)                     /*!< OUTCFG24 (Bit 0)                                      */
45114 #define TIMER_OUTCFG6_OUTCFG24_Msk        (0x3fUL)                  /*!< OUTCFG24 (Bitfield-Mask: 0x3f)                        */
45115 /* ========================================================  OUTCFG7  ======================================================== */
45116 #define TIMER_OUTCFG7_OUTCFG31_Pos        (24UL)                    /*!< OUTCFG31 (Bit 24)                                     */
45117 #define TIMER_OUTCFG7_OUTCFG31_Msk        (0x3f000000UL)            /*!< OUTCFG31 (Bitfield-Mask: 0x3f)                        */
45118 #define TIMER_OUTCFG7_OUTCFG30_Pos        (16UL)                    /*!< OUTCFG30 (Bit 16)                                     */
45119 #define TIMER_OUTCFG7_OUTCFG30_Msk        (0x3f0000UL)              /*!< OUTCFG30 (Bitfield-Mask: 0x3f)                        */
45120 #define TIMER_OUTCFG7_OUTCFG29_Pos        (8UL)                     /*!< OUTCFG29 (Bit 8)                                      */
45121 #define TIMER_OUTCFG7_OUTCFG29_Msk        (0x3f00UL)                /*!< OUTCFG29 (Bitfield-Mask: 0x3f)                        */
45122 #define TIMER_OUTCFG7_OUTCFG28_Pos        (0UL)                     /*!< OUTCFG28 (Bit 0)                                      */
45123 #define TIMER_OUTCFG7_OUTCFG28_Msk        (0x3fUL)                  /*!< OUTCFG28 (Bitfield-Mask: 0x3f)                        */
45124 /* ========================================================  OUTCFG8  ======================================================== */
45125 #define TIMER_OUTCFG8_OUTCFG35_Pos        (24UL)                    /*!< OUTCFG35 (Bit 24)                                     */
45126 #define TIMER_OUTCFG8_OUTCFG35_Msk        (0x3f000000UL)            /*!< OUTCFG35 (Bitfield-Mask: 0x3f)                        */
45127 #define TIMER_OUTCFG8_OUTCFG34_Pos        (16UL)                    /*!< OUTCFG34 (Bit 16)                                     */
45128 #define TIMER_OUTCFG8_OUTCFG34_Msk        (0x3f0000UL)              /*!< OUTCFG34 (Bitfield-Mask: 0x3f)                        */
45129 #define TIMER_OUTCFG8_OUTCFG33_Pos        (8UL)                     /*!< OUTCFG33 (Bit 8)                                      */
45130 #define TIMER_OUTCFG8_OUTCFG33_Msk        (0x3f00UL)                /*!< OUTCFG33 (Bitfield-Mask: 0x3f)                        */
45131 #define TIMER_OUTCFG8_OUTCFG32_Pos        (0UL)                     /*!< OUTCFG32 (Bit 0)                                      */
45132 #define TIMER_OUTCFG8_OUTCFG32_Msk        (0x3fUL)                  /*!< OUTCFG32 (Bitfield-Mask: 0x3f)                        */
45133 /* ========================================================  OUTCFG9  ======================================================== */
45134 #define TIMER_OUTCFG9_OUTCFG39_Pos        (24UL)                    /*!< OUTCFG39 (Bit 24)                                     */
45135 #define TIMER_OUTCFG9_OUTCFG39_Msk        (0x3f000000UL)            /*!< OUTCFG39 (Bitfield-Mask: 0x3f)                        */
45136 #define TIMER_OUTCFG9_OUTCFG38_Pos        (16UL)                    /*!< OUTCFG38 (Bit 16)                                     */
45137 #define TIMER_OUTCFG9_OUTCFG38_Msk        (0x3f0000UL)              /*!< OUTCFG38 (Bitfield-Mask: 0x3f)                        */
45138 #define TIMER_OUTCFG9_OUTCFG37_Pos        (8UL)                     /*!< OUTCFG37 (Bit 8)                                      */
45139 #define TIMER_OUTCFG9_OUTCFG37_Msk        (0x3f00UL)                /*!< OUTCFG37 (Bitfield-Mask: 0x3f)                        */
45140 #define TIMER_OUTCFG9_OUTCFG36_Pos        (0UL)                     /*!< OUTCFG36 (Bit 0)                                      */
45141 #define TIMER_OUTCFG9_OUTCFG36_Msk        (0x3fUL)                  /*!< OUTCFG36 (Bitfield-Mask: 0x3f)                        */
45142 /* =======================================================  OUTCFG10  ======================================================== */
45143 #define TIMER_OUTCFG10_OUTCFG43_Pos       (24UL)                    /*!< OUTCFG43 (Bit 24)                                     */
45144 #define TIMER_OUTCFG10_OUTCFG43_Msk       (0x3f000000UL)            /*!< OUTCFG43 (Bitfield-Mask: 0x3f)                        */
45145 #define TIMER_OUTCFG10_OUTCFG42_Pos       (16UL)                    /*!< OUTCFG42 (Bit 16)                                     */
45146 #define TIMER_OUTCFG10_OUTCFG42_Msk       (0x3f0000UL)              /*!< OUTCFG42 (Bitfield-Mask: 0x3f)                        */
45147 #define TIMER_OUTCFG10_OUTCFG41_Pos       (8UL)                     /*!< OUTCFG41 (Bit 8)                                      */
45148 #define TIMER_OUTCFG10_OUTCFG41_Msk       (0x3f00UL)                /*!< OUTCFG41 (Bitfield-Mask: 0x3f)                        */
45149 #define TIMER_OUTCFG10_OUTCFG40_Pos       (0UL)                     /*!< OUTCFG40 (Bit 0)                                      */
45150 #define TIMER_OUTCFG10_OUTCFG40_Msk       (0x3fUL)                  /*!< OUTCFG40 (Bitfield-Mask: 0x3f)                        */
45151 /* =======================================================  OUTCFG11  ======================================================== */
45152 #define TIMER_OUTCFG11_OUTCFG47_Pos       (24UL)                    /*!< OUTCFG47 (Bit 24)                                     */
45153 #define TIMER_OUTCFG11_OUTCFG47_Msk       (0x3f000000UL)            /*!< OUTCFG47 (Bitfield-Mask: 0x3f)                        */
45154 #define TIMER_OUTCFG11_OUTCFG46_Pos       (16UL)                    /*!< OUTCFG46 (Bit 16)                                     */
45155 #define TIMER_OUTCFG11_OUTCFG46_Msk       (0x3f0000UL)              /*!< OUTCFG46 (Bitfield-Mask: 0x3f)                        */
45156 #define TIMER_OUTCFG11_OUTCFG45_Pos       (8UL)                     /*!< OUTCFG45 (Bit 8)                                      */
45157 #define TIMER_OUTCFG11_OUTCFG45_Msk       (0x3f00UL)                /*!< OUTCFG45 (Bitfield-Mask: 0x3f)                        */
45158 #define TIMER_OUTCFG11_OUTCFG44_Pos       (0UL)                     /*!< OUTCFG44 (Bit 0)                                      */
45159 #define TIMER_OUTCFG11_OUTCFG44_Msk       (0x3fUL)                  /*!< OUTCFG44 (Bitfield-Mask: 0x3f)                        */
45160 /* =======================================================  OUTCFG12  ======================================================== */
45161 #define TIMER_OUTCFG12_OUTCFG51_Pos       (24UL)                    /*!< OUTCFG51 (Bit 24)                                     */
45162 #define TIMER_OUTCFG12_OUTCFG51_Msk       (0x3f000000UL)            /*!< OUTCFG51 (Bitfield-Mask: 0x3f)                        */
45163 #define TIMER_OUTCFG12_OUTCFG50_Pos       (16UL)                    /*!< OUTCFG50 (Bit 16)                                     */
45164 #define TIMER_OUTCFG12_OUTCFG50_Msk       (0x3f0000UL)              /*!< OUTCFG50 (Bitfield-Mask: 0x3f)                        */
45165 #define TIMER_OUTCFG12_OUTCFG49_Pos       (8UL)                     /*!< OUTCFG49 (Bit 8)                                      */
45166 #define TIMER_OUTCFG12_OUTCFG49_Msk       (0x3f00UL)                /*!< OUTCFG49 (Bitfield-Mask: 0x3f)                        */
45167 #define TIMER_OUTCFG12_OUTCFG48_Pos       (0UL)                     /*!< OUTCFG48 (Bit 0)                                      */
45168 #define TIMER_OUTCFG12_OUTCFG48_Msk       (0x3fUL)                  /*!< OUTCFG48 (Bitfield-Mask: 0x3f)                        */
45169 /* =======================================================  OUTCFG13  ======================================================== */
45170 #define TIMER_OUTCFG13_OUTCFG55_Pos       (24UL)                    /*!< OUTCFG55 (Bit 24)                                     */
45171 #define TIMER_OUTCFG13_OUTCFG55_Msk       (0x3f000000UL)            /*!< OUTCFG55 (Bitfield-Mask: 0x3f)                        */
45172 #define TIMER_OUTCFG13_OUTCFG54_Pos       (16UL)                    /*!< OUTCFG54 (Bit 16)                                     */
45173 #define TIMER_OUTCFG13_OUTCFG54_Msk       (0x3f0000UL)              /*!< OUTCFG54 (Bitfield-Mask: 0x3f)                        */
45174 #define TIMER_OUTCFG13_OUTCFG53_Pos       (8UL)                     /*!< OUTCFG53 (Bit 8)                                      */
45175 #define TIMER_OUTCFG13_OUTCFG53_Msk       (0x3f00UL)                /*!< OUTCFG53 (Bitfield-Mask: 0x3f)                        */
45176 #define TIMER_OUTCFG13_OUTCFG52_Pos       (0UL)                     /*!< OUTCFG52 (Bit 0)                                      */
45177 #define TIMER_OUTCFG13_OUTCFG52_Msk       (0x3fUL)                  /*!< OUTCFG52 (Bitfield-Mask: 0x3f)                        */
45178 /* =======================================================  OUTCFG14  ======================================================== */
45179 #define TIMER_OUTCFG14_OUTCFG59_Pos       (24UL)                    /*!< OUTCFG59 (Bit 24)                                     */
45180 #define TIMER_OUTCFG14_OUTCFG59_Msk       (0x3f000000UL)            /*!< OUTCFG59 (Bitfield-Mask: 0x3f)                        */
45181 #define TIMER_OUTCFG14_OUTCFG58_Pos       (16UL)                    /*!< OUTCFG58 (Bit 16)                                     */
45182 #define TIMER_OUTCFG14_OUTCFG58_Msk       (0x3f0000UL)              /*!< OUTCFG58 (Bitfield-Mask: 0x3f)                        */
45183 #define TIMER_OUTCFG14_OUTCFG57_Pos       (8UL)                     /*!< OUTCFG57 (Bit 8)                                      */
45184 #define TIMER_OUTCFG14_OUTCFG57_Msk       (0x3f00UL)                /*!< OUTCFG57 (Bitfield-Mask: 0x3f)                        */
45185 #define TIMER_OUTCFG14_OUTCFG56_Pos       (0UL)                     /*!< OUTCFG56 (Bit 0)                                      */
45186 #define TIMER_OUTCFG14_OUTCFG56_Msk       (0x3fUL)                  /*!< OUTCFG56 (Bitfield-Mask: 0x3f)                        */
45187 /* =======================================================  OUTCFG15  ======================================================== */
45188 #define TIMER_OUTCFG15_OUTCFG63_Pos       (24UL)                    /*!< OUTCFG63 (Bit 24)                                     */
45189 #define TIMER_OUTCFG15_OUTCFG63_Msk       (0x3f000000UL)            /*!< OUTCFG63 (Bitfield-Mask: 0x3f)                        */
45190 #define TIMER_OUTCFG15_OUTCFG62_Pos       (16UL)                    /*!< OUTCFG62 (Bit 16)                                     */
45191 #define TIMER_OUTCFG15_OUTCFG62_Msk       (0x3f0000UL)              /*!< OUTCFG62 (Bitfield-Mask: 0x3f)                        */
45192 #define TIMER_OUTCFG15_OUTCFG61_Pos       (8UL)                     /*!< OUTCFG61 (Bit 8)                                      */
45193 #define TIMER_OUTCFG15_OUTCFG61_Msk       (0x3f00UL)                /*!< OUTCFG61 (Bitfield-Mask: 0x3f)                        */
45194 #define TIMER_OUTCFG15_OUTCFG60_Pos       (0UL)                     /*!< OUTCFG60 (Bit 0)                                      */
45195 #define TIMER_OUTCFG15_OUTCFG60_Msk       (0x3fUL)                  /*!< OUTCFG60 (Bitfield-Mask: 0x3f)                        */
45196 /* =======================================================  OUTCFG16  ======================================================== */
45197 #define TIMER_OUTCFG16_OUTCFG67_Pos       (24UL)                    /*!< OUTCFG67 (Bit 24)                                     */
45198 #define TIMER_OUTCFG16_OUTCFG67_Msk       (0x3f000000UL)            /*!< OUTCFG67 (Bitfield-Mask: 0x3f)                        */
45199 #define TIMER_OUTCFG16_OUTCFG66_Pos       (16UL)                    /*!< OUTCFG66 (Bit 16)                                     */
45200 #define TIMER_OUTCFG16_OUTCFG66_Msk       (0x3f0000UL)              /*!< OUTCFG66 (Bitfield-Mask: 0x3f)                        */
45201 #define TIMER_OUTCFG16_OUTCFG65_Pos       (8UL)                     /*!< OUTCFG65 (Bit 8)                                      */
45202 #define TIMER_OUTCFG16_OUTCFG65_Msk       (0x3f00UL)                /*!< OUTCFG65 (Bitfield-Mask: 0x3f)                        */
45203 #define TIMER_OUTCFG16_OUTCFG64_Pos       (0UL)                     /*!< OUTCFG64 (Bit 0)                                      */
45204 #define TIMER_OUTCFG16_OUTCFG64_Msk       (0x3fUL)                  /*!< OUTCFG64 (Bitfield-Mask: 0x3f)                        */
45205 /* =======================================================  OUTCFG17  ======================================================== */
45206 #define TIMER_OUTCFG17_OUTCFG71_Pos       (24UL)                    /*!< OUTCFG71 (Bit 24)                                     */
45207 #define TIMER_OUTCFG17_OUTCFG71_Msk       (0x3f000000UL)            /*!< OUTCFG71 (Bitfield-Mask: 0x3f)                        */
45208 #define TIMER_OUTCFG17_OUTCFG70_Pos       (16UL)                    /*!< OUTCFG70 (Bit 16)                                     */
45209 #define TIMER_OUTCFG17_OUTCFG70_Msk       (0x3f0000UL)              /*!< OUTCFG70 (Bitfield-Mask: 0x3f)                        */
45210 #define TIMER_OUTCFG17_OUTCFG69_Pos       (8UL)                     /*!< OUTCFG69 (Bit 8)                                      */
45211 #define TIMER_OUTCFG17_OUTCFG69_Msk       (0x3f00UL)                /*!< OUTCFG69 (Bitfield-Mask: 0x3f)                        */
45212 #define TIMER_OUTCFG17_OUTCFG68_Pos       (0UL)                     /*!< OUTCFG68 (Bit 0)                                      */
45213 #define TIMER_OUTCFG17_OUTCFG68_Msk       (0x3fUL)                  /*!< OUTCFG68 (Bitfield-Mask: 0x3f)                        */
45214 /* =======================================================  OUTCFG18  ======================================================== */
45215 #define TIMER_OUTCFG18_OUTCFG75_Pos       (24UL)                    /*!< OUTCFG75 (Bit 24)                                     */
45216 #define TIMER_OUTCFG18_OUTCFG75_Msk       (0x3f000000UL)            /*!< OUTCFG75 (Bitfield-Mask: 0x3f)                        */
45217 #define TIMER_OUTCFG18_OUTCFG74_Pos       (16UL)                    /*!< OUTCFG74 (Bit 16)                                     */
45218 #define TIMER_OUTCFG18_OUTCFG74_Msk       (0x3f0000UL)              /*!< OUTCFG74 (Bitfield-Mask: 0x3f)                        */
45219 #define TIMER_OUTCFG18_OUTCFG73_Pos       (8UL)                     /*!< OUTCFG73 (Bit 8)                                      */
45220 #define TIMER_OUTCFG18_OUTCFG73_Msk       (0x3f00UL)                /*!< OUTCFG73 (Bitfield-Mask: 0x3f)                        */
45221 #define TIMER_OUTCFG18_OUTCFG72_Pos       (0UL)                     /*!< OUTCFG72 (Bit 0)                                      */
45222 #define TIMER_OUTCFG18_OUTCFG72_Msk       (0x3fUL)                  /*!< OUTCFG72 (Bitfield-Mask: 0x3f)                        */
45223 /* =======================================================  OUTCFG19  ======================================================== */
45224 #define TIMER_OUTCFG19_OUTCFG79_Pos       (24UL)                    /*!< OUTCFG79 (Bit 24)                                     */
45225 #define TIMER_OUTCFG19_OUTCFG79_Msk       (0x3f000000UL)            /*!< OUTCFG79 (Bitfield-Mask: 0x3f)                        */
45226 #define TIMER_OUTCFG19_OUTCFG78_Pos       (16UL)                    /*!< OUTCFG78 (Bit 16)                                     */
45227 #define TIMER_OUTCFG19_OUTCFG78_Msk       (0x3f0000UL)              /*!< OUTCFG78 (Bitfield-Mask: 0x3f)                        */
45228 #define TIMER_OUTCFG19_OUTCFG77_Pos       (8UL)                     /*!< OUTCFG77 (Bit 8)                                      */
45229 #define TIMER_OUTCFG19_OUTCFG77_Msk       (0x3f00UL)                /*!< OUTCFG77 (Bitfield-Mask: 0x3f)                        */
45230 #define TIMER_OUTCFG19_OUTCFG76_Pos       (0UL)                     /*!< OUTCFG76 (Bit 0)                                      */
45231 #define TIMER_OUTCFG19_OUTCFG76_Msk       (0x3fUL)                  /*!< OUTCFG76 (Bitfield-Mask: 0x3f)                        */
45232 /* =======================================================  OUTCFG20  ======================================================== */
45233 #define TIMER_OUTCFG20_OUTCFG83_Pos       (24UL)                    /*!< OUTCFG83 (Bit 24)                                     */
45234 #define TIMER_OUTCFG20_OUTCFG83_Msk       (0x3f000000UL)            /*!< OUTCFG83 (Bitfield-Mask: 0x3f)                        */
45235 #define TIMER_OUTCFG20_OUTCFG82_Pos       (16UL)                    /*!< OUTCFG82 (Bit 16)                                     */
45236 #define TIMER_OUTCFG20_OUTCFG82_Msk       (0x3f0000UL)              /*!< OUTCFG82 (Bitfield-Mask: 0x3f)                        */
45237 #define TIMER_OUTCFG20_OUTCFG81_Pos       (8UL)                     /*!< OUTCFG81 (Bit 8)                                      */
45238 #define TIMER_OUTCFG20_OUTCFG81_Msk       (0x3f00UL)                /*!< OUTCFG81 (Bitfield-Mask: 0x3f)                        */
45239 #define TIMER_OUTCFG20_OUTCFG80_Pos       (0UL)                     /*!< OUTCFG80 (Bit 0)                                      */
45240 #define TIMER_OUTCFG20_OUTCFG80_Msk       (0x3fUL)                  /*!< OUTCFG80 (Bitfield-Mask: 0x3f)                        */
45241 /* =======================================================  OUTCFG21  ======================================================== */
45242 #define TIMER_OUTCFG21_OUTCFG87_Pos       (24UL)                    /*!< OUTCFG87 (Bit 24)                                     */
45243 #define TIMER_OUTCFG21_OUTCFG87_Msk       (0x3f000000UL)            /*!< OUTCFG87 (Bitfield-Mask: 0x3f)                        */
45244 #define TIMER_OUTCFG21_OUTCFG86_Pos       (16UL)                    /*!< OUTCFG86 (Bit 16)                                     */
45245 #define TIMER_OUTCFG21_OUTCFG86_Msk       (0x3f0000UL)              /*!< OUTCFG86 (Bitfield-Mask: 0x3f)                        */
45246 #define TIMER_OUTCFG21_OUTCFG85_Pos       (8UL)                     /*!< OUTCFG85 (Bit 8)                                      */
45247 #define TIMER_OUTCFG21_OUTCFG85_Msk       (0x3f00UL)                /*!< OUTCFG85 (Bitfield-Mask: 0x3f)                        */
45248 #define TIMER_OUTCFG21_OUTCFG84_Pos       (0UL)                     /*!< OUTCFG84 (Bit 0)                                      */
45249 #define TIMER_OUTCFG21_OUTCFG84_Msk       (0x3fUL)                  /*!< OUTCFG84 (Bitfield-Mask: 0x3f)                        */
45250 /* =======================================================  OUTCFG22  ======================================================== */
45251 #define TIMER_OUTCFG22_OUTCFG91_Pos       (24UL)                    /*!< OUTCFG91 (Bit 24)                                     */
45252 #define TIMER_OUTCFG22_OUTCFG91_Msk       (0x3f000000UL)            /*!< OUTCFG91 (Bitfield-Mask: 0x3f)                        */
45253 #define TIMER_OUTCFG22_OUTCFG90_Pos       (16UL)                    /*!< OUTCFG90 (Bit 16)                                     */
45254 #define TIMER_OUTCFG22_OUTCFG90_Msk       (0x3f0000UL)              /*!< OUTCFG90 (Bitfield-Mask: 0x3f)                        */
45255 #define TIMER_OUTCFG22_OUTCFG89_Pos       (8UL)                     /*!< OUTCFG89 (Bit 8)                                      */
45256 #define TIMER_OUTCFG22_OUTCFG89_Msk       (0x3f00UL)                /*!< OUTCFG89 (Bitfield-Mask: 0x3f)                        */
45257 #define TIMER_OUTCFG22_OUTCFG88_Pos       (0UL)                     /*!< OUTCFG88 (Bit 0)                                      */
45258 #define TIMER_OUTCFG22_OUTCFG88_Msk       (0x3fUL)                  /*!< OUTCFG88 (Bitfield-Mask: 0x3f)                        */
45259 /* =======================================================  OUTCFG23  ======================================================== */
45260 #define TIMER_OUTCFG23_OUTCFG95_Pos       (24UL)                    /*!< OUTCFG95 (Bit 24)                                     */
45261 #define TIMER_OUTCFG23_OUTCFG95_Msk       (0x3f000000UL)            /*!< OUTCFG95 (Bitfield-Mask: 0x3f)                        */
45262 #define TIMER_OUTCFG23_OUTCFG94_Pos       (16UL)                    /*!< OUTCFG94 (Bit 16)                                     */
45263 #define TIMER_OUTCFG23_OUTCFG94_Msk       (0x3f0000UL)              /*!< OUTCFG94 (Bitfield-Mask: 0x3f)                        */
45264 #define TIMER_OUTCFG23_OUTCFG93_Pos       (8UL)                     /*!< OUTCFG93 (Bit 8)                                      */
45265 #define TIMER_OUTCFG23_OUTCFG93_Msk       (0x3f00UL)                /*!< OUTCFG93 (Bitfield-Mask: 0x3f)                        */
45266 #define TIMER_OUTCFG23_OUTCFG92_Pos       (0UL)                     /*!< OUTCFG92 (Bit 0)                                      */
45267 #define TIMER_OUTCFG23_OUTCFG92_Msk       (0x3fUL)                  /*!< OUTCFG92 (Bitfield-Mask: 0x3f)                        */
45268 /* =======================================================  OUTCFG24  ======================================================== */
45269 #define TIMER_OUTCFG24_OUTCFG99_Pos       (24UL)                    /*!< OUTCFG99 (Bit 24)                                     */
45270 #define TIMER_OUTCFG24_OUTCFG99_Msk       (0x3f000000UL)            /*!< OUTCFG99 (Bitfield-Mask: 0x3f)                        */
45271 #define TIMER_OUTCFG24_OUTCFG98_Pos       (16UL)                    /*!< OUTCFG98 (Bit 16)                                     */
45272 #define TIMER_OUTCFG24_OUTCFG98_Msk       (0x3f0000UL)              /*!< OUTCFG98 (Bitfield-Mask: 0x3f)                        */
45273 #define TIMER_OUTCFG24_OUTCFG97_Pos       (8UL)                     /*!< OUTCFG97 (Bit 8)                                      */
45274 #define TIMER_OUTCFG24_OUTCFG97_Msk       (0x3f00UL)                /*!< OUTCFG97 (Bitfield-Mask: 0x3f)                        */
45275 #define TIMER_OUTCFG24_OUTCFG96_Pos       (0UL)                     /*!< OUTCFG96 (Bit 0)                                      */
45276 #define TIMER_OUTCFG24_OUTCFG96_Msk       (0x3fUL)                  /*!< OUTCFG96 (Bitfield-Mask: 0x3f)                        */
45277 /* =======================================================  OUTCFG25  ======================================================== */
45278 #define TIMER_OUTCFG25_OUTCFG103_Pos      (24UL)                    /*!< OUTCFG103 (Bit 24)                                    */
45279 #define TIMER_OUTCFG25_OUTCFG103_Msk      (0x3f000000UL)            /*!< OUTCFG103 (Bitfield-Mask: 0x3f)                       */
45280 #define TIMER_OUTCFG25_OUTCFG102_Pos      (16UL)                    /*!< OUTCFG102 (Bit 16)                                    */
45281 #define TIMER_OUTCFG25_OUTCFG102_Msk      (0x3f0000UL)              /*!< OUTCFG102 (Bitfield-Mask: 0x3f)                       */
45282 #define TIMER_OUTCFG25_OUTCFG101_Pos      (8UL)                     /*!< OUTCFG101 (Bit 8)                                     */
45283 #define TIMER_OUTCFG25_OUTCFG101_Msk      (0x3f00UL)                /*!< OUTCFG101 (Bitfield-Mask: 0x3f)                       */
45284 #define TIMER_OUTCFG25_OUTCFG100_Pos      (0UL)                     /*!< OUTCFG100 (Bit 0)                                     */
45285 #define TIMER_OUTCFG25_OUTCFG100_Msk      (0x3fUL)                  /*!< OUTCFG100 (Bitfield-Mask: 0x3f)                       */
45286 /* =======================================================  OUTCFG26  ======================================================== */
45287 #define TIMER_OUTCFG26_OUTCFG107_Pos      (24UL)                    /*!< OUTCFG107 (Bit 24)                                    */
45288 #define TIMER_OUTCFG26_OUTCFG107_Msk      (0x3f000000UL)            /*!< OUTCFG107 (Bitfield-Mask: 0x3f)                       */
45289 #define TIMER_OUTCFG26_OUTCFG106_Pos      (16UL)                    /*!< OUTCFG106 (Bit 16)                                    */
45290 #define TIMER_OUTCFG26_OUTCFG106_Msk      (0x3f0000UL)              /*!< OUTCFG106 (Bitfield-Mask: 0x3f)                       */
45291 #define TIMER_OUTCFG26_OUTCFG105_Pos      (8UL)                     /*!< OUTCFG105 (Bit 8)                                     */
45292 #define TIMER_OUTCFG26_OUTCFG105_Msk      (0x3f00UL)                /*!< OUTCFG105 (Bitfield-Mask: 0x3f)                       */
45293 #define TIMER_OUTCFG26_OUTCFG104_Pos      (0UL)                     /*!< OUTCFG104 (Bit 0)                                     */
45294 #define TIMER_OUTCFG26_OUTCFG104_Msk      (0x3fUL)                  /*!< OUTCFG104 (Bitfield-Mask: 0x3f)                       */
45295 /* =======================================================  OUTCFG27  ======================================================== */
45296 #define TIMER_OUTCFG27_OUTCFG111_Pos      (24UL)                    /*!< OUTCFG111 (Bit 24)                                    */
45297 #define TIMER_OUTCFG27_OUTCFG111_Msk      (0x3f000000UL)            /*!< OUTCFG111 (Bitfield-Mask: 0x3f)                       */
45298 #define TIMER_OUTCFG27_OUTCFG110_Pos      (16UL)                    /*!< OUTCFG110 (Bit 16)                                    */
45299 #define TIMER_OUTCFG27_OUTCFG110_Msk      (0x3f0000UL)              /*!< OUTCFG110 (Bitfield-Mask: 0x3f)                       */
45300 #define TIMER_OUTCFG27_OUTCFG109_Pos      (8UL)                     /*!< OUTCFG109 (Bit 8)                                     */
45301 #define TIMER_OUTCFG27_OUTCFG109_Msk      (0x3f00UL)                /*!< OUTCFG109 (Bitfield-Mask: 0x3f)                       */
45302 #define TIMER_OUTCFG27_OUTCFG108_Pos      (0UL)                     /*!< OUTCFG108 (Bit 0)                                     */
45303 #define TIMER_OUTCFG27_OUTCFG108_Msk      (0x3fUL)                  /*!< OUTCFG108 (Bitfield-Mask: 0x3f)                       */
45304 /* =======================================================  OUTCFG28  ======================================================== */
45305 #define TIMER_OUTCFG28_OUTCFG115_Pos      (24UL)                    /*!< OUTCFG115 (Bit 24)                                    */
45306 #define TIMER_OUTCFG28_OUTCFG115_Msk      (0x3f000000UL)            /*!< OUTCFG115 (Bitfield-Mask: 0x3f)                       */
45307 #define TIMER_OUTCFG28_OUTCFG114_Pos      (16UL)                    /*!< OUTCFG114 (Bit 16)                                    */
45308 #define TIMER_OUTCFG28_OUTCFG114_Msk      (0x3f0000UL)              /*!< OUTCFG114 (Bitfield-Mask: 0x3f)                       */
45309 #define TIMER_OUTCFG28_OUTCFG113_Pos      (8UL)                     /*!< OUTCFG113 (Bit 8)                                     */
45310 #define TIMER_OUTCFG28_OUTCFG113_Msk      (0x3f00UL)                /*!< OUTCFG113 (Bitfield-Mask: 0x3f)                       */
45311 #define TIMER_OUTCFG28_OUTCFG112_Pos      (0UL)                     /*!< OUTCFG112 (Bit 0)                                     */
45312 #define TIMER_OUTCFG28_OUTCFG112_Msk      (0x3fUL)                  /*!< OUTCFG112 (Bitfield-Mask: 0x3f)                       */
45313 /* =======================================================  OUTCFG29  ======================================================== */
45314 #define TIMER_OUTCFG29_OUTCFG119_Pos      (24UL)                    /*!< OUTCFG119 (Bit 24)                                    */
45315 #define TIMER_OUTCFG29_OUTCFG119_Msk      (0x3f000000UL)            /*!< OUTCFG119 (Bitfield-Mask: 0x3f)                       */
45316 #define TIMER_OUTCFG29_OUTCFG118_Pos      (16UL)                    /*!< OUTCFG118 (Bit 16)                                    */
45317 #define TIMER_OUTCFG29_OUTCFG118_Msk      (0x3f0000UL)              /*!< OUTCFG118 (Bitfield-Mask: 0x3f)                       */
45318 #define TIMER_OUTCFG29_OUTCFG117_Pos      (8UL)                     /*!< OUTCFG117 (Bit 8)                                     */
45319 #define TIMER_OUTCFG29_OUTCFG117_Msk      (0x3f00UL)                /*!< OUTCFG117 (Bitfield-Mask: 0x3f)                       */
45320 #define TIMER_OUTCFG29_OUTCFG116_Pos      (0UL)                     /*!< OUTCFG116 (Bit 0)                                     */
45321 #define TIMER_OUTCFG29_OUTCFG116_Msk      (0x3fUL)                  /*!< OUTCFG116 (Bitfield-Mask: 0x3f)                       */
45322 /* =======================================================  OUTCFG30  ======================================================== */
45323 #define TIMER_OUTCFG30_OUTCFG123_Pos      (24UL)                    /*!< OUTCFG123 (Bit 24)                                    */
45324 #define TIMER_OUTCFG30_OUTCFG123_Msk      (0x3f000000UL)            /*!< OUTCFG123 (Bitfield-Mask: 0x3f)                       */
45325 #define TIMER_OUTCFG30_OUTCFG122_Pos      (16UL)                    /*!< OUTCFG122 (Bit 16)                                    */
45326 #define TIMER_OUTCFG30_OUTCFG122_Msk      (0x3f0000UL)              /*!< OUTCFG122 (Bitfield-Mask: 0x3f)                       */
45327 #define TIMER_OUTCFG30_OUTCFG121_Pos      (8UL)                     /*!< OUTCFG121 (Bit 8)                                     */
45328 #define TIMER_OUTCFG30_OUTCFG121_Msk      (0x3f00UL)                /*!< OUTCFG121 (Bitfield-Mask: 0x3f)                       */
45329 #define TIMER_OUTCFG30_OUTCFG120_Pos      (0UL)                     /*!< OUTCFG120 (Bit 0)                                     */
45330 #define TIMER_OUTCFG30_OUTCFG120_Msk      (0x3fUL)                  /*!< OUTCFG120 (Bitfield-Mask: 0x3f)                       */
45331 /* =======================================================  OUTCFG31  ======================================================== */
45332 #define TIMER_OUTCFG31_OUTCFG127_Pos      (24UL)                    /*!< OUTCFG127 (Bit 24)                                    */
45333 #define TIMER_OUTCFG31_OUTCFG127_Msk      (0x3f000000UL)            /*!< OUTCFG127 (Bitfield-Mask: 0x3f)                       */
45334 #define TIMER_OUTCFG31_OUTCFG126_Pos      (16UL)                    /*!< OUTCFG126 (Bit 16)                                    */
45335 #define TIMER_OUTCFG31_OUTCFG126_Msk      (0x3f0000UL)              /*!< OUTCFG126 (Bitfield-Mask: 0x3f)                       */
45336 #define TIMER_OUTCFG31_OUTCFG125_Pos      (8UL)                     /*!< OUTCFG125 (Bit 8)                                     */
45337 #define TIMER_OUTCFG31_OUTCFG125_Msk      (0x3f00UL)                /*!< OUTCFG125 (Bitfield-Mask: 0x3f)                       */
45338 #define TIMER_OUTCFG31_OUTCFG124_Pos      (0UL)                     /*!< OUTCFG124 (Bit 0)                                     */
45339 #define TIMER_OUTCFG31_OUTCFG124_Msk      (0x3fUL)                  /*!< OUTCFG124 (Bitfield-Mask: 0x3f)                       */
45340 /* =========================================================  CTRL0  ========================================================= */
45341 #define TIMER_CTRL0_TMR0LMT_Pos           (24UL)                    /*!< TMR0LMT (Bit 24)                                      */
45342 #define TIMER_CTRL0_TMR0LMT_Msk           (0xff000000UL)            /*!< TMR0LMT (Bitfield-Mask: 0xff)                         */
45343 #define TIMER_CTRL0_TMR0TMODE_Pos         (16UL)                    /*!< TMR0TMODE (Bit 16)                                    */
45344 #define TIMER_CTRL0_TMR0TMODE_Msk         (0x30000UL)               /*!< TMR0TMODE (Bitfield-Mask: 0x03)                       */
45345 #define TIMER_CTRL0_TMR0CLK_Pos           (8UL)                     /*!< TMR0CLK (Bit 8)                                       */
45346 #define TIMER_CTRL0_TMR0CLK_Msk           (0xff00UL)                /*!< TMR0CLK (Bitfield-Mask: 0xff)                         */
45347 #define TIMER_CTRL0_TMR0FN_Pos            (4UL)                     /*!< TMR0FN (Bit 4)                                        */
45348 #define TIMER_CTRL0_TMR0FN_Msk            (0xf0UL)                  /*!< TMR0FN (Bitfield-Mask: 0x0f)                          */
45349 #define TIMER_CTRL0_TMR0POL1_Pos          (3UL)                     /*!< TMR0POL1 (Bit 3)                                      */
45350 #define TIMER_CTRL0_TMR0POL1_Msk          (0x8UL)                   /*!< TMR0POL1 (Bitfield-Mask: 0x01)                        */
45351 #define TIMER_CTRL0_TMR0POL0_Pos          (2UL)                     /*!< TMR0POL0 (Bit 2)                                      */
45352 #define TIMER_CTRL0_TMR0POL0_Msk          (0x4UL)                   /*!< TMR0POL0 (Bitfield-Mask: 0x01)                        */
45353 #define TIMER_CTRL0_TMR0CLR_Pos           (1UL)                     /*!< TMR0CLR (Bit 1)                                       */
45354 #define TIMER_CTRL0_TMR0CLR_Msk           (0x2UL)                   /*!< TMR0CLR (Bitfield-Mask: 0x01)                         */
45355 #define TIMER_CTRL0_TMR0EN_Pos            (0UL)                     /*!< TMR0EN (Bit 0)                                        */
45356 #define TIMER_CTRL0_TMR0EN_Msk            (0x1UL)                   /*!< TMR0EN (Bitfield-Mask: 0x01)                          */
45357 /* ========================================================  TIMER0  ========================================================= */
45358 #define TIMER_TIMER0_TIMER0_Pos           (0UL)                     /*!< TIMER0 (Bit 0)                                        */
45359 #define TIMER_TIMER0_TIMER0_Msk           (0xffffffffUL)            /*!< TIMER0 (Bitfield-Mask: 0xffffffff)                    */
45360 /* =======================================================  TMR0CMP0  ======================================================== */
45361 #define TIMER_TMR0CMP0_TMR0CMP0_Pos       (0UL)                     /*!< TMR0CMP0 (Bit 0)                                      */
45362 #define TIMER_TMR0CMP0_TMR0CMP0_Msk       (0xffffffffUL)            /*!< TMR0CMP0 (Bitfield-Mask: 0xffffffff)                  */
45363 /* =======================================================  TMR0CMP1  ======================================================== */
45364 #define TIMER_TMR0CMP1_TMR0CMP1_Pos       (0UL)                     /*!< TMR0CMP1 (Bit 0)                                      */
45365 #define TIMER_TMR0CMP1_TMR0CMP1_Msk       (0xffffffffUL)            /*!< TMR0CMP1 (Bitfield-Mask: 0xffffffff)                  */
45366 /* =========================================================  MODE0  ========================================================= */
45367 #define TIMER_MODE0_TMR0TRIGSEL_Pos       (8UL)                     /*!< TMR0TRIGSEL (Bit 8)                                   */
45368 #define TIMER_MODE0_TMR0TRIGSEL_Msk       (0xff00UL)                /*!< TMR0TRIGSEL (Bitfield-Mask: 0xff)                     */
45369 /* ======================================================  TMR0LMTVAL  ======================================================= */
45370 #define TIMER_TMR0LMTVAL_TMR0LMTVAL_Pos   (0UL)                     /*!< TMR0LMTVAL (Bit 0)                                    */
45371 #define TIMER_TMR0LMTVAL_TMR0LMTVAL_Msk   (0xffUL)                  /*!< TMR0LMTVAL (Bitfield-Mask: 0xff)                      */
45372 /* =========================================================  CTRL1  ========================================================= */
45373 #define TIMER_CTRL1_TMR1LMT_Pos           (24UL)                    /*!< TMR1LMT (Bit 24)                                      */
45374 #define TIMER_CTRL1_TMR1LMT_Msk           (0xff000000UL)            /*!< TMR1LMT (Bitfield-Mask: 0xff)                         */
45375 #define TIMER_CTRL1_TMR1TMODE_Pos         (16UL)                    /*!< TMR1TMODE (Bit 16)                                    */
45376 #define TIMER_CTRL1_TMR1TMODE_Msk         (0x30000UL)               /*!< TMR1TMODE (Bitfield-Mask: 0x03)                       */
45377 #define TIMER_CTRL1_TMR1CLK_Pos           (8UL)                     /*!< TMR1CLK (Bit 8)                                       */
45378 #define TIMER_CTRL1_TMR1CLK_Msk           (0xff00UL)                /*!< TMR1CLK (Bitfield-Mask: 0xff)                         */
45379 #define TIMER_CTRL1_TMR1FN_Pos            (4UL)                     /*!< TMR1FN (Bit 4)                                        */
45380 #define TIMER_CTRL1_TMR1FN_Msk            (0xf0UL)                  /*!< TMR1FN (Bitfield-Mask: 0x0f)                          */
45381 #define TIMER_CTRL1_TMR1POL1_Pos          (3UL)                     /*!< TMR1POL1 (Bit 3)                                      */
45382 #define TIMER_CTRL1_TMR1POL1_Msk          (0x8UL)                   /*!< TMR1POL1 (Bitfield-Mask: 0x01)                        */
45383 #define TIMER_CTRL1_TMR1POL0_Pos          (2UL)                     /*!< TMR1POL0 (Bit 2)                                      */
45384 #define TIMER_CTRL1_TMR1POL0_Msk          (0x4UL)                   /*!< TMR1POL0 (Bitfield-Mask: 0x01)                        */
45385 #define TIMER_CTRL1_TMR1CLR_Pos           (1UL)                     /*!< TMR1CLR (Bit 1)                                       */
45386 #define TIMER_CTRL1_TMR1CLR_Msk           (0x2UL)                   /*!< TMR1CLR (Bitfield-Mask: 0x01)                         */
45387 #define TIMER_CTRL1_TMR1EN_Pos            (0UL)                     /*!< TMR1EN (Bit 0)                                        */
45388 #define TIMER_CTRL1_TMR1EN_Msk            (0x1UL)                   /*!< TMR1EN (Bitfield-Mask: 0x01)                          */
45389 /* ========================================================  TIMER1  ========================================================= */
45390 #define TIMER_TIMER1_TIMER1_Pos           (0UL)                     /*!< TIMER1 (Bit 0)                                        */
45391 #define TIMER_TIMER1_TIMER1_Msk           (0xffffffffUL)            /*!< TIMER1 (Bitfield-Mask: 0xffffffff)                    */
45392 /* =======================================================  TMR1CMP0  ======================================================== */
45393 #define TIMER_TMR1CMP0_TMR1CMP0_Pos       (0UL)                     /*!< TMR1CMP0 (Bit 0)                                      */
45394 #define TIMER_TMR1CMP0_TMR1CMP0_Msk       (0xffffffffUL)            /*!< TMR1CMP0 (Bitfield-Mask: 0xffffffff)                  */
45395 /* =======================================================  TMR1CMP1  ======================================================== */
45396 #define TIMER_TMR1CMP1_TMR1CMP1_Pos       (0UL)                     /*!< TMR1CMP1 (Bit 0)                                      */
45397 #define TIMER_TMR1CMP1_TMR1CMP1_Msk       (0xffffffffUL)            /*!< TMR1CMP1 (Bitfield-Mask: 0xffffffff)                  */
45398 /* =========================================================  MODE1  ========================================================= */
45399 #define TIMER_MODE1_TMR1TRIGSEL_Pos       (8UL)                     /*!< TMR1TRIGSEL (Bit 8)                                   */
45400 #define TIMER_MODE1_TMR1TRIGSEL_Msk       (0xff00UL)                /*!< TMR1TRIGSEL (Bitfield-Mask: 0xff)                     */
45401 /* ======================================================  TMR1LMTVAL  ======================================================= */
45402 #define TIMER_TMR1LMTVAL_TMR1LMTVAL_Pos   (0UL)                     /*!< TMR1LMTVAL (Bit 0)                                    */
45403 #define TIMER_TMR1LMTVAL_TMR1LMTVAL_Msk   (0xffUL)                  /*!< TMR1LMTVAL (Bitfield-Mask: 0xff)                      */
45404 /* =========================================================  CTRL2  ========================================================= */
45405 #define TIMER_CTRL2_TMR2LMT_Pos           (24UL)                    /*!< TMR2LMT (Bit 24)                                      */
45406 #define TIMER_CTRL2_TMR2LMT_Msk           (0xff000000UL)            /*!< TMR2LMT (Bitfield-Mask: 0xff)                         */
45407 #define TIMER_CTRL2_TMR2TMODE_Pos         (16UL)                    /*!< TMR2TMODE (Bit 16)                                    */
45408 #define TIMER_CTRL2_TMR2TMODE_Msk         (0x30000UL)               /*!< TMR2TMODE (Bitfield-Mask: 0x03)                       */
45409 #define TIMER_CTRL2_TMR2CLK_Pos           (8UL)                     /*!< TMR2CLK (Bit 8)                                       */
45410 #define TIMER_CTRL2_TMR2CLK_Msk           (0xff00UL)                /*!< TMR2CLK (Bitfield-Mask: 0xff)                         */
45411 #define TIMER_CTRL2_TMR2FN_Pos            (4UL)                     /*!< TMR2FN (Bit 4)                                        */
45412 #define TIMER_CTRL2_TMR2FN_Msk            (0xf0UL)                  /*!< TMR2FN (Bitfield-Mask: 0x0f)                          */
45413 #define TIMER_CTRL2_TMR2POL1_Pos          (3UL)                     /*!< TMR2POL1 (Bit 3)                                      */
45414 #define TIMER_CTRL2_TMR2POL1_Msk          (0x8UL)                   /*!< TMR2POL1 (Bitfield-Mask: 0x01)                        */
45415 #define TIMER_CTRL2_TMR2POL0_Pos          (2UL)                     /*!< TMR2POL0 (Bit 2)                                      */
45416 #define TIMER_CTRL2_TMR2POL0_Msk          (0x4UL)                   /*!< TMR2POL0 (Bitfield-Mask: 0x01)                        */
45417 #define TIMER_CTRL2_TMR2CLR_Pos           (1UL)                     /*!< TMR2CLR (Bit 1)                                       */
45418 #define TIMER_CTRL2_TMR2CLR_Msk           (0x2UL)                   /*!< TMR2CLR (Bitfield-Mask: 0x01)                         */
45419 #define TIMER_CTRL2_TMR2EN_Pos            (0UL)                     /*!< TMR2EN (Bit 0)                                        */
45420 #define TIMER_CTRL2_TMR2EN_Msk            (0x1UL)                   /*!< TMR2EN (Bitfield-Mask: 0x01)                          */
45421 /* ========================================================  TIMER2  ========================================================= */
45422 #define TIMER_TIMER2_TIMER2_Pos           (0UL)                     /*!< TIMER2 (Bit 0)                                        */
45423 #define TIMER_TIMER2_TIMER2_Msk           (0xffffffffUL)            /*!< TIMER2 (Bitfield-Mask: 0xffffffff)                    */
45424 /* =======================================================  TMR2CMP0  ======================================================== */
45425 #define TIMER_TMR2CMP0_TMR2CMP0_Pos       (0UL)                     /*!< TMR2CMP0 (Bit 0)                                      */
45426 #define TIMER_TMR2CMP0_TMR2CMP0_Msk       (0xffffffffUL)            /*!< TMR2CMP0 (Bitfield-Mask: 0xffffffff)                  */
45427 /* =======================================================  TMR2CMP1  ======================================================== */
45428 #define TIMER_TMR2CMP1_TMR2CMP1_Pos       (0UL)                     /*!< TMR2CMP1 (Bit 0)                                      */
45429 #define TIMER_TMR2CMP1_TMR2CMP1_Msk       (0xffffffffUL)            /*!< TMR2CMP1 (Bitfield-Mask: 0xffffffff)                  */
45430 /* =========================================================  MODE2  ========================================================= */
45431 #define TIMER_MODE2_TMR2TRIGSEL_Pos       (8UL)                     /*!< TMR2TRIGSEL (Bit 8)                                   */
45432 #define TIMER_MODE2_TMR2TRIGSEL_Msk       (0xff00UL)                /*!< TMR2TRIGSEL (Bitfield-Mask: 0xff)                     */
45433 /* ======================================================  TMR2LMTVAL  ======================================================= */
45434 #define TIMER_TMR2LMTVAL_TMR2LMTVAL_Pos   (0UL)                     /*!< TMR2LMTVAL (Bit 0)                                    */
45435 #define TIMER_TMR2LMTVAL_TMR2LMTVAL_Msk   (0xffUL)                  /*!< TMR2LMTVAL (Bitfield-Mask: 0xff)                      */
45436 /* =========================================================  CTRL3  ========================================================= */
45437 #define TIMER_CTRL3_TMR3LMT_Pos           (24UL)                    /*!< TMR3LMT (Bit 24)                                      */
45438 #define TIMER_CTRL3_TMR3LMT_Msk           (0xff000000UL)            /*!< TMR3LMT (Bitfield-Mask: 0xff)                         */
45439 #define TIMER_CTRL3_TMR3TMODE_Pos         (16UL)                    /*!< TMR3TMODE (Bit 16)                                    */
45440 #define TIMER_CTRL3_TMR3TMODE_Msk         (0x30000UL)               /*!< TMR3TMODE (Bitfield-Mask: 0x03)                       */
45441 #define TIMER_CTRL3_TMR3CLK_Pos           (8UL)                     /*!< TMR3CLK (Bit 8)                                       */
45442 #define TIMER_CTRL3_TMR3CLK_Msk           (0xff00UL)                /*!< TMR3CLK (Bitfield-Mask: 0xff)                         */
45443 #define TIMER_CTRL3_TMR3FN_Pos            (4UL)                     /*!< TMR3FN (Bit 4)                                        */
45444 #define TIMER_CTRL3_TMR3FN_Msk            (0xf0UL)                  /*!< TMR3FN (Bitfield-Mask: 0x0f)                          */
45445 #define TIMER_CTRL3_TMR3POL1_Pos          (3UL)                     /*!< TMR3POL1 (Bit 3)                                      */
45446 #define TIMER_CTRL3_TMR3POL1_Msk          (0x8UL)                   /*!< TMR3POL1 (Bitfield-Mask: 0x01)                        */
45447 #define TIMER_CTRL3_TMR3POL0_Pos          (2UL)                     /*!< TMR3POL0 (Bit 2)                                      */
45448 #define TIMER_CTRL3_TMR3POL0_Msk          (0x4UL)                   /*!< TMR3POL0 (Bitfield-Mask: 0x01)                        */
45449 #define TIMER_CTRL3_TMR3CLR_Pos           (1UL)                     /*!< TMR3CLR (Bit 1)                                       */
45450 #define TIMER_CTRL3_TMR3CLR_Msk           (0x2UL)                   /*!< TMR3CLR (Bitfield-Mask: 0x01)                         */
45451 #define TIMER_CTRL3_TMR3EN_Pos            (0UL)                     /*!< TMR3EN (Bit 0)                                        */
45452 #define TIMER_CTRL3_TMR3EN_Msk            (0x1UL)                   /*!< TMR3EN (Bitfield-Mask: 0x01)                          */
45453 /* ========================================================  TIMER3  ========================================================= */
45454 #define TIMER_TIMER3_TIMER3_Pos           (0UL)                     /*!< TIMER3 (Bit 0)                                        */
45455 #define TIMER_TIMER3_TIMER3_Msk           (0xffffffffUL)            /*!< TIMER3 (Bitfield-Mask: 0xffffffff)                    */
45456 /* =======================================================  TMR3CMP0  ======================================================== */
45457 #define TIMER_TMR3CMP0_TMR3CMP0_Pos       (0UL)                     /*!< TMR3CMP0 (Bit 0)                                      */
45458 #define TIMER_TMR3CMP0_TMR3CMP0_Msk       (0xffffffffUL)            /*!< TMR3CMP0 (Bitfield-Mask: 0xffffffff)                  */
45459 /* =======================================================  TMR3CMP1  ======================================================== */
45460 #define TIMER_TMR3CMP1_TMR3CMP1_Pos       (0UL)                     /*!< TMR3CMP1 (Bit 0)                                      */
45461 #define TIMER_TMR3CMP1_TMR3CMP1_Msk       (0xffffffffUL)            /*!< TMR3CMP1 (Bitfield-Mask: 0xffffffff)                  */
45462 /* =========================================================  MODE3  ========================================================= */
45463 #define TIMER_MODE3_TMR3TRIGSEL_Pos       (8UL)                     /*!< TMR3TRIGSEL (Bit 8)                                   */
45464 #define TIMER_MODE3_TMR3TRIGSEL_Msk       (0xff00UL)                /*!< TMR3TRIGSEL (Bitfield-Mask: 0xff)                     */
45465 /* ======================================================  TMR3LMTVAL  ======================================================= */
45466 #define TIMER_TMR3LMTVAL_TMR3LMTVAL_Pos   (0UL)                     /*!< TMR3LMTVAL (Bit 0)                                    */
45467 #define TIMER_TMR3LMTVAL_TMR3LMTVAL_Msk   (0xffUL)                  /*!< TMR3LMTVAL (Bitfield-Mask: 0xff)                      */
45468 /* =========================================================  CTRL4  ========================================================= */
45469 #define TIMER_CTRL4_TMR4LMT_Pos           (24UL)                    /*!< TMR4LMT (Bit 24)                                      */
45470 #define TIMER_CTRL4_TMR4LMT_Msk           (0xff000000UL)            /*!< TMR4LMT (Bitfield-Mask: 0xff)                         */
45471 #define TIMER_CTRL4_TMR4TMODE_Pos         (16UL)                    /*!< TMR4TMODE (Bit 16)                                    */
45472 #define TIMER_CTRL4_TMR4TMODE_Msk         (0x30000UL)               /*!< TMR4TMODE (Bitfield-Mask: 0x03)                       */
45473 #define TIMER_CTRL4_TMR4CLK_Pos           (8UL)                     /*!< TMR4CLK (Bit 8)                                       */
45474 #define TIMER_CTRL4_TMR4CLK_Msk           (0xff00UL)                /*!< TMR4CLK (Bitfield-Mask: 0xff)                         */
45475 #define TIMER_CTRL4_TMR4FN_Pos            (4UL)                     /*!< TMR4FN (Bit 4)                                        */
45476 #define TIMER_CTRL4_TMR4FN_Msk            (0xf0UL)                  /*!< TMR4FN (Bitfield-Mask: 0x0f)                          */
45477 #define TIMER_CTRL4_TMR4POL1_Pos          (3UL)                     /*!< TMR4POL1 (Bit 3)                                      */
45478 #define TIMER_CTRL4_TMR4POL1_Msk          (0x8UL)                   /*!< TMR4POL1 (Bitfield-Mask: 0x01)                        */
45479 #define TIMER_CTRL4_TMR4POL0_Pos          (2UL)                     /*!< TMR4POL0 (Bit 2)                                      */
45480 #define TIMER_CTRL4_TMR4POL0_Msk          (0x4UL)                   /*!< TMR4POL0 (Bitfield-Mask: 0x01)                        */
45481 #define TIMER_CTRL4_TMR4CLR_Pos           (1UL)                     /*!< TMR4CLR (Bit 1)                                       */
45482 #define TIMER_CTRL4_TMR4CLR_Msk           (0x2UL)                   /*!< TMR4CLR (Bitfield-Mask: 0x01)                         */
45483 #define TIMER_CTRL4_TMR4EN_Pos            (0UL)                     /*!< TMR4EN (Bit 0)                                        */
45484 #define TIMER_CTRL4_TMR4EN_Msk            (0x1UL)                   /*!< TMR4EN (Bitfield-Mask: 0x01)                          */
45485 /* ========================================================  TIMER4  ========================================================= */
45486 #define TIMER_TIMER4_TIMER4_Pos           (0UL)                     /*!< TIMER4 (Bit 0)                                        */
45487 #define TIMER_TIMER4_TIMER4_Msk           (0xffffffffUL)            /*!< TIMER4 (Bitfield-Mask: 0xffffffff)                    */
45488 /* =======================================================  TMR4CMP0  ======================================================== */
45489 #define TIMER_TMR4CMP0_TMR4CMP0_Pos       (0UL)                     /*!< TMR4CMP0 (Bit 0)                                      */
45490 #define TIMER_TMR4CMP0_TMR4CMP0_Msk       (0xffffffffUL)            /*!< TMR4CMP0 (Bitfield-Mask: 0xffffffff)                  */
45491 /* =======================================================  TMR4CMP1  ======================================================== */
45492 #define TIMER_TMR4CMP1_TMR4CMP1_Pos       (0UL)                     /*!< TMR4CMP1 (Bit 0)                                      */
45493 #define TIMER_TMR4CMP1_TMR4CMP1_Msk       (0xffffffffUL)            /*!< TMR4CMP1 (Bitfield-Mask: 0xffffffff)                  */
45494 /* =========================================================  MODE4  ========================================================= */
45495 #define TIMER_MODE4_TMR4TRIGSEL_Pos       (8UL)                     /*!< TMR4TRIGSEL (Bit 8)                                   */
45496 #define TIMER_MODE4_TMR4TRIGSEL_Msk       (0xff00UL)                /*!< TMR4TRIGSEL (Bitfield-Mask: 0xff)                     */
45497 /* ======================================================  TMR4LMTVAL  ======================================================= */
45498 #define TIMER_TMR4LMTVAL_TMR4LMTVAL_Pos   (0UL)                     /*!< TMR4LMTVAL (Bit 0)                                    */
45499 #define TIMER_TMR4LMTVAL_TMR4LMTVAL_Msk   (0xffUL)                  /*!< TMR4LMTVAL (Bitfield-Mask: 0xff)                      */
45500 /* =========================================================  CTRL5  ========================================================= */
45501 #define TIMER_CTRL5_TMR5LMT_Pos           (24UL)                    /*!< TMR5LMT (Bit 24)                                      */
45502 #define TIMER_CTRL5_TMR5LMT_Msk           (0xff000000UL)            /*!< TMR5LMT (Bitfield-Mask: 0xff)                         */
45503 #define TIMER_CTRL5_TMR5TMODE_Pos         (16UL)                    /*!< TMR5TMODE (Bit 16)                                    */
45504 #define TIMER_CTRL5_TMR5TMODE_Msk         (0x30000UL)               /*!< TMR5TMODE (Bitfield-Mask: 0x03)                       */
45505 #define TIMER_CTRL5_TMR5CLK_Pos           (8UL)                     /*!< TMR5CLK (Bit 8)                                       */
45506 #define TIMER_CTRL5_TMR5CLK_Msk           (0xff00UL)                /*!< TMR5CLK (Bitfield-Mask: 0xff)                         */
45507 #define TIMER_CTRL5_TMR5FN_Pos            (4UL)                     /*!< TMR5FN (Bit 4)                                        */
45508 #define TIMER_CTRL5_TMR5FN_Msk            (0xf0UL)                  /*!< TMR5FN (Bitfield-Mask: 0x0f)                          */
45509 #define TIMER_CTRL5_TMR5POL1_Pos          (3UL)                     /*!< TMR5POL1 (Bit 3)                                      */
45510 #define TIMER_CTRL5_TMR5POL1_Msk          (0x8UL)                   /*!< TMR5POL1 (Bitfield-Mask: 0x01)                        */
45511 #define TIMER_CTRL5_TMR5POL0_Pos          (2UL)                     /*!< TMR5POL0 (Bit 2)                                      */
45512 #define TIMER_CTRL5_TMR5POL0_Msk          (0x4UL)                   /*!< TMR5POL0 (Bitfield-Mask: 0x01)                        */
45513 #define TIMER_CTRL5_TMR5CLR_Pos           (1UL)                     /*!< TMR5CLR (Bit 1)                                       */
45514 #define TIMER_CTRL5_TMR5CLR_Msk           (0x2UL)                   /*!< TMR5CLR (Bitfield-Mask: 0x01)                         */
45515 #define TIMER_CTRL5_TMR5EN_Pos            (0UL)                     /*!< TMR5EN (Bit 0)                                        */
45516 #define TIMER_CTRL5_TMR5EN_Msk            (0x1UL)                   /*!< TMR5EN (Bitfield-Mask: 0x01)                          */
45517 /* ========================================================  TIMER5  ========================================================= */
45518 #define TIMER_TIMER5_TIMER5_Pos           (0UL)                     /*!< TIMER5 (Bit 0)                                        */
45519 #define TIMER_TIMER5_TIMER5_Msk           (0xffffffffUL)            /*!< TIMER5 (Bitfield-Mask: 0xffffffff)                    */
45520 /* =======================================================  TMR5CMP0  ======================================================== */
45521 #define TIMER_TMR5CMP0_TMR5CMP0_Pos       (0UL)                     /*!< TMR5CMP0 (Bit 0)                                      */
45522 #define TIMER_TMR5CMP0_TMR5CMP0_Msk       (0xffffffffUL)            /*!< TMR5CMP0 (Bitfield-Mask: 0xffffffff)                  */
45523 /* =======================================================  TMR5CMP1  ======================================================== */
45524 #define TIMER_TMR5CMP1_TMR5CMP1_Pos       (0UL)                     /*!< TMR5CMP1 (Bit 0)                                      */
45525 #define TIMER_TMR5CMP1_TMR5CMP1_Msk       (0xffffffffUL)            /*!< TMR5CMP1 (Bitfield-Mask: 0xffffffff)                  */
45526 /* =========================================================  MODE5  ========================================================= */
45527 #define TIMER_MODE5_TMR5TRIGSEL_Pos       (8UL)                     /*!< TMR5TRIGSEL (Bit 8)                                   */
45528 #define TIMER_MODE5_TMR5TRIGSEL_Msk       (0xff00UL)                /*!< TMR5TRIGSEL (Bitfield-Mask: 0xff)                     */
45529 /* ======================================================  TMR5LMTVAL  ======================================================= */
45530 #define TIMER_TMR5LMTVAL_TMR5LMTVAL_Pos   (0UL)                     /*!< TMR5LMTVAL (Bit 0)                                    */
45531 #define TIMER_TMR5LMTVAL_TMR5LMTVAL_Msk   (0xffUL)                  /*!< TMR5LMTVAL (Bitfield-Mask: 0xff)                      */
45532 /* =========================================================  CTRL6  ========================================================= */
45533 #define TIMER_CTRL6_TMR6LMT_Pos           (24UL)                    /*!< TMR6LMT (Bit 24)                                      */
45534 #define TIMER_CTRL6_TMR6LMT_Msk           (0xff000000UL)            /*!< TMR6LMT (Bitfield-Mask: 0xff)                         */
45535 #define TIMER_CTRL6_TMR6TMODE_Pos         (16UL)                    /*!< TMR6TMODE (Bit 16)                                    */
45536 #define TIMER_CTRL6_TMR6TMODE_Msk         (0x30000UL)               /*!< TMR6TMODE (Bitfield-Mask: 0x03)                       */
45537 #define TIMER_CTRL6_TMR6CLK_Pos           (8UL)                     /*!< TMR6CLK (Bit 8)                                       */
45538 #define TIMER_CTRL6_TMR6CLK_Msk           (0xff00UL)                /*!< TMR6CLK (Bitfield-Mask: 0xff)                         */
45539 #define TIMER_CTRL6_TMR6FN_Pos            (4UL)                     /*!< TMR6FN (Bit 4)                                        */
45540 #define TIMER_CTRL6_TMR6FN_Msk            (0xf0UL)                  /*!< TMR6FN (Bitfield-Mask: 0x0f)                          */
45541 #define TIMER_CTRL6_TMR6POL1_Pos          (3UL)                     /*!< TMR6POL1 (Bit 3)                                      */
45542 #define TIMER_CTRL6_TMR6POL1_Msk          (0x8UL)                   /*!< TMR6POL1 (Bitfield-Mask: 0x01)                        */
45543 #define TIMER_CTRL6_TMR6POL0_Pos          (2UL)                     /*!< TMR6POL0 (Bit 2)                                      */
45544 #define TIMER_CTRL6_TMR6POL0_Msk          (0x4UL)                   /*!< TMR6POL0 (Bitfield-Mask: 0x01)                        */
45545 #define TIMER_CTRL6_TMR6CLR_Pos           (1UL)                     /*!< TMR6CLR (Bit 1)                                       */
45546 #define TIMER_CTRL6_TMR6CLR_Msk           (0x2UL)                   /*!< TMR6CLR (Bitfield-Mask: 0x01)                         */
45547 #define TIMER_CTRL6_TMR6EN_Pos            (0UL)                     /*!< TMR6EN (Bit 0)                                        */
45548 #define TIMER_CTRL6_TMR6EN_Msk            (0x1UL)                   /*!< TMR6EN (Bitfield-Mask: 0x01)                          */
45549 /* ========================================================  TIMER6  ========================================================= */
45550 #define TIMER_TIMER6_TIMER6_Pos           (0UL)                     /*!< TIMER6 (Bit 0)                                        */
45551 #define TIMER_TIMER6_TIMER6_Msk           (0xffffffffUL)            /*!< TIMER6 (Bitfield-Mask: 0xffffffff)                    */
45552 /* =======================================================  TMR6CMP0  ======================================================== */
45553 #define TIMER_TMR6CMP0_TMR6CMP0_Pos       (0UL)                     /*!< TMR6CMP0 (Bit 0)                                      */
45554 #define TIMER_TMR6CMP0_TMR6CMP0_Msk       (0xffffffffUL)            /*!< TMR6CMP0 (Bitfield-Mask: 0xffffffff)                  */
45555 /* =======================================================  TMR6CMP1  ======================================================== */
45556 #define TIMER_TMR6CMP1_TMR6CMP1_Pos       (0UL)                     /*!< TMR6CMP1 (Bit 0)                                      */
45557 #define TIMER_TMR6CMP1_TMR6CMP1_Msk       (0xffffffffUL)            /*!< TMR6CMP1 (Bitfield-Mask: 0xffffffff)                  */
45558 /* =========================================================  MODE6  ========================================================= */
45559 #define TIMER_MODE6_TMR6TRIGSEL_Pos       (8UL)                     /*!< TMR6TRIGSEL (Bit 8)                                   */
45560 #define TIMER_MODE6_TMR6TRIGSEL_Msk       (0xff00UL)                /*!< TMR6TRIGSEL (Bitfield-Mask: 0xff)                     */
45561 /* ======================================================  TMR6LMTVAL  ======================================================= */
45562 #define TIMER_TMR6LMTVAL_TMR6LMTVAL_Pos   (0UL)                     /*!< TMR6LMTVAL (Bit 0)                                    */
45563 #define TIMER_TMR6LMTVAL_TMR6LMTVAL_Msk   (0xffUL)                  /*!< TMR6LMTVAL (Bitfield-Mask: 0xff)                      */
45564 /* =========================================================  CTRL7  ========================================================= */
45565 #define TIMER_CTRL7_TMR7LMT_Pos           (24UL)                    /*!< TMR7LMT (Bit 24)                                      */
45566 #define TIMER_CTRL7_TMR7LMT_Msk           (0xff000000UL)            /*!< TMR7LMT (Bitfield-Mask: 0xff)                         */
45567 #define TIMER_CTRL7_TMR7TMODE_Pos         (16UL)                    /*!< TMR7TMODE (Bit 16)                                    */
45568 #define TIMER_CTRL7_TMR7TMODE_Msk         (0x30000UL)               /*!< TMR7TMODE (Bitfield-Mask: 0x03)                       */
45569 #define TIMER_CTRL7_TMR7CLK_Pos           (8UL)                     /*!< TMR7CLK (Bit 8)                                       */
45570 #define TIMER_CTRL7_TMR7CLK_Msk           (0xff00UL)                /*!< TMR7CLK (Bitfield-Mask: 0xff)                         */
45571 #define TIMER_CTRL7_TMR7FN_Pos            (4UL)                     /*!< TMR7FN (Bit 4)                                        */
45572 #define TIMER_CTRL7_TMR7FN_Msk            (0xf0UL)                  /*!< TMR7FN (Bitfield-Mask: 0x0f)                          */
45573 #define TIMER_CTRL7_TMR7POL1_Pos          (3UL)                     /*!< TMR7POL1 (Bit 3)                                      */
45574 #define TIMER_CTRL7_TMR7POL1_Msk          (0x8UL)                   /*!< TMR7POL1 (Bitfield-Mask: 0x01)                        */
45575 #define TIMER_CTRL7_TMR7POL0_Pos          (2UL)                     /*!< TMR7POL0 (Bit 2)                                      */
45576 #define TIMER_CTRL7_TMR7POL0_Msk          (0x4UL)                   /*!< TMR7POL0 (Bitfield-Mask: 0x01)                        */
45577 #define TIMER_CTRL7_TMR7CLR_Pos           (1UL)                     /*!< TMR7CLR (Bit 1)                                       */
45578 #define TIMER_CTRL7_TMR7CLR_Msk           (0x2UL)                   /*!< TMR7CLR (Bitfield-Mask: 0x01)                         */
45579 #define TIMER_CTRL7_TMR7EN_Pos            (0UL)                     /*!< TMR7EN (Bit 0)                                        */
45580 #define TIMER_CTRL7_TMR7EN_Msk            (0x1UL)                   /*!< TMR7EN (Bitfield-Mask: 0x01)                          */
45581 /* ========================================================  TIMER7  ========================================================= */
45582 #define TIMER_TIMER7_TIMER7_Pos           (0UL)                     /*!< TIMER7 (Bit 0)                                        */
45583 #define TIMER_TIMER7_TIMER7_Msk           (0xffffffffUL)            /*!< TIMER7 (Bitfield-Mask: 0xffffffff)                    */
45584 /* =======================================================  TMR7CMP0  ======================================================== */
45585 #define TIMER_TMR7CMP0_TMR7CMP0_Pos       (0UL)                     /*!< TMR7CMP0 (Bit 0)                                      */
45586 #define TIMER_TMR7CMP0_TMR7CMP0_Msk       (0xffffffffUL)            /*!< TMR7CMP0 (Bitfield-Mask: 0xffffffff)                  */
45587 /* =======================================================  TMR7CMP1  ======================================================== */
45588 #define TIMER_TMR7CMP1_TMR7CMP1_Pos       (0UL)                     /*!< TMR7CMP1 (Bit 0)                                      */
45589 #define TIMER_TMR7CMP1_TMR7CMP1_Msk       (0xffffffffUL)            /*!< TMR7CMP1 (Bitfield-Mask: 0xffffffff)                  */
45590 /* =========================================================  MODE7  ========================================================= */
45591 #define TIMER_MODE7_TMR7TRIGSEL_Pos       (8UL)                     /*!< TMR7TRIGSEL (Bit 8)                                   */
45592 #define TIMER_MODE7_TMR7TRIGSEL_Msk       (0xff00UL)                /*!< TMR7TRIGSEL (Bitfield-Mask: 0xff)                     */
45593 /* ======================================================  TMR7LMTVAL  ======================================================= */
45594 #define TIMER_TMR7LMTVAL_TMR7LMTVAL_Pos   (0UL)                     /*!< TMR7LMTVAL (Bit 0)                                    */
45595 #define TIMER_TMR7LMTVAL_TMR7LMTVAL_Msk   (0xffUL)                  /*!< TMR7LMTVAL (Bitfield-Mask: 0xff)                      */
45596 /* =========================================================  CTRL8  ========================================================= */
45597 #define TIMER_CTRL8_TMR8LMT_Pos           (24UL)                    /*!< TMR8LMT (Bit 24)                                      */
45598 #define TIMER_CTRL8_TMR8LMT_Msk           (0xff000000UL)            /*!< TMR8LMT (Bitfield-Mask: 0xff)                         */
45599 #define TIMER_CTRL8_TMR8TMODE_Pos         (16UL)                    /*!< TMR8TMODE (Bit 16)                                    */
45600 #define TIMER_CTRL8_TMR8TMODE_Msk         (0x30000UL)               /*!< TMR8TMODE (Bitfield-Mask: 0x03)                       */
45601 #define TIMER_CTRL8_TMR8CLK_Pos           (8UL)                     /*!< TMR8CLK (Bit 8)                                       */
45602 #define TIMER_CTRL8_TMR8CLK_Msk           (0xff00UL)                /*!< TMR8CLK (Bitfield-Mask: 0xff)                         */
45603 #define TIMER_CTRL8_TMR8FN_Pos            (4UL)                     /*!< TMR8FN (Bit 4)                                        */
45604 #define TIMER_CTRL8_TMR8FN_Msk            (0xf0UL)                  /*!< TMR8FN (Bitfield-Mask: 0x0f)                          */
45605 #define TIMER_CTRL8_TMR8POL1_Pos          (3UL)                     /*!< TMR8POL1 (Bit 3)                                      */
45606 #define TIMER_CTRL8_TMR8POL1_Msk          (0x8UL)                   /*!< TMR8POL1 (Bitfield-Mask: 0x01)                        */
45607 #define TIMER_CTRL8_TMR8POL0_Pos          (2UL)                     /*!< TMR8POL0 (Bit 2)                                      */
45608 #define TIMER_CTRL8_TMR8POL0_Msk          (0x4UL)                   /*!< TMR8POL0 (Bitfield-Mask: 0x01)                        */
45609 #define TIMER_CTRL8_TMR8CLR_Pos           (1UL)                     /*!< TMR8CLR (Bit 1)                                       */
45610 #define TIMER_CTRL8_TMR8CLR_Msk           (0x2UL)                   /*!< TMR8CLR (Bitfield-Mask: 0x01)                         */
45611 #define TIMER_CTRL8_TMR8EN_Pos            (0UL)                     /*!< TMR8EN (Bit 0)                                        */
45612 #define TIMER_CTRL8_TMR8EN_Msk            (0x1UL)                   /*!< TMR8EN (Bitfield-Mask: 0x01)                          */
45613 /* ========================================================  TIMER8  ========================================================= */
45614 #define TIMER_TIMER8_TIMER8_Pos           (0UL)                     /*!< TIMER8 (Bit 0)                                        */
45615 #define TIMER_TIMER8_TIMER8_Msk           (0xffffffffUL)            /*!< TIMER8 (Bitfield-Mask: 0xffffffff)                    */
45616 /* =======================================================  TMR8CMP0  ======================================================== */
45617 #define TIMER_TMR8CMP0_TMR8CMP0_Pos       (0UL)                     /*!< TMR8CMP0 (Bit 0)                                      */
45618 #define TIMER_TMR8CMP0_TMR8CMP0_Msk       (0xffffffffUL)            /*!< TMR8CMP0 (Bitfield-Mask: 0xffffffff)                  */
45619 /* =======================================================  TMR8CMP1  ======================================================== */
45620 #define TIMER_TMR8CMP1_TMR8CMP1_Pos       (0UL)                     /*!< TMR8CMP1 (Bit 0)                                      */
45621 #define TIMER_TMR8CMP1_TMR8CMP1_Msk       (0xffffffffUL)            /*!< TMR8CMP1 (Bitfield-Mask: 0xffffffff)                  */
45622 /* =========================================================  MODE8  ========================================================= */
45623 #define TIMER_MODE8_TMR8TRIGSEL_Pos       (8UL)                     /*!< TMR8TRIGSEL (Bit 8)                                   */
45624 #define TIMER_MODE8_TMR8TRIGSEL_Msk       (0xff00UL)                /*!< TMR8TRIGSEL (Bitfield-Mask: 0xff)                     */
45625 /* ======================================================  TMR8LMTVAL  ======================================================= */
45626 #define TIMER_TMR8LMTVAL_TMR8LMTVAL_Pos   (0UL)                     /*!< TMR8LMTVAL (Bit 0)                                    */
45627 #define TIMER_TMR8LMTVAL_TMR8LMTVAL_Msk   (0xffUL)                  /*!< TMR8LMTVAL (Bitfield-Mask: 0xff)                      */
45628 /* =========================================================  CTRL9  ========================================================= */
45629 #define TIMER_CTRL9_TMR9LMT_Pos           (24UL)                    /*!< TMR9LMT (Bit 24)                                      */
45630 #define TIMER_CTRL9_TMR9LMT_Msk           (0xff000000UL)            /*!< TMR9LMT (Bitfield-Mask: 0xff)                         */
45631 #define TIMER_CTRL9_TMR9TMODE_Pos         (16UL)                    /*!< TMR9TMODE (Bit 16)                                    */
45632 #define TIMER_CTRL9_TMR9TMODE_Msk         (0x30000UL)               /*!< TMR9TMODE (Bitfield-Mask: 0x03)                       */
45633 #define TIMER_CTRL9_TMR9CLK_Pos           (8UL)                     /*!< TMR9CLK (Bit 8)                                       */
45634 #define TIMER_CTRL9_TMR9CLK_Msk           (0xff00UL)                /*!< TMR9CLK (Bitfield-Mask: 0xff)                         */
45635 #define TIMER_CTRL9_TMR9FN_Pos            (4UL)                     /*!< TMR9FN (Bit 4)                                        */
45636 #define TIMER_CTRL9_TMR9FN_Msk            (0xf0UL)                  /*!< TMR9FN (Bitfield-Mask: 0x0f)                          */
45637 #define TIMER_CTRL9_TMR9POL1_Pos          (3UL)                     /*!< TMR9POL1 (Bit 3)                                      */
45638 #define TIMER_CTRL9_TMR9POL1_Msk          (0x8UL)                   /*!< TMR9POL1 (Bitfield-Mask: 0x01)                        */
45639 #define TIMER_CTRL9_TMR9POL0_Pos          (2UL)                     /*!< TMR9POL0 (Bit 2)                                      */
45640 #define TIMER_CTRL9_TMR9POL0_Msk          (0x4UL)                   /*!< TMR9POL0 (Bitfield-Mask: 0x01)                        */
45641 #define TIMER_CTRL9_TMR9CLR_Pos           (1UL)                     /*!< TMR9CLR (Bit 1)                                       */
45642 #define TIMER_CTRL9_TMR9CLR_Msk           (0x2UL)                   /*!< TMR9CLR (Bitfield-Mask: 0x01)                         */
45643 #define TIMER_CTRL9_TMR9EN_Pos            (0UL)                     /*!< TMR9EN (Bit 0)                                        */
45644 #define TIMER_CTRL9_TMR9EN_Msk            (0x1UL)                   /*!< TMR9EN (Bitfield-Mask: 0x01)                          */
45645 /* ========================================================  TIMER9  ========================================================= */
45646 #define TIMER_TIMER9_TIMER9_Pos           (0UL)                     /*!< TIMER9 (Bit 0)                                        */
45647 #define TIMER_TIMER9_TIMER9_Msk           (0xffffffffUL)            /*!< TIMER9 (Bitfield-Mask: 0xffffffff)                    */
45648 /* =======================================================  TMR9CMP0  ======================================================== */
45649 #define TIMER_TMR9CMP0_TMR9CMP0_Pos       (0UL)                     /*!< TMR9CMP0 (Bit 0)                                      */
45650 #define TIMER_TMR9CMP0_TMR9CMP0_Msk       (0xffffffffUL)            /*!< TMR9CMP0 (Bitfield-Mask: 0xffffffff)                  */
45651 /* =======================================================  TMR9CMP1  ======================================================== */
45652 #define TIMER_TMR9CMP1_TMR9CMP1_Pos       (0UL)                     /*!< TMR9CMP1 (Bit 0)                                      */
45653 #define TIMER_TMR9CMP1_TMR9CMP1_Msk       (0xffffffffUL)            /*!< TMR9CMP1 (Bitfield-Mask: 0xffffffff)                  */
45654 /* =========================================================  MODE9  ========================================================= */
45655 #define TIMER_MODE9_TMR9TRIGSEL_Pos       (8UL)                     /*!< TMR9TRIGSEL (Bit 8)                                   */
45656 #define TIMER_MODE9_TMR9TRIGSEL_Msk       (0xff00UL)                /*!< TMR9TRIGSEL (Bitfield-Mask: 0xff)                     */
45657 /* ======================================================  TMR9LMTVAL  ======================================================= */
45658 #define TIMER_TMR9LMTVAL_TMR9LMTVAL_Pos   (0UL)                     /*!< TMR9LMTVAL (Bit 0)                                    */
45659 #define TIMER_TMR9LMTVAL_TMR9LMTVAL_Msk   (0xffUL)                  /*!< TMR9LMTVAL (Bitfield-Mask: 0xff)                      */
45660 /* ========================================================  CTRL10  ========================================================= */
45661 #define TIMER_CTRL10_TMR10LMT_Pos         (24UL)                    /*!< TMR10LMT (Bit 24)                                     */
45662 #define TIMER_CTRL10_TMR10LMT_Msk         (0xff000000UL)            /*!< TMR10LMT (Bitfield-Mask: 0xff)                        */
45663 #define TIMER_CTRL10_TMR10TMODE_Pos       (16UL)                    /*!< TMR10TMODE (Bit 16)                                   */
45664 #define TIMER_CTRL10_TMR10TMODE_Msk       (0x30000UL)               /*!< TMR10TMODE (Bitfield-Mask: 0x03)                      */
45665 #define TIMER_CTRL10_TMR10CLK_Pos         (8UL)                     /*!< TMR10CLK (Bit 8)                                      */
45666 #define TIMER_CTRL10_TMR10CLK_Msk         (0xff00UL)                /*!< TMR10CLK (Bitfield-Mask: 0xff)                        */
45667 #define TIMER_CTRL10_TMR10FN_Pos          (4UL)                     /*!< TMR10FN (Bit 4)                                       */
45668 #define TIMER_CTRL10_TMR10FN_Msk          (0xf0UL)                  /*!< TMR10FN (Bitfield-Mask: 0x0f)                         */
45669 #define TIMER_CTRL10_TMR10POL1_Pos        (3UL)                     /*!< TMR10POL1 (Bit 3)                                     */
45670 #define TIMER_CTRL10_TMR10POL1_Msk        (0x8UL)                   /*!< TMR10POL1 (Bitfield-Mask: 0x01)                       */
45671 #define TIMER_CTRL10_TMR10POL0_Pos        (2UL)                     /*!< TMR10POL0 (Bit 2)                                     */
45672 #define TIMER_CTRL10_TMR10POL0_Msk        (0x4UL)                   /*!< TMR10POL0 (Bitfield-Mask: 0x01)                       */
45673 #define TIMER_CTRL10_TMR10CLR_Pos         (1UL)                     /*!< TMR10CLR (Bit 1)                                      */
45674 #define TIMER_CTRL10_TMR10CLR_Msk         (0x2UL)                   /*!< TMR10CLR (Bitfield-Mask: 0x01)                        */
45675 #define TIMER_CTRL10_TMR10EN_Pos          (0UL)                     /*!< TMR10EN (Bit 0)                                       */
45676 #define TIMER_CTRL10_TMR10EN_Msk          (0x1UL)                   /*!< TMR10EN (Bitfield-Mask: 0x01)                         */
45677 /* ========================================================  TIMER10  ======================================================== */
45678 #define TIMER_TIMER10_TIMER10_Pos         (0UL)                     /*!< TIMER10 (Bit 0)                                       */
45679 #define TIMER_TIMER10_TIMER10_Msk         (0xffffffffUL)            /*!< TIMER10 (Bitfield-Mask: 0xffffffff)                   */
45680 /* =======================================================  TMR10CMP0  ======================================================= */
45681 #define TIMER_TMR10CMP0_TMR10CMP0_Pos     (0UL)                     /*!< TMR10CMP0 (Bit 0)                                     */
45682 #define TIMER_TMR10CMP0_TMR10CMP0_Msk     (0xffffffffUL)            /*!< TMR10CMP0 (Bitfield-Mask: 0xffffffff)                 */
45683 /* =======================================================  TMR10CMP1  ======================================================= */
45684 #define TIMER_TMR10CMP1_TMR10CMP1_Pos     (0UL)                     /*!< TMR10CMP1 (Bit 0)                                     */
45685 #define TIMER_TMR10CMP1_TMR10CMP1_Msk     (0xffffffffUL)            /*!< TMR10CMP1 (Bitfield-Mask: 0xffffffff)                 */
45686 /* ========================================================  MODE10  ========================================================= */
45687 #define TIMER_MODE10_TMR10TRIGSEL_Pos     (8UL)                     /*!< TMR10TRIGSEL (Bit 8)                                  */
45688 #define TIMER_MODE10_TMR10TRIGSEL_Msk     (0xff00UL)                /*!< TMR10TRIGSEL (Bitfield-Mask: 0xff)                    */
45689 /* ======================================================  TMR10LMTVAL  ====================================================== */
45690 #define TIMER_TMR10LMTVAL_TMR10LMTVAL_Pos (0UL)                     /*!< TMR10LMTVAL (Bit 0)                                   */
45691 #define TIMER_TMR10LMTVAL_TMR10LMTVAL_Msk (0xffUL)                  /*!< TMR10LMTVAL (Bitfield-Mask: 0xff)                     */
45692 /* ========================================================  CTRL11  ========================================================= */
45693 #define TIMER_CTRL11_TMR11LMT_Pos         (24UL)                    /*!< TMR11LMT (Bit 24)                                     */
45694 #define TIMER_CTRL11_TMR11LMT_Msk         (0xff000000UL)            /*!< TMR11LMT (Bitfield-Mask: 0xff)                        */
45695 #define TIMER_CTRL11_TMR11TMODE_Pos       (16UL)                    /*!< TMR11TMODE (Bit 16)                                   */
45696 #define TIMER_CTRL11_TMR11TMODE_Msk       (0x30000UL)               /*!< TMR11TMODE (Bitfield-Mask: 0x03)                      */
45697 #define TIMER_CTRL11_TMR11CLK_Pos         (8UL)                     /*!< TMR11CLK (Bit 8)                                      */
45698 #define TIMER_CTRL11_TMR11CLK_Msk         (0xff00UL)                /*!< TMR11CLK (Bitfield-Mask: 0xff)                        */
45699 #define TIMER_CTRL11_TMR11FN_Pos          (4UL)                     /*!< TMR11FN (Bit 4)                                       */
45700 #define TIMER_CTRL11_TMR11FN_Msk          (0xf0UL)                  /*!< TMR11FN (Bitfield-Mask: 0x0f)                         */
45701 #define TIMER_CTRL11_TMR11POL1_Pos        (3UL)                     /*!< TMR11POL1 (Bit 3)                                     */
45702 #define TIMER_CTRL11_TMR11POL1_Msk        (0x8UL)                   /*!< TMR11POL1 (Bitfield-Mask: 0x01)                       */
45703 #define TIMER_CTRL11_TMR11POL0_Pos        (2UL)                     /*!< TMR11POL0 (Bit 2)                                     */
45704 #define TIMER_CTRL11_TMR11POL0_Msk        (0x4UL)                   /*!< TMR11POL0 (Bitfield-Mask: 0x01)                       */
45705 #define TIMER_CTRL11_TMR11CLR_Pos         (1UL)                     /*!< TMR11CLR (Bit 1)                                      */
45706 #define TIMER_CTRL11_TMR11CLR_Msk         (0x2UL)                   /*!< TMR11CLR (Bitfield-Mask: 0x01)                        */
45707 #define TIMER_CTRL11_TMR11EN_Pos          (0UL)                     /*!< TMR11EN (Bit 0)                                       */
45708 #define TIMER_CTRL11_TMR11EN_Msk          (0x1UL)                   /*!< TMR11EN (Bitfield-Mask: 0x01)                         */
45709 /* ========================================================  TIMER11  ======================================================== */
45710 #define TIMER_TIMER11_TIMER11_Pos         (0UL)                     /*!< TIMER11 (Bit 0)                                       */
45711 #define TIMER_TIMER11_TIMER11_Msk         (0xffffffffUL)            /*!< TIMER11 (Bitfield-Mask: 0xffffffff)                   */
45712 /* =======================================================  TMR11CMP0  ======================================================= */
45713 #define TIMER_TMR11CMP0_TMR11CMP0_Pos     (0UL)                     /*!< TMR11CMP0 (Bit 0)                                     */
45714 #define TIMER_TMR11CMP0_TMR11CMP0_Msk     (0xffffffffUL)            /*!< TMR11CMP0 (Bitfield-Mask: 0xffffffff)                 */
45715 /* =======================================================  TMR11CMP1  ======================================================= */
45716 #define TIMER_TMR11CMP1_TMR11CMP1_Pos     (0UL)                     /*!< TMR11CMP1 (Bit 0)                                     */
45717 #define TIMER_TMR11CMP1_TMR11CMP1_Msk     (0xffffffffUL)            /*!< TMR11CMP1 (Bitfield-Mask: 0xffffffff)                 */
45718 /* ========================================================  MODE11  ========================================================= */
45719 #define TIMER_MODE11_TMR11TRIGSEL_Pos     (8UL)                     /*!< TMR11TRIGSEL (Bit 8)                                  */
45720 #define TIMER_MODE11_TMR11TRIGSEL_Msk     (0xff00UL)                /*!< TMR11TRIGSEL (Bitfield-Mask: 0xff)                    */
45721 /* ======================================================  TMR11LMTVAL  ====================================================== */
45722 #define TIMER_TMR11LMTVAL_TMR11LMTVAL_Pos (0UL)                     /*!< TMR11LMTVAL (Bit 0)                                   */
45723 #define TIMER_TMR11LMTVAL_TMR11LMTVAL_Msk (0xffUL)                  /*!< TMR11LMTVAL (Bitfield-Mask: 0xff)                     */
45724 /* ========================================================  CTRL12  ========================================================= */
45725 #define TIMER_CTRL12_TMR12LMT_Pos         (24UL)                    /*!< TMR12LMT (Bit 24)                                     */
45726 #define TIMER_CTRL12_TMR12LMT_Msk         (0xff000000UL)            /*!< TMR12LMT (Bitfield-Mask: 0xff)                        */
45727 #define TIMER_CTRL12_TMR12TMODE_Pos       (16UL)                    /*!< TMR12TMODE (Bit 16)                                   */
45728 #define TIMER_CTRL12_TMR12TMODE_Msk       (0x30000UL)               /*!< TMR12TMODE (Bitfield-Mask: 0x03)                      */
45729 #define TIMER_CTRL12_TMR12CLK_Pos         (8UL)                     /*!< TMR12CLK (Bit 8)                                      */
45730 #define TIMER_CTRL12_TMR12CLK_Msk         (0xff00UL)                /*!< TMR12CLK (Bitfield-Mask: 0xff)                        */
45731 #define TIMER_CTRL12_TMR12FN_Pos          (4UL)                     /*!< TMR12FN (Bit 4)                                       */
45732 #define TIMER_CTRL12_TMR12FN_Msk          (0xf0UL)                  /*!< TMR12FN (Bitfield-Mask: 0x0f)                         */
45733 #define TIMER_CTRL12_TMR12POL1_Pos        (3UL)                     /*!< TMR12POL1 (Bit 3)                                     */
45734 #define TIMER_CTRL12_TMR12POL1_Msk        (0x8UL)                   /*!< TMR12POL1 (Bitfield-Mask: 0x01)                       */
45735 #define TIMER_CTRL12_TMR12POL0_Pos        (2UL)                     /*!< TMR12POL0 (Bit 2)                                     */
45736 #define TIMER_CTRL12_TMR12POL0_Msk        (0x4UL)                   /*!< TMR12POL0 (Bitfield-Mask: 0x01)                       */
45737 #define TIMER_CTRL12_TMR12CLR_Pos         (1UL)                     /*!< TMR12CLR (Bit 1)                                      */
45738 #define TIMER_CTRL12_TMR12CLR_Msk         (0x2UL)                   /*!< TMR12CLR (Bitfield-Mask: 0x01)                        */
45739 #define TIMER_CTRL12_TMR12EN_Pos          (0UL)                     /*!< TMR12EN (Bit 0)                                       */
45740 #define TIMER_CTRL12_TMR12EN_Msk          (0x1UL)                   /*!< TMR12EN (Bitfield-Mask: 0x01)                         */
45741 /* ========================================================  TIMER12  ======================================================== */
45742 #define TIMER_TIMER12_TIMER12_Pos         (0UL)                     /*!< TIMER12 (Bit 0)                                       */
45743 #define TIMER_TIMER12_TIMER12_Msk         (0xffffffffUL)            /*!< TIMER12 (Bitfield-Mask: 0xffffffff)                   */
45744 /* =======================================================  TMR12CMP0  ======================================================= */
45745 #define TIMER_TMR12CMP0_TMR12CMP0_Pos     (0UL)                     /*!< TMR12CMP0 (Bit 0)                                     */
45746 #define TIMER_TMR12CMP0_TMR12CMP0_Msk     (0xffffffffUL)            /*!< TMR12CMP0 (Bitfield-Mask: 0xffffffff)                 */
45747 /* =======================================================  TMR12CMP1  ======================================================= */
45748 #define TIMER_TMR12CMP1_TMR12CMP1_Pos     (0UL)                     /*!< TMR12CMP1 (Bit 0)                                     */
45749 #define TIMER_TMR12CMP1_TMR12CMP1_Msk     (0xffffffffUL)            /*!< TMR12CMP1 (Bitfield-Mask: 0xffffffff)                 */
45750 /* ========================================================  MODE12  ========================================================= */
45751 #define TIMER_MODE12_TMR12TRIGSEL_Pos     (8UL)                     /*!< TMR12TRIGSEL (Bit 8)                                  */
45752 #define TIMER_MODE12_TMR12TRIGSEL_Msk     (0xff00UL)                /*!< TMR12TRIGSEL (Bitfield-Mask: 0xff)                    */
45753 /* ======================================================  TMR12LMTVAL  ====================================================== */
45754 #define TIMER_TMR12LMTVAL_TMR12LMTVAL_Pos (0UL)                     /*!< TMR12LMTVAL (Bit 0)                                   */
45755 #define TIMER_TMR12LMTVAL_TMR12LMTVAL_Msk (0xffUL)                  /*!< TMR12LMTVAL (Bitfield-Mask: 0xff)                     */
45756 /* ========================================================  CTRL13  ========================================================= */
45757 #define TIMER_CTRL13_TMR13LMT_Pos         (24UL)                    /*!< TMR13LMT (Bit 24)                                     */
45758 #define TIMER_CTRL13_TMR13LMT_Msk         (0xff000000UL)            /*!< TMR13LMT (Bitfield-Mask: 0xff)                        */
45759 #define TIMER_CTRL13_TMR13TMODE_Pos       (16UL)                    /*!< TMR13TMODE (Bit 16)                                   */
45760 #define TIMER_CTRL13_TMR13TMODE_Msk       (0x30000UL)               /*!< TMR13TMODE (Bitfield-Mask: 0x03)                      */
45761 #define TIMER_CTRL13_TMR13CLK_Pos         (8UL)                     /*!< TMR13CLK (Bit 8)                                      */
45762 #define TIMER_CTRL13_TMR13CLK_Msk         (0xff00UL)                /*!< TMR13CLK (Bitfield-Mask: 0xff)                        */
45763 #define TIMER_CTRL13_TMR13FN_Pos          (4UL)                     /*!< TMR13FN (Bit 4)                                       */
45764 #define TIMER_CTRL13_TMR13FN_Msk          (0xf0UL)                  /*!< TMR13FN (Bitfield-Mask: 0x0f)                         */
45765 #define TIMER_CTRL13_TMR13POL1_Pos        (3UL)                     /*!< TMR13POL1 (Bit 3)                                     */
45766 #define TIMER_CTRL13_TMR13POL1_Msk        (0x8UL)                   /*!< TMR13POL1 (Bitfield-Mask: 0x01)                       */
45767 #define TIMER_CTRL13_TMR13POL0_Pos        (2UL)                     /*!< TMR13POL0 (Bit 2)                                     */
45768 #define TIMER_CTRL13_TMR13POL0_Msk        (0x4UL)                   /*!< TMR13POL0 (Bitfield-Mask: 0x01)                       */
45769 #define TIMER_CTRL13_TMR13CLR_Pos         (1UL)                     /*!< TMR13CLR (Bit 1)                                      */
45770 #define TIMER_CTRL13_TMR13CLR_Msk         (0x2UL)                   /*!< TMR13CLR (Bitfield-Mask: 0x01)                        */
45771 #define TIMER_CTRL13_TMR13EN_Pos          (0UL)                     /*!< TMR13EN (Bit 0)                                       */
45772 #define TIMER_CTRL13_TMR13EN_Msk          (0x1UL)                   /*!< TMR13EN (Bitfield-Mask: 0x01)                         */
45773 /* ========================================================  TIMER13  ======================================================== */
45774 #define TIMER_TIMER13_TIMER13_Pos         (0UL)                     /*!< TIMER13 (Bit 0)                                       */
45775 #define TIMER_TIMER13_TIMER13_Msk         (0xffffffffUL)            /*!< TIMER13 (Bitfield-Mask: 0xffffffff)                   */
45776 /* =======================================================  TMR13CMP0  ======================================================= */
45777 #define TIMER_TMR13CMP0_TMR13CMP0_Pos     (0UL)                     /*!< TMR13CMP0 (Bit 0)                                     */
45778 #define TIMER_TMR13CMP0_TMR13CMP0_Msk     (0xffffffffUL)            /*!< TMR13CMP0 (Bitfield-Mask: 0xffffffff)                 */
45779 /* =======================================================  TMR13CMP1  ======================================================= */
45780 #define TIMER_TMR13CMP1_TMR13CMP1_Pos     (0UL)                     /*!< TMR13CMP1 (Bit 0)                                     */
45781 #define TIMER_TMR13CMP1_TMR13CMP1_Msk     (0xffffffffUL)            /*!< TMR13CMP1 (Bitfield-Mask: 0xffffffff)                 */
45782 /* ========================================================  MODE13  ========================================================= */
45783 #define TIMER_MODE13_TMR13TRIGSEL_Pos     (8UL)                     /*!< TMR13TRIGSEL (Bit 8)                                  */
45784 #define TIMER_MODE13_TMR13TRIGSEL_Msk     (0xff00UL)                /*!< TMR13TRIGSEL (Bitfield-Mask: 0xff)                    */
45785 /* ======================================================  TMR13LMTVAL  ====================================================== */
45786 #define TIMER_TMR13LMTVAL_TMR13LMTVAL_Pos (0UL)                     /*!< TMR13LMTVAL (Bit 0)                                   */
45787 #define TIMER_TMR13LMTVAL_TMR13LMTVAL_Msk (0xffUL)                  /*!< TMR13LMTVAL (Bitfield-Mask: 0xff)                     */
45788 /* ========================================================  CTRL14  ========================================================= */
45789 #define TIMER_CTRL14_TMR14LMT_Pos         (24UL)                    /*!< TMR14LMT (Bit 24)                                     */
45790 #define TIMER_CTRL14_TMR14LMT_Msk         (0xff000000UL)            /*!< TMR14LMT (Bitfield-Mask: 0xff)                        */
45791 #define TIMER_CTRL14_TMR14TMODE_Pos       (16UL)                    /*!< TMR14TMODE (Bit 16)                                   */
45792 #define TIMER_CTRL14_TMR14TMODE_Msk       (0x30000UL)               /*!< TMR14TMODE (Bitfield-Mask: 0x03)                      */
45793 #define TIMER_CTRL14_TMR14CLK_Pos         (8UL)                     /*!< TMR14CLK (Bit 8)                                      */
45794 #define TIMER_CTRL14_TMR14CLK_Msk         (0xff00UL)                /*!< TMR14CLK (Bitfield-Mask: 0xff)                        */
45795 #define TIMER_CTRL14_TMR14FN_Pos          (4UL)                     /*!< TMR14FN (Bit 4)                                       */
45796 #define TIMER_CTRL14_TMR14FN_Msk          (0xf0UL)                  /*!< TMR14FN (Bitfield-Mask: 0x0f)                         */
45797 #define TIMER_CTRL14_TMR14POL1_Pos        (3UL)                     /*!< TMR14POL1 (Bit 3)                                     */
45798 #define TIMER_CTRL14_TMR14POL1_Msk        (0x8UL)                   /*!< TMR14POL1 (Bitfield-Mask: 0x01)                       */
45799 #define TIMER_CTRL14_TMR14POL0_Pos        (2UL)                     /*!< TMR14POL0 (Bit 2)                                     */
45800 #define TIMER_CTRL14_TMR14POL0_Msk        (0x4UL)                   /*!< TMR14POL0 (Bitfield-Mask: 0x01)                       */
45801 #define TIMER_CTRL14_TMR14CLR_Pos         (1UL)                     /*!< TMR14CLR (Bit 1)                                      */
45802 #define TIMER_CTRL14_TMR14CLR_Msk         (0x2UL)                   /*!< TMR14CLR (Bitfield-Mask: 0x01)                        */
45803 #define TIMER_CTRL14_TMR14EN_Pos          (0UL)                     /*!< TMR14EN (Bit 0)                                       */
45804 #define TIMER_CTRL14_TMR14EN_Msk          (0x1UL)                   /*!< TMR14EN (Bitfield-Mask: 0x01)                         */
45805 /* ========================================================  TIMER14  ======================================================== */
45806 #define TIMER_TIMER14_TIMER14_Pos         (0UL)                     /*!< TIMER14 (Bit 0)                                       */
45807 #define TIMER_TIMER14_TIMER14_Msk         (0xffffffffUL)            /*!< TIMER14 (Bitfield-Mask: 0xffffffff)                   */
45808 /* =======================================================  TMR14CMP0  ======================================================= */
45809 #define TIMER_TMR14CMP0_TMR14CMP0_Pos     (0UL)                     /*!< TMR14CMP0 (Bit 0)                                     */
45810 #define TIMER_TMR14CMP0_TMR14CMP0_Msk     (0xffffffffUL)            /*!< TMR14CMP0 (Bitfield-Mask: 0xffffffff)                 */
45811 /* =======================================================  TMR14CMP1  ======================================================= */
45812 #define TIMER_TMR14CMP1_TMR14CMP1_Pos     (0UL)                     /*!< TMR14CMP1 (Bit 0)                                     */
45813 #define TIMER_TMR14CMP1_TMR14CMP1_Msk     (0xffffffffUL)            /*!< TMR14CMP1 (Bitfield-Mask: 0xffffffff)                 */
45814 /* ========================================================  MODE14  ========================================================= */
45815 #define TIMER_MODE14_TMR14TRIGSEL_Pos     (8UL)                     /*!< TMR14TRIGSEL (Bit 8)                                  */
45816 #define TIMER_MODE14_TMR14TRIGSEL_Msk     (0xff00UL)                /*!< TMR14TRIGSEL (Bitfield-Mask: 0xff)                    */
45817 /* ======================================================  TMR14LMTVAL  ====================================================== */
45818 #define TIMER_TMR14LMTVAL_TMR14LMTVAL_Pos (0UL)                     /*!< TMR14LMTVAL (Bit 0)                                   */
45819 #define TIMER_TMR14LMTVAL_TMR14LMTVAL_Msk (0xffUL)                  /*!< TMR14LMTVAL (Bitfield-Mask: 0xff)                     */
45820 /* ========================================================  CTRL15  ========================================================= */
45821 #define TIMER_CTRL15_TMR15LMT_Pos         (24UL)                    /*!< TMR15LMT (Bit 24)                                     */
45822 #define TIMER_CTRL15_TMR15LMT_Msk         (0xff000000UL)            /*!< TMR15LMT (Bitfield-Mask: 0xff)                        */
45823 #define TIMER_CTRL15_TMR15TMODE_Pos       (16UL)                    /*!< TMR15TMODE (Bit 16)                                   */
45824 #define TIMER_CTRL15_TMR15TMODE_Msk       (0x30000UL)               /*!< TMR15TMODE (Bitfield-Mask: 0x03)                      */
45825 #define TIMER_CTRL15_TMR15CLK_Pos         (8UL)                     /*!< TMR15CLK (Bit 8)                                      */
45826 #define TIMER_CTRL15_TMR15CLK_Msk         (0xff00UL)                /*!< TMR15CLK (Bitfield-Mask: 0xff)                        */
45827 #define TIMER_CTRL15_TMR15FN_Pos          (4UL)                     /*!< TMR15FN (Bit 4)                                       */
45828 #define TIMER_CTRL15_TMR15FN_Msk          (0xf0UL)                  /*!< TMR15FN (Bitfield-Mask: 0x0f)                         */
45829 #define TIMER_CTRL15_TMR15POL1_Pos        (3UL)                     /*!< TMR15POL1 (Bit 3)                                     */
45830 #define TIMER_CTRL15_TMR15POL1_Msk        (0x8UL)                   /*!< TMR15POL1 (Bitfield-Mask: 0x01)                       */
45831 #define TIMER_CTRL15_TMR15POL0_Pos        (2UL)                     /*!< TMR15POL0 (Bit 2)                                     */
45832 #define TIMER_CTRL15_TMR15POL0_Msk        (0x4UL)                   /*!< TMR15POL0 (Bitfield-Mask: 0x01)                       */
45833 #define TIMER_CTRL15_TMR15CLR_Pos         (1UL)                     /*!< TMR15CLR (Bit 1)                                      */
45834 #define TIMER_CTRL15_TMR15CLR_Msk         (0x2UL)                   /*!< TMR15CLR (Bitfield-Mask: 0x01)                        */
45835 #define TIMER_CTRL15_TMR15EN_Pos          (0UL)                     /*!< TMR15EN (Bit 0)                                       */
45836 #define TIMER_CTRL15_TMR15EN_Msk          (0x1UL)                   /*!< TMR15EN (Bitfield-Mask: 0x01)                         */
45837 /* ========================================================  TIMER15  ======================================================== */
45838 #define TIMER_TIMER15_TIMER15_Pos         (0UL)                     /*!< TIMER15 (Bit 0)                                       */
45839 #define TIMER_TIMER15_TIMER15_Msk         (0xffffffffUL)            /*!< TIMER15 (Bitfield-Mask: 0xffffffff)                   */
45840 /* =======================================================  TMR15CMP0  ======================================================= */
45841 #define TIMER_TMR15CMP0_TMR15CMP0_Pos     (0UL)                     /*!< TMR15CMP0 (Bit 0)                                     */
45842 #define TIMER_TMR15CMP0_TMR15CMP0_Msk     (0xffffffffUL)            /*!< TMR15CMP0 (Bitfield-Mask: 0xffffffff)                 */
45843 /* =======================================================  TMR15CMP1  ======================================================= */
45844 #define TIMER_TMR15CMP1_TMR15CMP1_Pos     (0UL)                     /*!< TMR15CMP1 (Bit 0)                                     */
45845 #define TIMER_TMR15CMP1_TMR15CMP1_Msk     (0xffffffffUL)            /*!< TMR15CMP1 (Bitfield-Mask: 0xffffffff)                 */
45846 /* ========================================================  MODE15  ========================================================= */
45847 #define TIMER_MODE15_TMR15TRIGSEL_Pos     (8UL)                     /*!< TMR15TRIGSEL (Bit 8)                                  */
45848 #define TIMER_MODE15_TMR15TRIGSEL_Msk     (0xff00UL)                /*!< TMR15TRIGSEL (Bitfield-Mask: 0xff)                    */
45849 /* ======================================================  TMR15LMTVAL  ====================================================== */
45850 #define TIMER_TMR15LMTVAL_TMR15LMTVAL_Pos (0UL)                     /*!< TMR15LMTVAL (Bit 0)                                   */
45851 #define TIMER_TMR15LMTVAL_TMR15LMTVAL_Msk (0xffUL)                  /*!< TMR15LMTVAL (Bitfield-Mask: 0xff)                     */
45852 /* ======================================================  TIMERSPARES  ====================================================== */
45853 #define TIMER_TIMERSPARES_TMRSPARES_Pos   (0UL)                     /*!< TMRSPARES (Bit 0)                                     */
45854 #define TIMER_TIMERSPARES_TMRSPARES_Msk   (0xffffffffUL)            /*!< TMRSPARES (Bitfield-Mask: 0xffffffff)                 */
45855 
45856 
45857 /* =========================================================================================================================== */
45858 /* ================                                           UART0                                           ================ */
45859 /* =========================================================================================================================== */
45860 
45861 /* ==========================================================  DR  =========================================================== */
45862 #define UART0_DR_OEDATA_Pos               (11UL)                    /*!< OEDATA (Bit 11)                                       */
45863 #define UART0_DR_OEDATA_Msk               (0x800UL)                 /*!< OEDATA (Bitfield-Mask: 0x01)                          */
45864 #define UART0_DR_BEDATA_Pos               (10UL)                    /*!< BEDATA (Bit 10)                                       */
45865 #define UART0_DR_BEDATA_Msk               (0x400UL)                 /*!< BEDATA (Bitfield-Mask: 0x01)                          */
45866 #define UART0_DR_PEDATA_Pos               (9UL)                     /*!< PEDATA (Bit 9)                                        */
45867 #define UART0_DR_PEDATA_Msk               (0x200UL)                 /*!< PEDATA (Bitfield-Mask: 0x01)                          */
45868 #define UART0_DR_FEDATA_Pos               (8UL)                     /*!< FEDATA (Bit 8)                                        */
45869 #define UART0_DR_FEDATA_Msk               (0x100UL)                 /*!< FEDATA (Bitfield-Mask: 0x01)                          */
45870 #define UART0_DR_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
45871 #define UART0_DR_DATA_Msk                 (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
45872 /* ==========================================================  RSR  ========================================================== */
45873 #define UART0_RSR_OESTAT_Pos              (3UL)                     /*!< OESTAT (Bit 3)                                        */
45874 #define UART0_RSR_OESTAT_Msk              (0x8UL)                   /*!< OESTAT (Bitfield-Mask: 0x01)                          */
45875 #define UART0_RSR_BESTAT_Pos              (2UL)                     /*!< BESTAT (Bit 2)                                        */
45876 #define UART0_RSR_BESTAT_Msk              (0x4UL)                   /*!< BESTAT (Bitfield-Mask: 0x01)                          */
45877 #define UART0_RSR_PESTAT_Pos              (1UL)                     /*!< PESTAT (Bit 1)                                        */
45878 #define UART0_RSR_PESTAT_Msk              (0x2UL)                   /*!< PESTAT (Bitfield-Mask: 0x01)                          */
45879 #define UART0_RSR_FESTAT_Pos              (0UL)                     /*!< FESTAT (Bit 0)                                        */
45880 #define UART0_RSR_FESTAT_Msk              (0x1UL)                   /*!< FESTAT (Bitfield-Mask: 0x01)                          */
45881 /* ==========================================================  FR  =========================================================== */
45882 #define UART0_FR_TXBUSY_Pos               (8UL)                     /*!< TXBUSY (Bit 8)                                        */
45883 #define UART0_FR_TXBUSY_Msk               (0x100UL)                 /*!< TXBUSY (Bitfield-Mask: 0x01)                          */
45884 #define UART0_FR_TXFE_Pos                 (7UL)                     /*!< TXFE (Bit 7)                                          */
45885 #define UART0_FR_TXFE_Msk                 (0x80UL)                  /*!< TXFE (Bitfield-Mask: 0x01)                            */
45886 #define UART0_FR_RXFF_Pos                 (6UL)                     /*!< RXFF (Bit 6)                                          */
45887 #define UART0_FR_RXFF_Msk                 (0x40UL)                  /*!< RXFF (Bitfield-Mask: 0x01)                            */
45888 #define UART0_FR_TXFF_Pos                 (5UL)                     /*!< TXFF (Bit 5)                                          */
45889 #define UART0_FR_TXFF_Msk                 (0x20UL)                  /*!< TXFF (Bitfield-Mask: 0x01)                            */
45890 #define UART0_FR_RXFE_Pos                 (4UL)                     /*!< RXFE (Bit 4)                                          */
45891 #define UART0_FR_RXFE_Msk                 (0x10UL)                  /*!< RXFE (Bitfield-Mask: 0x01)                            */
45892 #define UART0_FR_BUSY_Pos                 (3UL)                     /*!< BUSY (Bit 3)                                          */
45893 #define UART0_FR_BUSY_Msk                 (0x8UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
45894 #define UART0_FR_DCD_Pos                  (2UL)                     /*!< DCD (Bit 2)                                           */
45895 #define UART0_FR_DCD_Msk                  (0x4UL)                   /*!< DCD (Bitfield-Mask: 0x01)                             */
45896 #define UART0_FR_DSR_Pos                  (1UL)                     /*!< DSR (Bit 1)                                           */
45897 #define UART0_FR_DSR_Msk                  (0x2UL)                   /*!< DSR (Bitfield-Mask: 0x01)                             */
45898 #define UART0_FR_CTS_Pos                  (0UL)                     /*!< CTS (Bit 0)                                           */
45899 #define UART0_FR_CTS_Msk                  (0x1UL)                   /*!< CTS (Bitfield-Mask: 0x01)                             */
45900 /* =========================================================  ILPR  ========================================================== */
45901 #define UART0_ILPR_ILPDVSR_Pos            (0UL)                     /*!< ILPDVSR (Bit 0)                                       */
45902 #define UART0_ILPR_ILPDVSR_Msk            (0xffUL)                  /*!< ILPDVSR (Bitfield-Mask: 0xff)                         */
45903 /* =========================================================  IBRD  ========================================================== */
45904 #define UART0_IBRD_DIVINT_Pos             (0UL)                     /*!< DIVINT (Bit 0)                                        */
45905 #define UART0_IBRD_DIVINT_Msk             (0xffffUL)                /*!< DIVINT (Bitfield-Mask: 0xffff)                        */
45906 /* =========================================================  FBRD  ========================================================== */
45907 #define UART0_FBRD_DIVFRAC_Pos            (0UL)                     /*!< DIVFRAC (Bit 0)                                       */
45908 #define UART0_FBRD_DIVFRAC_Msk            (0x3fUL)                  /*!< DIVFRAC (Bitfield-Mask: 0x3f)                         */
45909 /* =========================================================  LCRH  ========================================================== */
45910 #define UART0_LCRH_SPS_Pos                (7UL)                     /*!< SPS (Bit 7)                                           */
45911 #define UART0_LCRH_SPS_Msk                (0x80UL)                  /*!< SPS (Bitfield-Mask: 0x01)                             */
45912 #define UART0_LCRH_WLEN_Pos               (5UL)                     /*!< WLEN (Bit 5)                                          */
45913 #define UART0_LCRH_WLEN_Msk               (0x60UL)                  /*!< WLEN (Bitfield-Mask: 0x03)                            */
45914 #define UART0_LCRH_FEN_Pos                (4UL)                     /*!< FEN (Bit 4)                                           */
45915 #define UART0_LCRH_FEN_Msk                (0x10UL)                  /*!< FEN (Bitfield-Mask: 0x01)                             */
45916 #define UART0_LCRH_STP2_Pos               (3UL)                     /*!< STP2 (Bit 3)                                          */
45917 #define UART0_LCRH_STP2_Msk               (0x8UL)                   /*!< STP2 (Bitfield-Mask: 0x01)                            */
45918 #define UART0_LCRH_EPS_Pos                (2UL)                     /*!< EPS (Bit 2)                                           */
45919 #define UART0_LCRH_EPS_Msk                (0x4UL)                   /*!< EPS (Bitfield-Mask: 0x01)                             */
45920 #define UART0_LCRH_PEN_Pos                (1UL)                     /*!< PEN (Bit 1)                                           */
45921 #define UART0_LCRH_PEN_Msk                (0x2UL)                   /*!< PEN (Bitfield-Mask: 0x01)                             */
45922 #define UART0_LCRH_BRK_Pos                (0UL)                     /*!< BRK (Bit 0)                                           */
45923 #define UART0_LCRH_BRK_Msk                (0x1UL)                   /*!< BRK (Bitfield-Mask: 0x01)                             */
45924 /* ==========================================================  CR  =========================================================== */
45925 #define UART0_CR_CTSEN_Pos                (15UL)                    /*!< CTSEN (Bit 15)                                        */
45926 #define UART0_CR_CTSEN_Msk                (0x8000UL)                /*!< CTSEN (Bitfield-Mask: 0x01)                           */
45927 #define UART0_CR_RTSEN_Pos                (14UL)                    /*!< RTSEN (Bit 14)                                        */
45928 #define UART0_CR_RTSEN_Msk                (0x4000UL)                /*!< RTSEN (Bitfield-Mask: 0x01)                           */
45929 #define UART0_CR_OUT2_Pos                 (13UL)                    /*!< OUT2 (Bit 13)                                         */
45930 #define UART0_CR_OUT2_Msk                 (0x2000UL)                /*!< OUT2 (Bitfield-Mask: 0x01)                            */
45931 #define UART0_CR_OUT1_Pos                 (12UL)                    /*!< OUT1 (Bit 12)                                         */
45932 #define UART0_CR_OUT1_Msk                 (0x1000UL)                /*!< OUT1 (Bitfield-Mask: 0x01)                            */
45933 #define UART0_CR_RTS_Pos                  (11UL)                    /*!< RTS (Bit 11)                                          */
45934 #define UART0_CR_RTS_Msk                  (0x800UL)                 /*!< RTS (Bitfield-Mask: 0x01)                             */
45935 #define UART0_CR_DTR_Pos                  (10UL)                    /*!< DTR (Bit 10)                                          */
45936 #define UART0_CR_DTR_Msk                  (0x400UL)                 /*!< DTR (Bitfield-Mask: 0x01)                             */
45937 #define UART0_CR_RXE_Pos                  (9UL)                     /*!< RXE (Bit 9)                                           */
45938 #define UART0_CR_RXE_Msk                  (0x200UL)                 /*!< RXE (Bitfield-Mask: 0x01)                             */
45939 #define UART0_CR_TXE_Pos                  (8UL)                     /*!< TXE (Bit 8)                                           */
45940 #define UART0_CR_TXE_Msk                  (0x100UL)                 /*!< TXE (Bitfield-Mask: 0x01)                             */
45941 #define UART0_CR_LBE_Pos                  (7UL)                     /*!< LBE (Bit 7)                                           */
45942 #define UART0_CR_LBE_Msk                  (0x80UL)                  /*!< LBE (Bitfield-Mask: 0x01)                             */
45943 #define UART0_CR_CLKSEL_Pos               (4UL)                     /*!< CLKSEL (Bit 4)                                        */
45944 #define UART0_CR_CLKSEL_Msk               (0x70UL)                  /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
45945 #define UART0_CR_CLKEN_Pos                (3UL)                     /*!< CLKEN (Bit 3)                                         */
45946 #define UART0_CR_CLKEN_Msk                (0x8UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
45947 #define UART0_CR_SIRLP_Pos                (2UL)                     /*!< SIRLP (Bit 2)                                         */
45948 #define UART0_CR_SIRLP_Msk                (0x4UL)                   /*!< SIRLP (Bitfield-Mask: 0x01)                           */
45949 #define UART0_CR_SIREN_Pos                (1UL)                     /*!< SIREN (Bit 1)                                         */
45950 #define UART0_CR_SIREN_Msk                (0x2UL)                   /*!< SIREN (Bitfield-Mask: 0x01)                           */
45951 #define UART0_CR_UARTEN_Pos               (0UL)                     /*!< UARTEN (Bit 0)                                        */
45952 #define UART0_CR_UARTEN_Msk               (0x1UL)                   /*!< UARTEN (Bitfield-Mask: 0x01)                          */
45953 /* =========================================================  IFLS  ========================================================== */
45954 #define UART0_IFLS_RXIFLSEL_Pos           (3UL)                     /*!< RXIFLSEL (Bit 3)                                      */
45955 #define UART0_IFLS_RXIFLSEL_Msk           (0x38UL)                  /*!< RXIFLSEL (Bitfield-Mask: 0x07)                        */
45956 #define UART0_IFLS_TXIFLSEL_Pos           (0UL)                     /*!< TXIFLSEL (Bit 0)                                      */
45957 #define UART0_IFLS_TXIFLSEL_Msk           (0x7UL)                   /*!< TXIFLSEL (Bitfield-Mask: 0x07)                        */
45958 /* ==========================================================  IER  ========================================================== */
45959 #define UART0_IER_OEIM_Pos                (10UL)                    /*!< OEIM (Bit 10)                                         */
45960 #define UART0_IER_OEIM_Msk                (0x400UL)                 /*!< OEIM (Bitfield-Mask: 0x01)                            */
45961 #define UART0_IER_BEIM_Pos                (9UL)                     /*!< BEIM (Bit 9)                                          */
45962 #define UART0_IER_BEIM_Msk                (0x200UL)                 /*!< BEIM (Bitfield-Mask: 0x01)                            */
45963 #define UART0_IER_PEIM_Pos                (8UL)                     /*!< PEIM (Bit 8)                                          */
45964 #define UART0_IER_PEIM_Msk                (0x100UL)                 /*!< PEIM (Bitfield-Mask: 0x01)                            */
45965 #define UART0_IER_FEIM_Pos                (7UL)                     /*!< FEIM (Bit 7)                                          */
45966 #define UART0_IER_FEIM_Msk                (0x80UL)                  /*!< FEIM (Bitfield-Mask: 0x01)                            */
45967 #define UART0_IER_RTIM_Pos                (6UL)                     /*!< RTIM (Bit 6)                                          */
45968 #define UART0_IER_RTIM_Msk                (0x40UL)                  /*!< RTIM (Bitfield-Mask: 0x01)                            */
45969 #define UART0_IER_TXIM_Pos                (5UL)                     /*!< TXIM (Bit 5)                                          */
45970 #define UART0_IER_TXIM_Msk                (0x20UL)                  /*!< TXIM (Bitfield-Mask: 0x01)                            */
45971 #define UART0_IER_RXIM_Pos                (4UL)                     /*!< RXIM (Bit 4)                                          */
45972 #define UART0_IER_RXIM_Msk                (0x10UL)                  /*!< RXIM (Bitfield-Mask: 0x01)                            */
45973 #define UART0_IER_DSRMIM_Pos              (3UL)                     /*!< DSRMIM (Bit 3)                                        */
45974 #define UART0_IER_DSRMIM_Msk              (0x8UL)                   /*!< DSRMIM (Bitfield-Mask: 0x01)                          */
45975 #define UART0_IER_DCDMIM_Pos              (2UL)                     /*!< DCDMIM (Bit 2)                                        */
45976 #define UART0_IER_DCDMIM_Msk              (0x4UL)                   /*!< DCDMIM (Bitfield-Mask: 0x01)                          */
45977 #define UART0_IER_CTSMIM_Pos              (1UL)                     /*!< CTSMIM (Bit 1)                                        */
45978 #define UART0_IER_CTSMIM_Msk              (0x2UL)                   /*!< CTSMIM (Bitfield-Mask: 0x01)                          */
45979 #define UART0_IER_TXCMPMIM_Pos            (0UL)                     /*!< TXCMPMIM (Bit 0)                                      */
45980 #define UART0_IER_TXCMPMIM_Msk            (0x1UL)                   /*!< TXCMPMIM (Bitfield-Mask: 0x01)                        */
45981 /* ==========================================================  IES  ========================================================== */
45982 #define UART0_IES_OERIS_Pos               (10UL)                    /*!< OERIS (Bit 10)                                        */
45983 #define UART0_IES_OERIS_Msk               (0x400UL)                 /*!< OERIS (Bitfield-Mask: 0x01)                           */
45984 #define UART0_IES_BERIS_Pos               (9UL)                     /*!< BERIS (Bit 9)                                         */
45985 #define UART0_IES_BERIS_Msk               (0x200UL)                 /*!< BERIS (Bitfield-Mask: 0x01)                           */
45986 #define UART0_IES_PERIS_Pos               (8UL)                     /*!< PERIS (Bit 8)                                         */
45987 #define UART0_IES_PERIS_Msk               (0x100UL)                 /*!< PERIS (Bitfield-Mask: 0x01)                           */
45988 #define UART0_IES_FERIS_Pos               (7UL)                     /*!< FERIS (Bit 7)                                         */
45989 #define UART0_IES_FERIS_Msk               (0x80UL)                  /*!< FERIS (Bitfield-Mask: 0x01)                           */
45990 #define UART0_IES_RTRIS_Pos               (6UL)                     /*!< RTRIS (Bit 6)                                         */
45991 #define UART0_IES_RTRIS_Msk               (0x40UL)                  /*!< RTRIS (Bitfield-Mask: 0x01)                           */
45992 #define UART0_IES_TXRIS_Pos               (5UL)                     /*!< TXRIS (Bit 5)                                         */
45993 #define UART0_IES_TXRIS_Msk               (0x20UL)                  /*!< TXRIS (Bitfield-Mask: 0x01)                           */
45994 #define UART0_IES_RXRIS_Pos               (4UL)                     /*!< RXRIS (Bit 4)                                         */
45995 #define UART0_IES_RXRIS_Msk               (0x10UL)                  /*!< RXRIS (Bitfield-Mask: 0x01)                           */
45996 #define UART0_IES_DSRMRIS_Pos             (3UL)                     /*!< DSRMRIS (Bit 3)                                       */
45997 #define UART0_IES_DSRMRIS_Msk             (0x8UL)                   /*!< DSRMRIS (Bitfield-Mask: 0x01)                         */
45998 #define UART0_IES_DCDMRIS_Pos             (2UL)                     /*!< DCDMRIS (Bit 2)                                       */
45999 #define UART0_IES_DCDMRIS_Msk             (0x4UL)                   /*!< DCDMRIS (Bitfield-Mask: 0x01)                         */
46000 #define UART0_IES_CTSMRIS_Pos             (1UL)                     /*!< CTSMRIS (Bit 1)                                       */
46001 #define UART0_IES_CTSMRIS_Msk             (0x2UL)                   /*!< CTSMRIS (Bitfield-Mask: 0x01)                         */
46002 #define UART0_IES_TXCMPMRIS_Pos           (0UL)                     /*!< TXCMPMRIS (Bit 0)                                     */
46003 #define UART0_IES_TXCMPMRIS_Msk           (0x1UL)                   /*!< TXCMPMRIS (Bitfield-Mask: 0x01)                       */
46004 /* ==========================================================  MIS  ========================================================== */
46005 #define UART0_MIS_OEMIS_Pos               (10UL)                    /*!< OEMIS (Bit 10)                                        */
46006 #define UART0_MIS_OEMIS_Msk               (0x400UL)                 /*!< OEMIS (Bitfield-Mask: 0x01)                           */
46007 #define UART0_MIS_BEMIS_Pos               (9UL)                     /*!< BEMIS (Bit 9)                                         */
46008 #define UART0_MIS_BEMIS_Msk               (0x200UL)                 /*!< BEMIS (Bitfield-Mask: 0x01)                           */
46009 #define UART0_MIS_PEMIS_Pos               (8UL)                     /*!< PEMIS (Bit 8)                                         */
46010 #define UART0_MIS_PEMIS_Msk               (0x100UL)                 /*!< PEMIS (Bitfield-Mask: 0x01)                           */
46011 #define UART0_MIS_FEMIS_Pos               (7UL)                     /*!< FEMIS (Bit 7)                                         */
46012 #define UART0_MIS_FEMIS_Msk               (0x80UL)                  /*!< FEMIS (Bitfield-Mask: 0x01)                           */
46013 #define UART0_MIS_RTMIS_Pos               (6UL)                     /*!< RTMIS (Bit 6)                                         */
46014 #define UART0_MIS_RTMIS_Msk               (0x40UL)                  /*!< RTMIS (Bitfield-Mask: 0x01)                           */
46015 #define UART0_MIS_TXMIS_Pos               (5UL)                     /*!< TXMIS (Bit 5)                                         */
46016 #define UART0_MIS_TXMIS_Msk               (0x20UL)                  /*!< TXMIS (Bitfield-Mask: 0x01)                           */
46017 #define UART0_MIS_RXMIS_Pos               (4UL)                     /*!< RXMIS (Bit 4)                                         */
46018 #define UART0_MIS_RXMIS_Msk               (0x10UL)                  /*!< RXMIS (Bitfield-Mask: 0x01)                           */
46019 #define UART0_MIS_DSRMMIS_Pos             (3UL)                     /*!< DSRMMIS (Bit 3)                                       */
46020 #define UART0_MIS_DSRMMIS_Msk             (0x8UL)                   /*!< DSRMMIS (Bitfield-Mask: 0x01)                         */
46021 #define UART0_MIS_DCDMMIS_Pos             (2UL)                     /*!< DCDMMIS (Bit 2)                                       */
46022 #define UART0_MIS_DCDMMIS_Msk             (0x4UL)                   /*!< DCDMMIS (Bitfield-Mask: 0x01)                         */
46023 #define UART0_MIS_CTSMMIS_Pos             (1UL)                     /*!< CTSMMIS (Bit 1)                                       */
46024 #define UART0_MIS_CTSMMIS_Msk             (0x2UL)                   /*!< CTSMMIS (Bitfield-Mask: 0x01)                         */
46025 #define UART0_MIS_TXCMPMMIS_Pos           (0UL)                     /*!< TXCMPMMIS (Bit 0)                                     */
46026 #define UART0_MIS_TXCMPMMIS_Msk           (0x1UL)                   /*!< TXCMPMMIS (Bitfield-Mask: 0x01)                       */
46027 /* ==========================================================  IEC  ========================================================== */
46028 #define UART0_IEC_OEIC_Pos                (10UL)                    /*!< OEIC (Bit 10)                                         */
46029 #define UART0_IEC_OEIC_Msk                (0x400UL)                 /*!< OEIC (Bitfield-Mask: 0x01)                            */
46030 #define UART0_IEC_BEIC_Pos                (9UL)                     /*!< BEIC (Bit 9)                                          */
46031 #define UART0_IEC_BEIC_Msk                (0x200UL)                 /*!< BEIC (Bitfield-Mask: 0x01)                            */
46032 #define UART0_IEC_PEIC_Pos                (8UL)                     /*!< PEIC (Bit 8)                                          */
46033 #define UART0_IEC_PEIC_Msk                (0x100UL)                 /*!< PEIC (Bitfield-Mask: 0x01)                            */
46034 #define UART0_IEC_FEIC_Pos                (7UL)                     /*!< FEIC (Bit 7)                                          */
46035 #define UART0_IEC_FEIC_Msk                (0x80UL)                  /*!< FEIC (Bitfield-Mask: 0x01)                            */
46036 #define UART0_IEC_RTIC_Pos                (6UL)                     /*!< RTIC (Bit 6)                                          */
46037 #define UART0_IEC_RTIC_Msk                (0x40UL)                  /*!< RTIC (Bitfield-Mask: 0x01)                            */
46038 #define UART0_IEC_TXIC_Pos                (5UL)                     /*!< TXIC (Bit 5)                                          */
46039 #define UART0_IEC_TXIC_Msk                (0x20UL)                  /*!< TXIC (Bitfield-Mask: 0x01)                            */
46040 #define UART0_IEC_RXIC_Pos                (4UL)                     /*!< RXIC (Bit 4)                                          */
46041 #define UART0_IEC_RXIC_Msk                (0x10UL)                  /*!< RXIC (Bitfield-Mask: 0x01)                            */
46042 #define UART0_IEC_DSRMIC_Pos              (3UL)                     /*!< DSRMIC (Bit 3)                                        */
46043 #define UART0_IEC_DSRMIC_Msk              (0x8UL)                   /*!< DSRMIC (Bitfield-Mask: 0x01)                          */
46044 #define UART0_IEC_DCDMIC_Pos              (2UL)                     /*!< DCDMIC (Bit 2)                                        */
46045 #define UART0_IEC_DCDMIC_Msk              (0x4UL)                   /*!< DCDMIC (Bitfield-Mask: 0x01)                          */
46046 #define UART0_IEC_CTSMIC_Pos              (1UL)                     /*!< CTSMIC (Bit 1)                                        */
46047 #define UART0_IEC_CTSMIC_Msk              (0x2UL)                   /*!< CTSMIC (Bitfield-Mask: 0x01)                          */
46048 #define UART0_IEC_TXCMPMIC_Pos            (0UL)                     /*!< TXCMPMIC (Bit 0)                                      */
46049 #define UART0_IEC_TXCMPMIC_Msk            (0x1UL)                   /*!< TXCMPMIC (Bitfield-Mask: 0x01)                        */
46050 
46051 
46052 /* =========================================================================================================================== */
46053 /* ================                                          USBPHY                                           ================ */
46054 /* =========================================================================================================================== */
46055 
46056 /* =========================================================  REG00  ========================================================= */
46057 #define USBPHY_REG00_BF75_Pos             (5UL)                     /*!< BF75 (Bit 5)                                          */
46058 #define USBPHY_REG00_BF75_Msk             (0xe0UL)                  /*!< BF75 (Bitfield-Mask: 0x07)                            */
46059 #define USBPHY_REG00_BF43_Pos             (3UL)                     /*!< BF43 (Bit 3)                                          */
46060 #define USBPHY_REG00_BF43_Msk             (0x18UL)                  /*!< BF43 (Bitfield-Mask: 0x03)                            */
46061 #define USBPHY_REG00_BF20_Pos             (0UL)                     /*!< BF20 (Bit 0)                                          */
46062 #define USBPHY_REG00_BF20_Msk             (0x7UL)                   /*!< BF20 (Bitfield-Mask: 0x07)                            */
46063 /* =========================================================  REG04  ========================================================= */
46064 #define USBPHY_REG04_BF76_Pos             (6UL)                     /*!< BF76 (Bit 6)                                          */
46065 #define USBPHY_REG04_BF76_Msk             (0xc0UL)                  /*!< BF76 (Bitfield-Mask: 0x03)                            */
46066 #define USBPHY_REG04_BF55_Pos             (5UL)                     /*!< BF55 (Bit 5)                                          */
46067 #define USBPHY_REG04_BF55_Msk             (0x20UL)                  /*!< BF55 (Bitfield-Mask: 0x01)                            */
46068 #define USBPHY_REG04_BF43_Pos             (3UL)                     /*!< BF43 (Bit 3)                                          */
46069 #define USBPHY_REG04_BF43_Msk             (0x18UL)                  /*!< BF43 (Bitfield-Mask: 0x03)                            */
46070 #define USBPHY_REG04_BF20_Pos             (0UL)                     /*!< BF20 (Bit 0)                                          */
46071 #define USBPHY_REG04_BF20_Msk             (0x7UL)                   /*!< BF20 (Bitfield-Mask: 0x07)                            */
46072 /* =========================================================  REG08  ========================================================= */
46073 #define USBPHY_REG08_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
46074 #define USBPHY_REG08_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
46075 #define USBPHY_REG08_BF64_Pos             (4UL)                     /*!< BF64 (Bit 4)                                          */
46076 #define USBPHY_REG08_BF64_Msk             (0x70UL)                  /*!< BF64 (Bitfield-Mask: 0x07)                            */
46077 #define USBPHY_REG08_BF30_Pos             (0UL)                     /*!< BF30 (Bit 0)                                          */
46078 #define USBPHY_REG08_BF30_Msk             (0xfUL)                   /*!< BF30 (Bitfield-Mask: 0x0f)                            */
46079 /* =========================================================  REG0C  ========================================================= */
46080 #define USBPHY_REG0C_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
46081 #define USBPHY_REG0C_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
46082 #define USBPHY_REG0C_BF62_Pos             (2UL)                     /*!< BF62 (Bit 2)                                          */
46083 #define USBPHY_REG0C_BF62_Msk             (0x7cUL)                  /*!< BF62 (Bitfield-Mask: 0x1f)                            */
46084 #define USBPHY_REG0C_BF10_Pos             (0UL)                     /*!< BF10 (Bit 0)                                          */
46085 #define USBPHY_REG0C_BF10_Msk             (0x3UL)                   /*!< BF10 (Bitfield-Mask: 0x03)                            */
46086 /* =========================================================  REG10  ========================================================= */
46087 #define USBPHY_REG10_BF74_Pos             (4UL)                     /*!< BF74 (Bit 4)                                          */
46088 #define USBPHY_REG10_BF74_Msk             (0xf0UL)                  /*!< BF74 (Bitfield-Mask: 0x0f)                            */
46089 #define USBPHY_REG10_BF33_Pos             (3UL)                     /*!< BF33 (Bit 3)                                          */
46090 #define USBPHY_REG10_BF33_Msk             (0x8UL)                   /*!< BF33 (Bitfield-Mask: 0x01)                            */
46091 #define USBPHY_REG10_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
46092 #define USBPHY_REG10_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
46093 #define USBPHY_REG10_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
46094 #define USBPHY_REG10_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
46095 #define USBPHY_REG10_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46096 #define USBPHY_REG10_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46097 /* =========================================================  REG14  ========================================================= */
46098 #define USBPHY_REG14_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
46099 #define USBPHY_REG14_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
46100 #define USBPHY_REG14_BF66_Pos             (6UL)                     /*!< BF66 (Bit 6)                                          */
46101 #define USBPHY_REG14_BF66_Msk             (0x40UL)                  /*!< BF66 (Bitfield-Mask: 0x01)                            */
46102 #define USBPHY_REG14_BF55_Pos             (5UL)                     /*!< BF55 (Bit 5)                                          */
46103 #define USBPHY_REG14_BF55_Msk             (0x20UL)                  /*!< BF55 (Bitfield-Mask: 0x01)                            */
46104 #define USBPHY_REG14_BF42_Pos             (2UL)                     /*!< BF42 (Bit 2)                                          */
46105 #define USBPHY_REG14_BF42_Msk             (0x1cUL)                  /*!< BF42 (Bitfield-Mask: 0x07)                            */
46106 #define USBPHY_REG14_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
46107 #define USBPHY_REG14_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
46108 #define USBPHY_REG14_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46109 #define USBPHY_REG14_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46110 /* =========================================================  REG18  ========================================================= */
46111 #define USBPHY_REG18_BF73_Pos             (3UL)                     /*!< BF73 (Bit 3)                                          */
46112 #define USBPHY_REG18_BF73_Msk             (0xf8UL)                  /*!< BF73 (Bitfield-Mask: 0x1f)                            */
46113 #define USBPHY_REG18_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
46114 #define USBPHY_REG18_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
46115 #define USBPHY_REG18_BF10_Pos             (0UL)                     /*!< BF10 (Bit 0)                                          */
46116 #define USBPHY_REG18_BF10_Msk             (0x3UL)                   /*!< BF10 (Bitfield-Mask: 0x03)                            */
46117 /* =========================================================  REG1C  ========================================================= */
46118 #define USBPHY_REG1C_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
46119 #define USBPHY_REG1C_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
46120 #define USBPHY_REG1C_BF66_Pos             (6UL)                     /*!< BF66 (Bit 6)                                          */
46121 #define USBPHY_REG1C_BF66_Msk             (0x40UL)                  /*!< BF66 (Bitfield-Mask: 0x01)                            */
46122 #define USBPHY_REG1C_BF55_Pos             (5UL)                     /*!< BF55 (Bit 5)                                          */
46123 #define USBPHY_REG1C_BF55_Msk             (0x20UL)                  /*!< BF55 (Bitfield-Mask: 0x01)                            */
46124 #define USBPHY_REG1C_BF44_Pos             (4UL)                     /*!< BF44 (Bit 4)                                          */
46125 #define USBPHY_REG1C_BF44_Msk             (0x10UL)                  /*!< BF44 (Bitfield-Mask: 0x01)                            */
46126 #define USBPHY_REG1C_BF33_Pos             (3UL)                     /*!< BF33 (Bit 3)                                          */
46127 #define USBPHY_REG1C_BF33_Msk             (0x8UL)                   /*!< BF33 (Bitfield-Mask: 0x01)                            */
46128 #define USBPHY_REG1C_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
46129 #define USBPHY_REG1C_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
46130 #define USBPHY_REG1C_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
46131 #define USBPHY_REG1C_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
46132 #define USBPHY_REG1C_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46133 #define USBPHY_REG1C_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46134 /* =========================================================  REG20  ========================================================= */
46135 #define USBPHY_REG20_BF76_Pos             (6UL)                     /*!< BF76 (Bit 6)                                          */
46136 #define USBPHY_REG20_BF76_Msk             (0xc0UL)                  /*!< BF76 (Bitfield-Mask: 0x03)                            */
46137 #define USBPHY_REG20_BF54_Pos             (4UL)                     /*!< BF54 (Bit 4)                                          */
46138 #define USBPHY_REG20_BF54_Msk             (0x30UL)                  /*!< BF54 (Bitfield-Mask: 0x03)                            */
46139 #define USBPHY_REG20_BF33_Pos             (3UL)                     /*!< BF33 (Bit 3)                                          */
46140 #define USBPHY_REG20_BF33_Msk             (0x8UL)                   /*!< BF33 (Bitfield-Mask: 0x01)                            */
46141 #define USBPHY_REG20_BF20_Pos             (0UL)                     /*!< BF20 (Bit 0)                                          */
46142 #define USBPHY_REG20_BF20_Msk             (0x7UL)                   /*!< BF20 (Bitfield-Mask: 0x07)                            */
46143 /* =========================================================  REG24  ========================================================= */
46144 #define USBPHY_REG24_BF71_Pos             (1UL)                     /*!< BF71 (Bit 1)                                          */
46145 #define USBPHY_REG24_BF71_Msk             (0xfeUL)                  /*!< BF71 (Bitfield-Mask: 0x7f)                            */
46146 #define USBPHY_REG24_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46147 #define USBPHY_REG24_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46148 /* =========================================================  REG28  ========================================================= */
46149 #define USBPHY_REG28_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46150 #define USBPHY_REG28_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46151 /* =========================================================  REG2C  ========================================================= */
46152 #define USBPHY_REG2C_BF75_Pos             (5UL)                     /*!< BF75 (Bit 5)                                          */
46153 #define USBPHY_REG2C_BF75_Msk             (0xe0UL)                  /*!< BF75 (Bitfield-Mask: 0x07)                            */
46154 #define USBPHY_REG2C_BF44_Pos             (4UL)                     /*!< BF44 (Bit 4)                                          */
46155 #define USBPHY_REG2C_BF44_Msk             (0x10UL)                  /*!< BF44 (Bitfield-Mask: 0x01)                            */
46156 #define USBPHY_REG2C_BF33_Pos             (3UL)                     /*!< BF33 (Bit 3)                                          */
46157 #define USBPHY_REG2C_BF33_Msk             (0x8UL)                   /*!< BF33 (Bitfield-Mask: 0x01)                            */
46158 #define USBPHY_REG2C_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
46159 #define USBPHY_REG2C_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
46160 #define USBPHY_REG2C_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
46161 #define USBPHY_REG2C_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
46162 #define USBPHY_REG2C_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46163 #define USBPHY_REG2C_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46164 /* =========================================================  REG30  ========================================================= */
46165 #define USBPHY_REG30_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46166 #define USBPHY_REG30_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46167 /* =========================================================  REG34  ========================================================= */
46168 #define USBPHY_REG34_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46169 #define USBPHY_REG34_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46170 /* =========================================================  REG38  ========================================================= */
46171 #define USBPHY_REG38_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46172 #define USBPHY_REG38_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46173 /* =========================================================  REG3C  ========================================================= */
46174 #define USBPHY_REG3C_BF75_Pos             (5UL)                     /*!< BF75 (Bit 5)                                          */
46175 #define USBPHY_REG3C_BF75_Msk             (0xe0UL)                  /*!< BF75 (Bitfield-Mask: 0x07)                            */
46176 #define USBPHY_REG3C_BF42_Pos             (2UL)                     /*!< BF42 (Bit 2)                                          */
46177 #define USBPHY_REG3C_BF42_Msk             (0x1cUL)                  /*!< BF42 (Bitfield-Mask: 0x07)                            */
46178 #define USBPHY_REG3C_BF10_Pos             (0UL)                     /*!< BF10 (Bit 0)                                          */
46179 #define USBPHY_REG3C_BF10_Msk             (0x3UL)                   /*!< BF10 (Bitfield-Mask: 0x03)                            */
46180 /* =========================================================  REG40  ========================================================= */
46181 #define USBPHY_REG40_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
46182 #define USBPHY_REG40_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
46183 #define USBPHY_REG40_BF60_Pos             (0UL)                     /*!< BF60 (Bit 0)                                          */
46184 #define USBPHY_REG40_BF60_Msk             (0x7fUL)                  /*!< BF60 (Bitfield-Mask: 0x7f)                            */
46185 /* =========================================================  REG44  ========================================================= */
46186 #define USBPHY_REG44_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
46187 #define USBPHY_REG44_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
46188 #define USBPHY_REG44_BF65_Pos             (5UL)                     /*!< BF65 (Bit 5)                                          */
46189 #define USBPHY_REG44_BF65_Msk             (0x60UL)                  /*!< BF65 (Bitfield-Mask: 0x03)                            */
46190 #define USBPHY_REG44_BF42_Pos             (2UL)                     /*!< BF42 (Bit 2)                                          */
46191 #define USBPHY_REG44_BF42_Msk             (0x1cUL)                  /*!< BF42 (Bitfield-Mask: 0x07)                            */
46192 #define USBPHY_REG44_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
46193 #define USBPHY_REG44_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
46194 #define USBPHY_REG44_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46195 #define USBPHY_REG44_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46196 /* =========================================================  REG48  ========================================================= */
46197 #define USBPHY_REG48_BF71_Pos             (1UL)                     /*!< BF71 (Bit 1)                                          */
46198 #define USBPHY_REG48_BF71_Msk             (0xfeUL)                  /*!< BF71 (Bitfield-Mask: 0x7f)                            */
46199 #define USBPHY_REG48_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46200 #define USBPHY_REG48_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46201 /* =========================================================  REG4C  ========================================================= */
46202 #define USBPHY_REG4C_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46203 #define USBPHY_REG4C_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46204 /* =========================================================  REG50  ========================================================= */
46205 #define USBPHY_REG50_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46206 #define USBPHY_REG50_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46207 /* =========================================================  REG54  ========================================================= */
46208 #define USBPHY_REG54_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46209 #define USBPHY_REG54_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46210 /* =========================================================  REG58  ========================================================= */
46211 #define USBPHY_REG58_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46212 #define USBPHY_REG58_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46213 /* =========================================================  REG5C  ========================================================= */
46214 #define USBPHY_REG5C_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46215 #define USBPHY_REG5C_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46216 /* =========================================================  REG60  ========================================================= */
46217 #define USBPHY_REG60_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46218 #define USBPHY_REG60_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46219 /* =========================================================  REG64  ========================================================= */
46220 #define USBPHY_REG64_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46221 #define USBPHY_REG64_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46222 /* =========================================================  REG68  ========================================================= */
46223 #define USBPHY_REG68_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46224 #define USBPHY_REG68_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46225 /* =========================================================  REG6C  ========================================================= */
46226 #define USBPHY_REG6C_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46227 #define USBPHY_REG6C_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46228 /* =========================================================  REG70  ========================================================= */
46229 #define USBPHY_REG70_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46230 #define USBPHY_REG70_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46231 /* =========================================================  REG74  ========================================================= */
46232 #define USBPHY_REG74_BF74_Pos             (4UL)                     /*!< BF74 (Bit 4)                                          */
46233 #define USBPHY_REG74_BF74_Msk             (0xf0UL)                  /*!< BF74 (Bitfield-Mask: 0x0f)                            */
46234 #define USBPHY_REG74_BF31_Pos             (1UL)                     /*!< BF31 (Bit 1)                                          */
46235 #define USBPHY_REG74_BF31_Msk             (0xeUL)                   /*!< BF31 (Bitfield-Mask: 0x07)                            */
46236 #define USBPHY_REG74_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46237 #define USBPHY_REG74_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46238 /* =========================================================  REG78  ========================================================= */
46239 #define USBPHY_REG78_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46240 #define USBPHY_REG78_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46241 /* =========================================================  REG7C  ========================================================= */
46242 #define USBPHY_REG7C_BF77_Pos             (7UL)                     /*!< BF77 (Bit 7)                                          */
46243 #define USBPHY_REG7C_BF77_Msk             (0x80UL)                  /*!< BF77 (Bitfield-Mask: 0x01)                            */
46244 #define USBPHY_REG7C_BF66_Pos             (6UL)                     /*!< BF66 (Bit 6)                                          */
46245 #define USBPHY_REG7C_BF66_Msk             (0x40UL)                  /*!< BF66 (Bitfield-Mask: 0x01)                            */
46246 #define USBPHY_REG7C_BF55_Pos             (5UL)                     /*!< BF55 (Bit 5)                                          */
46247 #define USBPHY_REG7C_BF55_Msk             (0x20UL)                  /*!< BF55 (Bitfield-Mask: 0x01)                            */
46248 #define USBPHY_REG7C_BF40_Pos             (0UL)                     /*!< BF40 (Bit 0)                                          */
46249 #define USBPHY_REG7C_BF40_Msk             (0x1fUL)                  /*!< BF40 (Bitfield-Mask: 0x1f)                            */
46250 /* =========================================================  REG80  ========================================================= */
46251 #define USBPHY_REG80_BF73_Pos             (3UL)                     /*!< BF73 (Bit 3)                                          */
46252 #define USBPHY_REG80_BF73_Msk             (0xf8UL)                  /*!< BF73 (Bitfield-Mask: 0x1f)                            */
46253 #define USBPHY_REG80_BF22_Pos             (2UL)                     /*!< BF22 (Bit 2)                                          */
46254 #define USBPHY_REG80_BF22_Msk             (0x4UL)                   /*!< BF22 (Bitfield-Mask: 0x01)                            */
46255 #define USBPHY_REG80_BF11_Pos             (1UL)                     /*!< BF11 (Bit 1)                                          */
46256 #define USBPHY_REG80_BF11_Msk             (0x2UL)                   /*!< BF11 (Bitfield-Mask: 0x01)                            */
46257 #define USBPHY_REG80_BF00_Pos             (0UL)                     /*!< BF00 (Bit 0)                                          */
46258 #define USBPHY_REG80_BF00_Msk             (0x1UL)                   /*!< BF00 (Bitfield-Mask: 0x01)                            */
46259 /* =========================================================  REG84  ========================================================= */
46260 #define USBPHY_REG84_BF70_Pos             (0UL)                     /*!< BF70 (Bit 0)                                          */
46261 #define USBPHY_REG84_BF70_Msk             (0xffUL)                  /*!< BF70 (Bitfield-Mask: 0xff)                            */
46262 
46263 
46264 /* =========================================================================================================================== */
46265 /* ================                                            USB                                            ================ */
46266 /* =========================================================================================================================== */
46267 
46268 /* =========================================================  CFG0  ========================================================== */
46269 #define USB_CFG0_EP5InIntStat_Pos         (21UL)                    /*!< EP5InIntStat (Bit 21)                                 */
46270 #define USB_CFG0_EP5InIntStat_Msk         (0x200000UL)              /*!< EP5InIntStat (Bitfield-Mask: 0x01)                    */
46271 #define USB_CFG0_EP4InIntStat_Pos         (20UL)                    /*!< EP4InIntStat (Bit 20)                                 */
46272 #define USB_CFG0_EP4InIntStat_Msk         (0x100000UL)              /*!< EP4InIntStat (Bitfield-Mask: 0x01)                    */
46273 #define USB_CFG0_EP3InIntStat_Pos         (19UL)                    /*!< EP3InIntStat (Bit 19)                                 */
46274 #define USB_CFG0_EP3InIntStat_Msk         (0x80000UL)               /*!< EP3InIntStat (Bitfield-Mask: 0x01)                    */
46275 #define USB_CFG0_EP2InIntStat_Pos         (18UL)                    /*!< EP2InIntStat (Bit 18)                                 */
46276 #define USB_CFG0_EP2InIntStat_Msk         (0x40000UL)               /*!< EP2InIntStat (Bitfield-Mask: 0x01)                    */
46277 #define USB_CFG0_EP1InIntStat_Pos         (17UL)                    /*!< EP1InIntStat (Bit 17)                                 */
46278 #define USB_CFG0_EP1InIntStat_Msk         (0x20000UL)               /*!< EP1InIntStat (Bitfield-Mask: 0x01)                    */
46279 #define USB_CFG0_EP0InIntStat_Pos         (16UL)                    /*!< EP0InIntStat (Bit 16)                                 */
46280 #define USB_CFG0_EP0InIntStat_Msk         (0x10000UL)               /*!< EP0InIntStat (Bitfield-Mask: 0x01)                    */
46281 #define USB_CFG0_ISOUpdate_Pos            (15UL)                    /*!< ISOUpdate (Bit 15)                                    */
46282 #define USB_CFG0_ISOUpdate_Msk            (0x8000UL)                /*!< ISOUpdate (Bitfield-Mask: 0x01)                       */
46283 #define USB_CFG0_AMSPECIFIC_Pos           (14UL)                    /*!< AMSPECIFIC (Bit 14)                                   */
46284 #define USB_CFG0_AMSPECIFIC_Msk           (0x4000UL)                /*!< AMSPECIFIC (Bitfield-Mask: 0x01)                      */
46285 #define USB_CFG0_HSEnab_Pos               (13UL)                    /*!< HSEnab (Bit 13)                                       */
46286 #define USB_CFG0_HSEnab_Msk               (0x2000UL)                /*!< HSEnab (Bitfield-Mask: 0x01)                          */
46287 #define USB_CFG0_HSMode_Pos               (12UL)                    /*!< HSMode (Bit 12)                                       */
46288 #define USB_CFG0_HSMode_Msk               (0x1000UL)                /*!< HSMode (Bitfield-Mask: 0x01)                          */
46289 #define USB_CFG0_Reset_Pos                (11UL)                    /*!< Reset (Bit 11)                                        */
46290 #define USB_CFG0_Reset_Msk                (0x800UL)                 /*!< Reset (Bitfield-Mask: 0x01)                           */
46291 #define USB_CFG0_Resume_Pos               (10UL)                    /*!< Resume (Bit 10)                                       */
46292 #define USB_CFG0_Resume_Msk               (0x400UL)                 /*!< Resume (Bitfield-Mask: 0x01)                          */
46293 #define USB_CFG0_Suspen_Pos               (9UL)                     /*!< Suspen (Bit 9)                                        */
46294 #define USB_CFG0_Suspen_Msk               (0x200UL)                 /*!< Suspen (Bitfield-Mask: 0x01)                          */
46295 #define USB_CFG0_Enabl_Pos                (8UL)                     /*!< Enabl (Bit 8)                                         */
46296 #define USB_CFG0_Enabl_Msk                (0x100UL)                 /*!< Enabl (Bitfield-Mask: 0x01)                           */
46297 #define USB_CFG0_Update_Pos               (7UL)                     /*!< Update (Bit 7)                                        */
46298 #define USB_CFG0_Update_Msk               (0x80UL)                  /*!< Update (Bitfield-Mask: 0x01)                          */
46299 #define USB_CFG0_FuncAddr_Pos             (0UL)                     /*!< FuncAddr (Bit 0)                                      */
46300 #define USB_CFG0_FuncAddr_Msk             (0x7fUL)                  /*!< FuncAddr (Bitfield-Mask: 0x7f)                        */
46301 /* =========================================================  CFG1  ========================================================== */
46302 #define USB_CFG1_EP5InIntEn_Pos           (21UL)                    /*!< EP5InIntEn (Bit 21)                                   */
46303 #define USB_CFG1_EP5InIntEn_Msk           (0x200000UL)              /*!< EP5InIntEn (Bitfield-Mask: 0x01)                      */
46304 #define USB_CFG1_EP4InIntEn_Pos           (20UL)                    /*!< EP4InIntEn (Bit 20)                                   */
46305 #define USB_CFG1_EP4InIntEn_Msk           (0x100000UL)              /*!< EP4InIntEn (Bitfield-Mask: 0x01)                      */
46306 #define USB_CFG1_EP3InIntEn_Pos           (19UL)                    /*!< EP3InIntEn (Bit 19)                                   */
46307 #define USB_CFG1_EP3InIntEn_Msk           (0x80000UL)               /*!< EP3InIntEn (Bitfield-Mask: 0x01)                      */
46308 #define USB_CFG1_EP2InIntEn_Pos           (18UL)                    /*!< EP2InIntEn (Bit 18)                                   */
46309 #define USB_CFG1_EP2InIntEn_Msk           (0x40000UL)               /*!< EP2InIntEn (Bitfield-Mask: 0x01)                      */
46310 #define USB_CFG1_EP1InIntEn_Pos           (17UL)                    /*!< EP1InIntEn (Bit 17)                                   */
46311 #define USB_CFG1_EP1InIntEn_Msk           (0x20000UL)               /*!< EP1InIntEn (Bitfield-Mask: 0x01)                      */
46312 #define USB_CFG1_EP0InIntEn_Pos           (16UL)                    /*!< EP0InIntEn (Bit 16)                                   */
46313 #define USB_CFG1_EP0InIntEn_Msk           (0x10000UL)               /*!< EP0InIntEn (Bitfield-Mask: 0x01)                      */
46314 #define USB_CFG1_EP5OutIntStat_Pos        (5UL)                     /*!< EP5OutIntStat (Bit 5)                                 */
46315 #define USB_CFG1_EP5OutIntStat_Msk        (0x20UL)                  /*!< EP5OutIntStat (Bitfield-Mask: 0x01)                   */
46316 #define USB_CFG1_EP4OutIntStat_Pos        (4UL)                     /*!< EP4OutIntStat (Bit 4)                                 */
46317 #define USB_CFG1_EP4OutIntStat_Msk        (0x10UL)                  /*!< EP4OutIntStat (Bitfield-Mask: 0x01)                   */
46318 #define USB_CFG1_EP3OutIntStat_Pos        (3UL)                     /*!< EP3OutIntStat (Bit 3)                                 */
46319 #define USB_CFG1_EP3OutIntStat_Msk        (0x8UL)                   /*!< EP3OutIntStat (Bitfield-Mask: 0x01)                   */
46320 #define USB_CFG1_EP2OutIntStat_Pos        (2UL)                     /*!< EP2OutIntStat (Bit 2)                                 */
46321 #define USB_CFG1_EP2OutIntStat_Msk        (0x4UL)                   /*!< EP2OutIntStat (Bitfield-Mask: 0x01)                   */
46322 #define USB_CFG1_EP1OutIntStat_Pos        (1UL)                     /*!< EP1OutIntStat (Bit 1)                                 */
46323 #define USB_CFG1_EP1OutIntStat_Msk        (0x2UL)                   /*!< EP1OutIntStat (Bitfield-Mask: 0x01)                   */
46324 #define USB_CFG1_EP0OutIntStat_Pos        (0UL)                     /*!< EP0OutIntStat (Bit 0)                                 */
46325 #define USB_CFG1_EP0OutIntStat_Msk        (0x1UL)                   /*!< EP0OutIntStat (Bitfield-Mask: 0x01)                   */
46326 /* =========================================================  CFG2  ========================================================== */
46327 #define USB_CFG2_SOFE_Pos                 (27UL)                    /*!< SOFE (Bit 27)                                         */
46328 #define USB_CFG2_SOFE_Msk                 (0x8000000UL)             /*!< SOFE (Bitfield-Mask: 0x01)                            */
46329 #define USB_CFG2_ResetE_Pos               (26UL)                    /*!< ResetE (Bit 26)                                       */
46330 #define USB_CFG2_ResetE_Msk               (0x4000000UL)             /*!< ResetE (Bitfield-Mask: 0x01)                          */
46331 #define USB_CFG2_ResumeE_Pos              (25UL)                    /*!< ResumeE (Bit 25)                                      */
46332 #define USB_CFG2_ResumeE_Msk              (0x2000000UL)             /*!< ResumeE (Bitfield-Mask: 0x01)                         */
46333 #define USB_CFG2_SuspendE_Pos             (24UL)                    /*!< SuspendE (Bit 24)                                     */
46334 #define USB_CFG2_SuspendE_Msk             (0x1000000UL)             /*!< SuspendE (Bitfield-Mask: 0x01)                        */
46335 #define USB_CFG2_SOF_Pos                  (19UL)                    /*!< SOF (Bit 19)                                          */
46336 #define USB_CFG2_SOF_Msk                  (0x80000UL)               /*!< SOF (Bitfield-Mask: 0x01)                             */
46337 #define USB_CFG2_Reset_Pos                (18UL)                    /*!< Reset (Bit 18)                                        */
46338 #define USB_CFG2_Reset_Msk                (0x40000UL)               /*!< Reset (Bitfield-Mask: 0x01)                           */
46339 #define USB_CFG2_Resume_Pos               (17UL)                    /*!< Resume (Bit 17)                                       */
46340 #define USB_CFG2_Resume_Msk               (0x20000UL)               /*!< Resume (Bitfield-Mask: 0x01)                          */
46341 #define USB_CFG2_Suspend_Pos              (16UL)                    /*!< Suspend (Bit 16)                                      */
46342 #define USB_CFG2_Suspend_Msk              (0x10000UL)               /*!< Suspend (Bitfield-Mask: 0x01)                         */
46343 #define USB_CFG2_EP5OutIntEn_Pos          (5UL)                     /*!< EP5OutIntEn (Bit 5)                                   */
46344 #define USB_CFG2_EP5OutIntEn_Msk          (0x20UL)                  /*!< EP5OutIntEn (Bitfield-Mask: 0x01)                     */
46345 #define USB_CFG2_EP4OutIntEn_Pos          (4UL)                     /*!< EP4OutIntEn (Bit 4)                                   */
46346 #define USB_CFG2_EP4OutIntEn_Msk          (0x10UL)                  /*!< EP4OutIntEn (Bitfield-Mask: 0x01)                     */
46347 #define USB_CFG2_EP3OutIntEn_Pos          (3UL)                     /*!< EP3OutIntEn (Bit 3)                                   */
46348 #define USB_CFG2_EP3OutIntEn_Msk          (0x8UL)                   /*!< EP3OutIntEn (Bitfield-Mask: 0x01)                     */
46349 #define USB_CFG2_EP2OutIntEn_Pos          (2UL)                     /*!< EP2OutIntEn (Bit 2)                                   */
46350 #define USB_CFG2_EP2OutIntEn_Msk          (0x4UL)                   /*!< EP2OutIntEn (Bitfield-Mask: 0x01)                     */
46351 #define USB_CFG2_EP1OutIntEn_Pos          (1UL)                     /*!< EP1OutIntEn (Bit 1)                                   */
46352 #define USB_CFG2_EP1OutIntEn_Msk          (0x2UL)                   /*!< EP1OutIntEn (Bitfield-Mask: 0x01)                     */
46353 #define USB_CFG2_EP0OutIntEn_Pos          (0UL)                     /*!< EP0OutIntEn (Bit 0)                                   */
46354 #define USB_CFG2_EP0OutIntEn_Msk          (0x1UL)                   /*!< EP0OutIntEn (Bitfield-Mask: 0x01)                     */
46355 /* =========================================================  CFG3  ========================================================== */
46356 #define USB_CFG3_ForceFS_Pos              (29UL)                    /*!< ForceFS (Bit 29)                                      */
46357 #define USB_CFG3_ForceFS_Msk              (0x20000000UL)            /*!< ForceFS (Bitfield-Mask: 0x01)                         */
46358 #define USB_CFG3_ForceHS_Pos              (28UL)                    /*!< ForceHS (Bit 28)                                      */
46359 #define USB_CFG3_ForceHS_Msk              (0x10000000UL)            /*!< ForceHS (Bitfield-Mask: 0x01)                         */
46360 #define USB_CFG3_TestPacket_Pos           (27UL)                    /*!< TestPacket (Bit 27)                                   */
46361 #define USB_CFG3_TestPacket_Msk           (0x8000000UL)             /*!< TestPacket (Bitfield-Mask: 0x01)                      */
46362 #define USB_CFG3_TestK_Pos                (26UL)                    /*!< TestK (Bit 26)                                        */
46363 #define USB_CFG3_TestK_Msk                (0x4000000UL)             /*!< TestK (Bitfield-Mask: 0x01)                           */
46364 #define USB_CFG3_TestJ_Pos                (25UL)                    /*!< TestJ (Bit 25)                                        */
46365 #define USB_CFG3_TestJ_Msk                (0x2000000UL)             /*!< TestJ (Bitfield-Mask: 0x01)                           */
46366 #define USB_CFG3_TestSE0NAK_Pos           (24UL)                    /*!< TestSE0NAK (Bit 24)                                   */
46367 #define USB_CFG3_TestSE0NAK_Msk           (0x1000000UL)             /*!< TestSE0NAK (Bitfield-Mask: 0x01)                      */
46368 #define USB_CFG3_ENDPOINT_Pos             (16UL)                    /*!< ENDPOINT (Bit 16)                                     */
46369 #define USB_CFG3_ENDPOINT_Msk             (0xf0000UL)               /*!< ENDPOINT (Bitfield-Mask: 0x0f)                        */
46370 #define USB_CFG3_FRMNUM_Pos               (0UL)                     /*!< FRMNUM (Bit 0)                                        */
46371 #define USB_CFG3_FRMNUM_Msk               (0xffffUL)                /*!< FRMNUM (Bitfield-Mask: 0xffff)                        */
46372 /* =========================================================  IDX0  ========================================================== */
46373 #define USB_IDX0_AutoSet_Pos              (31UL)                    /*!< AutoSet (Bit 31)                                      */
46374 #define USB_IDX0_AutoSet_Msk              (0x80000000UL)            /*!< AutoSet (Bitfield-Mask: 0x01)                         */
46375 #define USB_IDX0_ISO_Pos                  (30UL)                    /*!< ISO (Bit 30)                                          */
46376 #define USB_IDX0_ISO_Msk                  (0x40000000UL)            /*!< ISO (Bitfield-Mask: 0x01)                             */
46377 #define USB_IDX0_Mode_Pos                 (29UL)                    /*!< Mode (Bit 29)                                         */
46378 #define USB_IDX0_Mode_Msk                 (0x20000000UL)            /*!< Mode (Bitfield-Mask: 0x01)                            */
46379 #define USB_IDX0_FrcDataTog_Pos           (27UL)                    /*!< FrcDataTog (Bit 27)                                   */
46380 #define USB_IDX0_FrcDataTog_Msk           (0x8000000UL)             /*!< FrcDataTog (Bitfield-Mask: 0x01)                      */
46381 #define USB_IDX0_DPktBufDis_Pos           (25UL)                    /*!< DPktBufDis (Bit 25)                                   */
46382 #define USB_IDX0_DPktBufDis_Msk           (0x2000000UL)             /*!< DPktBufDis (Bitfield-Mask: 0x01)                      */
46383 #define USB_IDX0_D0_Pos                   (24UL)                    /*!< D0 (Bit 24)                                           */
46384 #define USB_IDX0_D0_Msk                   (0x1000000UL)             /*!< D0 (Bitfield-Mask: 0x01)                              */
46385 #define USB_IDX0_IncompTxServiceSetupEnd_Pos (23UL)                 /*!< IncompTxServiceSetupEnd (Bit 23)                      */
46386 #define USB_IDX0_IncompTxServiceSetupEnd_Msk (0x800000UL)           /*!< IncompTxServiceSetupEnd (Bitfield-Mask: 0x01)         */
46387 #define USB_IDX0_ClrDataTogServicedOutPktRdy_Pos (22UL)             /*!< ClrDataTogServicedOutPktRdy (Bit 22)                  */
46388 #define USB_IDX0_ClrDataTogServicedOutPktRdy_Msk (0x400000UL)       /*!< ClrDataTogServicedOutPktRdy (Bitfield-Mask: 0x01)     */
46389 #define USB_IDX0_SentStallSendStall_Pos   (21UL)                    /*!< SentStallSendStall (Bit 21)                           */
46390 #define USB_IDX0_SentStallSendStall_Msk   (0x200000UL)              /*!< SentStallSendStall (Bitfield-Mask: 0x01)              */
46391 #define USB_IDX0_SendStallSetupEnd_Pos    (20UL)                    /*!< SendStallSetupEnd (Bit 20)                            */
46392 #define USB_IDX0_SendStallSetupEnd_Msk    (0x100000UL)              /*!< SendStallSetupEnd (Bitfield-Mask: 0x01)               */
46393 #define USB_IDX0_FlushFIFODataEnd_Pos     (19UL)                    /*!< FlushFIFODataEnd (Bit 19)                             */
46394 #define USB_IDX0_FlushFIFODataEnd_Msk     (0x80000UL)               /*!< FlushFIFODataEnd (Bitfield-Mask: 0x01)                */
46395 #define USB_IDX0_UnderRunSentStall_Pos    (18UL)                    /*!< UnderRunSentStall (Bit 18)                            */
46396 #define USB_IDX0_UnderRunSentStall_Msk    (0x40000UL)               /*!< UnderRunSentStall (Bitfield-Mask: 0x01)               */
46397 #define USB_IDX0_FIFONotEmptyInPktRdy_Pos (17UL)                    /*!< FIFONotEmptyInPktRdy (Bit 17)                         */
46398 #define USB_IDX0_FIFONotEmptyInPktRdy_Msk (0x20000UL)               /*!< FIFONotEmptyInPktRdy (Bitfield-Mask: 0x01)            */
46399 #define USB_IDX0_InPktRdyOutPktRdy_Pos    (16UL)                    /*!< InPktRdyOutPktRdy (Bit 16)                            */
46400 #define USB_IDX0_InPktRdyOutPktRdy_Msk    (0x10000UL)               /*!< InPktRdyOutPktRdy (Bitfield-Mask: 0x01)               */
46401 #define USB_IDX0_PKTSPLITOPTION_Pos       (11UL)                    /*!< PKTSPLITOPTION (Bit 11)                               */
46402 #define USB_IDX0_PKTSPLITOPTION_Msk       (0xf800UL)                /*!< PKTSPLITOPTION (Bitfield-Mask: 0x1f)                  */
46403 #define USB_IDX0_MAXPAYLOAD_Pos           (0UL)                     /*!< MAXPAYLOAD (Bit 0)                                    */
46404 #define USB_IDX0_MAXPAYLOAD_Msk           (0x7ffUL)                 /*!< MAXPAYLOAD (Bitfield-Mask: 0x7ff)                     */
46405 /* =========================================================  IDX1  ========================================================== */
46406 #define USB_IDX1_AutoClear_Pos            (31UL)                    /*!< AutoClear (Bit 31)                                    */
46407 #define USB_IDX1_AutoClear_Msk            (0x80000000UL)            /*!< AutoClear (Bitfield-Mask: 0x01)                       */
46408 #define USB_IDX1_ISO_Pos                  (30UL)                    /*!< ISO (Bit 30)                                          */
46409 #define USB_IDX1_ISO_Msk                  (0x40000000UL)            /*!< ISO (Bitfield-Mask: 0x01)                             */
46410 #define USB_IDX1_DisNye_Pos               (28UL)                    /*!< DisNye (Bit 28)                                       */
46411 #define USB_IDX1_DisNye_Msk               (0x10000000UL)            /*!< DisNye (Bitfield-Mask: 0x01)                          */
46412 #define USB_IDX1_DPktBufDis_Pos           (25UL)                    /*!< DPktBufDis (Bit 25)                                   */
46413 #define USB_IDX1_DPktBufDis_Msk           (0x2000000UL)             /*!< DPktBufDis (Bitfield-Mask: 0x01)                      */
46414 #define USB_IDX1_IncompRx_Pos             (24UL)                    /*!< IncompRx (Bit 24)                                     */
46415 #define USB_IDX1_IncompRx_Msk             (0x1000000UL)             /*!< IncompRx (Bitfield-Mask: 0x01)                        */
46416 #define USB_IDX1_ClrDataTog_Pos           (23UL)                    /*!< ClrDataTog (Bit 23)                                   */
46417 #define USB_IDX1_ClrDataTog_Msk           (0x800000UL)              /*!< ClrDataTog (Bitfield-Mask: 0x01)                      */
46418 #define USB_IDX1_SentStall_Pos            (22UL)                    /*!< SentStall (Bit 22)                                    */
46419 #define USB_IDX1_SentStall_Msk            (0x400000UL)              /*!< SentStall (Bitfield-Mask: 0x01)                       */
46420 #define USB_IDX1_SendStall_Pos            (21UL)                    /*!< SendStall (Bit 21)                                    */
46421 #define USB_IDX1_SendStall_Msk            (0x200000UL)              /*!< SendStall (Bitfield-Mask: 0x01)                       */
46422 #define USB_IDX1_FlushFIFO_Pos            (20UL)                    /*!< FlushFIFO (Bit 20)                                    */
46423 #define USB_IDX1_FlushFIFO_Msk            (0x100000UL)              /*!< FlushFIFO (Bitfield-Mask: 0x01)                       */
46424 #define USB_IDX1_DataError_Pos            (19UL)                    /*!< DataError (Bit 19)                                    */
46425 #define USB_IDX1_DataError_Msk            (0x80000UL)               /*!< DataError (Bitfield-Mask: 0x01)                       */
46426 #define USB_IDX1_OverRun_Pos              (18UL)                    /*!< OverRun (Bit 18)                                      */
46427 #define USB_IDX1_OverRun_Msk              (0x40000UL)               /*!< OverRun (Bitfield-Mask: 0x01)                         */
46428 #define USB_IDX1_FIFOFull_Pos             (17UL)                    /*!< FIFOFull (Bit 17)                                     */
46429 #define USB_IDX1_FIFOFull_Msk             (0x20000UL)               /*!< FIFOFull (Bitfield-Mask: 0x01)                        */
46430 #define USB_IDX1_OutPktRdy_Pos            (16UL)                    /*!< OutPktRdy (Bit 16)                                    */
46431 #define USB_IDX1_OutPktRdy_Msk            (0x10000UL)               /*!< OutPktRdy (Bitfield-Mask: 0x01)                       */
46432 #define USB_IDX1_PKTSPLITOPTION_Pos       (11UL)                    /*!< PKTSPLITOPTION (Bit 11)                               */
46433 #define USB_IDX1_PKTSPLITOPTION_Msk       (0xf800UL)                /*!< PKTSPLITOPTION (Bitfield-Mask: 0x1f)                  */
46434 #define USB_IDX1_MAXPAYLOAD_Pos           (0UL)                     /*!< MAXPAYLOAD (Bit 0)                                    */
46435 #define USB_IDX1_MAXPAYLOAD_Msk           (0x7ffUL)                 /*!< MAXPAYLOAD (Bitfield-Mask: 0x7ff)                     */
46436 /* =========================================================  IDX2  ========================================================== */
46437 #define USB_IDX2_OUTFIFOSZ_Pos            (24UL)                    /*!< OUTFIFOSZ (Bit 24)                                    */
46438 #define USB_IDX2_OUTFIFOSZ_Msk            (0x1f000000UL)            /*!< OUTFIFOSZ (Bitfield-Mask: 0x1f)                       */
46439 #define USB_IDX2_INFIFOSZ_Pos             (16UL)                    /*!< INFIFOSZ (Bit 16)                                     */
46440 #define USB_IDX2_INFIFOSZ_Msk             (0x1f0000UL)              /*!< INFIFOSZ (Bitfield-Mask: 0x1f)                        */
46441 #define USB_IDX2_ENDPTOUTCOUNT_Pos        (0UL)                     /*!< ENDPTOUTCOUNT (Bit 0)                                 */
46442 #define USB_IDX2_ENDPTOUTCOUNT_Msk        (0x1fffUL)                /*!< ENDPTOUTCOUNT (Bitfield-Mask: 0x1fff)                 */
46443 /* ========================================================  FIFOADD  ======================================================== */
46444 #define USB_FIFOADD_OUTFIFOADD_Pos        (16UL)                    /*!< OUTFIFOADD (Bit 16)                                   */
46445 #define USB_FIFOADD_OUTFIFOADD_Msk        (0x1fff0000UL)            /*!< OUTFIFOADD (Bitfield-Mask: 0x1fff)                    */
46446 #define USB_FIFOADD_INFIFOADD_Pos         (0UL)                     /*!< INFIFOADD (Bit 0)                                     */
46447 #define USB_FIFOADD_INFIFOADD_Msk         (0x1fffUL)                /*!< INFIFOADD (Bitfield-Mask: 0x1fff)                     */
46448 /* =========================================================  FIFO0  ========================================================= */
46449 #define USB_FIFO0_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
46450 #define USB_FIFO0_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
46451 /* =========================================================  FIFO1  ========================================================= */
46452 #define USB_FIFO1_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
46453 #define USB_FIFO1_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
46454 /* =========================================================  FIFO2  ========================================================= */
46455 #define USB_FIFO2_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
46456 #define USB_FIFO2_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
46457 /* =========================================================  FIFO3  ========================================================= */
46458 #define USB_FIFO3_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
46459 #define USB_FIFO3_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
46460 /* =========================================================  FIFO4  ========================================================= */
46461 #define USB_FIFO4_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
46462 #define USB_FIFO4_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
46463 /* =========================================================  FIFO5  ========================================================= */
46464 #define USB_FIFO5_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
46465 #define USB_FIFO5_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
46466 /* ========================================================  HWVERS  ========================================================= */
46467 #define USB_HWVERS_RC_Pos                 (15UL)                    /*!< RC (Bit 15)                                           */
46468 #define USB_HWVERS_RC_Msk                 (0x8000UL)                /*!< RC (Bitfield-Mask: 0x01)                              */
46469 #define USB_HWVERS_xx_Pos                 (10UL)                    /*!< xx (Bit 10)                                           */
46470 #define USB_HWVERS_xx_Msk                 (0x7c00UL)                /*!< xx (Bitfield-Mask: 0x1f)                              */
46471 #define USB_HWVERS_yyy_Pos                (0UL)                     /*!< yyy (Bit 0)                                           */
46472 #define USB_HWVERS_yyy_Msk                (0x3ffUL)                 /*!< yyy (Bitfield-Mask: 0x3ff)                            */
46473 /* =========================================================  INFO  ========================================================== */
46474 #define USB_INFO_RSTXS_Pos                (17UL)                    /*!< RSTXS (Bit 17)                                        */
46475 #define USB_INFO_RSTXS_Msk                (0x20000UL)               /*!< RSTXS (Bitfield-Mask: 0x01)                           */
46476 #define USB_INFO_RSTS_Pos                 (16UL)                    /*!< RSTS (Bit 16)                                         */
46477 #define USB_INFO_RSTS_Msk                 (0x10000UL)               /*!< RSTS (Bitfield-Mask: 0x01)                            */
46478 #define USB_INFO_RamBits_Pos              (8UL)                     /*!< RamBits (Bit 8)                                       */
46479 #define USB_INFO_RamBits_Msk              (0xf00UL)                 /*!< RamBits (Bitfield-Mask: 0x0f)                         */
46480 #define USB_INFO_OutEndPoints_Pos         (4UL)                     /*!< OutEndPoints (Bit 4)                                  */
46481 #define USB_INFO_OutEndPoints_Msk         (0xf0UL)                  /*!< OutEndPoints (Bitfield-Mask: 0x0f)                    */
46482 #define USB_INFO_InEndPoints_Pos          (0UL)                     /*!< InEndPoints (Bit 0)                                   */
46483 #define USB_INFO_InEndPoints_Msk          (0xfUL)                   /*!< InEndPoints (Bitfield-Mask: 0x0f)                     */
46484 /* =======================================================  TIMEOUT1  ======================================================== */
46485 #define USB_TIMEOUT1_CTUCH_Pos            (0UL)                     /*!< CTUCH (Bit 0)                                         */
46486 #define USB_TIMEOUT1_CTUCH_Msk            (0xffffUL)                /*!< CTUCH (Bitfield-Mask: 0xffff)                         */
46487 /* =======================================================  TIMEOUT2  ======================================================== */
46488 #define USB_TIMEOUT2_CTHRSTN_Pos          (0UL)                     /*!< CTHRSTN (Bit 0)                                       */
46489 #define USB_TIMEOUT2_CTHRSTN_Msk          (0xffffUL)                /*!< CTHRSTN (Bitfield-Mask: 0xffff)                       */
46490 /* ========================================================  CLKCTRL  ======================================================== */
46491 #define USB_CLKCTRL_PHYREFCLKSEL_Pos      (24UL)                    /*!< PHYREFCLKSEL (Bit 24)                                 */
46492 #define USB_CLKCTRL_PHYREFCLKSEL_Msk      (0x3000000UL)             /*!< PHYREFCLKSEL (Bitfield-Mask: 0x03)                    */
46493 #define USB_CLKCTRL_PHYAPBLCLKDIS_Pos     (16UL)                    /*!< PHYAPBLCLKDIS (Bit 16)                                */
46494 #define USB_CLKCTRL_PHYAPBLCLKDIS_Msk     (0x10000UL)               /*!< PHYAPBLCLKDIS (Bitfield-Mask: 0x01)                   */
46495 #define USB_CLKCTRL_CTRLAPBCLKDIS_Pos     (8UL)                     /*!< CTRLAPBCLKDIS (Bit 8)                                 */
46496 #define USB_CLKCTRL_CTRLAPBCLKDIS_Msk     (0x100UL)                 /*!< CTRLAPBCLKDIS (Bitfield-Mask: 0x01)                   */
46497 #define USB_CLKCTRL_PHYREFCLKDIS_Pos      (0UL)                     /*!< PHYREFCLKDIS (Bit 0)                                  */
46498 #define USB_CLKCTRL_PHYREFCLKDIS_Msk      (0x1UL)                   /*!< PHYREFCLKDIS (Bitfield-Mask: 0x01)                    */
46499 /* =======================================================  SRAMCTRL  ======================================================== */
46500 #define USB_SRAMCTRL_STOV_Pos             (14UL)                    /*!< STOV (Bit 14)                                         */
46501 #define USB_SRAMCTRL_STOV_Msk             (0x4000UL)                /*!< STOV (Bitfield-Mask: 0x01)                            */
46502 #define USB_SRAMCTRL_WABL_Pos             (13UL)                    /*!< WABL (Bit 13)                                         */
46503 #define USB_SRAMCTRL_WABL_Msk             (0x2000UL)                /*!< WABL (Bitfield-Mask: 0x01)                            */
46504 #define USB_SRAMCTRL_WABLM_Pos            (10UL)                    /*!< WABLM (Bit 10)                                        */
46505 #define USB_SRAMCTRL_WABLM_Msk            (0x1c00UL)                /*!< WABLM (Bitfield-Mask: 0x07)                           */
46506 #define USB_SRAMCTRL_RAWL_Pos             (9UL)                     /*!< RAWL (Bit 9)                                          */
46507 #define USB_SRAMCTRL_RAWL_Msk             (0x200UL)                 /*!< RAWL (Bitfield-Mask: 0x01)                            */
46508 #define USB_SRAMCTRL_RAWLM_Pos            (7UL)                     /*!< RAWLM (Bit 7)                                         */
46509 #define USB_SRAMCTRL_RAWLM_Msk            (0x180UL)                 /*!< RAWLM (Bitfield-Mask: 0x03)                           */
46510 #define USB_SRAMCTRL_EMAW_Pos             (5UL)                     /*!< EMAW (Bit 5)                                          */
46511 #define USB_SRAMCTRL_EMAW_Msk             (0x60UL)                  /*!< EMAW (Bitfield-Mask: 0x03)                            */
46512 #define USB_SRAMCTRL_EMAS_Pos             (4UL)                     /*!< EMAS (Bit 4)                                          */
46513 #define USB_SRAMCTRL_EMAS_Msk             (0x10UL)                  /*!< EMAS (Bitfield-Mask: 0x01)                            */
46514 #define USB_SRAMCTRL_EMA_Pos              (1UL)                     /*!< EMA (Bit 1)                                           */
46515 #define USB_SRAMCTRL_EMA_Msk              (0xeUL)                   /*!< EMA (Bitfield-Mask: 0x07)                             */
46516 #define USB_SRAMCTRL_RET1N_Pos            (0UL)                     /*!< RET1N (Bit 0)                                         */
46517 #define USB_SRAMCTRL_RET1N_Msk            (0x1UL)                   /*!< RET1N (Bitfield-Mask: 0x01)                           */
46518 /* ===================================================  UTMISTICKYSTATUS  ==================================================== */
46519 #define USB_UTMISTICKYSTATUS_obsportstciky_Pos (0UL)                /*!< obsportstciky (Bit 0)                                 */
46520 #define USB_UTMISTICKYSTATUS_obsportstciky_Msk (0x3UL)              /*!< obsportstciky (Bitfield-Mask: 0x03)                   */
46521 /* ======================================================  OBSCLRSTAT  ======================================================= */
46522 #define USB_OBSCLRSTAT_CLRSTAT_Pos        (0UL)                     /*!< CLRSTAT (Bit 0)                                       */
46523 #define USB_OBSCLRSTAT_CLRSTAT_Msk        (0x1UL)                   /*!< CLRSTAT (Bitfield-Mask: 0x01)                         */
46524 /* =====================================================  DPDMPULLDOWN  ====================================================== */
46525 #define USB_DPDMPULLDOWN_DPPULLDOWN_Pos   (1UL)                     /*!< DPPULLDOWN (Bit 1)                                    */
46526 #define USB_DPDMPULLDOWN_DPPULLDOWN_Msk   (0x2UL)                   /*!< DPPULLDOWN (Bitfield-Mask: 0x01)                      */
46527 #define USB_DPDMPULLDOWN_DMPULLDOWN_Pos   (0UL)                     /*!< DMPULLDOWN (Bit 0)                                    */
46528 #define USB_DPDMPULLDOWN_DMPULLDOWN_Msk   (0x1UL)                   /*!< DMPULLDOWN (Bitfield-Mask: 0x01)                      */
46529 /* ======================================================  BCDETSTATUS  ====================================================== */
46530 #define USB_BCDETSTATUS_DMCOMPOUT_Pos     (5UL)                     /*!< DMCOMPOUT (Bit 5)                                     */
46531 #define USB_BCDETSTATUS_DMCOMPOUT_Msk     (0x20UL)                  /*!< DMCOMPOUT (Bitfield-Mask: 0x01)                       */
46532 #define USB_BCDETSTATUS_DPCOMPOUT_Pos     (4UL)                     /*!< DPCOMPOUT (Bit 4)                                     */
46533 #define USB_BCDETSTATUS_DPCOMPOUT_Msk     (0x10UL)                  /*!< DPCOMPOUT (Bitfield-Mask: 0x01)                       */
46534 #define USB_BCDETSTATUS_DCPDETECTED_Pos   (2UL)                     /*!< DCPDETECTED (Bit 2)                                   */
46535 #define USB_BCDETSTATUS_DCPDETECTED_Msk   (0x4UL)                   /*!< DCPDETECTED (Bitfield-Mask: 0x01)                     */
46536 #define USB_BCDETSTATUS_CPDETECTED_Pos    (1UL)                     /*!< CPDETECTED (Bit 1)                                    */
46537 #define USB_BCDETSTATUS_CPDETECTED_Msk    (0x2UL)                   /*!< CPDETECTED (Bitfield-Mask: 0x01)                      */
46538 #define USB_BCDETSTATUS_DPATTACHED_Pos    (0UL)                     /*!< DPATTACHED (Bit 0)                                    */
46539 #define USB_BCDETSTATUS_DPATTACHED_Msk    (0x1UL)                   /*!< DPATTACHED (Bitfield-Mask: 0x01)                      */
46540 /* ======================================================  BCDETCRTL1  ======================================================= */
46541 #define USB_BCDETCRTL1_USBSWRESET_Pos     (31UL)                    /*!< USBSWRESET (Bit 31)                                   */
46542 #define USB_BCDETCRTL1_USBSWRESET_Msk     (0x80000000UL)            /*!< USBSWRESET (Bitfield-Mask: 0x01)                      */
46543 #define USB_BCDETCRTL1_USBDCOMPEN_Pos     (11UL)                    /*!< USBDCOMPEN (Bit 11)                                   */
46544 #define USB_BCDETCRTL1_USBDCOMPEN_Msk     (0x800UL)                 /*!< USBDCOMPEN (Bitfield-Mask: 0x01)                      */
46545 #define USB_BCDETCRTL1_USBDCOMPREF_Pos    (8UL)                     /*!< USBDCOMPREF (Bit 8)                                   */
46546 #define USB_BCDETCRTL1_USBDCOMPREF_Msk    (0x300UL)                 /*!< USBDCOMPREF (Bitfield-Mask: 0x03)                     */
46547 #define USB_BCDETCRTL1_IDPSINKEN_Pos      (7UL)                     /*!< IDPSINKEN (Bit 7)                                     */
46548 #define USB_BCDETCRTL1_IDPSINKEN_Msk      (0x80UL)                  /*!< IDPSINKEN (Bitfield-Mask: 0x01)                       */
46549 #define USB_BCDETCRTL1_VDMSRCEN_Pos       (6UL)                     /*!< VDMSRCEN (Bit 6)                                      */
46550 #define USB_BCDETCRTL1_VDMSRCEN_Msk       (0x40UL)                  /*!< VDMSRCEN (Bitfield-Mask: 0x01)                        */
46551 #define USB_BCDETCRTL1_RDMPDWNEN_Pos      (5UL)                     /*!< RDMPDWNEN (Bit 5)                                     */
46552 #define USB_BCDETCRTL1_RDMPDWNEN_Msk      (0x20UL)                  /*!< RDMPDWNEN (Bitfield-Mask: 0x01)                       */
46553 #define USB_BCDETCRTL1_VDPSRCEN_Pos       (4UL)                     /*!< VDPSRCEN (Bit 4)                                      */
46554 #define USB_BCDETCRTL1_VDPSRCEN_Msk       (0x10UL)                  /*!< VDPSRCEN (Bitfield-Mask: 0x01)                        */
46555 #define USB_BCDETCRTL1_IDPSRCEN_Pos       (3UL)                     /*!< IDPSRCEN (Bit 3)                                      */
46556 #define USB_BCDETCRTL1_IDPSRCEN_Msk       (0x8UL)                   /*!< IDPSRCEN (Bitfield-Mask: 0x01)                        */
46557 #define USB_BCDETCRTL1_IDMSINKEN_Pos      (2UL)                     /*!< IDMSINKEN (Bit 2)                                     */
46558 #define USB_BCDETCRTL1_IDMSINKEN_Msk      (0x4UL)                   /*!< IDMSINKEN (Bitfield-Mask: 0x01)                       */
46559 #define USB_BCDETCRTL1_BCWEAKPULLDOWNEN_Pos (1UL)                   /*!< BCWEAKPULLDOWNEN (Bit 1)                              */
46560 #define USB_BCDETCRTL1_BCWEAKPULLDOWNEN_Msk (0x2UL)                 /*!< BCWEAKPULLDOWNEN (Bitfield-Mask: 0x01)                */
46561 #define USB_BCDETCRTL1_BCWEAKPULLUPEN_Pos (0UL)                     /*!< BCWEAKPULLUPEN (Bit 0)                                */
46562 #define USB_BCDETCRTL1_BCWEAKPULLUPEN_Msk (0x1UL)                   /*!< BCWEAKPULLUPEN (Bitfield-Mask: 0x01)                  */
46563 /* ======================================================  BCDETCRTL2  ======================================================= */
46564 #define USB_BCDETCRTL2_BCWEAKPULLDOWNTUNE_Pos (10UL)                /*!< BCWEAKPULLDOWNTUNE (Bit 10)                           */
46565 #define USB_BCDETCRTL2_BCWEAKPULLDOWNTUNE_Msk (0xc00UL)             /*!< BCWEAKPULLDOWNTUNE (Bitfield-Mask: 0x03)              */
46566 #define USB_BCDETCRTL2_BCWEAKPULLUPTUNE_Pos (8UL)                   /*!< BCWEAKPULLUPTUNE (Bit 8)                              */
46567 #define USB_BCDETCRTL2_BCWEAKPULLUPTUNE_Msk (0x300UL)               /*!< BCWEAKPULLUPTUNE (Bitfield-Mask: 0x03)                */
46568 #define USB_BCDETCRTL2_FORCEDCPDET_Pos    (3UL)                     /*!< FORCEDCPDET (Bit 3)                                   */
46569 #define USB_BCDETCRTL2_FORCEDCPDET_Msk    (0x8UL)                   /*!< FORCEDCPDET (Bitfield-Mask: 0x01)                     */
46570 #define USB_BCDETCRTL2_FORCECPDET_Pos     (2UL)                     /*!< FORCECPDET (Bit 2)                                    */
46571 #define USB_BCDETCRTL2_FORCECPDET_Msk     (0x4UL)                   /*!< FORCECPDET (Bitfield-Mask: 0x01)                      */
46572 #define USB_BCDETCRTL2_FORCEDPATTACHED_Pos (1UL)                    /*!< FORCEDPATTACHED (Bit 1)                               */
46573 #define USB_BCDETCRTL2_FORCEDPATTACHED_Msk (0x2UL)                  /*!< FORCEDPATTACHED (Bitfield-Mask: 0x01)                 */
46574 #define USB_BCDETCRTL2_CHARGEDETBYP_Pos   (0UL)                     /*!< CHARGEDETBYP (Bit 0)                                  */
46575 #define USB_BCDETCRTL2_CHARGEDETBYP_Msk   (0x1UL)                   /*!< CHARGEDETBYP (Bitfield-Mask: 0x01)                    */
46576 
46577 
46578 /* =========================================================================================================================== */
46579 /* ================                                           VCOMP                                           ================ */
46580 /* =========================================================================================================================== */
46581 
46582 /* ==========================================================  CFG  ========================================================== */
46583 #define VCOMP_CFG_LVLSEL_Pos              (16UL)                    /*!< LVLSEL (Bit 16)                                       */
46584 #define VCOMP_CFG_LVLSEL_Msk              (0xf0000UL)               /*!< LVLSEL (Bitfield-Mask: 0x0f)                          */
46585 #define VCOMP_CFG_NSEL_Pos                (8UL)                     /*!< NSEL (Bit 8)                                          */
46586 #define VCOMP_CFG_NSEL_Msk                (0x300UL)                 /*!< NSEL (Bitfield-Mask: 0x03)                            */
46587 #define VCOMP_CFG_PSEL_Pos                (0UL)                     /*!< PSEL (Bit 0)                                          */
46588 #define VCOMP_CFG_PSEL_Msk                (0x3UL)                   /*!< PSEL (Bitfield-Mask: 0x03)                            */
46589 /* =========================================================  STAT  ========================================================== */
46590 #define VCOMP_STAT_PWDSTAT_Pos            (1UL)                     /*!< PWDSTAT (Bit 1)                                       */
46591 #define VCOMP_STAT_PWDSTAT_Msk            (0x2UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
46592 #define VCOMP_STAT_CMPOUT_Pos             (0UL)                     /*!< CMPOUT (Bit 0)                                        */
46593 #define VCOMP_STAT_CMPOUT_Msk             (0x1UL)                   /*!< CMPOUT (Bitfield-Mask: 0x01)                          */
46594 /* ========================================================  PWDKEY  ========================================================= */
46595 #define VCOMP_PWDKEY_PWDKEY_Pos           (0UL)                     /*!< PWDKEY (Bit 0)                                        */
46596 #define VCOMP_PWDKEY_PWDKEY_Msk           (0xffffffffUL)            /*!< PWDKEY (Bitfield-Mask: 0xffffffff)                    */
46597 /* =========================================================  INTEN  ========================================================= */
46598 #define VCOMP_INTEN_OUTHI_Pos             (1UL)                     /*!< OUTHI (Bit 1)                                         */
46599 #define VCOMP_INTEN_OUTHI_Msk             (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
46600 #define VCOMP_INTEN_OUTLOW_Pos            (0UL)                     /*!< OUTLOW (Bit 0)                                        */
46601 #define VCOMP_INTEN_OUTLOW_Msk            (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
46602 /* ========================================================  INTSTAT  ======================================================== */
46603 #define VCOMP_INTSTAT_OUTHI_Pos           (1UL)                     /*!< OUTHI (Bit 1)                                         */
46604 #define VCOMP_INTSTAT_OUTHI_Msk           (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
46605 #define VCOMP_INTSTAT_OUTLOW_Pos          (0UL)                     /*!< OUTLOW (Bit 0)                                        */
46606 #define VCOMP_INTSTAT_OUTLOW_Msk          (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
46607 /* ========================================================  INTCLR  ========================================================= */
46608 #define VCOMP_INTCLR_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
46609 #define VCOMP_INTCLR_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
46610 #define VCOMP_INTCLR_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
46611 #define VCOMP_INTCLR_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
46612 /* ========================================================  INTSET  ========================================================= */
46613 #define VCOMP_INTSET_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
46614 #define VCOMP_INTSET_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
46615 #define VCOMP_INTSET_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
46616 #define VCOMP_INTSET_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
46617 
46618 
46619 /* =========================================================================================================================== */
46620 /* ================                                            WDT                                            ================ */
46621 /* =========================================================================================================================== */
46622 
46623 /* ==========================================================  CFG  ========================================================== */
46624 #define WDT_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
46625 #define WDT_CFG_CLKSEL_Msk                (0x7000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
46626 #define WDT_CFG_INTVAL_Pos                (16UL)                    /*!< INTVAL (Bit 16)                                       */
46627 #define WDT_CFG_INTVAL_Msk                (0xff0000UL)              /*!< INTVAL (Bitfield-Mask: 0xff)                          */
46628 #define WDT_CFG_RESVAL_Pos                (8UL)                     /*!< RESVAL (Bit 8)                                        */
46629 #define WDT_CFG_RESVAL_Msk                (0xff00UL)                /*!< RESVAL (Bitfield-Mask: 0xff)                          */
46630 #define WDT_CFG_DSPRESETINTEN_Pos         (3UL)                     /*!< DSPRESETINTEN (Bit 3)                                 */
46631 #define WDT_CFG_DSPRESETINTEN_Msk         (0x8UL)                   /*!< DSPRESETINTEN (Bitfield-Mask: 0x01)                   */
46632 #define WDT_CFG_RESEN_Pos                 (2UL)                     /*!< RESEN (Bit 2)                                         */
46633 #define WDT_CFG_RESEN_Msk                 (0x4UL)                   /*!< RESEN (Bitfield-Mask: 0x01)                           */
46634 #define WDT_CFG_INTEN_Pos                 (1UL)                     /*!< INTEN (Bit 1)                                         */
46635 #define WDT_CFG_INTEN_Msk                 (0x2UL)                   /*!< INTEN (Bitfield-Mask: 0x01)                           */
46636 #define WDT_CFG_WDTEN_Pos                 (0UL)                     /*!< WDTEN (Bit 0)                                         */
46637 #define WDT_CFG_WDTEN_Msk                 (0x1UL)                   /*!< WDTEN (Bitfield-Mask: 0x01)                           */
46638 /* =========================================================  RSTRT  ========================================================= */
46639 #define WDT_RSTRT_RSTRT_Pos               (0UL)                     /*!< RSTRT (Bit 0)                                         */
46640 #define WDT_RSTRT_RSTRT_Msk               (0xffUL)                  /*!< RSTRT (Bitfield-Mask: 0xff)                           */
46641 /* =========================================================  LOCK  ========================================================== */
46642 #define WDT_LOCK_LOCK_Pos                 (0UL)                     /*!< LOCK (Bit 0)                                          */
46643 #define WDT_LOCK_LOCK_Msk                 (0xffUL)                  /*!< LOCK (Bitfield-Mask: 0xff)                            */
46644 /* =========================================================  COUNT  ========================================================= */
46645 #define WDT_COUNT_COUNT_Pos               (0UL)                     /*!< COUNT (Bit 0)                                         */
46646 #define WDT_COUNT_COUNT_Msk               (0xffUL)                  /*!< COUNT (Bitfield-Mask: 0xff)                           */
46647 /* ========================================================  DSP0CFG  ======================================================== */
46648 #define WDT_DSP0CFG_DSP0PMRESVAL_Pos      (24UL)                    /*!< DSP0PMRESVAL (Bit 24)                                 */
46649 #define WDT_DSP0CFG_DSP0PMRESVAL_Msk      (0xff000000UL)            /*!< DSP0PMRESVAL (Bitfield-Mask: 0xff)                    */
46650 #define WDT_DSP0CFG_DSP0INTVAL_Pos        (16UL)                    /*!< DSP0INTVAL (Bit 16)                                   */
46651 #define WDT_DSP0CFG_DSP0INTVAL_Msk        (0xff0000UL)              /*!< DSP0INTVAL (Bitfield-Mask: 0xff)                      */
46652 #define WDT_DSP0CFG_DSP0RESVAL_Pos        (8UL)                     /*!< DSP0RESVAL (Bit 8)                                    */
46653 #define WDT_DSP0CFG_DSP0RESVAL_Msk        (0xff00UL)                /*!< DSP0RESVAL (Bitfield-Mask: 0xff)                      */
46654 #define WDT_DSP0CFG_DSP0PMRESEN_Pos       (3UL)                     /*!< DSP0PMRESEN (Bit 3)                                   */
46655 #define WDT_DSP0CFG_DSP0PMRESEN_Msk       (0x8UL)                   /*!< DSP0PMRESEN (Bitfield-Mask: 0x01)                     */
46656 #define WDT_DSP0CFG_DSP0RESEN_Pos         (2UL)                     /*!< DSP0RESEN (Bit 2)                                     */
46657 #define WDT_DSP0CFG_DSP0RESEN_Msk         (0x4UL)                   /*!< DSP0RESEN (Bitfield-Mask: 0x01)                       */
46658 #define WDT_DSP0CFG_DSP0INTEN_Pos         (1UL)                     /*!< DSP0INTEN (Bit 1)                                     */
46659 #define WDT_DSP0CFG_DSP0INTEN_Msk         (0x2UL)                   /*!< DSP0INTEN (Bitfield-Mask: 0x01)                       */
46660 #define WDT_DSP0CFG_DSP0WDTEN_Pos         (0UL)                     /*!< DSP0WDTEN (Bit 0)                                     */
46661 #define WDT_DSP0CFG_DSP0WDTEN_Msk         (0x1UL)                   /*!< DSP0WDTEN (Bitfield-Mask: 0x01)                       */
46662 /* =======================================================  DSP0RSTRT  ======================================================= */
46663 #define WDT_DSP0RSTRT_DSP0RSTART_Pos      (0UL)                     /*!< DSP0RSTART (Bit 0)                                    */
46664 #define WDT_DSP0RSTRT_DSP0RSTART_Msk      (0xffUL)                  /*!< DSP0RSTART (Bitfield-Mask: 0xff)                      */
46665 /* =======================================================  DSP0TLOCK  ======================================================= */
46666 #define WDT_DSP0TLOCK_DSP0LOCK_Pos        (0UL)                     /*!< DSP0LOCK (Bit 0)                                      */
46667 #define WDT_DSP0TLOCK_DSP0LOCK_Msk        (0xffUL)                  /*!< DSP0LOCK (Bitfield-Mask: 0xff)                        */
46668 /* =======================================================  DSP0COUNT  ======================================================= */
46669 #define WDT_DSP0COUNT_DSP0COUNT_Pos       (0UL)                     /*!< DSP0COUNT (Bit 0)                                     */
46670 #define WDT_DSP0COUNT_DSP0COUNT_Msk       (0xffUL)                  /*!< DSP0COUNT (Bitfield-Mask: 0xff)                       */
46671 /* ========================================================  DSP1CFG  ======================================================== */
46672 #define WDT_DSP1CFG_DSP1PMRESVAL_Pos      (24UL)                    /*!< DSP1PMRESVAL (Bit 24)                                 */
46673 #define WDT_DSP1CFG_DSP1PMRESVAL_Msk      (0xff000000UL)            /*!< DSP1PMRESVAL (Bitfield-Mask: 0xff)                    */
46674 #define WDT_DSP1CFG_DSP1INTVAL_Pos        (16UL)                    /*!< DSP1INTVAL (Bit 16)                                   */
46675 #define WDT_DSP1CFG_DSP1INTVAL_Msk        (0xff0000UL)              /*!< DSP1INTVAL (Bitfield-Mask: 0xff)                      */
46676 #define WDT_DSP1CFG_DSP1RESVAL_Pos        (8UL)                     /*!< DSP1RESVAL (Bit 8)                                    */
46677 #define WDT_DSP1CFG_DSP1RESVAL_Msk        (0xff00UL)                /*!< DSP1RESVAL (Bitfield-Mask: 0xff)                      */
46678 #define WDT_DSP1CFG_DSP1PMRESEN_Pos       (3UL)                     /*!< DSP1PMRESEN (Bit 3)                                   */
46679 #define WDT_DSP1CFG_DSP1PMRESEN_Msk       (0x8UL)                   /*!< DSP1PMRESEN (Bitfield-Mask: 0x01)                     */
46680 #define WDT_DSP1CFG_DSP1RESEN_Pos         (2UL)                     /*!< DSP1RESEN (Bit 2)                                     */
46681 #define WDT_DSP1CFG_DSP1RESEN_Msk         (0x4UL)                   /*!< DSP1RESEN (Bitfield-Mask: 0x01)                       */
46682 #define WDT_DSP1CFG_DSP1INTEN_Pos         (1UL)                     /*!< DSP1INTEN (Bit 1)                                     */
46683 #define WDT_DSP1CFG_DSP1INTEN_Msk         (0x2UL)                   /*!< DSP1INTEN (Bitfield-Mask: 0x01)                       */
46684 #define WDT_DSP1CFG_DSP1WDTEN_Pos         (0UL)                     /*!< DSP1WDTEN (Bit 0)                                     */
46685 #define WDT_DSP1CFG_DSP1WDTEN_Msk         (0x1UL)                   /*!< DSP1WDTEN (Bitfield-Mask: 0x01)                       */
46686 /* =======================================================  DSP1RSTRT  ======================================================= */
46687 #define WDT_DSP1RSTRT_DSP1RSTART_Pos      (0UL)                     /*!< DSP1RSTART (Bit 0)                                    */
46688 #define WDT_DSP1RSTRT_DSP1RSTART_Msk      (0xffUL)                  /*!< DSP1RSTART (Bitfield-Mask: 0xff)                      */
46689 /* =======================================================  DSP1TLOCK  ======================================================= */
46690 #define WDT_DSP1TLOCK_DSP1LOCK_Pos        (0UL)                     /*!< DSP1LOCK (Bit 0)                                      */
46691 #define WDT_DSP1TLOCK_DSP1LOCK_Msk        (0xffUL)                  /*!< DSP1LOCK (Bitfield-Mask: 0xff)                        */
46692 /* =======================================================  DSP1COUNT  ======================================================= */
46693 #define WDT_DSP1COUNT_DSP1COUNT_Pos       (0UL)                     /*!< DSP1COUNT (Bit 0)                                     */
46694 #define WDT_DSP1COUNT_DSP1COUNT_Msk       (0xffUL)                  /*!< DSP1COUNT (Bitfield-Mask: 0xff)                       */
46695 /* =======================================================  WDTIEREN  ======================================================== */
46696 #define WDT_WDTIEREN_DSPRESETINT_Pos      (1UL)                     /*!< DSPRESETINT (Bit 1)                                   */
46697 #define WDT_WDTIEREN_DSPRESETINT_Msk      (0x2UL)                   /*!< DSPRESETINT (Bitfield-Mask: 0x01)                     */
46698 #define WDT_WDTIEREN_WDTINT_Pos           (0UL)                     /*!< WDTINT (Bit 0)                                        */
46699 #define WDT_WDTIEREN_WDTINT_Msk           (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
46700 /* ======================================================  WDTIERSTAT  ======================================================= */
46701 #define WDT_WDTIERSTAT_DSPRESETINT_Pos    (1UL)                     /*!< DSPRESETINT (Bit 1)                                   */
46702 #define WDT_WDTIERSTAT_DSPRESETINT_Msk    (0x2UL)                   /*!< DSPRESETINT (Bitfield-Mask: 0x01)                     */
46703 #define WDT_WDTIERSTAT_WDTINT_Pos         (0UL)                     /*!< WDTINT (Bit 0)                                        */
46704 #define WDT_WDTIERSTAT_WDTINT_Msk         (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
46705 /* =======================================================  WDTIERCLR  ======================================================= */
46706 #define WDT_WDTIERCLR_DSPRESETINT_Pos     (1UL)                     /*!< DSPRESETINT (Bit 1)                                   */
46707 #define WDT_WDTIERCLR_DSPRESETINT_Msk     (0x2UL)                   /*!< DSPRESETINT (Bitfield-Mask: 0x01)                     */
46708 #define WDT_WDTIERCLR_WDTINT_Pos          (0UL)                     /*!< WDTINT (Bit 0)                                        */
46709 #define WDT_WDTIERCLR_WDTINT_Msk          (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
46710 /* =======================================================  WDTIERSET  ======================================================= */
46711 #define WDT_WDTIERSET_DSPRESETINT_Pos     (1UL)                     /*!< DSPRESETINT (Bit 1)                                   */
46712 #define WDT_WDTIERSET_DSPRESETINT_Msk     (0x2UL)                   /*!< DSPRESETINT (Bitfield-Mask: 0x01)                     */
46713 #define WDT_WDTIERSET_WDTINT_Pos          (0UL)                     /*!< WDTINT (Bit 0)                                        */
46714 #define WDT_WDTIERSET_WDTINT_Msk          (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
46715 /* =======================================================  DSP0IEREN  ======================================================= */
46716 #define WDT_DSP0IEREN_DSP0INT_Pos         (0UL)                     /*!< DSP0INT (Bit 0)                                       */
46717 #define WDT_DSP0IEREN_DSP0INT_Msk         (0x1UL)                   /*!< DSP0INT (Bitfield-Mask: 0x01)                         */
46718 /* ======================================================  DSP0IERSTAT  ====================================================== */
46719 #define WDT_DSP0IERSTAT_DSP0INT_Pos       (0UL)                     /*!< DSP0INT (Bit 0)                                       */
46720 #define WDT_DSP0IERSTAT_DSP0INT_Msk       (0x1UL)                   /*!< DSP0INT (Bitfield-Mask: 0x01)                         */
46721 /* ======================================================  DSP0IERCLR  ======================================================= */
46722 #define WDT_DSP0IERCLR_DSP0INT_Pos        (0UL)                     /*!< DSP0INT (Bit 0)                                       */
46723 #define WDT_DSP0IERCLR_DSP0INT_Msk        (0x1UL)                   /*!< DSP0INT (Bitfield-Mask: 0x01)                         */
46724 /* ======================================================  DSP0IERSET  ======================================================= */
46725 #define WDT_DSP0IERSET_DSP0INT_Pos        (0UL)                     /*!< DSP0INT (Bit 0)                                       */
46726 #define WDT_DSP0IERSET_DSP0INT_Msk        (0x1UL)                   /*!< DSP0INT (Bitfield-Mask: 0x01)                         */
46727 /* =======================================================  DSP1IEREN  ======================================================= */
46728 #define WDT_DSP1IEREN_DSP1INT_Pos         (0UL)                     /*!< DSP1INT (Bit 0)                                       */
46729 #define WDT_DSP1IEREN_DSP1INT_Msk         (0x1UL)                   /*!< DSP1INT (Bitfield-Mask: 0x01)                         */
46730 /* ======================================================  DSP1IERSTAT  ====================================================== */
46731 #define WDT_DSP1IERSTAT_DSP1INT_Pos       (0UL)                     /*!< DSP1INT (Bit 0)                                       */
46732 #define WDT_DSP1IERSTAT_DSP1INT_Msk       (0x1UL)                   /*!< DSP1INT (Bitfield-Mask: 0x01)                         */
46733 /* ======================================================  DSP1IERCLR  ======================================================= */
46734 #define WDT_DSP1IERCLR_DSP1INT_Pos        (0UL)                     /*!< DSP1INT (Bit 0)                                       */
46735 #define WDT_DSP1IERCLR_DSP1INT_Msk        (0x1UL)                   /*!< DSP1INT (Bitfield-Mask: 0x01)                         */
46736 /* ======================================================  DSP1IERSET  ======================================================= */
46737 #define WDT_DSP1IERSET_DSP1INT_Pos        (0UL)                     /*!< DSP1INT (Bit 0)                                       */
46738 #define WDT_DSP1IERSET_DSP1INT_Msk        (0x1UL)                   /*!< DSP1INT (Bitfield-Mask: 0x01)                         */
46739 
46740 /** @} */ /* End of group PosMask_peripherals */
46741 
46742 
46743 /* =========================================================================================================================== */
46744 /* ================                           Enumerated Values Peripheral Section                            ================ */
46745 /* =========================================================================================================================== */
46746 
46747 
46748 /** @addtogroup EnumValue_peripherals
46749   * @{
46750   */
46751 
46752 
46753 
46754 /* =========================================================================================================================== */
46755 /* ================                                            ADC                                            ================ */
46756 /* =========================================================================================================================== */
46757 
46758 /* ==========================================================  CFG  ========================================================== */
46759 /* ================================================  ADC CFG CLKSEL [24..25]  ================================================ */
46760 typedef enum {                                  /*!< ADC_CFG_CLKSEL                                                            */
46761   ADC_CFG_CLKSEL_HFRC_48MHZ            = 0,     /*!< HFRC_48MHZ : This setting must not be used for CLKSEL for the
46762                                                      GP ADC even though it is the default setting. Software
46763                                                      must set CLKSEL to HFRC_24MHZ after any reset event and
46764                                                      before enabling the ADC.                                                  */
46765   ADC_CFG_CLKSEL_HFRC_48MHZ1           = 1,     /*!< HFRC_48MHZ1 : This setting must not be used for CLKSEL for the
46766                                                      GP ADC.                                                                   */
46767   ADC_CFG_CLKSEL_HFRC_24MHZ            = 2,     /*!< HFRC_24MHZ : HFRC clock at 24 MHz. This setting is the only
46768                                                      valid setting for the GP ADC.                                             */
46769   ADC_CFG_CLKSEL_HFRC2_48MHZ           = 3,     /*!< HFRC2_48MHZ : This setting must not be used for CLKSEL for the
46770                                                      GP ADC.                                                                   */
46771 } ADC_CFG_CLKSEL_Enum;
46772 
46773 /* ==============================================  ADC CFG RPTTRIGSEL [20..20]  ============================================== */
46774 typedef enum {                                  /*!< ADC_CFG_RPTTRIGSEL                                                        */
46775   ADC_CFG_RPTTRIGSEL_TMR               = 0,     /*!< TMR : Trigger from on-chip timer.                                         */
46776   ADC_CFG_RPTTRIGSEL_INT               = 1,     /*!< INT : Trigger from ADC-internal timer.                                    */
46777 } ADC_CFG_RPTTRIGSEL_Enum;
46778 
46779 /* ===============================================  ADC CFG TRIGPOL [19..19]  ================================================ */
46780 typedef enum {                                  /*!< ADC_CFG_TRIGPOL                                                           */
46781   ADC_CFG_TRIGPOL_RISING_EDGE          = 0,     /*!< RISING_EDGE : Trigger on rising edge.                                     */
46782   ADC_CFG_TRIGPOL_FALLING_EDGE         = 1,     /*!< FALLING_EDGE : Trigger on falling edge.                                   */
46783 } ADC_CFG_TRIGPOL_Enum;
46784 
46785 /* ===============================================  ADC CFG TRIGSEL [16..18]  ================================================ */
46786 typedef enum {                                  /*!< ADC_CFG_TRIGSEL                                                           */
46787   ADC_CFG_TRIGSEL_EXT0                 = 0,     /*!< EXT0 : Off chip External Trigger0 (ADC_ET0)                               */
46788   ADC_CFG_TRIGSEL_EXT1                 = 1,     /*!< EXT1 : Off chip External Trigger1 (ADC_ET1)                               */
46789   ADC_CFG_TRIGSEL_EXT2                 = 2,     /*!< EXT2 : Off chip External Trigger2 (ADC_ET2)                               */
46790   ADC_CFG_TRIGSEL_EXT3                 = 3,     /*!< EXT3 : Off chip External Trigger3 (ADC_ET3)                               */
46791   ADC_CFG_TRIGSEL_VCOMP                = 4,     /*!< VCOMP : Voltage Comparator Output                                         */
46792   ADC_CFG_TRIGSEL_SWT                  = 7,     /*!< SWT : Software Trigger                                                    */
46793 } ADC_CFG_TRIGSEL_Enum;
46794 
46795 /* ==============================================  ADC CFG DFIFORDEN [12..12]  =============================================== */
46796 typedef enum {                                  /*!< ADC_CFG_DFIFORDEN                                                         */
46797   ADC_CFG_DFIFORDEN_DIS                = 0,     /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register
46798                                                      will not POP an entry off the FIFO.                                       */
46799   ADC_CFG_DFIFORDEN_EN                 = 1,     /*!< EN : Reads to the FIFOPR registger will automatically pop an
46800                                                      entry off the FIFO.                                                       */
46801 } ADC_CFG_DFIFORDEN_Enum;
46802 
46803 /* =================================================  ADC CFG CKMODE [4..4]  ================================================= */
46804 typedef enum {                                  /*!< ADC_CFG_CKMODE                                                            */
46805   ADC_CFG_CKMODE_LPCKMODE              = 0,     /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set
46806                                                      LPCKMODE to 0x1 while configuring the ADC.                                */
46807   ADC_CFG_CKMODE_LLCKMODE              = 1,     /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk
46808                                                      will remain on while in functioning in LPMODE0.                           */
46809 } ADC_CFG_CKMODE_Enum;
46810 
46811 /* =================================================  ADC CFG LPMODE [3..3]  ================================================= */
46812 typedef enum {                                  /*!< ADC_CFG_LPMODE                                                            */
46813   ADC_CFG_LPMODE_MODE0                 = 0,     /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between
46814                                                      scans with minimum latency between a trigger event and
46815                                                      sample data collection.                                                   */
46816   ADC_CFG_LPMODE_MODE1                 = 1,     /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks
46817                                                      associated with the ADC until the next trigger event. Between
46818                                                      scans, the reference buffer requires up to 50us of delay
46819                                                      from a scan trigger event before the conversion will commence
46820                                                      while operating in this mode.                                             */
46821 } ADC_CFG_LPMODE_Enum;
46822 
46823 /* =================================================  ADC CFG RPTEN [2..2]  ================================================== */
46824 typedef enum {                                  /*!< ADC_CFG_RPTEN                                                             */
46825   ADC_CFG_RPTEN_SINGLE_SCAN            = 0,     /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single
46826                                                      scan upon each trigger event.                                             */
46827   ADC_CFG_RPTEN_REPEATING_SCAN         = 1,     /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete
46828                                                      its first scan upon the initial trigger event and all subsequent
46829                                                      scans will occur at regular intervals defined by the configuration
46830                                                      programmed for the CTTMRA3 timer or the ADC-internal timer
46831                                                      (see the RPTTRIGSEL field) until the timer is disabled
46832                                                      or the ADC is disabled. When disabling the ADC (setting
46833                                                      ADCEN to '0'), the RPTEN bit should be cleared.                           */
46834 } ADC_CFG_RPTEN_Enum;
46835 
46836 /* =================================================  ADC CFG ADCEN [0..0]  ================================================== */
46837 typedef enum {                                  /*!< ADC_CFG_ADCEN                                                             */
46838   ADC_CFG_ADCEN_DIS                    = 0,     /*!< DIS : Disable the ADC module.                                             */
46839   ADC_CFG_ADCEN_EN                     = 1,     /*!< EN : Enable the ADC module.                                               */
46840 } ADC_CFG_ADCEN_Enum;
46841 
46842 /* =========================================================  STAT  ========================================================== */
46843 /* ================================================  ADC STAT PWDSTAT [0..0]  ================================================ */
46844 typedef enum {                                  /*!< ADC_STAT_PWDSTAT                                                          */
46845   ADC_STAT_PWDSTAT_ON                  = 0,     /*!< ON : Powered on.                                                          */
46846   ADC_STAT_PWDSTAT_POWERED_DOWN        = 1,     /*!< POWERED_DOWN : ADC Low Power Mode 1.                                      */
46847 } ADC_STAT_PWDSTAT_Enum;
46848 
46849 /* ==========================================================  SWT  ========================================================== */
46850 /* ==================================================  ADC SWT SWT [0..7]  =================================================== */
46851 typedef enum {                                  /*!< ADC_SWT_SWT                                                               */
46852   ADC_SWT_SWT_GEN_SW_TRIGGER           = 55,    /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger.         */
46853   ADC_SWT_SWT_NO_SW_TRIGGER            = 0,     /*!< NO_SW_TRIGGER : Default value.                                            */
46854 } ADC_SWT_SWT_Enum;
46855 
46856 /* ========================================================  SL0CFG  ========================================================= */
46857 /* ==============================================  ADC SL0CFG ADSEL0 [24..26]  =============================================== */
46858 typedef enum {                                  /*!< ADC_SL0CFG_ADSEL0                                                         */
46859   ADC_SL0CFG_ADSEL0_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46860                                                      module for this slot.                                                     */
46861   ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46862                                                      module for this slot.                                                     */
46863   ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46864                                                      module for this slot.                                                     */
46865   ADC_SL0CFG_ADSEL0_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46866                                                      module for this slot.                                                     */
46867   ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46868                                                      divide module for this slot.                                              */
46869   ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46870                                                      divide module for this slot.                                              */
46871   ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46872                                                      divide module for this slot.                                              */
46873   ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46874                                                      divide module for this slot.                                              */
46875 } ADC_SL0CFG_ADSEL0_Enum;
46876 
46877 /* ==============================================  ADC SL0CFG PRMODE0 [16..17]  ============================================== */
46878 typedef enum {                                  /*!< ADC_SL0CFG_PRMODE0                                                        */
46879   ADC_SL0CFG_PRMODE0_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46880   ADC_SL0CFG_PRMODE0_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46881   ADC_SL0CFG_PRMODE0_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46882   ADC_SL0CFG_PRMODE0_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46883 } ADC_SL0CFG_PRMODE0_Enum;
46884 
46885 /* ===============================================  ADC SL0CFG CHSEL0 [8..11]  =============================================== */
46886 typedef enum {                                  /*!< ADC_SL0CFG_CHSEL0                                                         */
46887   ADC_SL0CFG_CHSEL0_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46888   ADC_SL0CFG_CHSEL0_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46889   ADC_SL0CFG_CHSEL0_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46890   ADC_SL0CFG_CHSEL0_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46891   ADC_SL0CFG_CHSEL0_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46892   ADC_SL0CFG_CHSEL0_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46893   ADC_SL0CFG_CHSEL0_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46894   ADC_SL0CFG_CHSEL0_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46895   ADC_SL0CFG_CHSEL0_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46896   ADC_SL0CFG_CHSEL0_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46897   ADC_SL0CFG_CHSEL0_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46898   ADC_SL0CFG_CHSEL0_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46899 } ADC_SL0CFG_CHSEL0_Enum;
46900 
46901 /* ================================================  ADC SL0CFG WCEN0 [1..1]  ================================================ */
46902 typedef enum {                                  /*!< ADC_SL0CFG_WCEN0                                                          */
46903   ADC_SL0CFG_WCEN0_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 0.                              */
46904   ADC_SL0CFG_WCEN0_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 0.                            */
46905 } ADC_SL0CFG_WCEN0_Enum;
46906 
46907 /* ================================================  ADC SL0CFG SLEN0 [0..0]  ================================================ */
46908 typedef enum {                                  /*!< ADC_SL0CFG_SLEN0                                                          */
46909   ADC_SL0CFG_SLEN0_SLEN                = 1,     /*!< SLEN : Enable slot 0 for ADC conversions.                                 */
46910   ADC_SL0CFG_SLEN0_SLDIS               = 0,     /*!< SLDIS : Disable slot 0 for ADC conversions.                               */
46911 } ADC_SL0CFG_SLEN0_Enum;
46912 
46913 /* ========================================================  SL1CFG  ========================================================= */
46914 /* ==============================================  ADC SL1CFG ADSEL1 [24..26]  =============================================== */
46915 typedef enum {                                  /*!< ADC_SL1CFG_ADSEL1                                                         */
46916   ADC_SL1CFG_ADSEL1_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46917                                                      module for this slot.                                                     */
46918   ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46919                                                      module for this slot.                                                     */
46920   ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46921                                                      module for this slot.                                                     */
46922   ADC_SL1CFG_ADSEL1_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46923                                                      module for this slot.                                                     */
46924   ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46925                                                      divide module for this slot.                                              */
46926   ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46927                                                      divide module for this slot.                                              */
46928   ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46929                                                      divide module for this slot.                                              */
46930   ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46931                                                      divide module for this slot.                                              */
46932 } ADC_SL1CFG_ADSEL1_Enum;
46933 
46934 /* ==============================================  ADC SL1CFG PRMODE1 [16..17]  ============================================== */
46935 typedef enum {                                  /*!< ADC_SL1CFG_PRMODE1                                                        */
46936   ADC_SL1CFG_PRMODE1_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46937   ADC_SL1CFG_PRMODE1_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46938   ADC_SL1CFG_PRMODE1_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46939   ADC_SL1CFG_PRMODE1_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46940 } ADC_SL1CFG_PRMODE1_Enum;
46941 
46942 /* ===============================================  ADC SL1CFG CHSEL1 [8..11]  =============================================== */
46943 typedef enum {                                  /*!< ADC_SL1CFG_CHSEL1                                                         */
46944   ADC_SL1CFG_CHSEL1_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
46945   ADC_SL1CFG_CHSEL1_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
46946   ADC_SL1CFG_CHSEL1_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
46947   ADC_SL1CFG_CHSEL1_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
46948   ADC_SL1CFG_CHSEL1_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
46949   ADC_SL1CFG_CHSEL1_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
46950   ADC_SL1CFG_CHSEL1_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
46951   ADC_SL1CFG_CHSEL1_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
46952   ADC_SL1CFG_CHSEL1_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
46953   ADC_SL1CFG_CHSEL1_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
46954   ADC_SL1CFG_CHSEL1_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
46955   ADC_SL1CFG_CHSEL1_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
46956 } ADC_SL1CFG_CHSEL1_Enum;
46957 
46958 /* ================================================  ADC SL1CFG WCEN1 [1..1]  ================================================ */
46959 typedef enum {                                  /*!< ADC_SL1CFG_WCEN1                                                          */
46960   ADC_SL1CFG_WCEN1_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 1.                              */
46961   ADC_SL1CFG_WCEN1_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 1.                            */
46962 } ADC_SL1CFG_WCEN1_Enum;
46963 
46964 /* ================================================  ADC SL1CFG SLEN1 [0..0]  ================================================ */
46965 typedef enum {                                  /*!< ADC_SL1CFG_SLEN1                                                          */
46966   ADC_SL1CFG_SLEN1_SLEN                = 1,     /*!< SLEN : Enable slot 1 for ADC conversions.                                 */
46967   ADC_SL1CFG_SLEN1_SLDIS               = 0,     /*!< SLDIS : Disable slot 1 for ADC conversions.                               */
46968 } ADC_SL1CFG_SLEN1_Enum;
46969 
46970 /* ========================================================  SL2CFG  ========================================================= */
46971 /* ==============================================  ADC SL2CFG ADSEL2 [24..26]  =============================================== */
46972 typedef enum {                                  /*!< ADC_SL2CFG_ADSEL2                                                         */
46973   ADC_SL2CFG_ADSEL2_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
46974                                                      module for this slot.                                                     */
46975   ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
46976                                                      module for this slot.                                                     */
46977   ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
46978                                                      module for this slot.                                                     */
46979   ADC_SL2CFG_ADSEL2_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
46980                                                      module for this slot.                                                     */
46981   ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
46982                                                      divide module for this slot.                                              */
46983   ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
46984                                                      divide module for this slot.                                              */
46985   ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
46986                                                      divide module for this slot.                                              */
46987   ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
46988                                                      divide module for this slot.                                              */
46989 } ADC_SL2CFG_ADSEL2_Enum;
46990 
46991 /* ==============================================  ADC SL2CFG PRMODE2 [16..17]  ============================================== */
46992 typedef enum {                                  /*!< ADC_SL2CFG_PRMODE2                                                        */
46993   ADC_SL2CFG_PRMODE2_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
46994   ADC_SL2CFG_PRMODE2_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
46995   ADC_SL2CFG_PRMODE2_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
46996   ADC_SL2CFG_PRMODE2_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
46997 } ADC_SL2CFG_PRMODE2_Enum;
46998 
46999 /* ===============================================  ADC SL2CFG CHSEL2 [8..11]  =============================================== */
47000 typedef enum {                                  /*!< ADC_SL2CFG_CHSEL2                                                         */
47001   ADC_SL2CFG_CHSEL2_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
47002   ADC_SL2CFG_CHSEL2_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
47003   ADC_SL2CFG_CHSEL2_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
47004   ADC_SL2CFG_CHSEL2_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
47005   ADC_SL2CFG_CHSEL2_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
47006   ADC_SL2CFG_CHSEL2_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
47007   ADC_SL2CFG_CHSEL2_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
47008   ADC_SL2CFG_CHSEL2_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
47009   ADC_SL2CFG_CHSEL2_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
47010   ADC_SL2CFG_CHSEL2_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
47011   ADC_SL2CFG_CHSEL2_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
47012   ADC_SL2CFG_CHSEL2_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
47013 } ADC_SL2CFG_CHSEL2_Enum;
47014 
47015 /* ================================================  ADC SL2CFG WCEN2 [1..1]  ================================================ */
47016 typedef enum {                                  /*!< ADC_SL2CFG_WCEN2                                                          */
47017   ADC_SL2CFG_WCEN2_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 2.                              */
47018   ADC_SL2CFG_WCEN2_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 2.                            */
47019 } ADC_SL2CFG_WCEN2_Enum;
47020 
47021 /* ================================================  ADC SL2CFG SLEN2 [0..0]  ================================================ */
47022 typedef enum {                                  /*!< ADC_SL2CFG_SLEN2                                                          */
47023   ADC_SL2CFG_SLEN2_SLEN                = 1,     /*!< SLEN : Enable slot 2 for ADC conversions.                                 */
47024   ADC_SL2CFG_SLEN2_SLDIS               = 0,     /*!< SLDIS : Disable slot 2 for ADC conversions.                               */
47025 } ADC_SL2CFG_SLEN2_Enum;
47026 
47027 /* ========================================================  SL3CFG  ========================================================= */
47028 /* ==============================================  ADC SL3CFG ADSEL3 [24..26]  =============================================== */
47029 typedef enum {                                  /*!< ADC_SL3CFG_ADSEL3                                                         */
47030   ADC_SL3CFG_ADSEL3_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47031                                                      module for this slot.                                                     */
47032   ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47033                                                      module for this slot.                                                     */
47034   ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47035                                                      module for this slot.                                                     */
47036   ADC_SL3CFG_ADSEL3_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47037                                                      module for this slot.                                                     */
47038   ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47039                                                      divide module for this slot.                                              */
47040   ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47041                                                      divide module for this slot.                                              */
47042   ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47043                                                      divide module for this slot.                                              */
47044   ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47045                                                      divide module for this slot.                                              */
47046 } ADC_SL3CFG_ADSEL3_Enum;
47047 
47048 /* ==============================================  ADC SL3CFG PRMODE3 [16..17]  ============================================== */
47049 typedef enum {                                  /*!< ADC_SL3CFG_PRMODE3                                                        */
47050   ADC_SL3CFG_PRMODE3_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47051   ADC_SL3CFG_PRMODE3_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47052   ADC_SL3CFG_PRMODE3_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
47053   ADC_SL3CFG_PRMODE3_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
47054 } ADC_SL3CFG_PRMODE3_Enum;
47055 
47056 /* ===============================================  ADC SL3CFG CHSEL3 [8..11]  =============================================== */
47057 typedef enum {                                  /*!< ADC_SL3CFG_CHSEL3                                                         */
47058   ADC_SL3CFG_CHSEL3_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
47059   ADC_SL3CFG_CHSEL3_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
47060   ADC_SL3CFG_CHSEL3_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
47061   ADC_SL3CFG_CHSEL3_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
47062   ADC_SL3CFG_CHSEL3_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
47063   ADC_SL3CFG_CHSEL3_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
47064   ADC_SL3CFG_CHSEL3_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
47065   ADC_SL3CFG_CHSEL3_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
47066   ADC_SL3CFG_CHSEL3_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
47067   ADC_SL3CFG_CHSEL3_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
47068   ADC_SL3CFG_CHSEL3_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
47069   ADC_SL3CFG_CHSEL3_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
47070 } ADC_SL3CFG_CHSEL3_Enum;
47071 
47072 /* ================================================  ADC SL3CFG WCEN3 [1..1]  ================================================ */
47073 typedef enum {                                  /*!< ADC_SL3CFG_WCEN3                                                          */
47074   ADC_SL3CFG_WCEN3_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 3.                              */
47075   ADC_SL3CFG_WCEN3_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 3.                            */
47076 } ADC_SL3CFG_WCEN3_Enum;
47077 
47078 /* ================================================  ADC SL3CFG SLEN3 [0..0]  ================================================ */
47079 typedef enum {                                  /*!< ADC_SL3CFG_SLEN3                                                          */
47080   ADC_SL3CFG_SLEN3_SLEN                = 1,     /*!< SLEN : Enable slot 3 for ADC conversions.                                 */
47081   ADC_SL3CFG_SLEN3_SLDIS               = 0,     /*!< SLDIS : Disable slot 3 for ADC conversions.                               */
47082 } ADC_SL3CFG_SLEN3_Enum;
47083 
47084 /* ========================================================  SL4CFG  ========================================================= */
47085 /* ==============================================  ADC SL4CFG ADSEL4 [24..26]  =============================================== */
47086 typedef enum {                                  /*!< ADC_SL4CFG_ADSEL4                                                         */
47087   ADC_SL4CFG_ADSEL4_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47088                                                      module for this slot.                                                     */
47089   ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47090                                                      module for this slot.                                                     */
47091   ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47092                                                      module for this slot.                                                     */
47093   ADC_SL4CFG_ADSEL4_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47094                                                      module for this slot.                                                     */
47095   ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47096                                                      divide module for this slot.                                              */
47097   ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47098                                                      divide module for this slot.                                              */
47099   ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47100                                                      divide module for this slot.                                              */
47101   ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47102                                                      divide module for this slot.                                              */
47103 } ADC_SL4CFG_ADSEL4_Enum;
47104 
47105 /* ==============================================  ADC SL4CFG PRMODE4 [16..17]  ============================================== */
47106 typedef enum {                                  /*!< ADC_SL4CFG_PRMODE4                                                        */
47107   ADC_SL4CFG_PRMODE4_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47108   ADC_SL4CFG_PRMODE4_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47109   ADC_SL4CFG_PRMODE4_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
47110   ADC_SL4CFG_PRMODE4_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
47111 } ADC_SL4CFG_PRMODE4_Enum;
47112 
47113 /* ===============================================  ADC SL4CFG CHSEL4 [8..11]  =============================================== */
47114 typedef enum {                                  /*!< ADC_SL4CFG_CHSEL4                                                         */
47115   ADC_SL4CFG_CHSEL4_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
47116   ADC_SL4CFG_CHSEL4_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
47117   ADC_SL4CFG_CHSEL4_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
47118   ADC_SL4CFG_CHSEL4_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
47119   ADC_SL4CFG_CHSEL4_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
47120   ADC_SL4CFG_CHSEL4_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
47121   ADC_SL4CFG_CHSEL4_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
47122   ADC_SL4CFG_CHSEL4_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
47123   ADC_SL4CFG_CHSEL4_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
47124   ADC_SL4CFG_CHSEL4_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
47125   ADC_SL4CFG_CHSEL4_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
47126   ADC_SL4CFG_CHSEL4_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
47127 } ADC_SL4CFG_CHSEL4_Enum;
47128 
47129 /* ================================================  ADC SL4CFG WCEN4 [1..1]  ================================================ */
47130 typedef enum {                                  /*!< ADC_SL4CFG_WCEN4                                                          */
47131   ADC_SL4CFG_WCEN4_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 4.                              */
47132   ADC_SL4CFG_WCEN4_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 4.                            */
47133 } ADC_SL4CFG_WCEN4_Enum;
47134 
47135 /* ================================================  ADC SL4CFG SLEN4 [0..0]  ================================================ */
47136 typedef enum {                                  /*!< ADC_SL4CFG_SLEN4                                                          */
47137   ADC_SL4CFG_SLEN4_SLEN                = 1,     /*!< SLEN : Enable slot 4 for ADC conversions.                                 */
47138   ADC_SL4CFG_SLEN4_SLDIS               = 0,     /*!< SLDIS : Disable slot 4 for ADC conversions.                               */
47139 } ADC_SL4CFG_SLEN4_Enum;
47140 
47141 /* ========================================================  SL5CFG  ========================================================= */
47142 /* ==============================================  ADC SL5CFG ADSEL5 [24..26]  =============================================== */
47143 typedef enum {                                  /*!< ADC_SL5CFG_ADSEL5                                                         */
47144   ADC_SL5CFG_ADSEL5_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47145                                                      module for this slot.                                                     */
47146   ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47147                                                      module for this slot.                                                     */
47148   ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47149                                                      module for this slot.                                                     */
47150   ADC_SL5CFG_ADSEL5_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47151                                                      module for this slot.                                                     */
47152   ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47153                                                      divide module for this slot.                                              */
47154   ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47155                                                      divide module for this slot.                                              */
47156   ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47157                                                      divide module for this slot.                                              */
47158   ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47159                                                      divide module for this slot.                                              */
47160 } ADC_SL5CFG_ADSEL5_Enum;
47161 
47162 /* ==============================================  ADC SL5CFG PRMODE5 [16..17]  ============================================== */
47163 typedef enum {                                  /*!< ADC_SL5CFG_PRMODE5                                                        */
47164   ADC_SL5CFG_PRMODE5_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47165   ADC_SL5CFG_PRMODE5_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47166   ADC_SL5CFG_PRMODE5_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
47167   ADC_SL5CFG_PRMODE5_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
47168 } ADC_SL5CFG_PRMODE5_Enum;
47169 
47170 /* ===============================================  ADC SL5CFG CHSEL5 [8..11]  =============================================== */
47171 typedef enum {                                  /*!< ADC_SL5CFG_CHSEL5                                                         */
47172   ADC_SL5CFG_CHSEL5_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
47173   ADC_SL5CFG_CHSEL5_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
47174   ADC_SL5CFG_CHSEL5_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
47175   ADC_SL5CFG_CHSEL5_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
47176   ADC_SL5CFG_CHSEL5_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
47177   ADC_SL5CFG_CHSEL5_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
47178   ADC_SL5CFG_CHSEL5_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
47179   ADC_SL5CFG_CHSEL5_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
47180   ADC_SL5CFG_CHSEL5_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
47181   ADC_SL5CFG_CHSEL5_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
47182   ADC_SL5CFG_CHSEL5_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
47183   ADC_SL5CFG_CHSEL5_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
47184 } ADC_SL5CFG_CHSEL5_Enum;
47185 
47186 /* ================================================  ADC SL5CFG WCEN5 [1..1]  ================================================ */
47187 typedef enum {                                  /*!< ADC_SL5CFG_WCEN5                                                          */
47188   ADC_SL5CFG_WCEN5_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 5.                              */
47189   ADC_SL5CFG_WCEN5_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 5.                            */
47190 } ADC_SL5CFG_WCEN5_Enum;
47191 
47192 /* ================================================  ADC SL5CFG SLEN5 [0..0]  ================================================ */
47193 typedef enum {                                  /*!< ADC_SL5CFG_SLEN5                                                          */
47194   ADC_SL5CFG_SLEN5_SLEN                = 1,     /*!< SLEN : Enable slot 5 for ADC conversions.                                 */
47195   ADC_SL5CFG_SLEN5_SLDIS               = 0,     /*!< SLDIS : Disable slot 5 for ADC conversions.                               */
47196 } ADC_SL5CFG_SLEN5_Enum;
47197 
47198 /* ========================================================  SL6CFG  ========================================================= */
47199 /* ==============================================  ADC SL6CFG ADSEL6 [24..26]  =============================================== */
47200 typedef enum {                                  /*!< ADC_SL6CFG_ADSEL6                                                         */
47201   ADC_SL6CFG_ADSEL6_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47202                                                      module for this slot.                                                     */
47203   ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47204                                                      module for this slot.                                                     */
47205   ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47206                                                      module for this slot.                                                     */
47207   ADC_SL6CFG_ADSEL6_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47208                                                      module for this slot.                                                     */
47209   ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47210                                                      divide module for this slot.                                              */
47211   ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47212                                                      divide module for this slot.                                              */
47213   ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47214                                                      divide module for this slot.                                              */
47215   ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47216                                                      divide module for this slot.                                              */
47217 } ADC_SL6CFG_ADSEL6_Enum;
47218 
47219 /* ==============================================  ADC SL6CFG PRMODE6 [16..17]  ============================================== */
47220 typedef enum {                                  /*!< ADC_SL6CFG_PRMODE6                                                        */
47221   ADC_SL6CFG_PRMODE6_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47222   ADC_SL6CFG_PRMODE6_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47223   ADC_SL6CFG_PRMODE6_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
47224   ADC_SL6CFG_PRMODE6_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
47225 } ADC_SL6CFG_PRMODE6_Enum;
47226 
47227 /* ===============================================  ADC SL6CFG CHSEL6 [8..11]  =============================================== */
47228 typedef enum {                                  /*!< ADC_SL6CFG_CHSEL6                                                         */
47229   ADC_SL6CFG_CHSEL6_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
47230   ADC_SL6CFG_CHSEL6_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
47231   ADC_SL6CFG_CHSEL6_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
47232   ADC_SL6CFG_CHSEL6_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
47233   ADC_SL6CFG_CHSEL6_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
47234   ADC_SL6CFG_CHSEL6_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
47235   ADC_SL6CFG_CHSEL6_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
47236   ADC_SL6CFG_CHSEL6_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
47237   ADC_SL6CFG_CHSEL6_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
47238   ADC_SL6CFG_CHSEL6_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
47239   ADC_SL6CFG_CHSEL6_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
47240   ADC_SL6CFG_CHSEL6_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
47241 } ADC_SL6CFG_CHSEL6_Enum;
47242 
47243 /* ================================================  ADC SL6CFG WCEN6 [1..1]  ================================================ */
47244 typedef enum {                                  /*!< ADC_SL6CFG_WCEN6                                                          */
47245   ADC_SL6CFG_WCEN6_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 6.                              */
47246   ADC_SL6CFG_WCEN6_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 6.                            */
47247 } ADC_SL6CFG_WCEN6_Enum;
47248 
47249 /* ================================================  ADC SL6CFG SLEN6 [0..0]  ================================================ */
47250 typedef enum {                                  /*!< ADC_SL6CFG_SLEN6                                                          */
47251   ADC_SL6CFG_SLEN6_SLEN                = 1,     /*!< SLEN : Enable slot 6 for ADC conversions.                                 */
47252   ADC_SL6CFG_SLEN6_SLDIS               = 0,     /*!< SLDIS : Disable slot 6 for ADC conversions.                               */
47253 } ADC_SL6CFG_SLEN6_Enum;
47254 
47255 /* ========================================================  SL7CFG  ========================================================= */
47256 /* ==============================================  ADC SL7CFG ADSEL7 [24..26]  =============================================== */
47257 typedef enum {                                  /*!< ADC_SL7CFG_ADSEL7                                                         */
47258   ADC_SL7CFG_ADSEL7_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47259                                                      module for this slot.                                                     */
47260   ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47261                                                      module for this slot.                                                     */
47262   ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47263                                                      module for this slot.                                                     */
47264   ADC_SL7CFG_ADSEL7_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47265                                                      module for this slot.                                                     */
47266   ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47267                                                      divide module for this slot.                                              */
47268   ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47269                                                      divide module for this slot.                                              */
47270   ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47271                                                      divide module for this slot.                                              */
47272   ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47273                                                      divide module for this slot.                                              */
47274 } ADC_SL7CFG_ADSEL7_Enum;
47275 
47276 /* ==============================================  ADC SL7CFG PRMODE7 [16..17]  ============================================== */
47277 typedef enum {                                  /*!< ADC_SL7CFG_PRMODE7                                                        */
47278   ADC_SL7CFG_PRMODE7_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47279   ADC_SL7CFG_PRMODE7_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47280   ADC_SL7CFG_PRMODE7_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
47281   ADC_SL7CFG_PRMODE7_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
47282 } ADC_SL7CFG_PRMODE7_Enum;
47283 
47284 /* ===============================================  ADC SL7CFG CHSEL7 [8..11]  =============================================== */
47285 typedef enum {                                  /*!< ADC_SL7CFG_CHSEL7                                                         */
47286   ADC_SL7CFG_CHSEL7_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection to pad16.                     */
47287   ADC_SL7CFG_CHSEL7_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection to pad29.                     */
47288   ADC_SL7CFG_CHSEL7_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection to pad11.                     */
47289   ADC_SL7CFG_CHSEL7_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection to pad31.                     */
47290   ADC_SL7CFG_CHSEL7_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection to pad32.                     */
47291   ADC_SL7CFG_CHSEL7_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection to pad33.                     */
47292   ADC_SL7CFG_CHSEL7_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection to pad34.                     */
47293   ADC_SL7CFG_CHSEL7_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection to pad35.                     */
47294   ADC_SL7CFG_CHSEL7_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
47295   ADC_SL7CFG_CHSEL7_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
47296   ADC_SL7CFG_CHSEL7_TESTMUX            = 10,    /*!< TESTMUX : Analog testmux.                                                 */
47297   ADC_SL7CFG_CHSEL7_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
47298 } ADC_SL7CFG_CHSEL7_Enum;
47299 
47300 /* ================================================  ADC SL7CFG WCEN7 [1..1]  ================================================ */
47301 typedef enum {                                  /*!< ADC_SL7CFG_WCEN7                                                          */
47302   ADC_SL7CFG_WCEN7_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 7.                              */
47303   ADC_SL7CFG_WCEN7_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 7.                            */
47304 } ADC_SL7CFG_WCEN7_Enum;
47305 
47306 /* ================================================  ADC SL7CFG SLEN7 [0..0]  ================================================ */
47307 typedef enum {                                  /*!< ADC_SL7CFG_SLEN7                                                          */
47308   ADC_SL7CFG_SLEN7_SLEN                = 1,     /*!< SLEN : Enable slot 7 for ADC conversions.                                 */
47309   ADC_SL7CFG_SLEN7_SLDIS               = 0,     /*!< SLDIS : Disable slot 7 for ADC conversions.                               */
47310 } ADC_SL7CFG_SLEN7_Enum;
47311 
47312 /* =========================================================  WULIM  ========================================================= */
47313 /* =========================================================  WLLIM  ========================================================= */
47314 /* ========================================================  SCWLIM  ========================================================= */
47315 /* =========================================================  FIFO  ========================================================== */
47316 /* ========================================================  FIFOPR  ========================================================= */
47317 /* =====================================================  INTTRIGTIMER  ====================================================== */
47318 /* ===========================================  ADC INTTRIGTIMER TIMEREN [31..31]  =========================================== */
47319 typedef enum {                                  /*!< ADC_INTTRIGTIMER_TIMEREN                                                  */
47320   ADC_INTTRIGTIMER_TIMEREN_DIS         = 0,     /*!< DIS : Disable the ADC-internal trigger timer.                             */
47321   ADC_INTTRIGTIMER_TIMEREN_EN          = 1,     /*!< EN : Enable the ADC-internal trigger timer.                               */
47322 } ADC_INTTRIGTIMER_TIMEREN_Enum;
47323 
47324 /* =========================================================  ZXCFG  ========================================================= */
47325 /* =========================================================  ZXLIM  ========================================================= */
47326 /* ========================================================  GAINCFG  ======================================================== */
47327 /* =============================================  ADC GAINCFG UPDATEMODE [4..4]  ============================================= */
47328 typedef enum {                                  /*!< ADC_GAINCFG_UPDATEMODE                                                    */
47329   ADC_GAINCFG_UPDATEMODE_IMMED         = 0,     /*!< IMMED : Immediate update mode. Once gain is written, it is immediately
47330                                                      encoded and provided to the PGA.                                          */
47331   ADC_GAINCFG_UPDATEMODE_ZX            = 1,     /*!< ZX : Update gain only at detected zero crossing as configured
47332                                                      by ZX registers.                                                          */
47333 } ADC_GAINCFG_UPDATEMODE_Enum;
47334 
47335 /* =========================================================  GAIN  ========================================================== */
47336 /* ========================================================  SATCFG  ========================================================= */
47337 /* ========================================================  SATLIM  ========================================================= */
47338 /* ========================================================  SATMAX  ========================================================= */
47339 /* ========================================================  SATCLR  ========================================================= */
47340 /* =========================================================  INTEN  ========================================================= */
47341 /* ===============================================  ADC INTEN SATCB [11..11]  ================================================ */
47342 typedef enum {                                  /*!< ADC_INTEN_SATCB                                                           */
47343   ADC_INTEN_SATCB_SATCBINT             = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
47344                                                      occurred on either slot 2 or 3 (channel B)                                */
47345   ADC_INTEN_SATCB_NONSATCBINT          = 0,     /*!< NONSATCBINT : No-Saturation                                               */
47346 } ADC_INTEN_SATCB_Enum;
47347 
47348 /* ===============================================  ADC INTEN SATCA [10..10]  ================================================ */
47349 typedef enum {                                  /*!< ADC_INTEN_SATCA                                                           */
47350   ADC_INTEN_SATCA_SATCAINT             = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
47351                                                      occurred on either slot 0 or 1 (channel A)                                */
47352   ADC_INTEN_SATCA_NONSATCAINT          = 0,     /*!< NONSATCAINT : No Saturation                                               */
47353 } ADC_INTEN_SATCA_Enum;
47354 
47355 /* =================================================  ADC INTEN ZXCB [9..9]  ================================================= */
47356 typedef enum {                                  /*!< ADC_INTEN_ZXCB                                                            */
47357   ADC_INTEN_ZXCB_ZXCBINT               = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
47358                                                      occurred on either slot 2 or 3 (channel B)                                */
47359   ADC_INTEN_ZXCB_NONZXCBINT            = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
47360 } ADC_INTEN_ZXCB_Enum;
47361 
47362 /* =================================================  ADC INTEN ZXCA [8..8]  ================================================= */
47363 typedef enum {                                  /*!< ADC_INTEN_ZXCA                                                            */
47364   ADC_INTEN_ZXCA_ZXCAINT               = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
47365                                                      occurred on either slot 0 or 1 (channel A)                                */
47366   ADC_INTEN_ZXCA_NONZXCAINT            = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
47367 } ADC_INTEN_ZXCA_Enum;
47368 
47369 /* =================================================  ADC INTEN DERR [7..7]  ================================================= */
47370 typedef enum {                                  /*!< ADC_INTEN_DERR                                                            */
47371   ADC_INTEN_DERR_DMAERROR              = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
47372   ADC_INTEN_DERR_NODMAERROR            = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
47373 } ADC_INTEN_DERR_Enum;
47374 
47375 /* =================================================  ADC INTEN DCMP [6..6]  ================================================= */
47376 typedef enum {                                  /*!< ADC_INTEN_DCMP                                                            */
47377   ADC_INTEN_DCMP_DMACOMPLETE           = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
47378   ADC_INTEN_DCMP_DMAON                 = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
47379 } ADC_INTEN_DCMP_Enum;
47380 
47381 /* ================================================  ADC INTEN WCINC [5..5]  ================================================= */
47382 typedef enum {                                  /*!< ADC_INTEN_WCINC                                                           */
47383   ADC_INTEN_WCINC_WCINCINT             = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
47384   ADC_INTEN_WCINC_WCINCNOINT           = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
47385 } ADC_INTEN_WCINC_Enum;
47386 
47387 /* ================================================  ADC INTEN WCEXC [4..4]  ================================================= */
47388 typedef enum {                                  /*!< ADC_INTEN_WCEXC                                                           */
47389   ADC_INTEN_WCEXC_WCEXCINT             = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
47390   ADC_INTEN_WCEXC_WCEXCNOINT           = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
47391 } ADC_INTEN_WCEXC_Enum;
47392 
47393 /* ===============================================  ADC INTEN FIFOOVR2 [3..3]  =============================================== */
47394 typedef enum {                                  /*!< ADC_INTEN_FIFOOVR2                                                        */
47395   ADC_INTEN_FIFOOVR2_FIFOFULLINT       = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
47396   ADC_INTEN_FIFOOVR2_FIFOFULLNOINT     = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
47397 } ADC_INTEN_FIFOOVR2_Enum;
47398 
47399 /* ===============================================  ADC INTEN FIFOOVR1 [2..2]  =============================================== */
47400 typedef enum {                                  /*!< ADC_INTEN_FIFOOVR1                                                        */
47401   ADC_INTEN_FIFOOVR1_FIFO75INT         = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
47402   ADC_INTEN_FIFOOVR1_FIFO75NOINT       = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
47403 } ADC_INTEN_FIFOOVR1_Enum;
47404 
47405 /* ================================================  ADC INTEN SCNCMP [1..1]  ================================================ */
47406 typedef enum {                                  /*!< ADC_INTEN_SCNCMP                                                          */
47407   ADC_INTEN_SCNCMP_SCNCMPINT           = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
47408   ADC_INTEN_SCNCMP_SCNCMPNOINT         = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
47409 } ADC_INTEN_SCNCMP_Enum;
47410 
47411 /* ================================================  ADC INTEN CNVCMP [0..0]  ================================================ */
47412 typedef enum {                                  /*!< ADC_INTEN_CNVCMP                                                          */
47413   ADC_INTEN_CNVCMP_CNVCMPINT           = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
47414   ADC_INTEN_CNVCMP_CNVCMPNOINT         = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
47415 } ADC_INTEN_CNVCMP_Enum;
47416 
47417 /* ========================================================  INTSTAT  ======================================================== */
47418 /* ==============================================  ADC INTSTAT SATCB [11..11]  =============================================== */
47419 typedef enum {                                  /*!< ADC_INTSTAT_SATCB                                                         */
47420   ADC_INTSTAT_SATCB_SATCBINT           = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
47421                                                      occurred on either slot 2 or 3 (channel B)                                */
47422   ADC_INTSTAT_SATCB_NONSATCBINT        = 0,     /*!< NONSATCBINT : No-Saturation                                               */
47423 } ADC_INTSTAT_SATCB_Enum;
47424 
47425 /* ==============================================  ADC INTSTAT SATCA [10..10]  =============================================== */
47426 typedef enum {                                  /*!< ADC_INTSTAT_SATCA                                                         */
47427   ADC_INTSTAT_SATCA_SATCAINT           = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
47428                                                      occurred on either slot 0 or 1 (channel A)                                */
47429   ADC_INTSTAT_SATCA_NONSATCAINT        = 0,     /*!< NONSATCAINT : No Saturation                                               */
47430 } ADC_INTSTAT_SATCA_Enum;
47431 
47432 /* ================================================  ADC INTSTAT ZXCB [9..9]  ================================================ */
47433 typedef enum {                                  /*!< ADC_INTSTAT_ZXCB                                                          */
47434   ADC_INTSTAT_ZXCB_ZXCBINT             = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
47435                                                      occurred on either slot 2 or 3 (channel B)                                */
47436   ADC_INTSTAT_ZXCB_NONZXCBINT          = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
47437 } ADC_INTSTAT_ZXCB_Enum;
47438 
47439 /* ================================================  ADC INTSTAT ZXCA [8..8]  ================================================ */
47440 typedef enum {                                  /*!< ADC_INTSTAT_ZXCA                                                          */
47441   ADC_INTSTAT_ZXCA_ZXCAINT             = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
47442                                                      occurred on either slot 0 or 1 (channel A)                                */
47443   ADC_INTSTAT_ZXCA_NONZXCAINT          = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
47444 } ADC_INTSTAT_ZXCA_Enum;
47445 
47446 /* ================================================  ADC INTSTAT DERR [7..7]  ================================================ */
47447 typedef enum {                                  /*!< ADC_INTSTAT_DERR                                                          */
47448   ADC_INTSTAT_DERR_DMAERROR            = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
47449   ADC_INTSTAT_DERR_NODMAERROR          = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
47450 } ADC_INTSTAT_DERR_Enum;
47451 
47452 /* ================================================  ADC INTSTAT DCMP [6..6]  ================================================ */
47453 typedef enum {                                  /*!< ADC_INTSTAT_DCMP                                                          */
47454   ADC_INTSTAT_DCMP_DMACOMPLETE         = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
47455   ADC_INTSTAT_DCMP_DMAON               = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
47456 } ADC_INTSTAT_DCMP_Enum;
47457 
47458 /* ===============================================  ADC INTSTAT WCINC [5..5]  ================================================ */
47459 typedef enum {                                  /*!< ADC_INTSTAT_WCINC                                                         */
47460   ADC_INTSTAT_WCINC_WCINCINT           = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
47461   ADC_INTSTAT_WCINC_WCINCNOINT         = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
47462 } ADC_INTSTAT_WCINC_Enum;
47463 
47464 /* ===============================================  ADC INTSTAT WCEXC [4..4]  ================================================ */
47465 typedef enum {                                  /*!< ADC_INTSTAT_WCEXC                                                         */
47466   ADC_INTSTAT_WCEXC_WCEXCINT           = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
47467   ADC_INTSTAT_WCEXC_WCEXCNOINT         = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
47468 } ADC_INTSTAT_WCEXC_Enum;
47469 
47470 /* ==============================================  ADC INTSTAT FIFOOVR2 [3..3]  ============================================== */
47471 typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR2                                                      */
47472   ADC_INTSTAT_FIFOOVR2_FIFOFULLINT     = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
47473   ADC_INTSTAT_FIFOOVR2_FIFOFULLNOINT   = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
47474 } ADC_INTSTAT_FIFOOVR2_Enum;
47475 
47476 /* ==============================================  ADC INTSTAT FIFOOVR1 [2..2]  ============================================== */
47477 typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR1                                                      */
47478   ADC_INTSTAT_FIFOOVR1_FIFO75INT       = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
47479   ADC_INTSTAT_FIFOOVR1_FIFO75NOINT     = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
47480 } ADC_INTSTAT_FIFOOVR1_Enum;
47481 
47482 /* ===============================================  ADC INTSTAT SCNCMP [1..1]  =============================================== */
47483 typedef enum {                                  /*!< ADC_INTSTAT_SCNCMP                                                        */
47484   ADC_INTSTAT_SCNCMP_SCNCMPINT         = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
47485   ADC_INTSTAT_SCNCMP_SCNCMPNOINT       = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
47486 } ADC_INTSTAT_SCNCMP_Enum;
47487 
47488 /* ===============================================  ADC INTSTAT CNVCMP [0..0]  =============================================== */
47489 typedef enum {                                  /*!< ADC_INTSTAT_CNVCMP                                                        */
47490   ADC_INTSTAT_CNVCMP_CNVCMPINT         = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
47491   ADC_INTSTAT_CNVCMP_CNVCMPNOINT       = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
47492 } ADC_INTSTAT_CNVCMP_Enum;
47493 
47494 /* ========================================================  INTCLR  ========================================================= */
47495 /* ===============================================  ADC INTCLR SATCB [11..11]  =============================================== */
47496 typedef enum {                                  /*!< ADC_INTCLR_SATCB                                                          */
47497   ADC_INTCLR_SATCB_SATCBINT            = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
47498                                                      occurred on either slot 2 or 3 (channel B)                                */
47499   ADC_INTCLR_SATCB_NONSATCBINT         = 0,     /*!< NONSATCBINT : No-Saturation                                               */
47500 } ADC_INTCLR_SATCB_Enum;
47501 
47502 /* ===============================================  ADC INTCLR SATCA [10..10]  =============================================== */
47503 typedef enum {                                  /*!< ADC_INTCLR_SATCA                                                          */
47504   ADC_INTCLR_SATCA_SATCAINT            = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
47505                                                      occurred on either slot 0 or 1 (channel A)                                */
47506   ADC_INTCLR_SATCA_NONSATCAINT         = 0,     /*!< NONSATCAINT : No Saturation                                               */
47507 } ADC_INTCLR_SATCA_Enum;
47508 
47509 /* ================================================  ADC INTCLR ZXCB [9..9]  ================================================= */
47510 typedef enum {                                  /*!< ADC_INTCLR_ZXCB                                                           */
47511   ADC_INTCLR_ZXCB_ZXCBINT              = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
47512                                                      occurred on either slot 2 or 3 (channel B)                                */
47513   ADC_INTCLR_ZXCB_NONZXCBINT           = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
47514 } ADC_INTCLR_ZXCB_Enum;
47515 
47516 /* ================================================  ADC INTCLR ZXCA [8..8]  ================================================= */
47517 typedef enum {                                  /*!< ADC_INTCLR_ZXCA                                                           */
47518   ADC_INTCLR_ZXCA_ZXCAINT              = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
47519                                                      occurred on either slot 0 or 1 (channel A)                                */
47520   ADC_INTCLR_ZXCA_NONZXCAINT           = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
47521 } ADC_INTCLR_ZXCA_Enum;
47522 
47523 /* ================================================  ADC INTCLR DERR [7..7]  ================================================= */
47524 typedef enum {                                  /*!< ADC_INTCLR_DERR                                                           */
47525   ADC_INTCLR_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
47526   ADC_INTCLR_DERR_NODMAERROR           = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
47527 } ADC_INTCLR_DERR_Enum;
47528 
47529 /* ================================================  ADC INTCLR DCMP [6..6]  ================================================= */
47530 typedef enum {                                  /*!< ADC_INTCLR_DCMP                                                           */
47531   ADC_INTCLR_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
47532   ADC_INTCLR_DCMP_DMAON                = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
47533 } ADC_INTCLR_DCMP_Enum;
47534 
47535 /* ================================================  ADC INTCLR WCINC [5..5]  ================================================ */
47536 typedef enum {                                  /*!< ADC_INTCLR_WCINC                                                          */
47537   ADC_INTCLR_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
47538   ADC_INTCLR_WCINC_WCINCNOINT          = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
47539 } ADC_INTCLR_WCINC_Enum;
47540 
47541 /* ================================================  ADC INTCLR WCEXC [4..4]  ================================================ */
47542 typedef enum {                                  /*!< ADC_INTCLR_WCEXC                                                          */
47543   ADC_INTCLR_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
47544   ADC_INTCLR_WCEXC_WCEXCNOINT          = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
47545 } ADC_INTCLR_WCEXC_Enum;
47546 
47547 /* ==============================================  ADC INTCLR FIFOOVR2 [3..3]  =============================================== */
47548 typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR2                                                       */
47549   ADC_INTCLR_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
47550   ADC_INTCLR_FIFOOVR2_FIFOFULLNOINT    = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
47551 } ADC_INTCLR_FIFOOVR2_Enum;
47552 
47553 /* ==============================================  ADC INTCLR FIFOOVR1 [2..2]  =============================================== */
47554 typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR1                                                       */
47555   ADC_INTCLR_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
47556   ADC_INTCLR_FIFOOVR1_FIFO75NOINT      = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
47557 } ADC_INTCLR_FIFOOVR1_Enum;
47558 
47559 /* ===============================================  ADC INTCLR SCNCMP [1..1]  ================================================ */
47560 typedef enum {                                  /*!< ADC_INTCLR_SCNCMP                                                         */
47561   ADC_INTCLR_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
47562   ADC_INTCLR_SCNCMP_SCNCMPNOINT        = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
47563 } ADC_INTCLR_SCNCMP_Enum;
47564 
47565 /* ===============================================  ADC INTCLR CNVCMP [0..0]  ================================================ */
47566 typedef enum {                                  /*!< ADC_INTCLR_CNVCMP                                                         */
47567   ADC_INTCLR_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
47568   ADC_INTCLR_CNVCMP_CNVCMPNOINT        = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
47569 } ADC_INTCLR_CNVCMP_Enum;
47570 
47571 /* ========================================================  INTSET  ========================================================= */
47572 /* ===============================================  ADC INTSET SATCB [11..11]  =============================================== */
47573 typedef enum {                                  /*!< ADC_INTSET_SATCB                                                          */
47574   ADC_INTSET_SATCB_SATCBINT            = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
47575                                                      occurred on either slot 2 or 3 (channel B)                                */
47576   ADC_INTSET_SATCB_NONSATCBINT         = 0,     /*!< NONSATCBINT : No-Saturation                                               */
47577 } ADC_INTSET_SATCB_Enum;
47578 
47579 /* ===============================================  ADC INTSET SATCA [10..10]  =============================================== */
47580 typedef enum {                                  /*!< ADC_INTSET_SATCA                                                          */
47581   ADC_INTSET_SATCA_SATCAINT            = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
47582                                                      occurred on either slot 0 or 1 (channel A)                                */
47583   ADC_INTSET_SATCA_NONSATCAINT         = 0,     /*!< NONSATCAINT : No Saturation                                               */
47584 } ADC_INTSET_SATCA_Enum;
47585 
47586 /* ================================================  ADC INTSET ZXCB [9..9]  ================================================= */
47587 typedef enum {                                  /*!< ADC_INTSET_ZXCB                                                           */
47588   ADC_INTSET_ZXCB_ZXCBINT              = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
47589                                                      occurred on either slot 2 or 3 (channel B)                                */
47590   ADC_INTSET_ZXCB_NONZXCBINT           = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
47591 } ADC_INTSET_ZXCB_Enum;
47592 
47593 /* ================================================  ADC INTSET ZXCA [8..8]  ================================================= */
47594 typedef enum {                                  /*!< ADC_INTSET_ZXCA                                                           */
47595   ADC_INTSET_ZXCA_ZXCAINT              = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
47596                                                      occurred on either slot 0 or 1 (channel A)                                */
47597   ADC_INTSET_ZXCA_NONZXCAINT           = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
47598 } ADC_INTSET_ZXCA_Enum;
47599 
47600 /* ================================================  ADC INTSET DERR [7..7]  ================================================= */
47601 typedef enum {                                  /*!< ADC_INTSET_DERR                                                           */
47602   ADC_INTSET_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
47603   ADC_INTSET_DERR_NODMAERROR           = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
47604 } ADC_INTSET_DERR_Enum;
47605 
47606 /* ================================================  ADC INTSET DCMP [6..6]  ================================================= */
47607 typedef enum {                                  /*!< ADC_INTSET_DCMP                                                           */
47608   ADC_INTSET_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
47609   ADC_INTSET_DCMP_DMAON                = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
47610 } ADC_INTSET_DCMP_Enum;
47611 
47612 /* ================================================  ADC INTSET WCINC [5..5]  ================================================ */
47613 typedef enum {                                  /*!< ADC_INTSET_WCINC                                                          */
47614   ADC_INTSET_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
47615   ADC_INTSET_WCINC_WCINCNOINT          = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
47616 } ADC_INTSET_WCINC_Enum;
47617 
47618 /* ================================================  ADC INTSET WCEXC [4..4]  ================================================ */
47619 typedef enum {                                  /*!< ADC_INTSET_WCEXC                                                          */
47620   ADC_INTSET_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
47621   ADC_INTSET_WCEXC_WCEXCNOINT          = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
47622 } ADC_INTSET_WCEXC_Enum;
47623 
47624 /* ==============================================  ADC INTSET FIFOOVR2 [3..3]  =============================================== */
47625 typedef enum {                                  /*!< ADC_INTSET_FIFOOVR2                                                       */
47626   ADC_INTSET_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
47627   ADC_INTSET_FIFOOVR2_FIFOFULLNOINT    = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
47628 } ADC_INTSET_FIFOOVR2_Enum;
47629 
47630 /* ==============================================  ADC INTSET FIFOOVR1 [2..2]  =============================================== */
47631 typedef enum {                                  /*!< ADC_INTSET_FIFOOVR1                                                       */
47632   ADC_INTSET_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
47633   ADC_INTSET_FIFOOVR1_FIFO75NOINT      = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
47634 } ADC_INTSET_FIFOOVR1_Enum;
47635 
47636 /* ===============================================  ADC INTSET SCNCMP [1..1]  ================================================ */
47637 typedef enum {                                  /*!< ADC_INTSET_SCNCMP                                                         */
47638   ADC_INTSET_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
47639   ADC_INTSET_SCNCMP_SCNCMPNOINT        = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
47640 } ADC_INTSET_SCNCMP_Enum;
47641 
47642 /* ===============================================  ADC INTSET CNVCMP [0..0]  ================================================ */
47643 typedef enum {                                  /*!< ADC_INTSET_CNVCMP                                                         */
47644   ADC_INTSET_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
47645   ADC_INTSET_CNVCMP_CNVCMPNOINT        = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
47646 } ADC_INTSET_CNVCMP_Enum;
47647 
47648 /* =======================================================  DMATRIGEN  ======================================================= */
47649 /* ======================================================  DMATRIGSTAT  ====================================================== */
47650 /* ========================================================  DMACFG  ========================================================= */
47651 /* ==============================================  ADC DMACFG DMAMSK [17..17]  =============================================== */
47652 typedef enum {                                  /*!< ADC_DMACFG_DMAMSK                                                         */
47653   ADC_DMACFG_DMAMSK_DIS                = 0,     /*!< DIS : FIFO Contents are copied directly to memory without modification.   */
47654   ADC_DMACFG_DMAMSK_EN                 = 1,     /*!< EN : Only the FIFODATA contents are copied to memory on DMA
47655                                                      transfers. The SLOTNUM and FIFOCNT contents are cleared
47656                                                      to zero.                                                                  */
47657 } ADC_DMACFG_DMAMSK_Enum;
47658 
47659 /* ==============================================  ADC DMACFG DMADYNPRI [9..9]  ============================================== */
47660 typedef enum {                                  /*!< ADC_DMACFG_DMADYNPRI                                                      */
47661   ADC_DMACFG_DMADYNPRI_DIS             = 0,     /*!< DIS : Disable dynamic priority (use DMAPRI setting only)                  */
47662   ADC_DMACFG_DMADYNPRI_EN              = 1,     /*!< EN : Enable dynamic priority                                              */
47663 } ADC_DMACFG_DMADYNPRI_Enum;
47664 
47665 /* ===============================================  ADC DMACFG DMAPRI [8..8]  ================================================ */
47666 typedef enum {                                  /*!< ADC_DMACFG_DMAPRI                                                         */
47667   ADC_DMACFG_DMAPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
47668   ADC_DMACFG_DMAPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
47669 } ADC_DMACFG_DMAPRI_Enum;
47670 
47671 /* ===============================================  ADC DMACFG DMADIR [2..2]  ================================================ */
47672 typedef enum {                                  /*!< ADC_DMACFG_DMADIR                                                         */
47673   ADC_DMACFG_DMADIR_P2M                = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
47674   ADC_DMACFG_DMADIR_M2P                = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
47675 } ADC_DMACFG_DMADIR_Enum;
47676 
47677 /* ================================================  ADC DMACFG DMAEN [0..0]  ================================================ */
47678 typedef enum {                                  /*!< ADC_DMACFG_DMAEN                                                          */
47679   ADC_DMACFG_DMAEN_DIS                 = 0,     /*!< DIS : Disable DMA Function                                                */
47680   ADC_DMACFG_DMAEN_EN                  = 1,     /*!< EN : Enable DMA Function                                                  */
47681 } ADC_DMACFG_DMAEN_Enum;
47682 
47683 /* ======================================================  DMATOTCOUNT  ====================================================== */
47684 /* ======================================================  DMATARGADDR  ====================================================== */
47685 /* ========================================================  DMASTAT  ======================================================== */
47686 
47687 
47688 /* =========================================================================================================================== */
47689 /* ================                                          APBDMA                                           ================ */
47690 /* =========================================================================================================================== */
47691 
47692 /* ========================================================  BBVALUE  ======================================================== */
47693 /* ======================================================  BBSETCLEAR  ======================================================= */
47694 /* ========================================================  BBINPUT  ======================================================== */
47695 /* =======================================================  DEBUGDATA  ======================================================= */
47696 /* =========================================================  DEBUG  ========================================================= */
47697 /* ==============================================  APBDMA DEBUG DEBUGEN [0..3]  ============================================== */
47698 typedef enum {                                  /*!< APBDMA_DEBUG_DEBUGEN                                                      */
47699   APBDMA_DEBUG_DEBUGEN_OFF             = 0,     /*!< OFF : Debug Disabled                                                      */
47700   APBDMA_DEBUG_DEBUGEN_ARB             = 1,     /*!< ARB : Debug Arb values                                                    */
47701 } APBDMA_DEBUG_DEBUGEN_Enum;
47702 
47703 
47704 
47705 /* =========================================================================================================================== */
47706 /* ================                                          AUDADC                                           ================ */
47707 /* =========================================================================================================================== */
47708 
47709 /* ==========================================================  CFG  ========================================================== */
47710 /* ==============================================  AUDADC CFG CLKSEL [24..25]  =============================================== */
47711 typedef enum {                                  /*!< AUDADC_CFG_CLKSEL                                                         */
47712   AUDADC_CFG_CLKSEL_OFF                = 0,     /*!< OFF : Off mode. The HFRC, HFRC2, or high frequency XTAL clock
47713                                                      must be selected for the AUDADC to function. The AUDADC
47714                                                      controller automatically shuts off the clock in its low
47715                                                      power modes. When setting ADCEN to '0', the CLKSEL should
47716                                                      remain set to one of the two clock selects for proper power
47717                                                      down sequencing.                                                          */
47718   AUDADC_CFG_CLKSEL_HFRC_48MHz         = 1,     /*!< HFRC_48MHz : HFRC Clock                                                   */
47719   AUDADC_CFG_CLKSEL_XTALHS_24MHz       = 2,     /*!< XTALHS_24MHz : High frequency XTAL (nominally 24.567 MHz, but
47720                                                      can vary depending on which XTAL is selected)                             */
47721   AUDADC_CFG_CLKSEL_HFRC2_48MHz        = 3,     /*!< HFRC2_48MHz : HFRC2 Clock                                                 */
47722 } AUDADC_CFG_CLKSEL_Enum;
47723 
47724 /* ============================================  AUDADC CFG RPTTRIGSEL [20..20]  ============================================= */
47725 typedef enum {                                  /*!< AUDADC_CFG_RPTTRIGSEL                                                     */
47726   AUDADC_CFG_RPTTRIGSEL_TMR            = 0,     /*!< TMR : Trigger from on-chip timer.                                         */
47727   AUDADC_CFG_RPTTRIGSEL_INT            = 1,     /*!< INT : Trigger from AUDADC-internal timer.                                 */
47728 } AUDADC_CFG_RPTTRIGSEL_Enum;
47729 
47730 /* ==============================================  AUDADC CFG TRIGPOL [19..19]  ============================================== */
47731 typedef enum {                                  /*!< AUDADC_CFG_TRIGPOL                                                        */
47732   AUDADC_CFG_TRIGPOL_RISING_EDGE       = 0,     /*!< RISING_EDGE : Trigger on rising edge.                                     */
47733   AUDADC_CFG_TRIGPOL_FALLING_EDGE      = 1,     /*!< FALLING_EDGE : Trigger on falling edge.                                   */
47734 } AUDADC_CFG_TRIGPOL_Enum;
47735 
47736 /* ==============================================  AUDADC CFG TRIGSEL [16..18]  ============================================== */
47737 typedef enum {                                  /*!< AUDADC_CFG_TRIGSEL                                                        */
47738   AUDADC_CFG_TRIGSEL_EXT0              = 0,     /*!< EXT0 : Off chip External Trigger0 (ADC_ET0)                               */
47739   AUDADC_CFG_TRIGSEL_EXT1              = 1,     /*!< EXT1 : Off chip External Trigger1 (ADC_ET1)                               */
47740   AUDADC_CFG_TRIGSEL_EXT2              = 2,     /*!< EXT2 : Off chip External Trigger2 (ADC_ET2)                               */
47741   AUDADC_CFG_TRIGSEL_EXT3              = 3,     /*!< EXT3 : Off chip External Trigger3 (ADC_ET3)                               */
47742   AUDADC_CFG_TRIGSEL_VCOMP             = 4,     /*!< VCOMP : Voltage Comparator Output                                         */
47743   AUDADC_CFG_TRIGSEL_SWT               = 7,     /*!< SWT : Software Trigger                                                    */
47744 } AUDADC_CFG_TRIGSEL_Enum;
47745 
47746 /* =============================================  AUDADC CFG SAMPMODE [13..13]  ============================================== */
47747 typedef enum {                                  /*!< AUDADC_CFG_SAMPMODE                                                       */
47748   AUDADC_CFG_SAMPMODE_LP               = 0,     /*!< LP : Max of 2 low-gain PGA channels configured on slots 0 and
47749                                                      2. In this mode, slots 1 and 3, if enabled, will still
47750                                                      consume time but not perform conversions.                                 */
47751   AUDADC_CFG_SAMPMODE_MED              = 1,     /*!< MED : Max of 2 low-gain and 2 high-gain PGA channels. In this
47752                                                      mode, conversions will be performed on all enabled slots
47753                                                      0 through 3.                                                              */
47754 } AUDADC_CFG_SAMPMODE_Enum;
47755 
47756 /* =============================================  AUDADC CFG DFIFORDEN [12..12]  ============================================= */
47757 typedef enum {                                  /*!< AUDADC_CFG_DFIFORDEN                                                      */
47758   AUDADC_CFG_DFIFORDEN_DIS             = 0,     /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register
47759                                                      will not POP an entry off the FIFO.                                       */
47760   AUDADC_CFG_DFIFORDEN_EN              = 1,     /*!< EN : Reads to the FIFOPR registger will automatically pop an
47761                                                      entry off the FIFO.                                                       */
47762 } AUDADC_CFG_DFIFORDEN_Enum;
47763 
47764 /* ===============================================  AUDADC CFG CKMODE [4..4]  ================================================ */
47765 typedef enum {                                  /*!< AUDADC_CFG_CKMODE                                                         */
47766   AUDADC_CFG_CKMODE_LPCKMODE           = 0,     /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set
47767                                                      LPCKMODE to 0x1 while configuring the AUDADC.                             */
47768   AUDADC_CFG_CKMODE_LLCKMODE           = 1,     /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk
47769                                                      will remain on while in functioning in LPMODE0.                           */
47770 } AUDADC_CFG_CKMODE_Enum;
47771 
47772 /* ===============================================  AUDADC CFG LPMODE [3..3]  ================================================ */
47773 typedef enum {                                  /*!< AUDADC_CFG_LPMODE                                                         */
47774   AUDADC_CFG_LPMODE_MODE0              = 0,     /*!< MODE0 : Low Power Mode 0. Leaves the AUDADC fully powered between
47775                                                      scans with minimum latency between a trigger event and
47776                                                      sample data collection.                                                   */
47777   AUDADC_CFG_LPMODE_MODE1              = 1,     /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks
47778                                                      associated with the AUDADC until the next trigger event.
47779                                                      Between scans, the reference buffer requires up to 50us
47780                                                      of delay from a scan trigger event before the conversion
47781                                                      will commence while operating in this mode.                               */
47782 } AUDADC_CFG_LPMODE_Enum;
47783 
47784 /* ================================================  AUDADC CFG RPTEN [2..2]  ================================================ */
47785 typedef enum {                                  /*!< AUDADC_CFG_RPTEN                                                          */
47786   AUDADC_CFG_RPTEN_SINGLE_SCAN         = 0,     /*!< SINGLE_SCAN : In Single Scan Mode, the AUDADC will complete
47787                                                      a single scan upon each trigger event.                                    */
47788   AUDADC_CFG_RPTEN_REPEATING_SCAN      = 1,     /*!< REPEATING_SCAN : In Repeating Scan Mode, the AUDADC will complete
47789                                                      its first scan upon the initial trigger event and all subsequent
47790                                                      scans will occur at regular intervals defined by the configuration
47791                                                      programmed for the CTTMRA3 timer or the AUDADC-internal
47792                                                      timer (see the RPTTRIGSEL field) until the timer is disabled
47793                                                      or the AUDADC is disabled. When disabling the AUDADC (setting
47794                                                      ADCEN to '0'), the RPTEN bit should be cleared.                           */
47795 } AUDADC_CFG_RPTEN_Enum;
47796 
47797 /* ================================================  AUDADC CFG ADCEN [0..0]  ================================================ */
47798 typedef enum {                                  /*!< AUDADC_CFG_ADCEN                                                          */
47799   AUDADC_CFG_ADCEN_DIS                 = 0,     /*!< DIS : Disable the AUDADC module.                                          */
47800   AUDADC_CFG_ADCEN_EN                  = 1,     /*!< EN : Enable the AUDADC module.                                            */
47801 } AUDADC_CFG_ADCEN_Enum;
47802 
47803 /* =========================================================  STAT  ========================================================== */
47804 /* ==============================================  AUDADC STAT PWDSTAT [0..0]  =============================================== */
47805 typedef enum {                                  /*!< AUDADC_STAT_PWDSTAT                                                       */
47806   AUDADC_STAT_PWDSTAT_ON               = 0,     /*!< ON : Powered on.                                                          */
47807   AUDADC_STAT_PWDSTAT_POWERED_DOWN     = 1,     /*!< POWERED_DOWN : AUDADC Low Power Mode 1.                                   */
47808 } AUDADC_STAT_PWDSTAT_Enum;
47809 
47810 /* ==========================================================  SWT  ========================================================== */
47811 /* =================================================  AUDADC SWT SWT [0..7]  ================================================= */
47812 typedef enum {                                  /*!< AUDADC_SWT_SWT                                                            */
47813   AUDADC_SWT_SWT_GEN_SW_TRIGGER        = 55,    /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger.         */
47814   AUDADC_SWT_SWT_NO_SW_TRIGGER         = 0,     /*!< NO_SW_TRIGGER : Default value.                                            */
47815 } AUDADC_SWT_SWT_Enum;
47816 
47817 /* ========================================================  SL0CFG  ========================================================= */
47818 /* =============================================  AUDADC SL0CFG ADSEL0 [24..26]  ============================================= */
47819 typedef enum {                                  /*!< AUDADC_SL0CFG_ADSEL0                                                      */
47820   AUDADC_SL0CFG_ADSEL0_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47821                                                      module for this slot.                                                     */
47822   AUDADC_SL0CFG_ADSEL0_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47823                                                      module for this slot.                                                     */
47824   AUDADC_SL0CFG_ADSEL0_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47825                                                      module for this slot.                                                     */
47826   AUDADC_SL0CFG_ADSEL0_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47827                                                      module for this slot.                                                     */
47828   AUDADC_SL0CFG_ADSEL0_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47829                                                      divide module for this slot.                                              */
47830   AUDADC_SL0CFG_ADSEL0_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47831                                                      divide module for this slot.                                              */
47832   AUDADC_SL0CFG_ADSEL0_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47833                                                      divide module for this slot.                                              */
47834   AUDADC_SL0CFG_ADSEL0_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47835                                                      divide module for this slot.                                              */
47836 } AUDADC_SL0CFG_ADSEL0_Enum;
47837 
47838 /* ============================================  AUDADC SL0CFG PRMODE0 [16..17]  ============================================= */
47839 typedef enum {                                  /*!< AUDADC_SL0CFG_PRMODE0                                                     */
47840   AUDADC_SL0CFG_PRMODE0_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47841   AUDADC_SL0CFG_PRMODE0_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47842   AUDADC_SL0CFG_PRMODE0_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47843   AUDADC_SL0CFG_PRMODE0_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47844 } AUDADC_SL0CFG_PRMODE0_Enum;
47845 
47846 /* =============================================  AUDADC SL0CFG CHSEL0 [8..11]  ============================================== */
47847 typedef enum {                                  /*!< AUDADC_SL0CFG_CHSEL0                                                      */
47848   AUDADC_SL0CFG_CHSEL0_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47849   AUDADC_SL0CFG_CHSEL0_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47850   AUDADC_SL0CFG_CHSEL0_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47851   AUDADC_SL0CFG_CHSEL0_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47852 } AUDADC_SL0CFG_CHSEL0_Enum;
47853 
47854 /* ==============================================  AUDADC SL0CFG WCEN0 [1..1]  =============================================== */
47855 typedef enum {                                  /*!< AUDADC_SL0CFG_WCEN0                                                       */
47856   AUDADC_SL0CFG_WCEN0_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 0.                              */
47857   AUDADC_SL0CFG_WCEN0_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 0.                            */
47858 } AUDADC_SL0CFG_WCEN0_Enum;
47859 
47860 /* ==============================================  AUDADC SL0CFG SLEN0 [0..0]  =============================================== */
47861 typedef enum {                                  /*!< AUDADC_SL0CFG_SLEN0                                                       */
47862   AUDADC_SL0CFG_SLEN0_SLEN             = 1,     /*!< SLEN : Enable slot 0 for AUDADC conversions.                              */
47863   AUDADC_SL0CFG_SLEN0_SLDIS            = 0,     /*!< SLDIS : Disable slot 0 for AUDADC conversions.                            */
47864 } AUDADC_SL0CFG_SLEN0_Enum;
47865 
47866 /* ========================================================  SL1CFG  ========================================================= */
47867 /* =============================================  AUDADC SL1CFG ADSEL1 [24..26]  ============================================= */
47868 typedef enum {                                  /*!< AUDADC_SL1CFG_ADSEL1                                                      */
47869   AUDADC_SL1CFG_ADSEL1_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47870                                                      module for this slot.                                                     */
47871   AUDADC_SL1CFG_ADSEL1_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47872                                                      module for this slot.                                                     */
47873   AUDADC_SL1CFG_ADSEL1_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47874                                                      module for this slot.                                                     */
47875   AUDADC_SL1CFG_ADSEL1_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47876                                                      module for this slot.                                                     */
47877   AUDADC_SL1CFG_ADSEL1_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47878                                                      divide module for this slot.                                              */
47879   AUDADC_SL1CFG_ADSEL1_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47880                                                      divide module for this slot.                                              */
47881   AUDADC_SL1CFG_ADSEL1_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47882                                                      divide module for this slot.                                              */
47883   AUDADC_SL1CFG_ADSEL1_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47884                                                      divide module for this slot.                                              */
47885 } AUDADC_SL1CFG_ADSEL1_Enum;
47886 
47887 /* ============================================  AUDADC SL1CFG PRMODE1 [16..17]  ============================================= */
47888 typedef enum {                                  /*!< AUDADC_SL1CFG_PRMODE1                                                     */
47889   AUDADC_SL1CFG_PRMODE1_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47890   AUDADC_SL1CFG_PRMODE1_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47891   AUDADC_SL1CFG_PRMODE1_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47892   AUDADC_SL1CFG_PRMODE1_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47893 } AUDADC_SL1CFG_PRMODE1_Enum;
47894 
47895 /* =============================================  AUDADC SL1CFG CHSEL1 [8..11]  ============================================== */
47896 typedef enum {                                  /*!< AUDADC_SL1CFG_CHSEL1                                                      */
47897   AUDADC_SL1CFG_CHSEL1_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47898   AUDADC_SL1CFG_CHSEL1_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47899   AUDADC_SL1CFG_CHSEL1_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47900   AUDADC_SL1CFG_CHSEL1_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47901 } AUDADC_SL1CFG_CHSEL1_Enum;
47902 
47903 /* ==============================================  AUDADC SL1CFG WCEN1 [1..1]  =============================================== */
47904 typedef enum {                                  /*!< AUDADC_SL1CFG_WCEN1                                                       */
47905   AUDADC_SL1CFG_WCEN1_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 1.                              */
47906   AUDADC_SL1CFG_WCEN1_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 1.                            */
47907 } AUDADC_SL1CFG_WCEN1_Enum;
47908 
47909 /* ==============================================  AUDADC SL1CFG SLEN1 [0..0]  =============================================== */
47910 typedef enum {                                  /*!< AUDADC_SL1CFG_SLEN1                                                       */
47911   AUDADC_SL1CFG_SLEN1_SLEN             = 1,     /*!< SLEN : Enable slot 1 for AUDADC conversions.                              */
47912   AUDADC_SL1CFG_SLEN1_SLDIS            = 0,     /*!< SLDIS : Disable slot 1 for AUDADC conversions.                            */
47913 } AUDADC_SL1CFG_SLEN1_Enum;
47914 
47915 /* ========================================================  SL2CFG  ========================================================= */
47916 /* =============================================  AUDADC SL2CFG ADSEL2 [24..26]  ============================================= */
47917 typedef enum {                                  /*!< AUDADC_SL2CFG_ADSEL2                                                      */
47918   AUDADC_SL2CFG_ADSEL2_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47919                                                      module for this slot.                                                     */
47920   AUDADC_SL2CFG_ADSEL2_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47921                                                      module for this slot.                                                     */
47922   AUDADC_SL2CFG_ADSEL2_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47923                                                      module for this slot.                                                     */
47924   AUDADC_SL2CFG_ADSEL2_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47925                                                      module for this slot.                                                     */
47926   AUDADC_SL2CFG_ADSEL2_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47927                                                      divide module for this slot.                                              */
47928   AUDADC_SL2CFG_ADSEL2_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47929                                                      divide module for this slot.                                              */
47930   AUDADC_SL2CFG_ADSEL2_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47931                                                      divide module for this slot.                                              */
47932   AUDADC_SL2CFG_ADSEL2_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47933                                                      divide module for this slot.                                              */
47934 } AUDADC_SL2CFG_ADSEL2_Enum;
47935 
47936 /* ============================================  AUDADC SL2CFG PRMODE2 [16..17]  ============================================= */
47937 typedef enum {                                  /*!< AUDADC_SL2CFG_PRMODE2                                                     */
47938   AUDADC_SL2CFG_PRMODE2_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47939   AUDADC_SL2CFG_PRMODE2_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47940   AUDADC_SL2CFG_PRMODE2_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47941   AUDADC_SL2CFG_PRMODE2_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47942 } AUDADC_SL2CFG_PRMODE2_Enum;
47943 
47944 /* =============================================  AUDADC SL2CFG CHSEL2 [8..11]  ============================================== */
47945 typedef enum {                                  /*!< AUDADC_SL2CFG_CHSEL2                                                      */
47946   AUDADC_SL2CFG_CHSEL2_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47947   AUDADC_SL2CFG_CHSEL2_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47948   AUDADC_SL2CFG_CHSEL2_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47949   AUDADC_SL2CFG_CHSEL2_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47950 } AUDADC_SL2CFG_CHSEL2_Enum;
47951 
47952 /* ==============================================  AUDADC SL2CFG WCEN2 [1..1]  =============================================== */
47953 typedef enum {                                  /*!< AUDADC_SL2CFG_WCEN2                                                       */
47954   AUDADC_SL2CFG_WCEN2_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 2.                              */
47955   AUDADC_SL2CFG_WCEN2_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 2.                            */
47956 } AUDADC_SL2CFG_WCEN2_Enum;
47957 
47958 /* ==============================================  AUDADC SL2CFG SLEN2 [0..0]  =============================================== */
47959 typedef enum {                                  /*!< AUDADC_SL2CFG_SLEN2                                                       */
47960   AUDADC_SL2CFG_SLEN2_SLEN             = 1,     /*!< SLEN : Enable slot 2 for AUDADC conversions.                              */
47961   AUDADC_SL2CFG_SLEN2_SLDIS            = 0,     /*!< SLDIS : Disable slot 2 for AUDADC conversions.                            */
47962 } AUDADC_SL2CFG_SLEN2_Enum;
47963 
47964 /* ========================================================  SL3CFG  ========================================================= */
47965 /* =============================================  AUDADC SL3CFG ADSEL3 [24..26]  ============================================= */
47966 typedef enum {                                  /*!< AUDADC_SL3CFG_ADSEL3                                                      */
47967   AUDADC_SL3CFG_ADSEL3_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
47968                                                      module for this slot.                                                     */
47969   AUDADC_SL3CFG_ADSEL3_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
47970                                                      module for this slot.                                                     */
47971   AUDADC_SL3CFG_ADSEL3_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
47972                                                      module for this slot.                                                     */
47973   AUDADC_SL3CFG_ADSEL3_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
47974                                                      module for this slot.                                                     */
47975   AUDADC_SL3CFG_ADSEL3_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
47976                                                      divide module for this slot.                                              */
47977   AUDADC_SL3CFG_ADSEL3_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
47978                                                      divide module for this slot.                                              */
47979   AUDADC_SL3CFG_ADSEL3_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
47980                                                      divide module for this slot.                                              */
47981   AUDADC_SL3CFG_ADSEL3_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
47982                                                      divide module for this slot.                                              */
47983 } AUDADC_SL3CFG_ADSEL3_Enum;
47984 
47985 /* ============================================  AUDADC SL3CFG PRMODE3 [16..17]  ============================================= */
47986 typedef enum {                                  /*!< AUDADC_SL3CFG_PRMODE3                                                     */
47987   AUDADC_SL3CFG_PRMODE3_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
47988   AUDADC_SL3CFG_PRMODE3_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
47989   AUDADC_SL3CFG_PRMODE3_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
47990   AUDADC_SL3CFG_PRMODE3_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
47991 } AUDADC_SL3CFG_PRMODE3_Enum;
47992 
47993 /* =============================================  AUDADC SL3CFG CHSEL3 [8..11]  ============================================== */
47994 typedef enum {                                  /*!< AUDADC_SL3CFG_CHSEL3                                                      */
47995   AUDADC_SL3CFG_CHSEL3_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
47996   AUDADC_SL3CFG_CHSEL3_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
47997   AUDADC_SL3CFG_CHSEL3_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
47998   AUDADC_SL3CFG_CHSEL3_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
47999 } AUDADC_SL3CFG_CHSEL3_Enum;
48000 
48001 /* ==============================================  AUDADC SL3CFG WCEN3 [1..1]  =============================================== */
48002 typedef enum {                                  /*!< AUDADC_SL3CFG_WCEN3                                                       */
48003   AUDADC_SL3CFG_WCEN3_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 3.                              */
48004   AUDADC_SL3CFG_WCEN3_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 3.                            */
48005 } AUDADC_SL3CFG_WCEN3_Enum;
48006 
48007 /* ==============================================  AUDADC SL3CFG SLEN3 [0..0]  =============================================== */
48008 typedef enum {                                  /*!< AUDADC_SL3CFG_SLEN3                                                       */
48009   AUDADC_SL3CFG_SLEN3_SLEN             = 1,     /*!< SLEN : Enable slot 3 for AUDADC conversions.                              */
48010   AUDADC_SL3CFG_SLEN3_SLDIS            = 0,     /*!< SLDIS : Disable slot 3 for AUDADC conversions.                            */
48011 } AUDADC_SL3CFG_SLEN3_Enum;
48012 
48013 /* ========================================================  SL4CFG  ========================================================= */
48014 /* =============================================  AUDADC SL4CFG ADSEL4 [24..26]  ============================================= */
48015 typedef enum {                                  /*!< AUDADC_SL4CFG_ADSEL4                                                      */
48016   AUDADC_SL4CFG_ADSEL4_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
48017                                                      module for this slot.                                                     */
48018   AUDADC_SL4CFG_ADSEL4_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
48019                                                      module for this slot.                                                     */
48020   AUDADC_SL4CFG_ADSEL4_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
48021                                                      module for this slot.                                                     */
48022   AUDADC_SL4CFG_ADSEL4_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
48023                                                      module for this slot.                                                     */
48024   AUDADC_SL4CFG_ADSEL4_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
48025                                                      divide module for this slot.                                              */
48026   AUDADC_SL4CFG_ADSEL4_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
48027                                                      divide module for this slot.                                              */
48028   AUDADC_SL4CFG_ADSEL4_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
48029                                                      divide module for this slot.                                              */
48030   AUDADC_SL4CFG_ADSEL4_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
48031                                                      divide module for this slot.                                              */
48032 } AUDADC_SL4CFG_ADSEL4_Enum;
48033 
48034 /* ============================================  AUDADC SL4CFG PRMODE4 [16..17]  ============================================= */
48035 typedef enum {                                  /*!< AUDADC_SL4CFG_PRMODE4                                                     */
48036   AUDADC_SL4CFG_PRMODE4_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
48037   AUDADC_SL4CFG_PRMODE4_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
48038   AUDADC_SL4CFG_PRMODE4_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
48039   AUDADC_SL4CFG_PRMODE4_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
48040 } AUDADC_SL4CFG_PRMODE4_Enum;
48041 
48042 /* =============================================  AUDADC SL4CFG CHSEL4 [8..11]  ============================================== */
48043 typedef enum {                                  /*!< AUDADC_SL4CFG_CHSEL4                                                      */
48044   AUDADC_SL4CFG_CHSEL4_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
48045   AUDADC_SL4CFG_CHSEL4_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
48046   AUDADC_SL4CFG_CHSEL4_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
48047   AUDADC_SL4CFG_CHSEL4_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
48048 } AUDADC_SL4CFG_CHSEL4_Enum;
48049 
48050 /* ==============================================  AUDADC SL4CFG WCEN4 [1..1]  =============================================== */
48051 typedef enum {                                  /*!< AUDADC_SL4CFG_WCEN4                                                       */
48052   AUDADC_SL4CFG_WCEN4_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 4.                              */
48053   AUDADC_SL4CFG_WCEN4_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 4.                            */
48054 } AUDADC_SL4CFG_WCEN4_Enum;
48055 
48056 /* ==============================================  AUDADC SL4CFG SLEN4 [0..0]  =============================================== */
48057 typedef enum {                                  /*!< AUDADC_SL4CFG_SLEN4                                                       */
48058   AUDADC_SL4CFG_SLEN4_SLEN             = 1,     /*!< SLEN : Enable slot 4 for AUDADC conversions.                              */
48059   AUDADC_SL4CFG_SLEN4_SLDIS            = 0,     /*!< SLDIS : Disable slot 4 for AUDADC conversions.                            */
48060 } AUDADC_SL4CFG_SLEN4_Enum;
48061 
48062 /* ========================================================  SL5CFG  ========================================================= */
48063 /* =============================================  AUDADC SL5CFG ADSEL5 [24..26]  ============================================= */
48064 typedef enum {                                  /*!< AUDADC_SL5CFG_ADSEL5                                                      */
48065   AUDADC_SL5CFG_ADSEL5_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
48066                                                      module for this slot.                                                     */
48067   AUDADC_SL5CFG_ADSEL5_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
48068                                                      module for this slot.                                                     */
48069   AUDADC_SL5CFG_ADSEL5_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
48070                                                      module for this slot.                                                     */
48071   AUDADC_SL5CFG_ADSEL5_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
48072                                                      module for this slot.                                                     */
48073   AUDADC_SL5CFG_ADSEL5_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
48074                                                      divide module for this slot.                                              */
48075   AUDADC_SL5CFG_ADSEL5_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
48076                                                      divide module for this slot.                                              */
48077   AUDADC_SL5CFG_ADSEL5_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
48078                                                      divide module for this slot.                                              */
48079   AUDADC_SL5CFG_ADSEL5_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
48080                                                      divide module for this slot.                                              */
48081 } AUDADC_SL5CFG_ADSEL5_Enum;
48082 
48083 /* ============================================  AUDADC SL5CFG PRMODE5 [16..17]  ============================================= */
48084 typedef enum {                                  /*!< AUDADC_SL5CFG_PRMODE5                                                     */
48085   AUDADC_SL5CFG_PRMODE5_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
48086   AUDADC_SL5CFG_PRMODE5_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
48087   AUDADC_SL5CFG_PRMODE5_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
48088   AUDADC_SL5CFG_PRMODE5_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
48089 } AUDADC_SL5CFG_PRMODE5_Enum;
48090 
48091 /* =============================================  AUDADC SL5CFG CHSEL5 [8..11]  ============================================== */
48092 typedef enum {                                  /*!< AUDADC_SL5CFG_CHSEL5                                                      */
48093   AUDADC_SL5CFG_CHSEL5_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
48094   AUDADC_SL5CFG_CHSEL5_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
48095   AUDADC_SL5CFG_CHSEL5_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
48096   AUDADC_SL5CFG_CHSEL5_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
48097 } AUDADC_SL5CFG_CHSEL5_Enum;
48098 
48099 /* ==============================================  AUDADC SL5CFG WCEN5 [1..1]  =============================================== */
48100 typedef enum {                                  /*!< AUDADC_SL5CFG_WCEN5                                                       */
48101   AUDADC_SL5CFG_WCEN5_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 5.                              */
48102   AUDADC_SL5CFG_WCEN5_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 5.                            */
48103 } AUDADC_SL5CFG_WCEN5_Enum;
48104 
48105 /* ==============================================  AUDADC SL5CFG SLEN5 [0..0]  =============================================== */
48106 typedef enum {                                  /*!< AUDADC_SL5CFG_SLEN5                                                       */
48107   AUDADC_SL5CFG_SLEN5_SLEN             = 1,     /*!< SLEN : Enable slot 5 for AUDADC conversions.                              */
48108   AUDADC_SL5CFG_SLEN5_SLDIS            = 0,     /*!< SLDIS : Disable slot 5 for AUDADC conversions.                            */
48109 } AUDADC_SL5CFG_SLEN5_Enum;
48110 
48111 /* ========================================================  SL6CFG  ========================================================= */
48112 /* =============================================  AUDADC SL6CFG ADSEL6 [24..26]  ============================================= */
48113 typedef enum {                                  /*!< AUDADC_SL6CFG_ADSEL6                                                      */
48114   AUDADC_SL6CFG_ADSEL6_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
48115                                                      module for this slot.                                                     */
48116   AUDADC_SL6CFG_ADSEL6_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
48117                                                      module for this slot.                                                     */
48118   AUDADC_SL6CFG_ADSEL6_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
48119                                                      module for this slot.                                                     */
48120   AUDADC_SL6CFG_ADSEL6_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
48121                                                      module for this slot.                                                     */
48122   AUDADC_SL6CFG_ADSEL6_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
48123                                                      divide module for this slot.                                              */
48124   AUDADC_SL6CFG_ADSEL6_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
48125                                                      divide module for this slot.                                              */
48126   AUDADC_SL6CFG_ADSEL6_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
48127                                                      divide module for this slot.                                              */
48128   AUDADC_SL6CFG_ADSEL6_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
48129                                                      divide module for this slot.                                              */
48130 } AUDADC_SL6CFG_ADSEL6_Enum;
48131 
48132 /* ============================================  AUDADC SL6CFG PRMODE6 [16..17]  ============================================= */
48133 typedef enum {                                  /*!< AUDADC_SL6CFG_PRMODE6                                                     */
48134   AUDADC_SL6CFG_PRMODE6_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
48135   AUDADC_SL6CFG_PRMODE6_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
48136   AUDADC_SL6CFG_PRMODE6_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
48137   AUDADC_SL6CFG_PRMODE6_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
48138 } AUDADC_SL6CFG_PRMODE6_Enum;
48139 
48140 /* =============================================  AUDADC SL6CFG CHSEL6 [8..11]  ============================================== */
48141 typedef enum {                                  /*!< AUDADC_SL6CFG_CHSEL6                                                      */
48142   AUDADC_SL6CFG_CHSEL6_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
48143   AUDADC_SL6CFG_CHSEL6_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
48144   AUDADC_SL6CFG_CHSEL6_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
48145   AUDADC_SL6CFG_CHSEL6_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
48146 } AUDADC_SL6CFG_CHSEL6_Enum;
48147 
48148 /* ==============================================  AUDADC SL6CFG WCEN6 [1..1]  =============================================== */
48149 typedef enum {                                  /*!< AUDADC_SL6CFG_WCEN6                                                       */
48150   AUDADC_SL6CFG_WCEN6_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 6.                              */
48151   AUDADC_SL6CFG_WCEN6_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 6.                            */
48152 } AUDADC_SL6CFG_WCEN6_Enum;
48153 
48154 /* ==============================================  AUDADC SL6CFG SLEN6 [0..0]  =============================================== */
48155 typedef enum {                                  /*!< AUDADC_SL6CFG_SLEN6                                                       */
48156   AUDADC_SL6CFG_SLEN6_SLEN             = 1,     /*!< SLEN : Enable slot 6 for AUDADC conversions.                              */
48157   AUDADC_SL6CFG_SLEN6_SLDIS            = 0,     /*!< SLDIS : Disable slot 6 for AUDADC conversions.                            */
48158 } AUDADC_SL6CFG_SLEN6_Enum;
48159 
48160 /* ========================================================  SL7CFG  ========================================================= */
48161 /* =============================================  AUDADC SL7CFG ADSEL7 [24..26]  ============================================= */
48162 typedef enum {                                  /*!< AUDADC_SL7CFG_ADSEL7                                                      */
48163   AUDADC_SL7CFG_ADSEL7_AVG_1_MSRMT     = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
48164                                                      module for this slot.                                                     */
48165   AUDADC_SL7CFG_ADSEL7_AVG_2_MSRMTS    = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
48166                                                      module for this slot.                                                     */
48167   AUDADC_SL7CFG_ADSEL7_AVG_4_MSRMTS    = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
48168                                                      module for this slot.                                                     */
48169   AUDADC_SL7CFG_ADSEL7_AVG_8_MSRMT     = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
48170                                                      module for this slot.                                                     */
48171   AUDADC_SL7CFG_ADSEL7_AVG_16_MSRMTS   = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
48172                                                      divide module for this slot.                                              */
48173   AUDADC_SL7CFG_ADSEL7_AVG_32_MSRMTS   = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
48174                                                      divide module for this slot.                                              */
48175   AUDADC_SL7CFG_ADSEL7_AVG_64_MSRMTS   = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
48176                                                      divide module for this slot.                                              */
48177   AUDADC_SL7CFG_ADSEL7_AVG_128_MSRMTS  = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
48178                                                      divide module for this slot.                                              */
48179 } AUDADC_SL7CFG_ADSEL7_Enum;
48180 
48181 /* ============================================  AUDADC SL7CFG PRMODE7 [16..17]  ============================================= */
48182 typedef enum {                                  /*!< AUDADC_SL7CFG_PRMODE7                                                     */
48183   AUDADC_SL7CFG_PRMODE7_P12B0          = 0,     /*!< P12B0 : 12-bit precision mode                                             */
48184   AUDADC_SL7CFG_PRMODE7_P12B1          = 1,     /*!< P12B1 : 12-bit precision mode                                             */
48185   AUDADC_SL7CFG_PRMODE7_P10B           = 2,     /*!< P10B : 10-bit precision mode                                              */
48186   AUDADC_SL7CFG_PRMODE7_P8B            = 3,     /*!< P8B : 8-bit precision mode                                                */
48187 } AUDADC_SL7CFG_PRMODE7_Enum;
48188 
48189 /* =============================================  AUDADC SL7CFG CHSEL7 [8..11]  ============================================== */
48190 typedef enum {                                  /*!< AUDADC_SL7CFG_CHSEL7                                                      */
48191   AUDADC_SL7CFG_CHSEL7_SE0             = 0,     /*!< SE0 : PGA channel A0 output                                               */
48192   AUDADC_SL7CFG_CHSEL7_SE1             = 1,     /*!< SE1 : PGA channel A1 output                                               */
48193   AUDADC_SL7CFG_CHSEL7_SE2             = 2,     /*!< SE2 : PGA channel B0 output                                               */
48194   AUDADC_SL7CFG_CHSEL7_SE3             = 3,     /*!< SE3 : PGA channel B1 output                                               */
48195 } AUDADC_SL7CFG_CHSEL7_Enum;
48196 
48197 /* ==============================================  AUDADC SL7CFG WCEN7 [1..1]  =============================================== */
48198 typedef enum {                                  /*!< AUDADC_SL7CFG_WCEN7                                                       */
48199   AUDADC_SL7CFG_WCEN7_WCEN             = 1,     /*!< WCEN : Enable the window compare for slot 7.                              */
48200   AUDADC_SL7CFG_WCEN7_WCDIS            = 0,     /*!< WCDIS : Disable the window compare for slot 7.                            */
48201 } AUDADC_SL7CFG_WCEN7_Enum;
48202 
48203 /* ==============================================  AUDADC SL7CFG SLEN7 [0..0]  =============================================== */
48204 typedef enum {                                  /*!< AUDADC_SL7CFG_SLEN7                                                       */
48205   AUDADC_SL7CFG_SLEN7_SLEN             = 1,     /*!< SLEN : Enable slot 7 for AUDADC conversions.                              */
48206   AUDADC_SL7CFG_SLEN7_SLDIS            = 0,     /*!< SLDIS : Disable slot 7 for AUDADC conversions.                            */
48207 } AUDADC_SL7CFG_SLEN7_Enum;
48208 
48209 /* =========================================================  WULIM  ========================================================= */
48210 /* =========================================================  WLLIM  ========================================================= */
48211 /* ========================================================  SCWLIM  ========================================================= */
48212 /* =========================================================  FIFO  ========================================================== */
48213 /* ========================================================  FIFOPR  ========================================================= */
48214 /* =====================================================  INTTRIGTIMER  ====================================================== */
48215 /* =========================================  AUDADC INTTRIGTIMER TIMEREN [31..31]  ========================================== */
48216 typedef enum {                                  /*!< AUDADC_INTTRIGTIMER_TIMEREN                                               */
48217   AUDADC_INTTRIGTIMER_TIMEREN_DIS      = 0,     /*!< DIS : Disable the AUDADC-internal trigger timer.                          */
48218   AUDADC_INTTRIGTIMER_TIMEREN_EN       = 1,     /*!< EN : Enable the AUDADC-internal trigger timer.                            */
48219 } AUDADC_INTTRIGTIMER_TIMEREN_Enum;
48220 
48221 /* =======================================================  FIFOSTAT  ======================================================== */
48222 /* ======================================================  DATAOFFSET  ======================================================= */
48223 /* =========================================================  ZXCFG  ========================================================= */
48224 /* =========================================================  ZXLIM  ========================================================= */
48225 /* ========================================================  GAINCFG  ======================================================== */
48226 /* ===========================================  AUDADC GAINCFG UPDATEMODE [4..4]  ============================================ */
48227 typedef enum {                                  /*!< AUDADC_GAINCFG_UPDATEMODE                                                 */
48228   AUDADC_GAINCFG_UPDATEMODE_IMMED      = 0,     /*!< IMMED : Immediate update mode. Once gain is written, it is immediately
48229                                                      encoded and provided to the PGA.                                          */
48230   AUDADC_GAINCFG_UPDATEMODE_ZX         = 1,     /*!< ZX : Update gain only at detected zero crossing as configured
48231                                                      by ZX registers.                                                          */
48232 } AUDADC_GAINCFG_UPDATEMODE_Enum;
48233 
48234 /* =========================================================  GAIN  ========================================================== */
48235 /* ========================================================  SATCFG  ========================================================= */
48236 /* ========================================================  SATLIM  ========================================================= */
48237 /* ========================================================  SATMAX  ========================================================= */
48238 /* ========================================================  SATCLR  ========================================================= */
48239 /* =========================================================  INTEN  ========================================================= */
48240 /* ==============================================  AUDADC INTEN SATCB [11..11]  ============================================== */
48241 typedef enum {                                  /*!< AUDADC_INTEN_SATCB                                                        */
48242   AUDADC_INTEN_SATCB_SATCBINT          = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
48243                                                      occurred on either slot 2 or 3 (channel B)                                */
48244   AUDADC_INTEN_SATCB_NONSATCBINT       = 0,     /*!< NONSATCBINT : No-Saturation                                               */
48245 } AUDADC_INTEN_SATCB_Enum;
48246 
48247 /* ==============================================  AUDADC INTEN SATCA [10..10]  ============================================== */
48248 typedef enum {                                  /*!< AUDADC_INTEN_SATCA                                                        */
48249   AUDADC_INTEN_SATCA_SATCAINT          = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
48250                                                      occurred on either slot 0 or 1 (channel A)                                */
48251   AUDADC_INTEN_SATCA_NONSATCAINT       = 0,     /*!< NONSATCAINT : No Saturation                                               */
48252 } AUDADC_INTEN_SATCA_Enum;
48253 
48254 /* ===============================================  AUDADC INTEN ZXCB [9..9]  ================================================ */
48255 typedef enum {                                  /*!< AUDADC_INTEN_ZXCB                                                         */
48256   AUDADC_INTEN_ZXCB_ZXCBINT            = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
48257                                                      occurred on either slot 2 or 3 (channel B)                                */
48258   AUDADC_INTEN_ZXCB_NONZXCBINT         = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
48259 } AUDADC_INTEN_ZXCB_Enum;
48260 
48261 /* ===============================================  AUDADC INTEN ZXCA [8..8]  ================================================ */
48262 typedef enum {                                  /*!< AUDADC_INTEN_ZXCA                                                         */
48263   AUDADC_INTEN_ZXCA_ZXCAINT            = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
48264                                                      occurred on either slot 0 or 1 (channel A)                                */
48265   AUDADC_INTEN_ZXCA_NONZXCAINT         = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
48266 } AUDADC_INTEN_ZXCA_Enum;
48267 
48268 /* ===============================================  AUDADC INTEN DERR [7..7]  ================================================ */
48269 typedef enum {                                  /*!< AUDADC_INTEN_DERR                                                         */
48270   AUDADC_INTEN_DERR_DMAERROR           = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
48271   AUDADC_INTEN_DERR_NODMAERROR         = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
48272 } AUDADC_INTEN_DERR_Enum;
48273 
48274 /* ===============================================  AUDADC INTEN DCMP [6..6]  ================================================ */
48275 typedef enum {                                  /*!< AUDADC_INTEN_DCMP                                                         */
48276   AUDADC_INTEN_DCMP_DMACOMPLETE        = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
48277   AUDADC_INTEN_DCMP_DMAON              = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
48278 } AUDADC_INTEN_DCMP_Enum;
48279 
48280 /* ===============================================  AUDADC INTEN WCINC [5..5]  =============================================== */
48281 typedef enum {                                  /*!< AUDADC_INTEN_WCINC                                                        */
48282   AUDADC_INTEN_WCINC_WCINCINT          = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
48283   AUDADC_INTEN_WCINC_WCINCNOINT        = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
48284 } AUDADC_INTEN_WCINC_Enum;
48285 
48286 /* ===============================================  AUDADC INTEN WCEXC [4..4]  =============================================== */
48287 typedef enum {                                  /*!< AUDADC_INTEN_WCEXC                                                        */
48288   AUDADC_INTEN_WCEXC_WCEXCINT          = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
48289   AUDADC_INTEN_WCEXC_WCEXCNOINT        = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
48290 } AUDADC_INTEN_WCEXC_Enum;
48291 
48292 /* =============================================  AUDADC INTEN FIFOOVR2 [3..3]  ============================================== */
48293 typedef enum {                                  /*!< AUDADC_INTEN_FIFOOVR2                                                     */
48294   AUDADC_INTEN_FIFOOVR2_FIFOFULLINT    = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
48295   AUDADC_INTEN_FIFOOVR2_FIFOFULLNOINT  = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
48296 } AUDADC_INTEN_FIFOOVR2_Enum;
48297 
48298 /* =============================================  AUDADC INTEN FIFOOVR1 [2..2]  ============================================== */
48299 typedef enum {                                  /*!< AUDADC_INTEN_FIFOOVR1                                                     */
48300   AUDADC_INTEN_FIFOOVR1_FIFO75INT      = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
48301   AUDADC_INTEN_FIFOOVR1_FIFO75NOINT    = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
48302 } AUDADC_INTEN_FIFOOVR1_Enum;
48303 
48304 /* ==============================================  AUDADC INTEN SCNCMP [1..1]  =============================================== */
48305 typedef enum {                                  /*!< AUDADC_INTEN_SCNCMP                                                       */
48306   AUDADC_INTEN_SCNCMP_SCNCMPINT        = 1,     /*!< SCNCMPINT : AUDADC scan complete interrupt.                               */
48307   AUDADC_INTEN_SCNCMP_SCNCMPNOINT      = 0,     /*!< SCNCMPNOINT : No AUDADC scan complete interrupt.                          */
48308 } AUDADC_INTEN_SCNCMP_Enum;
48309 
48310 /* ==============================================  AUDADC INTEN CNVCMP [0..0]  =============================================== */
48311 typedef enum {                                  /*!< AUDADC_INTEN_CNVCMP                                                       */
48312   AUDADC_INTEN_CNVCMP_CNVCMPINT        = 1,     /*!< CNVCMPINT : AUDADC conversion complete interrupt.                         */
48313   AUDADC_INTEN_CNVCMP_CNVCMPNOINT      = 0,     /*!< CNVCMPNOINT : No AUDADC conversion complete interrupt.                    */
48314 } AUDADC_INTEN_CNVCMP_Enum;
48315 
48316 /* ========================================================  INTSTAT  ======================================================== */
48317 /* =============================================  AUDADC INTSTAT SATCB [11..11]  ============================================= */
48318 typedef enum {                                  /*!< AUDADC_INTSTAT_SATCB                                                      */
48319   AUDADC_INTSTAT_SATCB_SATCBINT        = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
48320                                                      occurred on either slot 2 or 3 (channel B)                                */
48321   AUDADC_INTSTAT_SATCB_NONSATCBINT     = 0,     /*!< NONSATCBINT : No-Saturation                                               */
48322 } AUDADC_INTSTAT_SATCB_Enum;
48323 
48324 /* =============================================  AUDADC INTSTAT SATCA [10..10]  ============================================= */
48325 typedef enum {                                  /*!< AUDADC_INTSTAT_SATCA                                                      */
48326   AUDADC_INTSTAT_SATCA_SATCAINT        = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
48327                                                      occurred on either slot 0 or 1 (channel A)                                */
48328   AUDADC_INTSTAT_SATCA_NONSATCAINT     = 0,     /*!< NONSATCAINT : No Saturation                                               */
48329 } AUDADC_INTSTAT_SATCA_Enum;
48330 
48331 /* ==============================================  AUDADC INTSTAT ZXCB [9..9]  =============================================== */
48332 typedef enum {                                  /*!< AUDADC_INTSTAT_ZXCB                                                       */
48333   AUDADC_INTSTAT_ZXCB_ZXCBINT          = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
48334                                                      occurred on either slot 2 or 3 (channel B)                                */
48335   AUDADC_INTSTAT_ZXCB_NONZXCBINT       = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
48336 } AUDADC_INTSTAT_ZXCB_Enum;
48337 
48338 /* ==============================================  AUDADC INTSTAT ZXCA [8..8]  =============================================== */
48339 typedef enum {                                  /*!< AUDADC_INTSTAT_ZXCA                                                       */
48340   AUDADC_INTSTAT_ZXCA_ZXCAINT          = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
48341                                                      occurred on either slot 0 or 1 (channel A)                                */
48342   AUDADC_INTSTAT_ZXCA_NONZXCAINT       = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
48343 } AUDADC_INTSTAT_ZXCA_Enum;
48344 
48345 /* ==============================================  AUDADC INTSTAT DERR [7..7]  =============================================== */
48346 typedef enum {                                  /*!< AUDADC_INTSTAT_DERR                                                       */
48347   AUDADC_INTSTAT_DERR_DMAERROR         = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
48348   AUDADC_INTSTAT_DERR_NODMAERROR       = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
48349 } AUDADC_INTSTAT_DERR_Enum;
48350 
48351 /* ==============================================  AUDADC INTSTAT DCMP [6..6]  =============================================== */
48352 typedef enum {                                  /*!< AUDADC_INTSTAT_DCMP                                                       */
48353   AUDADC_INTSTAT_DCMP_DMACOMPLETE      = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
48354   AUDADC_INTSTAT_DCMP_DMAON            = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
48355 } AUDADC_INTSTAT_DCMP_Enum;
48356 
48357 /* ==============================================  AUDADC INTSTAT WCINC [5..5]  ============================================== */
48358 typedef enum {                                  /*!< AUDADC_INTSTAT_WCINC                                                      */
48359   AUDADC_INTSTAT_WCINC_WCINCINT        = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
48360   AUDADC_INTSTAT_WCINC_WCINCNOINT      = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
48361 } AUDADC_INTSTAT_WCINC_Enum;
48362 
48363 /* ==============================================  AUDADC INTSTAT WCEXC [4..4]  ============================================== */
48364 typedef enum {                                  /*!< AUDADC_INTSTAT_WCEXC                                                      */
48365   AUDADC_INTSTAT_WCEXC_WCEXCINT        = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
48366   AUDADC_INTSTAT_WCEXC_WCEXCNOINT      = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
48367 } AUDADC_INTSTAT_WCEXC_Enum;
48368 
48369 /* ============================================  AUDADC INTSTAT FIFOOVR2 [3..3]  ============================================= */
48370 typedef enum {                                  /*!< AUDADC_INTSTAT_FIFOOVR2                                                   */
48371   AUDADC_INTSTAT_FIFOOVR2_FIFOFULLINT  = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
48372   AUDADC_INTSTAT_FIFOOVR2_FIFOFULLNOINT = 0,    /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
48373 } AUDADC_INTSTAT_FIFOOVR2_Enum;
48374 
48375 /* ============================================  AUDADC INTSTAT FIFOOVR1 [2..2]  ============================================= */
48376 typedef enum {                                  /*!< AUDADC_INTSTAT_FIFOOVR1                                                   */
48377   AUDADC_INTSTAT_FIFOOVR1_FIFO75INT    = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
48378   AUDADC_INTSTAT_FIFOOVR1_FIFO75NOINT  = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
48379 } AUDADC_INTSTAT_FIFOOVR1_Enum;
48380 
48381 /* =============================================  AUDADC INTSTAT SCNCMP [1..1]  ============================================== */
48382 typedef enum {                                  /*!< AUDADC_INTSTAT_SCNCMP                                                     */
48383   AUDADC_INTSTAT_SCNCMP_SCNCMPINT      = 1,     /*!< SCNCMPINT : AUDADC scan complete interrupt.                               */
48384   AUDADC_INTSTAT_SCNCMP_SCNCMPNOINT    = 0,     /*!< SCNCMPNOINT : No AUDADC scan complete interrupt.                          */
48385 } AUDADC_INTSTAT_SCNCMP_Enum;
48386 
48387 /* =============================================  AUDADC INTSTAT CNVCMP [0..0]  ============================================== */
48388 typedef enum {                                  /*!< AUDADC_INTSTAT_CNVCMP                                                     */
48389   AUDADC_INTSTAT_CNVCMP_CNVCMPINT      = 1,     /*!< CNVCMPINT : AUDADC conversion complete interrupt.                         */
48390   AUDADC_INTSTAT_CNVCMP_CNVCMPNOINT    = 0,     /*!< CNVCMPNOINT : No AUDADC conversion complete interrupt.                    */
48391 } AUDADC_INTSTAT_CNVCMP_Enum;
48392 
48393 /* ========================================================  INTCLR  ========================================================= */
48394 /* =============================================  AUDADC INTCLR SATCB [11..11]  ============================================== */
48395 typedef enum {                                  /*!< AUDADC_INTCLR_SATCB                                                       */
48396   AUDADC_INTCLR_SATCB_SATCBINT         = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
48397                                                      occurred on either slot 2 or 3 (channel B)                                */
48398   AUDADC_INTCLR_SATCB_NONSATCBINT      = 0,     /*!< NONSATCBINT : No-Saturation                                               */
48399 } AUDADC_INTCLR_SATCB_Enum;
48400 
48401 /* =============================================  AUDADC INTCLR SATCA [10..10]  ============================================== */
48402 typedef enum {                                  /*!< AUDADC_INTCLR_SATCA                                                       */
48403   AUDADC_INTCLR_SATCA_SATCAINT         = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
48404                                                      occurred on either slot 0 or 1 (channel A)                                */
48405   AUDADC_INTCLR_SATCA_NONSATCAINT      = 0,     /*!< NONSATCAINT : No Saturation                                               */
48406 } AUDADC_INTCLR_SATCA_Enum;
48407 
48408 /* ===============================================  AUDADC INTCLR ZXCB [9..9]  =============================================== */
48409 typedef enum {                                  /*!< AUDADC_INTCLR_ZXCB                                                        */
48410   AUDADC_INTCLR_ZXCB_ZXCBINT           = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
48411                                                      occurred on either slot 2 or 3 (channel B)                                */
48412   AUDADC_INTCLR_ZXCB_NONZXCBINT        = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
48413 } AUDADC_INTCLR_ZXCB_Enum;
48414 
48415 /* ===============================================  AUDADC INTCLR ZXCA [8..8]  =============================================== */
48416 typedef enum {                                  /*!< AUDADC_INTCLR_ZXCA                                                        */
48417   AUDADC_INTCLR_ZXCA_ZXCAINT           = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
48418                                                      occurred on either slot 0 or 1 (channel A)                                */
48419   AUDADC_INTCLR_ZXCA_NONZXCAINT        = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
48420 } AUDADC_INTCLR_ZXCA_Enum;
48421 
48422 /* ===============================================  AUDADC INTCLR DERR [7..7]  =============================================== */
48423 typedef enum {                                  /*!< AUDADC_INTCLR_DERR                                                        */
48424   AUDADC_INTCLR_DERR_DMAERROR          = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
48425   AUDADC_INTCLR_DERR_NODMAERROR        = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
48426 } AUDADC_INTCLR_DERR_Enum;
48427 
48428 /* ===============================================  AUDADC INTCLR DCMP [6..6]  =============================================== */
48429 typedef enum {                                  /*!< AUDADC_INTCLR_DCMP                                                        */
48430   AUDADC_INTCLR_DCMP_DMACOMPLETE       = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
48431   AUDADC_INTCLR_DCMP_DMAON             = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
48432 } AUDADC_INTCLR_DCMP_Enum;
48433 
48434 /* ==============================================  AUDADC INTCLR WCINC [5..5]  =============================================== */
48435 typedef enum {                                  /*!< AUDADC_INTCLR_WCINC                                                       */
48436   AUDADC_INTCLR_WCINC_WCINCINT         = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
48437   AUDADC_INTCLR_WCINC_WCINCNOINT       = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
48438 } AUDADC_INTCLR_WCINC_Enum;
48439 
48440 /* ==============================================  AUDADC INTCLR WCEXC [4..4]  =============================================== */
48441 typedef enum {                                  /*!< AUDADC_INTCLR_WCEXC                                                       */
48442   AUDADC_INTCLR_WCEXC_WCEXCINT         = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
48443   AUDADC_INTCLR_WCEXC_WCEXCNOINT       = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
48444 } AUDADC_INTCLR_WCEXC_Enum;
48445 
48446 /* =============================================  AUDADC INTCLR FIFOOVR2 [3..3]  ============================================= */
48447 typedef enum {                                  /*!< AUDADC_INTCLR_FIFOOVR2                                                    */
48448   AUDADC_INTCLR_FIFOOVR2_FIFOFULLINT   = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
48449   AUDADC_INTCLR_FIFOOVR2_FIFOFULLNOINT = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
48450 } AUDADC_INTCLR_FIFOOVR2_Enum;
48451 
48452 /* =============================================  AUDADC INTCLR FIFOOVR1 [2..2]  ============================================= */
48453 typedef enum {                                  /*!< AUDADC_INTCLR_FIFOOVR1                                                    */
48454   AUDADC_INTCLR_FIFOOVR1_FIFO75INT     = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
48455   AUDADC_INTCLR_FIFOOVR1_FIFO75NOINT   = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
48456 } AUDADC_INTCLR_FIFOOVR1_Enum;
48457 
48458 /* ==============================================  AUDADC INTCLR SCNCMP [1..1]  ============================================== */
48459 typedef enum {                                  /*!< AUDADC_INTCLR_SCNCMP                                                      */
48460   AUDADC_INTCLR_SCNCMP_SCNCMPINT       = 1,     /*!< SCNCMPINT : AUDADC scan complete interrupt.                               */
48461   AUDADC_INTCLR_SCNCMP_SCNCMPNOINT     = 0,     /*!< SCNCMPNOINT : No AUDADC scan complete interrupt.                          */
48462 } AUDADC_INTCLR_SCNCMP_Enum;
48463 
48464 /* ==============================================  AUDADC INTCLR CNVCMP [0..0]  ============================================== */
48465 typedef enum {                                  /*!< AUDADC_INTCLR_CNVCMP                                                      */
48466   AUDADC_INTCLR_CNVCMP_CNVCMPINT       = 1,     /*!< CNVCMPINT : AUDADC conversion complete interrupt.                         */
48467   AUDADC_INTCLR_CNVCMP_CNVCMPNOINT     = 0,     /*!< CNVCMPNOINT : No AUDADC conversion complete interrupt.                    */
48468 } AUDADC_INTCLR_CNVCMP_Enum;
48469 
48470 /* ========================================================  INTSET  ========================================================= */
48471 /* =============================================  AUDADC INTSET SATCB [11..11]  ============================================== */
48472 typedef enum {                                  /*!< AUDADC_INTSET_SATCB                                                       */
48473   AUDADC_INTSET_SATCB_SATCBINT         = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
48474                                                      occurred on either slot 2 or 3 (channel B)                                */
48475   AUDADC_INTSET_SATCB_NONSATCBINT      = 0,     /*!< NONSATCBINT : No-Saturation                                               */
48476 } AUDADC_INTSET_SATCB_Enum;
48477 
48478 /* =============================================  AUDADC INTSET SATCA [10..10]  ============================================== */
48479 typedef enum {                                  /*!< AUDADC_INTSET_SATCA                                                       */
48480   AUDADC_INTSET_SATCA_SATCAINT         = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
48481                                                      occurred on either slot 0 or 1 (channel A)                                */
48482   AUDADC_INTSET_SATCA_NONSATCAINT      = 0,     /*!< NONSATCAINT : No Saturation                                               */
48483 } AUDADC_INTSET_SATCA_Enum;
48484 
48485 /* ===============================================  AUDADC INTSET ZXCB [9..9]  =============================================== */
48486 typedef enum {                                  /*!< AUDADC_INTSET_ZXCB                                                        */
48487   AUDADC_INTSET_ZXCB_ZXCBINT           = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
48488                                                      occurred on either slot 2 or 3 (channel B)                                */
48489   AUDADC_INTSET_ZXCB_NONZXCBINT        = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
48490 } AUDADC_INTSET_ZXCB_Enum;
48491 
48492 /* ===============================================  AUDADC INTSET ZXCA [8..8]  =============================================== */
48493 typedef enum {                                  /*!< AUDADC_INTSET_ZXCA                                                        */
48494   AUDADC_INTSET_ZXCA_ZXCAINT           = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
48495                                                      occurred on either slot 0 or 1 (channel A)                                */
48496   AUDADC_INTSET_ZXCA_NONZXCAINT        = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
48497 } AUDADC_INTSET_ZXCA_Enum;
48498 
48499 /* ===============================================  AUDADC INTSET DERR [7..7]  =============================================== */
48500 typedef enum {                                  /*!< AUDADC_INTSET_DERR                                                        */
48501   AUDADC_INTSET_DERR_DMAERROR          = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
48502   AUDADC_INTSET_DERR_NODMAERROR        = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
48503 } AUDADC_INTSET_DERR_Enum;
48504 
48505 /* ===============================================  AUDADC INTSET DCMP [6..6]  =============================================== */
48506 typedef enum {                                  /*!< AUDADC_INTSET_DCMP                                                        */
48507   AUDADC_INTSET_DCMP_DMACOMPLETE       = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
48508   AUDADC_INTSET_DCMP_DMAON             = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
48509 } AUDADC_INTSET_DCMP_Enum;
48510 
48511 /* ==============================================  AUDADC INTSET WCINC [5..5]  =============================================== */
48512 typedef enum {                                  /*!< AUDADC_INTSET_WCINC                                                       */
48513   AUDADC_INTSET_WCINC_WCINCINT         = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
48514   AUDADC_INTSET_WCINC_WCINCNOINT       = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
48515 } AUDADC_INTSET_WCINC_Enum;
48516 
48517 /* ==============================================  AUDADC INTSET WCEXC [4..4]  =============================================== */
48518 typedef enum {                                  /*!< AUDADC_INTSET_WCEXC                                                       */
48519   AUDADC_INTSET_WCEXC_WCEXCINT         = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
48520   AUDADC_INTSET_WCEXC_WCEXCNOINT       = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
48521 } AUDADC_INTSET_WCEXC_Enum;
48522 
48523 /* =============================================  AUDADC INTSET FIFOOVR2 [3..3]  ============================================= */
48524 typedef enum {                                  /*!< AUDADC_INTSET_FIFOOVR2                                                    */
48525   AUDADC_INTSET_FIFOOVR2_FIFOFULLINT   = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
48526   AUDADC_INTSET_FIFOOVR2_FIFOFULLNOINT = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
48527 } AUDADC_INTSET_FIFOOVR2_Enum;
48528 
48529 /* =============================================  AUDADC INTSET FIFOOVR1 [2..2]  ============================================= */
48530 typedef enum {                                  /*!< AUDADC_INTSET_FIFOOVR1                                                    */
48531   AUDADC_INTSET_FIFOOVR1_FIFO75INT     = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
48532   AUDADC_INTSET_FIFOOVR1_FIFO75NOINT   = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
48533 } AUDADC_INTSET_FIFOOVR1_Enum;
48534 
48535 /* ==============================================  AUDADC INTSET SCNCMP [1..1]  ============================================== */
48536 typedef enum {                                  /*!< AUDADC_INTSET_SCNCMP                                                      */
48537   AUDADC_INTSET_SCNCMP_SCNCMPINT       = 1,     /*!< SCNCMPINT : AUDADC scan complete interrupt.                               */
48538   AUDADC_INTSET_SCNCMP_SCNCMPNOINT     = 0,     /*!< SCNCMPNOINT : No AUDADC scan complete interrupt.                          */
48539 } AUDADC_INTSET_SCNCMP_Enum;
48540 
48541 /* ==============================================  AUDADC INTSET CNVCMP [0..0]  ============================================== */
48542 typedef enum {                                  /*!< AUDADC_INTSET_CNVCMP                                                      */
48543   AUDADC_INTSET_CNVCMP_CNVCMPINT       = 1,     /*!< CNVCMPINT : AUDADC conversion complete interrupt.                         */
48544   AUDADC_INTSET_CNVCMP_CNVCMPNOINT     = 0,     /*!< CNVCMPNOINT : No AUDADC conversion complete interrupt.                    */
48545 } AUDADC_INTSET_CNVCMP_Enum;
48546 
48547 /* =======================================================  DMATRIGEN  ======================================================= */
48548 /* ======================================================  DMATRIGSTAT  ====================================================== */
48549 /* ========================================================  DMACFG  ========================================================= */
48550 /* ============================================  AUDADC DMACFG DMADYNPRI [9..9]  ============================================= */
48551 typedef enum {                                  /*!< AUDADC_DMACFG_DMADYNPRI                                                   */
48552   AUDADC_DMACFG_DMADYNPRI_DIS          = 0,     /*!< DIS : Disable dynamic priority (use DMAPRI setting only)                  */
48553   AUDADC_DMACFG_DMADYNPRI_EN           = 1,     /*!< EN : Enable dynamic priority                                              */
48554 } AUDADC_DMACFG_DMADYNPRI_Enum;
48555 
48556 /* ==============================================  AUDADC DMACFG DMAPRI [8..8]  ============================================== */
48557 typedef enum {                                  /*!< AUDADC_DMACFG_DMAPRI                                                      */
48558   AUDADC_DMACFG_DMAPRI_LOW             = 0,     /*!< LOW : Low Priority (service as best effort)                               */
48559   AUDADC_DMACFG_DMAPRI_HIGH            = 1,     /*!< HIGH : High Priority (service immediately)                                */
48560 } AUDADC_DMACFG_DMAPRI_Enum;
48561 
48562 /* ==============================================  AUDADC DMACFG DMADIR [2..2]  ============================================== */
48563 typedef enum {                                  /*!< AUDADC_DMACFG_DMADIR                                                      */
48564   AUDADC_DMACFG_DMADIR_P2M             = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
48565   AUDADC_DMACFG_DMADIR_M2P             = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
48566 } AUDADC_DMACFG_DMADIR_Enum;
48567 
48568 /* ==============================================  AUDADC DMACFG DMAEN [0..0]  =============================================== */
48569 typedef enum {                                  /*!< AUDADC_DMACFG_DMAEN                                                       */
48570   AUDADC_DMACFG_DMAEN_DIS              = 0,     /*!< DIS : Disable DMA Function                                                */
48571   AUDADC_DMACFG_DMAEN_EN               = 1,     /*!< EN : Enable DMA Function                                                  */
48572 } AUDADC_DMACFG_DMAEN_Enum;
48573 
48574 /* ======================================================  DMATOTCOUNT  ====================================================== */
48575 /* ======================================================  DMATARGADDR  ====================================================== */
48576 /* ========================================================  DMASTAT  ======================================================== */
48577 
48578 
48579 /* =========================================================================================================================== */
48580 /* ================                                          CLKGEN                                           ================ */
48581 /* =========================================================================================================================== */
48582 
48583 /* =========================================================  OCTRL  ========================================================= */
48584 /* ===============================================  CLKGEN OCTRL OSEL [7..7]  ================================================ */
48585 typedef enum {                                  /*!< CLKGEN_OCTRL_OSEL                                                         */
48586   CLKGEN_OCTRL_OSEL_RTC_XT             = 0,     /*!< RTC_XT : RTC uses the XT                                                  */
48587   CLKGEN_OCTRL_OSEL_RTC_LFRC           = 1,     /*!< RTC_LFRC : RTC uses the LFRC                                              */
48588 } CLKGEN_OCTRL_OSEL_Enum;
48589 
48590 /* ========================================================  CLKOUT  ========================================================= */
48591 /* ===============================================  CLKGEN CLKOUT CKEN [7..7]  =============================================== */
48592 typedef enum {                                  /*!< CLKGEN_CLKOUT_CKEN                                                        */
48593   CLKGEN_CLKOUT_CKEN_DIS               = 0,     /*!< DIS : Disable CLKOUT                                                      */
48594   CLKGEN_CLKOUT_CKEN_EN                = 1,     /*!< EN : Enable CLKOUT                                                        */
48595 } CLKGEN_CLKOUT_CKEN_Enum;
48596 
48597 /* ==============================================  CLKGEN CLKOUT CKSEL [0..5]  =============================================== */
48598 typedef enum {                                  /*!< CLKGEN_CLKOUT_CKSEL                                                       */
48599   CLKGEN_CLKOUT_CKSEL_LFRC             = 0,     /*!< LFRC : LFRC clock source selection                                        */
48600   CLKGEN_CLKOUT_CKSEL_XT_DIV2          = 1,     /*!< XT_DIV2 : XT / 2 clock source selection                                   */
48601   CLKGEN_CLKOUT_CKSEL_XT_DIV4          = 2,     /*!< XT_DIV4 : XT / 4 clock source selection                                   */
48602   CLKGEN_CLKOUT_CKSEL_XT_DIV8          = 3,     /*!< XT_DIV8 : XT / 8 clock source selection                                   */
48603   CLKGEN_CLKOUT_CKSEL_XT_DIV16         = 4,     /*!< XT_DIV16 : XT / 16 clock source selection                                 */
48604   CLKGEN_CLKOUT_CKSEL_XT_DIV32         = 5,     /*!< XT_DIV32 : XT / 32 clock source selection                                 */
48605   CLKGEN_CLKOUT_CKSEL_RTC_1Hz          = 16,    /*!< RTC_1Hz : 1 Hz as selected in RTC                                         */
48606   CLKGEN_CLKOUT_CKSEL_XT_DIV2M         = 22,    /*!< XT_DIV2M : XT / 2097152 (2^21) clock source selection                     */
48607   CLKGEN_CLKOUT_CKSEL_XT               = 23,    /*!< XT : XT clock source selection                                            */
48608   CLKGEN_CLKOUT_CKSEL_CG_100Hz         = 24,    /*!< CG_100Hz : 100 Hz as selected in CLKGEN                                   */
48609   CLKGEN_CLKOUT_CKSEL_HFRC_DIV2        = 25,    /*!< HFRC_DIV2 : HFRC / 2 clock source selection                               */
48610   CLKGEN_CLKOUT_CKSEL_HFRC_DIV8        = 26,    /*!< HFRC_DIV8 : HFRC / 8 clock source selection                               */
48611   CLKGEN_CLKOUT_CKSEL_HFRC_DIV16       = 27,    /*!< HFRC_DIV16 : HFRC / 16 clock source selection                             */
48612   CLKGEN_CLKOUT_CKSEL_HFRC_DIV32       = 28,    /*!< HFRC_DIV32 : HFRC / 32 clock source selection                             */
48613   CLKGEN_CLKOUT_CKSEL_HFRC_DIV128      = 29,    /*!< HFRC_DIV128 : HFRC / 128 clock source selection                           */
48614   CLKGEN_CLKOUT_CKSEL_HFRC_DIV256      = 30,    /*!< HFRC_DIV256 : HFRC / 256 clock source selection                           */
48615   CLKGEN_CLKOUT_CKSEL_HFRC_DIV512      = 31,    /*!< HFRC_DIV512 : HFRC / 512 clock source selection                           */
48616   CLKGEN_CLKOUT_CKSEL_HFRC_DIV1024     = 32,    /*!< HFRC_DIV1024 : HFRC / 1024 clock source selection                         */
48617   CLKGEN_CLKOUT_CKSEL_FLASH_CLK        = 34,    /*!< FLASH_CLK : Flash Clock clock source selection                            */
48618   CLKGEN_CLKOUT_CKSEL_LFRC_DIV2        = 35,    /*!< LFRC_DIV2 : LFRC / 2 clock source selection                               */
48619   CLKGEN_CLKOUT_CKSEL_LFRC_DIV32       = 36,    /*!< LFRC_DIV32 : LFRC / 32 clock source selection                             */
48620   CLKGEN_CLKOUT_CKSEL_LFRC_DIV512      = 37,    /*!< LFRC_DIV512 : LFRC / 512 clock source selection                           */
48621   CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K      = 38,    /*!< LFRC_DIV32K : LFRC / 32768 clock source selection                         */
48622   CLKGEN_CLKOUT_CKSEL_XT_DIV256        = 39,    /*!< XT_DIV256 : XT / 256 clock source selection                               */
48623   CLKGEN_CLKOUT_CKSEL_XT_DIV8K         = 40,    /*!< XT_DIV8K : XT / 8192 clock source selection                               */
48624   CLKGEN_CLKOUT_CKSEL_XT_DIV64K        = 41,    /*!< XT_DIV64K : XT / 65536 (2^16) clock source selection                      */
48625   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16      = 42,    /*!< ULFRC_DIV16 : Uncal LFRC / 16 clock source selection                      */
48626   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128     = 43,    /*!< ULFRC_DIV128 : Uncal LFRC / 128 clock source selection                    */
48627   CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz        = 44,    /*!< ULFRC_1Hz : Uncal LFRC / 1024 clock source selection                      */
48628   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K      = 45,    /*!< ULFRC_DIV4K : Uncal LFRC / 4096 clock source selection                    */
48629   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M      = 46,    /*!< ULFRC_DIV1M : Uncal LFRC / 1048576 (2^20) clock source selection          */
48630   CLKGEN_CLKOUT_CKSEL_HFRC_DIV256K     = 47,    /*!< HFRC_DIV256K : HFRC / 262144 (2^18) clock source selection                */
48631   CLKGEN_CLKOUT_CKSEL_HFRC_DIV64M      = 48,    /*!< HFRC_DIV64M : HFRC / 67108864 (2^26) clock source selection               */
48632   CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M       = 49,    /*!< LFRC_DIV1M : LFRC / 1048576 (2^20) clock source selection                 */
48633   CLKGEN_CLKOUT_CKSEL_HFRCNE           = 50,    /*!< HFRCNE : HFRC (not autoenabled)                                           */
48634   CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8      = 51,    /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled)                                  */
48635   CLKGEN_CLKOUT_CKSEL_XTNE             = 53,    /*!< XTNE : XT (not autoenabled)                                               */
48636   CLKGEN_CLKOUT_CKSEL_XTNE_DIV16       = 54,    /*!< XTNE_DIV16 : XT / 16 (not autoenabled)                                    */
48637   CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32     = 55,    /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled)                                */
48638   CLKGEN_CLKOUT_CKSEL_LFRCNE           = 57,    /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values            */
48639   CLKGEN_CLKOUT_CKSEL_HFRC2_6MHz       = 58,    /*!< HFRC2_6MHz : HFRC2 6MHz clock source selection                            */
48640   CLKGEN_CLKOUT_CKSEL_HFRC2_12MHz      = 59,    /*!< HFRC2_12MHz : HFRC2 24MHz clock source selection                          */
48641   CLKGEN_CLKOUT_CKSEL_HFRC2_24MHz      = 60,    /*!< HFRC2_24MHz : HFRC2 24MHz clock source selection                          */
48642 } CLKGEN_CLKOUT_CKSEL_Enum;
48643 
48644 /* =========================================================  HFADJ  ========================================================= */
48645 /* ==========================================  CLKGEN HFADJ HFADJMAXDELTA [24..28]  ========================================== */
48646 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJMAXDELTA                                                */
48647   CLKGEN_HFADJ_HFADJMAXDELTA_DISABLED  = 0,     /*!< DISABLED : Maximum Delta function is disabled                             */
48648   CLKGEN_HFADJ_HFADJMAXDELTA_ENABLED   = 1,     /*!< ENABLED : Maximum Delta function is enabled                               */
48649 } CLKGEN_HFADJ_HFADJMAXDELTA_Enum;
48650 
48651 /* ============================================  CLKGEN HFADJ HFADJGAIN [21..23]  ============================================ */
48652 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJGAIN                                                    */
48653   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1     = 0,     /*!< Gain_of_1 : HF Adjust with Gain of 1                                      */
48654   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1,    /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5                               */
48655   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2,    /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25                              */
48656   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3,    /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125                             */
48657   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4,   /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625                           */
48658   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5,   /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125                          */
48659 } CLKGEN_HFADJ_HFADJGAIN_Enum;
48660 
48661 /* ============================================  CLKGEN HFADJ HFWARMUP [20..20]  ============================================= */
48662 typedef enum {                                  /*!< CLKGEN_HFADJ_HFWARMUP                                                     */
48663   CLKGEN_HFADJ_HFWARMUP_1SEC           = 0,     /*!< 1SEC : Autoadjust XT warmup period = 1-2 seconds                          */
48664   CLKGEN_HFADJ_HFWARMUP_2SEC           = 1,     /*!< 2SEC : Autoadjust XT warmup period = 2-4 seconds                          */
48665 } CLKGEN_HFADJ_HFWARMUP_Enum;
48666 
48667 /* ==============================================  CLKGEN HFADJ HFADJCK [1..3]  ============================================== */
48668 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJCK                                                      */
48669   CLKGEN_HFADJ_HFADJCK_4SEC            = 0,     /*!< 4SEC : Autoadjust repeat period = 4 seconds                               */
48670   CLKGEN_HFADJ_HFADJCK_16SEC           = 1,     /*!< 16SEC : Autoadjust repeat period = 16 seconds                             */
48671   CLKGEN_HFADJ_HFADJCK_32SEC           = 2,     /*!< 32SEC : Autoadjust repeat period = 32 seconds                             */
48672   CLKGEN_HFADJ_HFADJCK_64SEC           = 3,     /*!< 64SEC : Autoadjust repeat period = 64 seconds                             */
48673   CLKGEN_HFADJ_HFADJCK_128SEC          = 4,     /*!< 128SEC : Autoadjust repeat period = 128 seconds                           */
48674   CLKGEN_HFADJ_HFADJCK_256SEC          = 5,     /*!< 256SEC : Autoadjust repeat period = 256 seconds                           */
48675   CLKGEN_HFADJ_HFADJCK_512SEC          = 6,     /*!< 512SEC : Autoadjust repeat period = 512 seconds                           */
48676   CLKGEN_HFADJ_HFADJCK_1024SEC         = 7,     /*!< 1024SEC : Autoadjust repeat period = 1024 seconds                         */
48677 } CLKGEN_HFADJ_HFADJCK_Enum;
48678 
48679 /* ==============================================  CLKGEN HFADJ HFADJEN [0..0]  ============================================== */
48680 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJEN                                                      */
48681   CLKGEN_HFADJ_HFADJEN_DIS             = 0,     /*!< DIS : Disable the HFRC adjustment                                         */
48682   CLKGEN_HFADJ_HFADJEN_EN              = 1,     /*!< EN : Enable the HFRC adjustment                                           */
48683 } CLKGEN_HFADJ_HFADJEN_Enum;
48684 
48685 /* ======================================================  CLOCKENSTAT  ====================================================== */
48686 /* ========================================  CLKGEN CLOCKENSTAT CLOCKENSTAT [0..31]  ========================================= */
48687 typedef enum {                                  /*!< CLKGEN_CLOCKENSTAT_CLOCKENSTAT                                            */
48688   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_PERIPH_ALL_XTAL_EN = 16777216,/*!< PERIPH_ALL_XTAL_EN : [24] Clock enable for PERIPH_ALL_XTAL_EN */
48689   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_PERIPH_ALL_HFRC_EN = 33554432,/*!< PERIPH_ALL_HFRC_EN : [25] Clock enable for PERIPH_ALL_HFRC_EN */
48690   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_HFADJEN = 67108864,/*!< HFADJEN : [26] HFRC Adjust enabled                                    */
48691   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_HFRC_EN_HFADJ = 134217728,/*!< HFRC_EN_HFADJ : [27] HFRC HFADJ enabled                        */
48692   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_nOSEL = 268435456,/*!< nOSEL : [28] ~OSEL                                                     */
48693   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_clkout_xtal_en = 536870912,/*!< clkout_xtal_en : [29] XTAL clkout enabled                     */
48694   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_clkout_hfrc_en = 1073741824,/*!< clkout_hfrc_en : [30] HFRC clkout enabled                    */
48695 } CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum;
48696 
48697 /* =====================================================  CLOCKEN2STAT  ====================================================== */
48698 /* =======================================  CLKGEN CLOCKEN2STAT CLOCKEN2STAT [0..31]  ======================================== */
48699 typedef enum {                                  /*!< CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT                                          */
48700   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_ADC_CLKEN = 1,/*!< ADC_CLKEN : [0] Clock enable for the ADC.                                */
48701   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_ACTIVITY_CLKEN = 2,/*!< APBDMA_ACTIVITY_CLKEN : [1] Clock enable for the APBDMA ACTIVITY */
48702   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AOH_CLKEN = 4,/*!< APBDMA_AOH_CLKEN : [2] Clock enable for the APBDMA AOH DOMAIN     */
48703   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AOL_CLKEN = 8,/*!< APBDMA_AOL_CLKEN : [3] Clock enable for the APBDMA AOL DOMAIN     */
48704   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_APB_CLKEN = 16,/*!< APBDMA_APB_CLKEN : [4] Clock enable for the APBDMA_APB           */
48705   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AUD_CLKEN = 32,/*!< APBDMA_AUD_CLKEN : [5] Clock enable for the APBDMA_AUD           */
48706   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_CRYPTO_CLKEN = 64,/*!< APBDMA_CRYPTO_CLKEN : [6] Clock enable for the APBDMA_HCPA    */
48707   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DBG_CLKEN = 128,/*!< APBDMA_DBG_CLKEN : [7] Clock enable for the APBDMA_DBG          */
48708   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DISP_CLKEN = 256,/*!< APBDMA_DISP_CLKEN : [8] Clock enable for the APBDMA_DISP       */
48709   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DISPPHY_CLKEN = 512,/*!< APBDMA_DISPPHY_CLKEN : [9] Clock enable for the APBDMA_DISPPHY */
48710   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DSPA_CLKEN = 1024,/*!< APBDMA_DSPA_CLKEN : [10] Clock enable for the APBDMA_DSPA     */
48711   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_GFX_CLKEN = 2048,/*!< APBDMA_GFX_CLKEN : [11] Clock enable for the APBDMA_GFX        */
48712   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPA_CLKEN = 4096,/*!< APBDMA_HSPA_CLKEN : [12] Clock enable for the APBDMA_HSPA     */
48713   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPB_CLKEN = 8192,/*!< APBDMA_HSPB_CLKEN : [13] Clock enable for the APBDMA_HSPB     */
48714   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPC_CLKEN = 16384,/*!< APBDMA_HSPC_CLKEN : [14] Clock enable for the APBDMA_HSPC    */
48715   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_IOS_CLKEN = 32768,/*!< APBDMA_IOS_CLKEN : [15] Clock enable for the APBDMA_IOS       */
48716   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI0_CLKEN = 65536,/*!< APBDMA_MSPI0_CLKEN : [16] Clock enable for the APBDMA_MSPI0 */
48717   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI1_CLKEN = 131072,/*!< APBDMA_MSPI1_CLKEN : [17] Clock enable for the APBDMA_MSPI1 */
48718   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI2_CLKEN = 262144,/*!< APBDMA_MSPI2_CLKEN : [18] Clock enable for the APBDMA_MSPI2 */
48719   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_SDIO_CLKEN = 524288,/*!< APBDMA_SDIO_CLKEN : [19] Clock enable for the APBDMA_SDIO   */
48720   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_USB_CLKEN = 1048576,/*!< APBDMA_USB_CLKEN : [20] Clock enable for the APBDMA_USB     */
48721   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_AUDADC_CLKEN = 2097152,/*!< AUDADC_CLKEN : [21] Clock enable for the AUDADC                 */
48722   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_CM4_TPIU_CLKEN = 4194304,/*!< CM4_TPIU_CLKEN : [22] Clock enable for the CM4_TPIU           */
48723   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DBG_TPIU_CLKEN = 8388608,/*!< DBG_TPIU_CLKEN : [23] Clock enable for the DBG_TPIU           */
48724   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DBG_TS_CLKEN = 16777216,/*!< DBG_TS_CLKEN : [24] Clock enable for the DBG_TS                */
48725   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DISP_CLK_CLKEN = 33554432,/*!< DISP_CLK_CLKEN : [25] Clock enable for the DISP_CLK          */
48726   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DPHY_PLL_REF_CLKEN = 67108864,/*!< DPHY_PLL_REF_CLKEN : [26] Clock enable for the DPHY_PLL_REF */
48727   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S0_CLKEN = 134217728,/*!< DSP_I2S0_CLKEN : [27] Clock enable for the DSP_I2S0         */
48728   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S0_REFCLK_CLKEN = 268435456,/*!< DSP_I2S0_REFCLK_CLKEN : [28] Clock enable for the DSP_I2S0_REFCLK */
48729   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S1_CLKEN = 536870912,/*!< DSP_I2S1_CLKEN : [29] Clock enable for the DSP_I2S1         */
48730   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S1_REFCLK_CLKEN = 1073741824,/*!< DSP_I2S1_REFCLK_CLKEN : [30] Clock enable for the DSP_I2S1_REFCLK */
48731   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_MILLI_CLKEN = -2147483648,/*!< DSP_MILLI_CLKEN : [31] Clock enable for the DSP_MILLI    */
48732 } CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum;
48733 
48734 /* =====================================================  CLOCKEN3STAT  ====================================================== */
48735 /* =======================================  CLKGEN CLOCKEN3STAT CLOCKEN3STAT [0..31]  ======================================== */
48736 typedef enum {                                  /*!< CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT                                          */
48737   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM0_CLKEN = 1,/*!< DSP_PDM0_CLKEN : [0] Clock enable for the DSP_PDM0                  */
48738   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM1_CLKEN = 2,/*!< DSP_PDM1_CLKEN : [1] Clock enable for the DSP_PDM1                  */
48739   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM2_CLKEN = 4,/*!< DSP_PDM2_CLKEN : [2] Clock enable for the DSP_PDM2                  */
48740   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM3_CLKEN = 8,/*!< DSP_PDM3_CLKEN : [3] Clock enable for the DSP_PDM3                  */
48741   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_I3C0_REFCLK_CLKEN = 16,/*!< I3C0_REFCLK_CLKEN : [4] Clock enable for the I3C0_REFCLK        */
48742   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_I3C1_REFCLK_CLKEN = 32,/*!< I3C1_REFCLK_CLKEN : [5] Clock enable for the I3C1_REFCLK        */
48743   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC0_CLKEN = 64,/*!< IOMSTRIFC0_CLKEN : [6] Clock enable for the IOMSTRIFC0           */
48744   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC1_CLKEN = 128,/*!< IOMSTRIFC1_CLKEN : [7] Clock enable for the IO MASTER 1 IFC
48745                                                      INTERFACE                                                                 */
48746   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC2_CLKEN = 256,/*!< IOMSTRIFC2_CLKEN : [8] Clock enable for the IO MASTER 2 IFC
48747                                                      INTERFACE                                                                 */
48748   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC3_CLKEN = 512,/*!< IOMSTRIFC3_CLKEN : [9] Clock enable for the IO MASTER 3 IFC
48749                                                      INTERFACE                                                                 */
48750   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC4_CLKEN = 1024,/*!< IOMSTRIFC4_CLKEN : [10] Clock enable for the IO MASTER 4 IFC
48751                                                      INTERFACE                                                                 */
48752   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC5_CLKEN = 2048,/*!< IOMSTRIFC5_CLKEN : [11] Clock enable for the IO MASTER 5 IFC
48753                                                      INTERFACE                                                                 */
48754   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC6_CLKEN = 4096,/*!< IOMSTRIFC6_CLKEN : [12] Clock enable for the IO MASTER 6 IFC
48755                                                      INTERFACE                                                                 */
48756   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC7_CLKEN = 8192,/*!< IOMSTRIFC7_CLKEN : [13] Clock enable for the IO MASTER 7 IFC
48757                                                      INTERFACE                                                                 */
48758   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RSTGEN_CLKEN = 16384,/*!< RSTGEN_CLKEN : [14] Clock enable for the RSTGEN                   */
48759   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RSTGEN_POS_CLKEN = 32768,/*!< RSTGEN_POS_CLKEN : [15] Clock enable for the RSTGEN           */
48760   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_CLKEN = 65536,/*!< RTC_CLKEN : [16] Clock enable for the RTC                            */
48761   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_SDIO_XIN_CLKEN = 131072,/*!< SDIO_XIN_CLKEN : [17] Clock enable for the SDIO_XIN            */
48762   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART0HF_CLKEN = 262144,/*!< UART0HF_CLKEN : [18] Clock enable for the UART0 HF              */
48763   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART1HF_CLKEN = 524288,/*!< UART1HF_CLKEN : [19] Clock enable for the UART1 HF              */
48764   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART2HF_CLKEN = 1048576,/*!< UART2HF_CLKEN : [20] Clock enable for the UART2 HF             */
48765   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART3HF_CLKEN = 2097152,/*!< UART3HF_CLKEN : [21] Clock enable for the UART3 HF             */
48766   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_USB_REFCLK_CLKEN = 4194304,/*!< USB_REFCLK_CLKEN : [22] Clock enable for the USB_REFCLK     */
48767   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_WDT_CLKEN = 8388608,/*!< WDT_CLKEN : [23] Clock enable for the WDT                          */
48768 } CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum;
48769 
48770 /* =========================================================  MISC  ========================================================== */
48771 /* =========================================  CLKGEN MISC HFRC96TRUNKGATE [24..24]  ========================================== */
48772 typedef enum {                                  /*!< CLKGEN_MISC_HFRC96TRUNKGATE                                               */
48773   CLKGEN_MISC_HFRC96TRUNKGATE_DIS      = 0,     /*!< DIS : Disable HFRC96_TRUNK_GATE                                           */
48774   CLKGEN_MISC_HFRC96TRUNKGATE_EN       = 1,     /*!< EN : DO NOT USE. HFRC96_TRUNK_GATE. Setting this bit when BIT23=0,
48775                                                      will kill HFRC root clock.                                                */
48776 } CLKGEN_MISC_HFRC96TRUNKGATE_Enum;
48777 
48778 /* ========================================  CLKGEN MISC HFRCFUNCCLKGATEEN [23..23]  ========================================= */
48779 typedef enum {                                  /*!< CLKGEN_MISC_HFRCFUNCCLKGATEEN                                             */
48780   CLKGEN_MISC_HFRCFUNCCLKGATEEN_DIS    = 0,     /*!< DIS : Disable clock gate                                                  */
48781   CLKGEN_MISC_HFRCFUNCCLKGATEEN_EN     = 1,     /*!< EN : Enable clock gate                                                    */
48782 } CLKGEN_MISC_HFRCFUNCCLKGATEEN_Enum;
48783 
48784 /* =======================================  CLKGEN MISC ETMTRACECLKCLKGATEEN [22..22]  ======================================= */
48785 typedef enum {                                  /*!< CLKGEN_MISC_ETMTRACECLKCLKGATEEN                                          */
48786   CLKGEN_MISC_ETMTRACECLKCLKGATEEN_DIS = 0,     /*!< DIS : Disable clock gate                                                  */
48787   CLKGEN_MISC_ETMTRACECLKCLKGATEEN_EN  = 1,     /*!< EN : Enable clock gate                                                    */
48788 } CLKGEN_MISC_ETMTRACECLKCLKGATEEN_Enum;
48789 
48790 /* ======================================  CLKGEN MISC APBDMACPUCLKCLKGATEEN [21..21]  ======================================= */
48791 typedef enum {                                  /*!< CLKGEN_MISC_APBDMACPUCLKCLKGATEEN                                         */
48792   CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_DIS = 0,    /*!< DIS : Disable clock gate                                                  */
48793   CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_EN = 1,     /*!< EN : Enable clock gate                                                    */
48794 } CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_Enum;
48795 
48796 /* ========================================  CLKGEN MISC GFXAXICLKCLKGATEEN [20..20]  ======================================== */
48797 typedef enum {                                  /*!< CLKGEN_MISC_GFXAXICLKCLKGATEEN                                            */
48798   CLKGEN_MISC_GFXAXICLKCLKGATEEN_DIS   = 0,     /*!< DIS : Disable clock gate                                                  */
48799   CLKGEN_MISC_GFXAXICLKCLKGATEEN_EN    = 1,     /*!< EN : Enable clock gate                                                    */
48800 } CLKGEN_MISC_GFXAXICLKCLKGATEEN_Enum;
48801 
48802 /* =========================================  CLKGEN MISC GFXCLKCLKGATEEN [19..19]  ========================================== */
48803 typedef enum {                                  /*!< CLKGEN_MISC_GFXCLKCLKGATEEN                                               */
48804   CLKGEN_MISC_GFXCLKCLKGATEEN_DIS      = 0,     /*!< DIS : Disable clock gate                                                  */
48805   CLKGEN_MISC_GFXCLKCLKGATEEN_EN       = 1,     /*!< EN : Enable clock gate                                                    */
48806 } CLKGEN_MISC_GFXCLKCLKGATEEN_Enum;
48807 
48808 /* =========================================  CLKGEN MISC CM4DAXICLKGATEEN [18..18]  ========================================= */
48809 typedef enum {                                  /*!< CLKGEN_MISC_CM4DAXICLKGATEEN                                              */
48810   CLKGEN_MISC_CM4DAXICLKGATEEN_DIS     = 0,     /*!< DIS : Disable clock gate                                                  */
48811   CLKGEN_MISC_CM4DAXICLKGATEEN_EN      = 1,     /*!< EN : Enable clock gate                                                    */
48812 } CLKGEN_MISC_CM4DAXICLKGATEEN_Enum;
48813 
48814 /* =======================================  CLKGEN MISC PWRONCLKENUSBREFCLK [17..17]  ======================================== */
48815 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENUSBREFCLK                                           */
48816   CLKGEN_MISC_PWRONCLKENUSBREFCLK_USBREFCLKENRST = 0,/*!< USBREFCLKENRST : Enable USB REF Clock to run during reset            */
48817   CLKGEN_MISC_PWRONCLKENUSBREFCLK_DEFEATURE = 1,/*!< DEFEATURE : Chicken bit to revert to rev A                                */
48818 } CLKGEN_MISC_PWRONCLKENUSBREFCLK_Enum;
48819 
48820 /* =======================================  CLKGEN MISC PWRONCLKENI2S1REFCLK [16..16]  ======================================= */
48821 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENI2S1REFCLK                                          */
48822   CLKGEN_MISC_PWRONCLKENI2S1REFCLK_I2S1REFCLKENRST = 0,/*!< I2S1REFCLKENRST : Enable I2S instance 1 Clock to run during
48823                                                      reset                                                                     */
48824   CLKGEN_MISC_PWRONCLKENI2S1REFCLK_DEFEATURE = 1,/*!< DEFEATURE : Chicken bit to revert to rev A                               */
48825 } CLKGEN_MISC_PWRONCLKENI2S1REFCLK_Enum;
48826 
48827 /* =======================================  CLKGEN MISC PWRONCLKENI2S0REFCLK [15..15]  ======================================= */
48828 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENI2S0REFCLK                                          */
48829   CLKGEN_MISC_PWRONCLKENI2S0REFCLK_I2S0REFCLKENRST = 0,/*!< I2S0REFCLKENRST : Enable I2S instance 0 Clock to run during
48830                                                      reset                                                                     */
48831   CLKGEN_MISC_PWRONCLKENI2S0REFCLK_DEFEATURE = 1,/*!< DEFEATURE : Chicken bit to revert to rev A                               */
48832 } CLKGEN_MISC_PWRONCLKENI2S0REFCLK_Enum;
48833 
48834 /* ========================================  CLKGEN MISC AXIXACLKENOVRRIDE [14..14]  ========================================= */
48835 typedef enum {                                  /*!< CLKGEN_MISC_AXIXACLKENOVRRIDE                                             */
48836   CLKGEN_MISC_AXIXACLKENOVRRIDE_DEFEATURE_DISABLED = 0,/*!< DEFEATURE_DISABLED : Fine grain clock gating enabled               */
48837   CLKGEN_MISC_AXIXACLKENOVRRIDE_DEFEATURE = 1,  /*!< DEFEATURE : AXI Clock enabled when core is not in Sleep mode              */
48838 } CLKGEN_MISC_AXIXACLKENOVRRIDE_Enum;
48839 
48840 /* ==========================================  CLKGEN MISC PWRONCLKENI2S1 [13..13]  ========================================== */
48841 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENI2S1                                                */
48842   CLKGEN_MISC_PWRONCLKENI2S1_I2S1CLKENRST = 0,  /*!< I2S1CLKENRST : Enable I2S instance 1 engine Clock to run during
48843                                                      reset                                                                     */
48844   CLKGEN_MISC_PWRONCLKENI2S1_DEFEATURE = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
48845 } CLKGEN_MISC_PWRONCLKENI2S1_Enum;
48846 
48847 /* ==========================================  CLKGEN MISC PWRONCLKENI2S0 [12..12]  ========================================== */
48848 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENI2S0                                                */
48849   CLKGEN_MISC_PWRONCLKENI2S0_I2S0CLKENRST = 0,  /*!< I2S0CLKENRST : Enable I2S instance 0 engine Clock to run during
48850                                                      reset                                                                     */
48851   CLKGEN_MISC_PWRONCLKENI2S0_DEFEATURE = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
48852 } CLKGEN_MISC_PWRONCLKENI2S0_Enum;
48853 
48854 /* =========================================  CLKGEN MISC PWRONCLKENCRYPTO [11..11]  ========================================= */
48855 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENCRYPTO                                              */
48856   CLKGEN_MISC_PWRONCLKENCRYPTO_CRYPTOCLKENRST = 0,/*!< CRYPTOCLKENRST : Enable Cryto engine Clock to run during reset          */
48857   CLKGEN_MISC_PWRONCLKENCRYPTO_DEFEATURE = 1,   /*!< DEFEATURE : Chicken bit to revert to rev A                                */
48858 } CLKGEN_MISC_PWRONCLKENCRYPTO_Enum;
48859 
48860 /* ==========================================  CLKGEN MISC PWRONCLKENSDIO [10..10]  ========================================== */
48861 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENSDIO                                                */
48862   CLKGEN_MISC_PWRONCLKENSDIO_SDIOCLKENRST = 0,  /*!< SDIOCLKENRST : Enable SDIO Clock to run during reset                      */
48863   CLKGEN_MISC_PWRONCLKENSDIO_DEFEATURE = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
48864 } CLKGEN_MISC_PWRONCLKENSDIO_Enum;
48865 
48866 /* ===========================================  CLKGEN MISC PWRONCLKENUSB [9..9]  ============================================ */
48867 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENUSB                                                 */
48868   CLKGEN_MISC_PWRONCLKENUSB_USBCLKENRST = 0,    /*!< USBCLKENRST : Enable USB Clock to run during reset                        */
48869   CLKGEN_MISC_PWRONCLKENUSB_DEFEATURE  = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
48870 } CLKGEN_MISC_PWRONCLKENUSB_Enum;
48871 
48872 /* ===========================================  CLKGEN MISC PWRONCLKENGFX [8..8]  ============================================ */
48873 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENGFX                                                 */
48874   CLKGEN_MISC_PWRONCLKENGFX_GFXCLKENRST = 0,    /*!< GFXCLKENRST : Enable GFX Clock to run during reset                        */
48875   CLKGEN_MISC_PWRONCLKENGFX_DEFEATURE  = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
48876 } CLKGEN_MISC_PWRONCLKENGFX_Enum;
48877 
48878 /* =========================================  CLKGEN MISC PWRONCLKENDISPPHY [7..7]  ========================================== */
48879 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENDISPPHY                                             */
48880   CLKGEN_MISC_PWRONCLKENDISPPHY_DISPPHYCLKENRST = 0,/*!< DISPPHYCLKENRST : Enable Display Phy Clock to run during reset        */
48881   CLKGEN_MISC_PWRONCLKENDISPPHY_DEFEATURE = 1,  /*!< DEFEATURE : Chicken bit to revert to rev A                                */
48882 } CLKGEN_MISC_PWRONCLKENDISPPHY_Enum;
48883 
48884 /* ===========================================  CLKGEN MISC PWRONCLKENDISP [6..6]  =========================================== */
48885 typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENDISP                                                */
48886   CLKGEN_MISC_PWRONCLKENDISP_DISPCLKENRST = 0,  /*!< DISPCLKENRST : Enable Display Clock to run during reset                   */
48887   CLKGEN_MISC_PWRONCLKENDISP_DEFEATURE = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
48888 } CLKGEN_MISC_PWRONCLKENDISP_Enum;
48889 
48890 /* ==============================================  CLKGEN MISC FRCHFRC2 [5..5]  ============================================== */
48891 typedef enum {                                  /*!< CLKGEN_MISC_FRCHFRC2                                                      */
48892   CLKGEN_MISC_FRCHFRC2_NOFRC           = 0,     /*!< NOFRC : Do not force HFRC2 on; stops in deep sleep mode.                  */
48893   CLKGEN_MISC_FRCHFRC2_FRC             = 1,     /*!< FRC : Force HFRC2 on; runs in deep sleep mode.                            */
48894 } CLKGEN_MISC_FRCHFRC2_Enum;
48895 
48896 /* ==========================================  CLKGEN MISC USEHFRC2FQ192MHZ [4..4]  ========================================== */
48897 typedef enum {                                  /*!< CLKGEN_MISC_USEHFRC2FQ192MHZ                                              */
48898   CLKGEN_MISC_USEHFRC2FQ192MHZ_HFRCFQ192MHz = 0,/*!< HFRCFQ192MHz : Use HFRC-192MHz                                            */
48899   CLKGEN_MISC_USEHFRC2FQ192MHZ_HFRC2FQ192MHz = 1,/*!< HFRC2FQ192MHz : Use HFRC2-192MHz                                         */
48900 } CLKGEN_MISC_USEHFRC2FQ192MHZ_Enum;
48901 
48902 /* ==========================================  CLKGEN MISC USEHFRC2FQ96MHZ [3..3]  =========================================== */
48903 typedef enum {                                  /*!< CLKGEN_MISC_USEHFRC2FQ96MHZ                                               */
48904   CLKGEN_MISC_USEHFRC2FQ96MHZ_HFRCFQ96MHz = 0,  /*!< HFRCFQ96MHz : Use HFRC-96MHz                                              */
48905   CLKGEN_MISC_USEHFRC2FQ96MHZ_HFRC2FQ96MHz = 1, /*!< HFRC2FQ96MHz : Use HFRC2-96MHz                                            */
48906 } CLKGEN_MISC_USEHFRC2FQ96MHZ_Enum;
48907 
48908 /* ==========================================  CLKGEN MISC USEHFRC2FQ48MHZ [2..2]  =========================================== */
48909 typedef enum {                                  /*!< CLKGEN_MISC_USEHFRC2FQ48MHZ                                               */
48910   CLKGEN_MISC_USEHFRC2FQ48MHZ_HFRCFQ48MHz = 0,  /*!< HFRCFQ48MHz : Use HFRC-48MHz                                              */
48911   CLKGEN_MISC_USEHFRC2FQ48MHZ_HFRC2FQ48MHz = 1, /*!< HFRC2FQ48MHz : Use HFRC2-48MHz                                            */
48912 } CLKGEN_MISC_USEHFRC2FQ48MHZ_Enum;
48913 
48914 /* ============================================  CLKGEN MISC FRCBURSTOFF [1..1]  ============================================= */
48915 typedef enum {                                  /*!< CLKGEN_MISC_FRCBURSTOFF                                                   */
48916   CLKGEN_MISC_FRCBURSTOFF_BURSTCLKON   = 0,     /*!< BURSTCLKON : fclk, hclk and fclk_wic are turned on during the
48917                                                      burst transition                                                          */
48918   CLKGEN_MISC_FRCBURSTOFF_BURSTCLKOFF  = 1,     /*!< BURSTCLKOFF : fclk, hclk and fclk are turned off during burst
48919                                                      transition                                                                */
48920 } CLKGEN_MISC_FRCBURSTOFF_Enum;
48921 
48922 /* ==============================================  CLKGEN MISC FRCHFRC [0..0]  =============================================== */
48923 typedef enum {                                  /*!< CLKGEN_MISC_FRCHFRC                                                       */
48924   CLKGEN_MISC_FRCHFRC_NOFRC            = 0,     /*!< NOFRC : HFRC stops in deep sleep mode                                     */
48925   CLKGEN_MISC_FRCHFRC_FRC              = 1,     /*!< FRC : HFRC runs in deep sleep mode                                        */
48926 } CLKGEN_MISC_FRCHFRC_Enum;
48927 
48928 /* ========================================================  HF2ADJ0  ======================================================== */
48929 /* =========================================  CLKGEN HF2ADJ0 HF2ADJFASTSTREN [1..1]  ========================================= */
48930 typedef enum {                                  /*!< CLKGEN_HF2ADJ0_HF2ADJFASTSTREN                                            */
48931   CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_DIS   = 0,     /*!< DIS : Fast_start_delay disable                                            */
48932   CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_EN    = 1,     /*!< EN : Fast_start_delay enable                                              */
48933 } CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Enum;
48934 
48935 /* ============================================  CLKGEN HF2ADJ0 HF2ADJEN [0..0]  ============================================= */
48936 typedef enum {                                  /*!< CLKGEN_HF2ADJ0_HF2ADJEN                                                   */
48937   CLKGEN_HF2ADJ0_HF2ADJEN_DIS          = 0,     /*!< DIS : HF2ADJ disable                                                      */
48938   CLKGEN_HF2ADJ0_HF2ADJEN_EN           = 1,     /*!< EN : HF2ADJ enable                                                        */
48939 } CLKGEN_HF2ADJ0_HF2ADJEN_Enum;
48940 
48941 /* ========================================================  HF2ADJ1  ======================================================== */
48942 /* ==========================================  CLKGEN HF2ADJ1 HF2ADJTRIMEN [0..2]  =========================================== */
48943 typedef enum {                                  /*!< CLKGEN_HF2ADJ1_HF2ADJTRIMEN                                               */
48944   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN0 = 0,     /*!< TRIM_EN0 : 0                                                              */
48945   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN1 = 1,     /*!< TRIM_EN1 : HF2ADJTRIMOUT                                                  */
48946   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN2 = 2,     /*!< TRIM_EN2 : HF2ADJTRIMOFFSET                                               */
48947   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN3 = 3,     /*!< TRIM_EN3 : HF2ADJTRIMOUT + HF2ADJTRIMOFFSET                               */
48948   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN4 = 4,     /*!< TRIM_EN4 : HF2TUNE                                                        */
48949   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN5 = 5,     /*!< TRIM_EN5 : HF2ADJTRIMOUT + HF2TUNE                                        */
48950   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN6 = 6,     /*!< TRIM_EN6 : HF2ADJTRIMOFFSET + HF2TUNE                                     */
48951   CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN7 = 7,     /*!< TRIM_EN7 : HF2ADJTRIMOUT + HF2ADJTRIMOFFSET + HF2TUNE                     */
48952 } CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Enum;
48953 
48954 /* ========================================================  HF2ADJ2  ======================================================== */
48955 /* =======================================  CLKGEN HF2ADJ2 HF2ADJXTALDIVRATIO [0..1]  ======================================== */
48956 typedef enum {                                  /*!< CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO                                         */
48957   CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M = 0,/*!< XTAL32M : XTAL32MHz                                                       */
48958   CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV2 = 1,/*!< XTAL32M_DIV2 : XTAL32MHz / 2                                         */
48959   CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV4 = 2,/*!< XTAL32M_DIV4 : XTAL32MHz / 4                                         */
48960   CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV8 = 3,/*!< XTAL32M_DIV8 : XTAL32MHz / 8                                         */
48961 } CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Enum;
48962 
48963 /* ========================================================  HF2VAL  ========================================================= */
48964 /* =======================================================  LFRCCTRL  ======================================================== */
48965 /* ======================================================  DISPCLKCTRL  ====================================================== */
48966 /* =========================================  CLKGEN DISPCLKCTRL DISPCLKSEL [4..5]  ========================================== */
48967 typedef enum {                                  /*!< CLKGEN_DISPCLKCTRL_DISPCLKSEL                                             */
48968   CLKGEN_DISPCLKCTRL_DISPCLKSEL_OFF    = 0,     /*!< OFF : Static value of 0 selected for DPHY clock input                     */
48969   CLKGEN_DISPCLKCTRL_DISPCLKSEL_HFRC48 = 1,     /*!< HFRC48 : 48MHz sourced from the HFRC                                      */
48970   CLKGEN_DISPCLKCTRL_DISPCLKSEL_HFRC96 = 2,     /*!< HFRC96 : 96MHz sourced from the HFRC                                      */
48971   CLKGEN_DISPCLKCTRL_DISPCLKSEL_DPHYPLL = 3,    /*!< DPHYPLL : DPHY PLL                                                        */
48972 } CLKGEN_DISPCLKCTRL_DISPCLKSEL_Enum;
48973 
48974 /* ==========================================  CLKGEN DISPCLKCTRL PLLCLKSEL [0..1]  ========================================== */
48975 typedef enum {                                  /*!< CLKGEN_DISPCLKCTRL_PLLCLKSEL                                              */
48976   CLKGEN_DISPCLKCTRL_PLLCLKSEL_OFF     = 0,     /*!< OFF : Static value of 0 selected for DPHY clock input                     */
48977   CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFRC12  = 1,     /*!< HFRC12 : 12MHz sourced from the HFRC                                      */
48978   CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFRC6   = 2,     /*!< HFRC6 : 6MHz sourced from the HFRC                                        */
48979   CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFXT_16 = 3,     /*!< HFXT_16 : High Frequency XTAL input (16MHz)                               */
48980 } CLKGEN_DISPCLKCTRL_PLLCLKSEL_Enum;
48981 
48982 /* =====================================================  CLKGENSPARES  ====================================================== */
48983 /* ===================================================  HFRCIDLECOUNTERS  ==================================================== */
48984 /* =======================================================  INTRPTEN  ======================================================== */
48985 /* ======================================================  INTRPTSTAT  ======================================================= */
48986 /* =======================================================  INTRPTCLR  ======================================================= */
48987 /* =======================================================  INTRPTSET  ======================================================= */
48988 
48989 
48990 /* =========================================================================================================================== */
48991 /* ================                                            CPU                                            ================ */
48992 /* =========================================================================================================================== */
48993 
48994 /* =======================================================  CACHECFG  ======================================================== */
48995 /* ==============================================  CPU CACHECFG CONFIG [4..7]  =============================================== */
48996 typedef enum {                                  /*!< CPU_CACHECFG_CONFIG                                                       */
48997   CPU_CACHECFG_CONFIG_W1_128B_512E     = 4,     /*!< W1_128B_512E : Direct mapped, 128-bit linesize, 512 entries
48998                                                      (4 SRAMs active)                                                          */
48999   CPU_CACHECFG_CONFIG_W2_128B_512E     = 5,     /*!< W2_128B_512E : Two-way set associative, 128-bit linesize, 512
49000                                                      entries (8 SRAMs active)                                                  */
49001   CPU_CACHECFG_CONFIG_W1_128B_1024E    = 8,     /*!< W1_128B_1024E : Direct mapped, 128-bit linesize, 1024 entries
49002                                                      (8 SRAMs active)                                                          */
49003   CPU_CACHECFG_CONFIG_W1_128B_2048E    = 12,    /*!< W1_128B_2048E : Direct mapped, 128-bit linesize, 2048 entries
49004                                                      (4 SRAMs active)                                                          */
49005   CPU_CACHECFG_CONFIG_W2_128B_2048E    = 13,    /*!< W2_128B_2048E : Two-way set associative, 128-bit linesize, 2048
49006                                                      entries (8 SRAMs active)                                                  */
49007   CPU_CACHECFG_CONFIG_W1_128B_4096E    = 14,    /*!< W1_128B_4096E : Direct mapped, 128-bit linesize, 4096 entries
49008                                                      (8 SRAMs active)                                                          */
49009 } CPU_CACHECFG_CONFIG_Enum;
49010 
49011 /* =======================================================  CACHECTRL  ======================================================= */
49012 /* ============================================  CPU CACHECTRL RESETSTAT [1..1]  ============================================= */
49013 typedef enum {                                  /*!< CPU_CACHECTRL_RESETSTAT                                                   */
49014   CPU_CACHECTRL_RESETSTAT_CLEAR        = 1,     /*!< CLEAR : Clear Cache Stats                                                 */
49015   CPU_CACHECTRL_RESETSTAT_DEFAULT      = 0,     /*!< DEFAULT : default Cache Stats                                             */
49016 } CPU_CACHECTRL_RESETSTAT_Enum;
49017 
49018 /* =======================================================  NCR0START  ======================================================= */
49019 /* ========================================================  NCR0END  ======================================================== */
49020 /* =======================================================  NCR1START  ======================================================= */
49021 /* ========================================================  NCR1END  ======================================================== */
49022 /* ========================================================  DAXICFG  ======================================================== */
49023 /* ==========================================  CPU DAXICFG MRUGROUPLEVEL [24..25]  =========================================== */
49024 typedef enum {                                  /*!< CPU_DAXICFG_MRUGROUPLEVEL                                                 */
49025   CPU_DAXICFG_MRUGROUPLEVEL_MAX        = 0,     /*!< MAX : Maximum level for current number of buffers enabled.                */
49026   CPU_DAXICFG_MRUGROUPLEVEL_ONELESSTHANMAX = 1, /*!< ONELESSTHANMAX : One less than maximum level or zero for current
49027                                                      number of buffers enabled.                                                */
49028   CPU_DAXICFG_MRUGROUPLEVEL_TWOLESSTHANMAX = 2, /*!< TWOLESSTHANMAX : Two less than maximum level or zero for current
49029                                                      number of buffers enabled.                                                */
49030   CPU_DAXICFG_MRUGROUPLEVEL_THREELESSTHANMAX = 3,/*!< THREELESSTHANMAX : Three less than maximum level or zero for
49031                                                      current number of buffers enabled.                                        */
49032 } CPU_DAXICFG_MRUGROUPLEVEL_Enum;
49033 
49034 /* ===========================================  CPU DAXICFG AGINGCOUNTER [16..20]  =========================================== */
49035 typedef enum {                                  /*!< CPU_DAXICFG_AGINGCOUNTER                                                  */
49036   CPU_DAXICFG_AGINGCOUNTER_ONE         = 0,     /*!< ONE : One step per age                                                    */
49037   CPU_DAXICFG_AGINGCOUNTER_TWO         = 1,     /*!< TWO : Two steps per age                                                   */
49038   CPU_DAXICFG_AGINGCOUNTER_FOUR        = 2,     /*!< FOUR : Four steps per age                                                 */
49039   CPU_DAXICFG_AGINGCOUNTER_EIGHT       = 3,     /*!< EIGHT : EIGHT steps per age                                               */
49040   CPU_DAXICFG_AGINGCOUNTER_SIXTEEN     = 4,     /*!< SIXTEEN : Sixteen steps per age                                           */
49041   CPU_DAXICFG_AGINGCOUNTER_THIRTYTWO   = 5,     /*!< THIRTYTWO : Thirty-two steps per age                                      */
49042   CPU_DAXICFG_AGINGCOUNTER_SIXTYFOUR   = 6,     /*!< SIXTYFOUR : 64 steps per age                                              */
49043   CPU_DAXICFG_AGINGCOUNTER_ONEHUNDREDTWENTYEIGHT = 7,/*!< ONEHUNDREDTWENTYEIGHT : One hundred twenty-eight steps per age       */
49044   CPU_DAXICFG_AGINGCOUNTER_TWOHUNDEREDFIFTYSIX = 8,/*!< TWOHUNDEREDFIFTYSIX : Two hundred fifty-six steps per age              */
49045   CPU_DAXICFG_AGINGCOUNTER_FIVEHUNDREDTWELVE = 9,/*!< FIVEHUNDREDTWELVE : Five hundred twelve steps per age                    */
49046   CPU_DAXICFG_AGINGCOUNTER_ONEK        = 10,    /*!< ONEK : One thousand twenty-four steps per age                             */
49047   CPU_DAXICFG_AGINGCOUNTER_TWOK        = 11,    /*!< TWOK : Two thousand forty-eight steps per age                             */
49048   CPU_DAXICFG_AGINGCOUNTER_FOURK       = 12,    /*!< FOURK : Four thousand ninety-six steps per age                            */
49049   CPU_DAXICFG_AGINGCOUNTER_EIGHTK      = 13,    /*!< EIGHTK : Eight thousand one hundred ninety-two steps per age              */
49050   CPU_DAXICFG_AGINGCOUNTER_SIXTEENK    = 14,    /*!< SIXTEENK : Sixteen thousand three hundred eighty-four steps
49051                                                      per age                                                                   */
49052   CPU_DAXICFG_AGINGCOUNTER_THIRTYTWOK  = 15,    /*!< THIRTYTWOK : Thirty-two thousand seven hundred sixty-eight steps
49053                                                      per age                                                                   */
49054   CPU_DAXICFG_AGINGCOUNTER_SIXTYFOURK  = 16,    /*!< SIXTYFOURK : Sixty-fix thousand five hundred thirty-six steps
49055                                                      per age                                                                   */
49056 } CPU_DAXICFG_AGINGCOUNTER_Enum;
49057 
49058 /* ===========================================  CPU DAXICFG BUFFERENABLE [8..11]  ============================================ */
49059 typedef enum {                                  /*!< CPU_DAXICFG_BUFFERENABLE                                                  */
49060   CPU_DAXICFG_BUFFERENABLE_ONE         = 0,     /*!< ONE : One buffer mode enabled.                                            */
49061   CPU_DAXICFG_BUFFERENABLE_TWO         = 1,     /*!< TWO : Two buffers enabled.                                                */
49062   CPU_DAXICFG_BUFFERENABLE_THREE       = 2,     /*!< THREE : Three buffers enabled.                                            */
49063   CPU_DAXICFG_BUFFERENABLE_FOUR        = 3,     /*!< FOUR : Four buffers enabled.                                              */
49064   CPU_DAXICFG_BUFFERENABLE_FIVE        = 4,     /*!< FIVE : Five buffers enabled.                                              */
49065   CPU_DAXICFG_BUFFERENABLE_SIX         = 5,     /*!< SIX : Six buffers enabled.                                                */
49066   CPU_DAXICFG_BUFFERENABLE_SEVEN       = 6,     /*!< SEVEN : Seven buffers enabled.                                            */
49067   CPU_DAXICFG_BUFFERENABLE_EIGHT       = 7,     /*!< EIGHT : Eight buffers enabled.                                            */
49068   CPU_DAXICFG_BUFFERENABLE_THIRTEEN    = 8,     /*!< THIRTEEN : Eight buffers enabled.                                         */
49069   CPU_DAXICFG_BUFFERENABLE_FOURTEEN    = 9,     /*!< FOURTEEN : Eight buffers enabled.                                         */
49070   CPU_DAXICFG_BUFFERENABLE_FIFTEEN     = 10,    /*!< FIFTEEN : Eight buffers enabled.                                          */
49071   CPU_DAXICFG_BUFFERENABLE_SIXTEEN     = 11,    /*!< SIXTEEN : Eight buffers enabled.                                          */
49072   CPU_DAXICFG_BUFFERENABLE_TWENTYNINE  = 12,    /*!< TWENTYNINE : Twenty-nine buffers enabled.                                 */
49073   CPU_DAXICFG_BUFFERENABLE_THIRTY      = 13,    /*!< THIRTY : Thirty buffers enabled.                                          */
49074   CPU_DAXICFG_BUFFERENABLE_THIRTYONE   = 14,    /*!< THIRTYONE : Thirty-one buffers enabled.                                   */
49075   CPU_DAXICFG_BUFFERENABLE_THIRTYTWO   = 15,    /*!< THIRTYTWO : Thirty-two buffers enabled.                                   */
49076 } CPU_DAXICFG_BUFFERENABLE_Enum;
49077 
49078 /* =========================================  CPU DAXICFG DAXISTATECLKGATEEN [5..5]  ========================================= */
49079 typedef enum {                                  /*!< CPU_DAXICFG_DAXISTATECLKGATEEN                                            */
49080   CPU_DAXICFG_DAXISTATECLKGATEEN_EN    = 0,     /*!< EN : Enable clock gating of DAXI state.                                   */
49081   CPU_DAXICFG_DAXISTATECLKGATEEN_DIS   = 1,     /*!< DIS : Disable clock gating of DAXI state.                                 */
49082 } CPU_DAXICFG_DAXISTATECLKGATEEN_Enum;
49083 
49084 /* =========================================  CPU DAXICFG DAXIDATACLKGATEEN [4..4]  ========================================== */
49085 typedef enum {                                  /*!< CPU_DAXICFG_DAXIDATACLKGATEEN                                             */
49086   CPU_DAXICFG_DAXIDATACLKGATEEN_EN     = 0,     /*!< EN : Enable clock gating of DAXI line buffer data.                        */
49087   CPU_DAXICFG_DAXIDATACLKGATEEN_DIS    = 1,     /*!< DIS : Disable clock gating of DAXI line buffer data.                      */
49088 } CPU_DAXICFG_DAXIDATACLKGATEEN_Enum;
49089 
49090 /* ==========================================  CPU DAXICFG DAXIBECLKGATEEN [3..3]  =========================================== */
49091 typedef enum {                                  /*!< CPU_DAXICFG_DAXIBECLKGATEEN                                               */
49092   CPU_DAXICFG_DAXIBECLKGATEEN_EN       = 0,     /*!< EN : Enable clock gating of DAXI line buffer byte enables.                */
49093   CPU_DAXICFG_DAXIBECLKGATEEN_DIS      = 1,     /*!< DIS : Disable clock gating of DAXI line buffer byte enables.              */
49094 } CPU_DAXICFG_DAXIBECLKGATEEN_Enum;
49095 
49096 /* ==========================================  CPU DAXICFG DAXIPASSTHROUGH [2..2]  =========================================== */
49097 typedef enum {                                  /*!< CPU_DAXICFG_DAXIPASSTHROUGH                                               */
49098   CPU_DAXICFG_DAXIPASSTHROUGH_DIS      = 0,     /*!< DIS : Disable pass through mode, caching lines in DAXI enabled.           */
49099   CPU_DAXICFG_DAXIPASSTHROUGH_EN       = 1,     /*!< EN : Enable pass through mode, caching lines in DAXI disabled.            */
49100 } CPU_DAXICFG_DAXIPASSTHROUGH_Enum;
49101 
49102 /* ============================================  CPU DAXICFG AGINGSENABLE [1..1]  ============================================ */
49103 typedef enum {                                  /*!< CPU_DAXICFG_AGINGSENABLE                                                  */
49104   CPU_DAXICFG_AGINGSENABLE_DIS         = 0,     /*!< DIS : Flushing out shared entries using aging mechanism disabled.         */
49105   CPU_DAXICFG_AGINGSENABLE_EN          = 1,     /*!< EN : Flushing out shared entries using aging mechanism enabled.           */
49106 } CPU_DAXICFG_AGINGSENABLE_Enum;
49107 
49108 /* =============================================  CPU DAXICFG FLUSHLEVEL [0..0]  ============================================= */
49109 typedef enum {                                  /*!< CPU_DAXICFG_FLUSHLEVEL                                                    */
49110   CPU_DAXICFG_FLUSHLEVEL_TWO           = 0,     /*!< TWO : Flush out dirty buffers if 3 or more ane enabled and less
49111                                                      than two are free or if 2 are enabled and none are free.                  */
49112   CPU_DAXICFG_FLUSHLEVEL_THREE         = 1,     /*!< THREE : Flush out dirty buffers if 3 or more are enabled less
49113                                                      than three are free or if 2 are enabled and less then two
49114                                                      are free.                                                                 */
49115 } CPU_DAXICFG_FLUSHLEVEL_Enum;
49116 
49117 /* =======================================================  DAXICTRL  ======================================================== */
49118 /* ====================================================  ICODEFAULTADDR  ===================================================== */
49119 /* ====================================================  DCODEFAULTADDR  ===================================================== */
49120 /* =====================================================  SYSFAULTADDR  ====================================================== */
49121 /* ======================================================  FAULTSTATUS  ====================================================== */
49122 /* ============================================  CPU FAULTSTATUS SYSFAULT [2..2]  ============================================ */
49123 typedef enum {                                  /*!< CPU_FAULTSTATUS_SYSFAULT                                                  */
49124   CPU_FAULTSTATUS_SYSFAULT_NOFAULT     = 0,     /*!< NOFAULT : No bus fault has been detected.                                 */
49125   CPU_FAULTSTATUS_SYSFAULT_FAULT       = 1,     /*!< FAULT : Bus fault detected.                                               */
49126 } CPU_FAULTSTATUS_SYSFAULT_Enum;
49127 
49128 /* ===========================================  CPU FAULTSTATUS DCODEFAULT [1..1]  =========================================== */
49129 typedef enum {                                  /*!< CPU_FAULTSTATUS_DCODEFAULT                                                */
49130   CPU_FAULTSTATUS_DCODEFAULT_NOFAULT   = 0,     /*!< NOFAULT : No DCODE fault has been detected.                               */
49131   CPU_FAULTSTATUS_DCODEFAULT_FAULT     = 1,     /*!< FAULT : DCODE fault detected.                                             */
49132 } CPU_FAULTSTATUS_DCODEFAULT_Enum;
49133 
49134 /* ===========================================  CPU FAULTSTATUS ICODEFAULT [0..0]  =========================================== */
49135 typedef enum {                                  /*!< CPU_FAULTSTATUS_ICODEFAULT                                                */
49136   CPU_FAULTSTATUS_ICODEFAULT_NOFAULT   = 0,     /*!< NOFAULT : No ICODE fault has been detected.                               */
49137   CPU_FAULTSTATUS_ICODEFAULT_FAULT     = 1,     /*!< FAULT : ICODE fault detected.                                             */
49138 } CPU_FAULTSTATUS_ICODEFAULT_Enum;
49139 
49140 /* ====================================================  FAULTCAPTUREEN  ===================================================== */
49141 /* =======================================  CPU FAULTCAPTUREEN FAULTCAPTUREEN [0..0]  ======================================== */
49142 typedef enum {                                  /*!< CPU_FAULTCAPTUREEN_FAULTCAPTUREEN                                         */
49143   CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0,    /*!< DIS : Disable fault capture.                                              */
49144   CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1,     /*!< EN : Enable fault capture.                                                */
49145 } CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum;
49146 
49147 /* =========================================================  INTEN  ========================================================= */
49148 /* ========================================================  INTSTAT  ======================================================== */
49149 /* ========================================================  INTCLR  ========================================================= */
49150 /* ========================================================  INTSET  ========================================================= */
49151 /* =====================================================  WRITEERRADDR  ====================================================== */
49152 /* =========================================================  DMON0  ========================================================= */
49153 /* =========================================================  DMON1  ========================================================= */
49154 /* =========================================================  DMON2  ========================================================= */
49155 /* =========================================================  DMON3  ========================================================= */
49156 /* =========================================================  IMON0  ========================================================= */
49157 /* =========================================================  IMON1  ========================================================= */
49158 /* =========================================================  IMON2  ========================================================= */
49159 /* =========================================================  IMON3  ========================================================= */
49160 
49161 
49162 /* =========================================================================================================================== */
49163 /* ================                                          CRYPTO                                           ================ */
49164 /* =========================================================================================================================== */
49165 
49166 /* ======================================================  MEMORYMAP0  ======================================================= */
49167 /* ======================================================  MEMORYMAP1  ======================================================= */
49168 /* ======================================================  MEMORYMAP2  ======================================================= */
49169 /* ======================================================  MEMORYMAP3  ======================================================= */
49170 /* ======================================================  MEMORYMAP4  ======================================================= */
49171 /* ======================================================  MEMORYMAP5  ======================================================= */
49172 /* ======================================================  MEMORYMAP6  ======================================================= */
49173 /* ======================================================  MEMORYMAP7  ======================================================= */
49174 /* ======================================================  MEMORYMAP8  ======================================================= */
49175 /* ======================================================  MEMORYMAP9  ======================================================= */
49176 /* ======================================================  MEMORYMAP10  ====================================================== */
49177 /* ======================================================  MEMORYMAP11  ====================================================== */
49178 /* ======================================================  MEMORYMAP12  ====================================================== */
49179 /* ======================================================  MEMORYMAP13  ====================================================== */
49180 /* ======================================================  MEMORYMAP14  ====================================================== */
49181 /* ======================================================  MEMORYMAP15  ====================================================== */
49182 /* ======================================================  MEMORYMAP16  ====================================================== */
49183 /* ======================================================  MEMORYMAP17  ====================================================== */
49184 /* ======================================================  MEMORYMAP18  ====================================================== */
49185 /* ======================================================  MEMORYMAP19  ====================================================== */
49186 /* ======================================================  MEMORYMAP20  ====================================================== */
49187 /* ======================================================  MEMORYMAP21  ====================================================== */
49188 /* ======================================================  MEMORYMAP22  ====================================================== */
49189 /* ======================================================  MEMORYMAP23  ====================================================== */
49190 /* ======================================================  MEMORYMAP24  ====================================================== */
49191 /* ======================================================  MEMORYMAP25  ====================================================== */
49192 /* ======================================================  MEMORYMAP26  ====================================================== */
49193 /* ======================================================  MEMORYMAP27  ====================================================== */
49194 /* ======================================================  MEMORYMAP28  ====================================================== */
49195 /* ======================================================  MEMORYMAP29  ====================================================== */
49196 /* ======================================================  MEMORYMAP30  ====================================================== */
49197 /* ======================================================  MEMORYMAP31  ====================================================== */
49198 /* ========================================================  OPCODE  ========================================================= */
49199 /* =============================================  CRYPTO OPCODE OPCODE [27..31]  ============================================= */
49200 typedef enum {                                  /*!< CRYPTO_OPCODE_OPCODE                                                      */
49201   CRYPTO_OPCODE_OPCODE_ADD             = 4,     /*!< ADD : Add,Inc opcode                                                      */
49202   CRYPTO_OPCODE_OPCODE_SUB             = 5,     /*!< SUB : Sub,Dec,Neg opcode                                                  */
49203   CRYPTO_OPCODE_OPCODE_MODADD          = 6,     /*!< MODADD : ModAdd,ModInc opcode                                             */
49204   CRYPTO_OPCODE_OPCODE_MODSUB          = 7,     /*!< MODSUB : ModSub,ModDec,ModNeg opcode                                      */
49205   CRYPTO_OPCODE_OPCODE_AND             = 8,     /*!< AND : AND,TST0,CLR0 opcode                                                */
49206   CRYPTO_OPCODE_OPCODE_OR              = 9,     /*!< OR : OR,COPY,SET0 opcode                                                  */
49207   CRYPTO_OPCODE_OPCODE_XOR             = 10,    /*!< XOR : XOR,FLIP0,INVERT,COMPARE opcode                                     */
49208   CRYPTO_OPCODE_OPCODE_SHR0            = 12,    /*!< SHR0 : SHR0 opcode                                                        */
49209   CRYPTO_OPCODE_OPCODE_SHR1            = 13,    /*!< SHR1 : SHR1 opcode                                                        */
49210   CRYPTO_OPCODE_OPCODE_SHL0            = 14,    /*!< SHL0 : SHL0 opcode                                                        */
49211   CRYPTO_OPCODE_OPCODE_SHL1            = 15,    /*!< SHL1 : SHL1 opcode                                                        */
49212   CRYPTO_OPCODE_OPCODE_MULLOW          = 16,    /*!< MULLOW : MulLow opcode                                                    */
49213   CRYPTO_OPCODE_OPCODE_MODMUL          = 17,    /*!< MODMUL : ModMul opcode                                                    */
49214   CRYPTO_OPCODE_OPCODE_MODMULN         = 18,    /*!< MODMULN : ModMulN opcode                                                  */
49215   CRYPTO_OPCODE_OPCODE_MODEXP          = 19,    /*!< MODEXP : ModExp opcode                                                    */
49216   CRYPTO_OPCODE_OPCODE_DIVISION        = 20,    /*!< DIVISION : Division opcode                                                */
49217   CRYPTO_OPCODE_OPCODE_DIV             = 21,    /*!< DIV : Div opcode                                                          */
49218   CRYPTO_OPCODE_OPCODE_MODDIV          = 22,    /*!< MODDIV : ModDiv opcode                                                    */
49219   CRYPTO_OPCODE_OPCODE_TERMINATE       = 0,     /*!< TERMINATE : Terminate opcode                                              */
49220 } CRYPTO_OPCODE_OPCODE_Enum;
49221 
49222 /* ======================================================  NNPT0T1ADDR  ====================================================== */
49223 /* =======================================================  PKASTATUS  ======================================================= */
49224 /* ======================================================  PKASWRESET  ======================================================= */
49225 /* =========================================================  PKAL0  ========================================================= */
49226 /* =========================================================  PKAL1  ========================================================= */
49227 /* =========================================================  PKAL2  ========================================================= */
49228 /* =========================================================  PKAL3  ========================================================= */
49229 /* =========================================================  PKAL4  ========================================================= */
49230 /* =========================================================  PKAL5  ========================================================= */
49231 /* =========================================================  PKAL6  ========================================================= */
49232 /* =========================================================  PKAL7  ========================================================= */
49233 /* ======================================================  PKAPIPERDY  ======================================================= */
49234 /* ========================================================  PKADONE  ======================================================== */
49235 /* =====================================================  PKAMONSELECT  ====================================================== */
49236 /* ======================================================  PKAVERSION  ======================================================= */
49237 /* ======================================================  PKAMONREAD  ======================================================= */
49238 /* ======================================================  PKASRAMADDR  ====================================================== */
49239 /* =====================================================  PKASRAMWDATA  ====================================================== */
49240 /* =====================================================  PKASRAMRDATA  ====================================================== */
49241 /* =====================================================  PKASRAMWRCLR  ====================================================== */
49242 /* =====================================================  PKASRAMRADDR  ====================================================== */
49243 /* =====================================================  PKAWORDACCESS  ===================================================== */
49244 /* ======================================================  PKABUFFADDR  ====================================================== */
49245 /* ========================================================  RNGIMR  ========================================================= */
49246 /* ========================================================  RNGISR  ========================================================= */
49247 /* ==========================================  CRYPTO RNGISR WHICHKATERR [25..26]  =========================================== */
49248 typedef enum {                                  /*!< CRYPTO_RNGISR_WHICHKATERR                                                 */
49249   CRYPTO_RNGISR_WHICHKATERR_INSTANT_1  = 0,     /*!< INSTANT_1 : first test of instantiation                                   */
49250   CRYPTO_RNGISR_WHICHKATERR_INSTANT_2  = 1,     /*!< INSTANT_2 : second test of instantiation                                  */
49251   CRYPTO_RNGISR_WHICHKATERR_RESEED_1   = 2,     /*!< RESEED_1 : first test of reseeding                                        */
49252   CRYPTO_RNGISR_WHICHKATERR_RESEED_2   = 3,     /*!< RESEED_2 : second test of reseeding                                       */
49253 } CRYPTO_RNGISR_WHICHKATERR_Enum;
49254 
49255 /* ========================================================  RNGICR  ========================================================= */
49256 /* ======================================================  TRNGCONFIG  ======================================================= */
49257 /* ============================================  CRYPTO TRNGCONFIG SOPSEL [2..2]  ============================================ */
49258 typedef enum {                                  /*!< CRYPTO_TRNGCONFIG_SOPSEL                                                  */
49259   CRYPTO_TRNGCONFIG_SOPSEL_SOP_DATA_1  = 1,     /*!< SOP_DATA_1 : sop_data port reflects TRNG output (EHR_DATA).               */
49260   CRYPTO_TRNGCONFIG_SOPSEL_SOP_DATA_2  = 0,     /*!< SOP_DATA_2 : sop_data port reflects PRNG output (RNG_READOUT).
49261                                                      Note: Secure output is used for direct connection of the
49262                                                      RNG block outputs to an engine input key.                                 */
49263 } CRYPTO_TRNGCONFIG_SOPSEL_Enum;
49264 
49265 /* =======================================================  TRNGVALID  ======================================================= */
49266 /* =======================================================  EHRDATA0  ======================================================== */
49267 /* =======================================================  EHRDATA1  ======================================================== */
49268 /* =======================================================  EHRDATA2  ======================================================== */
49269 /* =======================================================  EHRDATA3  ======================================================== */
49270 /* =======================================================  EHRDATA4  ======================================================== */
49271 /* =======================================================  EHRDATA5  ======================================================== */
49272 /* ====================================================  RNDSOURCEENABLE  ==================================================== */
49273 /* ======================================================  SAMPLECNT1  ======================================================= */
49274 /* ===================================================  AUTOCORRSTATISTIC  =================================================== */
49275 /* ===================================================  TRNGDEBUGCONTROL  ==================================================== */
49276 /* ======================================================  RNGSWRESET  ======================================================= */
49277 /* ====================================================  RNGDEBUGENINPUT  ==================================================== */
49278 /* ========================================================  RNGBUSY  ======================================================== */
49279 /* ====================================================  RSTBITSCOUNTER  ===================================================== */
49280 /* ======================================================  RNGVERSION  ======================================================= */
49281 /* ========================================  CRYPTO RNGVERSION RNGUSE5SBOXES [7..7]  ========================================= */
49282 typedef enum {                                  /*!< CRYPTO_RNGVERSION_RNGUSE5SBOXES                                           */
49283   CRYPTO_RNGVERSION_RNGUSE5SBOXES_20_SBOX_AES = 0,/*!< 20_SBOX_AES : 20 SBOX AES                                               */
49284   CRYPTO_RNGVERSION_RNGUSE5SBOXES_5_SBOX_AES = 1,/*!< 5_SBOX_AES : 5 SBOX AES                                                  */
49285 } CRYPTO_RNGVERSION_RNGUSE5SBOXES_Enum;
49286 
49287 /* =======================================  CRYPTO RNGVERSION RESEEDINGEXISTS [6..6]  ======================================== */
49288 typedef enum {                                  /*!< CRYPTO_RNGVERSION_RESEEDINGEXISTS                                         */
49289   CRYPTO_RNGVERSION_RESEEDINGEXISTS_EXISTS = 1, /*!< EXISTS : exists                                                           */
49290   CRYPTO_RNGVERSION_RESEEDINGEXISTS_NORESEED = 0,/*!< NORESEED : Reseed does not exists                                        */
49291 } CRYPTO_RNGVERSION_RESEEDINGEXISTS_Enum;
49292 
49293 /* ==========================================  CRYPTO RNGVERSION KATEXISTS [5..5]  =========================================== */
49294 typedef enum {                                  /*!< CRYPTO_RNGVERSION_KATEXISTS                                               */
49295   CRYPTO_RNGVERSION_KATEXISTS_NO_EXIST = 0,     /*!< NO_EXIST : does not exist                                                 */
49296   CRYPTO_RNGVERSION_KATEXISTS_EXISTS   = 1,     /*!< EXISTS : exists                                                           */
49297 } CRYPTO_RNGVERSION_KATEXISTS_Enum;
49298 
49299 /* ==========================================  CRYPTO RNGVERSION PRNGEXISTS [4..4]  ========================================== */
49300 typedef enum {                                  /*!< CRYPTO_RNGVERSION_PRNGEXISTS                                              */
49301   CRYPTO_RNGVERSION_PRNGEXISTS_NO_EXIST = 0,    /*!< NO_EXIST : does not exist                                                 */
49302   CRYPTO_RNGVERSION_PRNGEXISTS_EXISTS  = 1,     /*!< EXISTS : exists                                                           */
49303 } CRYPTO_RNGVERSION_PRNGEXISTS_Enum;
49304 
49305 /* ======================================  CRYPTO RNGVERSION TRNGTESTSBYPASSEN [3..3]  ======================================= */
49306 typedef enum {                                  /*!< CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN                                       */
49307   CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_TRNG_NE = 0,/*!< TRNG_NE : trng tests bypass not enabled                                 */
49308   CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_TRNG_E = 1,/*!< TRNG_E : trng tests bypass enabled                                       */
49309 } CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Enum;
49310 
49311 /* ========================================  CRYPTO RNGVERSION AUTOCORREXISTS [2..2]  ======================================== */
49312 typedef enum {                                  /*!< CRYPTO_RNGVERSION_AUTOCORREXISTS                                          */
49313   CRYPTO_RNGVERSION_AUTOCORREXISTS_NO_EXIST = 0,/*!< NO_EXIST : does not exist                                                 */
49314   CRYPTO_RNGVERSION_AUTOCORREXISTS_EXISTS = 1,  /*!< EXISTS : exists                                                           */
49315 } CRYPTO_RNGVERSION_AUTOCORREXISTS_Enum;
49316 
49317 /* =========================================  CRYPTO RNGVERSION CRNGTEXISTS [1..1]  ========================================== */
49318 typedef enum {                                  /*!< CRYPTO_RNGVERSION_CRNGTEXISTS                                             */
49319   CRYPTO_RNGVERSION_CRNGTEXISTS_NO_EXIST = 0,   /*!< NO_EXIST : does not exist                                                 */
49320   CRYPTO_RNGVERSION_CRNGTEXISTS_EXISTS = 1,     /*!< EXISTS : exists                                                           */
49321 } CRYPTO_RNGVERSION_CRNGTEXISTS_Enum;
49322 
49323 /* =========================================  CRYPTO RNGVERSION EHRWIDTH192 [0..0]  ========================================== */
49324 typedef enum {                                  /*!< CRYPTO_RNGVERSION_EHRWIDTH192                                             */
49325   CRYPTO_RNGVERSION_EHRWIDTH192_128_EHR = 0,    /*!< 128_EHR : 128 bit EHR                                                     */
49326   CRYPTO_RNGVERSION_EHRWIDTH192_192_EHR = 1,    /*!< 192_EHR : 192 bit EHR                                                     */
49327 } CRYPTO_RNGVERSION_EHRWIDTH192_Enum;
49328 
49329 /* =====================================================  RNGCLKENABLE  ====================================================== */
49330 /* =====================================================  RNGDMAENABLE  ====================================================== */
49331 /* =====================================================  RNGDMASRCMASK  ===================================================== */
49332 /* ====================================================  RNGDMASRAMADDR  ===================================================== */
49333 /* ====================================================  RNGWATCHDOGVAL  ===================================================== */
49334 /* =====================================================  RNGDMASTATUS  ====================================================== */
49335 /* ===================================================  CHACHACONTROLREG  ==================================================== */
49336 /* ======================================  CRYPTO CHACHACONTROLREG NUMOFROUNDS [4..5]  ======================================= */
49337 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_NUMOFROUNDS                                       */
49338   CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_20_ROUNDS = 0,/*!< 20_ROUNDS : 20 rounds                                                 */
49339   CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_12_ROUNDS = 1,/*!< 12_ROUNDS : 12 rounds                                                 */
49340   CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_8_ROUNDS = 2,/*!< 8_ROUNDS : 8 rounds                                                    */
49341   CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_N_A = 3,  /*!< N_A : Not applicable                                                      */
49342 } CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Enum;
49343 
49344 /* =========================================  CRYPTO CHACHACONTROLREG KEYLEN [3..3]  ========================================= */
49345 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_KEYLEN                                            */
49346   CRYPTO_CHACHACONTROLREG_KEYLEN_256_BIT = 0,   /*!< 256_BIT : 256 bit.                                                        */
49347   CRYPTO_CHACHACONTROLREG_KEYLEN_128_BIT = 1,   /*!< 128_BIT : 128 bit.                                                        */
49348 } CRYPTO_CHACHACONTROLREG_KEYLEN_Enum;
49349 
49350 /* ===================================  CRYPTO CHACHACONTROLREG CALCKEYFORPOLY1305 [2..2]  =================================== */
49351 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305                                */
49352   CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_DISABLE = 0,/*!< DISABLE : disable.                                               */
49353   CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_ENABLE = 1,/*!< ENABLE : enable.                                                  */
49354 } CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Enum;
49355 
49356 /* ======================================  CRYPTO CHACHACONTROLREG INITFROMHOST [1..1]  ====================================== */
49357 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_INITFROMHOST                                      */
49358   CRYPTO_CHACHACONTROLREG_INITFROMHOST_DISABLE = 0,/*!< DISABLE : disable.                                                     */
49359   CRYPTO_CHACHACONTROLREG_INITFROMHOST_ENABLE = 1,/*!< ENABLE : enable.                                                        */
49360 } CRYPTO_CHACHACONTROLREG_INITFROMHOST_Enum;
49361 
49362 /* =====================================  CRYPTO CHACHACONTROLREG CHACHAORSALSA [0..0]  ====================================== */
49363 typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_CHACHAORSALSA                                     */
49364   CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_CHACHA = 0,/*!< CHACHA : ChaCha mode,                                                  */
49365   CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_SALSA = 1,/*!< SALSA : Salsa mode.                                                     */
49366 } CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Enum;
49367 
49368 /* =====================================================  CHACHAVERSION  ===================================================== */
49369 /* ======================================================  CHACHAKEY0  ======================================================= */
49370 /* ======================================================  CHACHAKEY1  ======================================================= */
49371 /* ======================================================  CHACHAKEY2  ======================================================= */
49372 /* ======================================================  CHACHAKEY3  ======================================================= */
49373 /* ======================================================  CHACHAKEY4  ======================================================= */
49374 /* ======================================================  CHACHAKEY5  ======================================================= */
49375 /* ======================================================  CHACHAKEY6  ======================================================= */
49376 /* ======================================================  CHACHAKEY7  ======================================================= */
49377 /* =======================================================  CHACHAIV0  ======================================================= */
49378 /* =======================================================  CHACHAIV1  ======================================================= */
49379 /* ======================================================  CHACHABUSY  ======================================================= */
49380 /* =====================================================  CHACHAHWFLAGS  ===================================================== */
49381 /* ========================================  CRYPTO CHACHAHWFLAGS FASTCHACHA [2..2]  ========================================= */
49382 typedef enum {                                  /*!< CRYPTO_CHACHAHWFLAGS_FASTCHACHA                                           */
49383   CRYPTO_CHACHAHWFLAGS_FASTCHACHA_DISABLE = 0,  /*!< DISABLE : disable.                                                        */
49384   CRYPTO_CHACHAHWFLAGS_FASTCHACHA_ENABLE = 1,   /*!< ENABLE : enable.                                                          */
49385 } CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Enum;
49386 
49387 /* ========================================  CRYPTO CHACHAHWFLAGS SALSAEXISTS [1..1]  ======================================== */
49388 typedef enum {                                  /*!< CRYPTO_CHACHAHWFLAGS_SALSAEXISTS                                          */
49389   CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_DISABLE = 0, /*!< DISABLE : disable.                                                        */
49390   CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_ENABLE = 1,  /*!< ENABLE : enable.                                                          */
49391 } CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Enum;
49392 
49393 /* =======================================  CRYPTO CHACHAHWFLAGS CHACHAEXISTS [0..0]  ======================================== */
49394 typedef enum {                                  /*!< CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS                                         */
49395   CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_DISABLE = 0,/*!< DISABLE : disable.                                                        */
49396   CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_ENABLE = 1, /*!< ENABLE : enable.                                                          */
49397 } CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Enum;
49398 
49399 /* ===================================================  CHACHABLOCKCNTLSB  =================================================== */
49400 /* ===================================================  CHACHABLOCKCNTMSB  =================================================== */
49401 /* =====================================================  CHACHASWRESET  ===================================================== */
49402 /* ===================================================  CHACHAFORPOLYKEY0  =================================================== */
49403 /* ===================================================  CHACHAFORPOLYKEY1  =================================================== */
49404 /* ===================================================  CHACHAFORPOLYKEY2  =================================================== */
49405 /* ===================================================  CHACHAFORPOLYKEY3  =================================================== */
49406 /* ===================================================  CHACHAFORPOLYKEY4  =================================================== */
49407 /* ===================================================  CHACHAFORPOLYKEY5  =================================================== */
49408 /* ===================================================  CHACHAFORPOLYKEY6  =================================================== */
49409 /* ===================================================  CHACHAFORPOLYKEY7  =================================================== */
49410 /* ==============================================  CHACHABYTEWORDORDERCNTLREG  =============================================== */
49411 /* =============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADOUTBYTEORDER [4..4]  ============================== */
49412 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER                     */
49413   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_DISABLE = 0,/*!< DISABLE : disable.                                    */
49414   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each byte in each word output (b0->b3,
49415                                                      b1->b2, b2->b1,b3->b0))                                                   */
49416 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Enum;
49417 
49418 /* =============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADOUTWORDORDER [3..3]  ============================== */
49419 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER                     */
49420   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_DISABLE = 0,/*!< DISABLE : disable.                                    */
49421   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each word in 128 bit output ( w0->w3,
49422                                                      w1->w2, w2->w1,w3-w0))                                                    */
49423 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Enum;
49424 
49425 /* ===========================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHACOREMATRIXLBEORDER [2..2]  =========================== */
49426 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER                */
49427   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_DISABLE = 0,/*!< DISABLE : disable.                               */
49428   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each quarter of a matrix (m[0-127]->m[384-511],
49429                                                      m[128-255]->m[256-383], m[256-383]->m[128-255], m[384-511]->m[0-127]))    */
49430 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Enum;
49431 
49432 /* ==============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADINBYTEORDER [1..1]  ============================== */
49433 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER                      */
49434   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_DISABLE = 0,/*!< DISABLE : disable.                                     */
49435   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each byte in each word input (b0->b3,
49436                                                      b1->b2, b2->b1,b3->b0))                                                   */
49437 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Enum;
49438 
49439 /* ==============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADINWORDORDER [0..0]  ============================== */
49440 typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER                      */
49441   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_DISABLE = 0,/*!< DISABLE : disable.                                     */
49442   CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each word in 128 bit input ( w0->w3,
49443                                                      w1->w2, w2->w1,w3-w0))                                                    */
49444 } CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Enum;
49445 
49446 /* ====================================================  CHACHADEBUGREG  ===================================================== */
49447 /* ===================================  CRYPTO CHACHADEBUGREG CHACHADEBUGFSMSTATE [0..1]  ==================================== */
49448 typedef enum {                                  /*!< CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE                                 */
49449   CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_IDLE_STATE = 0,/*!< IDLE_STATE : The idle state.                                   */
49450   CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_INIT_STATE = 1,/*!< INIT_STATE : The init state.                                   */
49451 } CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Enum;
49452 
49453 /* =======================================================  AESKEY00  ======================================================== */
49454 /* =======================================================  AESKEY01  ======================================================== */
49455 /* =======================================================  AESKEY02  ======================================================== */
49456 /* =======================================================  AESKEY03  ======================================================== */
49457 /* =======================================================  AESKEY04  ======================================================== */
49458 /* =======================================================  AESKEY05  ======================================================== */
49459 /* =======================================================  AESKEY06  ======================================================== */
49460 /* =======================================================  AESKEY07  ======================================================== */
49461 /* =======================================================  AESKEY10  ======================================================== */
49462 /* =======================================================  AESKEY11  ======================================================== */
49463 /* =======================================================  AESKEY12  ======================================================== */
49464 /* =======================================================  AESKEY13  ======================================================== */
49465 /* =======================================================  AESKEY14  ======================================================== */
49466 /* =======================================================  AESKEY15  ======================================================== */
49467 /* =======================================================  AESKEY16  ======================================================== */
49468 /* =======================================================  AESKEY17  ======================================================== */
49469 /* ========================================================  AESIV00  ======================================================== */
49470 /* ========================================================  AESIV01  ======================================================== */
49471 /* ========================================================  AESIV02  ======================================================== */
49472 /* ========================================================  AESIV03  ======================================================== */
49473 /* ========================================================  AESIV10  ======================================================== */
49474 /* ========================================================  AESIV11  ======================================================== */
49475 /* ========================================================  AESIV12  ======================================================== */
49476 /* ========================================================  AESIV13  ======================================================== */
49477 /* =======================================================  AESCTR00  ======================================================== */
49478 /* =======================================================  AESCTR01  ======================================================== */
49479 /* =======================================================  AESCTR02  ======================================================== */
49480 /* =======================================================  AESCTR03  ======================================================== */
49481 /* ========================================================  AESBUSY  ======================================================== */
49482 /* =========================================================  AESSK  ========================================================= */
49483 /* ======================================================  AESCMACINIT  ====================================================== */
49484 /* ========================================================  AESSK1  ========================================================= */
49485 /* ===================================================  AESREMAININGBYTES  =================================================== */
49486 /* ======================================================  AESCONTROL  ======================================================= */
49487 /* ======================================  CRYPTO AESCONTROL AESXORCRYPTOKEY [29..29]  ======================================= */
49488 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESXORCRYPTOKEY                                         */
49489   CRYPTO_AESCONTROL_AESXORCRYPTOKEY_CRYPTOKEY = 0,/*!< CRYPTOKEY : The value that is written to AES_KEY0 is the value
49490                                                      of the HW cryptokey, as is.                                               */
49491   CRYPTO_AESCONTROL_AESXORCRYPTOKEY_CRYPTOKEY_XOR = 1,/*!< CRYPTOKEY_XOR : The value that is written to AES_KEY0 is the
49492                                                      value of the HW cryptokey xored with the current value
49493                                                      of AES_KEY0.                                                              */
49494 } CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Enum;
49495 
49496 /* =====================================  CRYPTO AESCONTROL AESOUTMIDTUNTOHASH [28..28]  ===================================== */
49497 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH                                      */
49498   CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_HASH_2 = 0,/*!< HASH_2 : The AES engine writes to the hash the result of the
49499                                                      second tunnel stage.                                                      */
49500   CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_HASH_1 = 1,/*!< HASH_1 : The AES engine writes to the hash the result of the
49501                                                      first tunnel stage.                                                       */
49502 } CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Enum;
49503 
49504 /* ======================================  CRYPTO AESCONTROL AESTUNNELB1PADEN [26..26]  ====================================== */
49505 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNELB1PADEN                                        */
49506   CRYPTO_AESCONTROL_AESTUNNELB1PADEN_DATA_NO_PAD = 0,/*!< DATA_NO_PAD : The data input to the second tunnel block is not
49507                                                      padded with zeros.                                                        */
49508   CRYPTO_AESCONTROL_AESTUNNELB1PADEN_DATA_IS_PAD = 1,/*!< DATA_IS_PAD : The data input to the second tunnel block is padded
49509                                                      with zeros.                                                               */
49510 } CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Enum;
49511 
49512 /* ===================================  CRYPTO AESCONTROL AESOUTPUTMIDTUNNELDATA [25..25]  =================================== */
49513 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA                                  */
49514   CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_ENGINE_RSLT_2 = 0,/*!< ENGINE_RSLT_2 : The AES engine outputs the result of the second
49515                                                      tunnel stage (standard tunneling).                                        */
49516   CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_ENGINE_RSLT_1 = 1,/*!< ENGINE_RSLT_1 : The AES engine outputs the result of the first
49517                                                      tunnel stage.                                                             */
49518 } CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Enum;
49519 
49520 /* =====================================  CRYPTO AESCONTROL AESTUNNEL0ENCRYPT [24..24]  ====================================== */
49521 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT                                       */
49522   CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_TUNNEL_1_D = 0,/*!< TUNNEL_1_D : the first tunnel stage performs decrypt operations.     */
49523   CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_TUNNEL_1_E = 1,/*!< TUNNEL_1_E : the first tunnel stage performs encrypt operations.     */
49524 } CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Enum;
49525 
49526 /* ==================================  CRYPTO AESCONTROL AESTUNB1USESPADDEDDATAIN [23..23]  ================================== */
49527 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN                                */
49528   CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_BLOCK_1 = 0,/*!< BLOCK_1 : the output of the first block (standard tunneling
49529                                                      operation).                                                               */
49530   CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_AFTER_PAD = 1,/*!< AFTER_PAD : data_in after padding rather than the output of
49531                                                      the first block.                                                          */
49532 } CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Enum;
49533 
49534 /* =====================================  CRYPTO AESCONTROL AESTUNNEL1DECRYPT [22..22]  ====================================== */
49535 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT                                       */
49536   CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_TUNNEL_2_E = 0,/*!< TUNNEL_2_E : the second tunnel stage performs encrypt operations.    */
49537   CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_TUNNEL_2_D = 1,/*!< TUNNEL_2_D : the second tunnel stage performs decrypt operations.    */
49538 } CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Enum;
49539 
49540 /* ===========================================  CRYPTO AESCONTROL NKKEY1 [14..15]  =========================================== */
49541 typedef enum {                                  /*!< CRYPTO_AESCONTROL_NKKEY1                                                  */
49542   CRYPTO_AESCONTROL_NKKEY1_128_BITS_KEY = 0,    /*!< 128_BITS_KEY : 128 bits key                                               */
49543   CRYPTO_AESCONTROL_NKKEY1_192_BITS_KEY = 1,    /*!< 192_BITS_KEY : 192 bits key                                               */
49544   CRYPTO_AESCONTROL_NKKEY1_256_BITS_KEY = 2,    /*!< 256_BITS_KEY : 256 bits key                                               */
49545   CRYPTO_AESCONTROL_NKKEY1_N_A         = 3,     /*!< N_A : Not applicable                                                      */
49546 } CRYPTO_AESCONTROL_NKKEY1_Enum;
49547 
49548 /* ===========================================  CRYPTO AESCONTROL NKKEY0 [12..13]  =========================================== */
49549 typedef enum {                                  /*!< CRYPTO_AESCONTROL_NKKEY0                                                  */
49550   CRYPTO_AESCONTROL_NKKEY0_128_BITS_KEY = 0,    /*!< 128_BITS_KEY : 128 bits key                                               */
49551   CRYPTO_AESCONTROL_NKKEY0_192_BITS_KEY = 1,    /*!< 192_BITS_KEY : 192 bits key                                               */
49552   CRYPTO_AESCONTROL_NKKEY0_256_BITS_KEY = 2,    /*!< 256_BITS_KEY : 256 bits key                                               */
49553   CRYPTO_AESCONTROL_NKKEY0_N_A         = 3,     /*!< N_A : Not applicable                                                      */
49554 } CRYPTO_AESCONTROL_NKKEY0_Enum;
49555 
49556 /* =======================================  CRYPTO AESCONTROL AESTUNNELISON [10..10]  ======================================== */
49557 typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNELISON                                           */
49558   CRYPTO_AESCONTROL_AESTUNNELISON_STD_NONTUNNEL = 0,/*!< STD_NONTUNNEL : standard non-tunneling operations                     */
49559   CRYPTO_AESCONTROL_AESTUNNELISON_TUNNEL = 1,   /*!< TUNNEL : tunneling operations.                                            */
49560 } CRYPTO_AESCONTROL_AESTUNNELISON_Enum;
49561 
49562 /* ===========================================  CRYPTO AESCONTROL MODEKEY1 [5..7]  =========================================== */
49563 typedef enum {                                  /*!< CRYPTO_AESCONTROL_MODEKEY1                                                */
49564   CRYPTO_AESCONTROL_MODEKEY1_ECB       = 0,     /*!< ECB : ECB modekey1                                                        */
49565   CRYPTO_AESCONTROL_MODEKEY1_CBC       = 1,     /*!< CBC : CBC modekey1                                                        */
49566   CRYPTO_AESCONTROL_MODEKEY1_CTR       = 2,     /*!< CTR : CTR modekey1                                                        */
49567   CRYPTO_AESCONTROL_MODEKEY1_CBC_MAC   = 3,     /*!< CBC_MAC : CBC MAC modekey1                                                */
49568   CRYPTO_AESCONTROL_MODEKEY1_XEX_XTS   = 4,     /*!< XEX_XTS : XEX_XTS modekey1                                                */
49569   CRYPTO_AESCONTROL_MODEKEY1_XCBC_MAC  = 5,     /*!< XCBC_MAC : XCBC MAC modekey1                                              */
49570   CRYPTO_AESCONTROL_MODEKEY1_OFB       = 6,     /*!< OFB : OFB modekey1                                                        */
49571   CRYPTO_AESCONTROL_MODEKEY1_CMAC      = 7,     /*!< CMAC : CMAC modekey1                                                      */
49572 } CRYPTO_AESCONTROL_MODEKEY1_Enum;
49573 
49574 /* ===========================================  CRYPTO AESCONTROL MODEKEY0 [2..4]  =========================================== */
49575 typedef enum {                                  /*!< CRYPTO_AESCONTROL_MODEKEY0                                                */
49576   CRYPTO_AESCONTROL_MODEKEY0_ECB       = 0,     /*!< ECB : ECB modekey0                                                        */
49577   CRYPTO_AESCONTROL_MODEKEY0_CBC       = 1,     /*!< CBC : CBC modekey0                                                        */
49578   CRYPTO_AESCONTROL_MODEKEY0_CTR       = 2,     /*!< CTR : CTR modekey0                                                        */
49579   CRYPTO_AESCONTROL_MODEKEY0_CBCMAC    = 3,     /*!< CBCMAC : CBCMAC modekey0                                                  */
49580   CRYPTO_AESCONTROL_MODEKEY0_XEX_XTS   = 4,     /*!< XEX_XTS : XEX XTS modekey0                                                */
49581   CRYPTO_AESCONTROL_MODEKEY0_XCBC_MAC  = 5,     /*!< XCBC_MAC : XCBC MAC modekey0                                              */
49582   CRYPTO_AESCONTROL_MODEKEY0_OFB       = 6,     /*!< OFB : OFB modekey0                                                        */
49583   CRYPTO_AESCONTROL_MODEKEY0_CMAC      = 7,     /*!< CMAC : CMAC modekey0                                                      */
49584 } CRYPTO_AESCONTROL_MODEKEY0_Enum;
49585 
49586 /* ===========================================  CRYPTO AESCONTROL DECKEY0 [0..0]  ============================================ */
49587 typedef enum {                                  /*!< CRYPTO_AESCONTROL_DECKEY0                                                 */
49588   CRYPTO_AESCONTROL_DECKEY0_ENCRYPT    = 0,     /*!< ENCRYPT : Encrypt                                                         */
49589   CRYPTO_AESCONTROL_DECKEY0_DECRYPT    = 1,     /*!< DECRYPT : Decrypt                                                         */
49590 } CRYPTO_AESCONTROL_DECKEY0_Enum;
49591 
49592 /* ======================================================  AESHWFLAGS  ======================================================= */
49593 /* ===================================================  AESCTRNOINCREMENT  =================================================== */
49594 /* ======================================================  AESDFAISON  ======================================================= */
49595 /* ====================================================  AESDFAERRSTATUS  ==================================================== */
49596 /* ===================================================  AESCMACSIZE0KICK  ==================================================== */
49597 /* ========================================================  HASHH0  ========================================================= */
49598 /* ========================================================  HASHH1  ========================================================= */
49599 /* ========================================================  HASHH2  ========================================================= */
49600 /* ========================================================  HASHH3  ========================================================= */
49601 /* ========================================================  HASHH4  ========================================================= */
49602 /* ========================================================  HASHH5  ========================================================= */
49603 /* ========================================================  HASHH6  ========================================================= */
49604 /* ========================================================  HASHH7  ========================================================= */
49605 /* ========================================================  HASHH8  ========================================================= */
49606 /* =====================================================  AUTOHWPADDING  ===================================================== */
49607 /* ======================================================  HASHXORDIN  ======================================================= */
49608 /* =====================================================  LOADINITSTATE  ===================================================== */
49609 /* =====================================================  HASHSELAESMAC  ===================================================== */
49610 /* =========================================  CRYPTO HASHSELAESMAC GHASHSEL [1..1]  ========================================== */
49611 typedef enum {                                  /*!< CRYPTO_HASHSELAESMAC_GHASHSEL                                             */
49612   CRYPTO_HASHSELAESMAC_GHASHSEL_HASH_MOD = 0,   /*!< HASH_MOD : select the hash module                                         */
49613   CRYPTO_HASHSELAESMAC_GHASHSEL_GHASH_MOD = 1,  /*!< GHASH_MOD : select the ghash module                                       */
49614 } CRYPTO_HASHSELAESMAC_GHASHSEL_Enum;
49615 
49616 /* =======================================  CRYPTO HASHSELAESMAC HASHSELAESMAC [0..0]  ======================================= */
49617 typedef enum {                                  /*!< CRYPTO_HASHSELAESMAC_HASHSELAESMAC                                        */
49618   CRYPTO_HASHSELAESMAC_HASHSELAESMAC_HASH_MOD = 0,/*!< HASH_MOD : select the hash module                                       */
49619   CRYPTO_HASHSELAESMAC_HASHSELAESMAC_MAC_MOD = 1,/*!< MAC_MOD : select the AES mac module                                      */
49620 } CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Enum;
49621 
49622 /* ======================================================  HASHVERSION  ====================================================== */
49623 /* ======================================================  HASHCONTROL  ====================================================== */
49624 /* ===========================================  CRYPTO HASHCONTROL MODE01 [0..1]  ============================================ */
49625 typedef enum {                                  /*!< CRYPTO_HASHCONTROL_MODE01                                                 */
49626   CRYPTO_HASHCONTROL_MODE01_MD5        = 0,     /*!< MD5 : MD5 if present                                                      */
49627   CRYPTO_HASHCONTROL_MODE01_SHA_1      = 1,     /*!< SHA_1 : SHA-1                                                             */
49628   CRYPTO_HASHCONTROL_MODE01_SHA_256    = 2,     /*!< SHA_256 : SHA-256                                                         */
49629 } CRYPTO_HASHCONTROL_MODE01_Enum;
49630 
49631 /* =======================================================  HASHPADEN  ======================================================= */
49632 /* ======================================================  HASHPADCFG  ======================================================= */
49633 /* ======================================================  HASHCURLEN0  ====================================================== */
49634 /* ======================================================  HASHCURLEN1  ====================================================== */
49635 /* =======================================================  HASHPARAM  ======================================================= */
49636 /* ====================================================  HASHAESSWRESET  ===================================================== */
49637 /* =====================================================  HASHENDIANESS  ===================================================== */
49638 /* =====================================================  AESCLKENABLE  ====================================================== */
49639 /* =============================================  CRYPTO AESCLKENABLE EN [0..0]  ============================================= */
49640 typedef enum {                                  /*!< CRYPTO_AESCLKENABLE_EN                                                    */
49641   CRYPTO_AESCLKENABLE_EN_CLK_E         = 1,     /*!< CLK_E : the AES clock is enabled.                                         */
49642   CRYPTO_AESCLKENABLE_EN_CLK_D         = 0,     /*!< CLK_D : the AES clock is disabled.                                        */
49643 } CRYPTO_AESCLKENABLE_EN_Enum;
49644 
49645 /* =====================================================  HASHCLKENABLE  ===================================================== */
49646 /* ============================================  CRYPTO HASHCLKENABLE EN [0..0]  ============================================= */
49647 typedef enum {                                  /*!< CRYPTO_HASHCLKENABLE_EN                                                   */
49648   CRYPTO_HASHCLKENABLE_EN_HASH_E       = 1,     /*!< HASH_E : the HASH clock is enabled.                                       */
49649   CRYPTO_HASHCLKENABLE_EN_HASH_D       = 0,     /*!< HASH_D : the HASH clock is disabled.                                      */
49650 } CRYPTO_HASHCLKENABLE_EN_Enum;
49651 
49652 /* =====================================================  PKACLKENABLE  ====================================================== */
49653 /* =============================================  CRYPTO PKACLKENABLE EN [0..0]  ============================================= */
49654 typedef enum {                                  /*!< CRYPTO_PKACLKENABLE_EN                                                    */
49655   CRYPTO_PKACLKENABLE_EN_PKA_E         = 1,     /*!< PKA_E : the PKA clock is enabled.                                         */
49656   CRYPTO_PKACLKENABLE_EN_PKA_D         = 0,     /*!< PKA_D : the PKA clock is disabled.                                        */
49657 } CRYPTO_PKACLKENABLE_EN_Enum;
49658 
49659 /* =====================================================  DMACLKENABLE  ====================================================== */
49660 /* =============================================  CRYPTO DMACLKENABLE EN [0..0]  ============================================= */
49661 typedef enum {                                  /*!< CRYPTO_DMACLKENABLE_EN                                                    */
49662   CRYPTO_DMACLKENABLE_EN_DMA_E         = 1,     /*!< DMA_E : the DMA clock is enabled.                                         */
49663   CRYPTO_DMACLKENABLE_EN_DMA_D         = 0,     /*!< DMA_D : the DMA clock is disabled.                                        */
49664 } CRYPTO_DMACLKENABLE_EN_Enum;
49665 
49666 /* =======================================================  CLKSTATUS  ======================================================= */
49667 /* =========================================  CRYPTO CLKSTATUS DMACLKSTATUS [8..8]  ========================================== */
49668 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_DMACLKSTATUS                                             */
49669   CRYPTO_CLKSTATUS_DMACLKSTATUS_DMA_E  = 1,     /*!< DMA_E : the DMA clock is enabled.                                         */
49670   CRYPTO_CLKSTATUS_DMACLKSTATUS_DMA_D  = 0,     /*!< DMA_D : the DMA clock is disabled.                                        */
49671 } CRYPTO_CLKSTATUS_DMACLKSTATUS_Enum;
49672 
49673 /* ========================================  CRYPTO CLKSTATUS CHACHACLKSTATUS [7..7]  ======================================== */
49674 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_CHACHACLKSTATUS                                          */
49675   CRYPTO_CLKSTATUS_CHACHACLKSTATUS_CHACHA_E = 1,/*!< CHACHA_E : the CHACHA clock is enabled.                                   */
49676   CRYPTO_CLKSTATUS_CHACHACLKSTATUS_CHACHA_D = 0,/*!< CHACHA_D : the CHACHA clock is disabled.                                  */
49677 } CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Enum;
49678 
49679 /* =========================================  CRYPTO CLKSTATUS PKACLKSTATUS [3..3]  ========================================== */
49680 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_PKACLKSTATUS                                             */
49681   CRYPTO_CLKSTATUS_PKACLKSTATUS_PKA_E  = 1,     /*!< PKA_E : the PKA clock is enabled.                                         */
49682   CRYPTO_CLKSTATUS_PKACLKSTATUS_PKA_D  = 0,     /*!< PKA_D : the PKA clock is disabled.                                        */
49683 } CRYPTO_CLKSTATUS_PKACLKSTATUS_Enum;
49684 
49685 /* =========================================  CRYPTO CLKSTATUS HASHCLKSTATUS [2..2]  ========================================= */
49686 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_HASHCLKSTATUS                                            */
49687   CRYPTO_CLKSTATUS_HASHCLKSTATUS_HASH_E = 1,    /*!< HASH_E : the HASH clock is enabled.                                       */
49688   CRYPTO_CLKSTATUS_HASHCLKSTATUS_HASH_D = 0,    /*!< HASH_D : the HASH clock is disabled.                                      */
49689 } CRYPTO_CLKSTATUS_HASHCLKSTATUS_Enum;
49690 
49691 /* =========================================  CRYPTO CLKSTATUS AESCLKSTATUS [0..0]  ========================================== */
49692 typedef enum {                                  /*!< CRYPTO_CLKSTATUS_AESCLKSTATUS                                             */
49693   CRYPTO_CLKSTATUS_AESCLKSTATUS_CLK_E  = 1,     /*!< CLK_E : the AES clock is enabled.                                         */
49694   CRYPTO_CLKSTATUS_AESCLKSTATUS_CLK_D  = 0,     /*!< CLK_D : the AES clock is disabled.                                        */
49695 } CRYPTO_CLKSTATUS_AESCLKSTATUS_Enum;
49696 
49697 /* ====================================================  CHACHACLKENABLE  ==================================================== */
49698 /* ===========================================  CRYPTO CHACHACLKENABLE EN [0..0]  ============================================ */
49699 typedef enum {                                  /*!< CRYPTO_CHACHACLKENABLE_EN                                                 */
49700   CRYPTO_CHACHACLKENABLE_EN_CHACHA_E   = 1,     /*!< CHACHA_E : the CHACHA SALSA clock is enabled.                             */
49701   CRYPTO_CHACHACLKENABLE_EN_CHACHA_D   = 0,     /*!< CHACHA_D : the CHACHA SALSA clock is disabled.                            */
49702 } CRYPTO_CHACHACLKENABLE_EN_Enum;
49703 
49704 /* =======================================================  CRYPTOCTL  ======================================================= */
49705 /* =============================================  CRYPTO CRYPTOCTL MODE [0..4]  ============================================== */
49706 typedef enum {                                  /*!< CRYPTO_CRYPTOCTL_MODE                                                     */
49707   CRYPTO_CRYPTOCTL_MODE_BYPASS         = 0,     /*!< BYPASS : bypass                                                           */
49708   CRYPTO_CRYPTOCTL_MODE_AES            = 1,     /*!< AES : aes                                                                 */
49709   CRYPTO_CRYPTOCTL_MODE_AES_TO_HASH    = 2,     /*!< AES_TO_HASH : aes to hash                                                 */
49710   CRYPTO_CRYPTOCTL_MODE_AES_AND_HASH   = 3,     /*!< AES_AND_HASH : aes and hash                                               */
49711   CRYPTO_CRYPTOCTL_MODE_DES            = 4,     /*!< DES : des                                                                 */
49712   CRYPTO_CRYPTOCTL_MODE_DES_TO_HASH    = 5,     /*!< DES_TO_HASH : des to hash                                                 */
49713   CRYPTO_CRYPTOCTL_MODE_DES_AND_HASH   = 6,     /*!< DES_AND_HASH : des and hash                                               */
49714   CRYPTO_CRYPTOCTL_MODE_HASH           = 7,     /*!< HASH : hash                                                               */
49715   CRYPTO_CRYPTOCTL_MODE_AES_MAC_AND_BYPASS = 9, /*!< AES_MAC_AND_BYPASS : aes mac and bypass                                   */
49716   CRYPTO_CRYPTOCTL_MODE_AES_TO_HASH_AND_DOUT = 10,/*!< AES_TO_HASH_AND_DOUT : aes to hash and _dout                            */
49717   CRYPTO_CRYPTOCTL_MODE_Reserved1      = 11,    /*!< Reserved1 : reserved1                                                     */
49718   CRYPTO_CRYPTOCTL_MODE_Reserved2      = 8,     /*!< Reserved2 : reserved2                                                     */
49719 } CRYPTO_CRYPTOCTL_MODE_Enum;
49720 
49721 /* ======================================================  CRYPTOBUSY  ======================================================= */
49722 /* ==========================================  CRYPTO CRYPTOBUSY CRYPTOBUSY [0..0]  ========================================== */
49723 typedef enum {                                  /*!< CRYPTO_CRYPTOBUSY_CRYPTOBUSY                                              */
49724   CRYPTO_CRYPTOBUSY_CRYPTOBUSY_READY   = 0,     /*!< READY : Ready                                                             */
49725   CRYPTO_CRYPTOBUSY_CRYPTOBUSY_BUSY    = 1,     /*!< BUSY : Busy                                                               */
49726 } CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Enum;
49727 
49728 /* =======================================================  HASHBUSY  ======================================================== */
49729 /* ============================================  CRYPTO HASHBUSY HASHBUSY [0..0]  ============================================ */
49730 typedef enum {                                  /*!< CRYPTO_HASHBUSY_HASHBUSY                                                  */
49731   CRYPTO_HASHBUSY_HASHBUSY_READY       = 0,     /*!< READY : Ready                                                             */
49732   CRYPTO_HASHBUSY_HASHBUSY_BUSY        = 1,     /*!< BUSY : Busy                                                               */
49733 } CRYPTO_HASHBUSY_HASHBUSY_Enum;
49734 
49735 /* =======================================================  CONTEXTID  ======================================================= */
49736 /* =====================================================  GHASHSUBKEY00  ===================================================== */
49737 /* =====================================================  GHASHSUBKEY01  ===================================================== */
49738 /* =====================================================  GHASHSUBKEY02  ===================================================== */
49739 /* =====================================================  GHASHSUBKEY03  ===================================================== */
49740 /* =======================================================  GHASHIV00  ======================================================= */
49741 /* =======================================================  GHASHIV01  ======================================================= */
49742 /* =======================================================  GHASHIV02  ======================================================= */
49743 /* =======================================================  GHASHIV03  ======================================================= */
49744 /* =======================================================  GHASHBUSY  ======================================================= */
49745 /* =======================================================  GHASHINIT  ======================================================= */
49746 /* ======================================================  HOSTRGFIRR  ======================================================= */
49747 /* ======================================================  HOSTRGFIMR  ======================================================= */
49748 /* ======================================================  HOSTRGFICR  ======================================================= */
49749 /* =====================================================  HOSTRGFENDIAN  ===================================================== */
49750 /* ========================================  CRYPTO HOSTRGFENDIAN DINRDWBG [15..15]  ========================================= */
49751 typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DINRDWBG                                             */
49752   CRYPTO_HOSTRGFENDIAN_DINRDWBG_LE     = 0,     /*!< LE : little endian                                                        */
49753   CRYPTO_HOSTRGFENDIAN_DINRDWBG_BE     = 1,     /*!< BE : big endian                                                           */
49754 } CRYPTO_HOSTRGFENDIAN_DINRDWBG_Enum;
49755 
49756 /* ========================================  CRYPTO HOSTRGFENDIAN DOUTWRWBG [11..11]  ======================================== */
49757 typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DOUTWRWBG                                            */
49758   CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_LE    = 0,     /*!< LE : little endian                                                        */
49759   CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_BE    = 1,     /*!< BE : big endian                                                           */
49760 } CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Enum;
49761 
49762 /* ==========================================  CRYPTO HOSTRGFENDIAN DINRDBG [7..7]  ========================================== */
49763 typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DINRDBG                                              */
49764   CRYPTO_HOSTRGFENDIAN_DINRDBG_LE      = 0,     /*!< LE : little endian                                                        */
49765   CRYPTO_HOSTRGFENDIAN_DINRDBG_BE      = 1,     /*!< BE : big endian                                                           */
49766 } CRYPTO_HOSTRGFENDIAN_DINRDBG_Enum;
49767 
49768 /* =========================================  CRYPTO HOSTRGFENDIAN DOUTWRBG [3..3]  ========================================== */
49769 typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DOUTWRBG                                             */
49770   CRYPTO_HOSTRGFENDIAN_DOUTWRBG_LE     = 0,     /*!< LE : little endian                                                        */
49771   CRYPTO_HOSTRGFENDIAN_DOUTWRBG_BE     = 1,     /*!< BE : big endian                                                           */
49772 } CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Enum;
49773 
49774 /* ===================================================  HOSTRGFSIGNATURE  ==================================================== */
49775 /* =======================================================  HOSTBOOT  ======================================================== */
49776 /* ===================================================  HOSTCRYPTOKEYSEL  ==================================================== */
49777 /* ======================================  CRYPTO HOSTCRYPTOKEYSEL SELCRYPTOKEY [0..2]  ====================================== */
49778 typedef enum {                                  /*!< CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY                                      */
49779   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_RKEK = 0,/*!< RKEK : rkek                                                               */
49780   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Krtl = 1,/*!< Krtl : the Krtl.                                                          */
49781   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCP = 2, /*!< KCP : the provision key KCP.                                              */
49782   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCE = 3, /*!< KCE : the code encryption key KCE.                                        */
49783   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KPICV = 4,/*!< KPICV : the KPICV, The ICV provisioning key .                            */
49784   CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCEICV = 5,/*!< KCEICV : the code encryption key KCEICV Note: When 'kprtl_lock'
49785                                                      is set - kprtl will be masked (trying to load it will load
49786                                                      zeros to the AES key register. When 'kcertl_lock' is set
49787                                                      - kcertl will be masked (trying to load it will load zeros
49788                                                      to the AES key register. When scan_mode is asserted all
49789                                                      the RTL keys (Krtll) will be masked.                                      */
49790 } CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Enum;
49791 
49792 /* ================================================  HOSTCORECLKGATINGENABLE  ================================================ */
49793 /* =====================================================  HOSTCCISIDLE  ====================================================== */
49794 /* =====================================================  HOSTPOWERDOWN  ===================================================== */
49795 /* =================================================  HOSTREMOVEGHASHENGINE  ================================================= */
49796 /* ================================================  HOSTREMOVECHACHAENGINE  ================================================= */
49797 /* ======================================================  AHBMSINGLES  ====================================================== */
49798 /* =======================================================  AHBMHPROT  ======================================================= */
49799 /* =====================================================  AHBMHMASTLOCK  ===================================================== */
49800 /* ======================================================  AHBMHNONSEC  ====================================================== */
49801 /* =======================================================  DINBUFFER  ======================================================= */
49802 /* =====================================================  DINMEMDMABUSY  ===================================================== */
49803 /* =======================================  CRYPTO DINMEMDMABUSY DINMEMDMABUSY [0..0]  ======================================= */
49804 typedef enum {                                  /*!< CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY                                        */
49805   CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_busy = 1,  /*!< busy : DMA busy                                                           */
49806   CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_not = 0,   /*!< not : DMA not busy                                                        */
49807 } CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Enum;
49808 
49809 /* ======================================================  SRCLLIWORD0  ====================================================== */
49810 /* ======================================================  SRCLLIWORD1  ====================================================== */
49811 /* ======================================================  SRAMSRCADDR  ====================================================== */
49812 /* ====================================================  DINSRAMBYTESLEN  ==================================================== */
49813 /* ====================================================  DINSRAMDMABUSY  ===================================================== */
49814 /* ===========================================  CRYPTO DINSRAMDMABUSY BUSY [0..0]  =========================================== */
49815 typedef enum {                                  /*!< CRYPTO_DINSRAMDMABUSY_BUSY                                                */
49816   CRYPTO_DINSRAMDMABUSY_BUSY_BUSY      = 1,     /*!< BUSY : busy                                                               */
49817   CRYPTO_DINSRAMDMABUSY_BUSY_NOT_BUSY  = 0,     /*!< NOT_BUSY : not busy                                                       */
49818 } CRYPTO_DINSRAMDMABUSY_BUSY_Enum;
49819 
49820 /* ===================================================  DINSRAMENDIANNESS  =================================================== */
49821 /* ===================================  CRYPTO DINSRAMENDIANNESS SRAMDINENDIANNESS [0..0]  =================================== */
49822 typedef enum {                                  /*!< CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS                                */
49823   CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_BE = 1,/*!< BE : big-endianness                                                   */
49824   CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_LE = 0,/*!< LE : little endianness                                                */
49825 } CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Enum;
49826 
49827 /* ====================================================  DINCPUDATASIZE  ===================================================== */
49828 /* ======================================================  FIFOINEMPTY  ====================================================== */
49829 /* ====================================================  DINFIFORSTPNTR  ===================================================== */
49830 /* ======================================================  DOUTBUFFER  ======================================================= */
49831 /* ====================================================  DOUTMEMDMABUSY  ===================================================== */
49832 /* ======================================  CRYPTO DOUTMEMDMABUSY DOUTMEMDMABUSY [0..0]  ====================================== */
49833 typedef enum {                                  /*!< CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY                                      */
49834   CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_BUSY = 1,/*!< BUSY : busy                                                               */
49835   CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_NOT_BUSY = 0,/*!< NOT_BUSY : not busy                                                   */
49836 } CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Enum;
49837 
49838 /* ======================================================  DSTLLIWORD0  ====================================================== */
49839 /* ======================================================  DSTLLIWORD1  ====================================================== */
49840 /* =====================================================  SRAMDESTADDR  ====================================================== */
49841 /* ===================================================  DOUTSRAMBYTESLEN  ==================================================== */
49842 /* ====================================================  DOUTSRAMDMABUSY  ==================================================== */
49843 /* ==========================================  CRYPTO DOUTSRAMDMABUSY BUSY [0..0]  =========================================== */
49844 typedef enum {                                  /*!< CRYPTO_DOUTSRAMDMABUSY_BUSY                                               */
49845   CRYPTO_DOUTSRAMDMABUSY_BUSY_DATA_SRAM = 0,    /*!< DATA_SRAM : all data was written to SRAM.                                 */
49846   CRYPTO_DOUTSRAMDMABUSY_BUSY_DMA_BUSY = 1,     /*!< DMA_BUSY : DOUT SRAM DMA busy.                                            */
49847 } CRYPTO_DOUTSRAMDMABUSY_BUSY_Enum;
49848 
49849 /* ==================================================  DOUTSRAMENDIANNESS  =================================================== */
49850 /* ==================================  CRYPTO DOUTSRAMENDIANNESS DOUTSRAMENDIANNESS [0..0]  ================================== */
49851 typedef enum {                                  /*!< CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS                              */
49852   CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_BE = 1,/*!< BE : big-endianness                                                 */
49853   CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_LE = 0,/*!< LE : little endianness                                              */
49854 } CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Enum;
49855 
49856 /* =====================================================  READALIGNLAST  ===================================================== */
49857 /* =====================================================  DOUTFIFOEMPTY  ===================================================== */
49858 /* =======================================  CRYPTO DOUTFIFOEMPTY DOUTFIFOEMPTY [0..0]  ======================================= */
49859 typedef enum {                                  /*!< CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY                                        */
49860   CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_FIFO_NE = 0,/*!< FIFO_NE : DOUT FIFO is not empty                                         */
49861   CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_FIFO_EDOUT = 1,/*!< FIFO_EDOUT : FIFO is empty                                            */
49862 } CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Enum;
49863 
49864 /* =======================================================  SRAMDATA  ======================================================== */
49865 /* =======================================================  SRAMADDR  ======================================================== */
49866 /* =====================================================  SRAMDATAREADY  ===================================================== */
49867 /* =====================================================  PERIPHERALID4  ===================================================== */
49868 /* =====================================================  PERIPHERALID0  ===================================================== */
49869 /* =====================================================  PERIPHERALID1  ===================================================== */
49870 /* =====================================================  PERIPHERALID2  ===================================================== */
49871 /* =====================================================  PERIPHERALID3  ===================================================== */
49872 /* =====================================================  COMPONENTID0  ====================================================== */
49873 /* =====================================================  COMPONENTID1  ====================================================== */
49874 /* =====================================================  COMPONENTID2  ====================================================== */
49875 /* =====================================================  COMPONENTID3  ====================================================== */
49876 /* ======================================================  HOSTDCUEN0  ======================================================= */
49877 /* ======================================================  HOSTDCUEN1  ======================================================= */
49878 /* ======================================================  HOSTDCUEN2  ======================================================= */
49879 /* ======================================================  HOSTDCUEN3  ======================================================= */
49880 /* =====================================================  HOSTDCULOCK0  ====================================================== */
49881 /* =====================================================  HOSTDCULOCK1  ====================================================== */
49882 /* =====================================================  HOSTDCULOCK2  ====================================================== */
49883 /* =====================================================  HOSTDCULOCK3  ====================================================== */
49884 /* ===============================================  AOICVDCURESTRICTIONMASK0  ================================================ */
49885 /* ===============================================  AOICVDCURESTRICTIONMASK1  ================================================ */
49886 /* ===============================================  AOICVDCURESTRICTIONMASK2  ================================================ */
49887 /* ===============================================  AOICVDCURESTRICTIONMASK3  ================================================ */
49888 /* ===================================================  AOCCSECDEBUGRESET  =================================================== */
49889 /* ====================================================  HOSTAOLOCKBITS  ===================================================== */
49890 /* ====================================================  AOAPBFILTERING  ===================================================== */
49891 /* =======================================================  AOCCGPPC  ======================================================== */
49892 /* ====================================================  HOSTRGFCCSWRST  ===================================================== */
49893 /* =================================================  AIBFUSEPROGCOMPLETED  ================================================== */
49894 /* ====================================================  NVMDEBUGSTATUS  ===================================================== */
49895 /* ==========================================  CRYPTO NVMDEBUGSTATUS NVMSM [1..3]  =========================================== */
49896 typedef enum {                                  /*!< CRYPTO_NVMDEBUGSTATUS_NVMSM                                               */
49897   CRYPTO_NVMDEBUGSTATUS_NVMSM_IDLE     = 0,     /*!< IDLE : IDLE NVMSM                                                         */
49898   CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_DUMMY = 1,   /*!< READ_DUMMY : READ_DUMMY NVMSM                                             */
49899   CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_MAN_FLAG = 2,/*!< READ_MAN_FLAG : READ_MAN_FLAG NVMSM                                       */
49900   CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_OEM_FLAG = 3,/*!< READ_OEM_FLAG : READ_OEM_FLAG NVMSM                                       */
49901   CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_GPPC = 4,    /*!< READ_GPPC : READ_GPPC NVMSM                                               */
49902   CRYPTO_NVMDEBUGSTATUS_NVMSM_DECODE   = 5,     /*!< DECODE : DECODE NVMSM                                                     */
49903   CRYPTO_NVMDEBUGSTATUS_NVMSM_OTP_LCS_VALID = 6,/*!< OTP_LCS_VALID : OTP_LCS_VALID NVMSM                                       */
49904   CRYPTO_NVMDEBUGSTATUS_NVMSM_LCS_IS_VALID = 7, /*!< LCS_IS_VALID : LCS_IS_VALID NVMSM                                         */
49905 } CRYPTO_NVMDEBUGSTATUS_NVMSM_Enum;
49906 
49907 /* ======================================================  LCSISVALID  ======================================================= */
49908 /* =======================================================  NVMISIDLE  ======================================================= */
49909 /* ========================================================  LCSREG  ========================================================= */
49910 /* ==============================================  CRYPTO LCSREG LCSREG [0..2]  ============================================== */
49911 typedef enum {                                  /*!< CRYPTO_LCSREG_LCSREG                                                      */
49912   CRYPTO_LCSREG_LCSREG_CM              = 0,     /*!< CM : CM lifecycle state                                                   */
49913   CRYPTO_LCSREG_LCSREG_DM              = 1,     /*!< DM : DM lifecycle state                                                   */
49914   CRYPTO_LCSREG_LCSREG_SE              = 5,     /*!< SE : SE lifecycle state                                                   */
49915   CRYPTO_LCSREG_LCSREG_RMA             = 7,     /*!< RMA : RMA lifecycle state                                                 */
49916 } CRYPTO_LCSREG_LCSREG_Enum;
49917 
49918 /* ===================================================  HOSTSHADOWKDRREG  ==================================================== */
49919 /* ===================================================  HOSTSHADOWKCPREG  ==================================================== */
49920 /* ===================================================  HOSTSHADOWKCEREG  ==================================================== */
49921 /* ==================================================  HOSTSHADOWKPICVREG  =================================================== */
49922 /* ==================================================  HOSTSHADOWKCEICVREG  ================================================== */
49923 /* ====================================================  OTPADDRWIDTHDEF  ==================================================== */
49924 
49925 
49926 /* =========================================================================================================================== */
49927 /* ================                                            DC                                             ================ */
49928 /* =========================================================================================================================== */
49929 
49930 /* =========================================================  MODE  ========================================================== */
49931 /* ===============================================  DC MODE VSYNCPOL [28..28]  =============================================== */
49932 typedef enum {                                  /*!< DC_MODE_VSYNCPOL                                                          */
49933   DC_MODE_VSYNCPOL_VSYNC_NEG           = 1,     /*!< VSYNC_NEG : VSYNC polarity is negative                                    */
49934   DC_MODE_VSYNCPOL_VSYNC_POS           = 0,     /*!< VSYNC_POS : VSYNC polarity is positive                                    */
49935 } DC_MODE_VSYNCPOL_Enum;
49936 
49937 /* ===============================================  DC MODE HSYNCPOL [27..27]  =============================================== */
49938 typedef enum {                                  /*!< DC_MODE_HSYNCPOL                                                          */
49939   DC_MODE_HSYNCPOL_HSYNC_NEG           = 1,     /*!< HSYNC_NEG : HSYNC polarity is negative                                    */
49940   DC_MODE_HSYNCPOL_HSYNC_POS           = 0,     /*!< HSYNC_POS : HSYNC polarity is positive                                    */
49941 } DC_MODE_HSYNCPOL_Enum;
49942 
49943 /* ================================================  DC MODE DEPOL [26..26]  ================================================= */
49944 typedef enum {                                  /*!< DC_MODE_DEPOL                                                             */
49945   DC_MODE_DEPOL_DE_NEG                 = 1,     /*!< DE_NEG : DE polarity is negative                                          */
49946   DC_MODE_DEPOL_DE_POS                 = 0,     /*!< DE_POS : DE polarity is positive                                          */
49947 } DC_MODE_DEPOL_Enum;
49948 
49949 /* ==============================================  DC MODE PIXCLKPOL [22..22]  =============================================== */
49950 typedef enum {                                  /*!< DC_MODE_PIXCLKPOL                                                         */
49951   DC_MODE_PIXCLKPOL_POL_NEG            = 1,     /*!< POL_NEG : Pixel Clock out polarity is negative                            */
49952   DC_MODE_PIXCLKPOL_POL_POS            = 0,     /*!< POL_POS : Pixel Clock out polarity is positive                            */
49953 } DC_MODE_PIXCLKPOL_Enum;
49954 
49955 /* =================================================  DC MODE COLFMT [9..9]  ================================================= */
49956 typedef enum {                                  /*!< DC_MODE_COLFMT                                                            */
49957   DC_MODE_COLFMT_YUV_EN                = 1,     /*!< YUV_EN : YUV/YCbCr format is enabled                                      */
49958   DC_MODE_COLFMT_RGB_EN                = 0,     /*!< RGB_EN : RGB format is enabled                                            */
49959 } DC_MODE_COLFMT_Enum;
49960 
49961 /* ================================================  DC MODE DISPFMT [5..8]  ================================================= */
49962 typedef enum {                                  /*!< DC_MODE_DISPFMT                                                           */
49963   DC_MODE_DISPFMT_DPI                  = 0,     /*!< DPI : DPI Interface                                                       */
49964   DC_MODE_DISPFMT_BYTE3                = 1,     /*!< BYTE3 : Byte-3 beat Interface                                             */
49965   DC_MODE_DISPFMT_BYTE4                = 2,     /*!< BYTE4 : Byte-4 beat (RGBX) Interface                                      */
49966   DC_MODE_DISPFMT_SERIAL               = 3,     /*!< SERIAL : Two phase serial 12-bit                                          */
49967   DC_MODE_DISPFMT_LVDS2                = 4,     /*!< LVDS2 : LVDS 24-bit unbalanced single pixel format 2                      */
49968   DC_MODE_DISPFMT_LVDS1                = 5,     /*!< LVDS1 : LVDS 24-bit unbalanced single pixel format 1                      */
49969   DC_MODE_DISPFMT_YUYV                 = 6,     /*!< YUYV : YUYV (16-bit mode)                                                 */
49970   DC_MODE_DISPFMT_BT656                = 7,     /*!< BT656 : BT.656                                                            */
49971   DC_MODE_DISPFMT_JDI                  = 8,     /*!< JDI : JDI MIP                                                             */
49972 } DC_MODE_DISPFMT_Enum;
49973 
49974 /* ========================================================  CLKCTRL  ======================================================== */
49975 /* =============================================  DC CLKCTRL SECCLKDIV [27..31]  ============================================= */
49976 typedef enum {                                  /*!< DC_CLKCTRL_SECCLKDIV                                                      */
49977   DC_CLKCTRL_SECCLKDIV_SDIV_0          = 0,     /*!< SDIV_0 : No division                                                      */
49978   DC_CLKCTRL_SECCLKDIV_SDIV_1          = 1,     /*!< SDIV_1 : No division                                                      */
49979   DC_CLKCTRL_SECCLKDIV_SDIV_2          = 2,     /*!< SDIV_2 : Divided by 2                                                     */
49980   DC_CLKCTRL_SECCLKDIV_SDIV_3          = 3,     /*!< SDIV_3 : Divided by 3                                                     */
49981   DC_CLKCTRL_SECCLKDIV_SDIV_4          = 4,     /*!< SDIV_4 : Divided by 4                                                     */
49982   DC_CLKCTRL_SECCLKDIV_SDIV_5          = 5,     /*!< SDIV_5 : Divided by 5                                                     */
49983   DC_CLKCTRL_SECCLKDIV_SDIV_6          = 6,     /*!< SDIV_6 : Divided by 6                                                     */
49984   DC_CLKCTRL_SECCLKDIV_SDIV_7          = 7,     /*!< SDIV_7 : Divided by 7                                                     */
49985   DC_CLKCTRL_SECCLKDIV_SDIV_8          = 8,     /*!< SDIV_8 : Divided by 8                                                     */
49986   DC_CLKCTRL_SECCLKDIV_SDIV_9          = 9,     /*!< SDIV_9 : Divided by 9                                                     */
49987   DC_CLKCTRL_SECCLKDIV_SDIV_10         = 10,    /*!< SDIV_10 : Divided by 10                                                   */
49988   DC_CLKCTRL_SECCLKDIV_SDIV_11         = 11,    /*!< SDIV_11 : Divided by 11                                                   */
49989   DC_CLKCTRL_SECCLKDIV_SDIV_12         = 12,    /*!< SDIV_12 : Divided by 12                                                   */
49990   DC_CLKCTRL_SECCLKDIV_SDIV_13         = 13,    /*!< SDIV_13 : Divided by 13                                                   */
49991   DC_CLKCTRL_SECCLKDIV_SDIV_14         = 14,    /*!< SDIV_14 : Divided by 14                                                   */
49992   DC_CLKCTRL_SECCLKDIV_SDIV_15         = 15,    /*!< SDIV_15 : Divided by 15                                                   */
49993 } DC_CLKCTRL_SECCLKDIV_Enum;
49994 
49995 /* =============================================  DC CLKCTRL DIVIDEVALUE [0..5]  ============================================= */
49996 typedef enum {                                  /*!< DC_CLKCTRL_DIVIDEVALUE                                                    */
49997   DC_CLKCTRL_DIVIDEVALUE_FDIV_0        = 0,     /*!< FDIV_0 : Divided by 0                                                     */
49998   DC_CLKCTRL_DIVIDEVALUE_FDIV_2        = 2,     /*!< FDIV_2 : Divided by 2                                                     */
49999   DC_CLKCTRL_DIVIDEVALUE_FDIV_3        = 3,     /*!< FDIV_3 : Divided by 3                                                     */
50000   DC_CLKCTRL_DIVIDEVALUE_FDIV_4        = 4,     /*!< FDIV_4 : Divided by 4                                                     */
50001   DC_CLKCTRL_DIVIDEVALUE_FDIV_5        = 5,     /*!< FDIV_5 : Divided by 5                                                     */
50002   DC_CLKCTRL_DIVIDEVALUE_FDIV_6        = 6,     /*!< FDIV_6 : Divided by 6                                                     */
50003   DC_CLKCTRL_DIVIDEVALUE_FDIV_7        = 7,     /*!< FDIV_7 : Divided by 7                                                     */
50004   DC_CLKCTRL_DIVIDEVALUE_FDIV_8        = 8,     /*!< FDIV_8 : Divided by 8                                                     */
50005   DC_CLKCTRL_DIVIDEVALUE_FDIV_9        = 9,     /*!< FDIV_9 : Divided by 9                                                     */
50006   DC_CLKCTRL_DIVIDEVALUE_FDIV_10       = 10,    /*!< FDIV_10 : Divided by 10                                                   */
50007   DC_CLKCTRL_DIVIDEVALUE_FDIV_11       = 11,    /*!< FDIV_11 : Divided by 11                                                   */
50008   DC_CLKCTRL_DIVIDEVALUE_FDIV_12       = 12,    /*!< FDIV_12 : Divided by 12                                                   */
50009   DC_CLKCTRL_DIVIDEVALUE_FDIV_13       = 13,    /*!< FDIV_13 : Divided by 13                                                   */
50010   DC_CLKCTRL_DIVIDEVALUE_FDIV_14       = 14,    /*!< FDIV_14 : Divided by 14                                                   */
50011   DC_CLKCTRL_DIVIDEVALUE_FDIV_15       = 15,    /*!< FDIV_15 : Divided by 15                                                   */
50012   DC_CLKCTRL_DIVIDEVALUE_FDIV_16       = 16,    /*!< FDIV_16 : Divided by 16                                                   */
50013   DC_CLKCTRL_DIVIDEVALUE_FDIV_17       = 17,    /*!< FDIV_17 : Divided by 17                                                   */
50014   DC_CLKCTRL_DIVIDEVALUE_FDIV_18       = 18,    /*!< FDIV_18 : Divided by 18                                                   */
50015   DC_CLKCTRL_DIVIDEVALUE_FDIV_19       = 19,    /*!< FDIV_19 : Divided by 19                                                   */
50016   DC_CLKCTRL_DIVIDEVALUE_FDIV_20       = 20,    /*!< FDIV_20 : Divided by 20                                                   */
50017   DC_CLKCTRL_DIVIDEVALUE_FDIV_21       = 21,    /*!< FDIV_21 : Divided by 21                                                   */
50018   DC_CLKCTRL_DIVIDEVALUE_FDIV_22       = 22,    /*!< FDIV_22 : Divided by 22                                                   */
50019   DC_CLKCTRL_DIVIDEVALUE_FDIV_23       = 23,    /*!< FDIV_23 : Divided by 23                                                   */
50020   DC_CLKCTRL_DIVIDEVALUE_FDIV_24       = 24,    /*!< FDIV_24 : Divided by 24                                                   */
50021   DC_CLKCTRL_DIVIDEVALUE_FDIV_25       = 25,    /*!< FDIV_25 : Divided by 25                                                   */
50022   DC_CLKCTRL_DIVIDEVALUE_FDIV_26       = 26,    /*!< FDIV_26 : Divided by 26                                                   */
50023   DC_CLKCTRL_DIVIDEVALUE_FDIV_27       = 27,    /*!< FDIV_27 : Divided by 27                                                   */
50024   DC_CLKCTRL_DIVIDEVALUE_FDIV_28       = 28,    /*!< FDIV_28 : Divided by 28                                                   */
50025   DC_CLKCTRL_DIVIDEVALUE_FDIV_29       = 29,    /*!< FDIV_29 : Divided by 29                                                   */
50026   DC_CLKCTRL_DIVIDEVALUE_FDIV_30       = 30,    /*!< FDIV_30 : Divided by 30                                                   */
50027   DC_CLKCTRL_DIVIDEVALUE_FDIV_31       = 31,    /*!< FDIV_31 : Divided by 31                                                   */
50028 } DC_CLKCTRL_DIVIDEVALUE_Enum;
50029 
50030 /* ========================================================  BGCOLOR  ======================================================== */
50031 /* =========================================================  RESXY  ========================================================= */
50032 /* =====================================================  FRONTPORCHXY  ====================================================== */
50033 /* ======================================================  BLANKINGXY  ======================================================= */
50034 /* ======================================================  BACKPORCHXY  ====================================================== */
50035 /* =======================================================  CURSORXY  ======================================================== */
50036 /* ========================================================  DBICFG  ========================================================= */
50037 /* ===============================================  DC DBICFG CSXSET [29..29]  =============================================== */
50038 typedef enum {                                  /*!< DC_DBICFG_CSXSET                                                          */
50039   DC_DBICFG_CSXSET_CSX1                = 1,     /*!< CSX1 : is set to one if DBI_CFG[29] has the value of one                  */
50040   DC_DBICFG_CSXSET_CSX0                = 0,     /*!< CSX0 : is set to zero if DBI_CFG[29] has the value of zero                */
50041 } DC_DBICFG_CSXSET_Enum;
50042 
50043 /* ==============================================  DC DBICFG TYPEBWIDTH [6..7]  ============================================== */
50044 typedef enum {                                  /*!< DC_DBICFG_TYPEBWIDTH                                                      */
50045   DC_DBICFG_TYPEBWIDTH_INT_16          = 0,     /*!< INT_16 : 16-bit interface                                                 */
50046   DC_DBICFG_TYPEBWIDTH_INT_9           = 1,     /*!< INT_9 : 9-bit interface                                                   */
50047   DC_DBICFG_TYPEBWIDTH_INT_8           = 2,     /*!< INT_8 : 8-bit interface                                                   */
50048   DC_DBICFG_TYPEBWIDTH_INT_SERIAL      = 3,     /*!< INT_SERIAL : Serial interface                                             */
50049 } DC_DBICFG_TYPEBWIDTH_Enum;
50050 
50051 /* =============================================  DC DBICFG DATAWDORDER [3..5]  ============================================== */
50052 typedef enum {                                  /*!< DC_DBICFG_DATAWDORDER                                                     */
50053   DC_DBICFG_DATAWDORDER_WD_ORDER_OPT0  = 0,     /*!< WD_ORDER_OPT0 : option 0                                                  */
50054   DC_DBICFG_DATAWDORDER_WD_ORDER_OPT1  = 1,     /*!< WD_ORDER_OPT1 : option 1                                                  */
50055   DC_DBICFG_DATAWDORDER_WD_ORDER_OPT2  = 2,     /*!< WD_ORDER_OPT2 : option 2                                                  */
50056   DC_DBICFG_DATAWDORDER_WD_ORDER_OPT3  = 3,     /*!< WD_ORDER_OPT3 : option 3                                                  */
50057 } DC_DBICFG_DATAWDORDER_Enum;
50058 
50059 /* =============================================  DC DBICFG DBICOLORFMT [0..2]  ============================================== */
50060 typedef enum {                                  /*!< DC_DBICFG_DBICOLORFMT                                                     */
50061   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB111 = 1,     /*!< DBI_FMT_RGB111 : RGB111 (3 bits/pixel)                                    */
50062   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB332 = 2,     /*!< DBI_FMT_RGB332 : RGB332 (8 bits/pixel)                                    */
50063   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB444 = 3,     /*!< DBI_FMT_RGB444 : RGB444 (12 bits/pixel)                                   */
50064   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB565 = 5,     /*!< DBI_FMT_RGB565 : RGB565 (16 bits/pixel)                                   */
50065   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB666 = 6,     /*!< DBI_FMT_RGB666 : RGB666 (18 bits/pixel)                                   */
50066   DC_DBICFG_DBICOLORFMT_DBI_FMT_RGB888 = 7,     /*!< DBI_FMT_RGB888 : RGB888 (24 bits/pixel)                                   */
50067 } DC_DBICFG_DBICOLORFMT_Enum;
50068 
50069 /* ========================================================  DCGPIO  ========================================================= */
50070 /* ======================================================  LAYER0MODE  ======================================================= */
50071 /* ==========================================  DC LAYER0MODE LAYER0DBLEND [12..15]  ========================================== */
50072 typedef enum {                                  /*!< DC_LAYER0MODE_LAYER0DBLEND                                                */
50073   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DBLACK_BLEND = 0,/*!< LAYER0_DBLACK_BLEND : blend black                                    */
50074   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DWHITE_BLEND = 1,/*!< LAYER0_DWHITE_BLEND : blend white                                    */
50075   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALBHAS_BLEND = 2,/*!< LAYER0_DALBHAS_BLEND : blend alpha source                           */
50076   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALPHAG_BLEND = 3,/*!< LAYER0_DALPHAG_BLEND : blend alpha global                           */
50077   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALPHASG_BLEND = 4,/*!< LAYER0_DALPHASG_BLEND : blend alpha source and alpha global        */
50078   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERT_BLEND_SRC = 5,/*!< LAYER0_DINVERT_BLEND_SRC : blend inverted source                */
50079   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERT_GLOBAL_BLEND = 6,/*!< LAYER0_DINVERT_GLOBAL_BLEND : blend inverted global          */
50080   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERTSG_BLEND = 7,/*!< LAYER0_DINVERTSG_BLEND : blend inverted source and inverted
50081                                                      global                                                                    */
50082   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DALPHA_BLEND = 10,/*!< LAYER0_DALPHA_BLEND : blend alpha destination                       */
50083   DC_LAYER0MODE_LAYER0DBLEND_LAYER0_DINVERT_BLEND_DST = 13,/*!< LAYER0_DINVERT_BLEND_DST : blend inverted destination          */
50084 } DC_LAYER0MODE_LAYER0DBLEND_Enum;
50085 
50086 /* ==========================================  DC LAYER0MODE LAYER0SBLEND [8..11]  =========================================== */
50087 typedef enum {                                  /*!< DC_LAYER0MODE_LAYER0SBLEND                                                */
50088   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SBLACK_BLEND = 0,/*!< LAYER0_SBLACK_BLEND : blend black                                    */
50089   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SWHITE_BLEND = 1,/*!< LAYER0_SWHITE_BLEND : blend white                                    */
50090   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALBHAS_BLEND = 2,/*!< LAYER0_SALBHAS_BLEND : blend alpha source                           */
50091   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALPHAG_BLEND = 3,/*!< LAYER0_SALPHAG_BLEND : blend alpha global                           */
50092   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALPHASG_BLEND = 4,/*!< LAYER0_SALPHASG_BLEND : blend alpha source and alpha global        */
50093   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERT_BLEND_SRC = 5,/*!< LAYER0_SINVERT_BLEND_SRC : blend inverted source                */
50094   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERT_GLOBAL_BLEND = 6,/*!< LAYER0_SINVERT_GLOBAL_BLEND : blend inverted global          */
50095   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERTSG_BLEND = 7,/*!< LAYER0_SINVERTSG_BLEND : blend inverted source and inverted
50096                                                      global                                                                    */
50097   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SALPHA_BLEND = 10,/*!< LAYER0_SALPHA_BLEND : blend alpha destination                       */
50098   DC_LAYER0MODE_LAYER0SBLEND_LAYER0_SINVERT_BLEND_DST = 13,/*!< LAYER0_SINVERT_BLEND_DST : blend inverted destination          */
50099 } DC_LAYER0MODE_LAYER0SBLEND_Enum;
50100 
50101 /* ==========================================  DC LAYER0MODE LAYER0COLMODE [0..4]  =========================================== */
50102 typedef enum {                                  /*!< DC_LAYER0MODE_LAYER0COLMODE                                               */
50103   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_LUTBLE = 0,/*!< LAYER0CM_LUTBLE : 8-bit color palette look-up table (LUT8)              */
50104   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGBX5551 = 1,/*!< LAYER0CM_RGBX5551 : 16-bit RGBX5551 color format                      */
50105   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGBX8888 = 2,/*!< LAYER0CM_RGBX8888 : 32-bit RGBX8888 color format                      */
50106   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGB332 = 4,/*!< LAYER0CM_RGB332 : 8-bit RGB332 color format                             */
50107   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RGB565 = 5,/*!< LAYER0CM_RGB565 : 16-bit RGB565 color format                            */
50108   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_XRGB8888 = 6,/*!< LAYER0CM_XRGB8888 : 32-bit XRGB8888 color format                      */
50109   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_L8 = 7,  /*!< LAYER0CM_L8 : L8 Grayscale/Palette format                                 */
50110   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_L1 = 8,  /*!< LAYER0CM_L1 : L1 Grayscale/Palette format                                 */
50111   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_L4 = 9,  /*!< LAYER0CM_L4 : L4 Grayscale/Palette format                                 */
50112   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_YUYV = 10,/*!< LAYER0CM_YUYV : color format                                             */
50113   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_RBG = 11,/*!< LAYER0CM_RBG : 24-bit RGB color format                                    */
50114   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_YUY2 = 12,/*!< LAYER0CM_YUY2 : YUY2 color format                                        */
50115   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_ABGR8888 = 13,/*!< LAYER0CM_ABGR8888 : 32-bit ABGR8888 color format                     */
50116   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_BGRA8888 = 14,/*!< LAYER0CM_BGRA8888 : 32-bit BGRA8888 color format                     */
50117   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_Video = 16,/*!< LAYER0CM_Video : Video 420 Mode                                         */
50118   DC_LAYER0MODE_LAYER0COLMODE_LAYER0CM_Trilinear = 17,/*!< LAYER0CM_Trilinear : Trilinea 420 Video Mode                        */
50119 } DC_LAYER0MODE_LAYER0COLMODE_Enum;
50120 
50121 /* =====================================================  LAYER0STARTXY  ===================================================== */
50122 /* =====================================================  LAYER0SIZEXY  ====================================================== */
50123 /* ======================================================  LAYER0ADDR  ======================================================= */
50124 /* =====================================================  LAYER0STRIDE  ====================================================== */
50125 /* ======================================  DC LAYER0STRIDE LAYER0AXIFIFOTHLD [19..20]  ======================================= */
50126 typedef enum {                                  /*!< DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD                                         */
50127   DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_HALF_SZ = 0,/*!< LAYER0_BURST_HALF_SZ : half fifo (default)                   */
50128   DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_2 = 1,/*!< LAYER0_BURST_2 : 2 burst-size                                      */
50129   DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_4 = 2,/*!< LAYER0_BURST_4 : 4 burst-size                                      */
50130   DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_LAYER0_BURST_8 = 3,/*!< LAYER0_BURST_8 : 8 burst-size                                      */
50131 } DC_LAYER0STRIDE_LAYER0AXIFIFOTHLD_Enum;
50132 
50133 /* ======================================  DC LAYER0STRIDE LAYER0AXIBURSTBITS [16..18]  ====================================== */
50134 typedef enum {                                  /*!< DC_LAYER0STRIDE_LAYER0AXIBURSTBITS                                        */
50135   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_DEF = 0,/*!< LAYER0_BEATS_DEF : 16-beats (default)                           */
50136   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_2 = 1,/*!< LAYER0_BEATS_2 : 2-beats                                          */
50137   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_4 = 2,/*!< LAYER0_BEATS_4 : 4-beats                                          */
50138   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_8 = 3,/*!< LAYER0_BEATS_8 : 8-beats                                          */
50139   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_16 = 4,/*!< LAYER0_BEATS_16 : 16-beats (CHECK mistake?)                      */
50140   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_32 = 5,/*!< LAYER0_BEATS_32 : 32-beats (AXI4 only)                           */
50141   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_64 = 6,/*!< LAYER0_BEATS_64 : 64-beats (AXI4 only)                           */
50142   DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_LAYER0_BEATS_128 = 7,/*!< LAYER0_BEATS_128 : 128-beats (AXI4 only)                        */
50143 } DC_LAYER0STRIDE_LAYER0AXIBURSTBITS_Enum;
50144 
50145 /* ======================================================  LAYER0RESXY  ====================================================== */
50146 /* =====================================================  LAYER0SCALEX  ====================================================== */
50147 /* =====================================================  LAYER0SCALEY  ====================================================== */
50148 /* ======================================================  LAYER1MODE  ======================================================= */
50149 /* ==========================================  DC LAYER1MODE LAYER1DBLEND [12..15]  ========================================== */
50150 typedef enum {                                  /*!< DC_LAYER1MODE_LAYER1DBLEND                                                */
50151   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DBLACK_BLEND = 0,/*!< LAYER1_DBLACK_BLEND : blend black                                    */
50152   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DWHITE_BLEND = 1,/*!< LAYER1_DWHITE_BLEND : blend white                                    */
50153   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALBHAS_BLEND = 2,/*!< LAYER1_DALBHAS_BLEND : blend alpha source                           */
50154   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALPHAG_BLEND = 3,/*!< LAYER1_DALPHAG_BLEND : blend alpha global                           */
50155   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALPHASG_BLEND = 4,/*!< LAYER1_DALPHASG_BLEND : blend alpha source and alpha global        */
50156   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERT_BLEND_SRC = 5,/*!< LAYER1_DINVERT_BLEND_SRC : blend inverted source                */
50157   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERT_GLOBAL_BLEND = 6,/*!< LAYER1_DINVERT_GLOBAL_BLEND : blend inverted global          */
50158   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERTSG_BLEND = 7,/*!< LAYER1_DINVERTSG_BLEND : blend inverted source and inverted
50159                                                      global                                                                    */
50160   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DALPHA_BLEND = 10,/*!< LAYER1_DALPHA_BLEND : blend alpha destination                       */
50161   DC_LAYER1MODE_LAYER1DBLEND_LAYER1_DINVERT_BLEND_DST = 13,/*!< LAYER1_DINVERT_BLEND_DST : blend inverted destination          */
50162 } DC_LAYER1MODE_LAYER1DBLEND_Enum;
50163 
50164 /* ==========================================  DC LAYER1MODE LAYER1SBLEND [8..11]  =========================================== */
50165 typedef enum {                                  /*!< DC_LAYER1MODE_LAYER1SBLEND                                                */
50166   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SBLACK_BLEND = 0,/*!< LAYER1_SBLACK_BLEND : blend black                                    */
50167   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SWHITE_BLEND = 1,/*!< LAYER1_SWHITE_BLEND : blend white                                    */
50168   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALBHAS_BLEND = 2,/*!< LAYER1_SALBHAS_BLEND : blend alpha source                           */
50169   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALPHAG_BLEND = 3,/*!< LAYER1_SALPHAG_BLEND : blend alpha global                           */
50170   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALPHASG_BLEND = 4,/*!< LAYER1_SALPHASG_BLEND : blend alpha source and alpha global        */
50171   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERT_BLEND_SRC = 5,/*!< LAYER1_SINVERT_BLEND_SRC : blend inverted source                */
50172   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERT_GLOBAL_BLEND = 6,/*!< LAYER1_SINVERT_GLOBAL_BLEND : blend inverted global          */
50173   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERTSG_BLEND = 7,/*!< LAYER1_SINVERTSG_BLEND : blend inverted source and inverted
50174                                                      global                                                                    */
50175   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SALPHA_BLEND = 10,/*!< LAYER1_SALPHA_BLEND : blend alpha destination                       */
50176   DC_LAYER1MODE_LAYER1SBLEND_LAYER1_SINVERT_BLEND_DST = 13,/*!< LAYER1_SINVERT_BLEND_DST : blend inverted destination          */
50177 } DC_LAYER1MODE_LAYER1SBLEND_Enum;
50178 
50179 /* =========================================  DC LAYER1MODE LAYER1COLORMODE [0..4]  ========================================== */
50180 typedef enum {                                  /*!< DC_LAYER1MODE_LAYER1COLORMODE                                             */
50181   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_LUTBLE = 0,/*!< LAYER1_LUTBLE : 8-bit color palette look-up table (LUT8)                */
50182   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGBX5551 = 1,/*!< LAYER1_RGBX5551 : 16-bit RGBX5551 color format                        */
50183   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGBX8888 = 2,/*!< LAYER1_RGBX8888 : 32-bit RGBX8888 color format                        */
50184   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGB332 = 4,/*!< LAYER1_RGB332 : 8-bit RGB332 color format                               */
50185   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGB565 = 5,/*!< LAYER1_RGB565 : 16-bit RGB565 color format                              */
50186   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_XRGB8888 = 6,/*!< LAYER1_XRGB8888 : 32-bit XRGB8888 color format                        */
50187   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_L8 = 7,  /*!< LAYER1_L8 : L8 Grayscale/Palette format                                   */
50188   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_L1 = 8,  /*!< LAYER1_L1 : L1 Grayscale/Palette format                                   */
50189   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_L4 = 9,  /*!< LAYER1_L4 : L4 Grayscale/Palette format                                   */
50190   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_YUYV = 10,/*!< LAYER1_YUYV : YUYV color format                                          */
50191   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_RGB = 11,/*!< LAYER1_RGB : 24-bit RGB color format                                      */
50192   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_YUY2 = 12,/*!< LAYER1_YUY2 : YUY2 color format                                          */
50193   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_ABGR8888 = 13,/*!< LAYER1_ABGR8888 : 32-bit ABGR8888 color format                       */
50194   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_BGRA8888 = 14,/*!< LAYER1_BGRA8888 : 32-bit BGRA8888 color format                       */
50195   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_VIDEO420 = 16,/*!< LAYER1_VIDEO420 : Video 420 Mode                                     */
50196   DC_LAYER1MODE_LAYER1COLORMODE_LAYER1_TRILIN420 = 17,/*!< LAYER1_TRILIN420 : Trilinear 420 Video Mode                         */
50197 } DC_LAYER1MODE_LAYER1COLORMODE_Enum;
50198 
50199 /* =====================================================  LAYER1STARTXY  ===================================================== */
50200 /* =====================================================  LAYER1SIZEXY  ====================================================== */
50201 /* ======================================================  LAYER1ADDR  ======================================================= */
50202 /* =====================================================  LAYER1STRIDE  ====================================================== */
50203 /* ======================================  DC LAYER1STRIDE LAYER1AXIFIFOTHLD [19..20]  ======================================= */
50204 typedef enum {                                  /*!< DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD                                         */
50205   DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_HALF_SZ = 0,/*!< LAYER1_BURST_HALF_SZ : half fifo (default)                   */
50206   DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_2 = 1,/*!< LAYER1_BURST_2 : 2 burst-size                                      */
50207   DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_4 = 2,/*!< LAYER1_BURST_4 : 4 burst-size                                      */
50208   DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_LAYER1_BURST_8 = 3,/*!< LAYER1_BURST_8 : 8 burst-size                                      */
50209 } DC_LAYER1STRIDE_LAYER1AXIFIFOTHLD_Enum;
50210 
50211 /* ======================================  DC LAYER1STRIDE LAYER1AXIBURSTBITS [16..18]  ====================================== */
50212 typedef enum {                                  /*!< DC_LAYER1STRIDE_LAYER1AXIBURSTBITS                                        */
50213   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_DEF = 0,/*!< LAYER1_BEATS_DEF : 16-beats (default)                           */
50214   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_2 = 1,/*!< LAYER1_BEATS_2 : 2-beats                                          */
50215   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_4 = 2,/*!< LAYER1_BEATS_4 : 4-beats                                          */
50216   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_8 = 3,/*!< LAYER1_BEATS_8 : 8-beats                                          */
50217   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_16 = 4,/*!< LAYER1_BEATS_16 : 16-beats (CHECK mistake?)                      */
50218   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_32 = 5,/*!< LAYER1_BEATS_32 : 32-beats (AXI4 only)                           */
50219   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_64 = 6,/*!< LAYER1_BEATS_64 : 64-beats (AXI4 only)                           */
50220   DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_LAYER1_BEATS_128 = 7,/*!< LAYER1_BEATS_128 : 128-beats (AXI4 only)                        */
50221 } DC_LAYER1STRIDE_LAYER1AXIBURSTBITS_Enum;
50222 
50223 /* ======================================================  LAYER1RESXY  ====================================================== */
50224 /* =====================================================  LAYER1SCALEX  ====================================================== */
50225 /* =====================================================  LAYER1SCALEY  ====================================================== */
50226 /* ======================================================  LAYER2MODE  ======================================================= */
50227 /* ==========================================  DC LAYER2MODE LAYER2DBLEND [12..15]  ========================================== */
50228 typedef enum {                                  /*!< DC_LAYER2MODE_LAYER2DBLEND                                                */
50229   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DBLACK_BLEND = 0,/*!< LAYER2_DBLACK_BLEND : blend black                                    */
50230   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DWHITE_BLEND = 1,/*!< LAYER2_DWHITE_BLEND : blend white                                    */
50231   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALBHAS_BLEND = 2,/*!< LAYER2_DALBHAS_BLEND : blend alpha source                           */
50232   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALPHAG_BLEND = 3,/*!< LAYER2_DALPHAG_BLEND : blend alpha global                           */
50233   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALPHASG_BLEND = 4,/*!< LAYER2_DALPHASG_BLEND : blend alpha source and alpha global        */
50234   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERT_BLEND_SRC = 5,/*!< LAYER2_DINVERT_BLEND_SRC : blend inverted source                */
50235   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERT_GLOBAL_BLEND = 6,/*!< LAYER2_DINVERT_GLOBAL_BLEND : blend inverted global          */
50236   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERTSG_BLEND = 7,/*!< LAYER2_DINVERTSG_BLEND : blend inverted source and inverted
50237                                                      global                                                                    */
50238   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DALPHA_BLEND = 10,/*!< LAYER2_DALPHA_BLEND : blend alpha destination                       */
50239   DC_LAYER2MODE_LAYER2DBLEND_LAYER2_DINVERT_BLEND_DST = 13,/*!< LAYER2_DINVERT_BLEND_DST : blend inverted destination          */
50240 } DC_LAYER2MODE_LAYER2DBLEND_Enum;
50241 
50242 /* ==========================================  DC LAYER2MODE LAYER2SBLEND [8..11]  =========================================== */
50243 typedef enum {                                  /*!< DC_LAYER2MODE_LAYER2SBLEND                                                */
50244   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SBLACK_BLEND = 0,/*!< LAYER2_SBLACK_BLEND : blend black                                    */
50245   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SWHITE_BLEND = 1,/*!< LAYER2_SWHITE_BLEND : blend white                                    */
50246   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALBHAS_BLEND = 2,/*!< LAYER2_SALBHAS_BLEND : blend alpha source                           */
50247   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALPHAG_BLEND = 3,/*!< LAYER2_SALPHAG_BLEND : blend alpha global                           */
50248   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALPHASG_BLEND = 4,/*!< LAYER2_SALPHASG_BLEND : blend alpha source and alpha global        */
50249   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERT_BLEND_SRC = 5,/*!< LAYER2_SINVERT_BLEND_SRC : blend inverted source                */
50250   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERT_GLOBAL_BLEND = 6,/*!< LAYER2_SINVERT_GLOBAL_BLEND : blend inverted global          */
50251   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERTSG_BLEND = 7,/*!< LAYER2_SINVERTSG_BLEND : blend inverted source and inverted
50252                                                      global                                                                    */
50253   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SALPHA_BLEND = 10,/*!< LAYER2_SALPHA_BLEND : blend alpha destination                       */
50254   DC_LAYER2MODE_LAYER2SBLEND_LAYER2_SINVERT_BLEND_DST = 13,/*!< LAYER2_SINVERT_BLEND_DST : blend inverted destination          */
50255 } DC_LAYER2MODE_LAYER2SBLEND_Enum;
50256 
50257 /* =========================================  DC LAYER2MODE LAYER2COLORMODE [0..4]  ========================================== */
50258 typedef enum {                                  /*!< DC_LAYER2MODE_LAYER2COLORMODE                                             */
50259   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_LUTBLE = 0,/*!< LAYER2_LUTBLE : 8-bit color palette look-up table (LUT8)                */
50260   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGBX5551 = 1,/*!< LAYER2_RGBX5551 : 16-bit RGBX5551 color format                        */
50261   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGBX8888 = 2,/*!< LAYER2_RGBX8888 : 32-bit RGBX8888 color format                        */
50262   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGB332 = 4,/*!< LAYER2_RGB332 : 8-bit RGB332 color format                               */
50263   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGB565 = 5,/*!< LAYER2_RGB565 : 16-bit RGB565 color format                              */
50264   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_XRGB8888 = 6,/*!< LAYER2_XRGB8888 : 32-bit XRGB8888 color format                        */
50265   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_L8 = 7,  /*!< LAYER2_L8 : L8 Grayscale/Palette format                                   */
50266   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_L1 = 8,  /*!< LAYER2_L1 : L1 Grayscale/Palette format                                   */
50267   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_L4 = 9,  /*!< LAYER2_L4 : L4 Grayscale/Palette format                                   */
50268   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_YUYV = 10,/*!< LAYER2_YUYV : YUYV color format                                          */
50269   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_RGB = 11,/*!< LAYER2_RGB : 24-bit RGB color format                                      */
50270   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_YUY2 = 12,/*!< LAYER2_YUY2 : YUY2 color format                                          */
50271   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_ABGR8888 = 13,/*!< LAYER2_ABGR8888 : 32-bit ABGR8888 color format                       */
50272   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_BGRA8888 = 14,/*!< LAYER2_BGRA8888 : 32-bit BGRA8888 color format                       */
50273   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_VIDEO420 = 16,/*!< LAYER2_VIDEO420 : Video 420 Mode                                     */
50274   DC_LAYER2MODE_LAYER2COLORMODE_LAYER2_TRILIN420 = 17,/*!< LAYER2_TRILIN420 : Trilinear 420 Video Mode                         */
50275 } DC_LAYER2MODE_LAYER2COLORMODE_Enum;
50276 
50277 /* =====================================================  LAYER2STARTXY  ===================================================== */
50278 /* =====================================================  LAYER2SIZEXY  ====================================================== */
50279 /* ======================================================  LAYER2ADDR  ======================================================= */
50280 /* =====================================================  LAYER2STRIDE  ====================================================== */
50281 /* ======================================  DC LAYER2STRIDE LAYER2AXIFIFOTHLD [19..20]  ======================================= */
50282 typedef enum {                                  /*!< DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD                                         */
50283   DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_HALF_SZ = 0,/*!< LAYER2_BURST_HALF_SZ : half fifo (default)                   */
50284   DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_2 = 1,/*!< LAYER2_BURST_2 : 2 burst-size                                      */
50285   DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_4 = 2,/*!< LAYER2_BURST_4 : 4 burst-size                                      */
50286   DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_LAYER2_BURST_8 = 3,/*!< LAYER2_BURST_8 : 8 burst-size                                      */
50287 } DC_LAYER2STRIDE_LAYER2AXIFIFOTHLD_Enum;
50288 
50289 /* ======================================  DC LAYER2STRIDE LAYER2AXIBURSTBITS [16..18]  ====================================== */
50290 typedef enum {                                  /*!< DC_LAYER2STRIDE_LAYER2AXIBURSTBITS                                        */
50291   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_DEF = 0,/*!< LAYER2_BEATS_DEF : 16-beats (default)                           */
50292   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_2 = 1,/*!< LAYER2_BEATS_2 : 2-beats                                          */
50293   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_4 = 2,/*!< LAYER2_BEATS_4 : 4-beats                                          */
50294   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_8 = 3,/*!< LAYER2_BEATS_8 : 8-beats                                          */
50295   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_16 = 4,/*!< LAYER2_BEATS_16 : 16-beats (CHECK mistake?)                      */
50296   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_32 = 5,/*!< LAYER2_BEATS_32 : 32-beats (AXI4 only)                           */
50297   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_64 = 6,/*!< LAYER2_BEATS_64 : 64-beats (AXI4 only)                           */
50298   DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_LAYER2_BEATS_128 = 7,/*!< LAYER2_BEATS_128 : 128-beats (AXI4 only)                        */
50299 } DC_LAYER2STRIDE_LAYER2AXIBURSTBITS_Enum;
50300 
50301 /* ======================================================  LAYER2RESXY  ====================================================== */
50302 /* =====================================================  LAYER2SCALEX  ====================================================== */
50303 /* =====================================================  LAYER2SCALEY  ====================================================== */
50304 /* ======================================================  LAYER3MODE  ======================================================= */
50305 /* ==========================================  DC LAYER3MODE LAYER3DBLEND [12..15]  ========================================== */
50306 typedef enum {                                  /*!< DC_LAYER3MODE_LAYER3DBLEND                                                */
50307   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DBLACK_BLEND = 0,/*!< LAYER3_DBLACK_BLEND : blend black                                    */
50308   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DWHITE_BLEND = 1,/*!< LAYER3_DWHITE_BLEND : blend white                                    */
50309   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALBHAS_BLEND = 2,/*!< LAYER3_DALBHAS_BLEND : blend alpha source                           */
50310   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALPHAG_BLEND = 3,/*!< LAYER3_DALPHAG_BLEND : blend alpha global                           */
50311   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALPHASG_BLEND = 4,/*!< LAYER3_DALPHASG_BLEND : blend alpha source and alpha global        */
50312   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERT_BLEND_SRC = 5,/*!< LAYER3_DINVERT_BLEND_SRC : blend inverted source                */
50313   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERT_GLOBAL_BLEND = 6,/*!< LAYER3_DINVERT_GLOBAL_BLEND : blend inverted global          */
50314   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERTSG_BLEND = 7,/*!< LAYER3_DINVERTSG_BLEND : blend inverted source and inverted
50315                                                      global                                                                    */
50316   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DALPHA_BLEND = 10,/*!< LAYER3_DALPHA_BLEND : blend alpha destination                       */
50317   DC_LAYER3MODE_LAYER3DBLEND_LAYER3_DINVERT_BLEND_DST = 13,/*!< LAYER3_DINVERT_BLEND_DST : blend inverted destination          */
50318 } DC_LAYER3MODE_LAYER3DBLEND_Enum;
50319 
50320 /* ==========================================  DC LAYER3MODE LAYER3SBLEND [8..11]  =========================================== */
50321 typedef enum {                                  /*!< DC_LAYER3MODE_LAYER3SBLEND                                                */
50322   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SBLACKBLEND = 0,/*!< LAYER3SBLACKBLEND : layer 3 black blend register. blend black          */
50323   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SWHITEBLEND = 1,/*!< LAYER3SWHITEBLEND : blend white                                        */
50324   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALBHASBLEND = 2,/*!< LAYER3SALBHASBLEND : blend alpha source                               */
50325   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALPHAGBLEND = 3,/*!< LAYER3SALPHAGBLEND : blend alpha global                               */
50326   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALPHASGBLEND = 4,/*!< LAYER3SALPHASGBLEND : blend alpha source and alpha global            */
50327   DC_LAYER3MODE_LAYER3SBLEND_LAYER3_SINVERT_BLEND_SRC = 5,/*!< LAYER3_SINVERT_BLEND_SRC : blend inverted source                */
50328   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SINVERTGLOBALBLEND = 6,/*!< LAYER3SINVERTGLOBALBLEND : blend inverted global                */
50329   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SINVERTSGBLEND = 7,/*!< LAYER3SINVERTSGBLEND : blend inverted source and inverted global    */
50330   DC_LAYER3MODE_LAYER3SBLEND_LAYER3SALPHABLEND = 10,/*!< LAYER3SALPHABLEND : blend alpha destination                           */
50331   DC_LAYER3MODE_LAYER3SBLEND_LAYER3_SINVERT_BLEND_DST = 13,/*!< LAYER3_SINVERT_BLEND_DST : blend inverted destination          */
50332 } DC_LAYER3MODE_LAYER3SBLEND_Enum;
50333 
50334 /* =========================================  DC LAYER3MODE LAYER3COLORMODE [0..4]  ========================================== */
50335 typedef enum {                                  /*!< DC_LAYER3MODE_LAYER3COLORMODE                                             */
50336   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_LUTBLE = 0,/*!< LAYER3_LUTBLE : 8-bit color palette look-up table (LUT8)                */
50337   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGBX5551 = 1,/*!< LAYER3_RGBX5551 : 16-bit RGBX5551 color format                        */
50338   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGBX8888 = 2,/*!< LAYER3_RGBX8888 : 32-bit RGBX8888 color format                        */
50339   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGB332 = 4,/*!< LAYER3_RGB332 : 8-bit RGB332 color format                               */
50340   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGB565 = 5,/*!< LAYER3_RGB565 : 16-bit RGB565 color format                              */
50341   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_XRGB8888 = 6,/*!< LAYER3_XRGB8888 : 32-bit XRGB8888 color format                        */
50342   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_L8 = 7,  /*!< LAYER3_L8 : L8 Grayscale/Palette format                                   */
50343   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_L1 = 8,  /*!< LAYER3_L1 : L1 Grayscale/Palette format                                   */
50344   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_L4 = 9,  /*!< LAYER3_L4 : L4 Grayscale/Palette format                                   */
50345   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_YUYV = 10,/*!< LAYER3_YUYV : YUYV color format                                          */
50346   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_RGB = 11,/*!< LAYER3_RGB : 24-bit RGB color format                                      */
50347   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_YUY2 = 12,/*!< LAYER3_YUY2 : YUY2 color format                                          */
50348   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_ABGR8888 = 13,/*!< LAYER3_ABGR8888 : 32-bit ABGR8888 color format                       */
50349   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_BGRA8888 = 14,/*!< LAYER3_BGRA8888 : 32-bit BGRA8888 color format                       */
50350   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_VIDEO420 = 16,/*!< LAYER3_VIDEO420 : Video 420 Mode                                     */
50351   DC_LAYER3MODE_LAYER3COLORMODE_LAYER3_TRILIN42 = 17,/*!< LAYER3_TRILIN42 : Trilinear 420 Video Mode                           */
50352 } DC_LAYER3MODE_LAYER3COLORMODE_Enum;
50353 
50354 /* =====================================================  LAYER3STARTXY  ===================================================== */
50355 /* =====================================================  LAYER3SIZEXY  ====================================================== */
50356 /* ======================================================  LAYER3ADDR  ======================================================= */
50357 /* =====================================================  LAYER3STRIDE  ====================================================== */
50358 /* ======================================  DC LAYER3STRIDE LAYER3AXIFIFOTHLD [19..20]  ======================================= */
50359 typedef enum {                                  /*!< DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD                                         */
50360   DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_HALF_SZ = 0,/*!< LAYER3_BURST_HALF_SZ : half fifo (default)                   */
50361   DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_2 = 1,/*!< LAYER3_BURST_2 : 2 burst-size                                      */
50362   DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_4 = 2,/*!< LAYER3_BURST_4 : 4 burst-size                                      */
50363   DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_LAYER3_BURST_8 = 3,/*!< LAYER3_BURST_8 : 8 burst-size                                      */
50364 } DC_LAYER3STRIDE_LAYER3AXIFIFOTHLD_Enum;
50365 
50366 /* ======================================  DC LAYER3STRIDE LAYER3AXIBURSTBITS [16..18]  ====================================== */
50367 typedef enum {                                  /*!< DC_LAYER3STRIDE_LAYER3AXIBURSTBITS                                        */
50368   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_DEF = 0,/*!< LAYER3_BEATS_DEF : 16-beats (default)                           */
50369   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_2 = 1,/*!< LAYER3_BEATS_2 : 2-beats                                          */
50370   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_4 = 2,/*!< LAYER3_BEATS_4 : 4-beats                                          */
50371   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_8 = 3,/*!< LAYER3_BEATS_8 : 8-beats                                          */
50372   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_16 = 4,/*!< LAYER3_BEATS_16 : 16-beats (CHECK mistake?)                      */
50373   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_32 = 5,/*!< LAYER3_BEATS_32 : 32-beats (AXI4 only)                           */
50374   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_64 = 6,/*!< LAYER3_BEATS_64 : 64-beats (AXI4 only)                           */
50375   DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_LAYER3_BEATS_128 = 7,/*!< LAYER3_BEATS_128 : 128-beats (AXI4 only)                        */
50376 } DC_LAYER3STRIDE_LAYER3AXIBURSTBITS_Enum;
50377 
50378 /* ======================================================  LAYER3RESXY  ====================================================== */
50379 /* =====================================================  LAYER3SCALEX  ====================================================== */
50380 /* =====================================================  LAYER3SCALEY  ====================================================== */
50381 /* ========================================================  DBICMD  ========================================================= */
50382 /* ========================================================  DBIRDAT  ======================================================== */
50383 /* =========================================================  CONFG  ========================================================= */
50384 /* =========================================================  IDREG  ========================================================= */
50385 /* =======================================================  INTERRUPT  ======================================================= */
50386 /* ===========================================  DC INTERRUPT INTTRIGGER [31..31]  ============================================ */
50387 typedef enum {                                  /*!< DC_INTERRUPT_INTTRIGGER                                                   */
50388   DC_INTERRUPT_INTTRIGGER_LEVEL        = 1,     /*!< LEVEL : Level triggering is enabled                                       */
50389   DC_INTERRUPT_INTTRIGGER_EDGE         = 0,     /*!< EDGE : Edge triggering is enabled                                         */
50390 } DC_INTERRUPT_INTTRIGGER_Enum;
50391 
50392 /* ========================================================  STATUS  ========================================================= */
50393 /* ========================================================  COLMOD  ========================================================= */
50394 /* ==========================================================  CRC  ========================================================== */
50395 /* =========================================================  GLLUT  ========================================================= */
50396 /* ======================================================  CURSORDATA  ======================================================= */
50397 /* =======================================================  CURSORLUT  ======================================================= */
50398 /* =========================================================  L0LUT  ========================================================= */
50399 /* =========================================================  L1LUT  ========================================================= */
50400 /* ========================================================  L2LUT0  ========================================================= */
50401 /* =========================================================  L3LUT  ========================================================= */
50402 
50403 
50404 /* =========================================================================================================================== */
50405 /* ================                                            DSI                                            ================ */
50406 /* =========================================================================================================================== */
50407 
50408 /* ======================================================  DEVICEREADY  ====================================================== */
50409 /* ==============================================  DSI DEVICEREADY ULPS [1..2]  ============================================== */
50410 typedef enum {                                  /*!< DSI_DEVICEREADY_ULPS                                                      */
50411   DSI_DEVICEREADY_ULPS_LOW_POWER       = 2,     /*!< LOW_POWER : This pattern is set by the processor to inform that
50412                                                      entire DSI host is to be put on ultra low power [POWER
50413                                                      SAVING] mode 01 - This pattern is set by the processor
50414                                                      to inform                                                                 */
50415   DSI_DEVICEREADY_ULPS_EXIT            = 1,     /*!< EXIT : This pattern is set by the processor to inform that entire
50416                                                      DSI host is to be pu on ultr low power EXIT mode                          */
50417   DSI_DEVICEREADY_ULPS_This            = 0,     /*!< This : pattern is set by the processor to make the DSI host
50418                                                      come out of the wakeup time and resume the normal operation
50419                                                      if the DSI Host already remains in the ULPS exit state.
50420                                                      S/W needs to ensure that there is a minimum of 1ms time
50421                                                      available before clearing the UPLS exit State. 1(a). In
50422                                                      DPI Only Mode: No DPI traffic should be sent after the
50423                                                      above patterns like 10 or 01 is set in this register. Device_ready
50424                                                      bit in Device Ready register should not be disturbed or
50425                                                      should remain set while the device is subject                             */
50426 } DSI_DEVICEREADY_ULPS_Enum;
50427 
50428 /* =============================================  DSI DEVICEREADY READY [0..0]  ============================================== */
50429 typedef enum {                                  /*!< DSI_DEVICEREADY_READY                                                     */
50430   DSI_DEVICEREADY_READY_PROGRAMMED     = 1,     /*!< PROGRAMMED : Set to 1 after dphy_parameter register, all the
50431                                                      count registers, and timeout and interrupt enable registers
50432                                                      are being programmed.                                                     */
50433   DSI_DEVICEREADY_READY_READY          = 0,     /*!< READY : Set by the processor to inform that device is ready
50434                                                      for transmission. This register should be set to 1 after
50435                                                      dphy_parameter register, all the count registers, and timeout
50436                                                      and interrupt enable registers are being programmed. Note:
50437                                                      Reprogramming the registers by resetting the device_ready
50438                                                      bit results in re-enumeration of the DSI controller from
50439                                                      the power up sequence.                                                    */
50440 } DSI_DEVICEREADY_READY_Enum;
50441 
50442 /* =======================================================  INTRSTAT  ======================================================== */
50443 /* ========================================================  INTREN  ========================================================= */
50444 /* ======================================================  DSIFUNCPRG  ======================================================= */
50445 /* ============================================  DSI DSIFUNCPRG REGNAME [13..15]  ============================================ */
50446 typedef enum {                                  /*!< DSI_DSIFUNCPRG_REGNAME                                                    */
50447   DSI_DSIFUNCPRG_REGNAME_command       = 0,     /*!< command : mode is not supported]                                          */
50448   DSI_DSIFUNCPRG_REGNAME_16BIT         = 1,     /*!< 16BIT : 16 bit data                                                       */
50449   DSI_DSIFUNCPRG_REGNAME_9BIT          = 2,     /*!< 9BIT : 9 bit data                                                         */
50450   DSI_DSIFUNCPRG_REGNAME_8BIT          = 3,     /*!< 8BIT : 8 bit data                                                         */
50451 } DSI_DSIFUNCPRG_REGNAME_Enum;
50452 
50453 /* ==========================================  DSI DSIFUNCPRG SUPCOLVIDMODE [7..9]  ========================================== */
50454 typedef enum {                                  /*!< DSI_DSIFUNCPRG_SUPCOLVIDMODE                                              */
50455   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE0 = 0,   /*!< FMTVMODE0 : Video mode is not supported                                   */
50456   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE1 = 1,   /*!< FMTVMODE1 : RGB565 or 16-bit format                                       */
50457   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE2 = 2,   /*!< FMTVMODE2 : RGB666 or 18-bit format                                       */
50458   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE3 = 3,   /*!< FMTVMODE3 : RGB 666 loosely packed format                                 */
50459   DSI_DSIFUNCPRG_SUPCOLVIDMODE_FMTVMODE4 = 4,   /*!< FMTVMODE4 : RGB888 or 24-bit format                                       */
50460 } DSI_DSIFUNCPRG_SUPCOLVIDMODE_Enum;
50461 
50462 /* ===========================================  DSI DSIFUNCPRG CHNUMCMODE [5..6]  ============================================ */
50463 typedef enum {                                  /*!< DSI_DSIFUNCPRG_CHNUMCMODE                                                 */
50464   DSI_DSIFUNCPRG_CHNUMCMODE_VCCH0      = 0,     /*!< VCCH0 : Virtual command mode channel 0                                    */
50465   DSI_DSIFUNCPRG_CHNUMCMODE_VCCH1      = 1,     /*!< VCCH1 : Virtual command mode channel 1                                    */
50466   DSI_DSIFUNCPRG_CHNUMCMODE_VCCH2      = 2,     /*!< VCCH2 : Virtual command mode channel 2                                    */
50467   DSI_DSIFUNCPRG_CHNUMCMODE_VCCH3      = 3,     /*!< VCCH3 : Virtual command mode channel 3                                    */
50468 } DSI_DSIFUNCPRG_CHNUMCMODE_Enum;
50469 
50470 /* =============================================  DSI DSIFUNCPRG CHNUMVM [3..4]  ============================================= */
50471 typedef enum {                                  /*!< DSI_DSIFUNCPRG_CHNUMVM                                                    */
50472   DSI_DSIFUNCPRG_CHNUMVM_VVCH0         = 0,     /*!< VVCH0 : Virtual video mode channel 0                                      */
50473   DSI_DSIFUNCPRG_CHNUMVM_VVCH1         = 1,     /*!< VVCH1 : Virtual video mode channel 1                                      */
50474   DSI_DSIFUNCPRG_CHNUMVM_VVCH2         = 2,     /*!< VVCH2 : Virtual video mode channel 2                                      */
50475   DSI_DSIFUNCPRG_CHNUMVM_VVCH3         = 3,     /*!< VVCH3 : Virtual video mode channel 3                                      */
50476 } DSI_DSIFUNCPRG_CHNUMVM_Enum;
50477 
50478 /* ============================================  DSI DSIFUNCPRG DATALANES [0..2]  ============================================ */
50479 typedef enum {                                  /*!< DSI_DSIFUNCPRG_DATALANES                                                  */
50480   DSI_DSIFUNCPRG_DATALANES_DATAL0      = 0,     /*!< DATAL0 : Zero data lane                                                   */
50481   DSI_DSIFUNCPRG_DATALANES_DATAL1      = 1,     /*!< DATAL1 : One data lane                                                    */
50482   DSI_DSIFUNCPRG_DATALANES_DATAL2      = 2,     /*!< DATAL2 : Two data lane                                                    */
50483   DSI_DSIFUNCPRG_DATALANES_DATAL3      = 3,     /*!< DATAL3 : Three data lane                                                  */
50484   DSI_DSIFUNCPRG_DATALANES_DATAL4      = 4,     /*!< DATAL4 : Four data lane                                                   */
50485 } DSI_DSIFUNCPRG_DATALANES_Enum;
50486 
50487 /* ======================================================  HSTXTIMEOUT  ====================================================== */
50488 /* ========================================================  LPRXTO  ========================================================= */
50489 /* ======================================================  TURNARNDTO  ======================================================= */
50490 /* ===================================================  DEVICERESETTIMER  ==================================================== */
50491 /* =====================================================  DPIRESOLUTION  ===================================================== */
50492 /* =======================================================  HSYNCCNT  ======================================================== */
50493 /* ====================================================  HORIZBKPORCHCNT  ==================================================== */
50494 /* ====================================================  HORIZFPORCHCNT  ===================================================== */
50495 /* ===================================================  HORZACTIVEAREACNT  =================================================== */
50496 /* =======================================================  VSYNCCNT  ======================================================== */
50497 /* ====================================================  VERTBKPORCHCNT  ===================================================== */
50498 /* =====================================================  VERTFPORCHCNT  ===================================================== */
50499 /* ===================================================  DATALANEHILOSWCNT  =================================================== */
50500 /* ==========================================================  DPI  ========================================================== */
50501 /* ======================================================  PLLLOCKCNT  ======================================================= */
50502 /* ========================================================  INITCNT  ======================================================== */
50503 /* =====================================================  MAXRETPACSZE  ====================================================== */
50504 /* =====================================================  VIDEOMODEFMT  ====================================================== */
50505 /* ===========================================  DSI VIDEOMODEFMT VIDEMDFMT [0..1]  =========================================== */
50506 typedef enum {                                  /*!< DSI_VIDEOMODEFMT_VIDEMDFMT                                                */
50507   DSI_VIDEOMODEFMT_VIDEMDFMT_VIDEMDFMT_0 = 0,   /*!< VIDEMDFMT_0 : VIDEMDFMT enum description needed here.                     */
50508   DSI_VIDEOMODEFMT_VIDEMDFMT_NONBURSTPULSE = 1, /*!< NONBURSTPULSE : Non Burst Mode with Sync Pulse                            */
50509   DSI_VIDEOMODEFMT_VIDEMDFMT_NONBURSTEVENTS = 2,/*!< NONBURSTEVENTS : Non Burst Mode with Sync events                          */
50510   DSI_VIDEOMODEFMT_VIDEMDFMT_BURST     = 3,     /*!< BURST : MODE Burst Mode                                                   */
50511 } DSI_VIDEOMODEFMT_VIDEMDFMT_Enum;
50512 
50513 /* ========================================================  CLKEOT  ========================================================= */
50514 /* =======================================================  POLARITY  ======================================================== */
50515 /* ===============================================  DSI POLARITY PBITS [0..3]  =============================================== */
50516 typedef enum {                                  /*!< DSI_POLARITY_PBITS                                                        */
50517   DSI_POLARITY_PBITS_POLV              = 0,     /*!< POLV : polarity for Vsync                                                 */
50518   DSI_POLARITY_PBITS_POLH              = 1,     /*!< POLH : Polarity for Hsync                                                 */
50519   DSI_POLARITY_PBITS_POLSD             = 2,     /*!< POLSD : Polarity for shut down                                            */
50520   DSI_POLARITY_PBITS_POLCM             = 3,     /*!< POLCM : Polarity for Color mode                                           */
50521 } DSI_POLARITY_PBITS_Enum;
50522 
50523 /* ======================================================  CLKLANESWT  ======================================================= */
50524 /* =======================================================  LPBYTECLK  ======================================================= */
50525 /* =======================================================  DPHYPARAM  ======================================================= */
50526 /* ====================================================  CLKLANETIMPARM  ===================================================== */
50527 /* =======================================================  RSTENBDFE  ======================================================= */
50528 /* =======================================================  AFETRIM0  ======================================================== */
50529 /* =======================================================  AFETRIM1  ======================================================== */
50530 /* =======================================================  AFETRIM2  ======================================================== */
50531 /* =======================================================  AFETRIM3  ======================================================== */
50532 /* =====================================================  ERRORAUTORCOV  ===================================================== */
50533 /* ====================================================  MIPIDIRDPIDIFF  ===================================================== */
50534 /* ==========================================  DSI MIPIDIRDPIDIFF DPIHIGH [15..15]  ========================================== */
50535 typedef enum {                                  /*!< DSI_MIPIDIRDPIDIFF_DPIHIGH                                                */
50536   DSI_MIPIDIRDPIDIFF_DPIHIGH_LESSTHAN  = 0,     /*!< LESSTHAN : one line time in DPI is less than to DSI line time             */
50537   DSI_MIPIDIRDPIDIFF_DPIHIGH_GREATER   = 1,     /*!< GREATER : one line time in DPI is greater than or equal to DSI
50538                                                      line time                                                                 */
50539 } DSI_MIPIDIRDPIDIFF_DPIHIGH_Enum;
50540 
50541 /* ===========================================  DSI MIPIDIRDPIDIFF MIPIDIR [0..0]  =========================================== */
50542 typedef enum {                                  /*!< DSI_MIPIDIRDPIDIFF_MIPIDIR                                                */
50543   DSI_MIPIDIRDPIDIFF_MIPIDIR_CONTROL   = 0,     /*!< CONTROL : DSI Host has the control over MIPI bus                          */
50544   DSI_MIPIDIRDPIDIFF_MIPIDIR_RECEIVE   = 1,     /*!< RECEIVE : DSI Host is in Receive mode                                     */
50545 } DSI_MIPIDIRDPIDIFF_MIPIDIR_Enum;
50546 
50547 /* ====================================================  DATALANEPOLSWAP  ==================================================== */
50548 /* =======================================  DSI DATALANEPOLSWAP DATALNPOLSWAP [0..3]  ======================================== */
50549 typedef enum {                                  /*!< DSI_DATALANEPOLSWAP_DATALNPOLSWAP                                         */
50550   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE0 = 1,  /*!< LANE0 : lane 0 polarity swap                                              */
50551   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE1 = 2,  /*!< LANE1 : lane 1 polarity swap                                              */
50552   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE2 = 4,  /*!< LANE2 : lane 2 polarity swap                                              */
50553   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_LANE3 = 8,  /*!< LANE3 : lane 3 polarity swap                                              */
50554   DSI_DATALANEPOLSWAP_DATALNPOLSWAP_ALLLANES = 15,/*!< ALLLANES : data lanes polarity swap                                     */
50555 } DSI_DATALANEPOLSWAP_DATALNPOLSWAP_Enum;
50556 
50557 
50558 
50559 /* =========================================================================================================================== */
50560 /* ================                                            DSP                                            ================ */
50561 /* =========================================================================================================================== */
50562 
50563 /* ========================================================  MUTEX0  ========================================================= */
50564 /* ===============================================  DSP MUTEX0 MUTEX0 [0..2]  ================================================ */
50565 typedef enum {                                  /*!< DSP_MUTEX0_MUTEX0                                                         */
50566   DSP_MUTEX0_MUTEX0_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
50567   DSP_MUTEX0_MUTEX0_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
50568   DSP_MUTEX0_MUTEX0_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
50569   DSP_MUTEX0_MUTEX0_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
50570   DSP_MUTEX0_MUTEX0_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
50571   DSP_MUTEX0_MUTEX0_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
50572 } DSP_MUTEX0_MUTEX0_Enum;
50573 
50574 /* ========================================================  MUTEX1  ========================================================= */
50575 /* ===============================================  DSP MUTEX1 MUTEX1 [0..2]  ================================================ */
50576 typedef enum {                                  /*!< DSP_MUTEX1_MUTEX1                                                         */
50577   DSP_MUTEX1_MUTEX1_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
50578   DSP_MUTEX1_MUTEX1_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
50579   DSP_MUTEX1_MUTEX1_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
50580   DSP_MUTEX1_MUTEX1_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
50581   DSP_MUTEX1_MUTEX1_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
50582   DSP_MUTEX1_MUTEX1_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
50583 } DSP_MUTEX1_MUTEX1_Enum;
50584 
50585 /* ========================================================  MUTEX2  ========================================================= */
50586 /* ===============================================  DSP MUTEX2 MUTEX2 [0..2]  ================================================ */
50587 typedef enum {                                  /*!< DSP_MUTEX2_MUTEX2                                                         */
50588   DSP_MUTEX2_MUTEX2_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
50589   DSP_MUTEX2_MUTEX2_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
50590   DSP_MUTEX2_MUTEX2_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
50591   DSP_MUTEX2_MUTEX2_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
50592   DSP_MUTEX2_MUTEX2_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
50593   DSP_MUTEX2_MUTEX2_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
50594 } DSP_MUTEX2_MUTEX2_Enum;
50595 
50596 /* ========================================================  MUTEX3  ========================================================= */
50597 /* ===============================================  DSP MUTEX3 MUTEX3 [0..2]  ================================================ */
50598 typedef enum {                                  /*!< DSP_MUTEX3_MUTEX3                                                         */
50599   DSP_MUTEX3_MUTEX3_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
50600   DSP_MUTEX3_MUTEX3_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
50601   DSP_MUTEX3_MUTEX3_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
50602   DSP_MUTEX3_MUTEX3_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
50603   DSP_MUTEX3_MUTEX3_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
50604   DSP_MUTEX3_MUTEX3_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
50605 } DSP_MUTEX3_MUTEX3_Enum;
50606 
50607 /* ========================================================  MUTEX4  ========================================================= */
50608 /* ===============================================  DSP MUTEX4 MUTEX4 [0..2]  ================================================ */
50609 typedef enum {                                  /*!< DSP_MUTEX4_MUTEX4                                                         */
50610   DSP_MUTEX4_MUTEX4_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
50611   DSP_MUTEX4_MUTEX4_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
50612   DSP_MUTEX4_MUTEX4_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
50613   DSP_MUTEX4_MUTEX4_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
50614   DSP_MUTEX4_MUTEX4_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
50615   DSP_MUTEX4_MUTEX4_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
50616 } DSP_MUTEX4_MUTEX4_Enum;
50617 
50618 /* ========================================================  MUTEX5  ========================================================= */
50619 /* ===============================================  DSP MUTEX5 MUTEX5 [0..2]  ================================================ */
50620 typedef enum {                                  /*!< DSP_MUTEX5_MUTEX5                                                         */
50621   DSP_MUTEX5_MUTEX5_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
50622   DSP_MUTEX5_MUTEX5_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
50623   DSP_MUTEX5_MUTEX5_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
50624   DSP_MUTEX5_MUTEX5_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
50625   DSP_MUTEX5_MUTEX5_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
50626   DSP_MUTEX5_MUTEX5_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
50627 } DSP_MUTEX5_MUTEX5_Enum;
50628 
50629 /* ========================================================  MUTEX6  ========================================================= */
50630 /* ===============================================  DSP MUTEX6 MUTEX6 [0..2]  ================================================ */
50631 typedef enum {                                  /*!< DSP_MUTEX6_MUTEX6                                                         */
50632   DSP_MUTEX6_MUTEX6_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
50633   DSP_MUTEX6_MUTEX6_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
50634   DSP_MUTEX6_MUTEX6_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
50635   DSP_MUTEX6_MUTEX6_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
50636   DSP_MUTEX6_MUTEX6_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
50637   DSP_MUTEX6_MUTEX6_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
50638 } DSP_MUTEX6_MUTEX6_Enum;
50639 
50640 /* ========================================================  MUTEX7  ========================================================= */
50641 /* ===============================================  DSP MUTEX7 MUTEX7 [0..2]  ================================================ */
50642 typedef enum {                                  /*!< DSP_MUTEX7_MUTEX7                                                         */
50643   DSP_MUTEX7_MUTEX7_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
50644   DSP_MUTEX7_MUTEX7_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
50645   DSP_MUTEX7_MUTEX7_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
50646   DSP_MUTEX7_MUTEX7_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
50647   DSP_MUTEX7_MUTEX7_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
50648   DSP_MUTEX7_MUTEX7_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
50649 } DSP_MUTEX7_MUTEX7_Enum;
50650 
50651 /* ======================================================  CPUMBINTSET  ====================================================== */
50652 /* ======================================================  CPUMBINTCLR  ====================================================== */
50653 /* =====================================================  CPUMBINTSTAT  ====================================================== */
50654 /* =====================================================  CPUCPUMBDATA  ====================================================== */
50655 /* =====================================================  DSP0CPUMBDATA  ===================================================== */
50656 /* =====================================================  DSP1CPUMBDATA  ===================================================== */
50657 /* =====================================================  DSP0MBINTSET  ====================================================== */
50658 /* =====================================================  DSP0MBINTCLR  ====================================================== */
50659 /* =====================================================  DSP0MBINTSTAT  ===================================================== */
50660 /* =====================================================  CPUDSP0MBDATA  ===================================================== */
50661 /* ====================================================  DSP0DSP0MBDATA  ===================================================== */
50662 /* ====================================================  DSP1DSP0MBDATA  ===================================================== */
50663 /* =====================================================  DSP1MBINTSET  ====================================================== */
50664 /* =====================================================  DSP1MBINTCLR  ====================================================== */
50665 /* =====================================================  DSP1MBINTSTAT  ===================================================== */
50666 /* =====================================================  CPUDSP1MBDATA  ===================================================== */
50667 /* ====================================================  DSP0DSP1MBDATA  ===================================================== */
50668 /* ====================================================  DSP1DSP1MBDATA  ===================================================== */
50669 /* ======================================================  DSP0CONTROL  ====================================================== */
50670 /* ==========================================  DSP DSP0CONTROL DSP0IDMATRIG [4..5]  ========================================== */
50671 typedef enum {                                  /*!< DSP_DSP0CONTROL_DSP0IDMATRIG                                              */
50672   DSP_DSP0CONTROL_DSP0IDMATRIG_XTRIG   = 3,     /*!< XTRIG : Trigger is disabled until a cross trigger pulse is asserted.
50673                                                      This will allow another source (determined by the XTRIGSRC
50674                                                      register) to allow the DMA descriptor chain to proceed.                   */
50675   DSP_DSP0CONTROL_DSP0IDMATRIG_SSTEP   = 2,     /*!< SSTEP : Trigger is disabled until a trigger pulse (PULSE in
50676                                                      IDMATRIG register) is asserted. This will allow a single
50677                                                      step in the DMA descriptor chain to be enabled until next
50678                                                      completion.                                                               */
50679   DSP_DSP0CONTROL_DSP0IDMATRIG_AON     = 1,     /*!< AON : Trigger is always enabled. With this set, any trigger
50680                                                      out will immediately generate a trigger in                                */
50681   DSP_DSP0CONTROL_DSP0IDMATRIG_DISABLE = 0,     /*!< DISABLE : Trigger is disabled. This will pause the iDMA indefinitely
50682                                                      until enabled.                                                            */
50683 } DSP_DSP0CONTROL_DSP0IDMATRIG_Enum;
50684 
50685 /* =====================================================  DSP0RESETVEC  ====================================================== */
50686 /* ======================================================  DSP0IRQMASK  ====================================================== */
50687 /* =====================================================  DSP0WAKEMASK  ====================================================== */
50688 /* ==================================================  DSP0RAWIRQSTAT31to0  ================================================== */
50689 /* =================================================  DSP0RAWIRQSTAT63to32  ================================================== */
50690 /* =================================================  DSP0RAWIRQSTAT95to64  ================================================== */
50691 /* =====================================================  DSP0L2LVLINT  ====================================================== */
50692 /* =====================================================  DSP0L3LVLINT  ====================================================== */
50693 /* =====================================================  DSP0L4LVLINT  ====================================================== */
50694 /* =====================================================  DSP0L5LVLINT  ====================================================== */
50695 /* ====================================================  DSP0IDMATRIGCTL  ==================================================== */
50696 /* ==================================================  DSP0INTORMASK31TO0A  ================================================== */
50697 /* =================================================  DSP0INTORMASK63TO32A  ================================================== */
50698 /* =================================================  DSP0INTORMASK95TO64A  ================================================== */
50699 /* ==================================================  DSP0INTORMASK31to0B  ================================================== */
50700 /* =================================================  DSP0INTORMASK63TO32B  ================================================== */
50701 /* =================================================  DSP0INTORMASK95TO64B  ================================================== */
50702 /* ===================================================  DSP0INTENIRQ31TO0  =================================================== */
50703 /* ==================================================  DSP0INTENIRQ63TO32  =================================================== */
50704 /* ==================================================  DSP0INTENIRQ95TO64  =================================================== */
50705 /* ======================================================  DSP1CONTROL  ====================================================== */
50706 /* ==========================================  DSP DSP1CONTROL DSP1IDMATRIG [4..5]  ========================================== */
50707 typedef enum {                                  /*!< DSP_DSP1CONTROL_DSP1IDMATRIG                                              */
50708   DSP_DSP1CONTROL_DSP1IDMATRIG_XTRIG   = 3,     /*!< XTRIG : Trigger is disabled until a cross trigger pulse is asserted.
50709                                                      This will allow another source (determined by the XTRIGSRC
50710                                                      register) to allow the DMA descriptor chain to proceed.                   */
50711   DSP_DSP1CONTROL_DSP1IDMATRIG_SSTEP   = 2,     /*!< SSTEP : Trigger is disabled until a trigger pulse (PULSE in
50712                                                      IDMATRIG register) is asserted. This will allow a single
50713                                                      step in the DMA descriptor chain to be enabled until next
50714                                                      completion.                                                               */
50715   DSP_DSP1CONTROL_DSP1IDMATRIG_AON     = 1,     /*!< AON : Trigger is always enabled. With this set, any trigger
50716                                                      out will immediately generate a trigger in                                */
50717   DSP_DSP1CONTROL_DSP1IDMATRIG_DISABLE = 0,     /*!< DISABLE : Trigger is disabled. This will pause the iDMA indefinitely
50718                                                      until enabled.                                                            */
50719 } DSP_DSP1CONTROL_DSP1IDMATRIG_Enum;
50720 
50721 /* =====================================================  DSP1RESETVEC  ====================================================== */
50722 /* ======================================================  DSP1IRQMASK  ====================================================== */
50723 /* =====================================================  DSP1WAKEMASK  ====================================================== */
50724 /* ==================================================  DSP1RAWIRQSTAT31to0  ================================================== */
50725 /* =================================================  DSP1RAWIRQSTAT63to32  ================================================== */
50726 /* =================================================  DSP1RAWIRQSTAT95to64  ================================================== */
50727 /* =====================================================  DSP1L2LVLINT  ====================================================== */
50728 /* =====================================================  DSP1L3LVLINT  ====================================================== */
50729 /* =====================================================  DSP1L4LVLINT  ====================================================== */
50730 /* =====================================================  DSP1L5LVLINT  ====================================================== */
50731 /* ====================================================  DSP1IDMATRIGCTL  ==================================================== */
50732 /* ==================================================  DSP1INTORMASK31TO0A  ================================================== */
50733 /* =================================================  DSP1INTORMASK63TO32A  ================================================== */
50734 /* =================================================  DSP1INTORMASK95TO64A  ================================================== */
50735 /* ==================================================  DSP1INTORMASK31to0B  ================================================== */
50736 /* =================================================  DSP1INTORMASK63TO32B  ================================================== */
50737 /* =================================================  DSP1INTORMASK95TO64B  ================================================== */
50738 /* ===================================================  DSP1INTENIRQ31TO0  =================================================== */
50739 /* ==================================================  DSP1INTENIRQ63TO32  =================================================== */
50740 /* ==================================================  DSP1INTENIRQ95TO64  =================================================== */
50741 
50742 
50743 /* =========================================================================================================================== */
50744 /* ================                                           FPIO                                            ================ */
50745 /* =========================================================================================================================== */
50746 
50747 /* ==========================================================  RD0  ========================================================== */
50748 /* ==========================================================  RD1  ========================================================== */
50749 /* ==========================================================  RD2  ========================================================== */
50750 /* ==========================================================  RD3  ========================================================== */
50751 /* ==========================================================  WT0  ========================================================== */
50752 /* ==========================================================  WT1  ========================================================== */
50753 /* ==========================================================  WT2  ========================================================== */
50754 /* ==========================================================  WT3  ========================================================== */
50755 /* =========================================================  WTS0  ========================================================== */
50756 /* =========================================================  WTS1  ========================================================== */
50757 /* =========================================================  WTS2  ========================================================== */
50758 /* =========================================================  WTS3  ========================================================== */
50759 /* =========================================================  WTC0  ========================================================== */
50760 /* =========================================================  WTC1  ========================================================== */
50761 /* =========================================================  WTC2  ========================================================== */
50762 /* =========================================================  WTC3  ========================================================== */
50763 /* ==========================================================  EN0  ========================================================== */
50764 /* ==========================================================  EN1  ========================================================== */
50765 /* ==========================================================  EN2  ========================================================== */
50766 /* ==========================================================  EN3  ========================================================== */
50767 /* =========================================================  ENS0  ========================================================== */
50768 /* =========================================================  ENS1  ========================================================== */
50769 /* =========================================================  ENS2  ========================================================== */
50770 /* =========================================================  ENS3  ========================================================== */
50771 /* =========================================================  ENC0  ========================================================== */
50772 /* =========================================================  ENC1  ========================================================== */
50773 /* =========================================================  ENC2  ========================================================== */
50774 /* =========================================================  ENC3  ========================================================== */
50775 
50776 
50777 /* =========================================================================================================================== */
50778 /* ================                                           GPIO                                            ================ */
50779 /* =========================================================================================================================== */
50780 
50781 /* ========================================================  PINCFG0  ======================================================== */
50782 /* =============================================  GPIO PINCFG0 NCEPOL0 [22..22]  ============================================= */
50783 typedef enum {                                  /*!< GPIO_PINCFG0_NCEPOL0                                                      */
50784   GPIO_PINCFG0_NCEPOL0_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
50785   GPIO_PINCFG0_NCEPOL0_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
50786 } GPIO_PINCFG0_NCEPOL0_Enum;
50787 
50788 /* =============================================  GPIO PINCFG0 NCESRC0 [16..21]  ============================================= */
50789 typedef enum {                                  /*!< GPIO_PINCFG0_NCESRC0                                                      */
50790   GPIO_PINCFG0_NCESRC0_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50791   GPIO_PINCFG0_NCESRC0_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50792   GPIO_PINCFG0_NCESRC0_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50793   GPIO_PINCFG0_NCESRC0_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50794   GPIO_PINCFG0_NCESRC0_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50795   GPIO_PINCFG0_NCESRC0_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50796   GPIO_PINCFG0_NCESRC0_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50797   GPIO_PINCFG0_NCESRC0_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50798   GPIO_PINCFG0_NCESRC0_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50799   GPIO_PINCFG0_NCESRC0_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50800   GPIO_PINCFG0_NCESRC0_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50801   GPIO_PINCFG0_NCESRC0_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50802   GPIO_PINCFG0_NCESRC0_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50803   GPIO_PINCFG0_NCESRC0_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50804   GPIO_PINCFG0_NCESRC0_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50805   GPIO_PINCFG0_NCESRC0_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50806   GPIO_PINCFG0_NCESRC0_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50807   GPIO_PINCFG0_NCESRC0_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50808   GPIO_PINCFG0_NCESRC0_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50809   GPIO_PINCFG0_NCESRC0_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50810   GPIO_PINCFG0_NCESRC0_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50811   GPIO_PINCFG0_NCESRC0_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50812   GPIO_PINCFG0_NCESRC0_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50813   GPIO_PINCFG0_NCESRC0_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50814   GPIO_PINCFG0_NCESRC0_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50815   GPIO_PINCFG0_NCESRC0_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50816   GPIO_PINCFG0_NCESRC0_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50817   GPIO_PINCFG0_NCESRC0_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50818   GPIO_PINCFG0_NCESRC0_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50819   GPIO_PINCFG0_NCESRC0_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50820   GPIO_PINCFG0_NCESRC0_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50821   GPIO_PINCFG0_NCESRC0_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50822   GPIO_PINCFG0_NCESRC0_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50823   GPIO_PINCFG0_NCESRC0_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50824   GPIO_PINCFG0_NCESRC0_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50825   GPIO_PINCFG0_NCESRC0_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50826   GPIO_PINCFG0_NCESRC0_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50827   GPIO_PINCFG0_NCESRC0_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50828   GPIO_PINCFG0_NCESRC0_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50829   GPIO_PINCFG0_NCESRC0_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50830   GPIO_PINCFG0_NCESRC0_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50831   GPIO_PINCFG0_NCESRC0_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50832   GPIO_PINCFG0_NCESRC0_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
50833 } GPIO_PINCFG0_NCESRC0_Enum;
50834 
50835 /* ============================================  GPIO PINCFG0 PULLCFG0 [13..15]  ============================================= */
50836 typedef enum {                                  /*!< GPIO_PINCFG0_PULLCFG0                                                     */
50837   GPIO_PINCFG0_PULLCFG0_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50838   GPIO_PINCFG0_PULLCFG0_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50839   GPIO_PINCFG0_PULLCFG0_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50840   GPIO_PINCFG0_PULLCFG0_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50841   GPIO_PINCFG0_PULLCFG0_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
50842   GPIO_PINCFG0_PULLCFG0_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
50843   GPIO_PINCFG0_PULLCFG0_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
50844   GPIO_PINCFG0_PULLCFG0_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
50845 } GPIO_PINCFG0_PULLCFG0_Enum;
50846 
50847 /* ===============================================  GPIO PINCFG0 DS0 [10..11]  =============================================== */
50848 typedef enum {                                  /*!< GPIO_PINCFG0_DS0                                                          */
50849   GPIO_PINCFG0_DS0_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50850   GPIO_PINCFG0_DS0_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50851 } GPIO_PINCFG0_DS0_Enum;
50852 
50853 /* ==============================================  GPIO PINCFG0 OUTCFG0 [8..9]  ============================================== */
50854 typedef enum {                                  /*!< GPIO_PINCFG0_OUTCFG0                                                      */
50855   GPIO_PINCFG0_OUTCFG0_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50856   GPIO_PINCFG0_OUTCFG0_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50857                                                      and 1 values on pin.                                                      */
50858   GPIO_PINCFG0_OUTCFG0_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50859                                                      low, tristate otherwise.                                                  */
50860   GPIO_PINCFG0_OUTCFG0_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50861                                                      drive 0, 1 of HiZ on pin.                                                 */
50862 } GPIO_PINCFG0_OUTCFG0_Enum;
50863 
50864 /* ==============================================  GPIO PINCFG0 IRPTEN0 [6..7]  ============================================== */
50865 typedef enum {                                  /*!< GPIO_PINCFG0_IRPTEN0                                                      */
50866   GPIO_PINCFG0_IRPTEN0_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50867   GPIO_PINCFG0_IRPTEN0_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50868                                                      on this GPIO                                                              */
50869   GPIO_PINCFG0_IRPTEN0_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50870                                                      on this GPIO                                                              */
50871   GPIO_PINCFG0_IRPTEN0_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50872                                                      GPIO                                                                      */
50873 } GPIO_PINCFG0_IRPTEN0_Enum;
50874 
50875 /* ==============================================  GPIO PINCFG0 FNCSEL0 [0..3]  ============================================== */
50876 typedef enum {                                  /*!< GPIO_PINCFG0_FNCSEL0                                                      */
50877   GPIO_PINCFG0_FNCSEL0_SWTRACECLK      = 0,     /*!< SWTRACECLK : Serial Wire Debug Trace Clock                                */
50878   GPIO_PINCFG0_FNCSEL0_SLSCL           = 1,     /*!< SLSCL : I2C Slave clock                                                   */
50879   GPIO_PINCFG0_FNCSEL0_SLSCK           = 2,     /*!< SLSCK : SPI Slave clock                                                   */
50880   GPIO_PINCFG0_FNCSEL0_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50881   GPIO_PINCFG0_FNCSEL0_UART0TX         = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
50882   GPIO_PINCFG0_FNCSEL0_UART1TX         = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
50883   GPIO_PINCFG0_FNCSEL0_CT0             = 6,     /*!< CT0 : Timer/Counter input or output; Selection of direction
50884                                                      is done via CTIMER register settings.                                     */
50885   GPIO_PINCFG0_FNCSEL0_NCE0            = 7,     /*!< NCE0 : IOMSTR/MSPI N Chip Select. Polarity is determined by
50886                                                      CE_POLARITY field                                                         */
50887   GPIO_PINCFG0_FNCSEL0_OBSBUS0         = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
50888   GPIO_PINCFG0_FNCSEL0_VCMPO           = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
50889   GPIO_PINCFG0_FNCSEL0_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
50890   GPIO_PINCFG0_FNCSEL0_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
50891   GPIO_PINCFG0_FNCSEL0_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
50892   GPIO_PINCFG0_FNCSEL0_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
50893   GPIO_PINCFG0_FNCSEL0_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
50894   GPIO_PINCFG0_FNCSEL0_RESERVED15      = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
50895 } GPIO_PINCFG0_FNCSEL0_Enum;
50896 
50897 /* ========================================================  PINCFG1  ======================================================== */
50898 /* =============================================  GPIO PINCFG1 NCEPOL1 [22..22]  ============================================= */
50899 typedef enum {                                  /*!< GPIO_PINCFG1_NCEPOL1                                                      */
50900   GPIO_PINCFG1_NCEPOL1_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
50901   GPIO_PINCFG1_NCEPOL1_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
50902 } GPIO_PINCFG1_NCEPOL1_Enum;
50903 
50904 /* =============================================  GPIO PINCFG1 NCESRC1 [16..21]  ============================================= */
50905 typedef enum {                                  /*!< GPIO_PINCFG1_NCESRC1                                                      */
50906   GPIO_PINCFG1_NCESRC1_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
50907   GPIO_PINCFG1_NCESRC1_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
50908   GPIO_PINCFG1_NCESRC1_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
50909   GPIO_PINCFG1_NCESRC1_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
50910   GPIO_PINCFG1_NCESRC1_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
50911   GPIO_PINCFG1_NCESRC1_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
50912   GPIO_PINCFG1_NCESRC1_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
50913   GPIO_PINCFG1_NCESRC1_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
50914   GPIO_PINCFG1_NCESRC1_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
50915   GPIO_PINCFG1_NCESRC1_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
50916   GPIO_PINCFG1_NCESRC1_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
50917   GPIO_PINCFG1_NCESRC1_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
50918   GPIO_PINCFG1_NCESRC1_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
50919   GPIO_PINCFG1_NCESRC1_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
50920   GPIO_PINCFG1_NCESRC1_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
50921   GPIO_PINCFG1_NCESRC1_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
50922   GPIO_PINCFG1_NCESRC1_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
50923   GPIO_PINCFG1_NCESRC1_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
50924   GPIO_PINCFG1_NCESRC1_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
50925   GPIO_PINCFG1_NCESRC1_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
50926   GPIO_PINCFG1_NCESRC1_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
50927   GPIO_PINCFG1_NCESRC1_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
50928   GPIO_PINCFG1_NCESRC1_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
50929   GPIO_PINCFG1_NCESRC1_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
50930   GPIO_PINCFG1_NCESRC1_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
50931   GPIO_PINCFG1_NCESRC1_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
50932   GPIO_PINCFG1_NCESRC1_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
50933   GPIO_PINCFG1_NCESRC1_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
50934   GPIO_PINCFG1_NCESRC1_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
50935   GPIO_PINCFG1_NCESRC1_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
50936   GPIO_PINCFG1_NCESRC1_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
50937   GPIO_PINCFG1_NCESRC1_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
50938   GPIO_PINCFG1_NCESRC1_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
50939   GPIO_PINCFG1_NCESRC1_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
50940   GPIO_PINCFG1_NCESRC1_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
50941   GPIO_PINCFG1_NCESRC1_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
50942   GPIO_PINCFG1_NCESRC1_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
50943   GPIO_PINCFG1_NCESRC1_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
50944   GPIO_PINCFG1_NCESRC1_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
50945   GPIO_PINCFG1_NCESRC1_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
50946   GPIO_PINCFG1_NCESRC1_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
50947   GPIO_PINCFG1_NCESRC1_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
50948   GPIO_PINCFG1_NCESRC1_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
50949 } GPIO_PINCFG1_NCESRC1_Enum;
50950 
50951 /* ============================================  GPIO PINCFG1 PULLCFG1 [13..15]  ============================================= */
50952 typedef enum {                                  /*!< GPIO_PINCFG1_PULLCFG1                                                     */
50953   GPIO_PINCFG1_PULLCFG1_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
50954   GPIO_PINCFG1_PULLCFG1_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
50955   GPIO_PINCFG1_PULLCFG1_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
50956   GPIO_PINCFG1_PULLCFG1_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
50957   GPIO_PINCFG1_PULLCFG1_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
50958   GPIO_PINCFG1_PULLCFG1_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
50959   GPIO_PINCFG1_PULLCFG1_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
50960   GPIO_PINCFG1_PULLCFG1_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
50961 } GPIO_PINCFG1_PULLCFG1_Enum;
50962 
50963 /* ===============================================  GPIO PINCFG1 DS1 [10..11]  =============================================== */
50964 typedef enum {                                  /*!< GPIO_PINCFG1_DS1                                                          */
50965   GPIO_PINCFG1_DS1_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
50966   GPIO_PINCFG1_DS1_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
50967 } GPIO_PINCFG1_DS1_Enum;
50968 
50969 /* ==============================================  GPIO PINCFG1 OUTCFG1 [8..9]  ============================================== */
50970 typedef enum {                                  /*!< GPIO_PINCFG1_OUTCFG1                                                      */
50971   GPIO_PINCFG1_OUTCFG1_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
50972   GPIO_PINCFG1_OUTCFG1_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
50973                                                      and 1 values on pin.                                                      */
50974   GPIO_PINCFG1_OUTCFG1_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
50975                                                      low, tristate otherwise.                                                  */
50976   GPIO_PINCFG1_OUTCFG1_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
50977                                                      drive 0, 1 of HiZ on pin.                                                 */
50978 } GPIO_PINCFG1_OUTCFG1_Enum;
50979 
50980 /* ==============================================  GPIO PINCFG1 IRPTEN1 [6..7]  ============================================== */
50981 typedef enum {                                  /*!< GPIO_PINCFG1_IRPTEN1                                                      */
50982   GPIO_PINCFG1_IRPTEN1_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
50983   GPIO_PINCFG1_IRPTEN1_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
50984                                                      on this GPIO                                                              */
50985   GPIO_PINCFG1_IRPTEN1_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
50986                                                      on this GPIO                                                              */
50987   GPIO_PINCFG1_IRPTEN1_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
50988                                                      GPIO                                                                      */
50989 } GPIO_PINCFG1_IRPTEN1_Enum;
50990 
50991 /* ==============================================  GPIO PINCFG1 FNCSEL1 [0..3]  ============================================== */
50992 typedef enum {                                  /*!< GPIO_PINCFG1_FNCSEL1                                                      */
50993   GPIO_PINCFG1_FNCSEL1_SWTRACE0        = 0,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
50994   GPIO_PINCFG1_FNCSEL1_SLSDAWIR3       = 1,     /*!< SLSDAWIR3 : I2C Slave I/O data (I2C) 3 Wire Data (SPI)                    */
50995   GPIO_PINCFG1_FNCSEL1_SLMOSI          = 2,     /*!< SLMOSI : SPI Slave input data                                             */
50996   GPIO_PINCFG1_FNCSEL1_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
50997   GPIO_PINCFG1_FNCSEL1_UART2TX         = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
50998   GPIO_PINCFG1_FNCSEL1_UART3TX         = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
50999   GPIO_PINCFG1_FNCSEL1_CT1             = 6,     /*!< CT1 : Timer/Counter input or output; Selection of direction
51000                                                      is done via CTIMER register settings.                                     */
51001   GPIO_PINCFG1_FNCSEL1_NCE1            = 7,     /*!< NCE1 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51002                                                      CE_POLARITY field                                                         */
51003   GPIO_PINCFG1_FNCSEL1_OBSBUS1         = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
51004   GPIO_PINCFG1_FNCSEL1_VCMPO           = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
51005   GPIO_PINCFG1_FNCSEL1_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51006   GPIO_PINCFG1_FNCSEL1_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
51007   GPIO_PINCFG1_FNCSEL1_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51008   GPIO_PINCFG1_FNCSEL1_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
51009   GPIO_PINCFG1_FNCSEL1_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51010   GPIO_PINCFG1_FNCSEL1_SCANIN4         = 15,    /*!< SCANIN4 : Internal function (SCAN)                                        */
51011 } GPIO_PINCFG1_FNCSEL1_Enum;
51012 
51013 /* ========================================================  PINCFG2  ======================================================== */
51014 /* =============================================  GPIO PINCFG2 NCEPOL2 [22..22]  ============================================= */
51015 typedef enum {                                  /*!< GPIO_PINCFG2_NCEPOL2                                                      */
51016   GPIO_PINCFG2_NCEPOL2_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
51017   GPIO_PINCFG2_NCEPOL2_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
51018 } GPIO_PINCFG2_NCEPOL2_Enum;
51019 
51020 /* =============================================  GPIO PINCFG2 NCESRC2 [16..21]  ============================================= */
51021 typedef enum {                                  /*!< GPIO_PINCFG2_NCESRC2                                                      */
51022   GPIO_PINCFG2_NCESRC2_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51023   GPIO_PINCFG2_NCESRC2_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51024   GPIO_PINCFG2_NCESRC2_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51025   GPIO_PINCFG2_NCESRC2_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51026   GPIO_PINCFG2_NCESRC2_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51027   GPIO_PINCFG2_NCESRC2_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51028   GPIO_PINCFG2_NCESRC2_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51029   GPIO_PINCFG2_NCESRC2_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51030   GPIO_PINCFG2_NCESRC2_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51031   GPIO_PINCFG2_NCESRC2_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51032   GPIO_PINCFG2_NCESRC2_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51033   GPIO_PINCFG2_NCESRC2_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51034   GPIO_PINCFG2_NCESRC2_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51035   GPIO_PINCFG2_NCESRC2_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51036   GPIO_PINCFG2_NCESRC2_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51037   GPIO_PINCFG2_NCESRC2_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51038   GPIO_PINCFG2_NCESRC2_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51039   GPIO_PINCFG2_NCESRC2_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51040   GPIO_PINCFG2_NCESRC2_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51041   GPIO_PINCFG2_NCESRC2_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51042   GPIO_PINCFG2_NCESRC2_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51043   GPIO_PINCFG2_NCESRC2_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51044   GPIO_PINCFG2_NCESRC2_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51045   GPIO_PINCFG2_NCESRC2_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51046   GPIO_PINCFG2_NCESRC2_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51047   GPIO_PINCFG2_NCESRC2_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51048   GPIO_PINCFG2_NCESRC2_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51049   GPIO_PINCFG2_NCESRC2_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51050   GPIO_PINCFG2_NCESRC2_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51051   GPIO_PINCFG2_NCESRC2_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51052   GPIO_PINCFG2_NCESRC2_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51053   GPIO_PINCFG2_NCESRC2_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51054   GPIO_PINCFG2_NCESRC2_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51055   GPIO_PINCFG2_NCESRC2_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51056   GPIO_PINCFG2_NCESRC2_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51057   GPIO_PINCFG2_NCESRC2_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51058   GPIO_PINCFG2_NCESRC2_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51059   GPIO_PINCFG2_NCESRC2_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51060   GPIO_PINCFG2_NCESRC2_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51061   GPIO_PINCFG2_NCESRC2_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51062   GPIO_PINCFG2_NCESRC2_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51063   GPIO_PINCFG2_NCESRC2_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51064   GPIO_PINCFG2_NCESRC2_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
51065 } GPIO_PINCFG2_NCESRC2_Enum;
51066 
51067 /* ============================================  GPIO PINCFG2 PULLCFG2 [13..15]  ============================================= */
51068 typedef enum {                                  /*!< GPIO_PINCFG2_PULLCFG2                                                     */
51069   GPIO_PINCFG2_PULLCFG2_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51070   GPIO_PINCFG2_PULLCFG2_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51071   GPIO_PINCFG2_PULLCFG2_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51072   GPIO_PINCFG2_PULLCFG2_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51073   GPIO_PINCFG2_PULLCFG2_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
51074   GPIO_PINCFG2_PULLCFG2_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
51075   GPIO_PINCFG2_PULLCFG2_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
51076   GPIO_PINCFG2_PULLCFG2_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
51077 } GPIO_PINCFG2_PULLCFG2_Enum;
51078 
51079 /* ===============================================  GPIO PINCFG2 DS2 [10..11]  =============================================== */
51080 typedef enum {                                  /*!< GPIO_PINCFG2_DS2                                                          */
51081   GPIO_PINCFG2_DS2_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51082   GPIO_PINCFG2_DS2_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51083 } GPIO_PINCFG2_DS2_Enum;
51084 
51085 /* ==============================================  GPIO PINCFG2 OUTCFG2 [8..9]  ============================================== */
51086 typedef enum {                                  /*!< GPIO_PINCFG2_OUTCFG2                                                      */
51087   GPIO_PINCFG2_OUTCFG2_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
51088   GPIO_PINCFG2_OUTCFG2_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51089                                                      and 1 values on pin.                                                      */
51090   GPIO_PINCFG2_OUTCFG2_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51091                                                      low, tristate otherwise.                                                  */
51092   GPIO_PINCFG2_OUTCFG2_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51093                                                      drive 0, 1 of HiZ on pin.                                                 */
51094 } GPIO_PINCFG2_OUTCFG2_Enum;
51095 
51096 /* ==============================================  GPIO PINCFG2 IRPTEN2 [6..7]  ============================================== */
51097 typedef enum {                                  /*!< GPIO_PINCFG2_IRPTEN2                                                      */
51098   GPIO_PINCFG2_IRPTEN2_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51099   GPIO_PINCFG2_IRPTEN2_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51100                                                      on this GPIO                                                              */
51101   GPIO_PINCFG2_IRPTEN2_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51102                                                      on this GPIO                                                              */
51103   GPIO_PINCFG2_IRPTEN2_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51104                                                      GPIO                                                                      */
51105 } GPIO_PINCFG2_IRPTEN2_Enum;
51106 
51107 /* ==============================================  GPIO PINCFG2 FNCSEL2 [0..3]  ============================================== */
51108 typedef enum {                                  /*!< GPIO_PINCFG2_FNCSEL2                                                      */
51109   GPIO_PINCFG2_FNCSEL2_SWTRACE1        = 0,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
51110   GPIO_PINCFG2_FNCSEL2_SLMISO          = 1,     /*!< SLMISO : SPI Slave output data                                            */
51111   GPIO_PINCFG2_FNCSEL2_TRIG1           = 2,     /*!< TRIG1 : ADC trigger input                                                 */
51112   GPIO_PINCFG2_FNCSEL2_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
51113   GPIO_PINCFG2_FNCSEL2_UART0RX         = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
51114   GPIO_PINCFG2_FNCSEL2_UART1RX         = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
51115   GPIO_PINCFG2_FNCSEL2_CT2             = 6,     /*!< CT2 : Timer/Counter input or output; Selection of direction
51116                                                      is done via CTIMER register settings.                                     */
51117   GPIO_PINCFG2_FNCSEL2_NCE2            = 7,     /*!< NCE2 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51118                                                      CE_POLARITY field                                                         */
51119   GPIO_PINCFG2_FNCSEL2_OBSBUS2         = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
51120   GPIO_PINCFG2_FNCSEL2_VCMPO           = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
51121   GPIO_PINCFG2_FNCSEL2_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51122   GPIO_PINCFG2_FNCSEL2_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
51123   GPIO_PINCFG2_FNCSEL2_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51124   GPIO_PINCFG2_FNCSEL2_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
51125   GPIO_PINCFG2_FNCSEL2_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51126   GPIO_PINCFG2_FNCSEL2_SCANRSTN        = 15,    /*!< SCANRSTN : Internal function (SCAN)                                       */
51127 } GPIO_PINCFG2_FNCSEL2_Enum;
51128 
51129 /* ========================================================  PINCFG3  ======================================================== */
51130 /* =============================================  GPIO PINCFG3 NCEPOL3 [22..22]  ============================================= */
51131 typedef enum {                                  /*!< GPIO_PINCFG3_NCEPOL3                                                      */
51132   GPIO_PINCFG3_NCEPOL3_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
51133   GPIO_PINCFG3_NCEPOL3_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
51134 } GPIO_PINCFG3_NCEPOL3_Enum;
51135 
51136 /* =============================================  GPIO PINCFG3 NCESRC3 [16..21]  ============================================= */
51137 typedef enum {                                  /*!< GPIO_PINCFG3_NCESRC3                                                      */
51138   GPIO_PINCFG3_NCESRC3_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51139   GPIO_PINCFG3_NCESRC3_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51140   GPIO_PINCFG3_NCESRC3_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51141   GPIO_PINCFG3_NCESRC3_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51142   GPIO_PINCFG3_NCESRC3_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51143   GPIO_PINCFG3_NCESRC3_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51144   GPIO_PINCFG3_NCESRC3_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51145   GPIO_PINCFG3_NCESRC3_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51146   GPIO_PINCFG3_NCESRC3_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51147   GPIO_PINCFG3_NCESRC3_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51148   GPIO_PINCFG3_NCESRC3_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51149   GPIO_PINCFG3_NCESRC3_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51150   GPIO_PINCFG3_NCESRC3_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51151   GPIO_PINCFG3_NCESRC3_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51152   GPIO_PINCFG3_NCESRC3_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51153   GPIO_PINCFG3_NCESRC3_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51154   GPIO_PINCFG3_NCESRC3_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51155   GPIO_PINCFG3_NCESRC3_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51156   GPIO_PINCFG3_NCESRC3_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51157   GPIO_PINCFG3_NCESRC3_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51158   GPIO_PINCFG3_NCESRC3_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51159   GPIO_PINCFG3_NCESRC3_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51160   GPIO_PINCFG3_NCESRC3_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51161   GPIO_PINCFG3_NCESRC3_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51162   GPIO_PINCFG3_NCESRC3_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51163   GPIO_PINCFG3_NCESRC3_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51164   GPIO_PINCFG3_NCESRC3_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51165   GPIO_PINCFG3_NCESRC3_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51166   GPIO_PINCFG3_NCESRC3_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51167   GPIO_PINCFG3_NCESRC3_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51168   GPIO_PINCFG3_NCESRC3_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51169   GPIO_PINCFG3_NCESRC3_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51170   GPIO_PINCFG3_NCESRC3_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51171   GPIO_PINCFG3_NCESRC3_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51172   GPIO_PINCFG3_NCESRC3_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51173   GPIO_PINCFG3_NCESRC3_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51174   GPIO_PINCFG3_NCESRC3_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51175   GPIO_PINCFG3_NCESRC3_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51176   GPIO_PINCFG3_NCESRC3_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51177   GPIO_PINCFG3_NCESRC3_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51178   GPIO_PINCFG3_NCESRC3_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51179   GPIO_PINCFG3_NCESRC3_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51180   GPIO_PINCFG3_NCESRC3_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
51181 } GPIO_PINCFG3_NCESRC3_Enum;
51182 
51183 /* ============================================  GPIO PINCFG3 PULLCFG3 [13..15]  ============================================= */
51184 typedef enum {                                  /*!< GPIO_PINCFG3_PULLCFG3                                                     */
51185   GPIO_PINCFG3_PULLCFG3_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51186   GPIO_PINCFG3_PULLCFG3_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51187   GPIO_PINCFG3_PULLCFG3_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51188   GPIO_PINCFG3_PULLCFG3_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51189   GPIO_PINCFG3_PULLCFG3_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
51190   GPIO_PINCFG3_PULLCFG3_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
51191   GPIO_PINCFG3_PULLCFG3_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
51192   GPIO_PINCFG3_PULLCFG3_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
51193 } GPIO_PINCFG3_PULLCFG3_Enum;
51194 
51195 /* ===============================================  GPIO PINCFG3 DS3 [10..11]  =============================================== */
51196 typedef enum {                                  /*!< GPIO_PINCFG3_DS3                                                          */
51197   GPIO_PINCFG3_DS3_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51198   GPIO_PINCFG3_DS3_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51199 } GPIO_PINCFG3_DS3_Enum;
51200 
51201 /* ==============================================  GPIO PINCFG3 OUTCFG3 [8..9]  ============================================== */
51202 typedef enum {                                  /*!< GPIO_PINCFG3_OUTCFG3                                                      */
51203   GPIO_PINCFG3_OUTCFG3_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
51204   GPIO_PINCFG3_OUTCFG3_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51205                                                      and 1 values on pin.                                                      */
51206   GPIO_PINCFG3_OUTCFG3_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51207                                                      low, tristate otherwise.                                                  */
51208   GPIO_PINCFG3_OUTCFG3_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51209                                                      drive 0, 1 of HiZ on pin.                                                 */
51210 } GPIO_PINCFG3_OUTCFG3_Enum;
51211 
51212 /* ==============================================  GPIO PINCFG3 IRPTEN3 [6..7]  ============================================== */
51213 typedef enum {                                  /*!< GPIO_PINCFG3_IRPTEN3                                                      */
51214   GPIO_PINCFG3_IRPTEN3_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51215   GPIO_PINCFG3_IRPTEN3_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51216                                                      on this GPIO                                                              */
51217   GPIO_PINCFG3_IRPTEN3_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51218                                                      on this GPIO                                                              */
51219   GPIO_PINCFG3_IRPTEN3_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51220                                                      GPIO                                                                      */
51221 } GPIO_PINCFG3_IRPTEN3_Enum;
51222 
51223 /* ==============================================  GPIO PINCFG3 FNCSEL3 [0..3]  ============================================== */
51224 typedef enum {                                  /*!< GPIO_PINCFG3_FNCSEL3                                                      */
51225   GPIO_PINCFG3_FNCSEL3_SWTRACE2        = 0,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
51226   GPIO_PINCFG3_FNCSEL3_SLnCE           = 1,     /*!< SLnCE : SPI Slave chip enable                                             */
51227   GPIO_PINCFG3_FNCSEL3_SWO             = 2,     /*!< SWO : Serial Wire Output                                                  */
51228   GPIO_PINCFG3_FNCSEL3_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
51229   GPIO_PINCFG3_FNCSEL3_UART2RX         = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
51230   GPIO_PINCFG3_FNCSEL3_UART3RX         = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
51231   GPIO_PINCFG3_FNCSEL3_CT3             = 6,     /*!< CT3 : Timer/Counter input or output; Selection of direction
51232                                                      is done via CTIMER register settings.                                     */
51233   GPIO_PINCFG3_FNCSEL3_NCE3            = 7,     /*!< NCE3 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51234                                                      CE_POLARITY field                                                         */
51235   GPIO_PINCFG3_FNCSEL3_OBSBUS3         = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
51236   GPIO_PINCFG3_FNCSEL3_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51237   GPIO_PINCFG3_FNCSEL3_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51238   GPIO_PINCFG3_FNCSEL3_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
51239   GPIO_PINCFG3_FNCSEL3_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51240   GPIO_PINCFG3_FNCSEL3_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
51241   GPIO_PINCFG3_FNCSEL3_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51242   GPIO_PINCFG3_FNCSEL3_SCANIN5         = 15,    /*!< SCANIN5 : Internal function (SCAN)                                        */
51243 } GPIO_PINCFG3_FNCSEL3_Enum;
51244 
51245 /* ========================================================  PINCFG4  ======================================================== */
51246 /* =============================================  GPIO PINCFG4 NCEPOL4 [22..22]  ============================================= */
51247 typedef enum {                                  /*!< GPIO_PINCFG4_NCEPOL4                                                      */
51248   GPIO_PINCFG4_NCEPOL4_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
51249   GPIO_PINCFG4_NCEPOL4_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
51250 } GPIO_PINCFG4_NCEPOL4_Enum;
51251 
51252 /* =============================================  GPIO PINCFG4 NCESRC4 [16..21]  ============================================= */
51253 typedef enum {                                  /*!< GPIO_PINCFG4_NCESRC4                                                      */
51254   GPIO_PINCFG4_NCESRC4_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51255   GPIO_PINCFG4_NCESRC4_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51256   GPIO_PINCFG4_NCESRC4_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51257   GPIO_PINCFG4_NCESRC4_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51258   GPIO_PINCFG4_NCESRC4_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51259   GPIO_PINCFG4_NCESRC4_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51260   GPIO_PINCFG4_NCESRC4_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51261   GPIO_PINCFG4_NCESRC4_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51262   GPIO_PINCFG4_NCESRC4_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51263   GPIO_PINCFG4_NCESRC4_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51264   GPIO_PINCFG4_NCESRC4_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51265   GPIO_PINCFG4_NCESRC4_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51266   GPIO_PINCFG4_NCESRC4_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51267   GPIO_PINCFG4_NCESRC4_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51268   GPIO_PINCFG4_NCESRC4_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51269   GPIO_PINCFG4_NCESRC4_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51270   GPIO_PINCFG4_NCESRC4_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51271   GPIO_PINCFG4_NCESRC4_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51272   GPIO_PINCFG4_NCESRC4_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51273   GPIO_PINCFG4_NCESRC4_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51274   GPIO_PINCFG4_NCESRC4_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51275   GPIO_PINCFG4_NCESRC4_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51276   GPIO_PINCFG4_NCESRC4_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51277   GPIO_PINCFG4_NCESRC4_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51278   GPIO_PINCFG4_NCESRC4_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51279   GPIO_PINCFG4_NCESRC4_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51280   GPIO_PINCFG4_NCESRC4_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51281   GPIO_PINCFG4_NCESRC4_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51282   GPIO_PINCFG4_NCESRC4_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51283   GPIO_PINCFG4_NCESRC4_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51284   GPIO_PINCFG4_NCESRC4_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51285   GPIO_PINCFG4_NCESRC4_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51286   GPIO_PINCFG4_NCESRC4_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51287   GPIO_PINCFG4_NCESRC4_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51288   GPIO_PINCFG4_NCESRC4_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51289   GPIO_PINCFG4_NCESRC4_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51290   GPIO_PINCFG4_NCESRC4_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51291   GPIO_PINCFG4_NCESRC4_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51292   GPIO_PINCFG4_NCESRC4_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51293   GPIO_PINCFG4_NCESRC4_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51294   GPIO_PINCFG4_NCESRC4_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51295   GPIO_PINCFG4_NCESRC4_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51296   GPIO_PINCFG4_NCESRC4_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
51297 } GPIO_PINCFG4_NCESRC4_Enum;
51298 
51299 /* ============================================  GPIO PINCFG4 PULLCFG4 [13..15]  ============================================= */
51300 typedef enum {                                  /*!< GPIO_PINCFG4_PULLCFG4                                                     */
51301   GPIO_PINCFG4_PULLCFG4_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51302   GPIO_PINCFG4_PULLCFG4_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51303   GPIO_PINCFG4_PULLCFG4_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51304   GPIO_PINCFG4_PULLCFG4_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51305   GPIO_PINCFG4_PULLCFG4_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
51306   GPIO_PINCFG4_PULLCFG4_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
51307   GPIO_PINCFG4_PULLCFG4_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
51308   GPIO_PINCFG4_PULLCFG4_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
51309 } GPIO_PINCFG4_PULLCFG4_Enum;
51310 
51311 /* ===============================================  GPIO PINCFG4 DS4 [10..11]  =============================================== */
51312 typedef enum {                                  /*!< GPIO_PINCFG4_DS4                                                          */
51313   GPIO_PINCFG4_DS4_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51314   GPIO_PINCFG4_DS4_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51315 } GPIO_PINCFG4_DS4_Enum;
51316 
51317 /* ==============================================  GPIO PINCFG4 OUTCFG4 [8..9]  ============================================== */
51318 typedef enum {                                  /*!< GPIO_PINCFG4_OUTCFG4                                                      */
51319   GPIO_PINCFG4_OUTCFG4_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
51320   GPIO_PINCFG4_OUTCFG4_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51321                                                      and 1 values on pin.                                                      */
51322   GPIO_PINCFG4_OUTCFG4_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51323                                                      low, tristate otherwise.                                                  */
51324   GPIO_PINCFG4_OUTCFG4_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51325                                                      drive 0, 1 of HiZ on pin.                                                 */
51326 } GPIO_PINCFG4_OUTCFG4_Enum;
51327 
51328 /* ==============================================  GPIO PINCFG4 IRPTEN4 [6..7]  ============================================== */
51329 typedef enum {                                  /*!< GPIO_PINCFG4_IRPTEN4                                                      */
51330   GPIO_PINCFG4_IRPTEN4_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51331   GPIO_PINCFG4_IRPTEN4_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51332                                                      on this GPIO                                                              */
51333   GPIO_PINCFG4_IRPTEN4_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51334                                                      on this GPIO                                                              */
51335   GPIO_PINCFG4_IRPTEN4_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51336                                                      GPIO                                                                      */
51337 } GPIO_PINCFG4_IRPTEN4_Enum;
51338 
51339 /* ==============================================  GPIO PINCFG4 FNCSEL4 [0..3]  ============================================== */
51340 typedef enum {                                  /*!< GPIO_PINCFG4_FNCSEL4                                                      */
51341   GPIO_PINCFG4_FNCSEL4_SWTRACE3        = 0,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
51342   GPIO_PINCFG4_FNCSEL4_SLINT           = 1,     /*!< SLINT : Configurable Slave Interrupt                                      */
51343   GPIO_PINCFG4_FNCSEL4_32KHzXT         = 2,     /*!< 32KHzXT : 32kHZ from analog                                               */
51344   GPIO_PINCFG4_FNCSEL4_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
51345   GPIO_PINCFG4_FNCSEL4_UART0RTS        = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
51346   GPIO_PINCFG4_FNCSEL4_UART1RTS        = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
51347   GPIO_PINCFG4_FNCSEL4_CT4             = 6,     /*!< CT4 : Timer/Counter input or output; Selection of direction
51348                                                      is done via CTIMER register settings.                                     */
51349   GPIO_PINCFG4_FNCSEL4_NCE4            = 7,     /*!< NCE4 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51350                                                      CE_POLARITY field                                                         */
51351   GPIO_PINCFG4_FNCSEL4_OBSBUS4         = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
51352   GPIO_PINCFG4_FNCSEL4_I2S0_SDIN       = 9,     /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
51353   GPIO_PINCFG4_FNCSEL4_I2S1_SDIN       = 10,    /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
51354   GPIO_PINCFG4_FNCSEL4_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
51355   GPIO_PINCFG4_FNCSEL4_FLB_TDO         = 12,    /*!< FLB_TDO : Internal function (Flash Bist)                                  */
51356   GPIO_PINCFG4_FNCSEL4_FLLOAD_DIR      = 13,    /*!< FLLOAD_DIR : Internal function (Flash parallel load)                      */
51357   GPIO_PINCFG4_FNCSEL4_MDA_TDO         = 14,    /*!< MDA_TDO : Internal function (MBIST)                                       */
51358   GPIO_PINCFG4_FNCSEL4_OPCG_TRIG       = 15,    /*!< OPCG_TRIG : Internal function (SCAN)                                      */
51359 } GPIO_PINCFG4_FNCSEL4_Enum;
51360 
51361 /* ========================================================  PINCFG5  ======================================================== */
51362 /* =============================================  GPIO PINCFG5 NCEPOL5 [22..22]  ============================================= */
51363 typedef enum {                                  /*!< GPIO_PINCFG5_NCEPOL5                                                      */
51364   GPIO_PINCFG5_NCEPOL5_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
51365   GPIO_PINCFG5_NCEPOL5_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
51366 } GPIO_PINCFG5_NCEPOL5_Enum;
51367 
51368 /* =============================================  GPIO PINCFG5 NCESRC5 [16..21]  ============================================= */
51369 typedef enum {                                  /*!< GPIO_PINCFG5_NCESRC5                                                      */
51370   GPIO_PINCFG5_NCESRC5_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51371   GPIO_PINCFG5_NCESRC5_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51372   GPIO_PINCFG5_NCESRC5_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51373   GPIO_PINCFG5_NCESRC5_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51374   GPIO_PINCFG5_NCESRC5_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51375   GPIO_PINCFG5_NCESRC5_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51376   GPIO_PINCFG5_NCESRC5_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51377   GPIO_PINCFG5_NCESRC5_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51378   GPIO_PINCFG5_NCESRC5_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51379   GPIO_PINCFG5_NCESRC5_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51380   GPIO_PINCFG5_NCESRC5_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51381   GPIO_PINCFG5_NCESRC5_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51382   GPIO_PINCFG5_NCESRC5_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51383   GPIO_PINCFG5_NCESRC5_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51384   GPIO_PINCFG5_NCESRC5_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51385   GPIO_PINCFG5_NCESRC5_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51386   GPIO_PINCFG5_NCESRC5_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51387   GPIO_PINCFG5_NCESRC5_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51388   GPIO_PINCFG5_NCESRC5_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51389   GPIO_PINCFG5_NCESRC5_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51390   GPIO_PINCFG5_NCESRC5_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51391   GPIO_PINCFG5_NCESRC5_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51392   GPIO_PINCFG5_NCESRC5_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51393   GPIO_PINCFG5_NCESRC5_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51394   GPIO_PINCFG5_NCESRC5_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51395   GPIO_PINCFG5_NCESRC5_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51396   GPIO_PINCFG5_NCESRC5_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51397   GPIO_PINCFG5_NCESRC5_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51398   GPIO_PINCFG5_NCESRC5_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51399   GPIO_PINCFG5_NCESRC5_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51400   GPIO_PINCFG5_NCESRC5_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51401   GPIO_PINCFG5_NCESRC5_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51402   GPIO_PINCFG5_NCESRC5_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51403   GPIO_PINCFG5_NCESRC5_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51404   GPIO_PINCFG5_NCESRC5_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51405   GPIO_PINCFG5_NCESRC5_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51406   GPIO_PINCFG5_NCESRC5_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51407   GPIO_PINCFG5_NCESRC5_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51408   GPIO_PINCFG5_NCESRC5_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51409   GPIO_PINCFG5_NCESRC5_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51410   GPIO_PINCFG5_NCESRC5_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51411   GPIO_PINCFG5_NCESRC5_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51412   GPIO_PINCFG5_NCESRC5_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
51413 } GPIO_PINCFG5_NCESRC5_Enum;
51414 
51415 /* ============================================  GPIO PINCFG5 PULLCFG5 [13..15]  ============================================= */
51416 typedef enum {                                  /*!< GPIO_PINCFG5_PULLCFG5                                                     */
51417   GPIO_PINCFG5_PULLCFG5_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51418   GPIO_PINCFG5_PULLCFG5_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51419   GPIO_PINCFG5_PULLCFG5_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51420   GPIO_PINCFG5_PULLCFG5_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51421   GPIO_PINCFG5_PULLCFG5_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
51422   GPIO_PINCFG5_PULLCFG5_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
51423   GPIO_PINCFG5_PULLCFG5_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
51424   GPIO_PINCFG5_PULLCFG5_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
51425 } GPIO_PINCFG5_PULLCFG5_Enum;
51426 
51427 /* ===============================================  GPIO PINCFG5 DS5 [10..11]  =============================================== */
51428 typedef enum {                                  /*!< GPIO_PINCFG5_DS5                                                          */
51429   GPIO_PINCFG5_DS5_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51430   GPIO_PINCFG5_DS5_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51431   GPIO_PINCFG5_DS5_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
51432   GPIO_PINCFG5_DS5_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
51433 } GPIO_PINCFG5_DS5_Enum;
51434 
51435 /* ==============================================  GPIO PINCFG5 OUTCFG5 [8..9]  ============================================== */
51436 typedef enum {                                  /*!< GPIO_PINCFG5_OUTCFG5                                                      */
51437   GPIO_PINCFG5_OUTCFG5_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
51438   GPIO_PINCFG5_OUTCFG5_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51439                                                      and 1 values on pin.                                                      */
51440   GPIO_PINCFG5_OUTCFG5_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51441                                                      low, tristate otherwise.                                                  */
51442   GPIO_PINCFG5_OUTCFG5_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51443                                                      drive 0, 1 of HiZ on pin.                                                 */
51444 } GPIO_PINCFG5_OUTCFG5_Enum;
51445 
51446 /* ==============================================  GPIO PINCFG5 IRPTEN5 [6..7]  ============================================== */
51447 typedef enum {                                  /*!< GPIO_PINCFG5_IRPTEN5                                                      */
51448   GPIO_PINCFG5_IRPTEN5_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51449   GPIO_PINCFG5_IRPTEN5_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51450                                                      on this GPIO                                                              */
51451   GPIO_PINCFG5_IRPTEN5_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51452                                                      on this GPIO                                                              */
51453   GPIO_PINCFG5_IRPTEN5_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51454                                                      GPIO                                                                      */
51455 } GPIO_PINCFG5_IRPTEN5_Enum;
51456 
51457 /* ==============================================  GPIO PINCFG5 FNCSEL5 [0..3]  ============================================== */
51458 typedef enum {                                  /*!< GPIO_PINCFG5_FNCSEL5                                                      */
51459   GPIO_PINCFG5_FNCSEL5_M0SCL           = 0,     /*!< M0SCL : Serial I2C Master Clock output (IOM 0)                            */
51460   GPIO_PINCFG5_FNCSEL5_M0SCK           = 1,     /*!< M0SCK : Serial SPI Master Clock output (IOM 0)                            */
51461   GPIO_PINCFG5_FNCSEL5_I2S0_CLK        = 2,     /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
51462                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51463                                                      2)                                                                        */
51464   GPIO_PINCFG5_FNCSEL5_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
51465   GPIO_PINCFG5_FNCSEL5_UART2RTS        = 4,     /*!< UART2RTS : UART Request to Send (RTS) (UART 2)                            */
51466   GPIO_PINCFG5_FNCSEL5_UART3RTS        = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
51467   GPIO_PINCFG5_FNCSEL5_CT5             = 6,     /*!< CT5 : Timer/Counter input or output; Selection of direction
51468                                                      is done via CTIMER register settings.                                     */
51469   GPIO_PINCFG5_FNCSEL5_NCE5            = 7,     /*!< NCE5 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51470                                                      CE_POLARITY field                                                         */
51471   GPIO_PINCFG5_FNCSEL5_OBSBUS5         = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
51472   GPIO_PINCFG5_FNCSEL5_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51473   GPIO_PINCFG5_FNCSEL5_I2S1_CLK        = 10,    /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
51474                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51475                                                      2)                                                                        */
51476   GPIO_PINCFG5_FNCSEL5_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
51477   GPIO_PINCFG5_FNCSEL5_FLB_TDI         = 12,    /*!< FLB_TDI : Internal function (Flash Bist)                                  */
51478   GPIO_PINCFG5_FNCSEL5_FLLOAD_DATA     = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
51479   GPIO_PINCFG5_FNCSEL5_MDA_SRST        = 14,    /*!< MDA_SRST : Internal function (MBIST)                                      */
51480   GPIO_PINCFG5_FNCSEL5_DFT_ISO         = 15,    /*!< DFT_ISO : Internal function (SCAN)                                        */
51481 } GPIO_PINCFG5_FNCSEL5_Enum;
51482 
51483 /* ========================================================  PINCFG6  ======================================================== */
51484 /* =============================================  GPIO PINCFG6 NCEPOL6 [22..22]  ============================================= */
51485 typedef enum {                                  /*!< GPIO_PINCFG6_NCEPOL6                                                      */
51486   GPIO_PINCFG6_NCEPOL6_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
51487   GPIO_PINCFG6_NCEPOL6_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
51488 } GPIO_PINCFG6_NCEPOL6_Enum;
51489 
51490 /* =============================================  GPIO PINCFG6 NCESRC6 [16..21]  ============================================= */
51491 typedef enum {                                  /*!< GPIO_PINCFG6_NCESRC6                                                      */
51492   GPIO_PINCFG6_NCESRC6_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51493   GPIO_PINCFG6_NCESRC6_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51494   GPIO_PINCFG6_NCESRC6_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51495   GPIO_PINCFG6_NCESRC6_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51496   GPIO_PINCFG6_NCESRC6_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51497   GPIO_PINCFG6_NCESRC6_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51498   GPIO_PINCFG6_NCESRC6_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51499   GPIO_PINCFG6_NCESRC6_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51500   GPIO_PINCFG6_NCESRC6_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51501   GPIO_PINCFG6_NCESRC6_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51502   GPIO_PINCFG6_NCESRC6_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51503   GPIO_PINCFG6_NCESRC6_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51504   GPIO_PINCFG6_NCESRC6_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51505   GPIO_PINCFG6_NCESRC6_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51506   GPIO_PINCFG6_NCESRC6_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51507   GPIO_PINCFG6_NCESRC6_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51508   GPIO_PINCFG6_NCESRC6_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51509   GPIO_PINCFG6_NCESRC6_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51510   GPIO_PINCFG6_NCESRC6_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51511   GPIO_PINCFG6_NCESRC6_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51512   GPIO_PINCFG6_NCESRC6_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51513   GPIO_PINCFG6_NCESRC6_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51514   GPIO_PINCFG6_NCESRC6_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51515   GPIO_PINCFG6_NCESRC6_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51516   GPIO_PINCFG6_NCESRC6_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51517   GPIO_PINCFG6_NCESRC6_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51518   GPIO_PINCFG6_NCESRC6_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51519   GPIO_PINCFG6_NCESRC6_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51520   GPIO_PINCFG6_NCESRC6_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51521   GPIO_PINCFG6_NCESRC6_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51522   GPIO_PINCFG6_NCESRC6_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51523   GPIO_PINCFG6_NCESRC6_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51524   GPIO_PINCFG6_NCESRC6_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51525   GPIO_PINCFG6_NCESRC6_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51526   GPIO_PINCFG6_NCESRC6_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51527   GPIO_PINCFG6_NCESRC6_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51528   GPIO_PINCFG6_NCESRC6_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51529   GPIO_PINCFG6_NCESRC6_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51530   GPIO_PINCFG6_NCESRC6_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51531   GPIO_PINCFG6_NCESRC6_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51532   GPIO_PINCFG6_NCESRC6_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51533   GPIO_PINCFG6_NCESRC6_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51534   GPIO_PINCFG6_NCESRC6_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
51535 } GPIO_PINCFG6_NCESRC6_Enum;
51536 
51537 /* ============================================  GPIO PINCFG6 PULLCFG6 [13..15]  ============================================= */
51538 typedef enum {                                  /*!< GPIO_PINCFG6_PULLCFG6                                                     */
51539   GPIO_PINCFG6_PULLCFG6_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51540   GPIO_PINCFG6_PULLCFG6_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51541   GPIO_PINCFG6_PULLCFG6_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51542   GPIO_PINCFG6_PULLCFG6_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51543   GPIO_PINCFG6_PULLCFG6_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
51544   GPIO_PINCFG6_PULLCFG6_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
51545   GPIO_PINCFG6_PULLCFG6_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
51546   GPIO_PINCFG6_PULLCFG6_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
51547 } GPIO_PINCFG6_PULLCFG6_Enum;
51548 
51549 /* ===============================================  GPIO PINCFG6 DS6 [10..11]  =============================================== */
51550 typedef enum {                                  /*!< GPIO_PINCFG6_DS6                                                          */
51551   GPIO_PINCFG6_DS6_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51552   GPIO_PINCFG6_DS6_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51553   GPIO_PINCFG6_DS6_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
51554   GPIO_PINCFG6_DS6_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
51555 } GPIO_PINCFG6_DS6_Enum;
51556 
51557 /* ==============================================  GPIO PINCFG6 OUTCFG6 [8..9]  ============================================== */
51558 typedef enum {                                  /*!< GPIO_PINCFG6_OUTCFG6                                                      */
51559   GPIO_PINCFG6_OUTCFG6_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
51560   GPIO_PINCFG6_OUTCFG6_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51561                                                      and 1 values on pin.                                                      */
51562   GPIO_PINCFG6_OUTCFG6_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51563                                                      low, tristate otherwise.                                                  */
51564   GPIO_PINCFG6_OUTCFG6_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51565                                                      drive 0, 1 of HiZ on pin.                                                 */
51566 } GPIO_PINCFG6_OUTCFG6_Enum;
51567 
51568 /* ==============================================  GPIO PINCFG6 IRPTEN6 [6..7]  ============================================== */
51569 typedef enum {                                  /*!< GPIO_PINCFG6_IRPTEN6                                                      */
51570   GPIO_PINCFG6_IRPTEN6_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51571   GPIO_PINCFG6_IRPTEN6_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51572                                                      on this GPIO                                                              */
51573   GPIO_PINCFG6_IRPTEN6_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51574                                                      on this GPIO                                                              */
51575   GPIO_PINCFG6_IRPTEN6_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51576                                                      GPIO                                                                      */
51577 } GPIO_PINCFG6_IRPTEN6_Enum;
51578 
51579 /* ==============================================  GPIO PINCFG6 FNCSEL6 [0..3]  ============================================== */
51580 typedef enum {                                  /*!< GPIO_PINCFG6_FNCSEL6                                                      */
51581   GPIO_PINCFG6_FNCSEL6_M0SDAWIR3       = 0,     /*!< M0SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
51582                                                      Master Data I/O (SPI 3 wire mode) (IOM 0)                                 */
51583   GPIO_PINCFG6_FNCSEL6_M0MOSI          = 1,     /*!< M0MOSI : Serial SPI Master MOSI output (IOM 0)                            */
51584   GPIO_PINCFG6_FNCSEL6_I2S0_DATA       = 2,     /*!< I2S0_DATA : Bidirectional I2S Data. Operates in output mode
51585                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51586                                                      2)                                                                        */
51587   GPIO_PINCFG6_FNCSEL6_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
51588   GPIO_PINCFG6_FNCSEL6_UART0CTS        = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
51589   GPIO_PINCFG6_FNCSEL6_UART1CTS        = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
51590   GPIO_PINCFG6_FNCSEL6_CT6             = 6,     /*!< CT6 : Timer/Counter input or output; Selection of direction
51591                                                      is done via CTIMER register settings.                                     */
51592   GPIO_PINCFG6_FNCSEL6_NCE6            = 7,     /*!< NCE6 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51593                                                      CE_POLARITY field                                                         */
51594   GPIO_PINCFG6_FNCSEL6_OBSBUS6         = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
51595   GPIO_PINCFG6_FNCSEL6_I2S0_SDOUT      = 9,     /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
51596   GPIO_PINCFG6_FNCSEL6_I2S1_SDOUT      = 10,    /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
51597   GPIO_PINCFG6_FNCSEL6_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
51598   GPIO_PINCFG6_FNCSEL6_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51599   GPIO_PINCFG6_FNCSEL6_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
51600   GPIO_PINCFG6_FNCSEL6_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51601   GPIO_PINCFG6_FNCSEL6_SCANIN6         = 15,    /*!< SCANIN6 : Internal function (SCAN)                                        */
51602 } GPIO_PINCFG6_FNCSEL6_Enum;
51603 
51604 /* ========================================================  PINCFG7  ======================================================== */
51605 /* =============================================  GPIO PINCFG7 NCEPOL7 [22..22]  ============================================= */
51606 typedef enum {                                  /*!< GPIO_PINCFG7_NCEPOL7                                                      */
51607   GPIO_PINCFG7_NCEPOL7_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
51608   GPIO_PINCFG7_NCEPOL7_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
51609 } GPIO_PINCFG7_NCEPOL7_Enum;
51610 
51611 /* =============================================  GPIO PINCFG7 NCESRC7 [16..21]  ============================================= */
51612 typedef enum {                                  /*!< GPIO_PINCFG7_NCESRC7                                                      */
51613   GPIO_PINCFG7_NCESRC7_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51614   GPIO_PINCFG7_NCESRC7_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51615   GPIO_PINCFG7_NCESRC7_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51616   GPIO_PINCFG7_NCESRC7_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51617   GPIO_PINCFG7_NCESRC7_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51618   GPIO_PINCFG7_NCESRC7_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51619   GPIO_PINCFG7_NCESRC7_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51620   GPIO_PINCFG7_NCESRC7_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51621   GPIO_PINCFG7_NCESRC7_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51622   GPIO_PINCFG7_NCESRC7_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51623   GPIO_PINCFG7_NCESRC7_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51624   GPIO_PINCFG7_NCESRC7_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51625   GPIO_PINCFG7_NCESRC7_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51626   GPIO_PINCFG7_NCESRC7_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51627   GPIO_PINCFG7_NCESRC7_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51628   GPIO_PINCFG7_NCESRC7_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51629   GPIO_PINCFG7_NCESRC7_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51630   GPIO_PINCFG7_NCESRC7_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51631   GPIO_PINCFG7_NCESRC7_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51632   GPIO_PINCFG7_NCESRC7_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51633   GPIO_PINCFG7_NCESRC7_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51634   GPIO_PINCFG7_NCESRC7_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51635   GPIO_PINCFG7_NCESRC7_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51636   GPIO_PINCFG7_NCESRC7_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51637   GPIO_PINCFG7_NCESRC7_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51638   GPIO_PINCFG7_NCESRC7_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51639   GPIO_PINCFG7_NCESRC7_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51640   GPIO_PINCFG7_NCESRC7_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51641   GPIO_PINCFG7_NCESRC7_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51642   GPIO_PINCFG7_NCESRC7_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51643   GPIO_PINCFG7_NCESRC7_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51644   GPIO_PINCFG7_NCESRC7_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51645   GPIO_PINCFG7_NCESRC7_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51646   GPIO_PINCFG7_NCESRC7_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51647   GPIO_PINCFG7_NCESRC7_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51648   GPIO_PINCFG7_NCESRC7_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51649   GPIO_PINCFG7_NCESRC7_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51650   GPIO_PINCFG7_NCESRC7_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51651   GPIO_PINCFG7_NCESRC7_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51652   GPIO_PINCFG7_NCESRC7_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51653   GPIO_PINCFG7_NCESRC7_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51654   GPIO_PINCFG7_NCESRC7_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51655   GPIO_PINCFG7_NCESRC7_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
51656 } GPIO_PINCFG7_NCESRC7_Enum;
51657 
51658 /* ============================================  GPIO PINCFG7 PULLCFG7 [13..15]  ============================================= */
51659 typedef enum {                                  /*!< GPIO_PINCFG7_PULLCFG7                                                     */
51660   GPIO_PINCFG7_PULLCFG7_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51661   GPIO_PINCFG7_PULLCFG7_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51662   GPIO_PINCFG7_PULLCFG7_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51663   GPIO_PINCFG7_PULLCFG7_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51664   GPIO_PINCFG7_PULLCFG7_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
51665   GPIO_PINCFG7_PULLCFG7_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
51666   GPIO_PINCFG7_PULLCFG7_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
51667   GPIO_PINCFG7_PULLCFG7_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
51668 } GPIO_PINCFG7_PULLCFG7_Enum;
51669 
51670 /* ===============================================  GPIO PINCFG7 DS7 [10..11]  =============================================== */
51671 typedef enum {                                  /*!< GPIO_PINCFG7_DS7                                                          */
51672   GPIO_PINCFG7_DS7_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51673   GPIO_PINCFG7_DS7_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51674   GPIO_PINCFG7_DS7_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
51675   GPIO_PINCFG7_DS7_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
51676 } GPIO_PINCFG7_DS7_Enum;
51677 
51678 /* ==============================================  GPIO PINCFG7 OUTCFG7 [8..9]  ============================================== */
51679 typedef enum {                                  /*!< GPIO_PINCFG7_OUTCFG7                                                      */
51680   GPIO_PINCFG7_OUTCFG7_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
51681   GPIO_PINCFG7_OUTCFG7_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51682                                                      and 1 values on pin.                                                      */
51683   GPIO_PINCFG7_OUTCFG7_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51684                                                      low, tristate otherwise.                                                  */
51685   GPIO_PINCFG7_OUTCFG7_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51686                                                      drive 0, 1 of HiZ on pin.                                                 */
51687 } GPIO_PINCFG7_OUTCFG7_Enum;
51688 
51689 /* ==============================================  GPIO PINCFG7 IRPTEN7 [6..7]  ============================================== */
51690 typedef enum {                                  /*!< GPIO_PINCFG7_IRPTEN7                                                      */
51691   GPIO_PINCFG7_IRPTEN7_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51692   GPIO_PINCFG7_IRPTEN7_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51693                                                      on this GPIO                                                              */
51694   GPIO_PINCFG7_IRPTEN7_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51695                                                      on this GPIO                                                              */
51696   GPIO_PINCFG7_IRPTEN7_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51697                                                      GPIO                                                                      */
51698 } GPIO_PINCFG7_IRPTEN7_Enum;
51699 
51700 /* ==============================================  GPIO PINCFG7 FNCSEL7 [0..3]  ============================================== */
51701 typedef enum {                                  /*!< GPIO_PINCFG7_FNCSEL7                                                      */
51702   GPIO_PINCFG7_FNCSEL7_M0MISO          = 0,     /*!< M0MISO : Serial SPI MASTER MISO input (IOM 0)                             */
51703   GPIO_PINCFG7_FNCSEL7_TRIG0           = 1,     /*!< TRIG0 : ADC trigger input                                                 */
51704   GPIO_PINCFG7_FNCSEL7_I2S0_WS         = 2,     /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
51705                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51706                                                      2)                                                                        */
51707   GPIO_PINCFG7_FNCSEL7_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
51708   GPIO_PINCFG7_FNCSEL7_UART2CTS        = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
51709   GPIO_PINCFG7_FNCSEL7_UART3CTS        = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
51710   GPIO_PINCFG7_FNCSEL7_CT7             = 6,     /*!< CT7 : Timer/Counter input or output; Selection of direction
51711                                                      is done via CTIMER register settings.                                     */
51712   GPIO_PINCFG7_FNCSEL7_NCE7            = 7,     /*!< NCE7 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51713                                                      CE_POLARITY field                                                         */
51714   GPIO_PINCFG7_FNCSEL7_OBSBUS7         = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
51715   GPIO_PINCFG7_FNCSEL7_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51716   GPIO_PINCFG7_FNCSEL7_I2S1_WS         = 10,    /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
51717                                                      in master mode and input mode for slave mode. (I2S Master/Slave
51718                                                      2)                                                                        */
51719   GPIO_PINCFG7_FNCSEL7_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
51720   GPIO_PINCFG7_FNCSEL7_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51721   GPIO_PINCFG7_FNCSEL7_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
51722   GPIO_PINCFG7_FNCSEL7_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51723   GPIO_PINCFG7_FNCSEL7_SCANIN7         = 15,    /*!< SCANIN7 : Internal function (SCAN)                                        */
51724 } GPIO_PINCFG7_FNCSEL7_Enum;
51725 
51726 /* ========================================================  PINCFG8  ======================================================== */
51727 /* =============================================  GPIO PINCFG8 NCEPOL8 [22..22]  ============================================= */
51728 typedef enum {                                  /*!< GPIO_PINCFG8_NCEPOL8                                                      */
51729   GPIO_PINCFG8_NCEPOL8_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
51730   GPIO_PINCFG8_NCEPOL8_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
51731 } GPIO_PINCFG8_NCEPOL8_Enum;
51732 
51733 /* =============================================  GPIO PINCFG8 NCESRC8 [16..21]  ============================================= */
51734 typedef enum {                                  /*!< GPIO_PINCFG8_NCESRC8                                                      */
51735   GPIO_PINCFG8_NCESRC8_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51736   GPIO_PINCFG8_NCESRC8_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51737   GPIO_PINCFG8_NCESRC8_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51738   GPIO_PINCFG8_NCESRC8_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51739   GPIO_PINCFG8_NCESRC8_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51740   GPIO_PINCFG8_NCESRC8_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51741   GPIO_PINCFG8_NCESRC8_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51742   GPIO_PINCFG8_NCESRC8_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51743   GPIO_PINCFG8_NCESRC8_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51744   GPIO_PINCFG8_NCESRC8_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51745   GPIO_PINCFG8_NCESRC8_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51746   GPIO_PINCFG8_NCESRC8_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51747   GPIO_PINCFG8_NCESRC8_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51748   GPIO_PINCFG8_NCESRC8_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51749   GPIO_PINCFG8_NCESRC8_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51750   GPIO_PINCFG8_NCESRC8_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51751   GPIO_PINCFG8_NCESRC8_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51752   GPIO_PINCFG8_NCESRC8_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51753   GPIO_PINCFG8_NCESRC8_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51754   GPIO_PINCFG8_NCESRC8_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51755   GPIO_PINCFG8_NCESRC8_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51756   GPIO_PINCFG8_NCESRC8_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51757   GPIO_PINCFG8_NCESRC8_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51758   GPIO_PINCFG8_NCESRC8_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51759   GPIO_PINCFG8_NCESRC8_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51760   GPIO_PINCFG8_NCESRC8_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51761   GPIO_PINCFG8_NCESRC8_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51762   GPIO_PINCFG8_NCESRC8_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51763   GPIO_PINCFG8_NCESRC8_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51764   GPIO_PINCFG8_NCESRC8_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51765   GPIO_PINCFG8_NCESRC8_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51766   GPIO_PINCFG8_NCESRC8_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51767   GPIO_PINCFG8_NCESRC8_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51768   GPIO_PINCFG8_NCESRC8_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51769   GPIO_PINCFG8_NCESRC8_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51770   GPIO_PINCFG8_NCESRC8_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51771   GPIO_PINCFG8_NCESRC8_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51772   GPIO_PINCFG8_NCESRC8_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51773   GPIO_PINCFG8_NCESRC8_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51774   GPIO_PINCFG8_NCESRC8_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51775   GPIO_PINCFG8_NCESRC8_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51776   GPIO_PINCFG8_NCESRC8_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51777   GPIO_PINCFG8_NCESRC8_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
51778 } GPIO_PINCFG8_NCESRC8_Enum;
51779 
51780 /* ============================================  GPIO PINCFG8 PULLCFG8 [13..15]  ============================================= */
51781 typedef enum {                                  /*!< GPIO_PINCFG8_PULLCFG8                                                     */
51782   GPIO_PINCFG8_PULLCFG8_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51783   GPIO_PINCFG8_PULLCFG8_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51784   GPIO_PINCFG8_PULLCFG8_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51785   GPIO_PINCFG8_PULLCFG8_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51786   GPIO_PINCFG8_PULLCFG8_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
51787   GPIO_PINCFG8_PULLCFG8_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
51788   GPIO_PINCFG8_PULLCFG8_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
51789   GPIO_PINCFG8_PULLCFG8_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
51790 } GPIO_PINCFG8_PULLCFG8_Enum;
51791 
51792 /* ===============================================  GPIO PINCFG8 DS8 [10..11]  =============================================== */
51793 typedef enum {                                  /*!< GPIO_PINCFG8_DS8                                                          */
51794   GPIO_PINCFG8_DS8_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51795   GPIO_PINCFG8_DS8_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51796   GPIO_PINCFG8_DS8_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
51797   GPIO_PINCFG8_DS8_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
51798 } GPIO_PINCFG8_DS8_Enum;
51799 
51800 /* ==============================================  GPIO PINCFG8 OUTCFG8 [8..9]  ============================================== */
51801 typedef enum {                                  /*!< GPIO_PINCFG8_OUTCFG8                                                      */
51802   GPIO_PINCFG8_OUTCFG8_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
51803   GPIO_PINCFG8_OUTCFG8_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51804                                                      and 1 values on pin.                                                      */
51805   GPIO_PINCFG8_OUTCFG8_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51806                                                      low, tristate otherwise.                                                  */
51807   GPIO_PINCFG8_OUTCFG8_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51808                                                      drive 0, 1 of HiZ on pin.                                                 */
51809 } GPIO_PINCFG8_OUTCFG8_Enum;
51810 
51811 /* ==============================================  GPIO PINCFG8 IRPTEN8 [6..7]  ============================================== */
51812 typedef enum {                                  /*!< GPIO_PINCFG8_IRPTEN8                                                      */
51813   GPIO_PINCFG8_IRPTEN8_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51814   GPIO_PINCFG8_IRPTEN8_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51815                                                      on this GPIO                                                              */
51816   GPIO_PINCFG8_IRPTEN8_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51817                                                      on this GPIO                                                              */
51818   GPIO_PINCFG8_IRPTEN8_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51819                                                      GPIO                                                                      */
51820 } GPIO_PINCFG8_IRPTEN8_Enum;
51821 
51822 /* ==============================================  GPIO PINCFG8 FNCSEL8 [0..3]  ============================================== */
51823 typedef enum {                                  /*!< GPIO_PINCFG8_FNCSEL8                                                      */
51824   GPIO_PINCFG8_FNCSEL8_CMPRF1          = 0,     /*!< CMPRF1 : Comparator reference 1                                           */
51825   GPIO_PINCFG8_FNCSEL8_TRIG1           = 1,     /*!< TRIG1 : ADC trigger input                                                 */
51826   GPIO_PINCFG8_FNCSEL8_RESERVED2       = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
51827   GPIO_PINCFG8_FNCSEL8_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
51828   GPIO_PINCFG8_FNCSEL8_M1SCL           = 4,     /*!< M1SCL : Serial I2C Master Clock output (IOM 1)                            */
51829   GPIO_PINCFG8_FNCSEL8_M1SCK           = 5,     /*!< M1SCK : Serial SPI Master Clock output (IOM 1)                            */
51830   GPIO_PINCFG8_FNCSEL8_CT8             = 6,     /*!< CT8 : Timer/Counter input or output; Selection of direction
51831                                                      is done via CTIMER register settings.                                     */
51832   GPIO_PINCFG8_FNCSEL8_NCE8            = 7,     /*!< NCE8 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51833                                                      CE_POLARITY field                                                         */
51834   GPIO_PINCFG8_FNCSEL8_OBSBUS8         = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
51835   GPIO_PINCFG8_FNCSEL8_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51836   GPIO_PINCFG8_FNCSEL8_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51837   GPIO_PINCFG8_FNCSEL8_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
51838   GPIO_PINCFG8_FNCSEL8_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51839   GPIO_PINCFG8_FNCSEL8_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
51840   GPIO_PINCFG8_FNCSEL8_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51841   GPIO_PINCFG8_FNCSEL8_SCANOUT4        = 15,    /*!< SCANOUT4 : Internal function (SCAN)                                       */
51842 } GPIO_PINCFG8_FNCSEL8_Enum;
51843 
51844 /* ========================================================  PINCFG9  ======================================================== */
51845 /* =============================================  GPIO PINCFG9 NCEPOL9 [22..22]  ============================================= */
51846 typedef enum {                                  /*!< GPIO_PINCFG9_NCEPOL9                                                      */
51847   GPIO_PINCFG9_NCEPOL9_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
51848   GPIO_PINCFG9_NCEPOL9_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
51849 } GPIO_PINCFG9_NCEPOL9_Enum;
51850 
51851 /* =============================================  GPIO PINCFG9 NCESRC9 [16..21]  ============================================= */
51852 typedef enum {                                  /*!< GPIO_PINCFG9_NCESRC9                                                      */
51853   GPIO_PINCFG9_NCESRC9_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51854   GPIO_PINCFG9_NCESRC9_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51855   GPIO_PINCFG9_NCESRC9_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51856   GPIO_PINCFG9_NCESRC9_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51857   GPIO_PINCFG9_NCESRC9_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51858   GPIO_PINCFG9_NCESRC9_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51859   GPIO_PINCFG9_NCESRC9_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51860   GPIO_PINCFG9_NCESRC9_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51861   GPIO_PINCFG9_NCESRC9_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51862   GPIO_PINCFG9_NCESRC9_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51863   GPIO_PINCFG9_NCESRC9_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51864   GPIO_PINCFG9_NCESRC9_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51865   GPIO_PINCFG9_NCESRC9_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51866   GPIO_PINCFG9_NCESRC9_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51867   GPIO_PINCFG9_NCESRC9_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51868   GPIO_PINCFG9_NCESRC9_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51869   GPIO_PINCFG9_NCESRC9_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51870   GPIO_PINCFG9_NCESRC9_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51871   GPIO_PINCFG9_NCESRC9_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51872   GPIO_PINCFG9_NCESRC9_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51873   GPIO_PINCFG9_NCESRC9_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51874   GPIO_PINCFG9_NCESRC9_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51875   GPIO_PINCFG9_NCESRC9_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51876   GPIO_PINCFG9_NCESRC9_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51877   GPIO_PINCFG9_NCESRC9_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51878   GPIO_PINCFG9_NCESRC9_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51879   GPIO_PINCFG9_NCESRC9_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51880   GPIO_PINCFG9_NCESRC9_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
51881   GPIO_PINCFG9_NCESRC9_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
51882   GPIO_PINCFG9_NCESRC9_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
51883   GPIO_PINCFG9_NCESRC9_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
51884   GPIO_PINCFG9_NCESRC9_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
51885   GPIO_PINCFG9_NCESRC9_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
51886   GPIO_PINCFG9_NCESRC9_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
51887   GPIO_PINCFG9_NCESRC9_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
51888   GPIO_PINCFG9_NCESRC9_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
51889   GPIO_PINCFG9_NCESRC9_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
51890   GPIO_PINCFG9_NCESRC9_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
51891   GPIO_PINCFG9_NCESRC9_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
51892   GPIO_PINCFG9_NCESRC9_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
51893   GPIO_PINCFG9_NCESRC9_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
51894   GPIO_PINCFG9_NCESRC9_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
51895   GPIO_PINCFG9_NCESRC9_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
51896 } GPIO_PINCFG9_NCESRC9_Enum;
51897 
51898 /* ============================================  GPIO PINCFG9 PULLCFG9 [13..15]  ============================================= */
51899 typedef enum {                                  /*!< GPIO_PINCFG9_PULLCFG9                                                     */
51900   GPIO_PINCFG9_PULLCFG9_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
51901   GPIO_PINCFG9_PULLCFG9_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
51902   GPIO_PINCFG9_PULLCFG9_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
51903   GPIO_PINCFG9_PULLCFG9_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
51904   GPIO_PINCFG9_PULLCFG9_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
51905   GPIO_PINCFG9_PULLCFG9_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
51906   GPIO_PINCFG9_PULLCFG9_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
51907   GPIO_PINCFG9_PULLCFG9_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
51908 } GPIO_PINCFG9_PULLCFG9_Enum;
51909 
51910 /* ===============================================  GPIO PINCFG9 DS9 [10..11]  =============================================== */
51911 typedef enum {                                  /*!< GPIO_PINCFG9_DS9                                                          */
51912   GPIO_PINCFG9_DS9_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
51913   GPIO_PINCFG9_DS9_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
51914   GPIO_PINCFG9_DS9_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
51915   GPIO_PINCFG9_DS9_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
51916 } GPIO_PINCFG9_DS9_Enum;
51917 
51918 /* ==============================================  GPIO PINCFG9 OUTCFG9 [8..9]  ============================================== */
51919 typedef enum {                                  /*!< GPIO_PINCFG9_OUTCFG9                                                      */
51920   GPIO_PINCFG9_OUTCFG9_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
51921   GPIO_PINCFG9_OUTCFG9_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
51922                                                      and 1 values on pin.                                                      */
51923   GPIO_PINCFG9_OUTCFG9_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
51924                                                      low, tristate otherwise.                                                  */
51925   GPIO_PINCFG9_OUTCFG9_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
51926                                                      drive 0, 1 of HiZ on pin.                                                 */
51927 } GPIO_PINCFG9_OUTCFG9_Enum;
51928 
51929 /* ==============================================  GPIO PINCFG9 IRPTEN9 [6..7]  ============================================== */
51930 typedef enum {                                  /*!< GPIO_PINCFG9_IRPTEN9                                                      */
51931   GPIO_PINCFG9_IRPTEN9_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
51932   GPIO_PINCFG9_IRPTEN9_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
51933                                                      on this GPIO                                                              */
51934   GPIO_PINCFG9_IRPTEN9_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
51935                                                      on this GPIO                                                              */
51936   GPIO_PINCFG9_IRPTEN9_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
51937                                                      GPIO                                                                      */
51938 } GPIO_PINCFG9_IRPTEN9_Enum;
51939 
51940 /* ==============================================  GPIO PINCFG9 FNCSEL9 [0..3]  ============================================== */
51941 typedef enum {                                  /*!< GPIO_PINCFG9_FNCSEL9                                                      */
51942   GPIO_PINCFG9_FNCSEL9_CMPRF0          = 0,     /*!< CMPRF0 : Comparator reference 0                                           */
51943   GPIO_PINCFG9_FNCSEL9_TRIG2           = 1,     /*!< TRIG2 : ADC trigger input                                                 */
51944   GPIO_PINCFG9_FNCSEL9_RESERVED2       = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
51945   GPIO_PINCFG9_FNCSEL9_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
51946   GPIO_PINCFG9_FNCSEL9_M1SDAWIR3       = 4,     /*!< M1SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
51947                                                      Master Data I/O (SPI 3 wire mode) (IOM 1)                                 */
51948   GPIO_PINCFG9_FNCSEL9_M1MOSI          = 5,     /*!< M1MOSI : Serial SPI Master MOSI output (IOM 1)                            */
51949   GPIO_PINCFG9_FNCSEL9_CT9             = 6,     /*!< CT9 : Timer/Counter input or output; Selection of direction
51950                                                      is done via CTIMER register settings.                                     */
51951   GPIO_PINCFG9_FNCSEL9_NCE9            = 7,     /*!< NCE9 : IOMSTR/MSPI N Chip Select. Polarity is determined by
51952                                                      CE_POLARITY field                                                         */
51953   GPIO_PINCFG9_FNCSEL9_OBSBUS9         = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
51954   GPIO_PINCFG9_FNCSEL9_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
51955   GPIO_PINCFG9_FNCSEL9_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
51956   GPIO_PINCFG9_FNCSEL9_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
51957   GPIO_PINCFG9_FNCSEL9_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
51958   GPIO_PINCFG9_FNCSEL9_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
51959   GPIO_PINCFG9_FNCSEL9_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
51960   GPIO_PINCFG9_FNCSEL9_SCANOUT5        = 15,    /*!< SCANOUT5 : Internal function (SCAN)                                       */
51961 } GPIO_PINCFG9_FNCSEL9_Enum;
51962 
51963 /* =======================================================  PINCFG10  ======================================================== */
51964 /* ============================================  GPIO PINCFG10 NCEPOL10 [22..22]  ============================================ */
51965 typedef enum {                                  /*!< GPIO_PINCFG10_NCEPOL10                                                    */
51966   GPIO_PINCFG10_NCEPOL10_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
51967   GPIO_PINCFG10_NCEPOL10_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
51968 } GPIO_PINCFG10_NCEPOL10_Enum;
51969 
51970 /* ============================================  GPIO PINCFG10 NCESRC10 [16..21]  ============================================ */
51971 typedef enum {                                  /*!< GPIO_PINCFG10_NCESRC10                                                    */
51972   GPIO_PINCFG10_NCESRC10_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
51973   GPIO_PINCFG10_NCESRC10_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
51974   GPIO_PINCFG10_NCESRC10_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
51975   GPIO_PINCFG10_NCESRC10_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
51976   GPIO_PINCFG10_NCESRC10_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
51977   GPIO_PINCFG10_NCESRC10_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
51978   GPIO_PINCFG10_NCESRC10_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
51979   GPIO_PINCFG10_NCESRC10_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
51980   GPIO_PINCFG10_NCESRC10_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
51981   GPIO_PINCFG10_NCESRC10_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
51982   GPIO_PINCFG10_NCESRC10_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
51983   GPIO_PINCFG10_NCESRC10_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
51984   GPIO_PINCFG10_NCESRC10_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
51985   GPIO_PINCFG10_NCESRC10_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
51986   GPIO_PINCFG10_NCESRC10_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
51987   GPIO_PINCFG10_NCESRC10_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
51988   GPIO_PINCFG10_NCESRC10_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
51989   GPIO_PINCFG10_NCESRC10_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
51990   GPIO_PINCFG10_NCESRC10_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
51991   GPIO_PINCFG10_NCESRC10_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
51992   GPIO_PINCFG10_NCESRC10_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
51993   GPIO_PINCFG10_NCESRC10_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
51994   GPIO_PINCFG10_NCESRC10_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
51995   GPIO_PINCFG10_NCESRC10_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
51996   GPIO_PINCFG10_NCESRC10_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
51997   GPIO_PINCFG10_NCESRC10_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
51998   GPIO_PINCFG10_NCESRC10_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
51999   GPIO_PINCFG10_NCESRC10_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52000   GPIO_PINCFG10_NCESRC10_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52001   GPIO_PINCFG10_NCESRC10_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52002   GPIO_PINCFG10_NCESRC10_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52003   GPIO_PINCFG10_NCESRC10_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52004   GPIO_PINCFG10_NCESRC10_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52005   GPIO_PINCFG10_NCESRC10_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52006   GPIO_PINCFG10_NCESRC10_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52007   GPIO_PINCFG10_NCESRC10_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52008   GPIO_PINCFG10_NCESRC10_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52009   GPIO_PINCFG10_NCESRC10_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52010   GPIO_PINCFG10_NCESRC10_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52011   GPIO_PINCFG10_NCESRC10_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52012   GPIO_PINCFG10_NCESRC10_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52013   GPIO_PINCFG10_NCESRC10_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52014   GPIO_PINCFG10_NCESRC10_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52015 } GPIO_PINCFG10_NCESRC10_Enum;
52016 
52017 /* ===========================================  GPIO PINCFG10 PULLCFG10 [13..15]  ============================================ */
52018 typedef enum {                                  /*!< GPIO_PINCFG10_PULLCFG10                                                   */
52019   GPIO_PINCFG10_PULLCFG10_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52020   GPIO_PINCFG10_PULLCFG10_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52021   GPIO_PINCFG10_PULLCFG10_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52022   GPIO_PINCFG10_PULLCFG10_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52023   GPIO_PINCFG10_PULLCFG10_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52024   GPIO_PINCFG10_PULLCFG10_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52025   GPIO_PINCFG10_PULLCFG10_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52026   GPIO_PINCFG10_PULLCFG10_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52027 } GPIO_PINCFG10_PULLCFG10_Enum;
52028 
52029 /* ==============================================  GPIO PINCFG10 DS10 [10..11]  ============================================== */
52030 typedef enum {                                  /*!< GPIO_PINCFG10_DS10                                                        */
52031   GPIO_PINCFG10_DS10_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52032   GPIO_PINCFG10_DS10_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52033   GPIO_PINCFG10_DS10_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
52034   GPIO_PINCFG10_DS10_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
52035 } GPIO_PINCFG10_DS10_Enum;
52036 
52037 /* =============================================  GPIO PINCFG10 OUTCFG10 [8..9]  ============================================= */
52038 typedef enum {                                  /*!< GPIO_PINCFG10_OUTCFG10                                                    */
52039   GPIO_PINCFG10_OUTCFG10_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52040   GPIO_PINCFG10_OUTCFG10_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52041                                                      and 1 values on pin.                                                      */
52042   GPIO_PINCFG10_OUTCFG10_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52043                                                      low, tristate otherwise.                                                  */
52044   GPIO_PINCFG10_OUTCFG10_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52045                                                      drive 0, 1 of HiZ on pin.                                                 */
52046 } GPIO_PINCFG10_OUTCFG10_Enum;
52047 
52048 /* =============================================  GPIO PINCFG10 IRPTEN10 [6..7]  ============================================= */
52049 typedef enum {                                  /*!< GPIO_PINCFG10_IRPTEN10                                                    */
52050   GPIO_PINCFG10_IRPTEN10_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52051   GPIO_PINCFG10_IRPTEN10_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52052                                                      on this GPIO                                                              */
52053   GPIO_PINCFG10_IRPTEN10_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52054                                                      on this GPIO                                                              */
52055   GPIO_PINCFG10_IRPTEN10_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52056                                                      GPIO                                                                      */
52057 } GPIO_PINCFG10_IRPTEN10_Enum;
52058 
52059 /* =============================================  GPIO PINCFG10 FNCSEL10 [0..3]  ============================================= */
52060 typedef enum {                                  /*!< GPIO_PINCFG10_FNCSEL10                                                    */
52061   GPIO_PINCFG10_FNCSEL10_CMPIN0        = 0,     /*!< CMPIN0 : Voltage comparator input 0                                       */
52062   GPIO_PINCFG10_FNCSEL10_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
52063   GPIO_PINCFG10_FNCSEL10_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
52064   GPIO_PINCFG10_FNCSEL10_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52065   GPIO_PINCFG10_FNCSEL10_M1MISO        = 4,     /*!< M1MISO : Serial SPI MASTER MISO input (IOM 1)                             */
52066   GPIO_PINCFG10_FNCSEL10_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
52067   GPIO_PINCFG10_FNCSEL10_CT10          = 6,     /*!< CT10 : Timer/Counter input or output; Selection of direction
52068                                                      is done via CTIMER register settings.                                     */
52069   GPIO_PINCFG10_FNCSEL10_NCE10         = 7,     /*!< NCE10 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52070                                                      CE_POLARITY field                                                         */
52071   GPIO_PINCFG10_FNCSEL10_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
52072   GPIO_PINCFG10_FNCSEL10_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
52073   GPIO_PINCFG10_FNCSEL10_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52074   GPIO_PINCFG10_FNCSEL10_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52075   GPIO_PINCFG10_FNCSEL10_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52076   GPIO_PINCFG10_FNCSEL10_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52077   GPIO_PINCFG10_FNCSEL10_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52078   GPIO_PINCFG10_FNCSEL10_OPCG_LOAD     = 15,    /*!< OPCG_LOAD : Internal function (SCAN)                                      */
52079 } GPIO_PINCFG10_FNCSEL10_Enum;
52080 
52081 /* =======================================================  PINCFG11  ======================================================== */
52082 /* ============================================  GPIO PINCFG11 NCEPOL11 [22..22]  ============================================ */
52083 typedef enum {                                  /*!< GPIO_PINCFG11_NCEPOL11                                                    */
52084   GPIO_PINCFG11_NCEPOL11_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52085   GPIO_PINCFG11_NCEPOL11_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52086 } GPIO_PINCFG11_NCEPOL11_Enum;
52087 
52088 /* ============================================  GPIO PINCFG11 NCESRC11 [16..21]  ============================================ */
52089 typedef enum {                                  /*!< GPIO_PINCFG11_NCESRC11                                                    */
52090   GPIO_PINCFG11_NCESRC11_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52091   GPIO_PINCFG11_NCESRC11_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52092   GPIO_PINCFG11_NCESRC11_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52093   GPIO_PINCFG11_NCESRC11_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52094   GPIO_PINCFG11_NCESRC11_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52095   GPIO_PINCFG11_NCESRC11_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52096   GPIO_PINCFG11_NCESRC11_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52097   GPIO_PINCFG11_NCESRC11_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52098   GPIO_PINCFG11_NCESRC11_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52099   GPIO_PINCFG11_NCESRC11_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52100   GPIO_PINCFG11_NCESRC11_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52101   GPIO_PINCFG11_NCESRC11_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52102   GPIO_PINCFG11_NCESRC11_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52103   GPIO_PINCFG11_NCESRC11_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52104   GPIO_PINCFG11_NCESRC11_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52105   GPIO_PINCFG11_NCESRC11_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52106   GPIO_PINCFG11_NCESRC11_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52107   GPIO_PINCFG11_NCESRC11_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52108   GPIO_PINCFG11_NCESRC11_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52109   GPIO_PINCFG11_NCESRC11_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52110   GPIO_PINCFG11_NCESRC11_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52111   GPIO_PINCFG11_NCESRC11_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52112   GPIO_PINCFG11_NCESRC11_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52113   GPIO_PINCFG11_NCESRC11_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52114   GPIO_PINCFG11_NCESRC11_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52115   GPIO_PINCFG11_NCESRC11_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52116   GPIO_PINCFG11_NCESRC11_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52117   GPIO_PINCFG11_NCESRC11_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52118   GPIO_PINCFG11_NCESRC11_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52119   GPIO_PINCFG11_NCESRC11_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52120   GPIO_PINCFG11_NCESRC11_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52121   GPIO_PINCFG11_NCESRC11_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52122   GPIO_PINCFG11_NCESRC11_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52123   GPIO_PINCFG11_NCESRC11_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52124   GPIO_PINCFG11_NCESRC11_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52125   GPIO_PINCFG11_NCESRC11_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52126   GPIO_PINCFG11_NCESRC11_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52127   GPIO_PINCFG11_NCESRC11_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52128   GPIO_PINCFG11_NCESRC11_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52129   GPIO_PINCFG11_NCESRC11_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52130   GPIO_PINCFG11_NCESRC11_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52131   GPIO_PINCFG11_NCESRC11_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52132   GPIO_PINCFG11_NCESRC11_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52133 } GPIO_PINCFG11_NCESRC11_Enum;
52134 
52135 /* ===========================================  GPIO PINCFG11 PULLCFG11 [13..15]  ============================================ */
52136 typedef enum {                                  /*!< GPIO_PINCFG11_PULLCFG11                                                   */
52137   GPIO_PINCFG11_PULLCFG11_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52138   GPIO_PINCFG11_PULLCFG11_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52139   GPIO_PINCFG11_PULLCFG11_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52140   GPIO_PINCFG11_PULLCFG11_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52141   GPIO_PINCFG11_PULLCFG11_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52142   GPIO_PINCFG11_PULLCFG11_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52143   GPIO_PINCFG11_PULLCFG11_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52144   GPIO_PINCFG11_PULLCFG11_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52145 } GPIO_PINCFG11_PULLCFG11_Enum;
52146 
52147 /* ==============================================  GPIO PINCFG11 DS11 [10..11]  ============================================== */
52148 typedef enum {                                  /*!< GPIO_PINCFG11_DS11                                                        */
52149   GPIO_PINCFG11_DS11_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52150   GPIO_PINCFG11_DS11_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52151 } GPIO_PINCFG11_DS11_Enum;
52152 
52153 /* =============================================  GPIO PINCFG11 OUTCFG11 [8..9]  ============================================= */
52154 typedef enum {                                  /*!< GPIO_PINCFG11_OUTCFG11                                                    */
52155   GPIO_PINCFG11_OUTCFG11_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52156   GPIO_PINCFG11_OUTCFG11_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52157                                                      and 1 values on pin.                                                      */
52158   GPIO_PINCFG11_OUTCFG11_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52159                                                      low, tristate otherwise.                                                  */
52160   GPIO_PINCFG11_OUTCFG11_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52161                                                      drive 0, 1 of HiZ on pin.                                                 */
52162 } GPIO_PINCFG11_OUTCFG11_Enum;
52163 
52164 /* =============================================  GPIO PINCFG11 IRPTEN11 [6..7]  ============================================= */
52165 typedef enum {                                  /*!< GPIO_PINCFG11_IRPTEN11                                                    */
52166   GPIO_PINCFG11_IRPTEN11_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52167   GPIO_PINCFG11_IRPTEN11_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52168                                                      on this GPIO                                                              */
52169   GPIO_PINCFG11_IRPTEN11_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52170                                                      on this GPIO                                                              */
52171   GPIO_PINCFG11_IRPTEN11_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52172                                                      GPIO                                                                      */
52173 } GPIO_PINCFG11_IRPTEN11_Enum;
52174 
52175 /* =============================================  GPIO PINCFG11 FNCSEL11 [0..3]  ============================================= */
52176 typedef enum {                                  /*!< GPIO_PINCFG11_FNCSEL11                                                    */
52177   GPIO_PINCFG11_FNCSEL11_CMPIN1        = 0,     /*!< CMPIN1 : Voltage comparator input 1                                       */
52178   GPIO_PINCFG11_FNCSEL11_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
52179   GPIO_PINCFG11_FNCSEL11_I2S0_CLK      = 2,     /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
52180                                                      in master mode and input mode for slave mode. (I2S Master/Slave
52181                                                      2)                                                                        */
52182   GPIO_PINCFG11_FNCSEL11_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52183   GPIO_PINCFG11_FNCSEL11_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
52184   GPIO_PINCFG11_FNCSEL11_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
52185   GPIO_PINCFG11_FNCSEL11_CT11          = 6,     /*!< CT11 : Timer/Counter input or output; Selection of direction
52186                                                      is done via CTIMER register settings.                                     */
52187   GPIO_PINCFG11_FNCSEL11_NCE11         = 7,     /*!< NCE11 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52188                                                      CE_POLARITY field                                                         */
52189   GPIO_PINCFG11_FNCSEL11_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
52190   GPIO_PINCFG11_FNCSEL11_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
52191   GPIO_PINCFG11_FNCSEL11_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52192   GPIO_PINCFG11_FNCSEL11_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52193   GPIO_PINCFG11_FNCSEL11_FLB_TCLK      = 12,    /*!< FLB_TCLK : Internal function (Flash Bist)                                 */
52194   GPIO_PINCFG11_FNCSEL11_FLLOAD_ADDR   = 13,    /*!< FLLOAD_ADDR : Internal function (Flash parallel load)                     */
52195   GPIO_PINCFG11_FNCSEL11_MDA_TCK       = 14,    /*!< MDA_TCK : Internal function (MBIST)                                       */
52196   GPIO_PINCFG11_FNCSEL11_SCANIN0       = 15,    /*!< SCANIN0 : Internal function (SCAN)                                        */
52197 } GPIO_PINCFG11_FNCSEL11_Enum;
52198 
52199 /* =======================================================  PINCFG12  ======================================================== */
52200 /* ============================================  GPIO PINCFG12 NCEPOL12 [22..22]  ============================================ */
52201 typedef enum {                                  /*!< GPIO_PINCFG12_NCEPOL12                                                    */
52202   GPIO_PINCFG12_NCEPOL12_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52203   GPIO_PINCFG12_NCEPOL12_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52204 } GPIO_PINCFG12_NCEPOL12_Enum;
52205 
52206 /* ============================================  GPIO PINCFG12 NCESRC12 [16..21]  ============================================ */
52207 typedef enum {                                  /*!< GPIO_PINCFG12_NCESRC12                                                    */
52208   GPIO_PINCFG12_NCESRC12_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52209   GPIO_PINCFG12_NCESRC12_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52210   GPIO_PINCFG12_NCESRC12_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52211   GPIO_PINCFG12_NCESRC12_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52212   GPIO_PINCFG12_NCESRC12_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52213   GPIO_PINCFG12_NCESRC12_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52214   GPIO_PINCFG12_NCESRC12_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52215   GPIO_PINCFG12_NCESRC12_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52216   GPIO_PINCFG12_NCESRC12_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52217   GPIO_PINCFG12_NCESRC12_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52218   GPIO_PINCFG12_NCESRC12_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52219   GPIO_PINCFG12_NCESRC12_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52220   GPIO_PINCFG12_NCESRC12_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52221   GPIO_PINCFG12_NCESRC12_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52222   GPIO_PINCFG12_NCESRC12_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52223   GPIO_PINCFG12_NCESRC12_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52224   GPIO_PINCFG12_NCESRC12_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52225   GPIO_PINCFG12_NCESRC12_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52226   GPIO_PINCFG12_NCESRC12_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52227   GPIO_PINCFG12_NCESRC12_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52228   GPIO_PINCFG12_NCESRC12_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52229   GPIO_PINCFG12_NCESRC12_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52230   GPIO_PINCFG12_NCESRC12_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52231   GPIO_PINCFG12_NCESRC12_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52232   GPIO_PINCFG12_NCESRC12_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52233   GPIO_PINCFG12_NCESRC12_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52234   GPIO_PINCFG12_NCESRC12_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52235   GPIO_PINCFG12_NCESRC12_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52236   GPIO_PINCFG12_NCESRC12_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52237   GPIO_PINCFG12_NCESRC12_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52238   GPIO_PINCFG12_NCESRC12_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52239   GPIO_PINCFG12_NCESRC12_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52240   GPIO_PINCFG12_NCESRC12_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52241   GPIO_PINCFG12_NCESRC12_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52242   GPIO_PINCFG12_NCESRC12_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52243   GPIO_PINCFG12_NCESRC12_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52244   GPIO_PINCFG12_NCESRC12_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52245   GPIO_PINCFG12_NCESRC12_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52246   GPIO_PINCFG12_NCESRC12_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52247   GPIO_PINCFG12_NCESRC12_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52248   GPIO_PINCFG12_NCESRC12_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52249   GPIO_PINCFG12_NCESRC12_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52250   GPIO_PINCFG12_NCESRC12_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52251 } GPIO_PINCFG12_NCESRC12_Enum;
52252 
52253 /* ===========================================  GPIO PINCFG12 PULLCFG12 [13..15]  ============================================ */
52254 typedef enum {                                  /*!< GPIO_PINCFG12_PULLCFG12                                                   */
52255   GPIO_PINCFG12_PULLCFG12_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52256   GPIO_PINCFG12_PULLCFG12_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52257   GPIO_PINCFG12_PULLCFG12_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52258   GPIO_PINCFG12_PULLCFG12_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52259   GPIO_PINCFG12_PULLCFG12_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52260   GPIO_PINCFG12_PULLCFG12_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52261   GPIO_PINCFG12_PULLCFG12_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52262   GPIO_PINCFG12_PULLCFG12_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52263 } GPIO_PINCFG12_PULLCFG12_Enum;
52264 
52265 /* ==============================================  GPIO PINCFG12 DS12 [10..11]  ============================================== */
52266 typedef enum {                                  /*!< GPIO_PINCFG12_DS12                                                        */
52267   GPIO_PINCFG12_DS12_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52268   GPIO_PINCFG12_DS12_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52269 } GPIO_PINCFG12_DS12_Enum;
52270 
52271 /* =============================================  GPIO PINCFG12 OUTCFG12 [8..9]  ============================================= */
52272 typedef enum {                                  /*!< GPIO_PINCFG12_OUTCFG12                                                    */
52273   GPIO_PINCFG12_OUTCFG12_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52274   GPIO_PINCFG12_OUTCFG12_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52275                                                      and 1 values on pin.                                                      */
52276   GPIO_PINCFG12_OUTCFG12_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52277                                                      low, tristate otherwise.                                                  */
52278   GPIO_PINCFG12_OUTCFG12_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52279                                                      drive 0, 1 of HiZ on pin.                                                 */
52280 } GPIO_PINCFG12_OUTCFG12_Enum;
52281 
52282 /* =============================================  GPIO PINCFG12 IRPTEN12 [6..7]  ============================================= */
52283 typedef enum {                                  /*!< GPIO_PINCFG12_IRPTEN12                                                    */
52284   GPIO_PINCFG12_IRPTEN12_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52285   GPIO_PINCFG12_IRPTEN12_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52286                                                      on this GPIO                                                              */
52287   GPIO_PINCFG12_IRPTEN12_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52288                                                      on this GPIO                                                              */
52289   GPIO_PINCFG12_IRPTEN12_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52290                                                      GPIO                                                                      */
52291 } GPIO_PINCFG12_IRPTEN12_Enum;
52292 
52293 /* =============================================  GPIO PINCFG12 FNCSEL12 [0..3]  ============================================= */
52294 typedef enum {                                  /*!< GPIO_PINCFG12_FNCSEL12                                                    */
52295   GPIO_PINCFG12_FNCSEL12_ADCSE7        = 0,     /*!< ADCSE7 : Analog to Digital Converter SE IN7                               */
52296   GPIO_PINCFG12_FNCSEL12_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
52297   GPIO_PINCFG12_FNCSEL12_I2S0_DATA     = 2,     /*!< I2S0_DATA : Bidirectional I2S Data. Operates in output mode
52298                                                      in master mode and input mode for slave mode. (I2S Master/Slave
52299                                                      2)                                                                        */
52300   GPIO_PINCFG12_FNCSEL12_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52301   GPIO_PINCFG12_FNCSEL12_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
52302   GPIO_PINCFG12_FNCSEL12_UART1TX       = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
52303   GPIO_PINCFG12_FNCSEL12_CT12          = 6,     /*!< CT12 : Timer/Counter input or output; Selection of direction
52304                                                      is done via CTIMER register settings.                                     */
52305   GPIO_PINCFG12_FNCSEL12_NCE12         = 7,     /*!< NCE12 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52306                                                      CE_POLARITY field                                                         */
52307   GPIO_PINCFG12_FNCSEL12_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
52308   GPIO_PINCFG12_FNCSEL12_CMPRF2        = 9,     /*!< CMPRF2 : Comparator reference 2                                           */
52309   GPIO_PINCFG12_FNCSEL12_I2S0_SDOUT    = 10,    /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
52310   GPIO_PINCFG12_FNCSEL12_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52311   GPIO_PINCFG12_FNCSEL12_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52312   GPIO_PINCFG12_FNCSEL12_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52313   GPIO_PINCFG12_FNCSEL12_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52314   GPIO_PINCFG12_FNCSEL12_SCANOUT3      = 15,    /*!< SCANOUT3 : Internal function (SCAN)                                       */
52315 } GPIO_PINCFG12_FNCSEL12_Enum;
52316 
52317 /* =======================================================  PINCFG13  ======================================================== */
52318 /* ============================================  GPIO PINCFG13 NCEPOL13 [22..22]  ============================================ */
52319 typedef enum {                                  /*!< GPIO_PINCFG13_NCEPOL13                                                    */
52320   GPIO_PINCFG13_NCEPOL13_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52321   GPIO_PINCFG13_NCEPOL13_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52322 } GPIO_PINCFG13_NCEPOL13_Enum;
52323 
52324 /* ============================================  GPIO PINCFG13 NCESRC13 [16..21]  ============================================ */
52325 typedef enum {                                  /*!< GPIO_PINCFG13_NCESRC13                                                    */
52326   GPIO_PINCFG13_NCESRC13_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52327   GPIO_PINCFG13_NCESRC13_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52328   GPIO_PINCFG13_NCESRC13_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52329   GPIO_PINCFG13_NCESRC13_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52330   GPIO_PINCFG13_NCESRC13_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52331   GPIO_PINCFG13_NCESRC13_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52332   GPIO_PINCFG13_NCESRC13_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52333   GPIO_PINCFG13_NCESRC13_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52334   GPIO_PINCFG13_NCESRC13_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52335   GPIO_PINCFG13_NCESRC13_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52336   GPIO_PINCFG13_NCESRC13_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52337   GPIO_PINCFG13_NCESRC13_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52338   GPIO_PINCFG13_NCESRC13_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52339   GPIO_PINCFG13_NCESRC13_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52340   GPIO_PINCFG13_NCESRC13_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52341   GPIO_PINCFG13_NCESRC13_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52342   GPIO_PINCFG13_NCESRC13_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52343   GPIO_PINCFG13_NCESRC13_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52344   GPIO_PINCFG13_NCESRC13_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52345   GPIO_PINCFG13_NCESRC13_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52346   GPIO_PINCFG13_NCESRC13_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52347   GPIO_PINCFG13_NCESRC13_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52348   GPIO_PINCFG13_NCESRC13_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52349   GPIO_PINCFG13_NCESRC13_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52350   GPIO_PINCFG13_NCESRC13_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52351   GPIO_PINCFG13_NCESRC13_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52352   GPIO_PINCFG13_NCESRC13_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52353   GPIO_PINCFG13_NCESRC13_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52354   GPIO_PINCFG13_NCESRC13_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52355   GPIO_PINCFG13_NCESRC13_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52356   GPIO_PINCFG13_NCESRC13_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52357   GPIO_PINCFG13_NCESRC13_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52358   GPIO_PINCFG13_NCESRC13_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52359   GPIO_PINCFG13_NCESRC13_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52360   GPIO_PINCFG13_NCESRC13_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52361   GPIO_PINCFG13_NCESRC13_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52362   GPIO_PINCFG13_NCESRC13_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52363   GPIO_PINCFG13_NCESRC13_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52364   GPIO_PINCFG13_NCESRC13_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52365   GPIO_PINCFG13_NCESRC13_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52366   GPIO_PINCFG13_NCESRC13_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52367   GPIO_PINCFG13_NCESRC13_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52368   GPIO_PINCFG13_NCESRC13_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52369 } GPIO_PINCFG13_NCESRC13_Enum;
52370 
52371 /* ===========================================  GPIO PINCFG13 PULLCFG13 [13..15]  ============================================ */
52372 typedef enum {                                  /*!< GPIO_PINCFG13_PULLCFG13                                                   */
52373   GPIO_PINCFG13_PULLCFG13_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52374   GPIO_PINCFG13_PULLCFG13_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52375   GPIO_PINCFG13_PULLCFG13_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52376   GPIO_PINCFG13_PULLCFG13_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52377   GPIO_PINCFG13_PULLCFG13_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52378   GPIO_PINCFG13_PULLCFG13_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52379   GPIO_PINCFG13_PULLCFG13_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52380   GPIO_PINCFG13_PULLCFG13_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52381 } GPIO_PINCFG13_PULLCFG13_Enum;
52382 
52383 /* ==============================================  GPIO PINCFG13 DS13 [10..11]  ============================================== */
52384 typedef enum {                                  /*!< GPIO_PINCFG13_DS13                                                        */
52385   GPIO_PINCFG13_DS13_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52386   GPIO_PINCFG13_DS13_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52387 } GPIO_PINCFG13_DS13_Enum;
52388 
52389 /* =============================================  GPIO PINCFG13 OUTCFG13 [8..9]  ============================================= */
52390 typedef enum {                                  /*!< GPIO_PINCFG13_OUTCFG13                                                    */
52391   GPIO_PINCFG13_OUTCFG13_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52392   GPIO_PINCFG13_OUTCFG13_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52393                                                      and 1 values on pin.                                                      */
52394   GPIO_PINCFG13_OUTCFG13_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52395                                                      low, tristate otherwise.                                                  */
52396   GPIO_PINCFG13_OUTCFG13_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52397                                                      drive 0, 1 of HiZ on pin.                                                 */
52398 } GPIO_PINCFG13_OUTCFG13_Enum;
52399 
52400 /* =============================================  GPIO PINCFG13 IRPTEN13 [6..7]  ============================================= */
52401 typedef enum {                                  /*!< GPIO_PINCFG13_IRPTEN13                                                    */
52402   GPIO_PINCFG13_IRPTEN13_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52403   GPIO_PINCFG13_IRPTEN13_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52404                                                      on this GPIO                                                              */
52405   GPIO_PINCFG13_IRPTEN13_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52406                                                      on this GPIO                                                              */
52407   GPIO_PINCFG13_IRPTEN13_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52408                                                      GPIO                                                                      */
52409 } GPIO_PINCFG13_IRPTEN13_Enum;
52410 
52411 /* =============================================  GPIO PINCFG13 FNCSEL13 [0..3]  ============================================= */
52412 typedef enum {                                  /*!< GPIO_PINCFG13_FNCSEL13                                                    */
52413   GPIO_PINCFG13_FNCSEL13_ADCSE6        = 0,     /*!< ADCSE6 : Analog to Digital Converter SE IN6                               */
52414   GPIO_PINCFG13_FNCSEL13_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
52415   GPIO_PINCFG13_FNCSEL13_I2S0_WS       = 2,     /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
52416                                                      in master mode and input mode for slave mode. (I2S Master/Slave
52417                                                      2)                                                                        */
52418   GPIO_PINCFG13_FNCSEL13_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52419   GPIO_PINCFG13_FNCSEL13_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
52420   GPIO_PINCFG13_FNCSEL13_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
52421   GPIO_PINCFG13_FNCSEL13_CT13          = 6,     /*!< CT13 : Timer/Counter input or output; Selection of direction
52422                                                      is done via CTIMER register settings.                                     */
52423   GPIO_PINCFG13_FNCSEL13_NCE13         = 7,     /*!< NCE13 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52424                                                      CE_POLARITY field                                                         */
52425   GPIO_PINCFG13_FNCSEL13_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
52426   GPIO_PINCFG13_FNCSEL13_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
52427   GPIO_PINCFG13_FNCSEL13_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52428   GPIO_PINCFG13_FNCSEL13_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52429   GPIO_PINCFG13_FNCSEL13_FLB_FCLK      = 12,    /*!< FLB_FCLK : Internal function (Flash Bist)                                 */
52430   GPIO_PINCFG13_FNCSEL13_FLLOAD_DATA   = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
52431   GPIO_PINCFG13_FNCSEL13_MDA_TDI       = 14,    /*!< MDA_TDI : Internal function (MBIST)                                       */
52432   GPIO_PINCFG13_FNCSEL13_SCANOUT0      = 15,    /*!< SCANOUT0 : Internal function (SCAN)                                       */
52433 } GPIO_PINCFG13_FNCSEL13_Enum;
52434 
52435 /* =======================================================  PINCFG14  ======================================================== */
52436 /* ============================================  GPIO PINCFG14 NCEPOL14 [22..22]  ============================================ */
52437 typedef enum {                                  /*!< GPIO_PINCFG14_NCEPOL14                                                    */
52438   GPIO_PINCFG14_NCEPOL14_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52439   GPIO_PINCFG14_NCEPOL14_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52440 } GPIO_PINCFG14_NCEPOL14_Enum;
52441 
52442 /* ============================================  GPIO PINCFG14 NCESRC14 [16..21]  ============================================ */
52443 typedef enum {                                  /*!< GPIO_PINCFG14_NCESRC14                                                    */
52444   GPIO_PINCFG14_NCESRC14_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52445   GPIO_PINCFG14_NCESRC14_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52446   GPIO_PINCFG14_NCESRC14_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52447   GPIO_PINCFG14_NCESRC14_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52448   GPIO_PINCFG14_NCESRC14_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52449   GPIO_PINCFG14_NCESRC14_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52450   GPIO_PINCFG14_NCESRC14_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52451   GPIO_PINCFG14_NCESRC14_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52452   GPIO_PINCFG14_NCESRC14_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52453   GPIO_PINCFG14_NCESRC14_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52454   GPIO_PINCFG14_NCESRC14_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52455   GPIO_PINCFG14_NCESRC14_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52456   GPIO_PINCFG14_NCESRC14_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52457   GPIO_PINCFG14_NCESRC14_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52458   GPIO_PINCFG14_NCESRC14_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52459   GPIO_PINCFG14_NCESRC14_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52460   GPIO_PINCFG14_NCESRC14_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52461   GPIO_PINCFG14_NCESRC14_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52462   GPIO_PINCFG14_NCESRC14_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52463   GPIO_PINCFG14_NCESRC14_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52464   GPIO_PINCFG14_NCESRC14_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52465   GPIO_PINCFG14_NCESRC14_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52466   GPIO_PINCFG14_NCESRC14_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52467   GPIO_PINCFG14_NCESRC14_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52468   GPIO_PINCFG14_NCESRC14_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52469   GPIO_PINCFG14_NCESRC14_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52470   GPIO_PINCFG14_NCESRC14_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52471   GPIO_PINCFG14_NCESRC14_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52472   GPIO_PINCFG14_NCESRC14_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52473   GPIO_PINCFG14_NCESRC14_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52474   GPIO_PINCFG14_NCESRC14_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52475   GPIO_PINCFG14_NCESRC14_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52476   GPIO_PINCFG14_NCESRC14_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52477   GPIO_PINCFG14_NCESRC14_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52478   GPIO_PINCFG14_NCESRC14_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52479   GPIO_PINCFG14_NCESRC14_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52480   GPIO_PINCFG14_NCESRC14_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52481   GPIO_PINCFG14_NCESRC14_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52482   GPIO_PINCFG14_NCESRC14_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52483   GPIO_PINCFG14_NCESRC14_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52484   GPIO_PINCFG14_NCESRC14_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52485   GPIO_PINCFG14_NCESRC14_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52486   GPIO_PINCFG14_NCESRC14_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52487 } GPIO_PINCFG14_NCESRC14_Enum;
52488 
52489 /* ===========================================  GPIO PINCFG14 PULLCFG14 [13..15]  ============================================ */
52490 typedef enum {                                  /*!< GPIO_PINCFG14_PULLCFG14                                                   */
52491   GPIO_PINCFG14_PULLCFG14_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52492   GPIO_PINCFG14_PULLCFG14_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52493   GPIO_PINCFG14_PULLCFG14_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52494   GPIO_PINCFG14_PULLCFG14_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52495   GPIO_PINCFG14_PULLCFG14_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52496   GPIO_PINCFG14_PULLCFG14_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52497   GPIO_PINCFG14_PULLCFG14_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52498   GPIO_PINCFG14_PULLCFG14_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52499 } GPIO_PINCFG14_PULLCFG14_Enum;
52500 
52501 /* ==============================================  GPIO PINCFG14 DS14 [10..11]  ============================================== */
52502 typedef enum {                                  /*!< GPIO_PINCFG14_DS14                                                        */
52503   GPIO_PINCFG14_DS14_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52504   GPIO_PINCFG14_DS14_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52505 } GPIO_PINCFG14_DS14_Enum;
52506 
52507 /* =============================================  GPIO PINCFG14 OUTCFG14 [8..9]  ============================================= */
52508 typedef enum {                                  /*!< GPIO_PINCFG14_OUTCFG14                                                    */
52509   GPIO_PINCFG14_OUTCFG14_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52510   GPIO_PINCFG14_OUTCFG14_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52511                                                      and 1 values on pin.                                                      */
52512   GPIO_PINCFG14_OUTCFG14_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52513                                                      low, tristate otherwise.                                                  */
52514   GPIO_PINCFG14_OUTCFG14_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52515                                                      drive 0, 1 of HiZ on pin.                                                 */
52516 } GPIO_PINCFG14_OUTCFG14_Enum;
52517 
52518 /* =============================================  GPIO PINCFG14 IRPTEN14 [6..7]  ============================================= */
52519 typedef enum {                                  /*!< GPIO_PINCFG14_IRPTEN14                                                    */
52520   GPIO_PINCFG14_IRPTEN14_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52521   GPIO_PINCFG14_IRPTEN14_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52522                                                      on this GPIO                                                              */
52523   GPIO_PINCFG14_IRPTEN14_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52524                                                      on this GPIO                                                              */
52525   GPIO_PINCFG14_IRPTEN14_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52526                                                      GPIO                                                                      */
52527 } GPIO_PINCFG14_IRPTEN14_Enum;
52528 
52529 /* =============================================  GPIO PINCFG14 FNCSEL14 [0..3]  ============================================= */
52530 typedef enum {                                  /*!< GPIO_PINCFG14_FNCSEL14                                                    */
52531   GPIO_PINCFG14_FNCSEL14_ADCSE5        = 0,     /*!< ADCSE5 : Analog to Digital Converter SE IN5                               */
52532   GPIO_PINCFG14_FNCSEL14_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
52533   GPIO_PINCFG14_FNCSEL14_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
52534   GPIO_PINCFG14_FNCSEL14_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52535   GPIO_PINCFG14_FNCSEL14_MILLI_CLK     = 4,     /*!< MILLI_CLK : MILLI Clock                                                   */
52536   GPIO_PINCFG14_FNCSEL14_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
52537   GPIO_PINCFG14_FNCSEL14_CT14          = 6,     /*!< CT14 : Timer/Counter input or output; Selection of direction
52538                                                      is done via CTIMER register settings.                                     */
52539   GPIO_PINCFG14_FNCSEL14_NCE14         = 7,     /*!< NCE14 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52540                                                      CE_POLARITY field                                                         */
52541   GPIO_PINCFG14_FNCSEL14_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
52542   GPIO_PINCFG14_FNCSEL14_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
52543   GPIO_PINCFG14_FNCSEL14_I2S0_SDIN     = 10,    /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
52544   GPIO_PINCFG14_FNCSEL14_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52545   GPIO_PINCFG14_FNCSEL14_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52546   GPIO_PINCFG14_FNCSEL14_FLLOAD_ADDR   = 13,    /*!< FLLOAD_ADDR : Internal function (Flash parallel load)                     */
52547   GPIO_PINCFG14_FNCSEL14_MDA_TRSTN     = 14,    /*!< MDA_TRSTN : Internal function (MBIST)                                     */
52548   GPIO_PINCFG14_FNCSEL14_SCANOUT2      = 15,    /*!< SCANOUT2 : Internal function (SCAN)                                       */
52549 } GPIO_PINCFG14_FNCSEL14_Enum;
52550 
52551 /* =======================================================  PINCFG15  ======================================================== */
52552 /* ============================================  GPIO PINCFG15 NCEPOL15 [22..22]  ============================================ */
52553 typedef enum {                                  /*!< GPIO_PINCFG15_NCEPOL15                                                    */
52554   GPIO_PINCFG15_NCEPOL15_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52555   GPIO_PINCFG15_NCEPOL15_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52556 } GPIO_PINCFG15_NCEPOL15_Enum;
52557 
52558 /* ============================================  GPIO PINCFG15 NCESRC15 [16..21]  ============================================ */
52559 typedef enum {                                  /*!< GPIO_PINCFG15_NCESRC15                                                    */
52560   GPIO_PINCFG15_NCESRC15_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52561   GPIO_PINCFG15_NCESRC15_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52562   GPIO_PINCFG15_NCESRC15_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52563   GPIO_PINCFG15_NCESRC15_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52564   GPIO_PINCFG15_NCESRC15_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52565   GPIO_PINCFG15_NCESRC15_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52566   GPIO_PINCFG15_NCESRC15_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52567   GPIO_PINCFG15_NCESRC15_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52568   GPIO_PINCFG15_NCESRC15_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52569   GPIO_PINCFG15_NCESRC15_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52570   GPIO_PINCFG15_NCESRC15_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52571   GPIO_PINCFG15_NCESRC15_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52572   GPIO_PINCFG15_NCESRC15_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52573   GPIO_PINCFG15_NCESRC15_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52574   GPIO_PINCFG15_NCESRC15_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52575   GPIO_PINCFG15_NCESRC15_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52576   GPIO_PINCFG15_NCESRC15_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52577   GPIO_PINCFG15_NCESRC15_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52578   GPIO_PINCFG15_NCESRC15_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52579   GPIO_PINCFG15_NCESRC15_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52580   GPIO_PINCFG15_NCESRC15_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52581   GPIO_PINCFG15_NCESRC15_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52582   GPIO_PINCFG15_NCESRC15_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52583   GPIO_PINCFG15_NCESRC15_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52584   GPIO_PINCFG15_NCESRC15_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52585   GPIO_PINCFG15_NCESRC15_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52586   GPIO_PINCFG15_NCESRC15_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52587   GPIO_PINCFG15_NCESRC15_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52588   GPIO_PINCFG15_NCESRC15_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52589   GPIO_PINCFG15_NCESRC15_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52590   GPIO_PINCFG15_NCESRC15_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52591   GPIO_PINCFG15_NCESRC15_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52592   GPIO_PINCFG15_NCESRC15_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52593   GPIO_PINCFG15_NCESRC15_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52594   GPIO_PINCFG15_NCESRC15_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52595   GPIO_PINCFG15_NCESRC15_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52596   GPIO_PINCFG15_NCESRC15_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52597   GPIO_PINCFG15_NCESRC15_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52598   GPIO_PINCFG15_NCESRC15_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52599   GPIO_PINCFG15_NCESRC15_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52600   GPIO_PINCFG15_NCESRC15_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52601   GPIO_PINCFG15_NCESRC15_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52602   GPIO_PINCFG15_NCESRC15_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52603 } GPIO_PINCFG15_NCESRC15_Enum;
52604 
52605 /* ===========================================  GPIO PINCFG15 PULLCFG15 [13..15]  ============================================ */
52606 typedef enum {                                  /*!< GPIO_PINCFG15_PULLCFG15                                                   */
52607   GPIO_PINCFG15_PULLCFG15_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52608   GPIO_PINCFG15_PULLCFG15_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52609   GPIO_PINCFG15_PULLCFG15_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52610   GPIO_PINCFG15_PULLCFG15_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52611   GPIO_PINCFG15_PULLCFG15_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52612   GPIO_PINCFG15_PULLCFG15_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52613   GPIO_PINCFG15_PULLCFG15_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52614   GPIO_PINCFG15_PULLCFG15_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52615 } GPIO_PINCFG15_PULLCFG15_Enum;
52616 
52617 /* ==============================================  GPIO PINCFG15 DS15 [10..11]  ============================================== */
52618 typedef enum {                                  /*!< GPIO_PINCFG15_DS15                                                        */
52619   GPIO_PINCFG15_DS15_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52620   GPIO_PINCFG15_DS15_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52621 } GPIO_PINCFG15_DS15_Enum;
52622 
52623 /* =============================================  GPIO PINCFG15 OUTCFG15 [8..9]  ============================================= */
52624 typedef enum {                                  /*!< GPIO_PINCFG15_OUTCFG15                                                    */
52625   GPIO_PINCFG15_OUTCFG15_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52626   GPIO_PINCFG15_OUTCFG15_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52627                                                      and 1 values on pin.                                                      */
52628   GPIO_PINCFG15_OUTCFG15_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52629                                                      low, tristate otherwise.                                                  */
52630   GPIO_PINCFG15_OUTCFG15_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52631                                                      drive 0, 1 of HiZ on pin.                                                 */
52632 } GPIO_PINCFG15_OUTCFG15_Enum;
52633 
52634 /* =============================================  GPIO PINCFG15 IRPTEN15 [6..7]  ============================================= */
52635 typedef enum {                                  /*!< GPIO_PINCFG15_IRPTEN15                                                    */
52636   GPIO_PINCFG15_IRPTEN15_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52637   GPIO_PINCFG15_IRPTEN15_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52638                                                      on this GPIO                                                              */
52639   GPIO_PINCFG15_IRPTEN15_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52640                                                      on this GPIO                                                              */
52641   GPIO_PINCFG15_IRPTEN15_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52642                                                      GPIO                                                                      */
52643 } GPIO_PINCFG15_IRPTEN15_Enum;
52644 
52645 /* =============================================  GPIO PINCFG15 FNCSEL15 [0..3]  ============================================= */
52646 typedef enum {                                  /*!< GPIO_PINCFG15_FNCSEL15                                                    */
52647   GPIO_PINCFG15_FNCSEL15_ADCSE4        = 0,     /*!< ADCSE4 : Analog to Digital Converter SE IN4                               */
52648   GPIO_PINCFG15_FNCSEL15_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
52649   GPIO_PINCFG15_FNCSEL15_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
52650   GPIO_PINCFG15_FNCSEL15_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52651   GPIO_PINCFG15_FNCSEL15_MILLI_REC_DAT = 4,     /*!< MILLI_REC_DAT : MILLI Record Data                                         */
52652   GPIO_PINCFG15_FNCSEL15_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
52653   GPIO_PINCFG15_FNCSEL15_CT15          = 6,     /*!< CT15 : Timer/Counter input or output; Selection of direction
52654                                                      is done via CTIMER register settings.                                     */
52655   GPIO_PINCFG15_FNCSEL15_NCE15         = 7,     /*!< NCE15 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52656                                                      CE_POLARITY field                                                         */
52657   GPIO_PINCFG15_FNCSEL15_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
52658   GPIO_PINCFG15_FNCSEL15_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
52659   GPIO_PINCFG15_FNCSEL15_REFCLK_EXT    = 10,    /*!< REFCLK_EXT : External Reference Clock                                     */
52660   GPIO_PINCFG15_FNCSEL15_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52661   GPIO_PINCFG15_FNCSEL15_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52662   GPIO_PINCFG15_FNCSEL15_FLLOAD_DATA   = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
52663   GPIO_PINCFG15_FNCSEL15_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52664   GPIO_PINCFG15_FNCSEL15_SCANOUT1      = 15,    /*!< SCANOUT1 : Internal function (SCAN)                                       */
52665 } GPIO_PINCFG15_FNCSEL15_Enum;
52666 
52667 /* =======================================================  PINCFG16  ======================================================== */
52668 /* ============================================  GPIO PINCFG16 NCEPOL16 [22..22]  ============================================ */
52669 typedef enum {                                  /*!< GPIO_PINCFG16_NCEPOL16                                                    */
52670   GPIO_PINCFG16_NCEPOL16_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52671   GPIO_PINCFG16_NCEPOL16_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52672 } GPIO_PINCFG16_NCEPOL16_Enum;
52673 
52674 /* ============================================  GPIO PINCFG16 NCESRC16 [16..21]  ============================================ */
52675 typedef enum {                                  /*!< GPIO_PINCFG16_NCESRC16                                                    */
52676   GPIO_PINCFG16_NCESRC16_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52677   GPIO_PINCFG16_NCESRC16_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52678   GPIO_PINCFG16_NCESRC16_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52679   GPIO_PINCFG16_NCESRC16_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52680   GPIO_PINCFG16_NCESRC16_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52681   GPIO_PINCFG16_NCESRC16_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52682   GPIO_PINCFG16_NCESRC16_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52683   GPIO_PINCFG16_NCESRC16_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52684   GPIO_PINCFG16_NCESRC16_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52685   GPIO_PINCFG16_NCESRC16_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52686   GPIO_PINCFG16_NCESRC16_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52687   GPIO_PINCFG16_NCESRC16_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52688   GPIO_PINCFG16_NCESRC16_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52689   GPIO_PINCFG16_NCESRC16_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52690   GPIO_PINCFG16_NCESRC16_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52691   GPIO_PINCFG16_NCESRC16_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52692   GPIO_PINCFG16_NCESRC16_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52693   GPIO_PINCFG16_NCESRC16_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52694   GPIO_PINCFG16_NCESRC16_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52695   GPIO_PINCFG16_NCESRC16_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52696   GPIO_PINCFG16_NCESRC16_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52697   GPIO_PINCFG16_NCESRC16_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52698   GPIO_PINCFG16_NCESRC16_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52699   GPIO_PINCFG16_NCESRC16_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52700   GPIO_PINCFG16_NCESRC16_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52701   GPIO_PINCFG16_NCESRC16_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52702   GPIO_PINCFG16_NCESRC16_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52703   GPIO_PINCFG16_NCESRC16_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52704   GPIO_PINCFG16_NCESRC16_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52705   GPIO_PINCFG16_NCESRC16_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52706   GPIO_PINCFG16_NCESRC16_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52707   GPIO_PINCFG16_NCESRC16_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52708   GPIO_PINCFG16_NCESRC16_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52709   GPIO_PINCFG16_NCESRC16_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52710   GPIO_PINCFG16_NCESRC16_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52711   GPIO_PINCFG16_NCESRC16_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52712   GPIO_PINCFG16_NCESRC16_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52713   GPIO_PINCFG16_NCESRC16_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52714   GPIO_PINCFG16_NCESRC16_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52715   GPIO_PINCFG16_NCESRC16_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52716   GPIO_PINCFG16_NCESRC16_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52717   GPIO_PINCFG16_NCESRC16_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52718   GPIO_PINCFG16_NCESRC16_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52719 } GPIO_PINCFG16_NCESRC16_Enum;
52720 
52721 /* ===========================================  GPIO PINCFG16 PULLCFG16 [13..15]  ============================================ */
52722 typedef enum {                                  /*!< GPIO_PINCFG16_PULLCFG16                                                   */
52723   GPIO_PINCFG16_PULLCFG16_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52724   GPIO_PINCFG16_PULLCFG16_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52725   GPIO_PINCFG16_PULLCFG16_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52726   GPIO_PINCFG16_PULLCFG16_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52727   GPIO_PINCFG16_PULLCFG16_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52728   GPIO_PINCFG16_PULLCFG16_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52729   GPIO_PINCFG16_PULLCFG16_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52730   GPIO_PINCFG16_PULLCFG16_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52731 } GPIO_PINCFG16_PULLCFG16_Enum;
52732 
52733 /* ==============================================  GPIO PINCFG16 DS16 [10..11]  ============================================== */
52734 typedef enum {                                  /*!< GPIO_PINCFG16_DS16                                                        */
52735   GPIO_PINCFG16_DS16_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52736   GPIO_PINCFG16_DS16_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52737 } GPIO_PINCFG16_DS16_Enum;
52738 
52739 /* =============================================  GPIO PINCFG16 OUTCFG16 [8..9]  ============================================= */
52740 typedef enum {                                  /*!< GPIO_PINCFG16_OUTCFG16                                                    */
52741   GPIO_PINCFG16_OUTCFG16_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52742   GPIO_PINCFG16_OUTCFG16_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52743                                                      and 1 values on pin.                                                      */
52744   GPIO_PINCFG16_OUTCFG16_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52745                                                      low, tristate otherwise.                                                  */
52746   GPIO_PINCFG16_OUTCFG16_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52747                                                      drive 0, 1 of HiZ on pin.                                                 */
52748 } GPIO_PINCFG16_OUTCFG16_Enum;
52749 
52750 /* =============================================  GPIO PINCFG16 IRPTEN16 [6..7]  ============================================= */
52751 typedef enum {                                  /*!< GPIO_PINCFG16_IRPTEN16                                                    */
52752   GPIO_PINCFG16_IRPTEN16_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52753   GPIO_PINCFG16_IRPTEN16_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52754                                                      on this GPIO                                                              */
52755   GPIO_PINCFG16_IRPTEN16_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52756                                                      on this GPIO                                                              */
52757   GPIO_PINCFG16_IRPTEN16_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52758                                                      GPIO                                                                      */
52759 } GPIO_PINCFG16_IRPTEN16_Enum;
52760 
52761 /* =============================================  GPIO PINCFG16 FNCSEL16 [0..3]  ============================================= */
52762 typedef enum {                                  /*!< GPIO_PINCFG16_FNCSEL16                                                    */
52763   GPIO_PINCFG16_FNCSEL16_ADCSE3        = 0,     /*!< ADCSE3 : Analog to Digital Converter SE IN3                               */
52764   GPIO_PINCFG16_FNCSEL16_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
52765   GPIO_PINCFG16_FNCSEL16_I2S1_CLK      = 2,     /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
52766                                                      in master mode and input mode for slave mode. (I2S Master/Slave
52767                                                      2)                                                                        */
52768   GPIO_PINCFG16_FNCSEL16_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52769   GPIO_PINCFG16_FNCSEL16_MILLI_PBDATA1 = 4,     /*!< MILLI_PBDATA1 : MILLI Playback Data1                                      */
52770   GPIO_PINCFG16_FNCSEL16_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
52771   GPIO_PINCFG16_FNCSEL16_CT16          = 6,     /*!< CT16 : Timer/Counter input or output; Selection of direction
52772                                                      is done via CTIMER register settings.                                     */
52773   GPIO_PINCFG16_FNCSEL16_NCE16         = 7,     /*!< NCE16 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52774                                                      CE_POLARITY field                                                         */
52775   GPIO_PINCFG16_FNCSEL16_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
52776   GPIO_PINCFG16_FNCSEL16_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
52777   GPIO_PINCFG16_FNCSEL16_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52778   GPIO_PINCFG16_FNCSEL16_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52779   GPIO_PINCFG16_FNCSEL16_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52780   GPIO_PINCFG16_FNCSEL16_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
52781   GPIO_PINCFG16_FNCSEL16_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
52782   GPIO_PINCFG16_FNCSEL16_DFT_RET       = 15,    /*!< DFT_RET : Internal function (SCAN)                                        */
52783 } GPIO_PINCFG16_FNCSEL16_Enum;
52784 
52785 /* =======================================================  PINCFG17  ======================================================== */
52786 /* ============================================  GPIO PINCFG17 NCEPOL17 [22..22]  ============================================ */
52787 typedef enum {                                  /*!< GPIO_PINCFG17_NCEPOL17                                                    */
52788   GPIO_PINCFG17_NCEPOL17_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52789   GPIO_PINCFG17_NCEPOL17_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52790 } GPIO_PINCFG17_NCEPOL17_Enum;
52791 
52792 /* ============================================  GPIO PINCFG17 NCESRC17 [16..21]  ============================================ */
52793 typedef enum {                                  /*!< GPIO_PINCFG17_NCESRC17                                                    */
52794   GPIO_PINCFG17_NCESRC17_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52795   GPIO_PINCFG17_NCESRC17_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52796   GPIO_PINCFG17_NCESRC17_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52797   GPIO_PINCFG17_NCESRC17_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52798   GPIO_PINCFG17_NCESRC17_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52799   GPIO_PINCFG17_NCESRC17_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52800   GPIO_PINCFG17_NCESRC17_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52801   GPIO_PINCFG17_NCESRC17_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52802   GPIO_PINCFG17_NCESRC17_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52803   GPIO_PINCFG17_NCESRC17_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52804   GPIO_PINCFG17_NCESRC17_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52805   GPIO_PINCFG17_NCESRC17_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52806   GPIO_PINCFG17_NCESRC17_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52807   GPIO_PINCFG17_NCESRC17_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52808   GPIO_PINCFG17_NCESRC17_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52809   GPIO_PINCFG17_NCESRC17_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52810   GPIO_PINCFG17_NCESRC17_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52811   GPIO_PINCFG17_NCESRC17_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52812   GPIO_PINCFG17_NCESRC17_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52813   GPIO_PINCFG17_NCESRC17_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52814   GPIO_PINCFG17_NCESRC17_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52815   GPIO_PINCFG17_NCESRC17_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52816   GPIO_PINCFG17_NCESRC17_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52817   GPIO_PINCFG17_NCESRC17_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52818   GPIO_PINCFG17_NCESRC17_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52819   GPIO_PINCFG17_NCESRC17_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52820   GPIO_PINCFG17_NCESRC17_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52821   GPIO_PINCFG17_NCESRC17_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52822   GPIO_PINCFG17_NCESRC17_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52823   GPIO_PINCFG17_NCESRC17_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52824   GPIO_PINCFG17_NCESRC17_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52825   GPIO_PINCFG17_NCESRC17_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52826   GPIO_PINCFG17_NCESRC17_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52827   GPIO_PINCFG17_NCESRC17_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52828   GPIO_PINCFG17_NCESRC17_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52829   GPIO_PINCFG17_NCESRC17_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52830   GPIO_PINCFG17_NCESRC17_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52831   GPIO_PINCFG17_NCESRC17_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52832   GPIO_PINCFG17_NCESRC17_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52833   GPIO_PINCFG17_NCESRC17_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52834   GPIO_PINCFG17_NCESRC17_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52835   GPIO_PINCFG17_NCESRC17_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52836   GPIO_PINCFG17_NCESRC17_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52837 } GPIO_PINCFG17_NCESRC17_Enum;
52838 
52839 /* ===========================================  GPIO PINCFG17 PULLCFG17 [13..15]  ============================================ */
52840 typedef enum {                                  /*!< GPIO_PINCFG17_PULLCFG17                                                   */
52841   GPIO_PINCFG17_PULLCFG17_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52842   GPIO_PINCFG17_PULLCFG17_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52843   GPIO_PINCFG17_PULLCFG17_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52844   GPIO_PINCFG17_PULLCFG17_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52845   GPIO_PINCFG17_PULLCFG17_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52846   GPIO_PINCFG17_PULLCFG17_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52847   GPIO_PINCFG17_PULLCFG17_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52848   GPIO_PINCFG17_PULLCFG17_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52849 } GPIO_PINCFG17_PULLCFG17_Enum;
52850 
52851 /* ==============================================  GPIO PINCFG17 DS17 [10..11]  ============================================== */
52852 typedef enum {                                  /*!< GPIO_PINCFG17_DS17                                                        */
52853   GPIO_PINCFG17_DS17_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52854   GPIO_PINCFG17_DS17_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52855 } GPIO_PINCFG17_DS17_Enum;
52856 
52857 /* =============================================  GPIO PINCFG17 OUTCFG17 [8..9]  ============================================= */
52858 typedef enum {                                  /*!< GPIO_PINCFG17_OUTCFG17                                                    */
52859   GPIO_PINCFG17_OUTCFG17_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52860   GPIO_PINCFG17_OUTCFG17_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52861                                                      and 1 values on pin.                                                      */
52862   GPIO_PINCFG17_OUTCFG17_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52863                                                      low, tristate otherwise.                                                  */
52864   GPIO_PINCFG17_OUTCFG17_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52865                                                      drive 0, 1 of HiZ on pin.                                                 */
52866 } GPIO_PINCFG17_OUTCFG17_Enum;
52867 
52868 /* =============================================  GPIO PINCFG17 IRPTEN17 [6..7]  ============================================= */
52869 typedef enum {                                  /*!< GPIO_PINCFG17_IRPTEN17                                                    */
52870   GPIO_PINCFG17_IRPTEN17_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52871   GPIO_PINCFG17_IRPTEN17_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52872                                                      on this GPIO                                                              */
52873   GPIO_PINCFG17_IRPTEN17_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52874                                                      on this GPIO                                                              */
52875   GPIO_PINCFG17_IRPTEN17_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52876                                                      GPIO                                                                      */
52877 } GPIO_PINCFG17_IRPTEN17_Enum;
52878 
52879 /* =============================================  GPIO PINCFG17 FNCSEL17 [0..3]  ============================================= */
52880 typedef enum {                                  /*!< GPIO_PINCFG17_FNCSEL17                                                    */
52881   GPIO_PINCFG17_FNCSEL17_ADCSE2        = 0,     /*!< ADCSE2 : Analog to Digital Converter SE IN2                               */
52882   GPIO_PINCFG17_FNCSEL17_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
52883   GPIO_PINCFG17_FNCSEL17_I2S1_DATA     = 2,     /*!< I2S1_DATA : Bidirectional I2S Data. Operates in output mode
52884                                                      in master mode and input mode for slave mode. (I2S Master/Slave
52885                                                      2)                                                                        */
52886   GPIO_PINCFG17_FNCSEL17_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
52887   GPIO_PINCFG17_FNCSEL17_MILLI_PBDATA2 = 4,     /*!< MILLI_PBDATA2 : MILLI Playback Data2                                      */
52888   GPIO_PINCFG17_FNCSEL17_UART3RTS      = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
52889   GPIO_PINCFG17_FNCSEL17_CT17          = 6,     /*!< CT17 : Timer/Counter input or output; Selection of direction
52890                                                      is done via CTIMER register settings.                                     */
52891   GPIO_PINCFG17_FNCSEL17_NCE17         = 7,     /*!< NCE17 : IOMSTR/MSPI N Chip Select. Polarity is determined by
52892                                                      CE_POLARITY field                                                         */
52893   GPIO_PINCFG17_FNCSEL17_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
52894   GPIO_PINCFG17_FNCSEL17_I2S1_SDOUT    = 9,     /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
52895   GPIO_PINCFG17_FNCSEL17_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
52896   GPIO_PINCFG17_FNCSEL17_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
52897   GPIO_PINCFG17_FNCSEL17_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
52898   GPIO_PINCFG17_FNCSEL17_FLLOAD_STRB   = 13,    /*!< FLLOAD_STRB : Internal function (Flash parallel load)                     */
52899   GPIO_PINCFG17_FNCSEL17_MDA_TMS       = 14,    /*!< MDA_TMS : Internal function (MBIST)                                       */
52900   GPIO_PINCFG17_FNCSEL17_OPCG_CLK      = 15,    /*!< OPCG_CLK : Internal function (SCAN)                                       */
52901 } GPIO_PINCFG17_FNCSEL17_Enum;
52902 
52903 /* =======================================================  PINCFG18  ======================================================== */
52904 /* ============================================  GPIO PINCFG18 NCEPOL18 [22..22]  ============================================ */
52905 typedef enum {                                  /*!< GPIO_PINCFG18_NCEPOL18                                                    */
52906   GPIO_PINCFG18_NCEPOL18_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
52907   GPIO_PINCFG18_NCEPOL18_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
52908 } GPIO_PINCFG18_NCEPOL18_Enum;
52909 
52910 /* ============================================  GPIO PINCFG18 NCESRC18 [16..21]  ============================================ */
52911 typedef enum {                                  /*!< GPIO_PINCFG18_NCESRC18                                                    */
52912   GPIO_PINCFG18_NCESRC18_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
52913   GPIO_PINCFG18_NCESRC18_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
52914   GPIO_PINCFG18_NCESRC18_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
52915   GPIO_PINCFG18_NCESRC18_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
52916   GPIO_PINCFG18_NCESRC18_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
52917   GPIO_PINCFG18_NCESRC18_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
52918   GPIO_PINCFG18_NCESRC18_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
52919   GPIO_PINCFG18_NCESRC18_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
52920   GPIO_PINCFG18_NCESRC18_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
52921   GPIO_PINCFG18_NCESRC18_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
52922   GPIO_PINCFG18_NCESRC18_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
52923   GPIO_PINCFG18_NCESRC18_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
52924   GPIO_PINCFG18_NCESRC18_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
52925   GPIO_PINCFG18_NCESRC18_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
52926   GPIO_PINCFG18_NCESRC18_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
52927   GPIO_PINCFG18_NCESRC18_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
52928   GPIO_PINCFG18_NCESRC18_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
52929   GPIO_PINCFG18_NCESRC18_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
52930   GPIO_PINCFG18_NCESRC18_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
52931   GPIO_PINCFG18_NCESRC18_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
52932   GPIO_PINCFG18_NCESRC18_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
52933   GPIO_PINCFG18_NCESRC18_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
52934   GPIO_PINCFG18_NCESRC18_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
52935   GPIO_PINCFG18_NCESRC18_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
52936   GPIO_PINCFG18_NCESRC18_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
52937   GPIO_PINCFG18_NCESRC18_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
52938   GPIO_PINCFG18_NCESRC18_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
52939   GPIO_PINCFG18_NCESRC18_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
52940   GPIO_PINCFG18_NCESRC18_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
52941   GPIO_PINCFG18_NCESRC18_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
52942   GPIO_PINCFG18_NCESRC18_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
52943   GPIO_PINCFG18_NCESRC18_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
52944   GPIO_PINCFG18_NCESRC18_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
52945   GPIO_PINCFG18_NCESRC18_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
52946   GPIO_PINCFG18_NCESRC18_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
52947   GPIO_PINCFG18_NCESRC18_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
52948   GPIO_PINCFG18_NCESRC18_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
52949   GPIO_PINCFG18_NCESRC18_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
52950   GPIO_PINCFG18_NCESRC18_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
52951   GPIO_PINCFG18_NCESRC18_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
52952   GPIO_PINCFG18_NCESRC18_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
52953   GPIO_PINCFG18_NCESRC18_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
52954   GPIO_PINCFG18_NCESRC18_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
52955 } GPIO_PINCFG18_NCESRC18_Enum;
52956 
52957 /* ===========================================  GPIO PINCFG18 PULLCFG18 [13..15]  ============================================ */
52958 typedef enum {                                  /*!< GPIO_PINCFG18_PULLCFG18                                                   */
52959   GPIO_PINCFG18_PULLCFG18_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
52960   GPIO_PINCFG18_PULLCFG18_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
52961   GPIO_PINCFG18_PULLCFG18_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
52962   GPIO_PINCFG18_PULLCFG18_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
52963   GPIO_PINCFG18_PULLCFG18_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
52964   GPIO_PINCFG18_PULLCFG18_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
52965   GPIO_PINCFG18_PULLCFG18_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
52966   GPIO_PINCFG18_PULLCFG18_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
52967 } GPIO_PINCFG18_PULLCFG18_Enum;
52968 
52969 /* ==============================================  GPIO PINCFG18 DS18 [10..11]  ============================================== */
52970 typedef enum {                                  /*!< GPIO_PINCFG18_DS18                                                        */
52971   GPIO_PINCFG18_DS18_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
52972   GPIO_PINCFG18_DS18_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
52973 } GPIO_PINCFG18_DS18_Enum;
52974 
52975 /* =============================================  GPIO PINCFG18 OUTCFG18 [8..9]  ============================================= */
52976 typedef enum {                                  /*!< GPIO_PINCFG18_OUTCFG18                                                    */
52977   GPIO_PINCFG18_OUTCFG18_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
52978   GPIO_PINCFG18_OUTCFG18_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
52979                                                      and 1 values on pin.                                                      */
52980   GPIO_PINCFG18_OUTCFG18_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
52981                                                      low, tristate otherwise.                                                  */
52982   GPIO_PINCFG18_OUTCFG18_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
52983                                                      drive 0, 1 of HiZ on pin.                                                 */
52984 } GPIO_PINCFG18_OUTCFG18_Enum;
52985 
52986 /* =============================================  GPIO PINCFG18 IRPTEN18 [6..7]  ============================================= */
52987 typedef enum {                                  /*!< GPIO_PINCFG18_IRPTEN18                                                    */
52988   GPIO_PINCFG18_IRPTEN18_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
52989   GPIO_PINCFG18_IRPTEN18_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
52990                                                      on this GPIO                                                              */
52991   GPIO_PINCFG18_IRPTEN18_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
52992                                                      on this GPIO                                                              */
52993   GPIO_PINCFG18_IRPTEN18_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
52994                                                      GPIO                                                                      */
52995 } GPIO_PINCFG18_IRPTEN18_Enum;
52996 
52997 /* =============================================  GPIO PINCFG18 FNCSEL18 [0..3]  ============================================= */
52998 typedef enum {                                  /*!< GPIO_PINCFG18_FNCSEL18                                                    */
52999   GPIO_PINCFG18_FNCSEL18_ADCSE1        = 0,     /*!< ADCSE1 : Analog to Digital Converter SE IN1                               */
53000   GPIO_PINCFG18_FNCSEL18_ANATEST2      = 1,     /*!< ANATEST2 : Ambiq Analog test I/O - Unbuffered                             */
53001   GPIO_PINCFG18_FNCSEL18_I2S1_WS       = 2,     /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
53002                                                      in master mode and input mode for slave mode. (I2S Master/Slave
53003                                                      2)                                                                        */
53004   GPIO_PINCFG18_FNCSEL18_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53005   GPIO_PINCFG18_FNCSEL18_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
53006   GPIO_PINCFG18_FNCSEL18_UART1CTS      = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
53007   GPIO_PINCFG18_FNCSEL18_CT18          = 6,     /*!< CT18 : Timer/Counter input or output; Selection of direction
53008                                                      is done via CTIMER register settings.                                     */
53009   GPIO_PINCFG18_FNCSEL18_NCE18         = 7,     /*!< NCE18 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53010                                                      CE_POLARITY field                                                         */
53011   GPIO_PINCFG18_FNCSEL18_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
53012   GPIO_PINCFG18_FNCSEL18_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
53013   GPIO_PINCFG18_FNCSEL18_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53014   GPIO_PINCFG18_FNCSEL18_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53015   GPIO_PINCFG18_FNCSEL18_FLB_TMS       = 12,    /*!< FLB_TMS : Internal function (Flash Bist)                                  */
53016   GPIO_PINCFG18_FNCSEL18_FLLOAD_DATA   = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
53017   GPIO_PINCFG18_FNCSEL18_MDA_HFRC_EXT  = 14,    /*!< MDA_HFRC_EXT : Internal function (MBIST)                                  */
53018   GPIO_PINCFG18_FNCSEL18_SCANIN1       = 15,    /*!< SCANIN1 : Internal function (SCAN)                                        */
53019 } GPIO_PINCFG18_FNCSEL18_Enum;
53020 
53021 /* =======================================================  PINCFG19  ======================================================== */
53022 /* ============================================  GPIO PINCFG19 NCEPOL19 [22..22]  ============================================ */
53023 typedef enum {                                  /*!< GPIO_PINCFG19_NCEPOL19                                                    */
53024   GPIO_PINCFG19_NCEPOL19_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53025   GPIO_PINCFG19_NCEPOL19_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53026 } GPIO_PINCFG19_NCEPOL19_Enum;
53027 
53028 /* ============================================  GPIO PINCFG19 NCESRC19 [16..21]  ============================================ */
53029 typedef enum {                                  /*!< GPIO_PINCFG19_NCESRC19                                                    */
53030   GPIO_PINCFG19_NCESRC19_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53031   GPIO_PINCFG19_NCESRC19_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53032   GPIO_PINCFG19_NCESRC19_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53033   GPIO_PINCFG19_NCESRC19_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53034   GPIO_PINCFG19_NCESRC19_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53035   GPIO_PINCFG19_NCESRC19_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53036   GPIO_PINCFG19_NCESRC19_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53037   GPIO_PINCFG19_NCESRC19_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53038   GPIO_PINCFG19_NCESRC19_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53039   GPIO_PINCFG19_NCESRC19_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53040   GPIO_PINCFG19_NCESRC19_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53041   GPIO_PINCFG19_NCESRC19_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53042   GPIO_PINCFG19_NCESRC19_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53043   GPIO_PINCFG19_NCESRC19_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53044   GPIO_PINCFG19_NCESRC19_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53045   GPIO_PINCFG19_NCESRC19_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53046   GPIO_PINCFG19_NCESRC19_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53047   GPIO_PINCFG19_NCESRC19_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53048   GPIO_PINCFG19_NCESRC19_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53049   GPIO_PINCFG19_NCESRC19_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53050   GPIO_PINCFG19_NCESRC19_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53051   GPIO_PINCFG19_NCESRC19_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53052   GPIO_PINCFG19_NCESRC19_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53053   GPIO_PINCFG19_NCESRC19_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53054   GPIO_PINCFG19_NCESRC19_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53055   GPIO_PINCFG19_NCESRC19_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53056   GPIO_PINCFG19_NCESRC19_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53057   GPIO_PINCFG19_NCESRC19_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53058   GPIO_PINCFG19_NCESRC19_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53059   GPIO_PINCFG19_NCESRC19_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53060   GPIO_PINCFG19_NCESRC19_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53061   GPIO_PINCFG19_NCESRC19_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53062   GPIO_PINCFG19_NCESRC19_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53063   GPIO_PINCFG19_NCESRC19_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53064   GPIO_PINCFG19_NCESRC19_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53065   GPIO_PINCFG19_NCESRC19_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53066   GPIO_PINCFG19_NCESRC19_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53067   GPIO_PINCFG19_NCESRC19_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53068   GPIO_PINCFG19_NCESRC19_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53069   GPIO_PINCFG19_NCESRC19_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53070   GPIO_PINCFG19_NCESRC19_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53071   GPIO_PINCFG19_NCESRC19_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53072   GPIO_PINCFG19_NCESRC19_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53073 } GPIO_PINCFG19_NCESRC19_Enum;
53074 
53075 /* ===========================================  GPIO PINCFG19 PULLCFG19 [13..15]  ============================================ */
53076 typedef enum {                                  /*!< GPIO_PINCFG19_PULLCFG19                                                   */
53077   GPIO_PINCFG19_PULLCFG19_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53078   GPIO_PINCFG19_PULLCFG19_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53079   GPIO_PINCFG19_PULLCFG19_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53080   GPIO_PINCFG19_PULLCFG19_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53081   GPIO_PINCFG19_PULLCFG19_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53082   GPIO_PINCFG19_PULLCFG19_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53083   GPIO_PINCFG19_PULLCFG19_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53084   GPIO_PINCFG19_PULLCFG19_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53085 } GPIO_PINCFG19_PULLCFG19_Enum;
53086 
53087 /* ==============================================  GPIO PINCFG19 DS19 [10..11]  ============================================== */
53088 typedef enum {                                  /*!< GPIO_PINCFG19_DS19                                                        */
53089   GPIO_PINCFG19_DS19_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53090   GPIO_PINCFG19_DS19_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53091 } GPIO_PINCFG19_DS19_Enum;
53092 
53093 /* =============================================  GPIO PINCFG19 OUTCFG19 [8..9]  ============================================= */
53094 typedef enum {                                  /*!< GPIO_PINCFG19_OUTCFG19                                                    */
53095   GPIO_PINCFG19_OUTCFG19_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53096   GPIO_PINCFG19_OUTCFG19_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53097                                                      and 1 values on pin.                                                      */
53098   GPIO_PINCFG19_OUTCFG19_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53099                                                      low, tristate otherwise.                                                  */
53100   GPIO_PINCFG19_OUTCFG19_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53101                                                      drive 0, 1 of HiZ on pin.                                                 */
53102 } GPIO_PINCFG19_OUTCFG19_Enum;
53103 
53104 /* =============================================  GPIO PINCFG19 IRPTEN19 [6..7]  ============================================= */
53105 typedef enum {                                  /*!< GPIO_PINCFG19_IRPTEN19                                                    */
53106   GPIO_PINCFG19_IRPTEN19_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53107   GPIO_PINCFG19_IRPTEN19_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53108                                                      on this GPIO                                                              */
53109   GPIO_PINCFG19_IRPTEN19_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53110                                                      on this GPIO                                                              */
53111   GPIO_PINCFG19_IRPTEN19_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53112                                                      GPIO                                                                      */
53113 } GPIO_PINCFG19_IRPTEN19_Enum;
53114 
53115 /* =============================================  GPIO PINCFG19 FNCSEL19 [0..3]  ============================================= */
53116 typedef enum {                                  /*!< GPIO_PINCFG19_FNCSEL19                                                    */
53117   GPIO_PINCFG19_FNCSEL19_ADCSE0        = 0,     /*!< ADCSE0 : Analog to Digital Converter SE IN0                               */
53118   GPIO_PINCFG19_FNCSEL19_ANATEST1      = 1,     /*!< ANATEST1 : Ambiq Analog test I/O - Buffered                               */
53119   GPIO_PINCFG19_FNCSEL19_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
53120   GPIO_PINCFG19_FNCSEL19_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53121   GPIO_PINCFG19_FNCSEL19_UART2CTS      = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
53122   GPIO_PINCFG19_FNCSEL19_UART3CTS      = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
53123   GPIO_PINCFG19_FNCSEL19_CT19          = 6,     /*!< CT19 : Timer/Counter input or output; Selection of direction
53124                                                      is done via CTIMER register settings.                                     */
53125   GPIO_PINCFG19_FNCSEL19_NCE19         = 7,     /*!< NCE19 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53126                                                      CE_POLARITY field                                                         */
53127   GPIO_PINCFG19_FNCSEL19_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
53128   GPIO_PINCFG19_FNCSEL19_I2S1_SDIN     = 9,     /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
53129   GPIO_PINCFG19_FNCSEL19_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53130   GPIO_PINCFG19_FNCSEL19_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53131   GPIO_PINCFG19_FNCSEL19_FLB_TRSTN     = 12,    /*!< FLB_TRSTN : Internal function (Flash Bist)                                */
53132   GPIO_PINCFG19_FNCSEL19_FLLOAD_ADDR   = 13,    /*!< FLLOAD_ADDR : Internal function (Flash parallel load)                     */
53133   GPIO_PINCFG19_FNCSEL19_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53134   GPIO_PINCFG19_FNCSEL19_SCANIN2       = 15,    /*!< SCANIN2 : Internal function (SCAN)                                        */
53135 } GPIO_PINCFG19_FNCSEL19_Enum;
53136 
53137 /* =======================================================  PINCFG20  ======================================================== */
53138 /* ============================================  GPIO PINCFG20 NCEPOL20 [22..22]  ============================================ */
53139 typedef enum {                                  /*!< GPIO_PINCFG20_NCEPOL20                                                    */
53140   GPIO_PINCFG20_NCEPOL20_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53141   GPIO_PINCFG20_NCEPOL20_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53142 } GPIO_PINCFG20_NCEPOL20_Enum;
53143 
53144 /* ============================================  GPIO PINCFG20 NCESRC20 [16..21]  ============================================ */
53145 typedef enum {                                  /*!< GPIO_PINCFG20_NCESRC20                                                    */
53146   GPIO_PINCFG20_NCESRC20_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53147   GPIO_PINCFG20_NCESRC20_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53148   GPIO_PINCFG20_NCESRC20_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53149   GPIO_PINCFG20_NCESRC20_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53150   GPIO_PINCFG20_NCESRC20_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53151   GPIO_PINCFG20_NCESRC20_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53152   GPIO_PINCFG20_NCESRC20_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53153   GPIO_PINCFG20_NCESRC20_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53154   GPIO_PINCFG20_NCESRC20_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53155   GPIO_PINCFG20_NCESRC20_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53156   GPIO_PINCFG20_NCESRC20_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53157   GPIO_PINCFG20_NCESRC20_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53158   GPIO_PINCFG20_NCESRC20_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53159   GPIO_PINCFG20_NCESRC20_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53160   GPIO_PINCFG20_NCESRC20_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53161   GPIO_PINCFG20_NCESRC20_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53162   GPIO_PINCFG20_NCESRC20_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53163   GPIO_PINCFG20_NCESRC20_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53164   GPIO_PINCFG20_NCESRC20_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53165   GPIO_PINCFG20_NCESRC20_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53166   GPIO_PINCFG20_NCESRC20_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53167   GPIO_PINCFG20_NCESRC20_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53168   GPIO_PINCFG20_NCESRC20_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53169   GPIO_PINCFG20_NCESRC20_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53170   GPIO_PINCFG20_NCESRC20_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53171   GPIO_PINCFG20_NCESRC20_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53172   GPIO_PINCFG20_NCESRC20_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53173   GPIO_PINCFG20_NCESRC20_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53174   GPIO_PINCFG20_NCESRC20_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53175   GPIO_PINCFG20_NCESRC20_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53176   GPIO_PINCFG20_NCESRC20_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53177   GPIO_PINCFG20_NCESRC20_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53178   GPIO_PINCFG20_NCESRC20_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53179   GPIO_PINCFG20_NCESRC20_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53180   GPIO_PINCFG20_NCESRC20_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53181   GPIO_PINCFG20_NCESRC20_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53182   GPIO_PINCFG20_NCESRC20_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53183   GPIO_PINCFG20_NCESRC20_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53184   GPIO_PINCFG20_NCESRC20_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53185   GPIO_PINCFG20_NCESRC20_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53186   GPIO_PINCFG20_NCESRC20_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53187   GPIO_PINCFG20_NCESRC20_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53188   GPIO_PINCFG20_NCESRC20_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53189 } GPIO_PINCFG20_NCESRC20_Enum;
53190 
53191 /* ===========================================  GPIO PINCFG20 PULLCFG20 [13..15]  ============================================ */
53192 typedef enum {                                  /*!< GPIO_PINCFG20_PULLCFG20                                                   */
53193   GPIO_PINCFG20_PULLCFG20_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53194   GPIO_PINCFG20_PULLCFG20_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53195   GPIO_PINCFG20_PULLCFG20_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53196   GPIO_PINCFG20_PULLCFG20_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53197   GPIO_PINCFG20_PULLCFG20_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53198   GPIO_PINCFG20_PULLCFG20_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53199   GPIO_PINCFG20_PULLCFG20_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53200   GPIO_PINCFG20_PULLCFG20_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53201 } GPIO_PINCFG20_PULLCFG20_Enum;
53202 
53203 /* ==============================================  GPIO PINCFG20 DS20 [10..11]  ============================================== */
53204 typedef enum {                                  /*!< GPIO_PINCFG20_DS20                                                        */
53205   GPIO_PINCFG20_DS20_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53206   GPIO_PINCFG20_DS20_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53207 } GPIO_PINCFG20_DS20_Enum;
53208 
53209 /* =============================================  GPIO PINCFG20 OUTCFG20 [8..9]  ============================================= */
53210 typedef enum {                                  /*!< GPIO_PINCFG20_OUTCFG20                                                    */
53211   GPIO_PINCFG20_OUTCFG20_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53212   GPIO_PINCFG20_OUTCFG20_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53213                                                      and 1 values on pin.                                                      */
53214   GPIO_PINCFG20_OUTCFG20_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53215                                                      low, tristate otherwise.                                                  */
53216   GPIO_PINCFG20_OUTCFG20_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53217                                                      drive 0, 1 of HiZ on pin.                                                 */
53218 } GPIO_PINCFG20_OUTCFG20_Enum;
53219 
53220 /* =============================================  GPIO PINCFG20 IRPTEN20 [6..7]  ============================================= */
53221 typedef enum {                                  /*!< GPIO_PINCFG20_IRPTEN20                                                    */
53222   GPIO_PINCFG20_IRPTEN20_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53223   GPIO_PINCFG20_IRPTEN20_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53224                                                      on this GPIO                                                              */
53225   GPIO_PINCFG20_IRPTEN20_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53226                                                      on this GPIO                                                              */
53227   GPIO_PINCFG20_IRPTEN20_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53228                                                      GPIO                                                                      */
53229 } GPIO_PINCFG20_IRPTEN20_Enum;
53230 
53231 /* =============================================  GPIO PINCFG20 FNCSEL20 [0..3]  ============================================= */
53232 typedef enum {                                  /*!< GPIO_PINCFG20_FNCSEL20                                                    */
53233   GPIO_PINCFG20_FNCSEL20_SWDCK         = 0,     /*!< SWDCK : Serial Wire Debug clock input                                     */
53234   GPIO_PINCFG20_FNCSEL20_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
53235   GPIO_PINCFG20_FNCSEL20_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
53236   GPIO_PINCFG20_FNCSEL20_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53237   GPIO_PINCFG20_FNCSEL20_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
53238   GPIO_PINCFG20_FNCSEL20_UART1TX       = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
53239   GPIO_PINCFG20_FNCSEL20_CT20          = 6,     /*!< CT20 : Timer/Counter input or output; Selection of direction
53240                                                      is done via CTIMER register settings.                                     */
53241   GPIO_PINCFG20_FNCSEL20_NCE20         = 7,     /*!< NCE20 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53242                                                      CE_POLARITY field                                                         */
53243   GPIO_PINCFG20_FNCSEL20_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
53244   GPIO_PINCFG20_FNCSEL20_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
53245   GPIO_PINCFG20_FNCSEL20_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53246   GPIO_PINCFG20_FNCSEL20_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53247   GPIO_PINCFG20_FNCSEL20_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53248   GPIO_PINCFG20_FNCSEL20_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53249   GPIO_PINCFG20_FNCSEL20_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53250   GPIO_PINCFG20_FNCSEL20_SCANCLK       = 15,    /*!< SCANCLK : Internal function (SCAN)                                        */
53251 } GPIO_PINCFG20_FNCSEL20_Enum;
53252 
53253 /* =======================================================  PINCFG21  ======================================================== */
53254 /* ============================================  GPIO PINCFG21 NCEPOL21 [22..22]  ============================================ */
53255 typedef enum {                                  /*!< GPIO_PINCFG21_NCEPOL21                                                    */
53256   GPIO_PINCFG21_NCEPOL21_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53257   GPIO_PINCFG21_NCEPOL21_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53258 } GPIO_PINCFG21_NCEPOL21_Enum;
53259 
53260 /* ============================================  GPIO PINCFG21 NCESRC21 [16..21]  ============================================ */
53261 typedef enum {                                  /*!< GPIO_PINCFG21_NCESRC21                                                    */
53262   GPIO_PINCFG21_NCESRC21_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53263   GPIO_PINCFG21_NCESRC21_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53264   GPIO_PINCFG21_NCESRC21_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53265   GPIO_PINCFG21_NCESRC21_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53266   GPIO_PINCFG21_NCESRC21_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53267   GPIO_PINCFG21_NCESRC21_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53268   GPIO_PINCFG21_NCESRC21_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53269   GPIO_PINCFG21_NCESRC21_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53270   GPIO_PINCFG21_NCESRC21_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53271   GPIO_PINCFG21_NCESRC21_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53272   GPIO_PINCFG21_NCESRC21_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53273   GPIO_PINCFG21_NCESRC21_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53274   GPIO_PINCFG21_NCESRC21_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53275   GPIO_PINCFG21_NCESRC21_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53276   GPIO_PINCFG21_NCESRC21_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53277   GPIO_PINCFG21_NCESRC21_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53278   GPIO_PINCFG21_NCESRC21_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53279   GPIO_PINCFG21_NCESRC21_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53280   GPIO_PINCFG21_NCESRC21_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53281   GPIO_PINCFG21_NCESRC21_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53282   GPIO_PINCFG21_NCESRC21_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53283   GPIO_PINCFG21_NCESRC21_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53284   GPIO_PINCFG21_NCESRC21_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53285   GPIO_PINCFG21_NCESRC21_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53286   GPIO_PINCFG21_NCESRC21_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53287   GPIO_PINCFG21_NCESRC21_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53288   GPIO_PINCFG21_NCESRC21_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53289   GPIO_PINCFG21_NCESRC21_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53290   GPIO_PINCFG21_NCESRC21_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53291   GPIO_PINCFG21_NCESRC21_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53292   GPIO_PINCFG21_NCESRC21_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53293   GPIO_PINCFG21_NCESRC21_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53294   GPIO_PINCFG21_NCESRC21_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53295   GPIO_PINCFG21_NCESRC21_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53296   GPIO_PINCFG21_NCESRC21_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53297   GPIO_PINCFG21_NCESRC21_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53298   GPIO_PINCFG21_NCESRC21_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53299   GPIO_PINCFG21_NCESRC21_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53300   GPIO_PINCFG21_NCESRC21_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53301   GPIO_PINCFG21_NCESRC21_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53302   GPIO_PINCFG21_NCESRC21_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53303   GPIO_PINCFG21_NCESRC21_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53304   GPIO_PINCFG21_NCESRC21_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53305 } GPIO_PINCFG21_NCESRC21_Enum;
53306 
53307 /* ===========================================  GPIO PINCFG21 PULLCFG21 [13..15]  ============================================ */
53308 typedef enum {                                  /*!< GPIO_PINCFG21_PULLCFG21                                                   */
53309   GPIO_PINCFG21_PULLCFG21_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53310   GPIO_PINCFG21_PULLCFG21_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53311   GPIO_PINCFG21_PULLCFG21_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53312   GPIO_PINCFG21_PULLCFG21_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53313   GPIO_PINCFG21_PULLCFG21_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53314   GPIO_PINCFG21_PULLCFG21_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53315   GPIO_PINCFG21_PULLCFG21_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53316   GPIO_PINCFG21_PULLCFG21_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53317 } GPIO_PINCFG21_PULLCFG21_Enum;
53318 
53319 /* ==============================================  GPIO PINCFG21 DS21 [10..11]  ============================================== */
53320 typedef enum {                                  /*!< GPIO_PINCFG21_DS21                                                        */
53321   GPIO_PINCFG21_DS21_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53322   GPIO_PINCFG21_DS21_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53323 } GPIO_PINCFG21_DS21_Enum;
53324 
53325 /* =============================================  GPIO PINCFG21 OUTCFG21 [8..9]  ============================================= */
53326 typedef enum {                                  /*!< GPIO_PINCFG21_OUTCFG21                                                    */
53327   GPIO_PINCFG21_OUTCFG21_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53328   GPIO_PINCFG21_OUTCFG21_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53329                                                      and 1 values on pin.                                                      */
53330   GPIO_PINCFG21_OUTCFG21_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53331                                                      low, tristate otherwise.                                                  */
53332   GPIO_PINCFG21_OUTCFG21_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53333                                                      drive 0, 1 of HiZ on pin.                                                 */
53334 } GPIO_PINCFG21_OUTCFG21_Enum;
53335 
53336 /* =============================================  GPIO PINCFG21 IRPTEN21 [6..7]  ============================================= */
53337 typedef enum {                                  /*!< GPIO_PINCFG21_IRPTEN21                                                    */
53338   GPIO_PINCFG21_IRPTEN21_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53339   GPIO_PINCFG21_IRPTEN21_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53340                                                      on this GPIO                                                              */
53341   GPIO_PINCFG21_IRPTEN21_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53342                                                      on this GPIO                                                              */
53343   GPIO_PINCFG21_IRPTEN21_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53344                                                      GPIO                                                                      */
53345 } GPIO_PINCFG21_IRPTEN21_Enum;
53346 
53347 /* =============================================  GPIO PINCFG21 FNCSEL21 [0..3]  ============================================= */
53348 typedef enum {                                  /*!< GPIO_PINCFG21_FNCSEL21                                                    */
53349   GPIO_PINCFG21_FNCSEL21_SWDIO         = 0,     /*!< SWDIO : Serial Wire Debug data input/output                               */
53350   GPIO_PINCFG21_FNCSEL21_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
53351   GPIO_PINCFG21_FNCSEL21_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
53352   GPIO_PINCFG21_FNCSEL21_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53353   GPIO_PINCFG21_FNCSEL21_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
53354   GPIO_PINCFG21_FNCSEL21_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
53355   GPIO_PINCFG21_FNCSEL21_CT21          = 6,     /*!< CT21 : Timer/Counter input or output; Selection of direction
53356                                                      is done via CTIMER register settings.                                     */
53357   GPIO_PINCFG21_FNCSEL21_NCE21         = 7,     /*!< NCE21 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53358                                                      CE_POLARITY field                                                         */
53359   GPIO_PINCFG21_FNCSEL21_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
53360   GPIO_PINCFG21_FNCSEL21_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
53361   GPIO_PINCFG21_FNCSEL21_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53362   GPIO_PINCFG21_FNCSEL21_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53363   GPIO_PINCFG21_FNCSEL21_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53364   GPIO_PINCFG21_FNCSEL21_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53365   GPIO_PINCFG21_FNCSEL21_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53366   GPIO_PINCFG21_FNCSEL21_SCANSHFT      = 15,    /*!< SCANSHFT : Internal function (SCAN)                                       */
53367 } GPIO_PINCFG21_FNCSEL21_Enum;
53368 
53369 /* =======================================================  PINCFG22  ======================================================== */
53370 /* ============================================  GPIO PINCFG22 NCEPOL22 [22..22]  ============================================ */
53371 typedef enum {                                  /*!< GPIO_PINCFG22_NCEPOL22                                                    */
53372   GPIO_PINCFG22_NCEPOL22_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53373   GPIO_PINCFG22_NCEPOL22_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53374 } GPIO_PINCFG22_NCEPOL22_Enum;
53375 
53376 /* ============================================  GPIO PINCFG22 NCESRC22 [16..21]  ============================================ */
53377 typedef enum {                                  /*!< GPIO_PINCFG22_NCESRC22                                                    */
53378   GPIO_PINCFG22_NCESRC22_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53379   GPIO_PINCFG22_NCESRC22_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53380   GPIO_PINCFG22_NCESRC22_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53381   GPIO_PINCFG22_NCESRC22_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53382   GPIO_PINCFG22_NCESRC22_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53383   GPIO_PINCFG22_NCESRC22_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53384   GPIO_PINCFG22_NCESRC22_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53385   GPIO_PINCFG22_NCESRC22_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53386   GPIO_PINCFG22_NCESRC22_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53387   GPIO_PINCFG22_NCESRC22_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53388   GPIO_PINCFG22_NCESRC22_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53389   GPIO_PINCFG22_NCESRC22_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53390   GPIO_PINCFG22_NCESRC22_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53391   GPIO_PINCFG22_NCESRC22_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53392   GPIO_PINCFG22_NCESRC22_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53393   GPIO_PINCFG22_NCESRC22_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53394   GPIO_PINCFG22_NCESRC22_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53395   GPIO_PINCFG22_NCESRC22_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53396   GPIO_PINCFG22_NCESRC22_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53397   GPIO_PINCFG22_NCESRC22_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53398   GPIO_PINCFG22_NCESRC22_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53399   GPIO_PINCFG22_NCESRC22_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53400   GPIO_PINCFG22_NCESRC22_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53401   GPIO_PINCFG22_NCESRC22_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53402   GPIO_PINCFG22_NCESRC22_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53403   GPIO_PINCFG22_NCESRC22_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53404   GPIO_PINCFG22_NCESRC22_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53405   GPIO_PINCFG22_NCESRC22_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53406   GPIO_PINCFG22_NCESRC22_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53407   GPIO_PINCFG22_NCESRC22_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53408   GPIO_PINCFG22_NCESRC22_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53409   GPIO_PINCFG22_NCESRC22_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53410   GPIO_PINCFG22_NCESRC22_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53411   GPIO_PINCFG22_NCESRC22_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53412   GPIO_PINCFG22_NCESRC22_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53413   GPIO_PINCFG22_NCESRC22_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53414   GPIO_PINCFG22_NCESRC22_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53415   GPIO_PINCFG22_NCESRC22_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53416   GPIO_PINCFG22_NCESRC22_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53417   GPIO_PINCFG22_NCESRC22_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53418   GPIO_PINCFG22_NCESRC22_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53419   GPIO_PINCFG22_NCESRC22_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53420   GPIO_PINCFG22_NCESRC22_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53421 } GPIO_PINCFG22_NCESRC22_Enum;
53422 
53423 /* ===========================================  GPIO PINCFG22 PULLCFG22 [13..15]  ============================================ */
53424 typedef enum {                                  /*!< GPIO_PINCFG22_PULLCFG22                                                   */
53425   GPIO_PINCFG22_PULLCFG22_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53426   GPIO_PINCFG22_PULLCFG22_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53427   GPIO_PINCFG22_PULLCFG22_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53428   GPIO_PINCFG22_PULLCFG22_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53429   GPIO_PINCFG22_PULLCFG22_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53430   GPIO_PINCFG22_PULLCFG22_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53431   GPIO_PINCFG22_PULLCFG22_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53432   GPIO_PINCFG22_PULLCFG22_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53433 } GPIO_PINCFG22_PULLCFG22_Enum;
53434 
53435 /* ==============================================  GPIO PINCFG22 DS22 [10..11]  ============================================== */
53436 typedef enum {                                  /*!< GPIO_PINCFG22_DS22                                                        */
53437   GPIO_PINCFG22_DS22_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53438   GPIO_PINCFG22_DS22_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53439   GPIO_PINCFG22_DS22_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53440   GPIO_PINCFG22_DS22_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53441 } GPIO_PINCFG22_DS22_Enum;
53442 
53443 /* =============================================  GPIO PINCFG22 OUTCFG22 [8..9]  ============================================= */
53444 typedef enum {                                  /*!< GPIO_PINCFG22_OUTCFG22                                                    */
53445   GPIO_PINCFG22_OUTCFG22_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53446   GPIO_PINCFG22_OUTCFG22_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53447                                                      and 1 values on pin.                                                      */
53448   GPIO_PINCFG22_OUTCFG22_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53449                                                      low, tristate otherwise.                                                  */
53450   GPIO_PINCFG22_OUTCFG22_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53451                                                      drive 0, 1 of HiZ on pin.                                                 */
53452 } GPIO_PINCFG22_OUTCFG22_Enum;
53453 
53454 /* =============================================  GPIO PINCFG22 IRPTEN22 [6..7]  ============================================= */
53455 typedef enum {                                  /*!< GPIO_PINCFG22_IRPTEN22                                                    */
53456   GPIO_PINCFG22_IRPTEN22_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53457   GPIO_PINCFG22_IRPTEN22_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53458                                                      on this GPIO                                                              */
53459   GPIO_PINCFG22_IRPTEN22_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53460                                                      on this GPIO                                                              */
53461   GPIO_PINCFG22_IRPTEN22_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53462                                                      GPIO                                                                      */
53463 } GPIO_PINCFG22_IRPTEN22_Enum;
53464 
53465 /* =============================================  GPIO PINCFG22 FNCSEL22 [0..3]  ============================================= */
53466 typedef enum {                                  /*!< GPIO_PINCFG22_FNCSEL22                                                    */
53467   GPIO_PINCFG22_FNCSEL22_M7SCL         = 0,     /*!< M7SCL : Serial I2C Master Clock output (IOM 7)                            */
53468   GPIO_PINCFG22_FNCSEL22_M7SCK         = 1,     /*!< M7SCK : Serial SPI Master Clock output (IOM 7)                            */
53469   GPIO_PINCFG22_FNCSEL22_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
53470   GPIO_PINCFG22_FNCSEL22_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53471   GPIO_PINCFG22_FNCSEL22_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
53472   GPIO_PINCFG22_FNCSEL22_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
53473   GPIO_PINCFG22_FNCSEL22_CT22          = 6,     /*!< CT22 : Timer/Counter input or output; Selection of direction
53474                                                      is done via CTIMER register settings.                                     */
53475   GPIO_PINCFG22_FNCSEL22_NCE22         = 7,     /*!< NCE22 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53476                                                      CE_POLARITY field                                                         */
53477   GPIO_PINCFG22_FNCSEL22_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
53478   GPIO_PINCFG22_FNCSEL22_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
53479   GPIO_PINCFG22_FNCSEL22_I3CM1_SCL     = 10,    /*!< I3CM1_SCL : Serial I3C Master Clock output (IOM 1)                        */
53480   GPIO_PINCFG22_FNCSEL22_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53481   GPIO_PINCFG22_FNCSEL22_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53482   GPIO_PINCFG22_FNCSEL22_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53483   GPIO_PINCFG22_FNCSEL22_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53484   GPIO_PINCFG22_FNCSEL22_SCANIN3       = 15,    /*!< SCANIN3 : Internal function (SCAN)                                        */
53485 } GPIO_PINCFG22_FNCSEL22_Enum;
53486 
53487 /* =======================================================  PINCFG23  ======================================================== */
53488 /* ============================================  GPIO PINCFG23 NCEPOL23 [22..22]  ============================================ */
53489 typedef enum {                                  /*!< GPIO_PINCFG23_NCEPOL23                                                    */
53490   GPIO_PINCFG23_NCEPOL23_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53491   GPIO_PINCFG23_NCEPOL23_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53492 } GPIO_PINCFG23_NCEPOL23_Enum;
53493 
53494 /* ============================================  GPIO PINCFG23 NCESRC23 [16..21]  ============================================ */
53495 typedef enum {                                  /*!< GPIO_PINCFG23_NCESRC23                                                    */
53496   GPIO_PINCFG23_NCESRC23_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53497   GPIO_PINCFG23_NCESRC23_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53498   GPIO_PINCFG23_NCESRC23_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53499   GPIO_PINCFG23_NCESRC23_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53500   GPIO_PINCFG23_NCESRC23_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53501   GPIO_PINCFG23_NCESRC23_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53502   GPIO_PINCFG23_NCESRC23_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53503   GPIO_PINCFG23_NCESRC23_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53504   GPIO_PINCFG23_NCESRC23_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53505   GPIO_PINCFG23_NCESRC23_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53506   GPIO_PINCFG23_NCESRC23_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53507   GPIO_PINCFG23_NCESRC23_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53508   GPIO_PINCFG23_NCESRC23_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53509   GPIO_PINCFG23_NCESRC23_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53510   GPIO_PINCFG23_NCESRC23_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53511   GPIO_PINCFG23_NCESRC23_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53512   GPIO_PINCFG23_NCESRC23_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53513   GPIO_PINCFG23_NCESRC23_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53514   GPIO_PINCFG23_NCESRC23_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53515   GPIO_PINCFG23_NCESRC23_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53516   GPIO_PINCFG23_NCESRC23_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53517   GPIO_PINCFG23_NCESRC23_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53518   GPIO_PINCFG23_NCESRC23_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53519   GPIO_PINCFG23_NCESRC23_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53520   GPIO_PINCFG23_NCESRC23_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53521   GPIO_PINCFG23_NCESRC23_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53522   GPIO_PINCFG23_NCESRC23_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53523   GPIO_PINCFG23_NCESRC23_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53524   GPIO_PINCFG23_NCESRC23_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53525   GPIO_PINCFG23_NCESRC23_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53526   GPIO_PINCFG23_NCESRC23_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53527   GPIO_PINCFG23_NCESRC23_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53528   GPIO_PINCFG23_NCESRC23_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53529   GPIO_PINCFG23_NCESRC23_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53530   GPIO_PINCFG23_NCESRC23_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53531   GPIO_PINCFG23_NCESRC23_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53532   GPIO_PINCFG23_NCESRC23_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53533   GPIO_PINCFG23_NCESRC23_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53534   GPIO_PINCFG23_NCESRC23_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53535   GPIO_PINCFG23_NCESRC23_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53536   GPIO_PINCFG23_NCESRC23_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53537   GPIO_PINCFG23_NCESRC23_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53538   GPIO_PINCFG23_NCESRC23_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53539 } GPIO_PINCFG23_NCESRC23_Enum;
53540 
53541 /* ===========================================  GPIO PINCFG23 PULLCFG23 [13..15]  ============================================ */
53542 typedef enum {                                  /*!< GPIO_PINCFG23_PULLCFG23                                                   */
53543   GPIO_PINCFG23_PULLCFG23_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53544   GPIO_PINCFG23_PULLCFG23_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53545   GPIO_PINCFG23_PULLCFG23_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53546   GPIO_PINCFG23_PULLCFG23_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53547   GPIO_PINCFG23_PULLCFG23_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53548   GPIO_PINCFG23_PULLCFG23_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53549   GPIO_PINCFG23_PULLCFG23_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53550   GPIO_PINCFG23_PULLCFG23_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53551 } GPIO_PINCFG23_PULLCFG23_Enum;
53552 
53553 /* ==============================================  GPIO PINCFG23 DS23 [10..11]  ============================================== */
53554 typedef enum {                                  /*!< GPIO_PINCFG23_DS23                                                        */
53555   GPIO_PINCFG23_DS23_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53556   GPIO_PINCFG23_DS23_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53557   GPIO_PINCFG23_DS23_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53558   GPIO_PINCFG23_DS23_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53559 } GPIO_PINCFG23_DS23_Enum;
53560 
53561 /* =============================================  GPIO PINCFG23 OUTCFG23 [8..9]  ============================================= */
53562 typedef enum {                                  /*!< GPIO_PINCFG23_OUTCFG23                                                    */
53563   GPIO_PINCFG23_OUTCFG23_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53564   GPIO_PINCFG23_OUTCFG23_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53565                                                      and 1 values on pin.                                                      */
53566   GPIO_PINCFG23_OUTCFG23_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53567                                                      low, tristate otherwise.                                                  */
53568   GPIO_PINCFG23_OUTCFG23_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53569                                                      drive 0, 1 of HiZ on pin.                                                 */
53570 } GPIO_PINCFG23_OUTCFG23_Enum;
53571 
53572 /* =============================================  GPIO PINCFG23 IRPTEN23 [6..7]  ============================================= */
53573 typedef enum {                                  /*!< GPIO_PINCFG23_IRPTEN23                                                    */
53574   GPIO_PINCFG23_IRPTEN23_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53575   GPIO_PINCFG23_IRPTEN23_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53576                                                      on this GPIO                                                              */
53577   GPIO_PINCFG23_IRPTEN23_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53578                                                      on this GPIO                                                              */
53579   GPIO_PINCFG23_IRPTEN23_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53580                                                      GPIO                                                                      */
53581 } GPIO_PINCFG23_IRPTEN23_Enum;
53582 
53583 /* =============================================  GPIO PINCFG23 FNCSEL23 [0..3]  ============================================= */
53584 typedef enum {                                  /*!< GPIO_PINCFG23_FNCSEL23                                                    */
53585   GPIO_PINCFG23_FNCSEL23_M7SDAWIR3     = 0,     /*!< M7SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
53586                                                      Master Data I/O (SPI 3 wire mode) (IOM 7)                                 */
53587   GPIO_PINCFG23_FNCSEL23_M7MOSI        = 1,     /*!< M7MOSI : Serial SPI Master MOSI output (IOM 7)                            */
53588   GPIO_PINCFG23_FNCSEL23_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
53589   GPIO_PINCFG23_FNCSEL23_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53590   GPIO_PINCFG23_FNCSEL23_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
53591   GPIO_PINCFG23_FNCSEL23_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
53592   GPIO_PINCFG23_FNCSEL23_CT23          = 6,     /*!< CT23 : Timer/Counter input or output; Selection of direction
53593                                                      is done via CTIMER register settings.                                     */
53594   GPIO_PINCFG23_FNCSEL23_NCE23         = 7,     /*!< NCE23 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53595                                                      CE_POLARITY field                                                         */
53596   GPIO_PINCFG23_FNCSEL23_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
53597   GPIO_PINCFG23_FNCSEL23_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
53598   GPIO_PINCFG23_FNCSEL23_I3CM1_SDA     = 10,    /*!< I3CM1_SDA : Serial I3C Master Data I/O (IOM 1)                            */
53599   GPIO_PINCFG23_FNCSEL23_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53600   GPIO_PINCFG23_FNCSEL23_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53601   GPIO_PINCFG23_FNCSEL23_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53602   GPIO_PINCFG23_FNCSEL23_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53603   GPIO_PINCFG23_FNCSEL23_SCANOUT6      = 15,    /*!< SCANOUT6 : Internal function (SCAN)                                       */
53604 } GPIO_PINCFG23_FNCSEL23_Enum;
53605 
53606 /* =======================================================  PINCFG24  ======================================================== */
53607 /* ============================================  GPIO PINCFG24 NCEPOL24 [22..22]  ============================================ */
53608 typedef enum {                                  /*!< GPIO_PINCFG24_NCEPOL24                                                    */
53609   GPIO_PINCFG24_NCEPOL24_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53610   GPIO_PINCFG24_NCEPOL24_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53611 } GPIO_PINCFG24_NCEPOL24_Enum;
53612 
53613 /* ============================================  GPIO PINCFG24 NCESRC24 [16..21]  ============================================ */
53614 typedef enum {                                  /*!< GPIO_PINCFG24_NCESRC24                                                    */
53615   GPIO_PINCFG24_NCESRC24_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53616   GPIO_PINCFG24_NCESRC24_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53617   GPIO_PINCFG24_NCESRC24_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53618   GPIO_PINCFG24_NCESRC24_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53619   GPIO_PINCFG24_NCESRC24_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53620   GPIO_PINCFG24_NCESRC24_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53621   GPIO_PINCFG24_NCESRC24_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53622   GPIO_PINCFG24_NCESRC24_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53623   GPIO_PINCFG24_NCESRC24_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53624   GPIO_PINCFG24_NCESRC24_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53625   GPIO_PINCFG24_NCESRC24_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53626   GPIO_PINCFG24_NCESRC24_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53627   GPIO_PINCFG24_NCESRC24_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53628   GPIO_PINCFG24_NCESRC24_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53629   GPIO_PINCFG24_NCESRC24_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53630   GPIO_PINCFG24_NCESRC24_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53631   GPIO_PINCFG24_NCESRC24_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53632   GPIO_PINCFG24_NCESRC24_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53633   GPIO_PINCFG24_NCESRC24_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53634   GPIO_PINCFG24_NCESRC24_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53635   GPIO_PINCFG24_NCESRC24_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53636   GPIO_PINCFG24_NCESRC24_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53637   GPIO_PINCFG24_NCESRC24_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53638   GPIO_PINCFG24_NCESRC24_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53639   GPIO_PINCFG24_NCESRC24_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53640   GPIO_PINCFG24_NCESRC24_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53641   GPIO_PINCFG24_NCESRC24_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53642   GPIO_PINCFG24_NCESRC24_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53643   GPIO_PINCFG24_NCESRC24_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53644   GPIO_PINCFG24_NCESRC24_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53645   GPIO_PINCFG24_NCESRC24_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53646   GPIO_PINCFG24_NCESRC24_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53647   GPIO_PINCFG24_NCESRC24_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53648   GPIO_PINCFG24_NCESRC24_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53649   GPIO_PINCFG24_NCESRC24_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53650   GPIO_PINCFG24_NCESRC24_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53651   GPIO_PINCFG24_NCESRC24_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53652   GPIO_PINCFG24_NCESRC24_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53653   GPIO_PINCFG24_NCESRC24_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53654   GPIO_PINCFG24_NCESRC24_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53655   GPIO_PINCFG24_NCESRC24_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53656   GPIO_PINCFG24_NCESRC24_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53657   GPIO_PINCFG24_NCESRC24_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53658 } GPIO_PINCFG24_NCESRC24_Enum;
53659 
53660 /* ===========================================  GPIO PINCFG24 PULLCFG24 [13..15]  ============================================ */
53661 typedef enum {                                  /*!< GPIO_PINCFG24_PULLCFG24                                                   */
53662   GPIO_PINCFG24_PULLCFG24_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53663   GPIO_PINCFG24_PULLCFG24_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53664   GPIO_PINCFG24_PULLCFG24_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53665   GPIO_PINCFG24_PULLCFG24_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53666   GPIO_PINCFG24_PULLCFG24_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53667   GPIO_PINCFG24_PULLCFG24_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53668   GPIO_PINCFG24_PULLCFG24_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53669   GPIO_PINCFG24_PULLCFG24_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53670 } GPIO_PINCFG24_PULLCFG24_Enum;
53671 
53672 /* ==============================================  GPIO PINCFG24 DS24 [10..11]  ============================================== */
53673 typedef enum {                                  /*!< GPIO_PINCFG24_DS24                                                        */
53674   GPIO_PINCFG24_DS24_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53675   GPIO_PINCFG24_DS24_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53676   GPIO_PINCFG24_DS24_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53677   GPIO_PINCFG24_DS24_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53678 } GPIO_PINCFG24_DS24_Enum;
53679 
53680 /* =============================================  GPIO PINCFG24 OUTCFG24 [8..9]  ============================================= */
53681 typedef enum {                                  /*!< GPIO_PINCFG24_OUTCFG24                                                    */
53682   GPIO_PINCFG24_OUTCFG24_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53683   GPIO_PINCFG24_OUTCFG24_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53684                                                      and 1 values on pin.                                                      */
53685   GPIO_PINCFG24_OUTCFG24_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53686                                                      low, tristate otherwise.                                                  */
53687   GPIO_PINCFG24_OUTCFG24_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53688                                                      drive 0, 1 of HiZ on pin.                                                 */
53689 } GPIO_PINCFG24_OUTCFG24_Enum;
53690 
53691 /* =============================================  GPIO PINCFG24 IRPTEN24 [6..7]  ============================================= */
53692 typedef enum {                                  /*!< GPIO_PINCFG24_IRPTEN24                                                    */
53693   GPIO_PINCFG24_IRPTEN24_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53694   GPIO_PINCFG24_IRPTEN24_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53695                                                      on this GPIO                                                              */
53696   GPIO_PINCFG24_IRPTEN24_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53697                                                      on this GPIO                                                              */
53698   GPIO_PINCFG24_IRPTEN24_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53699                                                      GPIO                                                                      */
53700 } GPIO_PINCFG24_IRPTEN24_Enum;
53701 
53702 /* =============================================  GPIO PINCFG24 FNCSEL24 [0..3]  ============================================= */
53703 typedef enum {                                  /*!< GPIO_PINCFG24_FNCSEL24                                                    */
53704   GPIO_PINCFG24_FNCSEL24_M7MISO        = 0,     /*!< M7MISO : Serial SPI MASTER MISO input (IOM 7)                             */
53705   GPIO_PINCFG24_FNCSEL24_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
53706   GPIO_PINCFG24_FNCSEL24_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
53707   GPIO_PINCFG24_FNCSEL24_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53708   GPIO_PINCFG24_FNCSEL24_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
53709   GPIO_PINCFG24_FNCSEL24_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
53710   GPIO_PINCFG24_FNCSEL24_CT24          = 6,     /*!< CT24 : Timer/Counter input or output; Selection of direction
53711                                                      is done via CTIMER register settings.                                     */
53712   GPIO_PINCFG24_FNCSEL24_NCE24         = 7,     /*!< NCE24 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53713                                                      CE_POLARITY field                                                         */
53714   GPIO_PINCFG24_FNCSEL24_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
53715   GPIO_PINCFG24_FNCSEL24_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
53716   GPIO_PINCFG24_FNCSEL24_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53717   GPIO_PINCFG24_FNCSEL24_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53718   GPIO_PINCFG24_FNCSEL24_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53719   GPIO_PINCFG24_FNCSEL24_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53720   GPIO_PINCFG24_FNCSEL24_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53721   GPIO_PINCFG24_FNCSEL24_SCANOUT7      = 15,    /*!< SCANOUT7 : Internal function (SCAN)                                       */
53722 } GPIO_PINCFG24_FNCSEL24_Enum;
53723 
53724 /* =======================================================  PINCFG25  ======================================================== */
53725 /* ============================================  GPIO PINCFG25 NCEPOL25 [22..22]  ============================================ */
53726 typedef enum {                                  /*!< GPIO_PINCFG25_NCEPOL25                                                    */
53727   GPIO_PINCFG25_NCEPOL25_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53728   GPIO_PINCFG25_NCEPOL25_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53729 } GPIO_PINCFG25_NCEPOL25_Enum;
53730 
53731 /* ============================================  GPIO PINCFG25 NCESRC25 [16..21]  ============================================ */
53732 typedef enum {                                  /*!< GPIO_PINCFG25_NCESRC25                                                    */
53733   GPIO_PINCFG25_NCESRC25_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53734   GPIO_PINCFG25_NCESRC25_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53735   GPIO_PINCFG25_NCESRC25_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53736   GPIO_PINCFG25_NCESRC25_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53737   GPIO_PINCFG25_NCESRC25_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53738   GPIO_PINCFG25_NCESRC25_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53739   GPIO_PINCFG25_NCESRC25_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53740   GPIO_PINCFG25_NCESRC25_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53741   GPIO_PINCFG25_NCESRC25_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53742   GPIO_PINCFG25_NCESRC25_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53743   GPIO_PINCFG25_NCESRC25_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53744   GPIO_PINCFG25_NCESRC25_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53745   GPIO_PINCFG25_NCESRC25_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53746   GPIO_PINCFG25_NCESRC25_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53747   GPIO_PINCFG25_NCESRC25_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53748   GPIO_PINCFG25_NCESRC25_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53749   GPIO_PINCFG25_NCESRC25_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53750   GPIO_PINCFG25_NCESRC25_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53751   GPIO_PINCFG25_NCESRC25_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53752   GPIO_PINCFG25_NCESRC25_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53753   GPIO_PINCFG25_NCESRC25_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53754   GPIO_PINCFG25_NCESRC25_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53755   GPIO_PINCFG25_NCESRC25_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53756   GPIO_PINCFG25_NCESRC25_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53757   GPIO_PINCFG25_NCESRC25_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53758   GPIO_PINCFG25_NCESRC25_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53759   GPIO_PINCFG25_NCESRC25_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53760   GPIO_PINCFG25_NCESRC25_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53761   GPIO_PINCFG25_NCESRC25_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53762   GPIO_PINCFG25_NCESRC25_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53763   GPIO_PINCFG25_NCESRC25_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53764   GPIO_PINCFG25_NCESRC25_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53765   GPIO_PINCFG25_NCESRC25_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53766   GPIO_PINCFG25_NCESRC25_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53767   GPIO_PINCFG25_NCESRC25_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53768   GPIO_PINCFG25_NCESRC25_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53769   GPIO_PINCFG25_NCESRC25_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53770   GPIO_PINCFG25_NCESRC25_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53771   GPIO_PINCFG25_NCESRC25_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53772   GPIO_PINCFG25_NCESRC25_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53773   GPIO_PINCFG25_NCESRC25_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53774   GPIO_PINCFG25_NCESRC25_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53775   GPIO_PINCFG25_NCESRC25_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53776 } GPIO_PINCFG25_NCESRC25_Enum;
53777 
53778 /* ===========================================  GPIO PINCFG25 PULLCFG25 [13..15]  ============================================ */
53779 typedef enum {                                  /*!< GPIO_PINCFG25_PULLCFG25                                                   */
53780   GPIO_PINCFG25_PULLCFG25_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53781   GPIO_PINCFG25_PULLCFG25_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53782   GPIO_PINCFG25_PULLCFG25_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53783   GPIO_PINCFG25_PULLCFG25_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53784   GPIO_PINCFG25_PULLCFG25_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53785   GPIO_PINCFG25_PULLCFG25_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53786   GPIO_PINCFG25_PULLCFG25_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53787   GPIO_PINCFG25_PULLCFG25_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53788 } GPIO_PINCFG25_PULLCFG25_Enum;
53789 
53790 /* ==============================================  GPIO PINCFG25 DS25 [10..11]  ============================================== */
53791 typedef enum {                                  /*!< GPIO_PINCFG25_DS25                                                        */
53792   GPIO_PINCFG25_DS25_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53793   GPIO_PINCFG25_DS25_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53794   GPIO_PINCFG25_DS25_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53795   GPIO_PINCFG25_DS25_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53796 } GPIO_PINCFG25_DS25_Enum;
53797 
53798 /* =============================================  GPIO PINCFG25 OUTCFG25 [8..9]  ============================================= */
53799 typedef enum {                                  /*!< GPIO_PINCFG25_OUTCFG25                                                    */
53800   GPIO_PINCFG25_OUTCFG25_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53801   GPIO_PINCFG25_OUTCFG25_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53802                                                      and 1 values on pin.                                                      */
53803   GPIO_PINCFG25_OUTCFG25_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53804                                                      low, tristate otherwise.                                                  */
53805   GPIO_PINCFG25_OUTCFG25_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53806                                                      drive 0, 1 of HiZ on pin.                                                 */
53807 } GPIO_PINCFG25_OUTCFG25_Enum;
53808 
53809 /* =============================================  GPIO PINCFG25 IRPTEN25 [6..7]  ============================================= */
53810 typedef enum {                                  /*!< GPIO_PINCFG25_IRPTEN25                                                    */
53811   GPIO_PINCFG25_IRPTEN25_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53812   GPIO_PINCFG25_IRPTEN25_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53813                                                      on this GPIO                                                              */
53814   GPIO_PINCFG25_IRPTEN25_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53815                                                      on this GPIO                                                              */
53816   GPIO_PINCFG25_IRPTEN25_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53817                                                      GPIO                                                                      */
53818 } GPIO_PINCFG25_IRPTEN25_Enum;
53819 
53820 /* =============================================  GPIO PINCFG25 FNCSEL25 [0..3]  ============================================= */
53821 typedef enum {                                  /*!< GPIO_PINCFG25_FNCSEL25                                                    */
53822   GPIO_PINCFG25_FNCSEL25_M2SCL         = 0,     /*!< M2SCL : Serial I2C Master Clock output (IOM 2)                            */
53823   GPIO_PINCFG25_FNCSEL25_M2SCK         = 1,     /*!< M2SCK : Serial SPI Master Clock output (IOM 2)                            */
53824   GPIO_PINCFG25_FNCSEL25_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
53825   GPIO_PINCFG25_FNCSEL25_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53826   GPIO_PINCFG25_FNCSEL25_LFRC_EXT      = 4,     /*!< LFRC_EXT : External LFRC Clock                                            */
53827   GPIO_PINCFG25_FNCSEL25_DSP_TMS       = 5,     /*!< DSP_TMS : JTAG tms input                                                  */
53828   GPIO_PINCFG25_FNCSEL25_CT25          = 6,     /*!< CT25 : Timer/Counter input or output; Selection of direction
53829                                                      is done via CTIMER register settings.                                     */
53830   GPIO_PINCFG25_FNCSEL25_NCE25         = 7,     /*!< NCE25 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53831                                                      CE_POLARITY field                                                         */
53832   GPIO_PINCFG25_FNCSEL25_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
53833   GPIO_PINCFG25_FNCSEL25_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
53834   GPIO_PINCFG25_FNCSEL25_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53835   GPIO_PINCFG25_FNCSEL25_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53836   GPIO_PINCFG25_FNCSEL25_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53837   GPIO_PINCFG25_FNCSEL25_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53838   GPIO_PINCFG25_FNCSEL25_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53839   GPIO_PINCFG25_FNCSEL25_SCANIN8       = 15,    /*!< SCANIN8 : Internal function (SCAN)                                        */
53840 } GPIO_PINCFG25_FNCSEL25_Enum;
53841 
53842 /* =======================================================  PINCFG26  ======================================================== */
53843 /* ============================================  GPIO PINCFG26 NCEPOL26 [22..22]  ============================================ */
53844 typedef enum {                                  /*!< GPIO_PINCFG26_NCEPOL26                                                    */
53845   GPIO_PINCFG26_NCEPOL26_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53846   GPIO_PINCFG26_NCEPOL26_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53847 } GPIO_PINCFG26_NCEPOL26_Enum;
53848 
53849 /* ============================================  GPIO PINCFG26 NCESRC26 [16..21]  ============================================ */
53850 typedef enum {                                  /*!< GPIO_PINCFG26_NCESRC26                                                    */
53851   GPIO_PINCFG26_NCESRC26_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53852   GPIO_PINCFG26_NCESRC26_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53853   GPIO_PINCFG26_NCESRC26_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53854   GPIO_PINCFG26_NCESRC26_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53855   GPIO_PINCFG26_NCESRC26_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53856   GPIO_PINCFG26_NCESRC26_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53857   GPIO_PINCFG26_NCESRC26_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53858   GPIO_PINCFG26_NCESRC26_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53859   GPIO_PINCFG26_NCESRC26_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53860   GPIO_PINCFG26_NCESRC26_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53861   GPIO_PINCFG26_NCESRC26_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53862   GPIO_PINCFG26_NCESRC26_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53863   GPIO_PINCFG26_NCESRC26_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53864   GPIO_PINCFG26_NCESRC26_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53865   GPIO_PINCFG26_NCESRC26_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53866   GPIO_PINCFG26_NCESRC26_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53867   GPIO_PINCFG26_NCESRC26_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53868   GPIO_PINCFG26_NCESRC26_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53869   GPIO_PINCFG26_NCESRC26_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53870   GPIO_PINCFG26_NCESRC26_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53871   GPIO_PINCFG26_NCESRC26_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53872   GPIO_PINCFG26_NCESRC26_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53873   GPIO_PINCFG26_NCESRC26_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53874   GPIO_PINCFG26_NCESRC26_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53875   GPIO_PINCFG26_NCESRC26_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53876   GPIO_PINCFG26_NCESRC26_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53877   GPIO_PINCFG26_NCESRC26_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53878   GPIO_PINCFG26_NCESRC26_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53879   GPIO_PINCFG26_NCESRC26_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53880   GPIO_PINCFG26_NCESRC26_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
53881   GPIO_PINCFG26_NCESRC26_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
53882   GPIO_PINCFG26_NCESRC26_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
53883   GPIO_PINCFG26_NCESRC26_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
53884   GPIO_PINCFG26_NCESRC26_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
53885   GPIO_PINCFG26_NCESRC26_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
53886   GPIO_PINCFG26_NCESRC26_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
53887   GPIO_PINCFG26_NCESRC26_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
53888   GPIO_PINCFG26_NCESRC26_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
53889   GPIO_PINCFG26_NCESRC26_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
53890   GPIO_PINCFG26_NCESRC26_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
53891   GPIO_PINCFG26_NCESRC26_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
53892   GPIO_PINCFG26_NCESRC26_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
53893   GPIO_PINCFG26_NCESRC26_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
53894 } GPIO_PINCFG26_NCESRC26_Enum;
53895 
53896 /* ===========================================  GPIO PINCFG26 PULLCFG26 [13..15]  ============================================ */
53897 typedef enum {                                  /*!< GPIO_PINCFG26_PULLCFG26                                                   */
53898   GPIO_PINCFG26_PULLCFG26_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
53899   GPIO_PINCFG26_PULLCFG26_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
53900   GPIO_PINCFG26_PULLCFG26_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
53901   GPIO_PINCFG26_PULLCFG26_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
53902   GPIO_PINCFG26_PULLCFG26_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
53903   GPIO_PINCFG26_PULLCFG26_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
53904   GPIO_PINCFG26_PULLCFG26_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
53905   GPIO_PINCFG26_PULLCFG26_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
53906 } GPIO_PINCFG26_PULLCFG26_Enum;
53907 
53908 /* ==============================================  GPIO PINCFG26 DS26 [10..11]  ============================================== */
53909 typedef enum {                                  /*!< GPIO_PINCFG26_DS26                                                        */
53910   GPIO_PINCFG26_DS26_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
53911   GPIO_PINCFG26_DS26_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
53912   GPIO_PINCFG26_DS26_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
53913   GPIO_PINCFG26_DS26_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
53914 } GPIO_PINCFG26_DS26_Enum;
53915 
53916 /* =============================================  GPIO PINCFG26 OUTCFG26 [8..9]  ============================================= */
53917 typedef enum {                                  /*!< GPIO_PINCFG26_OUTCFG26                                                    */
53918   GPIO_PINCFG26_OUTCFG26_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
53919   GPIO_PINCFG26_OUTCFG26_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
53920                                                      and 1 values on pin.                                                      */
53921   GPIO_PINCFG26_OUTCFG26_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
53922                                                      low, tristate otherwise.                                                  */
53923   GPIO_PINCFG26_OUTCFG26_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
53924                                                      drive 0, 1 of HiZ on pin.                                                 */
53925 } GPIO_PINCFG26_OUTCFG26_Enum;
53926 
53927 /* =============================================  GPIO PINCFG26 IRPTEN26 [6..7]  ============================================= */
53928 typedef enum {                                  /*!< GPIO_PINCFG26_IRPTEN26                                                    */
53929   GPIO_PINCFG26_IRPTEN26_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
53930   GPIO_PINCFG26_IRPTEN26_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
53931                                                      on this GPIO                                                              */
53932   GPIO_PINCFG26_IRPTEN26_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
53933                                                      on this GPIO                                                              */
53934   GPIO_PINCFG26_IRPTEN26_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
53935                                                      GPIO                                                                      */
53936 } GPIO_PINCFG26_IRPTEN26_Enum;
53937 
53938 /* =============================================  GPIO PINCFG26 FNCSEL26 [0..3]  ============================================= */
53939 typedef enum {                                  /*!< GPIO_PINCFG26_FNCSEL26                                                    */
53940   GPIO_PINCFG26_FNCSEL26_M2SDAWIR3     = 0,     /*!< M2SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
53941                                                      Master Data I/O (SPI 3 wire mode) (IOM 2)                                 */
53942   GPIO_PINCFG26_FNCSEL26_M2MOSI        = 1,     /*!< M2MOSI : Serial SPI Master MOSI output (IOM 2)                            */
53943   GPIO_PINCFG26_FNCSEL26_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
53944   GPIO_PINCFG26_FNCSEL26_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
53945   GPIO_PINCFG26_FNCSEL26_HFRC_EXT      = 4,     /*!< HFRC_EXT : External HFRC Clock                                            */
53946   GPIO_PINCFG26_FNCSEL26_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
53947   GPIO_PINCFG26_FNCSEL26_CT26          = 6,     /*!< CT26 : Timer/Counter input or output; Selection of direction
53948                                                      is done via CTIMER register settings.                                     */
53949   GPIO_PINCFG26_FNCSEL26_NCE26         = 7,     /*!< NCE26 : IOMSTR/MSPI N Chip Select. Polarity is determined by
53950                                                      CE_POLARITY field                                                         */
53951   GPIO_PINCFG26_FNCSEL26_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
53952   GPIO_PINCFG26_FNCSEL26_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
53953   GPIO_PINCFG26_FNCSEL26_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
53954   GPIO_PINCFG26_FNCSEL26_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
53955   GPIO_PINCFG26_FNCSEL26_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
53956   GPIO_PINCFG26_FNCSEL26_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
53957   GPIO_PINCFG26_FNCSEL26_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
53958   GPIO_PINCFG26_FNCSEL26_SCANIN9       = 15,    /*!< SCANIN9 : Internal function (SCAN)                                        */
53959 } GPIO_PINCFG26_FNCSEL26_Enum;
53960 
53961 /* =======================================================  PINCFG27  ======================================================== */
53962 /* ============================================  GPIO PINCFG27 NCEPOL27 [22..22]  ============================================ */
53963 typedef enum {                                  /*!< GPIO_PINCFG27_NCEPOL27                                                    */
53964   GPIO_PINCFG27_NCEPOL27_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
53965   GPIO_PINCFG27_NCEPOL27_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
53966 } GPIO_PINCFG27_NCEPOL27_Enum;
53967 
53968 /* ============================================  GPIO PINCFG27 NCESRC27 [16..21]  ============================================ */
53969 typedef enum {                                  /*!< GPIO_PINCFG27_NCESRC27                                                    */
53970   GPIO_PINCFG27_NCESRC27_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
53971   GPIO_PINCFG27_NCESRC27_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
53972   GPIO_PINCFG27_NCESRC27_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
53973   GPIO_PINCFG27_NCESRC27_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
53974   GPIO_PINCFG27_NCESRC27_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
53975   GPIO_PINCFG27_NCESRC27_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
53976   GPIO_PINCFG27_NCESRC27_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
53977   GPIO_PINCFG27_NCESRC27_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
53978   GPIO_PINCFG27_NCESRC27_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
53979   GPIO_PINCFG27_NCESRC27_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
53980   GPIO_PINCFG27_NCESRC27_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
53981   GPIO_PINCFG27_NCESRC27_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
53982   GPIO_PINCFG27_NCESRC27_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
53983   GPIO_PINCFG27_NCESRC27_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
53984   GPIO_PINCFG27_NCESRC27_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
53985   GPIO_PINCFG27_NCESRC27_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
53986   GPIO_PINCFG27_NCESRC27_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
53987   GPIO_PINCFG27_NCESRC27_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
53988   GPIO_PINCFG27_NCESRC27_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
53989   GPIO_PINCFG27_NCESRC27_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
53990   GPIO_PINCFG27_NCESRC27_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
53991   GPIO_PINCFG27_NCESRC27_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
53992   GPIO_PINCFG27_NCESRC27_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
53993   GPIO_PINCFG27_NCESRC27_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
53994   GPIO_PINCFG27_NCESRC27_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
53995   GPIO_PINCFG27_NCESRC27_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
53996   GPIO_PINCFG27_NCESRC27_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
53997   GPIO_PINCFG27_NCESRC27_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
53998   GPIO_PINCFG27_NCESRC27_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
53999   GPIO_PINCFG27_NCESRC27_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54000   GPIO_PINCFG27_NCESRC27_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54001   GPIO_PINCFG27_NCESRC27_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54002   GPIO_PINCFG27_NCESRC27_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54003   GPIO_PINCFG27_NCESRC27_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54004   GPIO_PINCFG27_NCESRC27_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54005   GPIO_PINCFG27_NCESRC27_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54006   GPIO_PINCFG27_NCESRC27_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54007   GPIO_PINCFG27_NCESRC27_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54008   GPIO_PINCFG27_NCESRC27_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54009   GPIO_PINCFG27_NCESRC27_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54010   GPIO_PINCFG27_NCESRC27_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54011   GPIO_PINCFG27_NCESRC27_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54012   GPIO_PINCFG27_NCESRC27_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54013 } GPIO_PINCFG27_NCESRC27_Enum;
54014 
54015 /* ===========================================  GPIO PINCFG27 PULLCFG27 [13..15]  ============================================ */
54016 typedef enum {                                  /*!< GPIO_PINCFG27_PULLCFG27                                                   */
54017   GPIO_PINCFG27_PULLCFG27_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54018   GPIO_PINCFG27_PULLCFG27_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54019   GPIO_PINCFG27_PULLCFG27_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54020   GPIO_PINCFG27_PULLCFG27_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54021   GPIO_PINCFG27_PULLCFG27_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54022   GPIO_PINCFG27_PULLCFG27_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54023   GPIO_PINCFG27_PULLCFG27_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54024   GPIO_PINCFG27_PULLCFG27_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54025 } GPIO_PINCFG27_PULLCFG27_Enum;
54026 
54027 /* ==============================================  GPIO PINCFG27 DS27 [10..11]  ============================================== */
54028 typedef enum {                                  /*!< GPIO_PINCFG27_DS27                                                        */
54029   GPIO_PINCFG27_DS27_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54030   GPIO_PINCFG27_DS27_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54031   GPIO_PINCFG27_DS27_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54032   GPIO_PINCFG27_DS27_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54033 } GPIO_PINCFG27_DS27_Enum;
54034 
54035 /* =============================================  GPIO PINCFG27 OUTCFG27 [8..9]  ============================================= */
54036 typedef enum {                                  /*!< GPIO_PINCFG27_OUTCFG27                                                    */
54037   GPIO_PINCFG27_OUTCFG27_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54038   GPIO_PINCFG27_OUTCFG27_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54039                                                      and 1 values on pin.                                                      */
54040   GPIO_PINCFG27_OUTCFG27_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54041                                                      low, tristate otherwise.                                                  */
54042   GPIO_PINCFG27_OUTCFG27_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54043                                                      drive 0, 1 of HiZ on pin.                                                 */
54044 } GPIO_PINCFG27_OUTCFG27_Enum;
54045 
54046 /* =============================================  GPIO PINCFG27 IRPTEN27 [6..7]  ============================================= */
54047 typedef enum {                                  /*!< GPIO_PINCFG27_IRPTEN27                                                    */
54048   GPIO_PINCFG27_IRPTEN27_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54049   GPIO_PINCFG27_IRPTEN27_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54050                                                      on this GPIO                                                              */
54051   GPIO_PINCFG27_IRPTEN27_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54052                                                      on this GPIO                                                              */
54053   GPIO_PINCFG27_IRPTEN27_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54054                                                      GPIO                                                                      */
54055 } GPIO_PINCFG27_IRPTEN27_Enum;
54056 
54057 /* =============================================  GPIO PINCFG27 FNCSEL27 [0..3]  ============================================= */
54058 typedef enum {                                  /*!< GPIO_PINCFG27_FNCSEL27                                                    */
54059   GPIO_PINCFG27_FNCSEL27_M2MISO        = 0,     /*!< M2MISO : Serial SPI MASTER MISO input (IOM 2)                             */
54060   GPIO_PINCFG27_FNCSEL27_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
54061   GPIO_PINCFG27_FNCSEL27_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
54062   GPIO_PINCFG27_FNCSEL27_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54063   GPIO_PINCFG27_FNCSEL27_XT_EXT        = 4,     /*!< XT_EXT : External XT Clock                                                */
54064   GPIO_PINCFG27_FNCSEL27_DSP_TCK       = 5,     /*!< DSP_TCK : JTAG tck clock interface                                        */
54065   GPIO_PINCFG27_FNCSEL27_CT27          = 6,     /*!< CT27 : Timer/Counter input or output; Selection of direction
54066                                                      is done via CTIMER register settings.                                     */
54067   GPIO_PINCFG27_FNCSEL27_NCE27         = 7,     /*!< NCE27 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54068                                                      CE_POLARITY field                                                         */
54069   GPIO_PINCFG27_FNCSEL27_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
54070   GPIO_PINCFG27_FNCSEL27_I2S0_SDIN     = 9,     /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
54071   GPIO_PINCFG27_FNCSEL27_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54072   GPIO_PINCFG27_FNCSEL27_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54073   GPIO_PINCFG27_FNCSEL27_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54074   GPIO_PINCFG27_FNCSEL27_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54075   GPIO_PINCFG27_FNCSEL27_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54076   GPIO_PINCFG27_FNCSEL27_SCANIN10      = 15,    /*!< SCANIN10 : Internal function (SCAN)                                       */
54077 } GPIO_PINCFG27_FNCSEL27_Enum;
54078 
54079 /* =======================================================  PINCFG28  ======================================================== */
54080 /* ============================================  GPIO PINCFG28 NCEPOL28 [22..22]  ============================================ */
54081 typedef enum {                                  /*!< GPIO_PINCFG28_NCEPOL28                                                    */
54082   GPIO_PINCFG28_NCEPOL28_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54083   GPIO_PINCFG28_NCEPOL28_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54084 } GPIO_PINCFG28_NCEPOL28_Enum;
54085 
54086 /* ============================================  GPIO PINCFG28 NCESRC28 [16..21]  ============================================ */
54087 typedef enum {                                  /*!< GPIO_PINCFG28_NCESRC28                                                    */
54088   GPIO_PINCFG28_NCESRC28_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54089   GPIO_PINCFG28_NCESRC28_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54090   GPIO_PINCFG28_NCESRC28_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54091   GPIO_PINCFG28_NCESRC28_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54092   GPIO_PINCFG28_NCESRC28_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54093   GPIO_PINCFG28_NCESRC28_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54094   GPIO_PINCFG28_NCESRC28_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54095   GPIO_PINCFG28_NCESRC28_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54096   GPIO_PINCFG28_NCESRC28_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54097   GPIO_PINCFG28_NCESRC28_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54098   GPIO_PINCFG28_NCESRC28_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54099   GPIO_PINCFG28_NCESRC28_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54100   GPIO_PINCFG28_NCESRC28_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54101   GPIO_PINCFG28_NCESRC28_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54102   GPIO_PINCFG28_NCESRC28_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54103   GPIO_PINCFG28_NCESRC28_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54104   GPIO_PINCFG28_NCESRC28_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54105   GPIO_PINCFG28_NCESRC28_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54106   GPIO_PINCFG28_NCESRC28_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54107   GPIO_PINCFG28_NCESRC28_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54108   GPIO_PINCFG28_NCESRC28_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54109   GPIO_PINCFG28_NCESRC28_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54110   GPIO_PINCFG28_NCESRC28_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54111   GPIO_PINCFG28_NCESRC28_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54112   GPIO_PINCFG28_NCESRC28_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54113   GPIO_PINCFG28_NCESRC28_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54114   GPIO_PINCFG28_NCESRC28_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54115   GPIO_PINCFG28_NCESRC28_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54116   GPIO_PINCFG28_NCESRC28_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54117   GPIO_PINCFG28_NCESRC28_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54118   GPIO_PINCFG28_NCESRC28_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54119   GPIO_PINCFG28_NCESRC28_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54120   GPIO_PINCFG28_NCESRC28_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54121   GPIO_PINCFG28_NCESRC28_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54122   GPIO_PINCFG28_NCESRC28_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54123   GPIO_PINCFG28_NCESRC28_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54124   GPIO_PINCFG28_NCESRC28_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54125   GPIO_PINCFG28_NCESRC28_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54126   GPIO_PINCFG28_NCESRC28_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54127   GPIO_PINCFG28_NCESRC28_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54128   GPIO_PINCFG28_NCESRC28_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54129   GPIO_PINCFG28_NCESRC28_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54130   GPIO_PINCFG28_NCESRC28_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54131 } GPIO_PINCFG28_NCESRC28_Enum;
54132 
54133 /* ===========================================  GPIO PINCFG28 PULLCFG28 [13..15]  ============================================ */
54134 typedef enum {                                  /*!< GPIO_PINCFG28_PULLCFG28                                                   */
54135   GPIO_PINCFG28_PULLCFG28_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54136   GPIO_PINCFG28_PULLCFG28_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54137   GPIO_PINCFG28_PULLCFG28_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54138   GPIO_PINCFG28_PULLCFG28_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54139   GPIO_PINCFG28_PULLCFG28_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54140   GPIO_PINCFG28_PULLCFG28_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54141   GPIO_PINCFG28_PULLCFG28_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54142   GPIO_PINCFG28_PULLCFG28_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54143 } GPIO_PINCFG28_PULLCFG28_Enum;
54144 
54145 /* ==============================================  GPIO PINCFG28 DS28 [10..11]  ============================================== */
54146 typedef enum {                                  /*!< GPIO_PINCFG28_DS28                                                        */
54147   GPIO_PINCFG28_DS28_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54148   GPIO_PINCFG28_DS28_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54149 } GPIO_PINCFG28_DS28_Enum;
54150 
54151 /* =============================================  GPIO PINCFG28 OUTCFG28 [8..9]  ============================================= */
54152 typedef enum {                                  /*!< GPIO_PINCFG28_OUTCFG28                                                    */
54153   GPIO_PINCFG28_OUTCFG28_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54154   GPIO_PINCFG28_OUTCFG28_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54155                                                      and 1 values on pin.                                                      */
54156   GPIO_PINCFG28_OUTCFG28_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54157                                                      low, tristate otherwise.                                                  */
54158   GPIO_PINCFG28_OUTCFG28_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54159                                                      drive 0, 1 of HiZ on pin.                                                 */
54160 } GPIO_PINCFG28_OUTCFG28_Enum;
54161 
54162 /* =============================================  GPIO PINCFG28 IRPTEN28 [6..7]  ============================================= */
54163 typedef enum {                                  /*!< GPIO_PINCFG28_IRPTEN28                                                    */
54164   GPIO_PINCFG28_IRPTEN28_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54165   GPIO_PINCFG28_IRPTEN28_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54166                                                      on this GPIO                                                              */
54167   GPIO_PINCFG28_IRPTEN28_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54168                                                      on this GPIO                                                              */
54169   GPIO_PINCFG28_IRPTEN28_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54170                                                      GPIO                                                                      */
54171 } GPIO_PINCFG28_IRPTEN28_Enum;
54172 
54173 /* =============================================  GPIO PINCFG28 FNCSEL28 [0..3]  ============================================= */
54174 typedef enum {                                  /*!< GPIO_PINCFG28_FNCSEL28                                                    */
54175   GPIO_PINCFG28_FNCSEL28_SWO           = 0,     /*!< SWO : Serial Wire Output                                                  */
54176   GPIO_PINCFG28_FNCSEL28_VCMPO         = 1,     /*!< VCMPO : Output of the voltage comparator signal                           */
54177   GPIO_PINCFG28_FNCSEL28_I2S0_CLK      = 2,     /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
54178                                                      in master mode and input mode for slave mode. (I2S Master/Slave
54179                                                      2)                                                                        */
54180   GPIO_PINCFG28_FNCSEL28_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54181   GPIO_PINCFG28_FNCSEL28_UART2CTS      = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
54182   GPIO_PINCFG28_FNCSEL28_DSP_TDO       = 5,     /*!< DSP_TDO : JTAG tdo output                                                 */
54183   GPIO_PINCFG28_FNCSEL28_CT28          = 6,     /*!< CT28 : Timer/Counter input or output; Selection of direction
54184                                                      is done via CTIMER register settings.                                     */
54185   GPIO_PINCFG28_FNCSEL28_NCE28         = 7,     /*!< NCE28 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54186                                                      CE_POLARITY field                                                         */
54187   GPIO_PINCFG28_FNCSEL28_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
54188   GPIO_PINCFG28_FNCSEL28_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54189   GPIO_PINCFG28_FNCSEL28_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54190   GPIO_PINCFG28_FNCSEL28_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54191   GPIO_PINCFG28_FNCSEL28_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54192   GPIO_PINCFG28_FNCSEL28_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54193   GPIO_PINCFG28_FNCSEL28_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54194   GPIO_PINCFG28_FNCSEL28_CME           = 15,    /*!< CME : Internal function (SCAN)                                            */
54195 } GPIO_PINCFG28_FNCSEL28_Enum;
54196 
54197 /* =======================================================  PINCFG29  ======================================================== */
54198 /* ============================================  GPIO PINCFG29 NCEPOL29 [22..22]  ============================================ */
54199 typedef enum {                                  /*!< GPIO_PINCFG29_NCEPOL29                                                    */
54200   GPIO_PINCFG29_NCEPOL29_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54201   GPIO_PINCFG29_NCEPOL29_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54202 } GPIO_PINCFG29_NCEPOL29_Enum;
54203 
54204 /* ============================================  GPIO PINCFG29 NCESRC29 [16..21]  ============================================ */
54205 typedef enum {                                  /*!< GPIO_PINCFG29_NCESRC29                                                    */
54206   GPIO_PINCFG29_NCESRC29_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54207   GPIO_PINCFG29_NCESRC29_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54208   GPIO_PINCFG29_NCESRC29_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54209   GPIO_PINCFG29_NCESRC29_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54210   GPIO_PINCFG29_NCESRC29_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54211   GPIO_PINCFG29_NCESRC29_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54212   GPIO_PINCFG29_NCESRC29_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54213   GPIO_PINCFG29_NCESRC29_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54214   GPIO_PINCFG29_NCESRC29_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54215   GPIO_PINCFG29_NCESRC29_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54216   GPIO_PINCFG29_NCESRC29_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54217   GPIO_PINCFG29_NCESRC29_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54218   GPIO_PINCFG29_NCESRC29_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54219   GPIO_PINCFG29_NCESRC29_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54220   GPIO_PINCFG29_NCESRC29_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54221   GPIO_PINCFG29_NCESRC29_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54222   GPIO_PINCFG29_NCESRC29_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54223   GPIO_PINCFG29_NCESRC29_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54224   GPIO_PINCFG29_NCESRC29_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54225   GPIO_PINCFG29_NCESRC29_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54226   GPIO_PINCFG29_NCESRC29_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54227   GPIO_PINCFG29_NCESRC29_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54228   GPIO_PINCFG29_NCESRC29_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54229   GPIO_PINCFG29_NCESRC29_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54230   GPIO_PINCFG29_NCESRC29_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54231   GPIO_PINCFG29_NCESRC29_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54232   GPIO_PINCFG29_NCESRC29_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54233   GPIO_PINCFG29_NCESRC29_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54234   GPIO_PINCFG29_NCESRC29_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54235   GPIO_PINCFG29_NCESRC29_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54236   GPIO_PINCFG29_NCESRC29_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54237   GPIO_PINCFG29_NCESRC29_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54238   GPIO_PINCFG29_NCESRC29_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54239   GPIO_PINCFG29_NCESRC29_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54240   GPIO_PINCFG29_NCESRC29_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54241   GPIO_PINCFG29_NCESRC29_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54242   GPIO_PINCFG29_NCESRC29_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54243   GPIO_PINCFG29_NCESRC29_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54244   GPIO_PINCFG29_NCESRC29_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54245   GPIO_PINCFG29_NCESRC29_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54246   GPIO_PINCFG29_NCESRC29_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54247   GPIO_PINCFG29_NCESRC29_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54248   GPIO_PINCFG29_NCESRC29_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54249 } GPIO_PINCFG29_NCESRC29_Enum;
54250 
54251 /* ===========================================  GPIO PINCFG29 PULLCFG29 [13..15]  ============================================ */
54252 typedef enum {                                  /*!< GPIO_PINCFG29_PULLCFG29                                                   */
54253   GPIO_PINCFG29_PULLCFG29_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54254   GPIO_PINCFG29_PULLCFG29_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54255   GPIO_PINCFG29_PULLCFG29_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54256   GPIO_PINCFG29_PULLCFG29_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54257   GPIO_PINCFG29_PULLCFG29_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54258   GPIO_PINCFG29_PULLCFG29_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54259   GPIO_PINCFG29_PULLCFG29_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54260   GPIO_PINCFG29_PULLCFG29_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54261 } GPIO_PINCFG29_PULLCFG29_Enum;
54262 
54263 /* ==============================================  GPIO PINCFG29 DS29 [10..11]  ============================================== */
54264 typedef enum {                                  /*!< GPIO_PINCFG29_DS29                                                        */
54265   GPIO_PINCFG29_DS29_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54266   GPIO_PINCFG29_DS29_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54267 } GPIO_PINCFG29_DS29_Enum;
54268 
54269 /* =============================================  GPIO PINCFG29 OUTCFG29 [8..9]  ============================================= */
54270 typedef enum {                                  /*!< GPIO_PINCFG29_OUTCFG29                                                    */
54271   GPIO_PINCFG29_OUTCFG29_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54272   GPIO_PINCFG29_OUTCFG29_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54273                                                      and 1 values on pin.                                                      */
54274   GPIO_PINCFG29_OUTCFG29_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54275                                                      low, tristate otherwise.                                                  */
54276   GPIO_PINCFG29_OUTCFG29_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54277                                                      drive 0, 1 of HiZ on pin.                                                 */
54278 } GPIO_PINCFG29_OUTCFG29_Enum;
54279 
54280 /* =============================================  GPIO PINCFG29 IRPTEN29 [6..7]  ============================================= */
54281 typedef enum {                                  /*!< GPIO_PINCFG29_IRPTEN29                                                    */
54282   GPIO_PINCFG29_IRPTEN29_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54283   GPIO_PINCFG29_IRPTEN29_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54284                                                      on this GPIO                                                              */
54285   GPIO_PINCFG29_IRPTEN29_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54286                                                      on this GPIO                                                              */
54287   GPIO_PINCFG29_IRPTEN29_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54288                                                      GPIO                                                                      */
54289 } GPIO_PINCFG29_IRPTEN29_Enum;
54290 
54291 /* =============================================  GPIO PINCFG29 FNCSEL29 [0..3]  ============================================= */
54292 typedef enum {                                  /*!< GPIO_PINCFG29_FNCSEL29                                                    */
54293   GPIO_PINCFG29_FNCSEL29_TRIG0         = 0,     /*!< TRIG0 : ADC trigger input                                                 */
54294   GPIO_PINCFG29_FNCSEL29_VCMPO         = 1,     /*!< VCMPO : Output of the voltage comparator signal                           */
54295   GPIO_PINCFG29_FNCSEL29_I2S0_DATA     = 2,     /*!< I2S0_DATA : Bidirectional I2S Data. Operates in output mode
54296                                                      in master mode and input mode for slave mode. (I2S Master/Slave
54297                                                      2)                                                                        */
54298   GPIO_PINCFG29_FNCSEL29_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54299   GPIO_PINCFG29_FNCSEL29_UART1CTS      = 4,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
54300   GPIO_PINCFG29_FNCSEL29_DSP_TRSTN     = 5,     /*!< DSP_TRSTN : JTAG TRSTN input                                              */
54301   GPIO_PINCFG29_FNCSEL29_CT29          = 6,     /*!< CT29 : Timer/Counter input or output; Selection of direction
54302                                                      is done via CTIMER register settings.                                     */
54303   GPIO_PINCFG29_FNCSEL29_NCE29         = 7,     /*!< NCE29 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54304                                                      CE_POLARITY field                                                         */
54305   GPIO_PINCFG29_FNCSEL29_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
54306   GPIO_PINCFG29_FNCSEL29_I2S0_SDOUT    = 9,     /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
54307   GPIO_PINCFG29_FNCSEL29_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54308   GPIO_PINCFG29_FNCSEL29_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54309   GPIO_PINCFG29_FNCSEL29_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54310   GPIO_PINCFG29_FNCSEL29_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54311   GPIO_PINCFG29_FNCSEL29_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54312   GPIO_PINCFG29_FNCSEL29_CMLE          = 15,    /*!< CMLE : Internal function (SCAN)                                           */
54313 } GPIO_PINCFG29_FNCSEL29_Enum;
54314 
54315 /* =======================================================  PINCFG30  ======================================================== */
54316 /* ============================================  GPIO PINCFG30 NCEPOL30 [22..22]  ============================================ */
54317 typedef enum {                                  /*!< GPIO_PINCFG30_NCEPOL30                                                    */
54318   GPIO_PINCFG30_NCEPOL30_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54319   GPIO_PINCFG30_NCEPOL30_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54320 } GPIO_PINCFG30_NCEPOL30_Enum;
54321 
54322 /* ============================================  GPIO PINCFG30 NCESRC30 [16..21]  ============================================ */
54323 typedef enum {                                  /*!< GPIO_PINCFG30_NCESRC30                                                    */
54324   GPIO_PINCFG30_NCESRC30_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54325   GPIO_PINCFG30_NCESRC30_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54326   GPIO_PINCFG30_NCESRC30_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54327   GPIO_PINCFG30_NCESRC30_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54328   GPIO_PINCFG30_NCESRC30_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54329   GPIO_PINCFG30_NCESRC30_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54330   GPIO_PINCFG30_NCESRC30_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54331   GPIO_PINCFG30_NCESRC30_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54332   GPIO_PINCFG30_NCESRC30_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54333   GPIO_PINCFG30_NCESRC30_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54334   GPIO_PINCFG30_NCESRC30_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54335   GPIO_PINCFG30_NCESRC30_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54336   GPIO_PINCFG30_NCESRC30_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54337   GPIO_PINCFG30_NCESRC30_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54338   GPIO_PINCFG30_NCESRC30_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54339   GPIO_PINCFG30_NCESRC30_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54340   GPIO_PINCFG30_NCESRC30_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54341   GPIO_PINCFG30_NCESRC30_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54342   GPIO_PINCFG30_NCESRC30_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54343   GPIO_PINCFG30_NCESRC30_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54344   GPIO_PINCFG30_NCESRC30_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54345   GPIO_PINCFG30_NCESRC30_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54346   GPIO_PINCFG30_NCESRC30_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54347   GPIO_PINCFG30_NCESRC30_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54348   GPIO_PINCFG30_NCESRC30_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54349   GPIO_PINCFG30_NCESRC30_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54350   GPIO_PINCFG30_NCESRC30_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54351   GPIO_PINCFG30_NCESRC30_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54352   GPIO_PINCFG30_NCESRC30_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54353   GPIO_PINCFG30_NCESRC30_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54354   GPIO_PINCFG30_NCESRC30_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54355   GPIO_PINCFG30_NCESRC30_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54356   GPIO_PINCFG30_NCESRC30_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54357   GPIO_PINCFG30_NCESRC30_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54358   GPIO_PINCFG30_NCESRC30_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54359   GPIO_PINCFG30_NCESRC30_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54360   GPIO_PINCFG30_NCESRC30_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54361   GPIO_PINCFG30_NCESRC30_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54362   GPIO_PINCFG30_NCESRC30_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54363   GPIO_PINCFG30_NCESRC30_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54364   GPIO_PINCFG30_NCESRC30_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54365   GPIO_PINCFG30_NCESRC30_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54366   GPIO_PINCFG30_NCESRC30_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54367 } GPIO_PINCFG30_NCESRC30_Enum;
54368 
54369 /* ===========================================  GPIO PINCFG30 PULLCFG30 [13..15]  ============================================ */
54370 typedef enum {                                  /*!< GPIO_PINCFG30_PULLCFG30                                                   */
54371   GPIO_PINCFG30_PULLCFG30_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54372   GPIO_PINCFG30_PULLCFG30_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54373   GPIO_PINCFG30_PULLCFG30_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54374   GPIO_PINCFG30_PULLCFG30_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54375   GPIO_PINCFG30_PULLCFG30_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54376   GPIO_PINCFG30_PULLCFG30_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54377   GPIO_PINCFG30_PULLCFG30_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54378   GPIO_PINCFG30_PULLCFG30_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54379 } GPIO_PINCFG30_PULLCFG30_Enum;
54380 
54381 /* ==============================================  GPIO PINCFG30 DS30 [10..11]  ============================================== */
54382 typedef enum {                                  /*!< GPIO_PINCFG30_DS30                                                        */
54383   GPIO_PINCFG30_DS30_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54384   GPIO_PINCFG30_DS30_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54385 } GPIO_PINCFG30_DS30_Enum;
54386 
54387 /* =============================================  GPIO PINCFG30 OUTCFG30 [8..9]  ============================================= */
54388 typedef enum {                                  /*!< GPIO_PINCFG30_OUTCFG30                                                    */
54389   GPIO_PINCFG30_OUTCFG30_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54390   GPIO_PINCFG30_OUTCFG30_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54391                                                      and 1 values on pin.                                                      */
54392   GPIO_PINCFG30_OUTCFG30_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54393                                                      low, tristate otherwise.                                                  */
54394   GPIO_PINCFG30_OUTCFG30_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54395                                                      drive 0, 1 of HiZ on pin.                                                 */
54396 } GPIO_PINCFG30_OUTCFG30_Enum;
54397 
54398 /* =============================================  GPIO PINCFG30 IRPTEN30 [6..7]  ============================================= */
54399 typedef enum {                                  /*!< GPIO_PINCFG30_IRPTEN30                                                    */
54400   GPIO_PINCFG30_IRPTEN30_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54401   GPIO_PINCFG30_IRPTEN30_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54402                                                      on this GPIO                                                              */
54403   GPIO_PINCFG30_IRPTEN30_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54404                                                      on this GPIO                                                              */
54405   GPIO_PINCFG30_IRPTEN30_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54406                                                      GPIO                                                                      */
54407 } GPIO_PINCFG30_IRPTEN30_Enum;
54408 
54409 /* =============================================  GPIO PINCFG30 FNCSEL30 [0..3]  ============================================= */
54410 typedef enum {                                  /*!< GPIO_PINCFG30_FNCSEL30                                                    */
54411   GPIO_PINCFG30_FNCSEL30_TRIG1         = 0,     /*!< TRIG1 : ADC trigger input                                                 */
54412   GPIO_PINCFG30_FNCSEL30_VCMPO         = 1,     /*!< VCMPO : Output of the voltage comparator signal                           */
54413   GPIO_PINCFG30_FNCSEL30_I2S0_WS       = 2,     /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
54414                                                      in master mode and input mode for slave mode. (I2S Master/Slave
54415                                                      2)                                                                        */
54416   GPIO_PINCFG30_FNCSEL30_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54417   GPIO_PINCFG30_FNCSEL30_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
54418   GPIO_PINCFG30_FNCSEL30_DSP_TDI       = 5,     /*!< DSP_TDI : JTAG tdi input                                                  */
54419   GPIO_PINCFG30_FNCSEL30_CT30          = 6,     /*!< CT30 : Timer/Counter input or output; Selection of direction
54420                                                      is done via CTIMER register settings.                                     */
54421   GPIO_PINCFG30_FNCSEL30_NCE30         = 7,     /*!< NCE30 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54422                                                      CE_POLARITY field                                                         */
54423   GPIO_PINCFG30_FNCSEL30_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
54424   GPIO_PINCFG30_FNCSEL30_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54425   GPIO_PINCFG30_FNCSEL30_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54426   GPIO_PINCFG30_FNCSEL30_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54427   GPIO_PINCFG30_FNCSEL30_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54428   GPIO_PINCFG30_FNCSEL30_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54429   GPIO_PINCFG30_FNCSEL30_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54430   GPIO_PINCFG30_FNCSEL30_SCANOUT8      = 15,    /*!< SCANOUT8 : Internal function (SCAN)                                       */
54431 } GPIO_PINCFG30_FNCSEL30_Enum;
54432 
54433 /* =======================================================  PINCFG31  ======================================================== */
54434 /* ============================================  GPIO PINCFG31 NCEPOL31 [22..22]  ============================================ */
54435 typedef enum {                                  /*!< GPIO_PINCFG31_NCEPOL31                                                    */
54436   GPIO_PINCFG31_NCEPOL31_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54437   GPIO_PINCFG31_NCEPOL31_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54438 } GPIO_PINCFG31_NCEPOL31_Enum;
54439 
54440 /* ============================================  GPIO PINCFG31 NCESRC31 [16..21]  ============================================ */
54441 typedef enum {                                  /*!< GPIO_PINCFG31_NCESRC31                                                    */
54442   GPIO_PINCFG31_NCESRC31_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54443   GPIO_PINCFG31_NCESRC31_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54444   GPIO_PINCFG31_NCESRC31_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54445   GPIO_PINCFG31_NCESRC31_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54446   GPIO_PINCFG31_NCESRC31_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54447   GPIO_PINCFG31_NCESRC31_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54448   GPIO_PINCFG31_NCESRC31_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54449   GPIO_PINCFG31_NCESRC31_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54450   GPIO_PINCFG31_NCESRC31_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54451   GPIO_PINCFG31_NCESRC31_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54452   GPIO_PINCFG31_NCESRC31_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54453   GPIO_PINCFG31_NCESRC31_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54454   GPIO_PINCFG31_NCESRC31_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54455   GPIO_PINCFG31_NCESRC31_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54456   GPIO_PINCFG31_NCESRC31_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54457   GPIO_PINCFG31_NCESRC31_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54458   GPIO_PINCFG31_NCESRC31_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54459   GPIO_PINCFG31_NCESRC31_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54460   GPIO_PINCFG31_NCESRC31_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54461   GPIO_PINCFG31_NCESRC31_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54462   GPIO_PINCFG31_NCESRC31_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54463   GPIO_PINCFG31_NCESRC31_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54464   GPIO_PINCFG31_NCESRC31_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54465   GPIO_PINCFG31_NCESRC31_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54466   GPIO_PINCFG31_NCESRC31_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54467   GPIO_PINCFG31_NCESRC31_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54468   GPIO_PINCFG31_NCESRC31_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54469   GPIO_PINCFG31_NCESRC31_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54470   GPIO_PINCFG31_NCESRC31_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54471   GPIO_PINCFG31_NCESRC31_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54472   GPIO_PINCFG31_NCESRC31_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54473   GPIO_PINCFG31_NCESRC31_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54474   GPIO_PINCFG31_NCESRC31_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54475   GPIO_PINCFG31_NCESRC31_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54476   GPIO_PINCFG31_NCESRC31_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54477   GPIO_PINCFG31_NCESRC31_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54478   GPIO_PINCFG31_NCESRC31_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54479   GPIO_PINCFG31_NCESRC31_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54480   GPIO_PINCFG31_NCESRC31_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54481   GPIO_PINCFG31_NCESRC31_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54482   GPIO_PINCFG31_NCESRC31_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54483   GPIO_PINCFG31_NCESRC31_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54484   GPIO_PINCFG31_NCESRC31_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54485 } GPIO_PINCFG31_NCESRC31_Enum;
54486 
54487 /* ===========================================  GPIO PINCFG31 PULLCFG31 [13..15]  ============================================ */
54488 typedef enum {                                  /*!< GPIO_PINCFG31_PULLCFG31                                                   */
54489   GPIO_PINCFG31_PULLCFG31_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54490   GPIO_PINCFG31_PULLCFG31_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54491   GPIO_PINCFG31_PULLCFG31_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54492   GPIO_PINCFG31_PULLCFG31_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54493   GPIO_PINCFG31_PULLCFG31_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54494   GPIO_PINCFG31_PULLCFG31_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54495   GPIO_PINCFG31_PULLCFG31_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54496   GPIO_PINCFG31_PULLCFG31_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54497 } GPIO_PINCFG31_PULLCFG31_Enum;
54498 
54499 /* ==============================================  GPIO PINCFG31 DS31 [10..11]  ============================================== */
54500 typedef enum {                                  /*!< GPIO_PINCFG31_DS31                                                        */
54501   GPIO_PINCFG31_DS31_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54502   GPIO_PINCFG31_DS31_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54503   GPIO_PINCFG31_DS31_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54504   GPIO_PINCFG31_DS31_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54505 } GPIO_PINCFG31_DS31_Enum;
54506 
54507 /* =============================================  GPIO PINCFG31 OUTCFG31 [8..9]  ============================================= */
54508 typedef enum {                                  /*!< GPIO_PINCFG31_OUTCFG31                                                    */
54509   GPIO_PINCFG31_OUTCFG31_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54510   GPIO_PINCFG31_OUTCFG31_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54511                                                      and 1 values on pin.                                                      */
54512   GPIO_PINCFG31_OUTCFG31_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54513                                                      low, tristate otherwise.                                                  */
54514   GPIO_PINCFG31_OUTCFG31_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54515                                                      drive 0, 1 of HiZ on pin.                                                 */
54516 } GPIO_PINCFG31_OUTCFG31_Enum;
54517 
54518 /* =============================================  GPIO PINCFG31 IRPTEN31 [6..7]  ============================================= */
54519 typedef enum {                                  /*!< GPIO_PINCFG31_IRPTEN31                                                    */
54520   GPIO_PINCFG31_IRPTEN31_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54521   GPIO_PINCFG31_IRPTEN31_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54522                                                      on this GPIO                                                              */
54523   GPIO_PINCFG31_IRPTEN31_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54524                                                      on this GPIO                                                              */
54525   GPIO_PINCFG31_IRPTEN31_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54526                                                      GPIO                                                                      */
54527 } GPIO_PINCFG31_IRPTEN31_Enum;
54528 
54529 /* =============================================  GPIO PINCFG31 FNCSEL31 [0..3]  ============================================= */
54530 typedef enum {                                  /*!< GPIO_PINCFG31_FNCSEL31                                                    */
54531   GPIO_PINCFG31_FNCSEL31_M3SCL         = 0,     /*!< M3SCL : Serial I2C Master Clock output (IOM 3)                            */
54532   GPIO_PINCFG31_FNCSEL31_M3SCK         = 1,     /*!< M3SCK : Serial SPI Master Clock output (IOM 3)                            */
54533   GPIO_PINCFG31_FNCSEL31_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
54534   GPIO_PINCFG31_FNCSEL31_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54535   GPIO_PINCFG31_FNCSEL31_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
54536   GPIO_PINCFG31_FNCSEL31_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
54537   GPIO_PINCFG31_FNCSEL31_CT31          = 6,     /*!< CT31 : Timer/Counter input or output; Selection of direction
54538                                                      is done via CTIMER register settings.                                     */
54539   GPIO_PINCFG31_FNCSEL31_NCE31         = 7,     /*!< NCE31 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54540                                                      CE_POLARITY field                                                         */
54541   GPIO_PINCFG31_FNCSEL31_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
54542   GPIO_PINCFG31_FNCSEL31_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
54543   GPIO_PINCFG31_FNCSEL31_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54544   GPIO_PINCFG31_FNCSEL31_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54545   GPIO_PINCFG31_FNCSEL31_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54546   GPIO_PINCFG31_FNCSEL31_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54547   GPIO_PINCFG31_FNCSEL31_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54548   GPIO_PINCFG31_FNCSEL31_SCANOUT9      = 15,    /*!< SCANOUT9 : Internal function (SCAN)                                       */
54549 } GPIO_PINCFG31_FNCSEL31_Enum;
54550 
54551 /* =======================================================  PINCFG32  ======================================================== */
54552 /* ============================================  GPIO PINCFG32 NCEPOL32 [22..22]  ============================================ */
54553 typedef enum {                                  /*!< GPIO_PINCFG32_NCEPOL32                                                    */
54554   GPIO_PINCFG32_NCEPOL32_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54555   GPIO_PINCFG32_NCEPOL32_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54556 } GPIO_PINCFG32_NCEPOL32_Enum;
54557 
54558 /* ============================================  GPIO PINCFG32 NCESRC32 [16..21]  ============================================ */
54559 typedef enum {                                  /*!< GPIO_PINCFG32_NCESRC32                                                    */
54560   GPIO_PINCFG32_NCESRC32_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54561   GPIO_PINCFG32_NCESRC32_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54562   GPIO_PINCFG32_NCESRC32_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54563   GPIO_PINCFG32_NCESRC32_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54564   GPIO_PINCFG32_NCESRC32_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54565   GPIO_PINCFG32_NCESRC32_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54566   GPIO_PINCFG32_NCESRC32_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54567   GPIO_PINCFG32_NCESRC32_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54568   GPIO_PINCFG32_NCESRC32_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54569   GPIO_PINCFG32_NCESRC32_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54570   GPIO_PINCFG32_NCESRC32_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54571   GPIO_PINCFG32_NCESRC32_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54572   GPIO_PINCFG32_NCESRC32_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54573   GPIO_PINCFG32_NCESRC32_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54574   GPIO_PINCFG32_NCESRC32_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54575   GPIO_PINCFG32_NCESRC32_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54576   GPIO_PINCFG32_NCESRC32_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54577   GPIO_PINCFG32_NCESRC32_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54578   GPIO_PINCFG32_NCESRC32_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54579   GPIO_PINCFG32_NCESRC32_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54580   GPIO_PINCFG32_NCESRC32_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54581   GPIO_PINCFG32_NCESRC32_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54582   GPIO_PINCFG32_NCESRC32_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54583   GPIO_PINCFG32_NCESRC32_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54584   GPIO_PINCFG32_NCESRC32_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54585   GPIO_PINCFG32_NCESRC32_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54586   GPIO_PINCFG32_NCESRC32_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54587   GPIO_PINCFG32_NCESRC32_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54588   GPIO_PINCFG32_NCESRC32_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54589   GPIO_PINCFG32_NCESRC32_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54590   GPIO_PINCFG32_NCESRC32_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54591   GPIO_PINCFG32_NCESRC32_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54592   GPIO_PINCFG32_NCESRC32_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54593   GPIO_PINCFG32_NCESRC32_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54594   GPIO_PINCFG32_NCESRC32_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54595   GPIO_PINCFG32_NCESRC32_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54596   GPIO_PINCFG32_NCESRC32_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54597   GPIO_PINCFG32_NCESRC32_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54598   GPIO_PINCFG32_NCESRC32_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54599   GPIO_PINCFG32_NCESRC32_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54600   GPIO_PINCFG32_NCESRC32_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54601   GPIO_PINCFG32_NCESRC32_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54602   GPIO_PINCFG32_NCESRC32_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54603 } GPIO_PINCFG32_NCESRC32_Enum;
54604 
54605 /* ===========================================  GPIO PINCFG32 PULLCFG32 [13..15]  ============================================ */
54606 typedef enum {                                  /*!< GPIO_PINCFG32_PULLCFG32                                                   */
54607   GPIO_PINCFG32_PULLCFG32_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54608   GPIO_PINCFG32_PULLCFG32_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54609   GPIO_PINCFG32_PULLCFG32_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54610   GPIO_PINCFG32_PULLCFG32_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54611   GPIO_PINCFG32_PULLCFG32_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54612   GPIO_PINCFG32_PULLCFG32_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54613   GPIO_PINCFG32_PULLCFG32_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54614   GPIO_PINCFG32_PULLCFG32_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54615 } GPIO_PINCFG32_PULLCFG32_Enum;
54616 
54617 /* ==============================================  GPIO PINCFG32 DS32 [10..11]  ============================================== */
54618 typedef enum {                                  /*!< GPIO_PINCFG32_DS32                                                        */
54619   GPIO_PINCFG32_DS32_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54620   GPIO_PINCFG32_DS32_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54621   GPIO_PINCFG32_DS32_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54622   GPIO_PINCFG32_DS32_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54623 } GPIO_PINCFG32_DS32_Enum;
54624 
54625 /* =============================================  GPIO PINCFG32 OUTCFG32 [8..9]  ============================================= */
54626 typedef enum {                                  /*!< GPIO_PINCFG32_OUTCFG32                                                    */
54627   GPIO_PINCFG32_OUTCFG32_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54628   GPIO_PINCFG32_OUTCFG32_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54629                                                      and 1 values on pin.                                                      */
54630   GPIO_PINCFG32_OUTCFG32_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54631                                                      low, tristate otherwise.                                                  */
54632   GPIO_PINCFG32_OUTCFG32_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54633                                                      drive 0, 1 of HiZ on pin.                                                 */
54634 } GPIO_PINCFG32_OUTCFG32_Enum;
54635 
54636 /* =============================================  GPIO PINCFG32 IRPTEN32 [6..7]  ============================================= */
54637 typedef enum {                                  /*!< GPIO_PINCFG32_IRPTEN32                                                    */
54638   GPIO_PINCFG32_IRPTEN32_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54639   GPIO_PINCFG32_IRPTEN32_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54640                                                      on this GPIO                                                              */
54641   GPIO_PINCFG32_IRPTEN32_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54642                                                      on this GPIO                                                              */
54643   GPIO_PINCFG32_IRPTEN32_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54644                                                      GPIO                                                                      */
54645 } GPIO_PINCFG32_IRPTEN32_Enum;
54646 
54647 /* =============================================  GPIO PINCFG32 FNCSEL32 [0..3]  ============================================= */
54648 typedef enum {                                  /*!< GPIO_PINCFG32_FNCSEL32                                                    */
54649   GPIO_PINCFG32_FNCSEL32_M3SDAWIR3     = 0,     /*!< M3SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
54650                                                      Master Data I/O (SPI 3 wire mode) (IOM 3)                                 */
54651   GPIO_PINCFG32_FNCSEL32_M3MOSI        = 1,     /*!< M3MOSI : Serial SPI Master MOSI output (IOM 3)                            */
54652   GPIO_PINCFG32_FNCSEL32_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
54653   GPIO_PINCFG32_FNCSEL32_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54654   GPIO_PINCFG32_FNCSEL32_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
54655   GPIO_PINCFG32_FNCSEL32_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
54656   GPIO_PINCFG32_FNCSEL32_CT32          = 6,     /*!< CT32 : Timer/Counter input or output; Selection of direction
54657                                                      is done via CTIMER register settings.                                     */
54658   GPIO_PINCFG32_FNCSEL32_NCE32         = 7,     /*!< NCE32 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54659                                                      CE_POLARITY field                                                         */
54660   GPIO_PINCFG32_FNCSEL32_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
54661   GPIO_PINCFG32_FNCSEL32_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
54662   GPIO_PINCFG32_FNCSEL32_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54663   GPIO_PINCFG32_FNCSEL32_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54664   GPIO_PINCFG32_FNCSEL32_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54665   GPIO_PINCFG32_FNCSEL32_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54666   GPIO_PINCFG32_FNCSEL32_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54667   GPIO_PINCFG32_FNCSEL32_LPG_ENABLE    = 15,    /*!< LPG_ENABLE : Internal function (SCAN)                                     */
54668 } GPIO_PINCFG32_FNCSEL32_Enum;
54669 
54670 /* =======================================================  PINCFG33  ======================================================== */
54671 /* ============================================  GPIO PINCFG33 NCEPOL33 [22..22]  ============================================ */
54672 typedef enum {                                  /*!< GPIO_PINCFG33_NCEPOL33                                                    */
54673   GPIO_PINCFG33_NCEPOL33_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54674   GPIO_PINCFG33_NCEPOL33_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54675 } GPIO_PINCFG33_NCEPOL33_Enum;
54676 
54677 /* ============================================  GPIO PINCFG33 NCESRC33 [16..21]  ============================================ */
54678 typedef enum {                                  /*!< GPIO_PINCFG33_NCESRC33                                                    */
54679   GPIO_PINCFG33_NCESRC33_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54680   GPIO_PINCFG33_NCESRC33_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54681   GPIO_PINCFG33_NCESRC33_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54682   GPIO_PINCFG33_NCESRC33_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54683   GPIO_PINCFG33_NCESRC33_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54684   GPIO_PINCFG33_NCESRC33_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54685   GPIO_PINCFG33_NCESRC33_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54686   GPIO_PINCFG33_NCESRC33_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54687   GPIO_PINCFG33_NCESRC33_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54688   GPIO_PINCFG33_NCESRC33_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54689   GPIO_PINCFG33_NCESRC33_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54690   GPIO_PINCFG33_NCESRC33_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54691   GPIO_PINCFG33_NCESRC33_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54692   GPIO_PINCFG33_NCESRC33_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54693   GPIO_PINCFG33_NCESRC33_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54694   GPIO_PINCFG33_NCESRC33_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54695   GPIO_PINCFG33_NCESRC33_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54696   GPIO_PINCFG33_NCESRC33_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54697   GPIO_PINCFG33_NCESRC33_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54698   GPIO_PINCFG33_NCESRC33_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54699   GPIO_PINCFG33_NCESRC33_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54700   GPIO_PINCFG33_NCESRC33_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54701   GPIO_PINCFG33_NCESRC33_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54702   GPIO_PINCFG33_NCESRC33_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54703   GPIO_PINCFG33_NCESRC33_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54704   GPIO_PINCFG33_NCESRC33_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54705   GPIO_PINCFG33_NCESRC33_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54706   GPIO_PINCFG33_NCESRC33_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54707   GPIO_PINCFG33_NCESRC33_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54708   GPIO_PINCFG33_NCESRC33_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54709   GPIO_PINCFG33_NCESRC33_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54710   GPIO_PINCFG33_NCESRC33_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54711   GPIO_PINCFG33_NCESRC33_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54712   GPIO_PINCFG33_NCESRC33_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54713   GPIO_PINCFG33_NCESRC33_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54714   GPIO_PINCFG33_NCESRC33_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54715   GPIO_PINCFG33_NCESRC33_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54716   GPIO_PINCFG33_NCESRC33_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54717   GPIO_PINCFG33_NCESRC33_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54718   GPIO_PINCFG33_NCESRC33_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54719   GPIO_PINCFG33_NCESRC33_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54720   GPIO_PINCFG33_NCESRC33_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54721   GPIO_PINCFG33_NCESRC33_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54722 } GPIO_PINCFG33_NCESRC33_Enum;
54723 
54724 /* ===========================================  GPIO PINCFG33 PULLCFG33 [13..15]  ============================================ */
54725 typedef enum {                                  /*!< GPIO_PINCFG33_PULLCFG33                                                   */
54726   GPIO_PINCFG33_PULLCFG33_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54727   GPIO_PINCFG33_PULLCFG33_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54728   GPIO_PINCFG33_PULLCFG33_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54729   GPIO_PINCFG33_PULLCFG33_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54730   GPIO_PINCFG33_PULLCFG33_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54731   GPIO_PINCFG33_PULLCFG33_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54732   GPIO_PINCFG33_PULLCFG33_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54733   GPIO_PINCFG33_PULLCFG33_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54734 } GPIO_PINCFG33_PULLCFG33_Enum;
54735 
54736 /* ==============================================  GPIO PINCFG33 DS33 [10..11]  ============================================== */
54737 typedef enum {                                  /*!< GPIO_PINCFG33_DS33                                                        */
54738   GPIO_PINCFG33_DS33_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54739   GPIO_PINCFG33_DS33_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54740   GPIO_PINCFG33_DS33_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54741   GPIO_PINCFG33_DS33_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54742 } GPIO_PINCFG33_DS33_Enum;
54743 
54744 /* =============================================  GPIO PINCFG33 OUTCFG33 [8..9]  ============================================= */
54745 typedef enum {                                  /*!< GPIO_PINCFG33_OUTCFG33                                                    */
54746   GPIO_PINCFG33_OUTCFG33_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54747   GPIO_PINCFG33_OUTCFG33_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54748                                                      and 1 values on pin.                                                      */
54749   GPIO_PINCFG33_OUTCFG33_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54750                                                      low, tristate otherwise.                                                  */
54751   GPIO_PINCFG33_OUTCFG33_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54752                                                      drive 0, 1 of HiZ on pin.                                                 */
54753 } GPIO_PINCFG33_OUTCFG33_Enum;
54754 
54755 /* =============================================  GPIO PINCFG33 IRPTEN33 [6..7]  ============================================= */
54756 typedef enum {                                  /*!< GPIO_PINCFG33_IRPTEN33                                                    */
54757   GPIO_PINCFG33_IRPTEN33_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54758   GPIO_PINCFG33_IRPTEN33_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54759                                                      on this GPIO                                                              */
54760   GPIO_PINCFG33_IRPTEN33_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54761                                                      on this GPIO                                                              */
54762   GPIO_PINCFG33_IRPTEN33_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54763                                                      GPIO                                                                      */
54764 } GPIO_PINCFG33_IRPTEN33_Enum;
54765 
54766 /* =============================================  GPIO PINCFG33 FNCSEL33 [0..3]  ============================================= */
54767 typedef enum {                                  /*!< GPIO_PINCFG33_FNCSEL33                                                    */
54768   GPIO_PINCFG33_FNCSEL33_M3MISO        = 0,     /*!< M3MISO : Serial SPI MASTER MISO input (IOM 3)                             */
54769   GPIO_PINCFG33_FNCSEL33_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
54770   GPIO_PINCFG33_FNCSEL33_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
54771   GPIO_PINCFG33_FNCSEL33_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54772   GPIO_PINCFG33_FNCSEL33_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
54773   GPIO_PINCFG33_FNCSEL33_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
54774   GPIO_PINCFG33_FNCSEL33_CT33          = 6,     /*!< CT33 : Timer/Counter input or output; Selection of direction
54775                                                      is done via CTIMER register settings.                                     */
54776   GPIO_PINCFG33_FNCSEL33_NCE33         = 7,     /*!< NCE33 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54777                                                      CE_POLARITY field                                                         */
54778   GPIO_PINCFG33_FNCSEL33_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
54779   GPIO_PINCFG33_FNCSEL33_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
54780   GPIO_PINCFG33_FNCSEL33_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54781   GPIO_PINCFG33_FNCSEL33_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54782   GPIO_PINCFG33_FNCSEL33_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54783   GPIO_PINCFG33_FNCSEL33_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54784   GPIO_PINCFG33_FNCSEL33_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54785   GPIO_PINCFG33_FNCSEL33_LPG_LOAD      = 15,    /*!< LPG_LOAD : Internal function (SCAN)                                       */
54786 } GPIO_PINCFG33_FNCSEL33_Enum;
54787 
54788 /* =======================================================  PINCFG34  ======================================================== */
54789 /* ============================================  GPIO PINCFG34 NCEPOL34 [22..22]  ============================================ */
54790 typedef enum {                                  /*!< GPIO_PINCFG34_NCEPOL34                                                    */
54791   GPIO_PINCFG34_NCEPOL34_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54792   GPIO_PINCFG34_NCEPOL34_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54793 } GPIO_PINCFG34_NCEPOL34_Enum;
54794 
54795 /* ============================================  GPIO PINCFG34 NCESRC34 [16..21]  ============================================ */
54796 typedef enum {                                  /*!< GPIO_PINCFG34_NCESRC34                                                    */
54797   GPIO_PINCFG34_NCESRC34_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54798   GPIO_PINCFG34_NCESRC34_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54799   GPIO_PINCFG34_NCESRC34_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54800   GPIO_PINCFG34_NCESRC34_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54801   GPIO_PINCFG34_NCESRC34_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54802   GPIO_PINCFG34_NCESRC34_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54803   GPIO_PINCFG34_NCESRC34_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54804   GPIO_PINCFG34_NCESRC34_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54805   GPIO_PINCFG34_NCESRC34_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54806   GPIO_PINCFG34_NCESRC34_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54807   GPIO_PINCFG34_NCESRC34_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54808   GPIO_PINCFG34_NCESRC34_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54809   GPIO_PINCFG34_NCESRC34_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54810   GPIO_PINCFG34_NCESRC34_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54811   GPIO_PINCFG34_NCESRC34_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54812   GPIO_PINCFG34_NCESRC34_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54813   GPIO_PINCFG34_NCESRC34_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54814   GPIO_PINCFG34_NCESRC34_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54815   GPIO_PINCFG34_NCESRC34_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54816   GPIO_PINCFG34_NCESRC34_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54817   GPIO_PINCFG34_NCESRC34_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54818   GPIO_PINCFG34_NCESRC34_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54819   GPIO_PINCFG34_NCESRC34_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54820   GPIO_PINCFG34_NCESRC34_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54821   GPIO_PINCFG34_NCESRC34_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54822   GPIO_PINCFG34_NCESRC34_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54823   GPIO_PINCFG34_NCESRC34_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54824   GPIO_PINCFG34_NCESRC34_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54825   GPIO_PINCFG34_NCESRC34_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54826   GPIO_PINCFG34_NCESRC34_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54827   GPIO_PINCFG34_NCESRC34_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54828   GPIO_PINCFG34_NCESRC34_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54829   GPIO_PINCFG34_NCESRC34_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54830   GPIO_PINCFG34_NCESRC34_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54831   GPIO_PINCFG34_NCESRC34_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54832   GPIO_PINCFG34_NCESRC34_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54833   GPIO_PINCFG34_NCESRC34_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54834   GPIO_PINCFG34_NCESRC34_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54835   GPIO_PINCFG34_NCESRC34_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54836   GPIO_PINCFG34_NCESRC34_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54837   GPIO_PINCFG34_NCESRC34_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54838   GPIO_PINCFG34_NCESRC34_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54839   GPIO_PINCFG34_NCESRC34_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54840 } GPIO_PINCFG34_NCESRC34_Enum;
54841 
54842 /* ===========================================  GPIO PINCFG34 PULLCFG34 [13..15]  ============================================ */
54843 typedef enum {                                  /*!< GPIO_PINCFG34_PULLCFG34                                                   */
54844   GPIO_PINCFG34_PULLCFG34_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54845   GPIO_PINCFG34_PULLCFG34_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54846   GPIO_PINCFG34_PULLCFG34_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54847   GPIO_PINCFG34_PULLCFG34_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54848   GPIO_PINCFG34_PULLCFG34_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54849   GPIO_PINCFG34_PULLCFG34_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54850   GPIO_PINCFG34_PULLCFG34_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54851   GPIO_PINCFG34_PULLCFG34_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54852 } GPIO_PINCFG34_PULLCFG34_Enum;
54853 
54854 /* ==============================================  GPIO PINCFG34 DS34 [10..11]  ============================================== */
54855 typedef enum {                                  /*!< GPIO_PINCFG34_DS34                                                        */
54856   GPIO_PINCFG34_DS34_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54857   GPIO_PINCFG34_DS34_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54858   GPIO_PINCFG34_DS34_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54859   GPIO_PINCFG34_DS34_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54860 } GPIO_PINCFG34_DS34_Enum;
54861 
54862 /* =============================================  GPIO PINCFG34 OUTCFG34 [8..9]  ============================================= */
54863 typedef enum {                                  /*!< GPIO_PINCFG34_OUTCFG34                                                    */
54864   GPIO_PINCFG34_OUTCFG34_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54865   GPIO_PINCFG34_OUTCFG34_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54866                                                      and 1 values on pin.                                                      */
54867   GPIO_PINCFG34_OUTCFG34_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54868                                                      low, tristate otherwise.                                                  */
54869   GPIO_PINCFG34_OUTCFG34_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54870                                                      drive 0, 1 of HiZ on pin.                                                 */
54871 } GPIO_PINCFG34_OUTCFG34_Enum;
54872 
54873 /* =============================================  GPIO PINCFG34 IRPTEN34 [6..7]  ============================================= */
54874 typedef enum {                                  /*!< GPIO_PINCFG34_IRPTEN34                                                    */
54875   GPIO_PINCFG34_IRPTEN34_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54876   GPIO_PINCFG34_IRPTEN34_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54877                                                      on this GPIO                                                              */
54878   GPIO_PINCFG34_IRPTEN34_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54879                                                      on this GPIO                                                              */
54880   GPIO_PINCFG34_IRPTEN34_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54881                                                      GPIO                                                                      */
54882 } GPIO_PINCFG34_IRPTEN34_Enum;
54883 
54884 /* =============================================  GPIO PINCFG34 FNCSEL34 [0..3]  ============================================= */
54885 typedef enum {                                  /*!< GPIO_PINCFG34_FNCSEL34                                                    */
54886   GPIO_PINCFG34_FNCSEL34_M4SCL         = 0,     /*!< M4SCL : Serial I2C Master Clock output (IOM 4)                            */
54887   GPIO_PINCFG34_FNCSEL34_M4SCK         = 1,     /*!< M4SCK : Serial SPI Master Clock output (IOM 4)                            */
54888   GPIO_PINCFG34_FNCSEL34_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
54889   GPIO_PINCFG34_FNCSEL34_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
54890   GPIO_PINCFG34_FNCSEL34_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
54891   GPIO_PINCFG34_FNCSEL34_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
54892   GPIO_PINCFG34_FNCSEL34_CT34          = 6,     /*!< CT34 : Timer/Counter input or output; Selection of direction
54893                                                      is done via CTIMER register settings.                                     */
54894   GPIO_PINCFG34_FNCSEL34_NCE34         = 7,     /*!< NCE34 : IOMSTR/MSPI N Chip Select. Polarity is determined by
54895                                                      CE_POLARITY field                                                         */
54896   GPIO_PINCFG34_FNCSEL34_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
54897   GPIO_PINCFG34_FNCSEL34_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
54898   GPIO_PINCFG34_FNCSEL34_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
54899   GPIO_PINCFG34_FNCSEL34_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
54900   GPIO_PINCFG34_FNCSEL34_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
54901   GPIO_PINCFG34_FNCSEL34_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
54902   GPIO_PINCFG34_FNCSEL34_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
54903   GPIO_PINCFG34_FNCSEL34_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
54904 } GPIO_PINCFG34_FNCSEL34_Enum;
54905 
54906 /* =======================================================  PINCFG35  ======================================================== */
54907 /* ============================================  GPIO PINCFG35 NCEPOL35 [22..22]  ============================================ */
54908 typedef enum {                                  /*!< GPIO_PINCFG35_NCEPOL35                                                    */
54909   GPIO_PINCFG35_NCEPOL35_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
54910   GPIO_PINCFG35_NCEPOL35_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
54911 } GPIO_PINCFG35_NCEPOL35_Enum;
54912 
54913 /* ============================================  GPIO PINCFG35 NCESRC35 [16..21]  ============================================ */
54914 typedef enum {                                  /*!< GPIO_PINCFG35_NCESRC35                                                    */
54915   GPIO_PINCFG35_NCESRC35_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
54916   GPIO_PINCFG35_NCESRC35_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
54917   GPIO_PINCFG35_NCESRC35_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
54918   GPIO_PINCFG35_NCESRC35_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
54919   GPIO_PINCFG35_NCESRC35_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
54920   GPIO_PINCFG35_NCESRC35_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
54921   GPIO_PINCFG35_NCESRC35_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
54922   GPIO_PINCFG35_NCESRC35_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
54923   GPIO_PINCFG35_NCESRC35_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
54924   GPIO_PINCFG35_NCESRC35_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
54925   GPIO_PINCFG35_NCESRC35_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
54926   GPIO_PINCFG35_NCESRC35_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
54927   GPIO_PINCFG35_NCESRC35_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
54928   GPIO_PINCFG35_NCESRC35_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
54929   GPIO_PINCFG35_NCESRC35_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
54930   GPIO_PINCFG35_NCESRC35_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
54931   GPIO_PINCFG35_NCESRC35_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
54932   GPIO_PINCFG35_NCESRC35_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
54933   GPIO_PINCFG35_NCESRC35_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
54934   GPIO_PINCFG35_NCESRC35_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
54935   GPIO_PINCFG35_NCESRC35_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
54936   GPIO_PINCFG35_NCESRC35_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
54937   GPIO_PINCFG35_NCESRC35_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
54938   GPIO_PINCFG35_NCESRC35_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
54939   GPIO_PINCFG35_NCESRC35_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
54940   GPIO_PINCFG35_NCESRC35_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
54941   GPIO_PINCFG35_NCESRC35_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
54942   GPIO_PINCFG35_NCESRC35_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
54943   GPIO_PINCFG35_NCESRC35_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
54944   GPIO_PINCFG35_NCESRC35_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
54945   GPIO_PINCFG35_NCESRC35_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
54946   GPIO_PINCFG35_NCESRC35_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
54947   GPIO_PINCFG35_NCESRC35_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
54948   GPIO_PINCFG35_NCESRC35_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
54949   GPIO_PINCFG35_NCESRC35_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
54950   GPIO_PINCFG35_NCESRC35_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
54951   GPIO_PINCFG35_NCESRC35_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
54952   GPIO_PINCFG35_NCESRC35_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
54953   GPIO_PINCFG35_NCESRC35_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
54954   GPIO_PINCFG35_NCESRC35_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
54955   GPIO_PINCFG35_NCESRC35_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
54956   GPIO_PINCFG35_NCESRC35_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
54957   GPIO_PINCFG35_NCESRC35_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
54958 } GPIO_PINCFG35_NCESRC35_Enum;
54959 
54960 /* ===========================================  GPIO PINCFG35 PULLCFG35 [13..15]  ============================================ */
54961 typedef enum {                                  /*!< GPIO_PINCFG35_PULLCFG35                                                   */
54962   GPIO_PINCFG35_PULLCFG35_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
54963   GPIO_PINCFG35_PULLCFG35_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
54964   GPIO_PINCFG35_PULLCFG35_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
54965   GPIO_PINCFG35_PULLCFG35_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
54966   GPIO_PINCFG35_PULLCFG35_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
54967   GPIO_PINCFG35_PULLCFG35_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
54968   GPIO_PINCFG35_PULLCFG35_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
54969   GPIO_PINCFG35_PULLCFG35_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
54970 } GPIO_PINCFG35_PULLCFG35_Enum;
54971 
54972 /* ==============================================  GPIO PINCFG35 DS35 [10..11]  ============================================== */
54973 typedef enum {                                  /*!< GPIO_PINCFG35_DS35                                                        */
54974   GPIO_PINCFG35_DS35_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
54975   GPIO_PINCFG35_DS35_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
54976   GPIO_PINCFG35_DS35_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
54977   GPIO_PINCFG35_DS35_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
54978 } GPIO_PINCFG35_DS35_Enum;
54979 
54980 /* =============================================  GPIO PINCFG35 OUTCFG35 [8..9]  ============================================= */
54981 typedef enum {                                  /*!< GPIO_PINCFG35_OUTCFG35                                                    */
54982   GPIO_PINCFG35_OUTCFG35_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
54983   GPIO_PINCFG35_OUTCFG35_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
54984                                                      and 1 values on pin.                                                      */
54985   GPIO_PINCFG35_OUTCFG35_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
54986                                                      low, tristate otherwise.                                                  */
54987   GPIO_PINCFG35_OUTCFG35_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
54988                                                      drive 0, 1 of HiZ on pin.                                                 */
54989 } GPIO_PINCFG35_OUTCFG35_Enum;
54990 
54991 /* =============================================  GPIO PINCFG35 IRPTEN35 [6..7]  ============================================= */
54992 typedef enum {                                  /*!< GPIO_PINCFG35_IRPTEN35                                                    */
54993   GPIO_PINCFG35_IRPTEN35_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
54994   GPIO_PINCFG35_IRPTEN35_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
54995                                                      on this GPIO                                                              */
54996   GPIO_PINCFG35_IRPTEN35_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
54997                                                      on this GPIO                                                              */
54998   GPIO_PINCFG35_IRPTEN35_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
54999                                                      GPIO                                                                      */
55000 } GPIO_PINCFG35_IRPTEN35_Enum;
55001 
55002 /* =============================================  GPIO PINCFG35 FNCSEL35 [0..3]  ============================================= */
55003 typedef enum {                                  /*!< GPIO_PINCFG35_FNCSEL35                                                    */
55004   GPIO_PINCFG35_FNCSEL35_M4SDAWIR3     = 0,     /*!< M4SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
55005                                                      Master Data I/O (SPI 3 wire mode) (IOM 4)                                 */
55006   GPIO_PINCFG35_FNCSEL35_M4MOSI        = 1,     /*!< M4MOSI : Serial SPI Master MOSI output (IOM 4)                            */
55007   GPIO_PINCFG35_FNCSEL35_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
55008   GPIO_PINCFG35_FNCSEL35_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55009   GPIO_PINCFG35_FNCSEL35_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
55010   GPIO_PINCFG35_FNCSEL35_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
55011   GPIO_PINCFG35_FNCSEL35_CT35          = 6,     /*!< CT35 : Timer/Counter input or output; Selection of direction
55012                                                      is done via CTIMER register settings.                                     */
55013   GPIO_PINCFG35_FNCSEL35_NCE35         = 7,     /*!< NCE35 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55014                                                      CE_POLARITY field                                                         */
55015   GPIO_PINCFG35_FNCSEL35_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
55016   GPIO_PINCFG35_FNCSEL35_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
55017   GPIO_PINCFG35_FNCSEL35_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55018   GPIO_PINCFG35_FNCSEL35_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55019   GPIO_PINCFG35_FNCSEL35_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55020   GPIO_PINCFG35_FNCSEL35_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55021   GPIO_PINCFG35_FNCSEL35_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55022   GPIO_PINCFG35_FNCSEL35_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55023 } GPIO_PINCFG35_FNCSEL35_Enum;
55024 
55025 /* =======================================================  PINCFG36  ======================================================== */
55026 /* ============================================  GPIO PINCFG36 NCEPOL36 [22..22]  ============================================ */
55027 typedef enum {                                  /*!< GPIO_PINCFG36_NCEPOL36                                                    */
55028   GPIO_PINCFG36_NCEPOL36_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55029   GPIO_PINCFG36_NCEPOL36_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55030 } GPIO_PINCFG36_NCEPOL36_Enum;
55031 
55032 /* ============================================  GPIO PINCFG36 NCESRC36 [16..21]  ============================================ */
55033 typedef enum {                                  /*!< GPIO_PINCFG36_NCESRC36                                                    */
55034   GPIO_PINCFG36_NCESRC36_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55035   GPIO_PINCFG36_NCESRC36_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55036   GPIO_PINCFG36_NCESRC36_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55037   GPIO_PINCFG36_NCESRC36_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55038   GPIO_PINCFG36_NCESRC36_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55039   GPIO_PINCFG36_NCESRC36_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55040   GPIO_PINCFG36_NCESRC36_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55041   GPIO_PINCFG36_NCESRC36_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55042   GPIO_PINCFG36_NCESRC36_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55043   GPIO_PINCFG36_NCESRC36_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55044   GPIO_PINCFG36_NCESRC36_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55045   GPIO_PINCFG36_NCESRC36_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55046   GPIO_PINCFG36_NCESRC36_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55047   GPIO_PINCFG36_NCESRC36_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55048   GPIO_PINCFG36_NCESRC36_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55049   GPIO_PINCFG36_NCESRC36_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55050   GPIO_PINCFG36_NCESRC36_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55051   GPIO_PINCFG36_NCESRC36_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55052   GPIO_PINCFG36_NCESRC36_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55053   GPIO_PINCFG36_NCESRC36_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55054   GPIO_PINCFG36_NCESRC36_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55055   GPIO_PINCFG36_NCESRC36_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55056   GPIO_PINCFG36_NCESRC36_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55057   GPIO_PINCFG36_NCESRC36_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55058   GPIO_PINCFG36_NCESRC36_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55059   GPIO_PINCFG36_NCESRC36_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55060   GPIO_PINCFG36_NCESRC36_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55061   GPIO_PINCFG36_NCESRC36_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55062   GPIO_PINCFG36_NCESRC36_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55063   GPIO_PINCFG36_NCESRC36_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55064   GPIO_PINCFG36_NCESRC36_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55065   GPIO_PINCFG36_NCESRC36_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55066   GPIO_PINCFG36_NCESRC36_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55067   GPIO_PINCFG36_NCESRC36_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55068   GPIO_PINCFG36_NCESRC36_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55069   GPIO_PINCFG36_NCESRC36_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55070   GPIO_PINCFG36_NCESRC36_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55071   GPIO_PINCFG36_NCESRC36_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55072   GPIO_PINCFG36_NCESRC36_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55073   GPIO_PINCFG36_NCESRC36_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55074   GPIO_PINCFG36_NCESRC36_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55075   GPIO_PINCFG36_NCESRC36_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55076   GPIO_PINCFG36_NCESRC36_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55077 } GPIO_PINCFG36_NCESRC36_Enum;
55078 
55079 /* ===========================================  GPIO PINCFG36 PULLCFG36 [13..15]  ============================================ */
55080 typedef enum {                                  /*!< GPIO_PINCFG36_PULLCFG36                                                   */
55081   GPIO_PINCFG36_PULLCFG36_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55082   GPIO_PINCFG36_PULLCFG36_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55083   GPIO_PINCFG36_PULLCFG36_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55084   GPIO_PINCFG36_PULLCFG36_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55085   GPIO_PINCFG36_PULLCFG36_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55086   GPIO_PINCFG36_PULLCFG36_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55087   GPIO_PINCFG36_PULLCFG36_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55088   GPIO_PINCFG36_PULLCFG36_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55089 } GPIO_PINCFG36_PULLCFG36_Enum;
55090 
55091 /* ==============================================  GPIO PINCFG36 DS36 [10..11]  ============================================== */
55092 typedef enum {                                  /*!< GPIO_PINCFG36_DS36                                                        */
55093   GPIO_PINCFG36_DS36_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55094   GPIO_PINCFG36_DS36_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55095   GPIO_PINCFG36_DS36_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55096   GPIO_PINCFG36_DS36_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55097 } GPIO_PINCFG36_DS36_Enum;
55098 
55099 /* =============================================  GPIO PINCFG36 OUTCFG36 [8..9]  ============================================= */
55100 typedef enum {                                  /*!< GPIO_PINCFG36_OUTCFG36                                                    */
55101   GPIO_PINCFG36_OUTCFG36_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55102   GPIO_PINCFG36_OUTCFG36_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55103                                                      and 1 values on pin.                                                      */
55104   GPIO_PINCFG36_OUTCFG36_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55105                                                      low, tristate otherwise.                                                  */
55106   GPIO_PINCFG36_OUTCFG36_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55107                                                      drive 0, 1 of HiZ on pin.                                                 */
55108 } GPIO_PINCFG36_OUTCFG36_Enum;
55109 
55110 /* =============================================  GPIO PINCFG36 IRPTEN36 [6..7]  ============================================= */
55111 typedef enum {                                  /*!< GPIO_PINCFG36_IRPTEN36                                                    */
55112   GPIO_PINCFG36_IRPTEN36_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55113   GPIO_PINCFG36_IRPTEN36_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55114                                                      on this GPIO                                                              */
55115   GPIO_PINCFG36_IRPTEN36_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55116                                                      on this GPIO                                                              */
55117   GPIO_PINCFG36_IRPTEN36_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55118                                                      GPIO                                                                      */
55119 } GPIO_PINCFG36_IRPTEN36_Enum;
55120 
55121 /* =============================================  GPIO PINCFG36 FNCSEL36 [0..3]  ============================================= */
55122 typedef enum {                                  /*!< GPIO_PINCFG36_FNCSEL36                                                    */
55123   GPIO_PINCFG36_FNCSEL36_M4MISO        = 0,     /*!< M4MISO : Serial SPI MASTER MISO input (IOM 4)                             */
55124   GPIO_PINCFG36_FNCSEL36_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
55125   GPIO_PINCFG36_FNCSEL36_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
55126   GPIO_PINCFG36_FNCSEL36_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55127   GPIO_PINCFG36_FNCSEL36_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
55128   GPIO_PINCFG36_FNCSEL36_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
55129   GPIO_PINCFG36_FNCSEL36_CT36          = 6,     /*!< CT36 : Timer/Counter input or output; Selection of direction
55130                                                      is done via CTIMER register settings.                                     */
55131   GPIO_PINCFG36_FNCSEL36_NCE36         = 7,     /*!< NCE36 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55132                                                      CE_POLARITY field                                                         */
55133   GPIO_PINCFG36_FNCSEL36_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
55134   GPIO_PINCFG36_FNCSEL36_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55135   GPIO_PINCFG36_FNCSEL36_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55136   GPIO_PINCFG36_FNCSEL36_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55137   GPIO_PINCFG36_FNCSEL36_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55138   GPIO_PINCFG36_FNCSEL36_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55139   GPIO_PINCFG36_FNCSEL36_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55140   GPIO_PINCFG36_FNCSEL36_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55141 } GPIO_PINCFG36_FNCSEL36_Enum;
55142 
55143 /* =======================================================  PINCFG37  ======================================================== */
55144 /* ============================================  GPIO PINCFG37 NCEPOL37 [22..22]  ============================================ */
55145 typedef enum {                                  /*!< GPIO_PINCFG37_NCEPOL37                                                    */
55146   GPIO_PINCFG37_NCEPOL37_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55147   GPIO_PINCFG37_NCEPOL37_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55148 } GPIO_PINCFG37_NCEPOL37_Enum;
55149 
55150 /* ============================================  GPIO PINCFG37 NCESRC37 [16..21]  ============================================ */
55151 typedef enum {                                  /*!< GPIO_PINCFG37_NCESRC37                                                    */
55152   GPIO_PINCFG37_NCESRC37_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55153   GPIO_PINCFG37_NCESRC37_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55154   GPIO_PINCFG37_NCESRC37_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55155   GPIO_PINCFG37_NCESRC37_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55156   GPIO_PINCFG37_NCESRC37_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55157   GPIO_PINCFG37_NCESRC37_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55158   GPIO_PINCFG37_NCESRC37_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55159   GPIO_PINCFG37_NCESRC37_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55160   GPIO_PINCFG37_NCESRC37_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55161   GPIO_PINCFG37_NCESRC37_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55162   GPIO_PINCFG37_NCESRC37_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55163   GPIO_PINCFG37_NCESRC37_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55164   GPIO_PINCFG37_NCESRC37_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55165   GPIO_PINCFG37_NCESRC37_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55166   GPIO_PINCFG37_NCESRC37_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55167   GPIO_PINCFG37_NCESRC37_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55168   GPIO_PINCFG37_NCESRC37_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55169   GPIO_PINCFG37_NCESRC37_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55170   GPIO_PINCFG37_NCESRC37_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55171   GPIO_PINCFG37_NCESRC37_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55172   GPIO_PINCFG37_NCESRC37_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55173   GPIO_PINCFG37_NCESRC37_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55174   GPIO_PINCFG37_NCESRC37_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55175   GPIO_PINCFG37_NCESRC37_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55176   GPIO_PINCFG37_NCESRC37_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55177   GPIO_PINCFG37_NCESRC37_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55178   GPIO_PINCFG37_NCESRC37_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55179   GPIO_PINCFG37_NCESRC37_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55180   GPIO_PINCFG37_NCESRC37_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55181   GPIO_PINCFG37_NCESRC37_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55182   GPIO_PINCFG37_NCESRC37_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55183   GPIO_PINCFG37_NCESRC37_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55184   GPIO_PINCFG37_NCESRC37_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55185   GPIO_PINCFG37_NCESRC37_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55186   GPIO_PINCFG37_NCESRC37_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55187   GPIO_PINCFG37_NCESRC37_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55188   GPIO_PINCFG37_NCESRC37_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55189   GPIO_PINCFG37_NCESRC37_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55190   GPIO_PINCFG37_NCESRC37_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55191   GPIO_PINCFG37_NCESRC37_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55192   GPIO_PINCFG37_NCESRC37_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55193   GPIO_PINCFG37_NCESRC37_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55194   GPIO_PINCFG37_NCESRC37_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55195 } GPIO_PINCFG37_NCESRC37_Enum;
55196 
55197 /* ===========================================  GPIO PINCFG37 PULLCFG37 [13..15]  ============================================ */
55198 typedef enum {                                  /*!< GPIO_PINCFG37_PULLCFG37                                                   */
55199   GPIO_PINCFG37_PULLCFG37_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55200   GPIO_PINCFG37_PULLCFG37_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55201   GPIO_PINCFG37_PULLCFG37_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55202   GPIO_PINCFG37_PULLCFG37_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55203   GPIO_PINCFG37_PULLCFG37_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55204   GPIO_PINCFG37_PULLCFG37_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55205   GPIO_PINCFG37_PULLCFG37_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55206   GPIO_PINCFG37_PULLCFG37_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55207 } GPIO_PINCFG37_PULLCFG37_Enum;
55208 
55209 /* ==============================================  GPIO PINCFG37 DS37 [10..11]  ============================================== */
55210 typedef enum {                                  /*!< GPIO_PINCFG37_DS37                                                        */
55211   GPIO_PINCFG37_DS37_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55212   GPIO_PINCFG37_DS37_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55213   GPIO_PINCFG37_DS37_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55214   GPIO_PINCFG37_DS37_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55215 } GPIO_PINCFG37_DS37_Enum;
55216 
55217 /* =============================================  GPIO PINCFG37 OUTCFG37 [8..9]  ============================================= */
55218 typedef enum {                                  /*!< GPIO_PINCFG37_OUTCFG37                                                    */
55219   GPIO_PINCFG37_OUTCFG37_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55220   GPIO_PINCFG37_OUTCFG37_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55221                                                      and 1 values on pin.                                                      */
55222   GPIO_PINCFG37_OUTCFG37_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55223                                                      low, tristate otherwise.                                                  */
55224   GPIO_PINCFG37_OUTCFG37_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55225                                                      drive 0, 1 of HiZ on pin.                                                 */
55226 } GPIO_PINCFG37_OUTCFG37_Enum;
55227 
55228 /* =============================================  GPIO PINCFG37 IRPTEN37 [6..7]  ============================================= */
55229 typedef enum {                                  /*!< GPIO_PINCFG37_IRPTEN37                                                    */
55230   GPIO_PINCFG37_IRPTEN37_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55231   GPIO_PINCFG37_IRPTEN37_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55232                                                      on this GPIO                                                              */
55233   GPIO_PINCFG37_IRPTEN37_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55234                                                      on this GPIO                                                              */
55235   GPIO_PINCFG37_IRPTEN37_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55236                                                      GPIO                                                                      */
55237 } GPIO_PINCFG37_IRPTEN37_Enum;
55238 
55239 /* =============================================  GPIO PINCFG37 FNCSEL37 [0..3]  ============================================= */
55240 typedef enum {                                  /*!< GPIO_PINCFG37_FNCSEL37                                                    */
55241   GPIO_PINCFG37_FNCSEL37_MSPI1_0       = 0,     /*!< MSPI1_0 : MSPI Master 1 Interface Signal                                  */
55242   GPIO_PINCFG37_FNCSEL37_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
55243   GPIO_PINCFG37_FNCSEL37_32KHzXT       = 2,     /*!< 32KHzXT : 32kHZ from analog                                               */
55244   GPIO_PINCFG37_FNCSEL37_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55245   GPIO_PINCFG37_FNCSEL37_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
55246   GPIO_PINCFG37_FNCSEL37_DISP_D15      = 5,     /*!< DISP_D15 : Display Data 15                                                */
55247   GPIO_PINCFG37_FNCSEL37_CT37          = 6,     /*!< CT37 : Timer/Counter input or output; Selection of direction
55248                                                      is done via CTIMER register settings.                                     */
55249   GPIO_PINCFG37_FNCSEL37_NCE37         = 7,     /*!< NCE37 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55250                                                      CE_POLARITY field                                                         */
55251   GPIO_PINCFG37_FNCSEL37_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
55252   GPIO_PINCFG37_FNCSEL37_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55253   GPIO_PINCFG37_FNCSEL37_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55254   GPIO_PINCFG37_FNCSEL37_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55255   GPIO_PINCFG37_FNCSEL37_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55256   GPIO_PINCFG37_FNCSEL37_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55257   GPIO_PINCFG37_FNCSEL37_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55258   GPIO_PINCFG37_FNCSEL37_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55259 } GPIO_PINCFG37_FNCSEL37_Enum;
55260 
55261 /* =======================================================  PINCFG38  ======================================================== */
55262 /* ============================================  GPIO PINCFG38 NCEPOL38 [22..22]  ============================================ */
55263 typedef enum {                                  /*!< GPIO_PINCFG38_NCEPOL38                                                    */
55264   GPIO_PINCFG38_NCEPOL38_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55265   GPIO_PINCFG38_NCEPOL38_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55266 } GPIO_PINCFG38_NCEPOL38_Enum;
55267 
55268 /* ============================================  GPIO PINCFG38 NCESRC38 [16..21]  ============================================ */
55269 typedef enum {                                  /*!< GPIO_PINCFG38_NCESRC38                                                    */
55270   GPIO_PINCFG38_NCESRC38_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55271   GPIO_PINCFG38_NCESRC38_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55272   GPIO_PINCFG38_NCESRC38_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55273   GPIO_PINCFG38_NCESRC38_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55274   GPIO_PINCFG38_NCESRC38_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55275   GPIO_PINCFG38_NCESRC38_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55276   GPIO_PINCFG38_NCESRC38_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55277   GPIO_PINCFG38_NCESRC38_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55278   GPIO_PINCFG38_NCESRC38_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55279   GPIO_PINCFG38_NCESRC38_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55280   GPIO_PINCFG38_NCESRC38_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55281   GPIO_PINCFG38_NCESRC38_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55282   GPIO_PINCFG38_NCESRC38_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55283   GPIO_PINCFG38_NCESRC38_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55284   GPIO_PINCFG38_NCESRC38_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55285   GPIO_PINCFG38_NCESRC38_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55286   GPIO_PINCFG38_NCESRC38_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55287   GPIO_PINCFG38_NCESRC38_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55288   GPIO_PINCFG38_NCESRC38_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55289   GPIO_PINCFG38_NCESRC38_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55290   GPIO_PINCFG38_NCESRC38_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55291   GPIO_PINCFG38_NCESRC38_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55292   GPIO_PINCFG38_NCESRC38_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55293   GPIO_PINCFG38_NCESRC38_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55294   GPIO_PINCFG38_NCESRC38_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55295   GPIO_PINCFG38_NCESRC38_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55296   GPIO_PINCFG38_NCESRC38_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55297   GPIO_PINCFG38_NCESRC38_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55298   GPIO_PINCFG38_NCESRC38_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55299   GPIO_PINCFG38_NCESRC38_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55300   GPIO_PINCFG38_NCESRC38_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55301   GPIO_PINCFG38_NCESRC38_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55302   GPIO_PINCFG38_NCESRC38_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55303   GPIO_PINCFG38_NCESRC38_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55304   GPIO_PINCFG38_NCESRC38_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55305   GPIO_PINCFG38_NCESRC38_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55306   GPIO_PINCFG38_NCESRC38_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55307   GPIO_PINCFG38_NCESRC38_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55308   GPIO_PINCFG38_NCESRC38_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55309   GPIO_PINCFG38_NCESRC38_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55310   GPIO_PINCFG38_NCESRC38_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55311   GPIO_PINCFG38_NCESRC38_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55312   GPIO_PINCFG38_NCESRC38_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55313 } GPIO_PINCFG38_NCESRC38_Enum;
55314 
55315 /* ===========================================  GPIO PINCFG38 PULLCFG38 [13..15]  ============================================ */
55316 typedef enum {                                  /*!< GPIO_PINCFG38_PULLCFG38                                                   */
55317   GPIO_PINCFG38_PULLCFG38_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55318   GPIO_PINCFG38_PULLCFG38_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55319   GPIO_PINCFG38_PULLCFG38_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55320   GPIO_PINCFG38_PULLCFG38_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55321   GPIO_PINCFG38_PULLCFG38_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55322   GPIO_PINCFG38_PULLCFG38_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55323   GPIO_PINCFG38_PULLCFG38_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55324   GPIO_PINCFG38_PULLCFG38_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55325 } GPIO_PINCFG38_PULLCFG38_Enum;
55326 
55327 /* ==============================================  GPIO PINCFG38 DS38 [10..11]  ============================================== */
55328 typedef enum {                                  /*!< GPIO_PINCFG38_DS38                                                        */
55329   GPIO_PINCFG38_DS38_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55330   GPIO_PINCFG38_DS38_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55331   GPIO_PINCFG38_DS38_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55332   GPIO_PINCFG38_DS38_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55333 } GPIO_PINCFG38_DS38_Enum;
55334 
55335 /* =============================================  GPIO PINCFG38 OUTCFG38 [8..9]  ============================================= */
55336 typedef enum {                                  /*!< GPIO_PINCFG38_OUTCFG38                                                    */
55337   GPIO_PINCFG38_OUTCFG38_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55338   GPIO_PINCFG38_OUTCFG38_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55339                                                      and 1 values on pin.                                                      */
55340   GPIO_PINCFG38_OUTCFG38_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55341                                                      low, tristate otherwise.                                                  */
55342   GPIO_PINCFG38_OUTCFG38_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55343                                                      drive 0, 1 of HiZ on pin.                                                 */
55344 } GPIO_PINCFG38_OUTCFG38_Enum;
55345 
55346 /* =============================================  GPIO PINCFG38 IRPTEN38 [6..7]  ============================================= */
55347 typedef enum {                                  /*!< GPIO_PINCFG38_IRPTEN38                                                    */
55348   GPIO_PINCFG38_IRPTEN38_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55349   GPIO_PINCFG38_IRPTEN38_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55350                                                      on this GPIO                                                              */
55351   GPIO_PINCFG38_IRPTEN38_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55352                                                      on this GPIO                                                              */
55353   GPIO_PINCFG38_IRPTEN38_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55354                                                      GPIO                                                                      */
55355 } GPIO_PINCFG38_IRPTEN38_Enum;
55356 
55357 /* =============================================  GPIO PINCFG38 FNCSEL38 [0..3]  ============================================= */
55358 typedef enum {                                  /*!< GPIO_PINCFG38_FNCSEL38                                                    */
55359   GPIO_PINCFG38_FNCSEL38_MSPI1_1       = 0,     /*!< MSPI1_1 : MSPI Master 1 Interface Signal                                  */
55360   GPIO_PINCFG38_FNCSEL38_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
55361   GPIO_PINCFG38_FNCSEL38_SWTRACECLK    = 2,     /*!< SWTRACECLK : Serial Wire Debug Trace Clock                                */
55362   GPIO_PINCFG38_FNCSEL38_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55363   GPIO_PINCFG38_FNCSEL38_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
55364   GPIO_PINCFG38_FNCSEL38_DISP_D16      = 5,     /*!< DISP_D16 : Display Data 16                                                */
55365   GPIO_PINCFG38_FNCSEL38_CT38          = 6,     /*!< CT38 : Timer/Counter input or output; Selection of direction
55366                                                      is done via CTIMER register settings.                                     */
55367   GPIO_PINCFG38_FNCSEL38_NCE38         = 7,     /*!< NCE38 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55368                                                      CE_POLARITY field                                                         */
55369   GPIO_PINCFG38_FNCSEL38_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
55370   GPIO_PINCFG38_FNCSEL38_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55371   GPIO_PINCFG38_FNCSEL38_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55372   GPIO_PINCFG38_FNCSEL38_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55373   GPIO_PINCFG38_FNCSEL38_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55374   GPIO_PINCFG38_FNCSEL38_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55375   GPIO_PINCFG38_FNCSEL38_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55376   GPIO_PINCFG38_FNCSEL38_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55377 } GPIO_PINCFG38_FNCSEL38_Enum;
55378 
55379 /* =======================================================  PINCFG39  ======================================================== */
55380 /* ============================================  GPIO PINCFG39 NCEPOL39 [22..22]  ============================================ */
55381 typedef enum {                                  /*!< GPIO_PINCFG39_NCEPOL39                                                    */
55382   GPIO_PINCFG39_NCEPOL39_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55383   GPIO_PINCFG39_NCEPOL39_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55384 } GPIO_PINCFG39_NCEPOL39_Enum;
55385 
55386 /* ============================================  GPIO PINCFG39 NCESRC39 [16..21]  ============================================ */
55387 typedef enum {                                  /*!< GPIO_PINCFG39_NCESRC39                                                    */
55388   GPIO_PINCFG39_NCESRC39_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55389   GPIO_PINCFG39_NCESRC39_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55390   GPIO_PINCFG39_NCESRC39_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55391   GPIO_PINCFG39_NCESRC39_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55392   GPIO_PINCFG39_NCESRC39_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55393   GPIO_PINCFG39_NCESRC39_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55394   GPIO_PINCFG39_NCESRC39_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55395   GPIO_PINCFG39_NCESRC39_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55396   GPIO_PINCFG39_NCESRC39_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55397   GPIO_PINCFG39_NCESRC39_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55398   GPIO_PINCFG39_NCESRC39_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55399   GPIO_PINCFG39_NCESRC39_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55400   GPIO_PINCFG39_NCESRC39_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55401   GPIO_PINCFG39_NCESRC39_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55402   GPIO_PINCFG39_NCESRC39_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55403   GPIO_PINCFG39_NCESRC39_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55404   GPIO_PINCFG39_NCESRC39_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55405   GPIO_PINCFG39_NCESRC39_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55406   GPIO_PINCFG39_NCESRC39_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55407   GPIO_PINCFG39_NCESRC39_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55408   GPIO_PINCFG39_NCESRC39_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55409   GPIO_PINCFG39_NCESRC39_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55410   GPIO_PINCFG39_NCESRC39_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55411   GPIO_PINCFG39_NCESRC39_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55412   GPIO_PINCFG39_NCESRC39_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55413   GPIO_PINCFG39_NCESRC39_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55414   GPIO_PINCFG39_NCESRC39_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55415   GPIO_PINCFG39_NCESRC39_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55416   GPIO_PINCFG39_NCESRC39_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55417   GPIO_PINCFG39_NCESRC39_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55418   GPIO_PINCFG39_NCESRC39_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55419   GPIO_PINCFG39_NCESRC39_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55420   GPIO_PINCFG39_NCESRC39_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55421   GPIO_PINCFG39_NCESRC39_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55422   GPIO_PINCFG39_NCESRC39_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55423   GPIO_PINCFG39_NCESRC39_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55424   GPIO_PINCFG39_NCESRC39_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55425   GPIO_PINCFG39_NCESRC39_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55426   GPIO_PINCFG39_NCESRC39_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55427   GPIO_PINCFG39_NCESRC39_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55428   GPIO_PINCFG39_NCESRC39_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55429   GPIO_PINCFG39_NCESRC39_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55430   GPIO_PINCFG39_NCESRC39_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55431 } GPIO_PINCFG39_NCESRC39_Enum;
55432 
55433 /* ===========================================  GPIO PINCFG39 PULLCFG39 [13..15]  ============================================ */
55434 typedef enum {                                  /*!< GPIO_PINCFG39_PULLCFG39                                                   */
55435   GPIO_PINCFG39_PULLCFG39_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55436   GPIO_PINCFG39_PULLCFG39_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55437   GPIO_PINCFG39_PULLCFG39_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55438   GPIO_PINCFG39_PULLCFG39_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55439   GPIO_PINCFG39_PULLCFG39_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55440   GPIO_PINCFG39_PULLCFG39_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55441   GPIO_PINCFG39_PULLCFG39_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55442   GPIO_PINCFG39_PULLCFG39_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55443 } GPIO_PINCFG39_PULLCFG39_Enum;
55444 
55445 /* ==============================================  GPIO PINCFG39 DS39 [10..11]  ============================================== */
55446 typedef enum {                                  /*!< GPIO_PINCFG39_DS39                                                        */
55447   GPIO_PINCFG39_DS39_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55448   GPIO_PINCFG39_DS39_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55449   GPIO_PINCFG39_DS39_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55450   GPIO_PINCFG39_DS39_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55451 } GPIO_PINCFG39_DS39_Enum;
55452 
55453 /* =============================================  GPIO PINCFG39 OUTCFG39 [8..9]  ============================================= */
55454 typedef enum {                                  /*!< GPIO_PINCFG39_OUTCFG39                                                    */
55455   GPIO_PINCFG39_OUTCFG39_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55456   GPIO_PINCFG39_OUTCFG39_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55457                                                      and 1 values on pin.                                                      */
55458   GPIO_PINCFG39_OUTCFG39_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55459                                                      low, tristate otherwise.                                                  */
55460   GPIO_PINCFG39_OUTCFG39_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55461                                                      drive 0, 1 of HiZ on pin.                                                 */
55462 } GPIO_PINCFG39_OUTCFG39_Enum;
55463 
55464 /* =============================================  GPIO PINCFG39 IRPTEN39 [6..7]  ============================================= */
55465 typedef enum {                                  /*!< GPIO_PINCFG39_IRPTEN39                                                    */
55466   GPIO_PINCFG39_IRPTEN39_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55467   GPIO_PINCFG39_IRPTEN39_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55468                                                      on this GPIO                                                              */
55469   GPIO_PINCFG39_IRPTEN39_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55470                                                      on this GPIO                                                              */
55471   GPIO_PINCFG39_IRPTEN39_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55472                                                      GPIO                                                                      */
55473 } GPIO_PINCFG39_IRPTEN39_Enum;
55474 
55475 /* =============================================  GPIO PINCFG39 FNCSEL39 [0..3]  ============================================= */
55476 typedef enum {                                  /*!< GPIO_PINCFG39_FNCSEL39                                                    */
55477   GPIO_PINCFG39_FNCSEL39_MSPI1_2       = 0,     /*!< MSPI1_2 : MSPI Master 1 Interface Signal                                  */
55478   GPIO_PINCFG39_FNCSEL39_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
55479   GPIO_PINCFG39_FNCSEL39_SWTRACE0      = 2,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
55480   GPIO_PINCFG39_FNCSEL39_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55481   GPIO_PINCFG39_FNCSEL39_UART2RTS      = 4,     /*!< UART2RTS : UART Request to Send (RTS) (UART 2)                            */
55482   GPIO_PINCFG39_FNCSEL39_DISP_D17      = 5,     /*!< DISP_D17 : Display Data 17                                                */
55483   GPIO_PINCFG39_FNCSEL39_CT39          = 6,     /*!< CT39 : Timer/Counter input or output; Selection of direction
55484                                                      is done via CTIMER register settings.                                     */
55485   GPIO_PINCFG39_FNCSEL39_NCE39         = 7,     /*!< NCE39 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55486                                                      CE_POLARITY field                                                         */
55487   GPIO_PINCFG39_FNCSEL39_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
55488   GPIO_PINCFG39_FNCSEL39_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55489   GPIO_PINCFG39_FNCSEL39_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55490   GPIO_PINCFG39_FNCSEL39_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55491   GPIO_PINCFG39_FNCSEL39_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55492   GPIO_PINCFG39_FNCSEL39_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55493   GPIO_PINCFG39_FNCSEL39_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55494   GPIO_PINCFG39_FNCSEL39_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55495 } GPIO_PINCFG39_FNCSEL39_Enum;
55496 
55497 /* =======================================================  PINCFG40  ======================================================== */
55498 /* ============================================  GPIO PINCFG40 NCEPOL40 [22..22]  ============================================ */
55499 typedef enum {                                  /*!< GPIO_PINCFG40_NCEPOL40                                                    */
55500   GPIO_PINCFG40_NCEPOL40_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55501   GPIO_PINCFG40_NCEPOL40_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55502 } GPIO_PINCFG40_NCEPOL40_Enum;
55503 
55504 /* ============================================  GPIO PINCFG40 NCESRC40 [16..21]  ============================================ */
55505 typedef enum {                                  /*!< GPIO_PINCFG40_NCESRC40                                                    */
55506   GPIO_PINCFG40_NCESRC40_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55507   GPIO_PINCFG40_NCESRC40_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55508   GPIO_PINCFG40_NCESRC40_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55509   GPIO_PINCFG40_NCESRC40_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55510   GPIO_PINCFG40_NCESRC40_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55511   GPIO_PINCFG40_NCESRC40_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55512   GPIO_PINCFG40_NCESRC40_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55513   GPIO_PINCFG40_NCESRC40_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55514   GPIO_PINCFG40_NCESRC40_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55515   GPIO_PINCFG40_NCESRC40_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55516   GPIO_PINCFG40_NCESRC40_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55517   GPIO_PINCFG40_NCESRC40_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55518   GPIO_PINCFG40_NCESRC40_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55519   GPIO_PINCFG40_NCESRC40_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55520   GPIO_PINCFG40_NCESRC40_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55521   GPIO_PINCFG40_NCESRC40_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55522   GPIO_PINCFG40_NCESRC40_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55523   GPIO_PINCFG40_NCESRC40_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55524   GPIO_PINCFG40_NCESRC40_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55525   GPIO_PINCFG40_NCESRC40_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55526   GPIO_PINCFG40_NCESRC40_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55527   GPIO_PINCFG40_NCESRC40_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55528   GPIO_PINCFG40_NCESRC40_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55529   GPIO_PINCFG40_NCESRC40_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55530   GPIO_PINCFG40_NCESRC40_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55531   GPIO_PINCFG40_NCESRC40_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55532   GPIO_PINCFG40_NCESRC40_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55533   GPIO_PINCFG40_NCESRC40_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55534   GPIO_PINCFG40_NCESRC40_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55535   GPIO_PINCFG40_NCESRC40_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55536   GPIO_PINCFG40_NCESRC40_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55537   GPIO_PINCFG40_NCESRC40_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55538   GPIO_PINCFG40_NCESRC40_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55539   GPIO_PINCFG40_NCESRC40_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55540   GPIO_PINCFG40_NCESRC40_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55541   GPIO_PINCFG40_NCESRC40_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55542   GPIO_PINCFG40_NCESRC40_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55543   GPIO_PINCFG40_NCESRC40_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55544   GPIO_PINCFG40_NCESRC40_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55545   GPIO_PINCFG40_NCESRC40_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55546   GPIO_PINCFG40_NCESRC40_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55547   GPIO_PINCFG40_NCESRC40_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55548   GPIO_PINCFG40_NCESRC40_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55549 } GPIO_PINCFG40_NCESRC40_Enum;
55550 
55551 /* ===========================================  GPIO PINCFG40 PULLCFG40 [13..15]  ============================================ */
55552 typedef enum {                                  /*!< GPIO_PINCFG40_PULLCFG40                                                   */
55553   GPIO_PINCFG40_PULLCFG40_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55554   GPIO_PINCFG40_PULLCFG40_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55555   GPIO_PINCFG40_PULLCFG40_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55556   GPIO_PINCFG40_PULLCFG40_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55557   GPIO_PINCFG40_PULLCFG40_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55558   GPIO_PINCFG40_PULLCFG40_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55559   GPIO_PINCFG40_PULLCFG40_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55560   GPIO_PINCFG40_PULLCFG40_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55561 } GPIO_PINCFG40_PULLCFG40_Enum;
55562 
55563 /* ==============================================  GPIO PINCFG40 DS40 [10..11]  ============================================== */
55564 typedef enum {                                  /*!< GPIO_PINCFG40_DS40                                                        */
55565   GPIO_PINCFG40_DS40_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55566   GPIO_PINCFG40_DS40_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55567   GPIO_PINCFG40_DS40_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55568   GPIO_PINCFG40_DS40_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55569 } GPIO_PINCFG40_DS40_Enum;
55570 
55571 /* =============================================  GPIO PINCFG40 OUTCFG40 [8..9]  ============================================= */
55572 typedef enum {                                  /*!< GPIO_PINCFG40_OUTCFG40                                                    */
55573   GPIO_PINCFG40_OUTCFG40_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55574   GPIO_PINCFG40_OUTCFG40_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55575                                                      and 1 values on pin.                                                      */
55576   GPIO_PINCFG40_OUTCFG40_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55577                                                      low, tristate otherwise.                                                  */
55578   GPIO_PINCFG40_OUTCFG40_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55579                                                      drive 0, 1 of HiZ on pin.                                                 */
55580 } GPIO_PINCFG40_OUTCFG40_Enum;
55581 
55582 /* =============================================  GPIO PINCFG40 IRPTEN40 [6..7]  ============================================= */
55583 typedef enum {                                  /*!< GPIO_PINCFG40_IRPTEN40                                                    */
55584   GPIO_PINCFG40_IRPTEN40_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55585   GPIO_PINCFG40_IRPTEN40_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55586                                                      on this GPIO                                                              */
55587   GPIO_PINCFG40_IRPTEN40_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55588                                                      on this GPIO                                                              */
55589   GPIO_PINCFG40_IRPTEN40_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55590                                                      GPIO                                                                      */
55591 } GPIO_PINCFG40_IRPTEN40_Enum;
55592 
55593 /* =============================================  GPIO PINCFG40 FNCSEL40 [0..3]  ============================================= */
55594 typedef enum {                                  /*!< GPIO_PINCFG40_FNCSEL40                                                    */
55595   GPIO_PINCFG40_FNCSEL40_MSPI1_3       = 0,     /*!< MSPI1_3 : MSPI Master 1 Interface Signal                                  */
55596   GPIO_PINCFG40_FNCSEL40_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
55597   GPIO_PINCFG40_FNCSEL40_SWTRACE1      = 2,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
55598   GPIO_PINCFG40_FNCSEL40_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55599   GPIO_PINCFG40_FNCSEL40_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
55600   GPIO_PINCFG40_FNCSEL40_DISP_D18      = 5,     /*!< DISP_D18 : Display Data 18                                                */
55601   GPIO_PINCFG40_FNCSEL40_CT40          = 6,     /*!< CT40 : Timer/Counter input or output; Selection of direction
55602                                                      is done via CTIMER register settings.                                     */
55603   GPIO_PINCFG40_FNCSEL40_NCE40         = 7,     /*!< NCE40 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55604                                                      CE_POLARITY field                                                         */
55605   GPIO_PINCFG40_FNCSEL40_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
55606   GPIO_PINCFG40_FNCSEL40_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55607   GPIO_PINCFG40_FNCSEL40_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55608   GPIO_PINCFG40_FNCSEL40_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55609   GPIO_PINCFG40_FNCSEL40_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55610   GPIO_PINCFG40_FNCSEL40_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55611   GPIO_PINCFG40_FNCSEL40_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55612   GPIO_PINCFG40_FNCSEL40_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55613 } GPIO_PINCFG40_FNCSEL40_Enum;
55614 
55615 /* =======================================================  PINCFG41  ======================================================== */
55616 /* ============================================  GPIO PINCFG41 NCEPOL41 [22..22]  ============================================ */
55617 typedef enum {                                  /*!< GPIO_PINCFG41_NCEPOL41                                                    */
55618   GPIO_PINCFG41_NCEPOL41_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55619   GPIO_PINCFG41_NCEPOL41_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55620 } GPIO_PINCFG41_NCEPOL41_Enum;
55621 
55622 /* ============================================  GPIO PINCFG41 NCESRC41 [16..21]  ============================================ */
55623 typedef enum {                                  /*!< GPIO_PINCFG41_NCESRC41                                                    */
55624   GPIO_PINCFG41_NCESRC41_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55625   GPIO_PINCFG41_NCESRC41_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55626   GPIO_PINCFG41_NCESRC41_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55627   GPIO_PINCFG41_NCESRC41_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55628   GPIO_PINCFG41_NCESRC41_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55629   GPIO_PINCFG41_NCESRC41_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55630   GPIO_PINCFG41_NCESRC41_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55631   GPIO_PINCFG41_NCESRC41_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55632   GPIO_PINCFG41_NCESRC41_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55633   GPIO_PINCFG41_NCESRC41_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55634   GPIO_PINCFG41_NCESRC41_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55635   GPIO_PINCFG41_NCESRC41_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55636   GPIO_PINCFG41_NCESRC41_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55637   GPIO_PINCFG41_NCESRC41_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55638   GPIO_PINCFG41_NCESRC41_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55639   GPIO_PINCFG41_NCESRC41_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55640   GPIO_PINCFG41_NCESRC41_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55641   GPIO_PINCFG41_NCESRC41_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55642   GPIO_PINCFG41_NCESRC41_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55643   GPIO_PINCFG41_NCESRC41_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55644   GPIO_PINCFG41_NCESRC41_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55645   GPIO_PINCFG41_NCESRC41_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55646   GPIO_PINCFG41_NCESRC41_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55647   GPIO_PINCFG41_NCESRC41_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55648   GPIO_PINCFG41_NCESRC41_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55649   GPIO_PINCFG41_NCESRC41_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55650   GPIO_PINCFG41_NCESRC41_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55651   GPIO_PINCFG41_NCESRC41_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55652   GPIO_PINCFG41_NCESRC41_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55653   GPIO_PINCFG41_NCESRC41_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55654   GPIO_PINCFG41_NCESRC41_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55655   GPIO_PINCFG41_NCESRC41_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55656   GPIO_PINCFG41_NCESRC41_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55657   GPIO_PINCFG41_NCESRC41_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55658   GPIO_PINCFG41_NCESRC41_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55659   GPIO_PINCFG41_NCESRC41_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55660   GPIO_PINCFG41_NCESRC41_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55661   GPIO_PINCFG41_NCESRC41_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55662   GPIO_PINCFG41_NCESRC41_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55663   GPIO_PINCFG41_NCESRC41_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55664   GPIO_PINCFG41_NCESRC41_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55665   GPIO_PINCFG41_NCESRC41_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55666   GPIO_PINCFG41_NCESRC41_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55667 } GPIO_PINCFG41_NCESRC41_Enum;
55668 
55669 /* ===========================================  GPIO PINCFG41 PULLCFG41 [13..15]  ============================================ */
55670 typedef enum {                                  /*!< GPIO_PINCFG41_PULLCFG41                                                   */
55671   GPIO_PINCFG41_PULLCFG41_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55672   GPIO_PINCFG41_PULLCFG41_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55673   GPIO_PINCFG41_PULLCFG41_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55674   GPIO_PINCFG41_PULLCFG41_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55675   GPIO_PINCFG41_PULLCFG41_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55676   GPIO_PINCFG41_PULLCFG41_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55677   GPIO_PINCFG41_PULLCFG41_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55678   GPIO_PINCFG41_PULLCFG41_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55679 } GPIO_PINCFG41_PULLCFG41_Enum;
55680 
55681 /* ==============================================  GPIO PINCFG41 DS41 [10..11]  ============================================== */
55682 typedef enum {                                  /*!< GPIO_PINCFG41_DS41                                                        */
55683   GPIO_PINCFG41_DS41_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55684   GPIO_PINCFG41_DS41_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55685   GPIO_PINCFG41_DS41_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55686   GPIO_PINCFG41_DS41_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55687 } GPIO_PINCFG41_DS41_Enum;
55688 
55689 /* =============================================  GPIO PINCFG41 OUTCFG41 [8..9]  ============================================= */
55690 typedef enum {                                  /*!< GPIO_PINCFG41_OUTCFG41                                                    */
55691   GPIO_PINCFG41_OUTCFG41_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55692   GPIO_PINCFG41_OUTCFG41_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55693                                                      and 1 values on pin.                                                      */
55694   GPIO_PINCFG41_OUTCFG41_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55695                                                      low, tristate otherwise.                                                  */
55696   GPIO_PINCFG41_OUTCFG41_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55697                                                      drive 0, 1 of HiZ on pin.                                                 */
55698 } GPIO_PINCFG41_OUTCFG41_Enum;
55699 
55700 /* =============================================  GPIO PINCFG41 IRPTEN41 [6..7]  ============================================= */
55701 typedef enum {                                  /*!< GPIO_PINCFG41_IRPTEN41                                                    */
55702   GPIO_PINCFG41_IRPTEN41_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55703   GPIO_PINCFG41_IRPTEN41_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55704                                                      on this GPIO                                                              */
55705   GPIO_PINCFG41_IRPTEN41_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55706                                                      on this GPIO                                                              */
55707   GPIO_PINCFG41_IRPTEN41_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55708                                                      GPIO                                                                      */
55709 } GPIO_PINCFG41_IRPTEN41_Enum;
55710 
55711 /* =============================================  GPIO PINCFG41 FNCSEL41 [0..3]  ============================================= */
55712 typedef enum {                                  /*!< GPIO_PINCFG41_FNCSEL41                                                    */
55713   GPIO_PINCFG41_FNCSEL41_MSPI1_4       = 0,     /*!< MSPI1_4 : MSPI Master 1 Interface Signal                                  */
55714   GPIO_PINCFG41_FNCSEL41_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
55715   GPIO_PINCFG41_FNCSEL41_SWTRACE2      = 2,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
55716   GPIO_PINCFG41_FNCSEL41_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55717   GPIO_PINCFG41_FNCSEL41_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
55718   GPIO_PINCFG41_FNCSEL41_DISP_D19      = 5,     /*!< DISP_D19 : Display Data 19                                                */
55719   GPIO_PINCFG41_FNCSEL41_CT41          = 6,     /*!< CT41 : Timer/Counter input or output; Selection of direction
55720                                                      is done via CTIMER register settings.                                     */
55721   GPIO_PINCFG41_FNCSEL41_NCE41         = 7,     /*!< NCE41 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55722                                                      CE_POLARITY field                                                         */
55723   GPIO_PINCFG41_FNCSEL41_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
55724   GPIO_PINCFG41_FNCSEL41_SWO           = 9,     /*!< SWO : Serial Wire Output                                                  */
55725   GPIO_PINCFG41_FNCSEL41_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55726   GPIO_PINCFG41_FNCSEL41_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55727   GPIO_PINCFG41_FNCSEL41_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55728   GPIO_PINCFG41_FNCSEL41_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55729   GPIO_PINCFG41_FNCSEL41_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55730   GPIO_PINCFG41_FNCSEL41_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55731 } GPIO_PINCFG41_FNCSEL41_Enum;
55732 
55733 /* =======================================================  PINCFG42  ======================================================== */
55734 /* ============================================  GPIO PINCFG42 NCEPOL42 [22..22]  ============================================ */
55735 typedef enum {                                  /*!< GPIO_PINCFG42_NCEPOL42                                                    */
55736   GPIO_PINCFG42_NCEPOL42_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55737   GPIO_PINCFG42_NCEPOL42_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55738 } GPIO_PINCFG42_NCEPOL42_Enum;
55739 
55740 /* ============================================  GPIO PINCFG42 NCESRC42 [16..21]  ============================================ */
55741 typedef enum {                                  /*!< GPIO_PINCFG42_NCESRC42                                                    */
55742   GPIO_PINCFG42_NCESRC42_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55743   GPIO_PINCFG42_NCESRC42_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55744   GPIO_PINCFG42_NCESRC42_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55745   GPIO_PINCFG42_NCESRC42_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55746   GPIO_PINCFG42_NCESRC42_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55747   GPIO_PINCFG42_NCESRC42_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55748   GPIO_PINCFG42_NCESRC42_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55749   GPIO_PINCFG42_NCESRC42_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55750   GPIO_PINCFG42_NCESRC42_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55751   GPIO_PINCFG42_NCESRC42_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55752   GPIO_PINCFG42_NCESRC42_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55753   GPIO_PINCFG42_NCESRC42_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55754   GPIO_PINCFG42_NCESRC42_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55755   GPIO_PINCFG42_NCESRC42_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55756   GPIO_PINCFG42_NCESRC42_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55757   GPIO_PINCFG42_NCESRC42_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55758   GPIO_PINCFG42_NCESRC42_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55759   GPIO_PINCFG42_NCESRC42_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55760   GPIO_PINCFG42_NCESRC42_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55761   GPIO_PINCFG42_NCESRC42_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55762   GPIO_PINCFG42_NCESRC42_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55763   GPIO_PINCFG42_NCESRC42_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55764   GPIO_PINCFG42_NCESRC42_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55765   GPIO_PINCFG42_NCESRC42_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55766   GPIO_PINCFG42_NCESRC42_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55767   GPIO_PINCFG42_NCESRC42_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55768   GPIO_PINCFG42_NCESRC42_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55769   GPIO_PINCFG42_NCESRC42_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55770   GPIO_PINCFG42_NCESRC42_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55771   GPIO_PINCFG42_NCESRC42_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55772   GPIO_PINCFG42_NCESRC42_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55773   GPIO_PINCFG42_NCESRC42_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55774   GPIO_PINCFG42_NCESRC42_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55775   GPIO_PINCFG42_NCESRC42_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55776   GPIO_PINCFG42_NCESRC42_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55777   GPIO_PINCFG42_NCESRC42_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55778   GPIO_PINCFG42_NCESRC42_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55779   GPIO_PINCFG42_NCESRC42_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55780   GPIO_PINCFG42_NCESRC42_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55781   GPIO_PINCFG42_NCESRC42_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55782   GPIO_PINCFG42_NCESRC42_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55783   GPIO_PINCFG42_NCESRC42_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55784   GPIO_PINCFG42_NCESRC42_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55785 } GPIO_PINCFG42_NCESRC42_Enum;
55786 
55787 /* ===========================================  GPIO PINCFG42 PULLCFG42 [13..15]  ============================================ */
55788 typedef enum {                                  /*!< GPIO_PINCFG42_PULLCFG42                                                   */
55789   GPIO_PINCFG42_PULLCFG42_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55790   GPIO_PINCFG42_PULLCFG42_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55791   GPIO_PINCFG42_PULLCFG42_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55792   GPIO_PINCFG42_PULLCFG42_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55793   GPIO_PINCFG42_PULLCFG42_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55794   GPIO_PINCFG42_PULLCFG42_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55795   GPIO_PINCFG42_PULLCFG42_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55796   GPIO_PINCFG42_PULLCFG42_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55797 } GPIO_PINCFG42_PULLCFG42_Enum;
55798 
55799 /* ==============================================  GPIO PINCFG42 DS42 [10..11]  ============================================== */
55800 typedef enum {                                  /*!< GPIO_PINCFG42_DS42                                                        */
55801   GPIO_PINCFG42_DS42_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55802   GPIO_PINCFG42_DS42_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55803   GPIO_PINCFG42_DS42_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55804   GPIO_PINCFG42_DS42_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55805 } GPIO_PINCFG42_DS42_Enum;
55806 
55807 /* =============================================  GPIO PINCFG42 OUTCFG42 [8..9]  ============================================= */
55808 typedef enum {                                  /*!< GPIO_PINCFG42_OUTCFG42                                                    */
55809   GPIO_PINCFG42_OUTCFG42_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55810   GPIO_PINCFG42_OUTCFG42_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55811                                                      and 1 values on pin.                                                      */
55812   GPIO_PINCFG42_OUTCFG42_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55813                                                      low, tristate otherwise.                                                  */
55814   GPIO_PINCFG42_OUTCFG42_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55815                                                      drive 0, 1 of HiZ on pin.                                                 */
55816 } GPIO_PINCFG42_OUTCFG42_Enum;
55817 
55818 /* =============================================  GPIO PINCFG42 IRPTEN42 [6..7]  ============================================= */
55819 typedef enum {                                  /*!< GPIO_PINCFG42_IRPTEN42                                                    */
55820   GPIO_PINCFG42_IRPTEN42_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55821   GPIO_PINCFG42_IRPTEN42_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55822                                                      on this GPIO                                                              */
55823   GPIO_PINCFG42_IRPTEN42_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55824                                                      on this GPIO                                                              */
55825   GPIO_PINCFG42_IRPTEN42_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55826                                                      GPIO                                                                      */
55827 } GPIO_PINCFG42_IRPTEN42_Enum;
55828 
55829 /* =============================================  GPIO PINCFG42 FNCSEL42 [0..3]  ============================================= */
55830 typedef enum {                                  /*!< GPIO_PINCFG42_FNCSEL42                                                    */
55831   GPIO_PINCFG42_FNCSEL42_MSPI1_5       = 0,     /*!< MSPI1_5 : MSPI Master 1 Interface Signal                                  */
55832   GPIO_PINCFG42_FNCSEL42_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
55833   GPIO_PINCFG42_FNCSEL42_SWTRACE3      = 2,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
55834   GPIO_PINCFG42_FNCSEL42_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55835   GPIO_PINCFG42_FNCSEL42_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
55836   GPIO_PINCFG42_FNCSEL42_DISP_D20      = 5,     /*!< DISP_D20 : Display Data 20                                                */
55837   GPIO_PINCFG42_FNCSEL42_CT42          = 6,     /*!< CT42 : Timer/Counter input or output; Selection of direction
55838                                                      is done via CTIMER register settings.                                     */
55839   GPIO_PINCFG42_FNCSEL42_NCE42         = 7,     /*!< NCE42 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55840                                                      CE_POLARITY field                                                         */
55841   GPIO_PINCFG42_FNCSEL42_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
55842   GPIO_PINCFG42_FNCSEL42_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55843   GPIO_PINCFG42_FNCSEL42_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55844   GPIO_PINCFG42_FNCSEL42_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55845   GPIO_PINCFG42_FNCSEL42_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55846   GPIO_PINCFG42_FNCSEL42_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55847   GPIO_PINCFG42_FNCSEL42_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55848   GPIO_PINCFG42_FNCSEL42_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55849 } GPIO_PINCFG42_FNCSEL42_Enum;
55850 
55851 /* =======================================================  PINCFG43  ======================================================== */
55852 /* ============================================  GPIO PINCFG43 NCEPOL43 [22..22]  ============================================ */
55853 typedef enum {                                  /*!< GPIO_PINCFG43_NCEPOL43                                                    */
55854   GPIO_PINCFG43_NCEPOL43_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55855   GPIO_PINCFG43_NCEPOL43_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55856 } GPIO_PINCFG43_NCEPOL43_Enum;
55857 
55858 /* ============================================  GPIO PINCFG43 NCESRC43 [16..21]  ============================================ */
55859 typedef enum {                                  /*!< GPIO_PINCFG43_NCESRC43                                                    */
55860   GPIO_PINCFG43_NCESRC43_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55861   GPIO_PINCFG43_NCESRC43_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55862   GPIO_PINCFG43_NCESRC43_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55863   GPIO_PINCFG43_NCESRC43_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55864   GPIO_PINCFG43_NCESRC43_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55865   GPIO_PINCFG43_NCESRC43_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55866   GPIO_PINCFG43_NCESRC43_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55867   GPIO_PINCFG43_NCESRC43_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55868   GPIO_PINCFG43_NCESRC43_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55869   GPIO_PINCFG43_NCESRC43_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55870   GPIO_PINCFG43_NCESRC43_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55871   GPIO_PINCFG43_NCESRC43_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55872   GPIO_PINCFG43_NCESRC43_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55873   GPIO_PINCFG43_NCESRC43_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55874   GPIO_PINCFG43_NCESRC43_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55875   GPIO_PINCFG43_NCESRC43_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55876   GPIO_PINCFG43_NCESRC43_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55877   GPIO_PINCFG43_NCESRC43_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55878   GPIO_PINCFG43_NCESRC43_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55879   GPIO_PINCFG43_NCESRC43_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55880   GPIO_PINCFG43_NCESRC43_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55881   GPIO_PINCFG43_NCESRC43_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
55882   GPIO_PINCFG43_NCESRC43_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
55883   GPIO_PINCFG43_NCESRC43_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
55884   GPIO_PINCFG43_NCESRC43_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
55885   GPIO_PINCFG43_NCESRC43_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
55886   GPIO_PINCFG43_NCESRC43_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
55887   GPIO_PINCFG43_NCESRC43_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
55888   GPIO_PINCFG43_NCESRC43_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
55889   GPIO_PINCFG43_NCESRC43_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
55890   GPIO_PINCFG43_NCESRC43_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
55891   GPIO_PINCFG43_NCESRC43_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
55892   GPIO_PINCFG43_NCESRC43_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
55893   GPIO_PINCFG43_NCESRC43_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
55894   GPIO_PINCFG43_NCESRC43_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
55895   GPIO_PINCFG43_NCESRC43_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
55896   GPIO_PINCFG43_NCESRC43_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
55897   GPIO_PINCFG43_NCESRC43_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
55898   GPIO_PINCFG43_NCESRC43_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
55899   GPIO_PINCFG43_NCESRC43_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
55900   GPIO_PINCFG43_NCESRC43_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
55901   GPIO_PINCFG43_NCESRC43_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
55902   GPIO_PINCFG43_NCESRC43_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
55903 } GPIO_PINCFG43_NCESRC43_Enum;
55904 
55905 /* ===========================================  GPIO PINCFG43 PULLCFG43 [13..15]  ============================================ */
55906 typedef enum {                                  /*!< GPIO_PINCFG43_PULLCFG43                                                   */
55907   GPIO_PINCFG43_PULLCFG43_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
55908   GPIO_PINCFG43_PULLCFG43_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
55909   GPIO_PINCFG43_PULLCFG43_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
55910   GPIO_PINCFG43_PULLCFG43_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
55911   GPIO_PINCFG43_PULLCFG43_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
55912   GPIO_PINCFG43_PULLCFG43_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
55913   GPIO_PINCFG43_PULLCFG43_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
55914   GPIO_PINCFG43_PULLCFG43_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
55915 } GPIO_PINCFG43_PULLCFG43_Enum;
55916 
55917 /* ==============================================  GPIO PINCFG43 DS43 [10..11]  ============================================== */
55918 typedef enum {                                  /*!< GPIO_PINCFG43_DS43                                                        */
55919   GPIO_PINCFG43_DS43_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
55920   GPIO_PINCFG43_DS43_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
55921   GPIO_PINCFG43_DS43_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
55922   GPIO_PINCFG43_DS43_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
55923 } GPIO_PINCFG43_DS43_Enum;
55924 
55925 /* =============================================  GPIO PINCFG43 OUTCFG43 [8..9]  ============================================= */
55926 typedef enum {                                  /*!< GPIO_PINCFG43_OUTCFG43                                                    */
55927   GPIO_PINCFG43_OUTCFG43_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
55928   GPIO_PINCFG43_OUTCFG43_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
55929                                                      and 1 values on pin.                                                      */
55930   GPIO_PINCFG43_OUTCFG43_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
55931                                                      low, tristate otherwise.                                                  */
55932   GPIO_PINCFG43_OUTCFG43_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
55933                                                      drive 0, 1 of HiZ on pin.                                                 */
55934 } GPIO_PINCFG43_OUTCFG43_Enum;
55935 
55936 /* =============================================  GPIO PINCFG43 IRPTEN43 [6..7]  ============================================= */
55937 typedef enum {                                  /*!< GPIO_PINCFG43_IRPTEN43                                                    */
55938   GPIO_PINCFG43_IRPTEN43_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
55939   GPIO_PINCFG43_IRPTEN43_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
55940                                                      on this GPIO                                                              */
55941   GPIO_PINCFG43_IRPTEN43_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
55942                                                      on this GPIO                                                              */
55943   GPIO_PINCFG43_IRPTEN43_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
55944                                                      GPIO                                                                      */
55945 } GPIO_PINCFG43_IRPTEN43_Enum;
55946 
55947 /* =============================================  GPIO PINCFG43 FNCSEL43 [0..3]  ============================================= */
55948 typedef enum {                                  /*!< GPIO_PINCFG43_FNCSEL43                                                    */
55949   GPIO_PINCFG43_FNCSEL43_MSPI1_6       = 0,     /*!< MSPI1_6 : MSPI Master 1 Interface Signal                                  */
55950   GPIO_PINCFG43_FNCSEL43_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
55951   GPIO_PINCFG43_FNCSEL43_SWTRACECTL    = 2,     /*!< SWTRACECTL : Serial Wire Debug Trace Control                              */
55952   GPIO_PINCFG43_FNCSEL43_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
55953   GPIO_PINCFG43_FNCSEL43_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
55954   GPIO_PINCFG43_FNCSEL43_DISP_D21      = 5,     /*!< DISP_D21 : Display Data 21                                                */
55955   GPIO_PINCFG43_FNCSEL43_CT43          = 6,     /*!< CT43 : Timer/Counter input or output; Selection of direction
55956                                                      is done via CTIMER register settings.                                     */
55957   GPIO_PINCFG43_FNCSEL43_NCE43         = 7,     /*!< NCE43 : IOMSTR/MSPI N Chip Select. Polarity is determined by
55958                                                      CE_POLARITY field                                                         */
55959   GPIO_PINCFG43_FNCSEL43_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
55960   GPIO_PINCFG43_FNCSEL43_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
55961   GPIO_PINCFG43_FNCSEL43_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
55962   GPIO_PINCFG43_FNCSEL43_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
55963   GPIO_PINCFG43_FNCSEL43_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
55964   GPIO_PINCFG43_FNCSEL43_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
55965   GPIO_PINCFG43_FNCSEL43_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
55966   GPIO_PINCFG43_FNCSEL43_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
55967 } GPIO_PINCFG43_FNCSEL43_Enum;
55968 
55969 /* =======================================================  PINCFG44  ======================================================== */
55970 /* ============================================  GPIO PINCFG44 NCEPOL44 [22..22]  ============================================ */
55971 typedef enum {                                  /*!< GPIO_PINCFG44_NCEPOL44                                                    */
55972   GPIO_PINCFG44_NCEPOL44_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
55973   GPIO_PINCFG44_NCEPOL44_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
55974 } GPIO_PINCFG44_NCEPOL44_Enum;
55975 
55976 /* ============================================  GPIO PINCFG44 NCESRC44 [16..21]  ============================================ */
55977 typedef enum {                                  /*!< GPIO_PINCFG44_NCESRC44                                                    */
55978   GPIO_PINCFG44_NCESRC44_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
55979   GPIO_PINCFG44_NCESRC44_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
55980   GPIO_PINCFG44_NCESRC44_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
55981   GPIO_PINCFG44_NCESRC44_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
55982   GPIO_PINCFG44_NCESRC44_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
55983   GPIO_PINCFG44_NCESRC44_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
55984   GPIO_PINCFG44_NCESRC44_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
55985   GPIO_PINCFG44_NCESRC44_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
55986   GPIO_PINCFG44_NCESRC44_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
55987   GPIO_PINCFG44_NCESRC44_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
55988   GPIO_PINCFG44_NCESRC44_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
55989   GPIO_PINCFG44_NCESRC44_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
55990   GPIO_PINCFG44_NCESRC44_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
55991   GPIO_PINCFG44_NCESRC44_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
55992   GPIO_PINCFG44_NCESRC44_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
55993   GPIO_PINCFG44_NCESRC44_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
55994   GPIO_PINCFG44_NCESRC44_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
55995   GPIO_PINCFG44_NCESRC44_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
55996   GPIO_PINCFG44_NCESRC44_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
55997   GPIO_PINCFG44_NCESRC44_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
55998   GPIO_PINCFG44_NCESRC44_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
55999   GPIO_PINCFG44_NCESRC44_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56000   GPIO_PINCFG44_NCESRC44_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56001   GPIO_PINCFG44_NCESRC44_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56002   GPIO_PINCFG44_NCESRC44_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56003   GPIO_PINCFG44_NCESRC44_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56004   GPIO_PINCFG44_NCESRC44_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56005   GPIO_PINCFG44_NCESRC44_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56006   GPIO_PINCFG44_NCESRC44_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56007   GPIO_PINCFG44_NCESRC44_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56008   GPIO_PINCFG44_NCESRC44_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56009   GPIO_PINCFG44_NCESRC44_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56010   GPIO_PINCFG44_NCESRC44_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56011   GPIO_PINCFG44_NCESRC44_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56012   GPIO_PINCFG44_NCESRC44_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56013   GPIO_PINCFG44_NCESRC44_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56014   GPIO_PINCFG44_NCESRC44_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56015   GPIO_PINCFG44_NCESRC44_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56016   GPIO_PINCFG44_NCESRC44_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56017   GPIO_PINCFG44_NCESRC44_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56018   GPIO_PINCFG44_NCESRC44_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56019   GPIO_PINCFG44_NCESRC44_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56020   GPIO_PINCFG44_NCESRC44_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56021 } GPIO_PINCFG44_NCESRC44_Enum;
56022 
56023 /* ===========================================  GPIO PINCFG44 PULLCFG44 [13..15]  ============================================ */
56024 typedef enum {                                  /*!< GPIO_PINCFG44_PULLCFG44                                                   */
56025   GPIO_PINCFG44_PULLCFG44_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56026   GPIO_PINCFG44_PULLCFG44_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56027   GPIO_PINCFG44_PULLCFG44_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56028   GPIO_PINCFG44_PULLCFG44_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56029   GPIO_PINCFG44_PULLCFG44_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56030   GPIO_PINCFG44_PULLCFG44_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56031   GPIO_PINCFG44_PULLCFG44_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56032   GPIO_PINCFG44_PULLCFG44_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56033 } GPIO_PINCFG44_PULLCFG44_Enum;
56034 
56035 /* ==============================================  GPIO PINCFG44 DS44 [10..11]  ============================================== */
56036 typedef enum {                                  /*!< GPIO_PINCFG44_DS44                                                        */
56037   GPIO_PINCFG44_DS44_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56038   GPIO_PINCFG44_DS44_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56039   GPIO_PINCFG44_DS44_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56040   GPIO_PINCFG44_DS44_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56041 } GPIO_PINCFG44_DS44_Enum;
56042 
56043 /* =============================================  GPIO PINCFG44 OUTCFG44 [8..9]  ============================================= */
56044 typedef enum {                                  /*!< GPIO_PINCFG44_OUTCFG44                                                    */
56045   GPIO_PINCFG44_OUTCFG44_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56046   GPIO_PINCFG44_OUTCFG44_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56047                                                      and 1 values on pin.                                                      */
56048   GPIO_PINCFG44_OUTCFG44_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56049                                                      low, tristate otherwise.                                                  */
56050   GPIO_PINCFG44_OUTCFG44_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56051                                                      drive 0, 1 of HiZ on pin.                                                 */
56052 } GPIO_PINCFG44_OUTCFG44_Enum;
56053 
56054 /* =============================================  GPIO PINCFG44 IRPTEN44 [6..7]  ============================================= */
56055 typedef enum {                                  /*!< GPIO_PINCFG44_IRPTEN44                                                    */
56056   GPIO_PINCFG44_IRPTEN44_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56057   GPIO_PINCFG44_IRPTEN44_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56058                                                      on this GPIO                                                              */
56059   GPIO_PINCFG44_IRPTEN44_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56060                                                      on this GPIO                                                              */
56061   GPIO_PINCFG44_IRPTEN44_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56062                                                      GPIO                                                                      */
56063 } GPIO_PINCFG44_IRPTEN44_Enum;
56064 
56065 /* =============================================  GPIO PINCFG44 FNCSEL44 [0..3]  ============================================= */
56066 typedef enum {                                  /*!< GPIO_PINCFG44_FNCSEL44                                                    */
56067   GPIO_PINCFG44_FNCSEL44_MSPI1_7       = 0,     /*!< MSPI1_7 : MSPI Master 1 Interface Signal                                  */
56068   GPIO_PINCFG44_FNCSEL44_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
56069   GPIO_PINCFG44_FNCSEL44_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
56070   GPIO_PINCFG44_FNCSEL44_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56071   GPIO_PINCFG44_FNCSEL44_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
56072   GPIO_PINCFG44_FNCSEL44_DISP_D22      = 5,     /*!< DISP_D22 : Display Data 22                                                */
56073   GPIO_PINCFG44_FNCSEL44_CT44          = 6,     /*!< CT44 : Timer/Counter input or output; Selection of direction
56074                                                      is done via CTIMER register settings.                                     */
56075   GPIO_PINCFG44_FNCSEL44_NCE44         = 7,     /*!< NCE44 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56076                                                      CE_POLARITY field                                                         */
56077   GPIO_PINCFG44_FNCSEL44_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
56078   GPIO_PINCFG44_FNCSEL44_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
56079   GPIO_PINCFG44_FNCSEL44_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56080   GPIO_PINCFG44_FNCSEL44_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56081   GPIO_PINCFG44_FNCSEL44_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56082   GPIO_PINCFG44_FNCSEL44_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56083   GPIO_PINCFG44_FNCSEL44_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56084   GPIO_PINCFG44_FNCSEL44_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56085 } GPIO_PINCFG44_FNCSEL44_Enum;
56086 
56087 /* =======================================================  PINCFG45  ======================================================== */
56088 /* ============================================  GPIO PINCFG45 NCEPOL45 [22..22]  ============================================ */
56089 typedef enum {                                  /*!< GPIO_PINCFG45_NCEPOL45                                                    */
56090   GPIO_PINCFG45_NCEPOL45_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56091   GPIO_PINCFG45_NCEPOL45_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56092 } GPIO_PINCFG45_NCEPOL45_Enum;
56093 
56094 /* ============================================  GPIO PINCFG45 NCESRC45 [16..21]  ============================================ */
56095 typedef enum {                                  /*!< GPIO_PINCFG45_NCESRC45                                                    */
56096   GPIO_PINCFG45_NCESRC45_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56097   GPIO_PINCFG45_NCESRC45_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56098   GPIO_PINCFG45_NCESRC45_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56099   GPIO_PINCFG45_NCESRC45_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56100   GPIO_PINCFG45_NCESRC45_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56101   GPIO_PINCFG45_NCESRC45_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56102   GPIO_PINCFG45_NCESRC45_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56103   GPIO_PINCFG45_NCESRC45_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56104   GPIO_PINCFG45_NCESRC45_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56105   GPIO_PINCFG45_NCESRC45_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56106   GPIO_PINCFG45_NCESRC45_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56107   GPIO_PINCFG45_NCESRC45_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56108   GPIO_PINCFG45_NCESRC45_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56109   GPIO_PINCFG45_NCESRC45_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56110   GPIO_PINCFG45_NCESRC45_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56111   GPIO_PINCFG45_NCESRC45_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56112   GPIO_PINCFG45_NCESRC45_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56113   GPIO_PINCFG45_NCESRC45_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56114   GPIO_PINCFG45_NCESRC45_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56115   GPIO_PINCFG45_NCESRC45_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56116   GPIO_PINCFG45_NCESRC45_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56117   GPIO_PINCFG45_NCESRC45_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56118   GPIO_PINCFG45_NCESRC45_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56119   GPIO_PINCFG45_NCESRC45_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56120   GPIO_PINCFG45_NCESRC45_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56121   GPIO_PINCFG45_NCESRC45_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56122   GPIO_PINCFG45_NCESRC45_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56123   GPIO_PINCFG45_NCESRC45_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56124   GPIO_PINCFG45_NCESRC45_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56125   GPIO_PINCFG45_NCESRC45_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56126   GPIO_PINCFG45_NCESRC45_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56127   GPIO_PINCFG45_NCESRC45_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56128   GPIO_PINCFG45_NCESRC45_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56129   GPIO_PINCFG45_NCESRC45_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56130   GPIO_PINCFG45_NCESRC45_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56131   GPIO_PINCFG45_NCESRC45_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56132   GPIO_PINCFG45_NCESRC45_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56133   GPIO_PINCFG45_NCESRC45_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56134   GPIO_PINCFG45_NCESRC45_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56135   GPIO_PINCFG45_NCESRC45_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56136   GPIO_PINCFG45_NCESRC45_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56137   GPIO_PINCFG45_NCESRC45_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56138   GPIO_PINCFG45_NCESRC45_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56139 } GPIO_PINCFG45_NCESRC45_Enum;
56140 
56141 /* ===========================================  GPIO PINCFG45 PULLCFG45 [13..15]  ============================================ */
56142 typedef enum {                                  /*!< GPIO_PINCFG45_PULLCFG45                                                   */
56143   GPIO_PINCFG45_PULLCFG45_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56144   GPIO_PINCFG45_PULLCFG45_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56145   GPIO_PINCFG45_PULLCFG45_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56146   GPIO_PINCFG45_PULLCFG45_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56147   GPIO_PINCFG45_PULLCFG45_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56148   GPIO_PINCFG45_PULLCFG45_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56149   GPIO_PINCFG45_PULLCFG45_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56150   GPIO_PINCFG45_PULLCFG45_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56151 } GPIO_PINCFG45_PULLCFG45_Enum;
56152 
56153 /* ==============================================  GPIO PINCFG45 DS45 [10..11]  ============================================== */
56154 typedef enum {                                  /*!< GPIO_PINCFG45_DS45                                                        */
56155   GPIO_PINCFG45_DS45_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56156   GPIO_PINCFG45_DS45_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56157   GPIO_PINCFG45_DS45_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56158   GPIO_PINCFG45_DS45_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56159 } GPIO_PINCFG45_DS45_Enum;
56160 
56161 /* =============================================  GPIO PINCFG45 OUTCFG45 [8..9]  ============================================= */
56162 typedef enum {                                  /*!< GPIO_PINCFG45_OUTCFG45                                                    */
56163   GPIO_PINCFG45_OUTCFG45_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56164   GPIO_PINCFG45_OUTCFG45_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56165                                                      and 1 values on pin.                                                      */
56166   GPIO_PINCFG45_OUTCFG45_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56167                                                      low, tristate otherwise.                                                  */
56168   GPIO_PINCFG45_OUTCFG45_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56169                                                      drive 0, 1 of HiZ on pin.                                                 */
56170 } GPIO_PINCFG45_OUTCFG45_Enum;
56171 
56172 /* =============================================  GPIO PINCFG45 IRPTEN45 [6..7]  ============================================= */
56173 typedef enum {                                  /*!< GPIO_PINCFG45_IRPTEN45                                                    */
56174   GPIO_PINCFG45_IRPTEN45_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56175   GPIO_PINCFG45_IRPTEN45_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56176                                                      on this GPIO                                                              */
56177   GPIO_PINCFG45_IRPTEN45_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56178                                                      on this GPIO                                                              */
56179   GPIO_PINCFG45_IRPTEN45_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56180                                                      GPIO                                                                      */
56181 } GPIO_PINCFG45_IRPTEN45_Enum;
56182 
56183 /* =============================================  GPIO PINCFG45 FNCSEL45 [0..3]  ============================================= */
56184 typedef enum {                                  /*!< GPIO_PINCFG45_FNCSEL45                                                    */
56185   GPIO_PINCFG45_FNCSEL45_MSPI1_8       = 0,     /*!< MSPI1_8 : MSPI Master 1 Interface Signal                                  */
56186   GPIO_PINCFG45_FNCSEL45_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
56187   GPIO_PINCFG45_FNCSEL45_32KHzXT       = 2,     /*!< 32KHzXT : 32kHZ from analog                                               */
56188   GPIO_PINCFG45_FNCSEL45_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56189   GPIO_PINCFG45_FNCSEL45_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
56190   GPIO_PINCFG45_FNCSEL45_DISP_D23      = 5,     /*!< DISP_D23 : Display Data 23                                                */
56191   GPIO_PINCFG45_FNCSEL45_CT45          = 6,     /*!< CT45 : Timer/Counter input or output; Selection of direction
56192                                                      is done via CTIMER register settings.                                     */
56193   GPIO_PINCFG45_FNCSEL45_NCE45         = 7,     /*!< NCE45 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56194                                                      CE_POLARITY field                                                         */
56195   GPIO_PINCFG45_FNCSEL45_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
56196   GPIO_PINCFG45_FNCSEL45_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56197   GPIO_PINCFG45_FNCSEL45_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56198   GPIO_PINCFG45_FNCSEL45_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56199   GPIO_PINCFG45_FNCSEL45_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56200   GPIO_PINCFG45_FNCSEL45_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56201   GPIO_PINCFG45_FNCSEL45_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56202   GPIO_PINCFG45_FNCSEL45_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56203 } GPIO_PINCFG45_FNCSEL45_Enum;
56204 
56205 /* =======================================================  PINCFG46  ======================================================== */
56206 /* ============================================  GPIO PINCFG46 NCEPOL46 [22..22]  ============================================ */
56207 typedef enum {                                  /*!< GPIO_PINCFG46_NCEPOL46                                                    */
56208   GPIO_PINCFG46_NCEPOL46_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56209   GPIO_PINCFG46_NCEPOL46_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56210 } GPIO_PINCFG46_NCEPOL46_Enum;
56211 
56212 /* ============================================  GPIO PINCFG46 NCESRC46 [16..21]  ============================================ */
56213 typedef enum {                                  /*!< GPIO_PINCFG46_NCESRC46                                                    */
56214   GPIO_PINCFG46_NCESRC46_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56215   GPIO_PINCFG46_NCESRC46_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56216   GPIO_PINCFG46_NCESRC46_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56217   GPIO_PINCFG46_NCESRC46_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56218   GPIO_PINCFG46_NCESRC46_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56219   GPIO_PINCFG46_NCESRC46_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56220   GPIO_PINCFG46_NCESRC46_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56221   GPIO_PINCFG46_NCESRC46_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56222   GPIO_PINCFG46_NCESRC46_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56223   GPIO_PINCFG46_NCESRC46_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56224   GPIO_PINCFG46_NCESRC46_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56225   GPIO_PINCFG46_NCESRC46_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56226   GPIO_PINCFG46_NCESRC46_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56227   GPIO_PINCFG46_NCESRC46_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56228   GPIO_PINCFG46_NCESRC46_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56229   GPIO_PINCFG46_NCESRC46_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56230   GPIO_PINCFG46_NCESRC46_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56231   GPIO_PINCFG46_NCESRC46_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56232   GPIO_PINCFG46_NCESRC46_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56233   GPIO_PINCFG46_NCESRC46_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56234   GPIO_PINCFG46_NCESRC46_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56235   GPIO_PINCFG46_NCESRC46_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56236   GPIO_PINCFG46_NCESRC46_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56237   GPIO_PINCFG46_NCESRC46_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56238   GPIO_PINCFG46_NCESRC46_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56239   GPIO_PINCFG46_NCESRC46_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56240   GPIO_PINCFG46_NCESRC46_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56241   GPIO_PINCFG46_NCESRC46_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56242   GPIO_PINCFG46_NCESRC46_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56243   GPIO_PINCFG46_NCESRC46_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56244   GPIO_PINCFG46_NCESRC46_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56245   GPIO_PINCFG46_NCESRC46_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56246   GPIO_PINCFG46_NCESRC46_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56247   GPIO_PINCFG46_NCESRC46_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56248   GPIO_PINCFG46_NCESRC46_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56249   GPIO_PINCFG46_NCESRC46_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56250   GPIO_PINCFG46_NCESRC46_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56251   GPIO_PINCFG46_NCESRC46_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56252   GPIO_PINCFG46_NCESRC46_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56253   GPIO_PINCFG46_NCESRC46_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56254   GPIO_PINCFG46_NCESRC46_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56255   GPIO_PINCFG46_NCESRC46_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56256   GPIO_PINCFG46_NCESRC46_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56257 } GPIO_PINCFG46_NCESRC46_Enum;
56258 
56259 /* ===========================================  GPIO PINCFG46 PULLCFG46 [13..15]  ============================================ */
56260 typedef enum {                                  /*!< GPIO_PINCFG46_PULLCFG46                                                   */
56261   GPIO_PINCFG46_PULLCFG46_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56262   GPIO_PINCFG46_PULLCFG46_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56263   GPIO_PINCFG46_PULLCFG46_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56264   GPIO_PINCFG46_PULLCFG46_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56265   GPIO_PINCFG46_PULLCFG46_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56266   GPIO_PINCFG46_PULLCFG46_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56267   GPIO_PINCFG46_PULLCFG46_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56268   GPIO_PINCFG46_PULLCFG46_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56269 } GPIO_PINCFG46_PULLCFG46_Enum;
56270 
56271 /* ==============================================  GPIO PINCFG46 DS46 [10..11]  ============================================== */
56272 typedef enum {                                  /*!< GPIO_PINCFG46_DS46                                                        */
56273   GPIO_PINCFG46_DS46_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56274   GPIO_PINCFG46_DS46_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56275   GPIO_PINCFG46_DS46_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56276   GPIO_PINCFG46_DS46_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56277 } GPIO_PINCFG46_DS46_Enum;
56278 
56279 /* =============================================  GPIO PINCFG46 OUTCFG46 [8..9]  ============================================= */
56280 typedef enum {                                  /*!< GPIO_PINCFG46_OUTCFG46                                                    */
56281   GPIO_PINCFG46_OUTCFG46_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56282   GPIO_PINCFG46_OUTCFG46_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56283                                                      and 1 values on pin.                                                      */
56284   GPIO_PINCFG46_OUTCFG46_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56285                                                      low, tristate otherwise.                                                  */
56286   GPIO_PINCFG46_OUTCFG46_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56287                                                      drive 0, 1 of HiZ on pin.                                                 */
56288 } GPIO_PINCFG46_OUTCFG46_Enum;
56289 
56290 /* =============================================  GPIO PINCFG46 IRPTEN46 [6..7]  ============================================= */
56291 typedef enum {                                  /*!< GPIO_PINCFG46_IRPTEN46                                                    */
56292   GPIO_PINCFG46_IRPTEN46_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56293   GPIO_PINCFG46_IRPTEN46_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56294                                                      on this GPIO                                                              */
56295   GPIO_PINCFG46_IRPTEN46_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56296                                                      on this GPIO                                                              */
56297   GPIO_PINCFG46_IRPTEN46_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56298                                                      GPIO                                                                      */
56299 } GPIO_PINCFG46_IRPTEN46_Enum;
56300 
56301 /* =============================================  GPIO PINCFG46 FNCSEL46 [0..3]  ============================================= */
56302 typedef enum {                                  /*!< GPIO_PINCFG46_FNCSEL46                                                    */
56303   GPIO_PINCFG46_FNCSEL46_MSPI1_9       = 0,     /*!< MSPI1_9 : MSPI Master 1 Interface Signal                                  */
56304   GPIO_PINCFG46_FNCSEL46_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
56305   GPIO_PINCFG46_FNCSEL46_CLKOUT_32M    = 2,     /*!< CLKOUT_32M : 32MHz Oscillator output clock                                */
56306   GPIO_PINCFG46_FNCSEL46_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56307   GPIO_PINCFG46_FNCSEL46_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
56308   GPIO_PINCFG46_FNCSEL46_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
56309   GPIO_PINCFG46_FNCSEL46_CT46          = 6,     /*!< CT46 : Timer/Counter input or output; Selection of direction
56310                                                      is done via CTIMER register settings.                                     */
56311   GPIO_PINCFG46_FNCSEL46_NCE46         = 7,     /*!< NCE46 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56312                                                      CE_POLARITY field                                                         */
56313   GPIO_PINCFG46_FNCSEL46_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
56314   GPIO_PINCFG46_FNCSEL46_I2S1_SDIN     = 9,     /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
56315   GPIO_PINCFG46_FNCSEL46_I2S0_SDIN     = 10,    /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
56316   GPIO_PINCFG46_FNCSEL46_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56317   GPIO_PINCFG46_FNCSEL46_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56318   GPIO_PINCFG46_FNCSEL46_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56319   GPIO_PINCFG46_FNCSEL46_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56320   GPIO_PINCFG46_FNCSEL46_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56321 } GPIO_PINCFG46_FNCSEL46_Enum;
56322 
56323 /* =======================================================  PINCFG47  ======================================================== */
56324 /* ============================================  GPIO PINCFG47 NCEPOL47 [22..22]  ============================================ */
56325 typedef enum {                                  /*!< GPIO_PINCFG47_NCEPOL47                                                    */
56326   GPIO_PINCFG47_NCEPOL47_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56327   GPIO_PINCFG47_NCEPOL47_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56328 } GPIO_PINCFG47_NCEPOL47_Enum;
56329 
56330 /* ============================================  GPIO PINCFG47 NCESRC47 [16..21]  ============================================ */
56331 typedef enum {                                  /*!< GPIO_PINCFG47_NCESRC47                                                    */
56332   GPIO_PINCFG47_NCESRC47_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56333   GPIO_PINCFG47_NCESRC47_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56334   GPIO_PINCFG47_NCESRC47_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56335   GPIO_PINCFG47_NCESRC47_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56336   GPIO_PINCFG47_NCESRC47_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56337   GPIO_PINCFG47_NCESRC47_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56338   GPIO_PINCFG47_NCESRC47_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56339   GPIO_PINCFG47_NCESRC47_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56340   GPIO_PINCFG47_NCESRC47_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56341   GPIO_PINCFG47_NCESRC47_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56342   GPIO_PINCFG47_NCESRC47_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56343   GPIO_PINCFG47_NCESRC47_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56344   GPIO_PINCFG47_NCESRC47_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56345   GPIO_PINCFG47_NCESRC47_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56346   GPIO_PINCFG47_NCESRC47_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56347   GPIO_PINCFG47_NCESRC47_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56348   GPIO_PINCFG47_NCESRC47_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56349   GPIO_PINCFG47_NCESRC47_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56350   GPIO_PINCFG47_NCESRC47_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56351   GPIO_PINCFG47_NCESRC47_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56352   GPIO_PINCFG47_NCESRC47_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56353   GPIO_PINCFG47_NCESRC47_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56354   GPIO_PINCFG47_NCESRC47_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56355   GPIO_PINCFG47_NCESRC47_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56356   GPIO_PINCFG47_NCESRC47_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56357   GPIO_PINCFG47_NCESRC47_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56358   GPIO_PINCFG47_NCESRC47_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56359   GPIO_PINCFG47_NCESRC47_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56360   GPIO_PINCFG47_NCESRC47_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56361   GPIO_PINCFG47_NCESRC47_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56362   GPIO_PINCFG47_NCESRC47_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56363   GPIO_PINCFG47_NCESRC47_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56364   GPIO_PINCFG47_NCESRC47_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56365   GPIO_PINCFG47_NCESRC47_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56366   GPIO_PINCFG47_NCESRC47_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56367   GPIO_PINCFG47_NCESRC47_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56368   GPIO_PINCFG47_NCESRC47_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56369   GPIO_PINCFG47_NCESRC47_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56370   GPIO_PINCFG47_NCESRC47_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56371   GPIO_PINCFG47_NCESRC47_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56372   GPIO_PINCFG47_NCESRC47_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56373   GPIO_PINCFG47_NCESRC47_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56374   GPIO_PINCFG47_NCESRC47_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56375 } GPIO_PINCFG47_NCESRC47_Enum;
56376 
56377 /* ===========================================  GPIO PINCFG47 PULLCFG47 [13..15]  ============================================ */
56378 typedef enum {                                  /*!< GPIO_PINCFG47_PULLCFG47                                                   */
56379   GPIO_PINCFG47_PULLCFG47_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56380   GPIO_PINCFG47_PULLCFG47_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56381   GPIO_PINCFG47_PULLCFG47_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56382   GPIO_PINCFG47_PULLCFG47_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56383   GPIO_PINCFG47_PULLCFG47_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56384   GPIO_PINCFG47_PULLCFG47_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56385   GPIO_PINCFG47_PULLCFG47_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56386   GPIO_PINCFG47_PULLCFG47_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56387 } GPIO_PINCFG47_PULLCFG47_Enum;
56388 
56389 /* ==============================================  GPIO PINCFG47 DS47 [10..11]  ============================================== */
56390 typedef enum {                                  /*!< GPIO_PINCFG47_DS47                                                        */
56391   GPIO_PINCFG47_DS47_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56392   GPIO_PINCFG47_DS47_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56393   GPIO_PINCFG47_DS47_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56394   GPIO_PINCFG47_DS47_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56395 } GPIO_PINCFG47_DS47_Enum;
56396 
56397 /* =============================================  GPIO PINCFG47 OUTCFG47 [8..9]  ============================================= */
56398 typedef enum {                                  /*!< GPIO_PINCFG47_OUTCFG47                                                    */
56399   GPIO_PINCFG47_OUTCFG47_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56400   GPIO_PINCFG47_OUTCFG47_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56401                                                      and 1 values on pin.                                                      */
56402   GPIO_PINCFG47_OUTCFG47_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56403                                                      low, tristate otherwise.                                                  */
56404   GPIO_PINCFG47_OUTCFG47_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56405                                                      drive 0, 1 of HiZ on pin.                                                 */
56406 } GPIO_PINCFG47_OUTCFG47_Enum;
56407 
56408 /* =============================================  GPIO PINCFG47 IRPTEN47 [6..7]  ============================================= */
56409 typedef enum {                                  /*!< GPIO_PINCFG47_IRPTEN47                                                    */
56410   GPIO_PINCFG47_IRPTEN47_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56411   GPIO_PINCFG47_IRPTEN47_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56412                                                      on this GPIO                                                              */
56413   GPIO_PINCFG47_IRPTEN47_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56414                                                      on this GPIO                                                              */
56415   GPIO_PINCFG47_IRPTEN47_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56416                                                      GPIO                                                                      */
56417 } GPIO_PINCFG47_IRPTEN47_Enum;
56418 
56419 /* =============================================  GPIO PINCFG47 FNCSEL47 [0..3]  ============================================= */
56420 typedef enum {                                  /*!< GPIO_PINCFG47_FNCSEL47                                                    */
56421   GPIO_PINCFG47_FNCSEL47_M5SCL         = 0,     /*!< M5SCL : Serial I2C Master Clock output (IOM 5)                            */
56422   GPIO_PINCFG47_FNCSEL47_M5SCK         = 1,     /*!< M5SCK : Serial SPI Master Clock output (IOM 5)                            */
56423   GPIO_PINCFG47_FNCSEL47_I2S1_CLK      = 2,     /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
56424                                                      in master mode and input mode for slave mode. (I2S Master/Slave
56425                                                      2)                                                                        */
56426   GPIO_PINCFG47_FNCSEL47_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56427   GPIO_PINCFG47_FNCSEL47_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
56428   GPIO_PINCFG47_FNCSEL47_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
56429   GPIO_PINCFG47_FNCSEL47_CT47          = 6,     /*!< CT47 : Timer/Counter input or output; Selection of direction
56430                                                      is done via CTIMER register settings.                                     */
56431   GPIO_PINCFG47_FNCSEL47_NCE47         = 7,     /*!< NCE47 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56432                                                      CE_POLARITY field                                                         */
56433   GPIO_PINCFG47_FNCSEL47_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
56434   GPIO_PINCFG47_FNCSEL47_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56435   GPIO_PINCFG47_FNCSEL47_I2S0_CLK      = 10,    /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
56436                                                      in master mode and input mode for slave mode. (I2S Master/Slave
56437                                                      2)                                                                        */
56438   GPIO_PINCFG47_FNCSEL47_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56439   GPIO_PINCFG47_FNCSEL47_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56440   GPIO_PINCFG47_FNCSEL47_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56441   GPIO_PINCFG47_FNCSEL47_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56442   GPIO_PINCFG47_FNCSEL47_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56443 } GPIO_PINCFG47_FNCSEL47_Enum;
56444 
56445 /* =======================================================  PINCFG48  ======================================================== */
56446 /* ============================================  GPIO PINCFG48 NCEPOL48 [22..22]  ============================================ */
56447 typedef enum {                                  /*!< GPIO_PINCFG48_NCEPOL48                                                    */
56448   GPIO_PINCFG48_NCEPOL48_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56449   GPIO_PINCFG48_NCEPOL48_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56450 } GPIO_PINCFG48_NCEPOL48_Enum;
56451 
56452 /* ============================================  GPIO PINCFG48 NCESRC48 [16..21]  ============================================ */
56453 typedef enum {                                  /*!< GPIO_PINCFG48_NCESRC48                                                    */
56454   GPIO_PINCFG48_NCESRC48_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56455   GPIO_PINCFG48_NCESRC48_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56456   GPIO_PINCFG48_NCESRC48_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56457   GPIO_PINCFG48_NCESRC48_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56458   GPIO_PINCFG48_NCESRC48_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56459   GPIO_PINCFG48_NCESRC48_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56460   GPIO_PINCFG48_NCESRC48_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56461   GPIO_PINCFG48_NCESRC48_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56462   GPIO_PINCFG48_NCESRC48_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56463   GPIO_PINCFG48_NCESRC48_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56464   GPIO_PINCFG48_NCESRC48_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56465   GPIO_PINCFG48_NCESRC48_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56466   GPIO_PINCFG48_NCESRC48_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56467   GPIO_PINCFG48_NCESRC48_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56468   GPIO_PINCFG48_NCESRC48_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56469   GPIO_PINCFG48_NCESRC48_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56470   GPIO_PINCFG48_NCESRC48_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56471   GPIO_PINCFG48_NCESRC48_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56472   GPIO_PINCFG48_NCESRC48_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56473   GPIO_PINCFG48_NCESRC48_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56474   GPIO_PINCFG48_NCESRC48_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56475   GPIO_PINCFG48_NCESRC48_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56476   GPIO_PINCFG48_NCESRC48_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56477   GPIO_PINCFG48_NCESRC48_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56478   GPIO_PINCFG48_NCESRC48_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56479   GPIO_PINCFG48_NCESRC48_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56480   GPIO_PINCFG48_NCESRC48_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56481   GPIO_PINCFG48_NCESRC48_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56482   GPIO_PINCFG48_NCESRC48_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56483   GPIO_PINCFG48_NCESRC48_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56484   GPIO_PINCFG48_NCESRC48_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56485   GPIO_PINCFG48_NCESRC48_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56486   GPIO_PINCFG48_NCESRC48_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56487   GPIO_PINCFG48_NCESRC48_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56488   GPIO_PINCFG48_NCESRC48_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56489   GPIO_PINCFG48_NCESRC48_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56490   GPIO_PINCFG48_NCESRC48_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56491   GPIO_PINCFG48_NCESRC48_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56492   GPIO_PINCFG48_NCESRC48_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56493   GPIO_PINCFG48_NCESRC48_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56494   GPIO_PINCFG48_NCESRC48_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56495   GPIO_PINCFG48_NCESRC48_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56496   GPIO_PINCFG48_NCESRC48_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56497 } GPIO_PINCFG48_NCESRC48_Enum;
56498 
56499 /* ===========================================  GPIO PINCFG48 PULLCFG48 [13..15]  ============================================ */
56500 typedef enum {                                  /*!< GPIO_PINCFG48_PULLCFG48                                                   */
56501   GPIO_PINCFG48_PULLCFG48_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56502   GPIO_PINCFG48_PULLCFG48_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56503   GPIO_PINCFG48_PULLCFG48_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56504   GPIO_PINCFG48_PULLCFG48_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56505   GPIO_PINCFG48_PULLCFG48_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56506   GPIO_PINCFG48_PULLCFG48_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56507   GPIO_PINCFG48_PULLCFG48_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56508   GPIO_PINCFG48_PULLCFG48_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56509 } GPIO_PINCFG48_PULLCFG48_Enum;
56510 
56511 /* ==============================================  GPIO PINCFG48 DS48 [10..11]  ============================================== */
56512 typedef enum {                                  /*!< GPIO_PINCFG48_DS48                                                        */
56513   GPIO_PINCFG48_DS48_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56514   GPIO_PINCFG48_DS48_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56515   GPIO_PINCFG48_DS48_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56516   GPIO_PINCFG48_DS48_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56517 } GPIO_PINCFG48_DS48_Enum;
56518 
56519 /* =============================================  GPIO PINCFG48 OUTCFG48 [8..9]  ============================================= */
56520 typedef enum {                                  /*!< GPIO_PINCFG48_OUTCFG48                                                    */
56521   GPIO_PINCFG48_OUTCFG48_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56522   GPIO_PINCFG48_OUTCFG48_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56523                                                      and 1 values on pin.                                                      */
56524   GPIO_PINCFG48_OUTCFG48_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56525                                                      low, tristate otherwise.                                                  */
56526   GPIO_PINCFG48_OUTCFG48_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56527                                                      drive 0, 1 of HiZ on pin.                                                 */
56528 } GPIO_PINCFG48_OUTCFG48_Enum;
56529 
56530 /* =============================================  GPIO PINCFG48 IRPTEN48 [6..7]  ============================================= */
56531 typedef enum {                                  /*!< GPIO_PINCFG48_IRPTEN48                                                    */
56532   GPIO_PINCFG48_IRPTEN48_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56533   GPIO_PINCFG48_IRPTEN48_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56534                                                      on this GPIO                                                              */
56535   GPIO_PINCFG48_IRPTEN48_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56536                                                      on this GPIO                                                              */
56537   GPIO_PINCFG48_IRPTEN48_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56538                                                      GPIO                                                                      */
56539 } GPIO_PINCFG48_IRPTEN48_Enum;
56540 
56541 /* =============================================  GPIO PINCFG48 FNCSEL48 [0..3]  ============================================= */
56542 typedef enum {                                  /*!< GPIO_PINCFG48_FNCSEL48                                                    */
56543   GPIO_PINCFG48_FNCSEL48_M5SDAWIR3     = 0,     /*!< M5SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
56544                                                      Master Data I/O (SPI 3 wire mode) (IOM 5)                                 */
56545   GPIO_PINCFG48_FNCSEL48_M5MOSI        = 1,     /*!< M5MOSI : Serial SPI Master MOSI output (IOM 5)                            */
56546   GPIO_PINCFG48_FNCSEL48_I2S1_DATA     = 2,     /*!< I2S1_DATA : Bidirectional I2S Data. Operates in output mode
56547                                                      in master mode and input mode for slave mode. (I2S Master/Slave
56548                                                      2)                                                                        */
56549   GPIO_PINCFG48_FNCSEL48_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56550   GPIO_PINCFG48_FNCSEL48_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
56551   GPIO_PINCFG48_FNCSEL48_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
56552   GPIO_PINCFG48_FNCSEL48_CT48          = 6,     /*!< CT48 : Timer/Counter input or output; Selection of direction
56553                                                      is done via CTIMER register settings.                                     */
56554   GPIO_PINCFG48_FNCSEL48_NCE48         = 7,     /*!< NCE48 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56555                                                      CE_POLARITY field                                                         */
56556   GPIO_PINCFG48_FNCSEL48_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
56557   GPIO_PINCFG48_FNCSEL48_I2S1_SDOUT    = 9,     /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
56558   GPIO_PINCFG48_FNCSEL48_I2S0_SDOUT    = 10,    /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
56559   GPIO_PINCFG48_FNCSEL48_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56560   GPIO_PINCFG48_FNCSEL48_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56561   GPIO_PINCFG48_FNCSEL48_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56562   GPIO_PINCFG48_FNCSEL48_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56563   GPIO_PINCFG48_FNCSEL48_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56564 } GPIO_PINCFG48_FNCSEL48_Enum;
56565 
56566 /* =======================================================  PINCFG49  ======================================================== */
56567 /* ============================================  GPIO PINCFG49 NCEPOL49 [22..22]  ============================================ */
56568 typedef enum {                                  /*!< GPIO_PINCFG49_NCEPOL49                                                    */
56569   GPIO_PINCFG49_NCEPOL49_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56570   GPIO_PINCFG49_NCEPOL49_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56571 } GPIO_PINCFG49_NCEPOL49_Enum;
56572 
56573 /* ============================================  GPIO PINCFG49 NCESRC49 [16..21]  ============================================ */
56574 typedef enum {                                  /*!< GPIO_PINCFG49_NCESRC49                                                    */
56575   GPIO_PINCFG49_NCESRC49_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56576   GPIO_PINCFG49_NCESRC49_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56577   GPIO_PINCFG49_NCESRC49_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56578   GPIO_PINCFG49_NCESRC49_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56579   GPIO_PINCFG49_NCESRC49_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56580   GPIO_PINCFG49_NCESRC49_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56581   GPIO_PINCFG49_NCESRC49_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56582   GPIO_PINCFG49_NCESRC49_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56583   GPIO_PINCFG49_NCESRC49_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56584   GPIO_PINCFG49_NCESRC49_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56585   GPIO_PINCFG49_NCESRC49_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56586   GPIO_PINCFG49_NCESRC49_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56587   GPIO_PINCFG49_NCESRC49_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56588   GPIO_PINCFG49_NCESRC49_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56589   GPIO_PINCFG49_NCESRC49_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56590   GPIO_PINCFG49_NCESRC49_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56591   GPIO_PINCFG49_NCESRC49_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56592   GPIO_PINCFG49_NCESRC49_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56593   GPIO_PINCFG49_NCESRC49_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56594   GPIO_PINCFG49_NCESRC49_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56595   GPIO_PINCFG49_NCESRC49_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56596   GPIO_PINCFG49_NCESRC49_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56597   GPIO_PINCFG49_NCESRC49_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56598   GPIO_PINCFG49_NCESRC49_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56599   GPIO_PINCFG49_NCESRC49_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56600   GPIO_PINCFG49_NCESRC49_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56601   GPIO_PINCFG49_NCESRC49_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56602   GPIO_PINCFG49_NCESRC49_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56603   GPIO_PINCFG49_NCESRC49_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56604   GPIO_PINCFG49_NCESRC49_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56605   GPIO_PINCFG49_NCESRC49_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56606   GPIO_PINCFG49_NCESRC49_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56607   GPIO_PINCFG49_NCESRC49_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56608   GPIO_PINCFG49_NCESRC49_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56609   GPIO_PINCFG49_NCESRC49_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56610   GPIO_PINCFG49_NCESRC49_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56611   GPIO_PINCFG49_NCESRC49_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56612   GPIO_PINCFG49_NCESRC49_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56613   GPIO_PINCFG49_NCESRC49_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56614   GPIO_PINCFG49_NCESRC49_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56615   GPIO_PINCFG49_NCESRC49_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56616   GPIO_PINCFG49_NCESRC49_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56617   GPIO_PINCFG49_NCESRC49_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56618 } GPIO_PINCFG49_NCESRC49_Enum;
56619 
56620 /* ===========================================  GPIO PINCFG49 PULLCFG49 [13..15]  ============================================ */
56621 typedef enum {                                  /*!< GPIO_PINCFG49_PULLCFG49                                                   */
56622   GPIO_PINCFG49_PULLCFG49_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56623   GPIO_PINCFG49_PULLCFG49_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56624   GPIO_PINCFG49_PULLCFG49_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56625   GPIO_PINCFG49_PULLCFG49_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56626   GPIO_PINCFG49_PULLCFG49_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56627   GPIO_PINCFG49_PULLCFG49_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56628   GPIO_PINCFG49_PULLCFG49_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56629   GPIO_PINCFG49_PULLCFG49_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56630 } GPIO_PINCFG49_PULLCFG49_Enum;
56631 
56632 /* ==============================================  GPIO PINCFG49 DS49 [10..11]  ============================================== */
56633 typedef enum {                                  /*!< GPIO_PINCFG49_DS49                                                        */
56634   GPIO_PINCFG49_DS49_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56635   GPIO_PINCFG49_DS49_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56636   GPIO_PINCFG49_DS49_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56637   GPIO_PINCFG49_DS49_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56638 } GPIO_PINCFG49_DS49_Enum;
56639 
56640 /* =============================================  GPIO PINCFG49 OUTCFG49 [8..9]  ============================================= */
56641 typedef enum {                                  /*!< GPIO_PINCFG49_OUTCFG49                                                    */
56642   GPIO_PINCFG49_OUTCFG49_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56643   GPIO_PINCFG49_OUTCFG49_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56644                                                      and 1 values on pin.                                                      */
56645   GPIO_PINCFG49_OUTCFG49_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56646                                                      low, tristate otherwise.                                                  */
56647   GPIO_PINCFG49_OUTCFG49_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56648                                                      drive 0, 1 of HiZ on pin.                                                 */
56649 } GPIO_PINCFG49_OUTCFG49_Enum;
56650 
56651 /* =============================================  GPIO PINCFG49 IRPTEN49 [6..7]  ============================================= */
56652 typedef enum {                                  /*!< GPIO_PINCFG49_IRPTEN49                                                    */
56653   GPIO_PINCFG49_IRPTEN49_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56654   GPIO_PINCFG49_IRPTEN49_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56655                                                      on this GPIO                                                              */
56656   GPIO_PINCFG49_IRPTEN49_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56657                                                      on this GPIO                                                              */
56658   GPIO_PINCFG49_IRPTEN49_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56659                                                      GPIO                                                                      */
56660 } GPIO_PINCFG49_IRPTEN49_Enum;
56661 
56662 /* =============================================  GPIO PINCFG49 FNCSEL49 [0..3]  ============================================= */
56663 typedef enum {                                  /*!< GPIO_PINCFG49_FNCSEL49                                                    */
56664   GPIO_PINCFG49_FNCSEL49_M5MISO        = 0,     /*!< M5MISO : Serial SPI MASTER MISO input (IOM 5)                             */
56665   GPIO_PINCFG49_FNCSEL49_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
56666   GPIO_PINCFG49_FNCSEL49_I2S1_WS       = 2,     /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
56667                                                      in master mode and input mode for slave mode. (I2S Master/Slave
56668                                                      2)                                                                        */
56669   GPIO_PINCFG49_FNCSEL49_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56670   GPIO_PINCFG49_FNCSEL49_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
56671   GPIO_PINCFG49_FNCSEL49_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
56672   GPIO_PINCFG49_FNCSEL49_CT49          = 6,     /*!< CT49 : Timer/Counter input or output; Selection of direction
56673                                                      is done via CTIMER register settings.                                     */
56674   GPIO_PINCFG49_FNCSEL49_NCE49         = 7,     /*!< NCE49 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56675                                                      CE_POLARITY field                                                         */
56676   GPIO_PINCFG49_FNCSEL49_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
56677   GPIO_PINCFG49_FNCSEL49_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56678   GPIO_PINCFG49_FNCSEL49_I2S0_WS       = 10,    /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
56679                                                      in master mode and input mode for slave mode. (I2S Master/Slave
56680                                                      2)                                                                        */
56681   GPIO_PINCFG49_FNCSEL49_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56682   GPIO_PINCFG49_FNCSEL49_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56683   GPIO_PINCFG49_FNCSEL49_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56684   GPIO_PINCFG49_FNCSEL49_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56685   GPIO_PINCFG49_FNCSEL49_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56686 } GPIO_PINCFG49_FNCSEL49_Enum;
56687 
56688 /* =======================================================  PINCFG50  ======================================================== */
56689 /* ============================================  GPIO PINCFG50 NCEPOL50 [22..22]  ============================================ */
56690 typedef enum {                                  /*!< GPIO_PINCFG50_NCEPOL50                                                    */
56691   GPIO_PINCFG50_NCEPOL50_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56692   GPIO_PINCFG50_NCEPOL50_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56693 } GPIO_PINCFG50_NCEPOL50_Enum;
56694 
56695 /* ============================================  GPIO PINCFG50 NCESRC50 [16..21]  ============================================ */
56696 typedef enum {                                  /*!< GPIO_PINCFG50_NCESRC50                                                    */
56697   GPIO_PINCFG50_NCESRC50_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56698   GPIO_PINCFG50_NCESRC50_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56699   GPIO_PINCFG50_NCESRC50_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56700   GPIO_PINCFG50_NCESRC50_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56701   GPIO_PINCFG50_NCESRC50_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56702   GPIO_PINCFG50_NCESRC50_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56703   GPIO_PINCFG50_NCESRC50_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56704   GPIO_PINCFG50_NCESRC50_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56705   GPIO_PINCFG50_NCESRC50_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56706   GPIO_PINCFG50_NCESRC50_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56707   GPIO_PINCFG50_NCESRC50_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56708   GPIO_PINCFG50_NCESRC50_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56709   GPIO_PINCFG50_NCESRC50_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56710   GPIO_PINCFG50_NCESRC50_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56711   GPIO_PINCFG50_NCESRC50_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56712   GPIO_PINCFG50_NCESRC50_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56713   GPIO_PINCFG50_NCESRC50_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56714   GPIO_PINCFG50_NCESRC50_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56715   GPIO_PINCFG50_NCESRC50_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56716   GPIO_PINCFG50_NCESRC50_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56717   GPIO_PINCFG50_NCESRC50_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56718   GPIO_PINCFG50_NCESRC50_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56719   GPIO_PINCFG50_NCESRC50_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56720   GPIO_PINCFG50_NCESRC50_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56721   GPIO_PINCFG50_NCESRC50_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56722   GPIO_PINCFG50_NCESRC50_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56723   GPIO_PINCFG50_NCESRC50_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56724   GPIO_PINCFG50_NCESRC50_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56725   GPIO_PINCFG50_NCESRC50_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56726   GPIO_PINCFG50_NCESRC50_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56727   GPIO_PINCFG50_NCESRC50_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56728   GPIO_PINCFG50_NCESRC50_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56729   GPIO_PINCFG50_NCESRC50_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56730   GPIO_PINCFG50_NCESRC50_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56731   GPIO_PINCFG50_NCESRC50_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56732   GPIO_PINCFG50_NCESRC50_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56733   GPIO_PINCFG50_NCESRC50_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56734   GPIO_PINCFG50_NCESRC50_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56735   GPIO_PINCFG50_NCESRC50_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56736   GPIO_PINCFG50_NCESRC50_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56737   GPIO_PINCFG50_NCESRC50_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56738   GPIO_PINCFG50_NCESRC50_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56739   GPIO_PINCFG50_NCESRC50_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56740 } GPIO_PINCFG50_NCESRC50_Enum;
56741 
56742 /* ===========================================  GPIO PINCFG50 PULLCFG50 [13..15]  ============================================ */
56743 typedef enum {                                  /*!< GPIO_PINCFG50_PULLCFG50                                                   */
56744   GPIO_PINCFG50_PULLCFG50_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56745   GPIO_PINCFG50_PULLCFG50_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56746   GPIO_PINCFG50_PULLCFG50_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56747   GPIO_PINCFG50_PULLCFG50_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56748   GPIO_PINCFG50_PULLCFG50_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56749   GPIO_PINCFG50_PULLCFG50_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56750   GPIO_PINCFG50_PULLCFG50_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56751   GPIO_PINCFG50_PULLCFG50_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56752 } GPIO_PINCFG50_PULLCFG50_Enum;
56753 
56754 /* ==============================================  GPIO PINCFG50 DS50 [10..11]  ============================================== */
56755 typedef enum {                                  /*!< GPIO_PINCFG50_DS50                                                        */
56756   GPIO_PINCFG50_DS50_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56757   GPIO_PINCFG50_DS50_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56758 } GPIO_PINCFG50_DS50_Enum;
56759 
56760 /* =============================================  GPIO PINCFG50 OUTCFG50 [8..9]  ============================================= */
56761 typedef enum {                                  /*!< GPIO_PINCFG50_OUTCFG50                                                    */
56762   GPIO_PINCFG50_OUTCFG50_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56763   GPIO_PINCFG50_OUTCFG50_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56764                                                      and 1 values on pin.                                                      */
56765   GPIO_PINCFG50_OUTCFG50_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56766                                                      low, tristate otherwise.                                                  */
56767   GPIO_PINCFG50_OUTCFG50_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56768                                                      drive 0, 1 of HiZ on pin.                                                 */
56769 } GPIO_PINCFG50_OUTCFG50_Enum;
56770 
56771 /* =============================================  GPIO PINCFG50 IRPTEN50 [6..7]  ============================================= */
56772 typedef enum {                                  /*!< GPIO_PINCFG50_IRPTEN50                                                    */
56773   GPIO_PINCFG50_IRPTEN50_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56774   GPIO_PINCFG50_IRPTEN50_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56775                                                      on this GPIO                                                              */
56776   GPIO_PINCFG50_IRPTEN50_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56777                                                      on this GPIO                                                              */
56778   GPIO_PINCFG50_IRPTEN50_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56779                                                      GPIO                                                                      */
56780 } GPIO_PINCFG50_IRPTEN50_Enum;
56781 
56782 /* =============================================  GPIO PINCFG50 FNCSEL50 [0..3]  ============================================= */
56783 typedef enum {                                  /*!< GPIO_PINCFG50_FNCSEL50                                                    */
56784   GPIO_PINCFG50_FNCSEL50_PDM0_CLK      = 0,     /*!< PDM0_CLK : PDMx Clock output (I2C Master/Slave D)                         */
56785   GPIO_PINCFG50_FNCSEL50_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
56786   GPIO_PINCFG50_FNCSEL50_SWTRACECLK    = 2,     /*!< SWTRACECLK : Serial Wire Debug Trace Clock                                */
56787   GPIO_PINCFG50_FNCSEL50_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56788   GPIO_PINCFG50_FNCSEL50_UART2RTS      = 4,     /*!< UART2RTS : UART Request to Send (RTS) (UART 2)                            */
56789   GPIO_PINCFG50_FNCSEL50_UART3RTS      = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
56790   GPIO_PINCFG50_FNCSEL50_CT50          = 6,     /*!< CT50 : Timer/Counter input or output; Selection of direction
56791                                                      is done via CTIMER register settings.                                     */
56792   GPIO_PINCFG50_FNCSEL50_NCE50         = 7,     /*!< NCE50 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56793                                                      CE_POLARITY field                                                         */
56794   GPIO_PINCFG50_FNCSEL50_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
56795   GPIO_PINCFG50_FNCSEL50_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
56796   GPIO_PINCFG50_FNCSEL50_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56797   GPIO_PINCFG50_FNCSEL50_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56798   GPIO_PINCFG50_FNCSEL50_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56799   GPIO_PINCFG50_FNCSEL50_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56800   GPIO_PINCFG50_FNCSEL50_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56801   GPIO_PINCFG50_FNCSEL50_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56802 } GPIO_PINCFG50_FNCSEL50_Enum;
56803 
56804 /* =======================================================  PINCFG51  ======================================================== */
56805 /* ============================================  GPIO PINCFG51 NCEPOL51 [22..22]  ============================================ */
56806 typedef enum {                                  /*!< GPIO_PINCFG51_NCEPOL51                                                    */
56807   GPIO_PINCFG51_NCEPOL51_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56808   GPIO_PINCFG51_NCEPOL51_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56809 } GPIO_PINCFG51_NCEPOL51_Enum;
56810 
56811 /* ============================================  GPIO PINCFG51 NCESRC51 [16..21]  ============================================ */
56812 typedef enum {                                  /*!< GPIO_PINCFG51_NCESRC51                                                    */
56813   GPIO_PINCFG51_NCESRC51_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56814   GPIO_PINCFG51_NCESRC51_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56815   GPIO_PINCFG51_NCESRC51_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56816   GPIO_PINCFG51_NCESRC51_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56817   GPIO_PINCFG51_NCESRC51_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56818   GPIO_PINCFG51_NCESRC51_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56819   GPIO_PINCFG51_NCESRC51_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56820   GPIO_PINCFG51_NCESRC51_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56821   GPIO_PINCFG51_NCESRC51_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56822   GPIO_PINCFG51_NCESRC51_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56823   GPIO_PINCFG51_NCESRC51_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56824   GPIO_PINCFG51_NCESRC51_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56825   GPIO_PINCFG51_NCESRC51_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56826   GPIO_PINCFG51_NCESRC51_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56827   GPIO_PINCFG51_NCESRC51_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56828   GPIO_PINCFG51_NCESRC51_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56829   GPIO_PINCFG51_NCESRC51_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56830   GPIO_PINCFG51_NCESRC51_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56831   GPIO_PINCFG51_NCESRC51_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56832   GPIO_PINCFG51_NCESRC51_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56833   GPIO_PINCFG51_NCESRC51_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56834   GPIO_PINCFG51_NCESRC51_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56835   GPIO_PINCFG51_NCESRC51_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56836   GPIO_PINCFG51_NCESRC51_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56837   GPIO_PINCFG51_NCESRC51_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56838   GPIO_PINCFG51_NCESRC51_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56839   GPIO_PINCFG51_NCESRC51_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56840   GPIO_PINCFG51_NCESRC51_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56841   GPIO_PINCFG51_NCESRC51_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56842   GPIO_PINCFG51_NCESRC51_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56843   GPIO_PINCFG51_NCESRC51_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56844   GPIO_PINCFG51_NCESRC51_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56845   GPIO_PINCFG51_NCESRC51_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56846   GPIO_PINCFG51_NCESRC51_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56847   GPIO_PINCFG51_NCESRC51_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56848   GPIO_PINCFG51_NCESRC51_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56849   GPIO_PINCFG51_NCESRC51_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56850   GPIO_PINCFG51_NCESRC51_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56851   GPIO_PINCFG51_NCESRC51_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56852   GPIO_PINCFG51_NCESRC51_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56853   GPIO_PINCFG51_NCESRC51_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56854   GPIO_PINCFG51_NCESRC51_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56855   GPIO_PINCFG51_NCESRC51_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56856 } GPIO_PINCFG51_NCESRC51_Enum;
56857 
56858 /* ===========================================  GPIO PINCFG51 PULLCFG51 [13..15]  ============================================ */
56859 typedef enum {                                  /*!< GPIO_PINCFG51_PULLCFG51                                                   */
56860   GPIO_PINCFG51_PULLCFG51_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56861   GPIO_PINCFG51_PULLCFG51_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56862   GPIO_PINCFG51_PULLCFG51_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56863   GPIO_PINCFG51_PULLCFG51_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56864   GPIO_PINCFG51_PULLCFG51_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56865   GPIO_PINCFG51_PULLCFG51_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56866   GPIO_PINCFG51_PULLCFG51_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56867   GPIO_PINCFG51_PULLCFG51_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56868 } GPIO_PINCFG51_PULLCFG51_Enum;
56869 
56870 /* ==============================================  GPIO PINCFG51 DS51 [10..11]  ============================================== */
56871 typedef enum {                                  /*!< GPIO_PINCFG51_DS51                                                        */
56872   GPIO_PINCFG51_DS51_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56873   GPIO_PINCFG51_DS51_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56874   GPIO_PINCFG51_DS51_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56875   GPIO_PINCFG51_DS51_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56876 } GPIO_PINCFG51_DS51_Enum;
56877 
56878 /* =============================================  GPIO PINCFG51 OUTCFG51 [8..9]  ============================================= */
56879 typedef enum {                                  /*!< GPIO_PINCFG51_OUTCFG51                                                    */
56880   GPIO_PINCFG51_OUTCFG51_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
56881   GPIO_PINCFG51_OUTCFG51_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
56882                                                      and 1 values on pin.                                                      */
56883   GPIO_PINCFG51_OUTCFG51_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
56884                                                      low, tristate otherwise.                                                  */
56885   GPIO_PINCFG51_OUTCFG51_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
56886                                                      drive 0, 1 of HiZ on pin.                                                 */
56887 } GPIO_PINCFG51_OUTCFG51_Enum;
56888 
56889 /* =============================================  GPIO PINCFG51 IRPTEN51 [6..7]  ============================================= */
56890 typedef enum {                                  /*!< GPIO_PINCFG51_IRPTEN51                                                    */
56891   GPIO_PINCFG51_IRPTEN51_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
56892   GPIO_PINCFG51_IRPTEN51_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
56893                                                      on this GPIO                                                              */
56894   GPIO_PINCFG51_IRPTEN51_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
56895                                                      on this GPIO                                                              */
56896   GPIO_PINCFG51_IRPTEN51_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
56897                                                      GPIO                                                                      */
56898 } GPIO_PINCFG51_IRPTEN51_Enum;
56899 
56900 /* =============================================  GPIO PINCFG51 FNCSEL51 [0..3]  ============================================= */
56901 typedef enum {                                  /*!< GPIO_PINCFG51_FNCSEL51                                                    */
56902   GPIO_PINCFG51_FNCSEL51_PDM0_DATA     = 0,     /*!< PDM0_DATA : PDMx audio data input to chip (I2C Master/Slave
56903                                                      D)                                                                        */
56904   GPIO_PINCFG51_FNCSEL51_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
56905   GPIO_PINCFG51_FNCSEL51_SWTRACE0      = 2,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
56906   GPIO_PINCFG51_FNCSEL51_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
56907   GPIO_PINCFG51_FNCSEL51_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
56908   GPIO_PINCFG51_FNCSEL51_UART1CTS      = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
56909   GPIO_PINCFG51_FNCSEL51_CT51          = 6,     /*!< CT51 : Timer/Counter input or output; Selection of direction
56910                                                      is done via CTIMER register settings.                                     */
56911   GPIO_PINCFG51_FNCSEL51_NCE51         = 7,     /*!< NCE51 : IOMSTR/MSPI N Chip Select. Polarity is determined by
56912                                                      CE_POLARITY field                                                         */
56913   GPIO_PINCFG51_FNCSEL51_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
56914   GPIO_PINCFG51_FNCSEL51_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
56915   GPIO_PINCFG51_FNCSEL51_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
56916   GPIO_PINCFG51_FNCSEL51_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
56917   GPIO_PINCFG51_FNCSEL51_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
56918   GPIO_PINCFG51_FNCSEL51_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
56919   GPIO_PINCFG51_FNCSEL51_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
56920   GPIO_PINCFG51_FNCSEL51_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
56921 } GPIO_PINCFG51_FNCSEL51_Enum;
56922 
56923 /* =======================================================  PINCFG52  ======================================================== */
56924 /* ============================================  GPIO PINCFG52 NCEPOL52 [22..22]  ============================================ */
56925 typedef enum {                                  /*!< GPIO_PINCFG52_NCEPOL52                                                    */
56926   GPIO_PINCFG52_NCEPOL52_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
56927   GPIO_PINCFG52_NCEPOL52_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
56928 } GPIO_PINCFG52_NCEPOL52_Enum;
56929 
56930 /* ============================================  GPIO PINCFG52 NCESRC52 [16..21]  ============================================ */
56931 typedef enum {                                  /*!< GPIO_PINCFG52_NCESRC52                                                    */
56932   GPIO_PINCFG52_NCESRC52_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
56933   GPIO_PINCFG52_NCESRC52_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
56934   GPIO_PINCFG52_NCESRC52_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
56935   GPIO_PINCFG52_NCESRC52_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
56936   GPIO_PINCFG52_NCESRC52_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
56937   GPIO_PINCFG52_NCESRC52_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
56938   GPIO_PINCFG52_NCESRC52_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
56939   GPIO_PINCFG52_NCESRC52_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
56940   GPIO_PINCFG52_NCESRC52_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
56941   GPIO_PINCFG52_NCESRC52_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
56942   GPIO_PINCFG52_NCESRC52_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
56943   GPIO_PINCFG52_NCESRC52_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
56944   GPIO_PINCFG52_NCESRC52_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
56945   GPIO_PINCFG52_NCESRC52_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
56946   GPIO_PINCFG52_NCESRC52_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
56947   GPIO_PINCFG52_NCESRC52_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
56948   GPIO_PINCFG52_NCESRC52_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
56949   GPIO_PINCFG52_NCESRC52_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
56950   GPIO_PINCFG52_NCESRC52_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
56951   GPIO_PINCFG52_NCESRC52_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
56952   GPIO_PINCFG52_NCESRC52_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
56953   GPIO_PINCFG52_NCESRC52_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
56954   GPIO_PINCFG52_NCESRC52_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
56955   GPIO_PINCFG52_NCESRC52_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
56956   GPIO_PINCFG52_NCESRC52_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
56957   GPIO_PINCFG52_NCESRC52_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
56958   GPIO_PINCFG52_NCESRC52_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
56959   GPIO_PINCFG52_NCESRC52_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
56960   GPIO_PINCFG52_NCESRC52_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
56961   GPIO_PINCFG52_NCESRC52_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
56962   GPIO_PINCFG52_NCESRC52_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
56963   GPIO_PINCFG52_NCESRC52_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
56964   GPIO_PINCFG52_NCESRC52_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
56965   GPIO_PINCFG52_NCESRC52_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
56966   GPIO_PINCFG52_NCESRC52_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
56967   GPIO_PINCFG52_NCESRC52_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
56968   GPIO_PINCFG52_NCESRC52_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
56969   GPIO_PINCFG52_NCESRC52_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
56970   GPIO_PINCFG52_NCESRC52_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
56971   GPIO_PINCFG52_NCESRC52_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
56972   GPIO_PINCFG52_NCESRC52_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
56973   GPIO_PINCFG52_NCESRC52_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
56974   GPIO_PINCFG52_NCESRC52_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
56975 } GPIO_PINCFG52_NCESRC52_Enum;
56976 
56977 /* ===========================================  GPIO PINCFG52 PULLCFG52 [13..15]  ============================================ */
56978 typedef enum {                                  /*!< GPIO_PINCFG52_PULLCFG52                                                   */
56979   GPIO_PINCFG52_PULLCFG52_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
56980   GPIO_PINCFG52_PULLCFG52_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
56981   GPIO_PINCFG52_PULLCFG52_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
56982   GPIO_PINCFG52_PULLCFG52_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
56983   GPIO_PINCFG52_PULLCFG52_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
56984   GPIO_PINCFG52_PULLCFG52_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
56985   GPIO_PINCFG52_PULLCFG52_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
56986   GPIO_PINCFG52_PULLCFG52_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
56987 } GPIO_PINCFG52_PULLCFG52_Enum;
56988 
56989 /* ==============================================  GPIO PINCFG52 DS52 [10..11]  ============================================== */
56990 typedef enum {                                  /*!< GPIO_PINCFG52_DS52                                                        */
56991   GPIO_PINCFG52_DS52_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
56992   GPIO_PINCFG52_DS52_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
56993   GPIO_PINCFG52_DS52_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
56994   GPIO_PINCFG52_DS52_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
56995 } GPIO_PINCFG52_DS52_Enum;
56996 
56997 /* =============================================  GPIO PINCFG52 OUTCFG52 [8..9]  ============================================= */
56998 typedef enum {                                  /*!< GPIO_PINCFG52_OUTCFG52                                                    */
56999   GPIO_PINCFG52_OUTCFG52_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57000   GPIO_PINCFG52_OUTCFG52_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57001                                                      and 1 values on pin.                                                      */
57002   GPIO_PINCFG52_OUTCFG52_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57003                                                      low, tristate otherwise.                                                  */
57004   GPIO_PINCFG52_OUTCFG52_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57005                                                      drive 0, 1 of HiZ on pin.                                                 */
57006 } GPIO_PINCFG52_OUTCFG52_Enum;
57007 
57008 /* =============================================  GPIO PINCFG52 IRPTEN52 [6..7]  ============================================= */
57009 typedef enum {                                  /*!< GPIO_PINCFG52_IRPTEN52                                                    */
57010   GPIO_PINCFG52_IRPTEN52_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57011   GPIO_PINCFG52_IRPTEN52_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57012                                                      on this GPIO                                                              */
57013   GPIO_PINCFG52_IRPTEN52_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57014                                                      on this GPIO                                                              */
57015   GPIO_PINCFG52_IRPTEN52_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57016                                                      GPIO                                                                      */
57017 } GPIO_PINCFG52_IRPTEN52_Enum;
57018 
57019 /* =============================================  GPIO PINCFG52 FNCSEL52 [0..3]  ============================================= */
57020 typedef enum {                                  /*!< GPIO_PINCFG52_FNCSEL52                                                    */
57021   GPIO_PINCFG52_FNCSEL52_PDM1_CLK      = 0,     /*!< PDM1_CLK : PDMx Clock output (I2C Master/Slave D)                         */
57022   GPIO_PINCFG52_FNCSEL52_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
57023   GPIO_PINCFG52_FNCSEL52_SWTRACE1      = 2,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
57024   GPIO_PINCFG52_FNCSEL52_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57025   GPIO_PINCFG52_FNCSEL52_UART2CTS      = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
57026   GPIO_PINCFG52_FNCSEL52_UART3CTS      = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
57027   GPIO_PINCFG52_FNCSEL52_CT52          = 6,     /*!< CT52 : Timer/Counter input or output; Selection of direction
57028                                                      is done via CTIMER register settings.                                     */
57029   GPIO_PINCFG52_FNCSEL52_NCE52         = 7,     /*!< NCE52 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57030                                                      CE_POLARITY field                                                         */
57031   GPIO_PINCFG52_FNCSEL52_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
57032   GPIO_PINCFG52_FNCSEL52_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
57033   GPIO_PINCFG52_FNCSEL52_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57034   GPIO_PINCFG52_FNCSEL52_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57035   GPIO_PINCFG52_FNCSEL52_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57036   GPIO_PINCFG52_FNCSEL52_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57037   GPIO_PINCFG52_FNCSEL52_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57038   GPIO_PINCFG52_FNCSEL52_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57039 } GPIO_PINCFG52_FNCSEL52_Enum;
57040 
57041 /* =======================================================  PINCFG53  ======================================================== */
57042 /* ============================================  GPIO PINCFG53 NCEPOL53 [22..22]  ============================================ */
57043 typedef enum {                                  /*!< GPIO_PINCFG53_NCEPOL53                                                    */
57044   GPIO_PINCFG53_NCEPOL53_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57045   GPIO_PINCFG53_NCEPOL53_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57046 } GPIO_PINCFG53_NCEPOL53_Enum;
57047 
57048 /* ============================================  GPIO PINCFG53 NCESRC53 [16..21]  ============================================ */
57049 typedef enum {                                  /*!< GPIO_PINCFG53_NCESRC53                                                    */
57050   GPIO_PINCFG53_NCESRC53_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57051   GPIO_PINCFG53_NCESRC53_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57052   GPIO_PINCFG53_NCESRC53_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57053   GPIO_PINCFG53_NCESRC53_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57054   GPIO_PINCFG53_NCESRC53_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57055   GPIO_PINCFG53_NCESRC53_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57056   GPIO_PINCFG53_NCESRC53_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57057   GPIO_PINCFG53_NCESRC53_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57058   GPIO_PINCFG53_NCESRC53_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57059   GPIO_PINCFG53_NCESRC53_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57060   GPIO_PINCFG53_NCESRC53_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57061   GPIO_PINCFG53_NCESRC53_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57062   GPIO_PINCFG53_NCESRC53_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57063   GPIO_PINCFG53_NCESRC53_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57064   GPIO_PINCFG53_NCESRC53_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57065   GPIO_PINCFG53_NCESRC53_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57066   GPIO_PINCFG53_NCESRC53_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57067   GPIO_PINCFG53_NCESRC53_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57068   GPIO_PINCFG53_NCESRC53_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57069   GPIO_PINCFG53_NCESRC53_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57070   GPIO_PINCFG53_NCESRC53_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57071   GPIO_PINCFG53_NCESRC53_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57072   GPIO_PINCFG53_NCESRC53_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57073   GPIO_PINCFG53_NCESRC53_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57074   GPIO_PINCFG53_NCESRC53_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57075   GPIO_PINCFG53_NCESRC53_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57076   GPIO_PINCFG53_NCESRC53_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57077   GPIO_PINCFG53_NCESRC53_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57078   GPIO_PINCFG53_NCESRC53_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57079   GPIO_PINCFG53_NCESRC53_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57080   GPIO_PINCFG53_NCESRC53_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57081   GPIO_PINCFG53_NCESRC53_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57082   GPIO_PINCFG53_NCESRC53_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57083   GPIO_PINCFG53_NCESRC53_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57084   GPIO_PINCFG53_NCESRC53_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57085   GPIO_PINCFG53_NCESRC53_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57086   GPIO_PINCFG53_NCESRC53_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57087   GPIO_PINCFG53_NCESRC53_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57088   GPIO_PINCFG53_NCESRC53_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57089   GPIO_PINCFG53_NCESRC53_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57090   GPIO_PINCFG53_NCESRC53_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57091   GPIO_PINCFG53_NCESRC53_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57092   GPIO_PINCFG53_NCESRC53_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57093 } GPIO_PINCFG53_NCESRC53_Enum;
57094 
57095 /* ===========================================  GPIO PINCFG53 PULLCFG53 [13..15]  ============================================ */
57096 typedef enum {                                  /*!< GPIO_PINCFG53_PULLCFG53                                                   */
57097   GPIO_PINCFG53_PULLCFG53_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57098   GPIO_PINCFG53_PULLCFG53_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57099   GPIO_PINCFG53_PULLCFG53_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57100   GPIO_PINCFG53_PULLCFG53_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57101   GPIO_PINCFG53_PULLCFG53_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57102   GPIO_PINCFG53_PULLCFG53_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57103   GPIO_PINCFG53_PULLCFG53_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57104   GPIO_PINCFG53_PULLCFG53_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57105 } GPIO_PINCFG53_PULLCFG53_Enum;
57106 
57107 /* ==============================================  GPIO PINCFG53 DS53 [10..11]  ============================================== */
57108 typedef enum {                                  /*!< GPIO_PINCFG53_DS53                                                        */
57109   GPIO_PINCFG53_DS53_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57110   GPIO_PINCFG53_DS53_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57111   GPIO_PINCFG53_DS53_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57112   GPIO_PINCFG53_DS53_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57113 } GPIO_PINCFG53_DS53_Enum;
57114 
57115 /* =============================================  GPIO PINCFG53 OUTCFG53 [8..9]  ============================================= */
57116 typedef enum {                                  /*!< GPIO_PINCFG53_OUTCFG53                                                    */
57117   GPIO_PINCFG53_OUTCFG53_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57118   GPIO_PINCFG53_OUTCFG53_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57119                                                      and 1 values on pin.                                                      */
57120   GPIO_PINCFG53_OUTCFG53_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57121                                                      low, tristate otherwise.                                                  */
57122   GPIO_PINCFG53_OUTCFG53_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57123                                                      drive 0, 1 of HiZ on pin.                                                 */
57124 } GPIO_PINCFG53_OUTCFG53_Enum;
57125 
57126 /* =============================================  GPIO PINCFG53 IRPTEN53 [6..7]  ============================================= */
57127 typedef enum {                                  /*!< GPIO_PINCFG53_IRPTEN53                                                    */
57128   GPIO_PINCFG53_IRPTEN53_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57129   GPIO_PINCFG53_IRPTEN53_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57130                                                      on this GPIO                                                              */
57131   GPIO_PINCFG53_IRPTEN53_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57132                                                      on this GPIO                                                              */
57133   GPIO_PINCFG53_IRPTEN53_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57134                                                      GPIO                                                                      */
57135 } GPIO_PINCFG53_IRPTEN53_Enum;
57136 
57137 /* =============================================  GPIO PINCFG53 FNCSEL53 [0..3]  ============================================= */
57138 typedef enum {                                  /*!< GPIO_PINCFG53_FNCSEL53                                                    */
57139   GPIO_PINCFG53_FNCSEL53_PDM1_DATA     = 0,     /*!< PDM1_DATA : PDMx audio data input to chip (I2C Master/Slave
57140                                                      D)                                                                        */
57141   GPIO_PINCFG53_FNCSEL53_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
57142   GPIO_PINCFG53_FNCSEL53_SWTRACE2      = 2,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
57143   GPIO_PINCFG53_FNCSEL53_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57144   GPIO_PINCFG53_FNCSEL53_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
57145   GPIO_PINCFG53_FNCSEL53_UART1TX       = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
57146   GPIO_PINCFG53_FNCSEL53_CT53          = 6,     /*!< CT53 : Timer/Counter input or output; Selection of direction
57147                                                      is done via CTIMER register settings.                                     */
57148   GPIO_PINCFG53_FNCSEL53_NCE53         = 7,     /*!< NCE53 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57149                                                      CE_POLARITY field                                                         */
57150   GPIO_PINCFG53_FNCSEL53_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
57151   GPIO_PINCFG53_FNCSEL53_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57152   GPIO_PINCFG53_FNCSEL53_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57153   GPIO_PINCFG53_FNCSEL53_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57154   GPIO_PINCFG53_FNCSEL53_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57155   GPIO_PINCFG53_FNCSEL53_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57156   GPIO_PINCFG53_FNCSEL53_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57157   GPIO_PINCFG53_FNCSEL53_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57158 } GPIO_PINCFG53_FNCSEL53_Enum;
57159 
57160 /* =======================================================  PINCFG54  ======================================================== */
57161 /* ============================================  GPIO PINCFG54 NCEPOL54 [22..22]  ============================================ */
57162 typedef enum {                                  /*!< GPIO_PINCFG54_NCEPOL54                                                    */
57163   GPIO_PINCFG54_NCEPOL54_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57164   GPIO_PINCFG54_NCEPOL54_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57165 } GPIO_PINCFG54_NCEPOL54_Enum;
57166 
57167 /* ============================================  GPIO PINCFG54 NCESRC54 [16..21]  ============================================ */
57168 typedef enum {                                  /*!< GPIO_PINCFG54_NCESRC54                                                    */
57169   GPIO_PINCFG54_NCESRC54_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57170   GPIO_PINCFG54_NCESRC54_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57171   GPIO_PINCFG54_NCESRC54_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57172   GPIO_PINCFG54_NCESRC54_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57173   GPIO_PINCFG54_NCESRC54_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57174   GPIO_PINCFG54_NCESRC54_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57175   GPIO_PINCFG54_NCESRC54_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57176   GPIO_PINCFG54_NCESRC54_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57177   GPIO_PINCFG54_NCESRC54_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57178   GPIO_PINCFG54_NCESRC54_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57179   GPIO_PINCFG54_NCESRC54_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57180   GPIO_PINCFG54_NCESRC54_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57181   GPIO_PINCFG54_NCESRC54_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57182   GPIO_PINCFG54_NCESRC54_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57183   GPIO_PINCFG54_NCESRC54_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57184   GPIO_PINCFG54_NCESRC54_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57185   GPIO_PINCFG54_NCESRC54_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57186   GPIO_PINCFG54_NCESRC54_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57187   GPIO_PINCFG54_NCESRC54_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57188   GPIO_PINCFG54_NCESRC54_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57189   GPIO_PINCFG54_NCESRC54_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57190   GPIO_PINCFG54_NCESRC54_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57191   GPIO_PINCFG54_NCESRC54_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57192   GPIO_PINCFG54_NCESRC54_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57193   GPIO_PINCFG54_NCESRC54_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57194   GPIO_PINCFG54_NCESRC54_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57195   GPIO_PINCFG54_NCESRC54_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57196   GPIO_PINCFG54_NCESRC54_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57197   GPIO_PINCFG54_NCESRC54_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57198   GPIO_PINCFG54_NCESRC54_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57199   GPIO_PINCFG54_NCESRC54_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57200   GPIO_PINCFG54_NCESRC54_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57201   GPIO_PINCFG54_NCESRC54_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57202   GPIO_PINCFG54_NCESRC54_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57203   GPIO_PINCFG54_NCESRC54_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57204   GPIO_PINCFG54_NCESRC54_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57205   GPIO_PINCFG54_NCESRC54_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57206   GPIO_PINCFG54_NCESRC54_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57207   GPIO_PINCFG54_NCESRC54_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57208   GPIO_PINCFG54_NCESRC54_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57209   GPIO_PINCFG54_NCESRC54_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57210   GPIO_PINCFG54_NCESRC54_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57211   GPIO_PINCFG54_NCESRC54_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57212 } GPIO_PINCFG54_NCESRC54_Enum;
57213 
57214 /* ===========================================  GPIO PINCFG54 PULLCFG54 [13..15]  ============================================ */
57215 typedef enum {                                  /*!< GPIO_PINCFG54_PULLCFG54                                                   */
57216   GPIO_PINCFG54_PULLCFG54_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57217   GPIO_PINCFG54_PULLCFG54_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57218   GPIO_PINCFG54_PULLCFG54_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57219   GPIO_PINCFG54_PULLCFG54_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57220   GPIO_PINCFG54_PULLCFG54_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57221   GPIO_PINCFG54_PULLCFG54_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57222   GPIO_PINCFG54_PULLCFG54_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57223   GPIO_PINCFG54_PULLCFG54_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57224 } GPIO_PINCFG54_PULLCFG54_Enum;
57225 
57226 /* ==============================================  GPIO PINCFG54 DS54 [10..11]  ============================================== */
57227 typedef enum {                                  /*!< GPIO_PINCFG54_DS54                                                        */
57228   GPIO_PINCFG54_DS54_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57229   GPIO_PINCFG54_DS54_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57230   GPIO_PINCFG54_DS54_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57231   GPIO_PINCFG54_DS54_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57232 } GPIO_PINCFG54_DS54_Enum;
57233 
57234 /* =============================================  GPIO PINCFG54 OUTCFG54 [8..9]  ============================================= */
57235 typedef enum {                                  /*!< GPIO_PINCFG54_OUTCFG54                                                    */
57236   GPIO_PINCFG54_OUTCFG54_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57237   GPIO_PINCFG54_OUTCFG54_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57238                                                      and 1 values on pin.                                                      */
57239   GPIO_PINCFG54_OUTCFG54_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57240                                                      low, tristate otherwise.                                                  */
57241   GPIO_PINCFG54_OUTCFG54_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57242                                                      drive 0, 1 of HiZ on pin.                                                 */
57243 } GPIO_PINCFG54_OUTCFG54_Enum;
57244 
57245 /* =============================================  GPIO PINCFG54 IRPTEN54 [6..7]  ============================================= */
57246 typedef enum {                                  /*!< GPIO_PINCFG54_IRPTEN54                                                    */
57247   GPIO_PINCFG54_IRPTEN54_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57248   GPIO_PINCFG54_IRPTEN54_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57249                                                      on this GPIO                                                              */
57250   GPIO_PINCFG54_IRPTEN54_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57251                                                      on this GPIO                                                              */
57252   GPIO_PINCFG54_IRPTEN54_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57253                                                      GPIO                                                                      */
57254 } GPIO_PINCFG54_IRPTEN54_Enum;
57255 
57256 /* =============================================  GPIO PINCFG54 FNCSEL54 [0..3]  ============================================= */
57257 typedef enum {                                  /*!< GPIO_PINCFG54_FNCSEL54                                                    */
57258   GPIO_PINCFG54_FNCSEL54_PDM2_CLK      = 0,     /*!< PDM2_CLK : PDMx Clock output (I2C Master/Slave D)                         */
57259   GPIO_PINCFG54_FNCSEL54_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
57260   GPIO_PINCFG54_FNCSEL54_SWTRACE3      = 2,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
57261   GPIO_PINCFG54_FNCSEL54_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57262   GPIO_PINCFG54_FNCSEL54_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
57263   GPIO_PINCFG54_FNCSEL54_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
57264   GPIO_PINCFG54_FNCSEL54_CT54          = 6,     /*!< CT54 : Timer/Counter input or output; Selection of direction
57265                                                      is done via CTIMER register settings.                                     */
57266   GPIO_PINCFG54_FNCSEL54_NCE54         = 7,     /*!< NCE54 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57267                                                      CE_POLARITY field                                                         */
57268   GPIO_PINCFG54_FNCSEL54_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
57269   GPIO_PINCFG54_FNCSEL54_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57270   GPIO_PINCFG54_FNCSEL54_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57271   GPIO_PINCFG54_FNCSEL54_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57272   GPIO_PINCFG54_FNCSEL54_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57273   GPIO_PINCFG54_FNCSEL54_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57274   GPIO_PINCFG54_FNCSEL54_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57275   GPIO_PINCFG54_FNCSEL54_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57276 } GPIO_PINCFG54_FNCSEL54_Enum;
57277 
57278 /* =======================================================  PINCFG55  ======================================================== */
57279 /* ============================================  GPIO PINCFG55 NCEPOL55 [22..22]  ============================================ */
57280 typedef enum {                                  /*!< GPIO_PINCFG55_NCEPOL55                                                    */
57281   GPIO_PINCFG55_NCEPOL55_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57282   GPIO_PINCFG55_NCEPOL55_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57283 } GPIO_PINCFG55_NCEPOL55_Enum;
57284 
57285 /* ============================================  GPIO PINCFG55 NCESRC55 [16..21]  ============================================ */
57286 typedef enum {                                  /*!< GPIO_PINCFG55_NCESRC55                                                    */
57287   GPIO_PINCFG55_NCESRC55_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57288   GPIO_PINCFG55_NCESRC55_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57289   GPIO_PINCFG55_NCESRC55_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57290   GPIO_PINCFG55_NCESRC55_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57291   GPIO_PINCFG55_NCESRC55_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57292   GPIO_PINCFG55_NCESRC55_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57293   GPIO_PINCFG55_NCESRC55_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57294   GPIO_PINCFG55_NCESRC55_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57295   GPIO_PINCFG55_NCESRC55_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57296   GPIO_PINCFG55_NCESRC55_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57297   GPIO_PINCFG55_NCESRC55_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57298   GPIO_PINCFG55_NCESRC55_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57299   GPIO_PINCFG55_NCESRC55_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57300   GPIO_PINCFG55_NCESRC55_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57301   GPIO_PINCFG55_NCESRC55_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57302   GPIO_PINCFG55_NCESRC55_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57303   GPIO_PINCFG55_NCESRC55_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57304   GPIO_PINCFG55_NCESRC55_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57305   GPIO_PINCFG55_NCESRC55_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57306   GPIO_PINCFG55_NCESRC55_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57307   GPIO_PINCFG55_NCESRC55_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57308   GPIO_PINCFG55_NCESRC55_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57309   GPIO_PINCFG55_NCESRC55_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57310   GPIO_PINCFG55_NCESRC55_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57311   GPIO_PINCFG55_NCESRC55_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57312   GPIO_PINCFG55_NCESRC55_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57313   GPIO_PINCFG55_NCESRC55_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57314   GPIO_PINCFG55_NCESRC55_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57315   GPIO_PINCFG55_NCESRC55_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57316   GPIO_PINCFG55_NCESRC55_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57317   GPIO_PINCFG55_NCESRC55_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57318   GPIO_PINCFG55_NCESRC55_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57319   GPIO_PINCFG55_NCESRC55_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57320   GPIO_PINCFG55_NCESRC55_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57321   GPIO_PINCFG55_NCESRC55_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57322   GPIO_PINCFG55_NCESRC55_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57323   GPIO_PINCFG55_NCESRC55_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57324   GPIO_PINCFG55_NCESRC55_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57325   GPIO_PINCFG55_NCESRC55_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57326   GPIO_PINCFG55_NCESRC55_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57327   GPIO_PINCFG55_NCESRC55_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57328   GPIO_PINCFG55_NCESRC55_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57329   GPIO_PINCFG55_NCESRC55_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57330 } GPIO_PINCFG55_NCESRC55_Enum;
57331 
57332 /* ===========================================  GPIO PINCFG55 PULLCFG55 [13..15]  ============================================ */
57333 typedef enum {                                  /*!< GPIO_PINCFG55_PULLCFG55                                                   */
57334   GPIO_PINCFG55_PULLCFG55_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57335   GPIO_PINCFG55_PULLCFG55_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57336   GPIO_PINCFG55_PULLCFG55_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57337   GPIO_PINCFG55_PULLCFG55_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57338   GPIO_PINCFG55_PULLCFG55_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57339   GPIO_PINCFG55_PULLCFG55_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57340   GPIO_PINCFG55_PULLCFG55_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57341   GPIO_PINCFG55_PULLCFG55_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57342 } GPIO_PINCFG55_PULLCFG55_Enum;
57343 
57344 /* ==============================================  GPIO PINCFG55 DS55 [10..11]  ============================================== */
57345 typedef enum {                                  /*!< GPIO_PINCFG55_DS55                                                        */
57346   GPIO_PINCFG55_DS55_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57347   GPIO_PINCFG55_DS55_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57348   GPIO_PINCFG55_DS55_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57349   GPIO_PINCFG55_DS55_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57350 } GPIO_PINCFG55_DS55_Enum;
57351 
57352 /* =============================================  GPIO PINCFG55 OUTCFG55 [8..9]  ============================================= */
57353 typedef enum {                                  /*!< GPIO_PINCFG55_OUTCFG55                                                    */
57354   GPIO_PINCFG55_OUTCFG55_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57355   GPIO_PINCFG55_OUTCFG55_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57356                                                      and 1 values on pin.                                                      */
57357   GPIO_PINCFG55_OUTCFG55_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57358                                                      low, tristate otherwise.                                                  */
57359   GPIO_PINCFG55_OUTCFG55_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57360                                                      drive 0, 1 of HiZ on pin.                                                 */
57361 } GPIO_PINCFG55_OUTCFG55_Enum;
57362 
57363 /* =============================================  GPIO PINCFG55 IRPTEN55 [6..7]  ============================================= */
57364 typedef enum {                                  /*!< GPIO_PINCFG55_IRPTEN55                                                    */
57365   GPIO_PINCFG55_IRPTEN55_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57366   GPIO_PINCFG55_IRPTEN55_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57367                                                      on this GPIO                                                              */
57368   GPIO_PINCFG55_IRPTEN55_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57369                                                      on this GPIO                                                              */
57370   GPIO_PINCFG55_IRPTEN55_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57371                                                      GPIO                                                                      */
57372 } GPIO_PINCFG55_IRPTEN55_Enum;
57373 
57374 /* =============================================  GPIO PINCFG55 FNCSEL55 [0..3]  ============================================= */
57375 typedef enum {                                  /*!< GPIO_PINCFG55_FNCSEL55                                                    */
57376   GPIO_PINCFG55_FNCSEL55_PDM2_DATA     = 0,     /*!< PDM2_DATA : PDMx audio data input to chip (I2C Master/Slave
57377                                                      D)                                                                        */
57378   GPIO_PINCFG55_FNCSEL55_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
57379   GPIO_PINCFG55_FNCSEL55_SWTRACECTL    = 2,     /*!< SWTRACECTL : Serial Wire Debug Trace Control                              */
57380   GPIO_PINCFG55_FNCSEL55_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57381   GPIO_PINCFG55_FNCSEL55_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
57382   GPIO_PINCFG55_FNCSEL55_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
57383   GPIO_PINCFG55_FNCSEL55_CT55          = 6,     /*!< CT55 : Timer/Counter input or output; Selection of direction
57384                                                      is done via CTIMER register settings.                                     */
57385   GPIO_PINCFG55_FNCSEL55_NCE55         = 7,     /*!< NCE55 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57386                                                      CE_POLARITY field                                                         */
57387   GPIO_PINCFG55_FNCSEL55_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
57388   GPIO_PINCFG55_FNCSEL55_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57389   GPIO_PINCFG55_FNCSEL55_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57390   GPIO_PINCFG55_FNCSEL55_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57391   GPIO_PINCFG55_FNCSEL55_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57392   GPIO_PINCFG55_FNCSEL55_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57393   GPIO_PINCFG55_FNCSEL55_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57394   GPIO_PINCFG55_FNCSEL55_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57395 } GPIO_PINCFG55_FNCSEL55_Enum;
57396 
57397 /* =======================================================  PINCFG56  ======================================================== */
57398 /* ============================================  GPIO PINCFG56 NCEPOL56 [22..22]  ============================================ */
57399 typedef enum {                                  /*!< GPIO_PINCFG56_NCEPOL56                                                    */
57400   GPIO_PINCFG56_NCEPOL56_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57401   GPIO_PINCFG56_NCEPOL56_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57402 } GPIO_PINCFG56_NCEPOL56_Enum;
57403 
57404 /* ============================================  GPIO PINCFG56 NCESRC56 [16..21]  ============================================ */
57405 typedef enum {                                  /*!< GPIO_PINCFG56_NCESRC56                                                    */
57406   GPIO_PINCFG56_NCESRC56_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57407   GPIO_PINCFG56_NCESRC56_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57408   GPIO_PINCFG56_NCESRC56_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57409   GPIO_PINCFG56_NCESRC56_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57410   GPIO_PINCFG56_NCESRC56_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57411   GPIO_PINCFG56_NCESRC56_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57412   GPIO_PINCFG56_NCESRC56_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57413   GPIO_PINCFG56_NCESRC56_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57414   GPIO_PINCFG56_NCESRC56_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57415   GPIO_PINCFG56_NCESRC56_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57416   GPIO_PINCFG56_NCESRC56_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57417   GPIO_PINCFG56_NCESRC56_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57418   GPIO_PINCFG56_NCESRC56_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57419   GPIO_PINCFG56_NCESRC56_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57420   GPIO_PINCFG56_NCESRC56_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57421   GPIO_PINCFG56_NCESRC56_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57422   GPIO_PINCFG56_NCESRC56_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57423   GPIO_PINCFG56_NCESRC56_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57424   GPIO_PINCFG56_NCESRC56_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57425   GPIO_PINCFG56_NCESRC56_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57426   GPIO_PINCFG56_NCESRC56_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57427   GPIO_PINCFG56_NCESRC56_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57428   GPIO_PINCFG56_NCESRC56_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57429   GPIO_PINCFG56_NCESRC56_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57430   GPIO_PINCFG56_NCESRC56_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57431   GPIO_PINCFG56_NCESRC56_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57432   GPIO_PINCFG56_NCESRC56_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57433   GPIO_PINCFG56_NCESRC56_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57434   GPIO_PINCFG56_NCESRC56_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57435   GPIO_PINCFG56_NCESRC56_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57436   GPIO_PINCFG56_NCESRC56_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57437   GPIO_PINCFG56_NCESRC56_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57438   GPIO_PINCFG56_NCESRC56_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57439   GPIO_PINCFG56_NCESRC56_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57440   GPIO_PINCFG56_NCESRC56_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57441   GPIO_PINCFG56_NCESRC56_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57442   GPIO_PINCFG56_NCESRC56_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57443   GPIO_PINCFG56_NCESRC56_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57444   GPIO_PINCFG56_NCESRC56_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57445   GPIO_PINCFG56_NCESRC56_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57446   GPIO_PINCFG56_NCESRC56_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57447   GPIO_PINCFG56_NCESRC56_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57448   GPIO_PINCFG56_NCESRC56_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57449 } GPIO_PINCFG56_NCESRC56_Enum;
57450 
57451 /* ===========================================  GPIO PINCFG56 PULLCFG56 [13..15]  ============================================ */
57452 typedef enum {                                  /*!< GPIO_PINCFG56_PULLCFG56                                                   */
57453   GPIO_PINCFG56_PULLCFG56_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57454   GPIO_PINCFG56_PULLCFG56_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57455   GPIO_PINCFG56_PULLCFG56_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57456   GPIO_PINCFG56_PULLCFG56_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57457   GPIO_PINCFG56_PULLCFG56_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57458   GPIO_PINCFG56_PULLCFG56_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57459   GPIO_PINCFG56_PULLCFG56_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57460   GPIO_PINCFG56_PULLCFG56_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57461 } GPIO_PINCFG56_PULLCFG56_Enum;
57462 
57463 /* ==============================================  GPIO PINCFG56 DS56 [10..11]  ============================================== */
57464 typedef enum {                                  /*!< GPIO_PINCFG56_DS56                                                        */
57465   GPIO_PINCFG56_DS56_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57466   GPIO_PINCFG56_DS56_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57467   GPIO_PINCFG56_DS56_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57468   GPIO_PINCFG56_DS56_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57469 } GPIO_PINCFG56_DS56_Enum;
57470 
57471 /* =============================================  GPIO PINCFG56 OUTCFG56 [8..9]  ============================================= */
57472 typedef enum {                                  /*!< GPIO_PINCFG56_OUTCFG56                                                    */
57473   GPIO_PINCFG56_OUTCFG56_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57474   GPIO_PINCFG56_OUTCFG56_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57475                                                      and 1 values on pin.                                                      */
57476   GPIO_PINCFG56_OUTCFG56_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57477                                                      low, tristate otherwise.                                                  */
57478   GPIO_PINCFG56_OUTCFG56_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57479                                                      drive 0, 1 of HiZ on pin.                                                 */
57480 } GPIO_PINCFG56_OUTCFG56_Enum;
57481 
57482 /* =============================================  GPIO PINCFG56 IRPTEN56 [6..7]  ============================================= */
57483 typedef enum {                                  /*!< GPIO_PINCFG56_IRPTEN56                                                    */
57484   GPIO_PINCFG56_IRPTEN56_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57485   GPIO_PINCFG56_IRPTEN56_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57486                                                      on this GPIO                                                              */
57487   GPIO_PINCFG56_IRPTEN56_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57488                                                      on this GPIO                                                              */
57489   GPIO_PINCFG56_IRPTEN56_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57490                                                      GPIO                                                                      */
57491 } GPIO_PINCFG56_IRPTEN56_Enum;
57492 
57493 /* =============================================  GPIO PINCFG56 FNCSEL56 [0..3]  ============================================= */
57494 typedef enum {                                  /*!< GPIO_PINCFG56_FNCSEL56                                                    */
57495   GPIO_PINCFG56_FNCSEL56_PDM3_CLK      = 0,     /*!< PDM3_CLK : PDMx Clock output (I2C Master/Slave D)                         */
57496   GPIO_PINCFG56_FNCSEL56_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
57497   GPIO_PINCFG56_FNCSEL56_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
57498   GPIO_PINCFG56_FNCSEL56_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57499   GPIO_PINCFG56_FNCSEL56_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
57500   GPIO_PINCFG56_FNCSEL56_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
57501   GPIO_PINCFG56_FNCSEL56_CT56          = 6,     /*!< CT56 : Timer/Counter input or output; Selection of direction
57502                                                      is done via CTIMER register settings.                                     */
57503   GPIO_PINCFG56_FNCSEL56_NCE56         = 7,     /*!< NCE56 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57504                                                      CE_POLARITY field                                                         */
57505   GPIO_PINCFG56_FNCSEL56_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
57506   GPIO_PINCFG56_FNCSEL56_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57507   GPIO_PINCFG56_FNCSEL56_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57508   GPIO_PINCFG56_FNCSEL56_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57509   GPIO_PINCFG56_FNCSEL56_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57510   GPIO_PINCFG56_FNCSEL56_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57511   GPIO_PINCFG56_FNCSEL56_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57512   GPIO_PINCFG56_FNCSEL56_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57513 } GPIO_PINCFG56_FNCSEL56_Enum;
57514 
57515 /* =======================================================  PINCFG57  ======================================================== */
57516 /* ============================================  GPIO PINCFG57 NCEPOL57 [22..22]  ============================================ */
57517 typedef enum {                                  /*!< GPIO_PINCFG57_NCEPOL57                                                    */
57518   GPIO_PINCFG57_NCEPOL57_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57519   GPIO_PINCFG57_NCEPOL57_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57520 } GPIO_PINCFG57_NCEPOL57_Enum;
57521 
57522 /* ============================================  GPIO PINCFG57 NCESRC57 [16..21]  ============================================ */
57523 typedef enum {                                  /*!< GPIO_PINCFG57_NCESRC57                                                    */
57524   GPIO_PINCFG57_NCESRC57_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57525   GPIO_PINCFG57_NCESRC57_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57526   GPIO_PINCFG57_NCESRC57_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57527   GPIO_PINCFG57_NCESRC57_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57528   GPIO_PINCFG57_NCESRC57_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57529   GPIO_PINCFG57_NCESRC57_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57530   GPIO_PINCFG57_NCESRC57_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57531   GPIO_PINCFG57_NCESRC57_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57532   GPIO_PINCFG57_NCESRC57_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57533   GPIO_PINCFG57_NCESRC57_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57534   GPIO_PINCFG57_NCESRC57_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57535   GPIO_PINCFG57_NCESRC57_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57536   GPIO_PINCFG57_NCESRC57_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57537   GPIO_PINCFG57_NCESRC57_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57538   GPIO_PINCFG57_NCESRC57_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57539   GPIO_PINCFG57_NCESRC57_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57540   GPIO_PINCFG57_NCESRC57_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57541   GPIO_PINCFG57_NCESRC57_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57542   GPIO_PINCFG57_NCESRC57_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57543   GPIO_PINCFG57_NCESRC57_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57544   GPIO_PINCFG57_NCESRC57_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57545   GPIO_PINCFG57_NCESRC57_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57546   GPIO_PINCFG57_NCESRC57_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57547   GPIO_PINCFG57_NCESRC57_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57548   GPIO_PINCFG57_NCESRC57_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57549   GPIO_PINCFG57_NCESRC57_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57550   GPIO_PINCFG57_NCESRC57_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57551   GPIO_PINCFG57_NCESRC57_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57552   GPIO_PINCFG57_NCESRC57_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57553   GPIO_PINCFG57_NCESRC57_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57554   GPIO_PINCFG57_NCESRC57_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57555   GPIO_PINCFG57_NCESRC57_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57556   GPIO_PINCFG57_NCESRC57_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57557   GPIO_PINCFG57_NCESRC57_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57558   GPIO_PINCFG57_NCESRC57_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57559   GPIO_PINCFG57_NCESRC57_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57560   GPIO_PINCFG57_NCESRC57_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57561   GPIO_PINCFG57_NCESRC57_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57562   GPIO_PINCFG57_NCESRC57_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57563   GPIO_PINCFG57_NCESRC57_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57564   GPIO_PINCFG57_NCESRC57_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57565   GPIO_PINCFG57_NCESRC57_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57566   GPIO_PINCFG57_NCESRC57_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57567 } GPIO_PINCFG57_NCESRC57_Enum;
57568 
57569 /* ===========================================  GPIO PINCFG57 PULLCFG57 [13..15]  ============================================ */
57570 typedef enum {                                  /*!< GPIO_PINCFG57_PULLCFG57                                                   */
57571   GPIO_PINCFG57_PULLCFG57_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57572   GPIO_PINCFG57_PULLCFG57_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57573   GPIO_PINCFG57_PULLCFG57_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57574   GPIO_PINCFG57_PULLCFG57_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57575   GPIO_PINCFG57_PULLCFG57_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57576   GPIO_PINCFG57_PULLCFG57_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57577   GPIO_PINCFG57_PULLCFG57_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57578   GPIO_PINCFG57_PULLCFG57_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57579 } GPIO_PINCFG57_PULLCFG57_Enum;
57580 
57581 /* ==============================================  GPIO PINCFG57 DS57 [10..11]  ============================================== */
57582 typedef enum {                                  /*!< GPIO_PINCFG57_DS57                                                        */
57583   GPIO_PINCFG57_DS57_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57584   GPIO_PINCFG57_DS57_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57585   GPIO_PINCFG57_DS57_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
57586   GPIO_PINCFG57_DS57_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
57587 } GPIO_PINCFG57_DS57_Enum;
57588 
57589 /* =============================================  GPIO PINCFG57 OUTCFG57 [8..9]  ============================================= */
57590 typedef enum {                                  /*!< GPIO_PINCFG57_OUTCFG57                                                    */
57591   GPIO_PINCFG57_OUTCFG57_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57592   GPIO_PINCFG57_OUTCFG57_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57593                                                      and 1 values on pin.                                                      */
57594   GPIO_PINCFG57_OUTCFG57_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57595                                                      low, tristate otherwise.                                                  */
57596   GPIO_PINCFG57_OUTCFG57_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57597                                                      drive 0, 1 of HiZ on pin.                                                 */
57598 } GPIO_PINCFG57_OUTCFG57_Enum;
57599 
57600 /* =============================================  GPIO PINCFG57 IRPTEN57 [6..7]  ============================================= */
57601 typedef enum {                                  /*!< GPIO_PINCFG57_IRPTEN57                                                    */
57602   GPIO_PINCFG57_IRPTEN57_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57603   GPIO_PINCFG57_IRPTEN57_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57604                                                      on this GPIO                                                              */
57605   GPIO_PINCFG57_IRPTEN57_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57606                                                      on this GPIO                                                              */
57607   GPIO_PINCFG57_IRPTEN57_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57608                                                      GPIO                                                                      */
57609 } GPIO_PINCFG57_IRPTEN57_Enum;
57610 
57611 /* =============================================  GPIO PINCFG57 FNCSEL57 [0..3]  ============================================= */
57612 typedef enum {                                  /*!< GPIO_PINCFG57_FNCSEL57                                                    */
57613   GPIO_PINCFG57_FNCSEL57_PDM3_DATA     = 0,     /*!< PDM3_DATA : PDMx audio data input to chip (I2C Master/Slave
57614                                                      D)                                                                        */
57615   GPIO_PINCFG57_FNCSEL57_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
57616   GPIO_PINCFG57_FNCSEL57_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
57617   GPIO_PINCFG57_FNCSEL57_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57618   GPIO_PINCFG57_FNCSEL57_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
57619   GPIO_PINCFG57_FNCSEL57_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
57620   GPIO_PINCFG57_FNCSEL57_CT57          = 6,     /*!< CT57 : Timer/Counter input or output; Selection of direction
57621                                                      is done via CTIMER register settings.                                     */
57622   GPIO_PINCFG57_FNCSEL57_NCE57         = 7,     /*!< NCE57 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57623                                                      CE_POLARITY field                                                         */
57624   GPIO_PINCFG57_FNCSEL57_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
57625   GPIO_PINCFG57_FNCSEL57_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
57626   GPIO_PINCFG57_FNCSEL57_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57627   GPIO_PINCFG57_FNCSEL57_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57628   GPIO_PINCFG57_FNCSEL57_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57629   GPIO_PINCFG57_FNCSEL57_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57630   GPIO_PINCFG57_FNCSEL57_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57631   GPIO_PINCFG57_FNCSEL57_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57632 } GPIO_PINCFG57_FNCSEL57_Enum;
57633 
57634 /* =======================================================  PINCFG58  ======================================================== */
57635 /* ============================================  GPIO PINCFG58 NCEPOL58 [22..22]  ============================================ */
57636 typedef enum {                                  /*!< GPIO_PINCFG58_NCEPOL58                                                    */
57637   GPIO_PINCFG58_NCEPOL58_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57638   GPIO_PINCFG58_NCEPOL58_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57639 } GPIO_PINCFG58_NCEPOL58_Enum;
57640 
57641 /* ============================================  GPIO PINCFG58 NCESRC58 [16..21]  ============================================ */
57642 typedef enum {                                  /*!< GPIO_PINCFG58_NCESRC58                                                    */
57643   GPIO_PINCFG58_NCESRC58_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57644   GPIO_PINCFG58_NCESRC58_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57645   GPIO_PINCFG58_NCESRC58_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57646   GPIO_PINCFG58_NCESRC58_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57647   GPIO_PINCFG58_NCESRC58_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57648   GPIO_PINCFG58_NCESRC58_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57649   GPIO_PINCFG58_NCESRC58_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57650   GPIO_PINCFG58_NCESRC58_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57651   GPIO_PINCFG58_NCESRC58_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57652   GPIO_PINCFG58_NCESRC58_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57653   GPIO_PINCFG58_NCESRC58_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57654   GPIO_PINCFG58_NCESRC58_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57655   GPIO_PINCFG58_NCESRC58_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57656   GPIO_PINCFG58_NCESRC58_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57657   GPIO_PINCFG58_NCESRC58_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57658   GPIO_PINCFG58_NCESRC58_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57659   GPIO_PINCFG58_NCESRC58_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57660   GPIO_PINCFG58_NCESRC58_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57661   GPIO_PINCFG58_NCESRC58_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57662   GPIO_PINCFG58_NCESRC58_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57663   GPIO_PINCFG58_NCESRC58_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57664   GPIO_PINCFG58_NCESRC58_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57665   GPIO_PINCFG58_NCESRC58_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57666   GPIO_PINCFG58_NCESRC58_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57667   GPIO_PINCFG58_NCESRC58_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57668   GPIO_PINCFG58_NCESRC58_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57669   GPIO_PINCFG58_NCESRC58_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57670   GPIO_PINCFG58_NCESRC58_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57671   GPIO_PINCFG58_NCESRC58_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57672   GPIO_PINCFG58_NCESRC58_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57673   GPIO_PINCFG58_NCESRC58_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57674   GPIO_PINCFG58_NCESRC58_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57675   GPIO_PINCFG58_NCESRC58_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57676   GPIO_PINCFG58_NCESRC58_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57677   GPIO_PINCFG58_NCESRC58_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57678   GPIO_PINCFG58_NCESRC58_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57679   GPIO_PINCFG58_NCESRC58_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57680   GPIO_PINCFG58_NCESRC58_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57681   GPIO_PINCFG58_NCESRC58_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57682   GPIO_PINCFG58_NCESRC58_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57683   GPIO_PINCFG58_NCESRC58_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57684   GPIO_PINCFG58_NCESRC58_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57685   GPIO_PINCFG58_NCESRC58_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57686 } GPIO_PINCFG58_NCESRC58_Enum;
57687 
57688 /* ===========================================  GPIO PINCFG58 PULLCFG58 [13..15]  ============================================ */
57689 typedef enum {                                  /*!< GPIO_PINCFG58_PULLCFG58                                                   */
57690   GPIO_PINCFG58_PULLCFG58_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57691   GPIO_PINCFG58_PULLCFG58_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57692   GPIO_PINCFG58_PULLCFG58_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57693   GPIO_PINCFG58_PULLCFG58_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57694   GPIO_PINCFG58_PULLCFG58_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57695   GPIO_PINCFG58_PULLCFG58_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57696   GPIO_PINCFG58_PULLCFG58_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57697   GPIO_PINCFG58_PULLCFG58_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57698 } GPIO_PINCFG58_PULLCFG58_Enum;
57699 
57700 /* ==============================================  GPIO PINCFG58 DS58 [10..11]  ============================================== */
57701 typedef enum {                                  /*!< GPIO_PINCFG58_DS58                                                        */
57702   GPIO_PINCFG58_DS58_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57703   GPIO_PINCFG58_DS58_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57704 } GPIO_PINCFG58_DS58_Enum;
57705 
57706 /* =============================================  GPIO PINCFG58 OUTCFG58 [8..9]  ============================================= */
57707 typedef enum {                                  /*!< GPIO_PINCFG58_OUTCFG58                                                    */
57708   GPIO_PINCFG58_OUTCFG58_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57709   GPIO_PINCFG58_OUTCFG58_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57710                                                      and 1 values on pin.                                                      */
57711   GPIO_PINCFG58_OUTCFG58_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57712                                                      low, tristate otherwise.                                                  */
57713   GPIO_PINCFG58_OUTCFG58_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57714                                                      drive 0, 1 of HiZ on pin.                                                 */
57715 } GPIO_PINCFG58_OUTCFG58_Enum;
57716 
57717 /* =============================================  GPIO PINCFG58 IRPTEN58 [6..7]  ============================================= */
57718 typedef enum {                                  /*!< GPIO_PINCFG58_IRPTEN58                                                    */
57719   GPIO_PINCFG58_IRPTEN58_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57720   GPIO_PINCFG58_IRPTEN58_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57721                                                      on this GPIO                                                              */
57722   GPIO_PINCFG58_IRPTEN58_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57723                                                      on this GPIO                                                              */
57724   GPIO_PINCFG58_IRPTEN58_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57725                                                      GPIO                                                                      */
57726 } GPIO_PINCFG58_IRPTEN58_Enum;
57727 
57728 /* =============================================  GPIO PINCFG58 FNCSEL58 [0..3]  ============================================= */
57729 typedef enum {                                  /*!< GPIO_PINCFG58_FNCSEL58                                                    */
57730   GPIO_PINCFG58_FNCSEL58_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
57731   GPIO_PINCFG58_FNCSEL58_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
57732   GPIO_PINCFG58_FNCSEL58_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
57733   GPIO_PINCFG58_FNCSEL58_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57734   GPIO_PINCFG58_FNCSEL58_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
57735   GPIO_PINCFG58_FNCSEL58_UART3RTS      = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
57736   GPIO_PINCFG58_FNCSEL58_CT58          = 6,     /*!< CT58 : Timer/Counter input or output; Selection of direction
57737                                                      is done via CTIMER register settings.                                     */
57738   GPIO_PINCFG58_FNCSEL58_NCE58         = 7,     /*!< NCE58 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57739                                                      CE_POLARITY field                                                         */
57740   GPIO_PINCFG58_FNCSEL58_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
57741   GPIO_PINCFG58_FNCSEL58_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57742   GPIO_PINCFG58_FNCSEL58_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57743   GPIO_PINCFG58_FNCSEL58_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57744   GPIO_PINCFG58_FNCSEL58_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57745   GPIO_PINCFG58_FNCSEL58_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57746   GPIO_PINCFG58_FNCSEL58_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57747   GPIO_PINCFG58_FNCSEL58_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57748 } GPIO_PINCFG58_FNCSEL58_Enum;
57749 
57750 /* =======================================================  PINCFG59  ======================================================== */
57751 /* ============================================  GPIO PINCFG59 NCEPOL59 [22..22]  ============================================ */
57752 typedef enum {                                  /*!< GPIO_PINCFG59_NCEPOL59                                                    */
57753   GPIO_PINCFG59_NCEPOL59_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57754   GPIO_PINCFG59_NCEPOL59_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57755 } GPIO_PINCFG59_NCEPOL59_Enum;
57756 
57757 /* ============================================  GPIO PINCFG59 NCESRC59 [16..21]  ============================================ */
57758 typedef enum {                                  /*!< GPIO_PINCFG59_NCESRC59                                                    */
57759   GPIO_PINCFG59_NCESRC59_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57760   GPIO_PINCFG59_NCESRC59_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57761   GPIO_PINCFG59_NCESRC59_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57762   GPIO_PINCFG59_NCESRC59_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57763   GPIO_PINCFG59_NCESRC59_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57764   GPIO_PINCFG59_NCESRC59_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57765   GPIO_PINCFG59_NCESRC59_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57766   GPIO_PINCFG59_NCESRC59_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57767   GPIO_PINCFG59_NCESRC59_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57768   GPIO_PINCFG59_NCESRC59_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57769   GPIO_PINCFG59_NCESRC59_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57770   GPIO_PINCFG59_NCESRC59_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57771   GPIO_PINCFG59_NCESRC59_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57772   GPIO_PINCFG59_NCESRC59_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57773   GPIO_PINCFG59_NCESRC59_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57774   GPIO_PINCFG59_NCESRC59_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57775   GPIO_PINCFG59_NCESRC59_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57776   GPIO_PINCFG59_NCESRC59_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57777   GPIO_PINCFG59_NCESRC59_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57778   GPIO_PINCFG59_NCESRC59_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57779   GPIO_PINCFG59_NCESRC59_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57780   GPIO_PINCFG59_NCESRC59_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57781   GPIO_PINCFG59_NCESRC59_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57782   GPIO_PINCFG59_NCESRC59_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57783   GPIO_PINCFG59_NCESRC59_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57784   GPIO_PINCFG59_NCESRC59_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57785   GPIO_PINCFG59_NCESRC59_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57786   GPIO_PINCFG59_NCESRC59_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57787   GPIO_PINCFG59_NCESRC59_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57788   GPIO_PINCFG59_NCESRC59_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57789   GPIO_PINCFG59_NCESRC59_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57790   GPIO_PINCFG59_NCESRC59_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57791   GPIO_PINCFG59_NCESRC59_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57792   GPIO_PINCFG59_NCESRC59_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57793   GPIO_PINCFG59_NCESRC59_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57794   GPIO_PINCFG59_NCESRC59_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57795   GPIO_PINCFG59_NCESRC59_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57796   GPIO_PINCFG59_NCESRC59_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57797   GPIO_PINCFG59_NCESRC59_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57798   GPIO_PINCFG59_NCESRC59_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57799   GPIO_PINCFG59_NCESRC59_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57800   GPIO_PINCFG59_NCESRC59_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57801   GPIO_PINCFG59_NCESRC59_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57802 } GPIO_PINCFG59_NCESRC59_Enum;
57803 
57804 /* ===========================================  GPIO PINCFG59 PULLCFG59 [13..15]  ============================================ */
57805 typedef enum {                                  /*!< GPIO_PINCFG59_PULLCFG59                                                   */
57806   GPIO_PINCFG59_PULLCFG59_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57807   GPIO_PINCFG59_PULLCFG59_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57808   GPIO_PINCFG59_PULLCFG59_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57809   GPIO_PINCFG59_PULLCFG59_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57810   GPIO_PINCFG59_PULLCFG59_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57811   GPIO_PINCFG59_PULLCFG59_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57812   GPIO_PINCFG59_PULLCFG59_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57813   GPIO_PINCFG59_PULLCFG59_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57814 } GPIO_PINCFG59_PULLCFG59_Enum;
57815 
57816 /* ==============================================  GPIO PINCFG59 DS59 [10..11]  ============================================== */
57817 typedef enum {                                  /*!< GPIO_PINCFG59_DS59                                                        */
57818   GPIO_PINCFG59_DS59_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57819   GPIO_PINCFG59_DS59_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57820 } GPIO_PINCFG59_DS59_Enum;
57821 
57822 /* =============================================  GPIO PINCFG59 OUTCFG59 [8..9]  ============================================= */
57823 typedef enum {                                  /*!< GPIO_PINCFG59_OUTCFG59                                                    */
57824   GPIO_PINCFG59_OUTCFG59_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57825   GPIO_PINCFG59_OUTCFG59_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57826                                                      and 1 values on pin.                                                      */
57827   GPIO_PINCFG59_OUTCFG59_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57828                                                      low, tristate otherwise.                                                  */
57829   GPIO_PINCFG59_OUTCFG59_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57830                                                      drive 0, 1 of HiZ on pin.                                                 */
57831 } GPIO_PINCFG59_OUTCFG59_Enum;
57832 
57833 /* =============================================  GPIO PINCFG59 IRPTEN59 [6..7]  ============================================= */
57834 typedef enum {                                  /*!< GPIO_PINCFG59_IRPTEN59                                                    */
57835   GPIO_PINCFG59_IRPTEN59_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57836   GPIO_PINCFG59_IRPTEN59_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57837                                                      on this GPIO                                                              */
57838   GPIO_PINCFG59_IRPTEN59_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57839                                                      on this GPIO                                                              */
57840   GPIO_PINCFG59_IRPTEN59_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57841                                                      GPIO                                                                      */
57842 } GPIO_PINCFG59_IRPTEN59_Enum;
57843 
57844 /* =============================================  GPIO PINCFG59 FNCSEL59 [0..3]  ============================================= */
57845 typedef enum {                                  /*!< GPIO_PINCFG59_FNCSEL59                                                    */
57846   GPIO_PINCFG59_FNCSEL59_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
57847   GPIO_PINCFG59_FNCSEL59_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
57848   GPIO_PINCFG59_FNCSEL59_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
57849   GPIO_PINCFG59_FNCSEL59_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57850   GPIO_PINCFG59_FNCSEL59_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
57851   GPIO_PINCFG59_FNCSEL59_UART1CTS      = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
57852   GPIO_PINCFG59_FNCSEL59_CT59          = 6,     /*!< CT59 : Timer/Counter input or output; Selection of direction
57853                                                      is done via CTIMER register settings.                                     */
57854   GPIO_PINCFG59_FNCSEL59_NCE59         = 7,     /*!< NCE59 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57855                                                      CE_POLARITY field                                                         */
57856   GPIO_PINCFG59_FNCSEL59_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
57857   GPIO_PINCFG59_FNCSEL59_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57858   GPIO_PINCFG59_FNCSEL59_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57859   GPIO_PINCFG59_FNCSEL59_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57860   GPIO_PINCFG59_FNCSEL59_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57861   GPIO_PINCFG59_FNCSEL59_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57862   GPIO_PINCFG59_FNCSEL59_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57863   GPIO_PINCFG59_FNCSEL59_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57864 } GPIO_PINCFG59_FNCSEL59_Enum;
57865 
57866 /* =======================================================  PINCFG60  ======================================================== */
57867 /* ============================================  GPIO PINCFG60 NCEPOL60 [22..22]  ============================================ */
57868 typedef enum {                                  /*!< GPIO_PINCFG60_NCEPOL60                                                    */
57869   GPIO_PINCFG60_NCEPOL60_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57870   GPIO_PINCFG60_NCEPOL60_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57871 } GPIO_PINCFG60_NCEPOL60_Enum;
57872 
57873 /* ============================================  GPIO PINCFG60 NCESRC60 [16..21]  ============================================ */
57874 typedef enum {                                  /*!< GPIO_PINCFG60_NCESRC60                                                    */
57875   GPIO_PINCFG60_NCESRC60_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57876   GPIO_PINCFG60_NCESRC60_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57877   GPIO_PINCFG60_NCESRC60_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57878   GPIO_PINCFG60_NCESRC60_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57879   GPIO_PINCFG60_NCESRC60_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57880   GPIO_PINCFG60_NCESRC60_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57881   GPIO_PINCFG60_NCESRC60_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57882   GPIO_PINCFG60_NCESRC60_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57883   GPIO_PINCFG60_NCESRC60_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
57884   GPIO_PINCFG60_NCESRC60_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
57885   GPIO_PINCFG60_NCESRC60_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
57886   GPIO_PINCFG60_NCESRC60_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
57887   GPIO_PINCFG60_NCESRC60_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
57888   GPIO_PINCFG60_NCESRC60_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
57889   GPIO_PINCFG60_NCESRC60_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
57890   GPIO_PINCFG60_NCESRC60_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
57891   GPIO_PINCFG60_NCESRC60_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
57892   GPIO_PINCFG60_NCESRC60_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
57893   GPIO_PINCFG60_NCESRC60_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
57894   GPIO_PINCFG60_NCESRC60_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
57895   GPIO_PINCFG60_NCESRC60_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
57896   GPIO_PINCFG60_NCESRC60_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
57897   GPIO_PINCFG60_NCESRC60_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
57898   GPIO_PINCFG60_NCESRC60_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
57899   GPIO_PINCFG60_NCESRC60_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
57900   GPIO_PINCFG60_NCESRC60_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
57901   GPIO_PINCFG60_NCESRC60_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
57902   GPIO_PINCFG60_NCESRC60_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
57903   GPIO_PINCFG60_NCESRC60_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
57904   GPIO_PINCFG60_NCESRC60_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
57905   GPIO_PINCFG60_NCESRC60_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
57906   GPIO_PINCFG60_NCESRC60_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
57907   GPIO_PINCFG60_NCESRC60_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
57908   GPIO_PINCFG60_NCESRC60_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
57909   GPIO_PINCFG60_NCESRC60_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
57910   GPIO_PINCFG60_NCESRC60_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
57911   GPIO_PINCFG60_NCESRC60_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
57912   GPIO_PINCFG60_NCESRC60_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
57913   GPIO_PINCFG60_NCESRC60_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
57914   GPIO_PINCFG60_NCESRC60_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
57915   GPIO_PINCFG60_NCESRC60_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
57916   GPIO_PINCFG60_NCESRC60_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
57917   GPIO_PINCFG60_NCESRC60_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
57918 } GPIO_PINCFG60_NCESRC60_Enum;
57919 
57920 /* ===========================================  GPIO PINCFG60 PULLCFG60 [13..15]  ============================================ */
57921 typedef enum {                                  /*!< GPIO_PINCFG60_PULLCFG60                                                   */
57922   GPIO_PINCFG60_PULLCFG60_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
57923   GPIO_PINCFG60_PULLCFG60_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
57924   GPIO_PINCFG60_PULLCFG60_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
57925   GPIO_PINCFG60_PULLCFG60_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
57926   GPIO_PINCFG60_PULLCFG60_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
57927   GPIO_PINCFG60_PULLCFG60_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
57928   GPIO_PINCFG60_PULLCFG60_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
57929   GPIO_PINCFG60_PULLCFG60_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
57930 } GPIO_PINCFG60_PULLCFG60_Enum;
57931 
57932 /* ==============================================  GPIO PINCFG60 DS60 [10..11]  ============================================== */
57933 typedef enum {                                  /*!< GPIO_PINCFG60_DS60                                                        */
57934   GPIO_PINCFG60_DS60_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
57935   GPIO_PINCFG60_DS60_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
57936 } GPIO_PINCFG60_DS60_Enum;
57937 
57938 /* =============================================  GPIO PINCFG60 OUTCFG60 [8..9]  ============================================= */
57939 typedef enum {                                  /*!< GPIO_PINCFG60_OUTCFG60                                                    */
57940   GPIO_PINCFG60_OUTCFG60_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
57941   GPIO_PINCFG60_OUTCFG60_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
57942                                                      and 1 values on pin.                                                      */
57943   GPIO_PINCFG60_OUTCFG60_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
57944                                                      low, tristate otherwise.                                                  */
57945   GPIO_PINCFG60_OUTCFG60_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
57946                                                      drive 0, 1 of HiZ on pin.                                                 */
57947 } GPIO_PINCFG60_OUTCFG60_Enum;
57948 
57949 /* =============================================  GPIO PINCFG60 IRPTEN60 [6..7]  ============================================= */
57950 typedef enum {                                  /*!< GPIO_PINCFG60_IRPTEN60                                                    */
57951   GPIO_PINCFG60_IRPTEN60_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
57952   GPIO_PINCFG60_IRPTEN60_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
57953                                                      on this GPIO                                                              */
57954   GPIO_PINCFG60_IRPTEN60_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
57955                                                      on this GPIO                                                              */
57956   GPIO_PINCFG60_IRPTEN60_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
57957                                                      GPIO                                                                      */
57958 } GPIO_PINCFG60_IRPTEN60_Enum;
57959 
57960 /* =============================================  GPIO PINCFG60 FNCSEL60 [0..3]  ============================================= */
57961 typedef enum {                                  /*!< GPIO_PINCFG60_FNCSEL60                                                    */
57962   GPIO_PINCFG60_FNCSEL60_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
57963   GPIO_PINCFG60_FNCSEL60_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
57964   GPIO_PINCFG60_FNCSEL60_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
57965   GPIO_PINCFG60_FNCSEL60_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
57966   GPIO_PINCFG60_FNCSEL60_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
57967   GPIO_PINCFG60_FNCSEL60_UART3CTS      = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
57968   GPIO_PINCFG60_FNCSEL60_CT60          = 6,     /*!< CT60 : Timer/Counter input or output; Selection of direction
57969                                                      is done via CTIMER register settings.                                     */
57970   GPIO_PINCFG60_FNCSEL60_NCE60         = 7,     /*!< NCE60 : IOMSTR/MSPI N Chip Select. Polarity is determined by
57971                                                      CE_POLARITY field                                                         */
57972   GPIO_PINCFG60_FNCSEL60_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
57973   GPIO_PINCFG60_FNCSEL60_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
57974   GPIO_PINCFG60_FNCSEL60_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
57975   GPIO_PINCFG60_FNCSEL60_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
57976   GPIO_PINCFG60_FNCSEL60_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
57977   GPIO_PINCFG60_FNCSEL60_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
57978   GPIO_PINCFG60_FNCSEL60_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
57979   GPIO_PINCFG60_FNCSEL60_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
57980 } GPIO_PINCFG60_FNCSEL60_Enum;
57981 
57982 /* =======================================================  PINCFG61  ======================================================== */
57983 /* ============================================  GPIO PINCFG61 NCEPOL61 [22..22]  ============================================ */
57984 typedef enum {                                  /*!< GPIO_PINCFG61_NCEPOL61                                                    */
57985   GPIO_PINCFG61_NCEPOL61_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
57986   GPIO_PINCFG61_NCEPOL61_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
57987 } GPIO_PINCFG61_NCEPOL61_Enum;
57988 
57989 /* ============================================  GPIO PINCFG61 NCESRC61 [16..21]  ============================================ */
57990 typedef enum {                                  /*!< GPIO_PINCFG61_NCESRC61                                                    */
57991   GPIO_PINCFG61_NCESRC61_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
57992   GPIO_PINCFG61_NCESRC61_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
57993   GPIO_PINCFG61_NCESRC61_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
57994   GPIO_PINCFG61_NCESRC61_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
57995   GPIO_PINCFG61_NCESRC61_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
57996   GPIO_PINCFG61_NCESRC61_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
57997   GPIO_PINCFG61_NCESRC61_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
57998   GPIO_PINCFG61_NCESRC61_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
57999   GPIO_PINCFG61_NCESRC61_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58000   GPIO_PINCFG61_NCESRC61_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58001   GPIO_PINCFG61_NCESRC61_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58002   GPIO_PINCFG61_NCESRC61_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58003   GPIO_PINCFG61_NCESRC61_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58004   GPIO_PINCFG61_NCESRC61_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58005   GPIO_PINCFG61_NCESRC61_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58006   GPIO_PINCFG61_NCESRC61_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58007   GPIO_PINCFG61_NCESRC61_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58008   GPIO_PINCFG61_NCESRC61_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58009   GPIO_PINCFG61_NCESRC61_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58010   GPIO_PINCFG61_NCESRC61_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58011   GPIO_PINCFG61_NCESRC61_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58012   GPIO_PINCFG61_NCESRC61_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58013   GPIO_PINCFG61_NCESRC61_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58014   GPIO_PINCFG61_NCESRC61_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58015   GPIO_PINCFG61_NCESRC61_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58016   GPIO_PINCFG61_NCESRC61_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58017   GPIO_PINCFG61_NCESRC61_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58018   GPIO_PINCFG61_NCESRC61_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58019   GPIO_PINCFG61_NCESRC61_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58020   GPIO_PINCFG61_NCESRC61_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58021   GPIO_PINCFG61_NCESRC61_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58022   GPIO_PINCFG61_NCESRC61_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58023   GPIO_PINCFG61_NCESRC61_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58024   GPIO_PINCFG61_NCESRC61_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58025   GPIO_PINCFG61_NCESRC61_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58026   GPIO_PINCFG61_NCESRC61_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58027   GPIO_PINCFG61_NCESRC61_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58028   GPIO_PINCFG61_NCESRC61_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58029   GPIO_PINCFG61_NCESRC61_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58030   GPIO_PINCFG61_NCESRC61_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58031   GPIO_PINCFG61_NCESRC61_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58032   GPIO_PINCFG61_NCESRC61_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58033   GPIO_PINCFG61_NCESRC61_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58034 } GPIO_PINCFG61_NCESRC61_Enum;
58035 
58036 /* ===========================================  GPIO PINCFG61 PULLCFG61 [13..15]  ============================================ */
58037 typedef enum {                                  /*!< GPIO_PINCFG61_PULLCFG61                                                   */
58038   GPIO_PINCFG61_PULLCFG61_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58039   GPIO_PINCFG61_PULLCFG61_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58040   GPIO_PINCFG61_PULLCFG61_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58041   GPIO_PINCFG61_PULLCFG61_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58042   GPIO_PINCFG61_PULLCFG61_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58043   GPIO_PINCFG61_PULLCFG61_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58044   GPIO_PINCFG61_PULLCFG61_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58045   GPIO_PINCFG61_PULLCFG61_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58046 } GPIO_PINCFG61_PULLCFG61_Enum;
58047 
58048 /* ==============================================  GPIO PINCFG61 DS61 [10..11]  ============================================== */
58049 typedef enum {                                  /*!< GPIO_PINCFG61_DS61                                                        */
58050   GPIO_PINCFG61_DS61_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58051   GPIO_PINCFG61_DS61_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58052   GPIO_PINCFG61_DS61_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58053   GPIO_PINCFG61_DS61_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58054 } GPIO_PINCFG61_DS61_Enum;
58055 
58056 /* =============================================  GPIO PINCFG61 OUTCFG61 [8..9]  ============================================= */
58057 typedef enum {                                  /*!< GPIO_PINCFG61_OUTCFG61                                                    */
58058   GPIO_PINCFG61_OUTCFG61_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58059   GPIO_PINCFG61_OUTCFG61_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58060                                                      and 1 values on pin.                                                      */
58061   GPIO_PINCFG61_OUTCFG61_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58062                                                      low, tristate otherwise.                                                  */
58063   GPIO_PINCFG61_OUTCFG61_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58064                                                      drive 0, 1 of HiZ on pin.                                                 */
58065 } GPIO_PINCFG61_OUTCFG61_Enum;
58066 
58067 /* =============================================  GPIO PINCFG61 IRPTEN61 [6..7]  ============================================= */
58068 typedef enum {                                  /*!< GPIO_PINCFG61_IRPTEN61                                                    */
58069   GPIO_PINCFG61_IRPTEN61_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58070   GPIO_PINCFG61_IRPTEN61_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58071                                                      on this GPIO                                                              */
58072   GPIO_PINCFG61_IRPTEN61_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58073                                                      on this GPIO                                                              */
58074   GPIO_PINCFG61_IRPTEN61_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58075                                                      GPIO                                                                      */
58076 } GPIO_PINCFG61_IRPTEN61_Enum;
58077 
58078 /* =============================================  GPIO PINCFG61 FNCSEL61 [0..3]  ============================================= */
58079 typedef enum {                                  /*!< GPIO_PINCFG61_FNCSEL61                                                    */
58080   GPIO_PINCFG61_FNCSEL61_M6SCL         = 0,     /*!< M6SCL : Serial I2C Master Clock output (IOM 6)                            */
58081   GPIO_PINCFG61_FNCSEL61_M6SCK         = 1,     /*!< M6SCK : Serial SPI Master Clock output (IOM 6)                            */
58082   GPIO_PINCFG61_FNCSEL61_I2S1_CLK      = 2,     /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
58083                                                      in master mode and input mode for slave mode. (I2S Master/Slave
58084                                                      2)                                                                        */
58085   GPIO_PINCFG61_FNCSEL61_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58086   GPIO_PINCFG61_FNCSEL61_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
58087   GPIO_PINCFG61_FNCSEL61_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
58088   GPIO_PINCFG61_FNCSEL61_CT61          = 6,     /*!< CT61 : Timer/Counter input or output; Selection of direction
58089                                                      is done via CTIMER register settings.                                     */
58090   GPIO_PINCFG61_FNCSEL61_NCE61         = 7,     /*!< NCE61 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58091                                                      CE_POLARITY field                                                         */
58092   GPIO_PINCFG61_FNCSEL61_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
58093   GPIO_PINCFG61_FNCSEL61_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58094   GPIO_PINCFG61_FNCSEL61_I3CM0_SCL     = 10,    /*!< I3CM0_SCL : Serial I3C Master Clock output (IOM 0)                        */
58095   GPIO_PINCFG61_FNCSEL61_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58096   GPIO_PINCFG61_FNCSEL61_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58097   GPIO_PINCFG61_FNCSEL61_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58098   GPIO_PINCFG61_FNCSEL61_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58099   GPIO_PINCFG61_FNCSEL61_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58100 } GPIO_PINCFG61_FNCSEL61_Enum;
58101 
58102 /* =======================================================  PINCFG62  ======================================================== */
58103 /* ============================================  GPIO PINCFG62 NCEPOL62 [22..22]  ============================================ */
58104 typedef enum {                                  /*!< GPIO_PINCFG62_NCEPOL62                                                    */
58105   GPIO_PINCFG62_NCEPOL62_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58106   GPIO_PINCFG62_NCEPOL62_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58107 } GPIO_PINCFG62_NCEPOL62_Enum;
58108 
58109 /* ============================================  GPIO PINCFG62 NCESRC62 [16..21]  ============================================ */
58110 typedef enum {                                  /*!< GPIO_PINCFG62_NCESRC62                                                    */
58111   GPIO_PINCFG62_NCESRC62_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58112   GPIO_PINCFG62_NCESRC62_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58113   GPIO_PINCFG62_NCESRC62_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58114   GPIO_PINCFG62_NCESRC62_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58115   GPIO_PINCFG62_NCESRC62_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58116   GPIO_PINCFG62_NCESRC62_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58117   GPIO_PINCFG62_NCESRC62_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58118   GPIO_PINCFG62_NCESRC62_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58119   GPIO_PINCFG62_NCESRC62_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58120   GPIO_PINCFG62_NCESRC62_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58121   GPIO_PINCFG62_NCESRC62_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58122   GPIO_PINCFG62_NCESRC62_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58123   GPIO_PINCFG62_NCESRC62_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58124   GPIO_PINCFG62_NCESRC62_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58125   GPIO_PINCFG62_NCESRC62_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58126   GPIO_PINCFG62_NCESRC62_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58127   GPIO_PINCFG62_NCESRC62_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58128   GPIO_PINCFG62_NCESRC62_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58129   GPIO_PINCFG62_NCESRC62_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58130   GPIO_PINCFG62_NCESRC62_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58131   GPIO_PINCFG62_NCESRC62_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58132   GPIO_PINCFG62_NCESRC62_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58133   GPIO_PINCFG62_NCESRC62_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58134   GPIO_PINCFG62_NCESRC62_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58135   GPIO_PINCFG62_NCESRC62_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58136   GPIO_PINCFG62_NCESRC62_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58137   GPIO_PINCFG62_NCESRC62_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58138   GPIO_PINCFG62_NCESRC62_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58139   GPIO_PINCFG62_NCESRC62_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58140   GPIO_PINCFG62_NCESRC62_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58141   GPIO_PINCFG62_NCESRC62_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58142   GPIO_PINCFG62_NCESRC62_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58143   GPIO_PINCFG62_NCESRC62_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58144   GPIO_PINCFG62_NCESRC62_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58145   GPIO_PINCFG62_NCESRC62_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58146   GPIO_PINCFG62_NCESRC62_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58147   GPIO_PINCFG62_NCESRC62_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58148   GPIO_PINCFG62_NCESRC62_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58149   GPIO_PINCFG62_NCESRC62_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58150   GPIO_PINCFG62_NCESRC62_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58151   GPIO_PINCFG62_NCESRC62_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58152   GPIO_PINCFG62_NCESRC62_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58153   GPIO_PINCFG62_NCESRC62_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58154 } GPIO_PINCFG62_NCESRC62_Enum;
58155 
58156 /* ===========================================  GPIO PINCFG62 PULLCFG62 [13..15]  ============================================ */
58157 typedef enum {                                  /*!< GPIO_PINCFG62_PULLCFG62                                                   */
58158   GPIO_PINCFG62_PULLCFG62_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58159   GPIO_PINCFG62_PULLCFG62_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58160   GPIO_PINCFG62_PULLCFG62_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58161   GPIO_PINCFG62_PULLCFG62_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58162   GPIO_PINCFG62_PULLCFG62_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58163   GPIO_PINCFG62_PULLCFG62_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58164   GPIO_PINCFG62_PULLCFG62_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58165   GPIO_PINCFG62_PULLCFG62_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58166 } GPIO_PINCFG62_PULLCFG62_Enum;
58167 
58168 /* ==============================================  GPIO PINCFG62 DS62 [10..11]  ============================================== */
58169 typedef enum {                                  /*!< GPIO_PINCFG62_DS62                                                        */
58170   GPIO_PINCFG62_DS62_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58171   GPIO_PINCFG62_DS62_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58172   GPIO_PINCFG62_DS62_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58173   GPIO_PINCFG62_DS62_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58174 } GPIO_PINCFG62_DS62_Enum;
58175 
58176 /* =============================================  GPIO PINCFG62 OUTCFG62 [8..9]  ============================================= */
58177 typedef enum {                                  /*!< GPIO_PINCFG62_OUTCFG62                                                    */
58178   GPIO_PINCFG62_OUTCFG62_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58179   GPIO_PINCFG62_OUTCFG62_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58180                                                      and 1 values on pin.                                                      */
58181   GPIO_PINCFG62_OUTCFG62_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58182                                                      low, tristate otherwise.                                                  */
58183   GPIO_PINCFG62_OUTCFG62_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58184                                                      drive 0, 1 of HiZ on pin.                                                 */
58185 } GPIO_PINCFG62_OUTCFG62_Enum;
58186 
58187 /* =============================================  GPIO PINCFG62 IRPTEN62 [6..7]  ============================================= */
58188 typedef enum {                                  /*!< GPIO_PINCFG62_IRPTEN62                                                    */
58189   GPIO_PINCFG62_IRPTEN62_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58190   GPIO_PINCFG62_IRPTEN62_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58191                                                      on this GPIO                                                              */
58192   GPIO_PINCFG62_IRPTEN62_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58193                                                      on this GPIO                                                              */
58194   GPIO_PINCFG62_IRPTEN62_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58195                                                      GPIO                                                                      */
58196 } GPIO_PINCFG62_IRPTEN62_Enum;
58197 
58198 /* =============================================  GPIO PINCFG62 FNCSEL62 [0..3]  ============================================= */
58199 typedef enum {                                  /*!< GPIO_PINCFG62_FNCSEL62                                                    */
58200   GPIO_PINCFG62_FNCSEL62_M6SDAWIR3     = 0,     /*!< M6SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
58201                                                      Master Data I/O (SPI 3 wire mode) (IOM 6)                                 */
58202   GPIO_PINCFG62_FNCSEL62_M6MOSI        = 1,     /*!< M6MOSI : Serial SPI Master MOSI output (IOM 6)                            */
58203   GPIO_PINCFG62_FNCSEL62_I2S1_DATA     = 2,     /*!< I2S1_DATA : Bidirectional I2S Data. Operates in output mode
58204                                                      in master mode and input mode for slave mode. (I2S Master/Slave
58205                                                      2)                                                                        */
58206   GPIO_PINCFG62_FNCSEL62_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58207   GPIO_PINCFG62_FNCSEL62_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
58208   GPIO_PINCFG62_FNCSEL62_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
58209   GPIO_PINCFG62_FNCSEL62_CT62          = 6,     /*!< CT62 : Timer/Counter input or output; Selection of direction
58210                                                      is done via CTIMER register settings.                                     */
58211   GPIO_PINCFG62_FNCSEL62_NCE62         = 7,     /*!< NCE62 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58212                                                      CE_POLARITY field                                                         */
58213   GPIO_PINCFG62_FNCSEL62_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
58214   GPIO_PINCFG62_FNCSEL62_I2S1_SDOUT    = 9,     /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
58215   GPIO_PINCFG62_FNCSEL62_I3CM0_SDA     = 10,    /*!< I3CM0_SDA : Serial I3C Master Data I/O (IOM 0)                            */
58216   GPIO_PINCFG62_FNCSEL62_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58217   GPIO_PINCFG62_FNCSEL62_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58218   GPIO_PINCFG62_FNCSEL62_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58219   GPIO_PINCFG62_FNCSEL62_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58220   GPIO_PINCFG62_FNCSEL62_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58221 } GPIO_PINCFG62_FNCSEL62_Enum;
58222 
58223 /* =======================================================  PINCFG63  ======================================================== */
58224 /* ============================================  GPIO PINCFG63 NCEPOL63 [22..22]  ============================================ */
58225 typedef enum {                                  /*!< GPIO_PINCFG63_NCEPOL63                                                    */
58226   GPIO_PINCFG63_NCEPOL63_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58227   GPIO_PINCFG63_NCEPOL63_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58228 } GPIO_PINCFG63_NCEPOL63_Enum;
58229 
58230 /* ============================================  GPIO PINCFG63 NCESRC63 [16..21]  ============================================ */
58231 typedef enum {                                  /*!< GPIO_PINCFG63_NCESRC63                                                    */
58232   GPIO_PINCFG63_NCESRC63_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58233   GPIO_PINCFG63_NCESRC63_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58234   GPIO_PINCFG63_NCESRC63_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58235   GPIO_PINCFG63_NCESRC63_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58236   GPIO_PINCFG63_NCESRC63_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58237   GPIO_PINCFG63_NCESRC63_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58238   GPIO_PINCFG63_NCESRC63_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58239   GPIO_PINCFG63_NCESRC63_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58240   GPIO_PINCFG63_NCESRC63_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58241   GPIO_PINCFG63_NCESRC63_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58242   GPIO_PINCFG63_NCESRC63_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58243   GPIO_PINCFG63_NCESRC63_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58244   GPIO_PINCFG63_NCESRC63_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58245   GPIO_PINCFG63_NCESRC63_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58246   GPIO_PINCFG63_NCESRC63_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58247   GPIO_PINCFG63_NCESRC63_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58248   GPIO_PINCFG63_NCESRC63_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58249   GPIO_PINCFG63_NCESRC63_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58250   GPIO_PINCFG63_NCESRC63_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58251   GPIO_PINCFG63_NCESRC63_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58252   GPIO_PINCFG63_NCESRC63_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58253   GPIO_PINCFG63_NCESRC63_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58254   GPIO_PINCFG63_NCESRC63_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58255   GPIO_PINCFG63_NCESRC63_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58256   GPIO_PINCFG63_NCESRC63_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58257   GPIO_PINCFG63_NCESRC63_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58258   GPIO_PINCFG63_NCESRC63_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58259   GPIO_PINCFG63_NCESRC63_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58260   GPIO_PINCFG63_NCESRC63_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58261   GPIO_PINCFG63_NCESRC63_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58262   GPIO_PINCFG63_NCESRC63_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58263   GPIO_PINCFG63_NCESRC63_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58264   GPIO_PINCFG63_NCESRC63_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58265   GPIO_PINCFG63_NCESRC63_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58266   GPIO_PINCFG63_NCESRC63_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58267   GPIO_PINCFG63_NCESRC63_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58268   GPIO_PINCFG63_NCESRC63_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58269   GPIO_PINCFG63_NCESRC63_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58270   GPIO_PINCFG63_NCESRC63_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58271   GPIO_PINCFG63_NCESRC63_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58272   GPIO_PINCFG63_NCESRC63_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58273   GPIO_PINCFG63_NCESRC63_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58274   GPIO_PINCFG63_NCESRC63_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58275 } GPIO_PINCFG63_NCESRC63_Enum;
58276 
58277 /* ===========================================  GPIO PINCFG63 PULLCFG63 [13..15]  ============================================ */
58278 typedef enum {                                  /*!< GPIO_PINCFG63_PULLCFG63                                                   */
58279   GPIO_PINCFG63_PULLCFG63_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58280   GPIO_PINCFG63_PULLCFG63_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58281   GPIO_PINCFG63_PULLCFG63_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58282   GPIO_PINCFG63_PULLCFG63_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58283   GPIO_PINCFG63_PULLCFG63_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58284   GPIO_PINCFG63_PULLCFG63_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58285   GPIO_PINCFG63_PULLCFG63_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58286   GPIO_PINCFG63_PULLCFG63_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58287 } GPIO_PINCFG63_PULLCFG63_Enum;
58288 
58289 /* ==============================================  GPIO PINCFG63 DS63 [10..11]  ============================================== */
58290 typedef enum {                                  /*!< GPIO_PINCFG63_DS63                                                        */
58291   GPIO_PINCFG63_DS63_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58292   GPIO_PINCFG63_DS63_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58293   GPIO_PINCFG63_DS63_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58294   GPIO_PINCFG63_DS63_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58295 } GPIO_PINCFG63_DS63_Enum;
58296 
58297 /* =============================================  GPIO PINCFG63 OUTCFG63 [8..9]  ============================================= */
58298 typedef enum {                                  /*!< GPIO_PINCFG63_OUTCFG63                                                    */
58299   GPIO_PINCFG63_OUTCFG63_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58300   GPIO_PINCFG63_OUTCFG63_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58301                                                      and 1 values on pin.                                                      */
58302   GPIO_PINCFG63_OUTCFG63_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58303                                                      low, tristate otherwise.                                                  */
58304   GPIO_PINCFG63_OUTCFG63_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58305                                                      drive 0, 1 of HiZ on pin.                                                 */
58306 } GPIO_PINCFG63_OUTCFG63_Enum;
58307 
58308 /* =============================================  GPIO PINCFG63 IRPTEN63 [6..7]  ============================================= */
58309 typedef enum {                                  /*!< GPIO_PINCFG63_IRPTEN63                                                    */
58310   GPIO_PINCFG63_IRPTEN63_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58311   GPIO_PINCFG63_IRPTEN63_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58312                                                      on this GPIO                                                              */
58313   GPIO_PINCFG63_IRPTEN63_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58314                                                      on this GPIO                                                              */
58315   GPIO_PINCFG63_IRPTEN63_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58316                                                      GPIO                                                                      */
58317 } GPIO_PINCFG63_IRPTEN63_Enum;
58318 
58319 /* =============================================  GPIO PINCFG63 FNCSEL63 [0..3]  ============================================= */
58320 typedef enum {                                  /*!< GPIO_PINCFG63_FNCSEL63                                                    */
58321   GPIO_PINCFG63_FNCSEL63_M6MISO        = 0,     /*!< M6MISO : Serial SPI MASTER MISO input (IOM 6)                             */
58322   GPIO_PINCFG63_FNCSEL63_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
58323   GPIO_PINCFG63_FNCSEL63_I2S1_WS       = 2,     /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
58324                                                      in master mode and input mode for slave mode. (I2S Master/Slave
58325                                                      2)                                                                        */
58326   GPIO_PINCFG63_FNCSEL63_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58327   GPIO_PINCFG63_FNCSEL63_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
58328   GPIO_PINCFG63_FNCSEL63_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
58329   GPIO_PINCFG63_FNCSEL63_CT63          = 6,     /*!< CT63 : Timer/Counter input or output; Selection of direction
58330                                                      is done via CTIMER register settings.                                     */
58331   GPIO_PINCFG63_FNCSEL63_NCE63         = 7,     /*!< NCE63 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58332                                                      CE_POLARITY field                                                         */
58333   GPIO_PINCFG63_FNCSEL63_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
58334   GPIO_PINCFG63_FNCSEL63_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
58335   GPIO_PINCFG63_FNCSEL63_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58336   GPIO_PINCFG63_FNCSEL63_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58337   GPIO_PINCFG63_FNCSEL63_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58338   GPIO_PINCFG63_FNCSEL63_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58339   GPIO_PINCFG63_FNCSEL63_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58340   GPIO_PINCFG63_FNCSEL63_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58341 } GPIO_PINCFG63_FNCSEL63_Enum;
58342 
58343 /* =======================================================  PINCFG64  ======================================================== */
58344 /* ============================================  GPIO PINCFG64 NCEPOL64 [22..22]  ============================================ */
58345 typedef enum {                                  /*!< GPIO_PINCFG64_NCEPOL64                                                    */
58346   GPIO_PINCFG64_NCEPOL64_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58347   GPIO_PINCFG64_NCEPOL64_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58348 } GPIO_PINCFG64_NCEPOL64_Enum;
58349 
58350 /* ============================================  GPIO PINCFG64 NCESRC64 [16..21]  ============================================ */
58351 typedef enum {                                  /*!< GPIO_PINCFG64_NCESRC64                                                    */
58352   GPIO_PINCFG64_NCESRC64_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58353   GPIO_PINCFG64_NCESRC64_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58354   GPIO_PINCFG64_NCESRC64_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58355   GPIO_PINCFG64_NCESRC64_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58356   GPIO_PINCFG64_NCESRC64_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58357   GPIO_PINCFG64_NCESRC64_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58358   GPIO_PINCFG64_NCESRC64_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58359   GPIO_PINCFG64_NCESRC64_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58360   GPIO_PINCFG64_NCESRC64_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58361   GPIO_PINCFG64_NCESRC64_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58362   GPIO_PINCFG64_NCESRC64_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58363   GPIO_PINCFG64_NCESRC64_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58364   GPIO_PINCFG64_NCESRC64_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58365   GPIO_PINCFG64_NCESRC64_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58366   GPIO_PINCFG64_NCESRC64_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58367   GPIO_PINCFG64_NCESRC64_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58368   GPIO_PINCFG64_NCESRC64_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58369   GPIO_PINCFG64_NCESRC64_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58370   GPIO_PINCFG64_NCESRC64_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58371   GPIO_PINCFG64_NCESRC64_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58372   GPIO_PINCFG64_NCESRC64_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58373   GPIO_PINCFG64_NCESRC64_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58374   GPIO_PINCFG64_NCESRC64_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58375   GPIO_PINCFG64_NCESRC64_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58376   GPIO_PINCFG64_NCESRC64_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58377   GPIO_PINCFG64_NCESRC64_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58378   GPIO_PINCFG64_NCESRC64_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58379   GPIO_PINCFG64_NCESRC64_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58380   GPIO_PINCFG64_NCESRC64_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58381   GPIO_PINCFG64_NCESRC64_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58382   GPIO_PINCFG64_NCESRC64_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58383   GPIO_PINCFG64_NCESRC64_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58384   GPIO_PINCFG64_NCESRC64_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58385   GPIO_PINCFG64_NCESRC64_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58386   GPIO_PINCFG64_NCESRC64_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58387   GPIO_PINCFG64_NCESRC64_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58388   GPIO_PINCFG64_NCESRC64_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58389   GPIO_PINCFG64_NCESRC64_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58390   GPIO_PINCFG64_NCESRC64_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58391   GPIO_PINCFG64_NCESRC64_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58392   GPIO_PINCFG64_NCESRC64_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58393   GPIO_PINCFG64_NCESRC64_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58394   GPIO_PINCFG64_NCESRC64_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58395 } GPIO_PINCFG64_NCESRC64_Enum;
58396 
58397 /* ===========================================  GPIO PINCFG64 PULLCFG64 [13..15]  ============================================ */
58398 typedef enum {                                  /*!< GPIO_PINCFG64_PULLCFG64                                                   */
58399   GPIO_PINCFG64_PULLCFG64_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58400   GPIO_PINCFG64_PULLCFG64_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58401   GPIO_PINCFG64_PULLCFG64_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58402   GPIO_PINCFG64_PULLCFG64_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58403   GPIO_PINCFG64_PULLCFG64_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58404   GPIO_PINCFG64_PULLCFG64_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58405   GPIO_PINCFG64_PULLCFG64_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58406   GPIO_PINCFG64_PULLCFG64_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58407 } GPIO_PINCFG64_PULLCFG64_Enum;
58408 
58409 /* ==============================================  GPIO PINCFG64 DS64 [10..11]  ============================================== */
58410 typedef enum {                                  /*!< GPIO_PINCFG64_DS64                                                        */
58411   GPIO_PINCFG64_DS64_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58412   GPIO_PINCFG64_DS64_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58413   GPIO_PINCFG64_DS64_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58414   GPIO_PINCFG64_DS64_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58415 } GPIO_PINCFG64_DS64_Enum;
58416 
58417 /* =============================================  GPIO PINCFG64 OUTCFG64 [8..9]  ============================================= */
58418 typedef enum {                                  /*!< GPIO_PINCFG64_OUTCFG64                                                    */
58419   GPIO_PINCFG64_OUTCFG64_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58420   GPIO_PINCFG64_OUTCFG64_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58421                                                      and 1 values on pin.                                                      */
58422   GPIO_PINCFG64_OUTCFG64_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58423                                                      low, tristate otherwise.                                                  */
58424   GPIO_PINCFG64_OUTCFG64_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58425                                                      drive 0, 1 of HiZ on pin.                                                 */
58426 } GPIO_PINCFG64_OUTCFG64_Enum;
58427 
58428 /* =============================================  GPIO PINCFG64 IRPTEN64 [6..7]  ============================================= */
58429 typedef enum {                                  /*!< GPIO_PINCFG64_IRPTEN64                                                    */
58430   GPIO_PINCFG64_IRPTEN64_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58431   GPIO_PINCFG64_IRPTEN64_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58432                                                      on this GPIO                                                              */
58433   GPIO_PINCFG64_IRPTEN64_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58434                                                      on this GPIO                                                              */
58435   GPIO_PINCFG64_IRPTEN64_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58436                                                      GPIO                                                                      */
58437 } GPIO_PINCFG64_IRPTEN64_Enum;
58438 
58439 /* =============================================  GPIO PINCFG64 FNCSEL64 [0..3]  ============================================= */
58440 typedef enum {                                  /*!< GPIO_PINCFG64_FNCSEL64                                                    */
58441   GPIO_PINCFG64_FNCSEL64_MSPI0_0       = 0,     /*!< MSPI0_0 : MSPI Master 0 Interface Signal                                  */
58442   GPIO_PINCFG64_FNCSEL64_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
58443   GPIO_PINCFG64_FNCSEL64_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
58444   GPIO_PINCFG64_FNCSEL64_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58445   GPIO_PINCFG64_FNCSEL64_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
58446   GPIO_PINCFG64_FNCSEL64_DISP_D0       = 5,     /*!< DISP_D0 : Display Data 0                                                  */
58447   GPIO_PINCFG64_FNCSEL64_CT64          = 6,     /*!< CT64 : Timer/Counter input or output; Selection of direction
58448                                                      is done via CTIMER register settings.                                     */
58449   GPIO_PINCFG64_FNCSEL64_NCE64         = 7,     /*!< NCE64 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58450                                                      CE_POLARITY field                                                         */
58451   GPIO_PINCFG64_FNCSEL64_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
58452   GPIO_PINCFG64_FNCSEL64_I2S1_SDIN     = 9,     /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
58453   GPIO_PINCFG64_FNCSEL64_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58454   GPIO_PINCFG64_FNCSEL64_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58455   GPIO_PINCFG64_FNCSEL64_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58456   GPIO_PINCFG64_FNCSEL64_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58457   GPIO_PINCFG64_FNCSEL64_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58458   GPIO_PINCFG64_FNCSEL64_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58459 } GPIO_PINCFG64_FNCSEL64_Enum;
58460 
58461 /* =======================================================  PINCFG65  ======================================================== */
58462 /* ============================================  GPIO PINCFG65 NCEPOL65 [22..22]  ============================================ */
58463 typedef enum {                                  /*!< GPIO_PINCFG65_NCEPOL65                                                    */
58464   GPIO_PINCFG65_NCEPOL65_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58465   GPIO_PINCFG65_NCEPOL65_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58466 } GPIO_PINCFG65_NCEPOL65_Enum;
58467 
58468 /* ============================================  GPIO PINCFG65 NCESRC65 [16..21]  ============================================ */
58469 typedef enum {                                  /*!< GPIO_PINCFG65_NCESRC65                                                    */
58470   GPIO_PINCFG65_NCESRC65_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58471   GPIO_PINCFG65_NCESRC65_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58472   GPIO_PINCFG65_NCESRC65_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58473   GPIO_PINCFG65_NCESRC65_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58474   GPIO_PINCFG65_NCESRC65_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58475   GPIO_PINCFG65_NCESRC65_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58476   GPIO_PINCFG65_NCESRC65_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58477   GPIO_PINCFG65_NCESRC65_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58478   GPIO_PINCFG65_NCESRC65_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58479   GPIO_PINCFG65_NCESRC65_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58480   GPIO_PINCFG65_NCESRC65_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58481   GPIO_PINCFG65_NCESRC65_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58482   GPIO_PINCFG65_NCESRC65_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58483   GPIO_PINCFG65_NCESRC65_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58484   GPIO_PINCFG65_NCESRC65_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58485   GPIO_PINCFG65_NCESRC65_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58486   GPIO_PINCFG65_NCESRC65_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58487   GPIO_PINCFG65_NCESRC65_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58488   GPIO_PINCFG65_NCESRC65_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58489   GPIO_PINCFG65_NCESRC65_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58490   GPIO_PINCFG65_NCESRC65_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58491   GPIO_PINCFG65_NCESRC65_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58492   GPIO_PINCFG65_NCESRC65_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58493   GPIO_PINCFG65_NCESRC65_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58494   GPIO_PINCFG65_NCESRC65_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58495   GPIO_PINCFG65_NCESRC65_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58496   GPIO_PINCFG65_NCESRC65_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58497   GPIO_PINCFG65_NCESRC65_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58498   GPIO_PINCFG65_NCESRC65_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58499   GPIO_PINCFG65_NCESRC65_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58500   GPIO_PINCFG65_NCESRC65_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58501   GPIO_PINCFG65_NCESRC65_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58502   GPIO_PINCFG65_NCESRC65_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58503   GPIO_PINCFG65_NCESRC65_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58504   GPIO_PINCFG65_NCESRC65_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58505   GPIO_PINCFG65_NCESRC65_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58506   GPIO_PINCFG65_NCESRC65_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58507   GPIO_PINCFG65_NCESRC65_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58508   GPIO_PINCFG65_NCESRC65_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58509   GPIO_PINCFG65_NCESRC65_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58510   GPIO_PINCFG65_NCESRC65_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58511   GPIO_PINCFG65_NCESRC65_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58512   GPIO_PINCFG65_NCESRC65_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58513 } GPIO_PINCFG65_NCESRC65_Enum;
58514 
58515 /* ===========================================  GPIO PINCFG65 PULLCFG65 [13..15]  ============================================ */
58516 typedef enum {                                  /*!< GPIO_PINCFG65_PULLCFG65                                                   */
58517   GPIO_PINCFG65_PULLCFG65_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58518   GPIO_PINCFG65_PULLCFG65_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58519   GPIO_PINCFG65_PULLCFG65_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58520   GPIO_PINCFG65_PULLCFG65_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58521   GPIO_PINCFG65_PULLCFG65_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58522   GPIO_PINCFG65_PULLCFG65_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58523   GPIO_PINCFG65_PULLCFG65_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58524   GPIO_PINCFG65_PULLCFG65_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58525 } GPIO_PINCFG65_PULLCFG65_Enum;
58526 
58527 /* ==============================================  GPIO PINCFG65 DS65 [10..11]  ============================================== */
58528 typedef enum {                                  /*!< GPIO_PINCFG65_DS65                                                        */
58529   GPIO_PINCFG65_DS65_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58530   GPIO_PINCFG65_DS65_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58531   GPIO_PINCFG65_DS65_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58532   GPIO_PINCFG65_DS65_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58533 } GPIO_PINCFG65_DS65_Enum;
58534 
58535 /* =============================================  GPIO PINCFG65 OUTCFG65 [8..9]  ============================================= */
58536 typedef enum {                                  /*!< GPIO_PINCFG65_OUTCFG65                                                    */
58537   GPIO_PINCFG65_OUTCFG65_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58538   GPIO_PINCFG65_OUTCFG65_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58539                                                      and 1 values on pin.                                                      */
58540   GPIO_PINCFG65_OUTCFG65_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58541                                                      low, tristate otherwise.                                                  */
58542   GPIO_PINCFG65_OUTCFG65_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58543                                                      drive 0, 1 of HiZ on pin.                                                 */
58544 } GPIO_PINCFG65_OUTCFG65_Enum;
58545 
58546 /* =============================================  GPIO PINCFG65 IRPTEN65 [6..7]  ============================================= */
58547 typedef enum {                                  /*!< GPIO_PINCFG65_IRPTEN65                                                    */
58548   GPIO_PINCFG65_IRPTEN65_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58549   GPIO_PINCFG65_IRPTEN65_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58550                                                      on this GPIO                                                              */
58551   GPIO_PINCFG65_IRPTEN65_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58552                                                      on this GPIO                                                              */
58553   GPIO_PINCFG65_IRPTEN65_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58554                                                      GPIO                                                                      */
58555 } GPIO_PINCFG65_IRPTEN65_Enum;
58556 
58557 /* =============================================  GPIO PINCFG65 FNCSEL65 [0..3]  ============================================= */
58558 typedef enum {                                  /*!< GPIO_PINCFG65_FNCSEL65                                                    */
58559   GPIO_PINCFG65_FNCSEL65_MSPI0_1       = 0,     /*!< MSPI0_1 : MSPI Master 0 Interface Signal                                  */
58560   GPIO_PINCFG65_FNCSEL65_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
58561   GPIO_PINCFG65_FNCSEL65_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
58562   GPIO_PINCFG65_FNCSEL65_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58563   GPIO_PINCFG65_FNCSEL65_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
58564   GPIO_PINCFG65_FNCSEL65_DISP_D1       = 5,     /*!< DISP_D1 : Display Data 1                                                  */
58565   GPIO_PINCFG65_FNCSEL65_CT65          = 6,     /*!< CT65 : Timer/Counter input or output; Selection of direction
58566                                                      is done via CTIMER register settings.                                     */
58567   GPIO_PINCFG65_FNCSEL65_NCE65         = 7,     /*!< NCE65 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58568                                                      CE_POLARITY field                                                         */
58569   GPIO_PINCFG65_FNCSEL65_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
58570   GPIO_PINCFG65_FNCSEL65_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58571   GPIO_PINCFG65_FNCSEL65_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58572   GPIO_PINCFG65_FNCSEL65_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58573   GPIO_PINCFG65_FNCSEL65_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58574   GPIO_PINCFG65_FNCSEL65_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58575   GPIO_PINCFG65_FNCSEL65_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58576   GPIO_PINCFG65_FNCSEL65_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58577 } GPIO_PINCFG65_FNCSEL65_Enum;
58578 
58579 /* =======================================================  PINCFG66  ======================================================== */
58580 /* ============================================  GPIO PINCFG66 NCEPOL66 [22..22]  ============================================ */
58581 typedef enum {                                  /*!< GPIO_PINCFG66_NCEPOL66                                                    */
58582   GPIO_PINCFG66_NCEPOL66_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58583   GPIO_PINCFG66_NCEPOL66_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58584 } GPIO_PINCFG66_NCEPOL66_Enum;
58585 
58586 /* ============================================  GPIO PINCFG66 NCESRC66 [16..21]  ============================================ */
58587 typedef enum {                                  /*!< GPIO_PINCFG66_NCESRC66                                                    */
58588   GPIO_PINCFG66_NCESRC66_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58589   GPIO_PINCFG66_NCESRC66_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58590   GPIO_PINCFG66_NCESRC66_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58591   GPIO_PINCFG66_NCESRC66_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58592   GPIO_PINCFG66_NCESRC66_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58593   GPIO_PINCFG66_NCESRC66_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58594   GPIO_PINCFG66_NCESRC66_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58595   GPIO_PINCFG66_NCESRC66_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58596   GPIO_PINCFG66_NCESRC66_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58597   GPIO_PINCFG66_NCESRC66_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58598   GPIO_PINCFG66_NCESRC66_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58599   GPIO_PINCFG66_NCESRC66_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58600   GPIO_PINCFG66_NCESRC66_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58601   GPIO_PINCFG66_NCESRC66_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58602   GPIO_PINCFG66_NCESRC66_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58603   GPIO_PINCFG66_NCESRC66_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58604   GPIO_PINCFG66_NCESRC66_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58605   GPIO_PINCFG66_NCESRC66_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58606   GPIO_PINCFG66_NCESRC66_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58607   GPIO_PINCFG66_NCESRC66_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58608   GPIO_PINCFG66_NCESRC66_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58609   GPIO_PINCFG66_NCESRC66_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58610   GPIO_PINCFG66_NCESRC66_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58611   GPIO_PINCFG66_NCESRC66_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58612   GPIO_PINCFG66_NCESRC66_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58613   GPIO_PINCFG66_NCESRC66_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58614   GPIO_PINCFG66_NCESRC66_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58615   GPIO_PINCFG66_NCESRC66_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58616   GPIO_PINCFG66_NCESRC66_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58617   GPIO_PINCFG66_NCESRC66_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58618   GPIO_PINCFG66_NCESRC66_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58619   GPIO_PINCFG66_NCESRC66_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58620   GPIO_PINCFG66_NCESRC66_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58621   GPIO_PINCFG66_NCESRC66_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58622   GPIO_PINCFG66_NCESRC66_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58623   GPIO_PINCFG66_NCESRC66_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58624   GPIO_PINCFG66_NCESRC66_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58625   GPIO_PINCFG66_NCESRC66_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58626   GPIO_PINCFG66_NCESRC66_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58627   GPIO_PINCFG66_NCESRC66_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58628   GPIO_PINCFG66_NCESRC66_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58629   GPIO_PINCFG66_NCESRC66_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58630   GPIO_PINCFG66_NCESRC66_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58631 } GPIO_PINCFG66_NCESRC66_Enum;
58632 
58633 /* ===========================================  GPIO PINCFG66 PULLCFG66 [13..15]  ============================================ */
58634 typedef enum {                                  /*!< GPIO_PINCFG66_PULLCFG66                                                   */
58635   GPIO_PINCFG66_PULLCFG66_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58636   GPIO_PINCFG66_PULLCFG66_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58637   GPIO_PINCFG66_PULLCFG66_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58638   GPIO_PINCFG66_PULLCFG66_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58639   GPIO_PINCFG66_PULLCFG66_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58640   GPIO_PINCFG66_PULLCFG66_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58641   GPIO_PINCFG66_PULLCFG66_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58642   GPIO_PINCFG66_PULLCFG66_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58643 } GPIO_PINCFG66_PULLCFG66_Enum;
58644 
58645 /* ==============================================  GPIO PINCFG66 DS66 [10..11]  ============================================== */
58646 typedef enum {                                  /*!< GPIO_PINCFG66_DS66                                                        */
58647   GPIO_PINCFG66_DS66_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58648   GPIO_PINCFG66_DS66_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58649   GPIO_PINCFG66_DS66_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58650   GPIO_PINCFG66_DS66_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58651 } GPIO_PINCFG66_DS66_Enum;
58652 
58653 /* =============================================  GPIO PINCFG66 OUTCFG66 [8..9]  ============================================= */
58654 typedef enum {                                  /*!< GPIO_PINCFG66_OUTCFG66                                                    */
58655   GPIO_PINCFG66_OUTCFG66_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58656   GPIO_PINCFG66_OUTCFG66_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58657                                                      and 1 values on pin.                                                      */
58658   GPIO_PINCFG66_OUTCFG66_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58659                                                      low, tristate otherwise.                                                  */
58660   GPIO_PINCFG66_OUTCFG66_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58661                                                      drive 0, 1 of HiZ on pin.                                                 */
58662 } GPIO_PINCFG66_OUTCFG66_Enum;
58663 
58664 /* =============================================  GPIO PINCFG66 IRPTEN66 [6..7]  ============================================= */
58665 typedef enum {                                  /*!< GPIO_PINCFG66_IRPTEN66                                                    */
58666   GPIO_PINCFG66_IRPTEN66_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58667   GPIO_PINCFG66_IRPTEN66_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58668                                                      on this GPIO                                                              */
58669   GPIO_PINCFG66_IRPTEN66_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58670                                                      on this GPIO                                                              */
58671   GPIO_PINCFG66_IRPTEN66_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58672                                                      GPIO                                                                      */
58673 } GPIO_PINCFG66_IRPTEN66_Enum;
58674 
58675 /* =============================================  GPIO PINCFG66 FNCSEL66 [0..3]  ============================================= */
58676 typedef enum {                                  /*!< GPIO_PINCFG66_FNCSEL66                                                    */
58677   GPIO_PINCFG66_FNCSEL66_MSPI0_2       = 0,     /*!< MSPI0_2 : MSPI Master 0 Interface Signal                                  */
58678   GPIO_PINCFG66_FNCSEL66_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
58679   GPIO_PINCFG66_FNCSEL66_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
58680   GPIO_PINCFG66_FNCSEL66_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58681   GPIO_PINCFG66_FNCSEL66_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
58682   GPIO_PINCFG66_FNCSEL66_DISP_D2       = 5,     /*!< DISP_D2 : Display Data 2                                                  */
58683   GPIO_PINCFG66_FNCSEL66_CT66          = 6,     /*!< CT66 : Timer/Counter input or output; Selection of direction
58684                                                      is done via CTIMER register settings.                                     */
58685   GPIO_PINCFG66_FNCSEL66_NCE66         = 7,     /*!< NCE66 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58686                                                      CE_POLARITY field                                                         */
58687   GPIO_PINCFG66_FNCSEL66_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
58688   GPIO_PINCFG66_FNCSEL66_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58689   GPIO_PINCFG66_FNCSEL66_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58690   GPIO_PINCFG66_FNCSEL66_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58691   GPIO_PINCFG66_FNCSEL66_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58692   GPIO_PINCFG66_FNCSEL66_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58693   GPIO_PINCFG66_FNCSEL66_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58694   GPIO_PINCFG66_FNCSEL66_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58695 } GPIO_PINCFG66_FNCSEL66_Enum;
58696 
58697 /* =======================================================  PINCFG67  ======================================================== */
58698 /* ============================================  GPIO PINCFG67 NCEPOL67 [22..22]  ============================================ */
58699 typedef enum {                                  /*!< GPIO_PINCFG67_NCEPOL67                                                    */
58700   GPIO_PINCFG67_NCEPOL67_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58701   GPIO_PINCFG67_NCEPOL67_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58702 } GPIO_PINCFG67_NCEPOL67_Enum;
58703 
58704 /* ============================================  GPIO PINCFG67 NCESRC67 [16..21]  ============================================ */
58705 typedef enum {                                  /*!< GPIO_PINCFG67_NCESRC67                                                    */
58706   GPIO_PINCFG67_NCESRC67_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58707   GPIO_PINCFG67_NCESRC67_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58708   GPIO_PINCFG67_NCESRC67_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58709   GPIO_PINCFG67_NCESRC67_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58710   GPIO_PINCFG67_NCESRC67_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58711   GPIO_PINCFG67_NCESRC67_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58712   GPIO_PINCFG67_NCESRC67_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58713   GPIO_PINCFG67_NCESRC67_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58714   GPIO_PINCFG67_NCESRC67_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58715   GPIO_PINCFG67_NCESRC67_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58716   GPIO_PINCFG67_NCESRC67_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58717   GPIO_PINCFG67_NCESRC67_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58718   GPIO_PINCFG67_NCESRC67_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58719   GPIO_PINCFG67_NCESRC67_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58720   GPIO_PINCFG67_NCESRC67_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58721   GPIO_PINCFG67_NCESRC67_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58722   GPIO_PINCFG67_NCESRC67_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58723   GPIO_PINCFG67_NCESRC67_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58724   GPIO_PINCFG67_NCESRC67_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58725   GPIO_PINCFG67_NCESRC67_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58726   GPIO_PINCFG67_NCESRC67_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58727   GPIO_PINCFG67_NCESRC67_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58728   GPIO_PINCFG67_NCESRC67_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58729   GPIO_PINCFG67_NCESRC67_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58730   GPIO_PINCFG67_NCESRC67_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58731   GPIO_PINCFG67_NCESRC67_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58732   GPIO_PINCFG67_NCESRC67_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58733   GPIO_PINCFG67_NCESRC67_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58734   GPIO_PINCFG67_NCESRC67_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58735   GPIO_PINCFG67_NCESRC67_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58736   GPIO_PINCFG67_NCESRC67_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58737   GPIO_PINCFG67_NCESRC67_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58738   GPIO_PINCFG67_NCESRC67_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58739   GPIO_PINCFG67_NCESRC67_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58740   GPIO_PINCFG67_NCESRC67_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58741   GPIO_PINCFG67_NCESRC67_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58742   GPIO_PINCFG67_NCESRC67_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58743   GPIO_PINCFG67_NCESRC67_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58744   GPIO_PINCFG67_NCESRC67_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58745   GPIO_PINCFG67_NCESRC67_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58746   GPIO_PINCFG67_NCESRC67_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58747   GPIO_PINCFG67_NCESRC67_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58748   GPIO_PINCFG67_NCESRC67_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58749 } GPIO_PINCFG67_NCESRC67_Enum;
58750 
58751 /* ===========================================  GPIO PINCFG67 PULLCFG67 [13..15]  ============================================ */
58752 typedef enum {                                  /*!< GPIO_PINCFG67_PULLCFG67                                                   */
58753   GPIO_PINCFG67_PULLCFG67_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58754   GPIO_PINCFG67_PULLCFG67_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58755   GPIO_PINCFG67_PULLCFG67_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58756   GPIO_PINCFG67_PULLCFG67_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58757   GPIO_PINCFG67_PULLCFG67_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58758   GPIO_PINCFG67_PULLCFG67_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58759   GPIO_PINCFG67_PULLCFG67_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58760   GPIO_PINCFG67_PULLCFG67_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58761 } GPIO_PINCFG67_PULLCFG67_Enum;
58762 
58763 /* ==============================================  GPIO PINCFG67 DS67 [10..11]  ============================================== */
58764 typedef enum {                                  /*!< GPIO_PINCFG67_DS67                                                        */
58765   GPIO_PINCFG67_DS67_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58766   GPIO_PINCFG67_DS67_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58767   GPIO_PINCFG67_DS67_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58768   GPIO_PINCFG67_DS67_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58769 } GPIO_PINCFG67_DS67_Enum;
58770 
58771 /* =============================================  GPIO PINCFG67 OUTCFG67 [8..9]  ============================================= */
58772 typedef enum {                                  /*!< GPIO_PINCFG67_OUTCFG67                                                    */
58773   GPIO_PINCFG67_OUTCFG67_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58774   GPIO_PINCFG67_OUTCFG67_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58775                                                      and 1 values on pin.                                                      */
58776   GPIO_PINCFG67_OUTCFG67_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58777                                                      low, tristate otherwise.                                                  */
58778   GPIO_PINCFG67_OUTCFG67_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58779                                                      drive 0, 1 of HiZ on pin.                                                 */
58780 } GPIO_PINCFG67_OUTCFG67_Enum;
58781 
58782 /* =============================================  GPIO PINCFG67 IRPTEN67 [6..7]  ============================================= */
58783 typedef enum {                                  /*!< GPIO_PINCFG67_IRPTEN67                                                    */
58784   GPIO_PINCFG67_IRPTEN67_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58785   GPIO_PINCFG67_IRPTEN67_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58786                                                      on this GPIO                                                              */
58787   GPIO_PINCFG67_IRPTEN67_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58788                                                      on this GPIO                                                              */
58789   GPIO_PINCFG67_IRPTEN67_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58790                                                      GPIO                                                                      */
58791 } GPIO_PINCFG67_IRPTEN67_Enum;
58792 
58793 /* =============================================  GPIO PINCFG67 FNCSEL67 [0..3]  ============================================= */
58794 typedef enum {                                  /*!< GPIO_PINCFG67_FNCSEL67                                                    */
58795   GPIO_PINCFG67_FNCSEL67_MSPI0_3       = 0,     /*!< MSPI0_3 : MSPI Master 0 Interface Signal                                  */
58796   GPIO_PINCFG67_FNCSEL67_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
58797   GPIO_PINCFG67_FNCSEL67_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
58798   GPIO_PINCFG67_FNCSEL67_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58799   GPIO_PINCFG67_FNCSEL67_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
58800   GPIO_PINCFG67_FNCSEL67_DISP_D3       = 5,     /*!< DISP_D3 : Display Data 3                                                  */
58801   GPIO_PINCFG67_FNCSEL67_CT67          = 6,     /*!< CT67 : Timer/Counter input or output; Selection of direction
58802                                                      is done via CTIMER register settings.                                     */
58803   GPIO_PINCFG67_FNCSEL67_NCE67         = 7,     /*!< NCE67 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58804                                                      CE_POLARITY field                                                         */
58805   GPIO_PINCFG67_FNCSEL67_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
58806   GPIO_PINCFG67_FNCSEL67_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58807   GPIO_PINCFG67_FNCSEL67_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58808   GPIO_PINCFG67_FNCSEL67_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58809   GPIO_PINCFG67_FNCSEL67_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58810   GPIO_PINCFG67_FNCSEL67_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58811   GPIO_PINCFG67_FNCSEL67_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58812   GPIO_PINCFG67_FNCSEL67_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58813 } GPIO_PINCFG67_FNCSEL67_Enum;
58814 
58815 /* =======================================================  PINCFG68  ======================================================== */
58816 /* ============================================  GPIO PINCFG68 NCEPOL68 [22..22]  ============================================ */
58817 typedef enum {                                  /*!< GPIO_PINCFG68_NCEPOL68                                                    */
58818   GPIO_PINCFG68_NCEPOL68_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58819   GPIO_PINCFG68_NCEPOL68_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58820 } GPIO_PINCFG68_NCEPOL68_Enum;
58821 
58822 /* ============================================  GPIO PINCFG68 NCESRC68 [16..21]  ============================================ */
58823 typedef enum {                                  /*!< GPIO_PINCFG68_NCESRC68                                                    */
58824   GPIO_PINCFG68_NCESRC68_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58825   GPIO_PINCFG68_NCESRC68_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58826   GPIO_PINCFG68_NCESRC68_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58827   GPIO_PINCFG68_NCESRC68_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58828   GPIO_PINCFG68_NCESRC68_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58829   GPIO_PINCFG68_NCESRC68_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58830   GPIO_PINCFG68_NCESRC68_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58831   GPIO_PINCFG68_NCESRC68_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58832   GPIO_PINCFG68_NCESRC68_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58833   GPIO_PINCFG68_NCESRC68_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58834   GPIO_PINCFG68_NCESRC68_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58835   GPIO_PINCFG68_NCESRC68_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58836   GPIO_PINCFG68_NCESRC68_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58837   GPIO_PINCFG68_NCESRC68_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58838   GPIO_PINCFG68_NCESRC68_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58839   GPIO_PINCFG68_NCESRC68_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58840   GPIO_PINCFG68_NCESRC68_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58841   GPIO_PINCFG68_NCESRC68_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58842   GPIO_PINCFG68_NCESRC68_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58843   GPIO_PINCFG68_NCESRC68_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58844   GPIO_PINCFG68_NCESRC68_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58845   GPIO_PINCFG68_NCESRC68_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58846   GPIO_PINCFG68_NCESRC68_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58847   GPIO_PINCFG68_NCESRC68_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58848   GPIO_PINCFG68_NCESRC68_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58849   GPIO_PINCFG68_NCESRC68_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58850   GPIO_PINCFG68_NCESRC68_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58851   GPIO_PINCFG68_NCESRC68_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58852   GPIO_PINCFG68_NCESRC68_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58853   GPIO_PINCFG68_NCESRC68_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58854   GPIO_PINCFG68_NCESRC68_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58855   GPIO_PINCFG68_NCESRC68_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58856   GPIO_PINCFG68_NCESRC68_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58857   GPIO_PINCFG68_NCESRC68_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58858   GPIO_PINCFG68_NCESRC68_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58859   GPIO_PINCFG68_NCESRC68_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58860   GPIO_PINCFG68_NCESRC68_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58861   GPIO_PINCFG68_NCESRC68_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58862   GPIO_PINCFG68_NCESRC68_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58863   GPIO_PINCFG68_NCESRC68_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58864   GPIO_PINCFG68_NCESRC68_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58865   GPIO_PINCFG68_NCESRC68_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58866   GPIO_PINCFG68_NCESRC68_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58867 } GPIO_PINCFG68_NCESRC68_Enum;
58868 
58869 /* ===========================================  GPIO PINCFG68 PULLCFG68 [13..15]  ============================================ */
58870 typedef enum {                                  /*!< GPIO_PINCFG68_PULLCFG68                                                   */
58871   GPIO_PINCFG68_PULLCFG68_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58872   GPIO_PINCFG68_PULLCFG68_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58873   GPIO_PINCFG68_PULLCFG68_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58874   GPIO_PINCFG68_PULLCFG68_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58875   GPIO_PINCFG68_PULLCFG68_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58876   GPIO_PINCFG68_PULLCFG68_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58877   GPIO_PINCFG68_PULLCFG68_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58878   GPIO_PINCFG68_PULLCFG68_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58879 } GPIO_PINCFG68_PULLCFG68_Enum;
58880 
58881 /* ==============================================  GPIO PINCFG68 DS68 [10..11]  ============================================== */
58882 typedef enum {                                  /*!< GPIO_PINCFG68_DS68                                                        */
58883   GPIO_PINCFG68_DS68_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
58884   GPIO_PINCFG68_DS68_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
58885   GPIO_PINCFG68_DS68_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
58886   GPIO_PINCFG68_DS68_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
58887 } GPIO_PINCFG68_DS68_Enum;
58888 
58889 /* =============================================  GPIO PINCFG68 OUTCFG68 [8..9]  ============================================= */
58890 typedef enum {                                  /*!< GPIO_PINCFG68_OUTCFG68                                                    */
58891   GPIO_PINCFG68_OUTCFG68_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
58892   GPIO_PINCFG68_OUTCFG68_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
58893                                                      and 1 values on pin.                                                      */
58894   GPIO_PINCFG68_OUTCFG68_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
58895                                                      low, tristate otherwise.                                                  */
58896   GPIO_PINCFG68_OUTCFG68_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
58897                                                      drive 0, 1 of HiZ on pin.                                                 */
58898 } GPIO_PINCFG68_OUTCFG68_Enum;
58899 
58900 /* =============================================  GPIO PINCFG68 IRPTEN68 [6..7]  ============================================= */
58901 typedef enum {                                  /*!< GPIO_PINCFG68_IRPTEN68                                                    */
58902   GPIO_PINCFG68_IRPTEN68_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
58903   GPIO_PINCFG68_IRPTEN68_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
58904                                                      on this GPIO                                                              */
58905   GPIO_PINCFG68_IRPTEN68_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
58906                                                      on this GPIO                                                              */
58907   GPIO_PINCFG68_IRPTEN68_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
58908                                                      GPIO                                                                      */
58909 } GPIO_PINCFG68_IRPTEN68_Enum;
58910 
58911 /* =============================================  GPIO PINCFG68 FNCSEL68 [0..3]  ============================================= */
58912 typedef enum {                                  /*!< GPIO_PINCFG68_FNCSEL68                                                    */
58913   GPIO_PINCFG68_FNCSEL68_MSPI0_4       = 0,     /*!< MSPI0_4 : MSPI Master 0 Interface Signal                                  */
58914   GPIO_PINCFG68_FNCSEL68_SWO           = 1,     /*!< SWO : Serial Wire Output                                                  */
58915   GPIO_PINCFG68_FNCSEL68_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
58916   GPIO_PINCFG68_FNCSEL68_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
58917   GPIO_PINCFG68_FNCSEL68_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
58918   GPIO_PINCFG68_FNCSEL68_DISP_D4       = 5,     /*!< DISP_D4 : Display Data 4                                                  */
58919   GPIO_PINCFG68_FNCSEL68_CT68          = 6,     /*!< CT68 : Timer/Counter input or output; Selection of direction
58920                                                      is done via CTIMER register settings.                                     */
58921   GPIO_PINCFG68_FNCSEL68_NCE68         = 7,     /*!< NCE68 : IOMSTR/MSPI N Chip Select. Polarity is determined by
58922                                                      CE_POLARITY field                                                         */
58923   GPIO_PINCFG68_FNCSEL68_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
58924   GPIO_PINCFG68_FNCSEL68_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
58925   GPIO_PINCFG68_FNCSEL68_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
58926   GPIO_PINCFG68_FNCSEL68_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
58927   GPIO_PINCFG68_FNCSEL68_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
58928   GPIO_PINCFG68_FNCSEL68_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
58929   GPIO_PINCFG68_FNCSEL68_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
58930   GPIO_PINCFG68_FNCSEL68_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
58931 } GPIO_PINCFG68_FNCSEL68_Enum;
58932 
58933 /* =======================================================  PINCFG69  ======================================================== */
58934 /* ============================================  GPIO PINCFG69 NCEPOL69 [22..22]  ============================================ */
58935 typedef enum {                                  /*!< GPIO_PINCFG69_NCEPOL69                                                    */
58936   GPIO_PINCFG69_NCEPOL69_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
58937   GPIO_PINCFG69_NCEPOL69_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
58938 } GPIO_PINCFG69_NCEPOL69_Enum;
58939 
58940 /* ============================================  GPIO PINCFG69 NCESRC69 [16..21]  ============================================ */
58941 typedef enum {                                  /*!< GPIO_PINCFG69_NCESRC69                                                    */
58942   GPIO_PINCFG69_NCESRC69_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
58943   GPIO_PINCFG69_NCESRC69_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
58944   GPIO_PINCFG69_NCESRC69_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
58945   GPIO_PINCFG69_NCESRC69_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
58946   GPIO_PINCFG69_NCESRC69_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
58947   GPIO_PINCFG69_NCESRC69_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
58948   GPIO_PINCFG69_NCESRC69_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
58949   GPIO_PINCFG69_NCESRC69_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
58950   GPIO_PINCFG69_NCESRC69_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
58951   GPIO_PINCFG69_NCESRC69_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
58952   GPIO_PINCFG69_NCESRC69_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
58953   GPIO_PINCFG69_NCESRC69_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
58954   GPIO_PINCFG69_NCESRC69_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
58955   GPIO_PINCFG69_NCESRC69_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
58956   GPIO_PINCFG69_NCESRC69_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
58957   GPIO_PINCFG69_NCESRC69_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
58958   GPIO_PINCFG69_NCESRC69_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
58959   GPIO_PINCFG69_NCESRC69_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
58960   GPIO_PINCFG69_NCESRC69_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
58961   GPIO_PINCFG69_NCESRC69_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
58962   GPIO_PINCFG69_NCESRC69_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
58963   GPIO_PINCFG69_NCESRC69_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
58964   GPIO_PINCFG69_NCESRC69_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
58965   GPIO_PINCFG69_NCESRC69_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
58966   GPIO_PINCFG69_NCESRC69_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
58967   GPIO_PINCFG69_NCESRC69_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
58968   GPIO_PINCFG69_NCESRC69_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
58969   GPIO_PINCFG69_NCESRC69_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
58970   GPIO_PINCFG69_NCESRC69_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
58971   GPIO_PINCFG69_NCESRC69_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
58972   GPIO_PINCFG69_NCESRC69_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
58973   GPIO_PINCFG69_NCESRC69_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
58974   GPIO_PINCFG69_NCESRC69_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
58975   GPIO_PINCFG69_NCESRC69_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
58976   GPIO_PINCFG69_NCESRC69_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
58977   GPIO_PINCFG69_NCESRC69_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
58978   GPIO_PINCFG69_NCESRC69_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
58979   GPIO_PINCFG69_NCESRC69_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
58980   GPIO_PINCFG69_NCESRC69_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
58981   GPIO_PINCFG69_NCESRC69_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
58982   GPIO_PINCFG69_NCESRC69_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
58983   GPIO_PINCFG69_NCESRC69_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
58984   GPIO_PINCFG69_NCESRC69_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
58985 } GPIO_PINCFG69_NCESRC69_Enum;
58986 
58987 /* ===========================================  GPIO PINCFG69 PULLCFG69 [13..15]  ============================================ */
58988 typedef enum {                                  /*!< GPIO_PINCFG69_PULLCFG69                                                   */
58989   GPIO_PINCFG69_PULLCFG69_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
58990   GPIO_PINCFG69_PULLCFG69_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
58991   GPIO_PINCFG69_PULLCFG69_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
58992   GPIO_PINCFG69_PULLCFG69_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
58993   GPIO_PINCFG69_PULLCFG69_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
58994   GPIO_PINCFG69_PULLCFG69_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
58995   GPIO_PINCFG69_PULLCFG69_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
58996   GPIO_PINCFG69_PULLCFG69_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
58997 } GPIO_PINCFG69_PULLCFG69_Enum;
58998 
58999 /* ==============================================  GPIO PINCFG69 DS69 [10..11]  ============================================== */
59000 typedef enum {                                  /*!< GPIO_PINCFG69_DS69                                                        */
59001   GPIO_PINCFG69_DS69_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59002   GPIO_PINCFG69_DS69_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59003   GPIO_PINCFG69_DS69_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59004   GPIO_PINCFG69_DS69_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59005 } GPIO_PINCFG69_DS69_Enum;
59006 
59007 /* =============================================  GPIO PINCFG69 OUTCFG69 [8..9]  ============================================= */
59008 typedef enum {                                  /*!< GPIO_PINCFG69_OUTCFG69                                                    */
59009   GPIO_PINCFG69_OUTCFG69_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59010   GPIO_PINCFG69_OUTCFG69_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59011                                                      and 1 values on pin.                                                      */
59012   GPIO_PINCFG69_OUTCFG69_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59013                                                      low, tristate otherwise.                                                  */
59014   GPIO_PINCFG69_OUTCFG69_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59015                                                      drive 0, 1 of HiZ on pin.                                                 */
59016 } GPIO_PINCFG69_OUTCFG69_Enum;
59017 
59018 /* =============================================  GPIO PINCFG69 IRPTEN69 [6..7]  ============================================= */
59019 typedef enum {                                  /*!< GPIO_PINCFG69_IRPTEN69                                                    */
59020   GPIO_PINCFG69_IRPTEN69_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59021   GPIO_PINCFG69_IRPTEN69_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59022                                                      on this GPIO                                                              */
59023   GPIO_PINCFG69_IRPTEN69_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59024                                                      on this GPIO                                                              */
59025   GPIO_PINCFG69_IRPTEN69_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59026                                                      GPIO                                                                      */
59027 } GPIO_PINCFG69_IRPTEN69_Enum;
59028 
59029 /* =============================================  GPIO PINCFG69 FNCSEL69 [0..3]  ============================================= */
59030 typedef enum {                                  /*!< GPIO_PINCFG69_FNCSEL69                                                    */
59031   GPIO_PINCFG69_FNCSEL69_MSPI0_5       = 0,     /*!< MSPI0_5 : MSPI Master 0 Interface Signal                                  */
59032   GPIO_PINCFG69_FNCSEL69_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
59033   GPIO_PINCFG69_FNCSEL69_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
59034   GPIO_PINCFG69_FNCSEL69_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59035   GPIO_PINCFG69_FNCSEL69_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
59036   GPIO_PINCFG69_FNCSEL69_DISP_D5       = 5,     /*!< DISP_D5 : Display Data 5                                                  */
59037   GPIO_PINCFG69_FNCSEL69_CT69          = 6,     /*!< CT69 : Timer/Counter input or output; Selection of direction
59038                                                      is done via CTIMER register settings.                                     */
59039   GPIO_PINCFG69_FNCSEL69_NCE69         = 7,     /*!< NCE69 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59040                                                      CE_POLARITY field                                                         */
59041   GPIO_PINCFG69_FNCSEL69_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
59042   GPIO_PINCFG69_FNCSEL69_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59043   GPIO_PINCFG69_FNCSEL69_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59044   GPIO_PINCFG69_FNCSEL69_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59045   GPIO_PINCFG69_FNCSEL69_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59046   GPIO_PINCFG69_FNCSEL69_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59047   GPIO_PINCFG69_FNCSEL69_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59048   GPIO_PINCFG69_FNCSEL69_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59049 } GPIO_PINCFG69_FNCSEL69_Enum;
59050 
59051 /* =======================================================  PINCFG70  ======================================================== */
59052 /* ============================================  GPIO PINCFG70 NCEPOL70 [22..22]  ============================================ */
59053 typedef enum {                                  /*!< GPIO_PINCFG70_NCEPOL70                                                    */
59054   GPIO_PINCFG70_NCEPOL70_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59055   GPIO_PINCFG70_NCEPOL70_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59056 } GPIO_PINCFG70_NCEPOL70_Enum;
59057 
59058 /* ============================================  GPIO PINCFG70 NCESRC70 [16..21]  ============================================ */
59059 typedef enum {                                  /*!< GPIO_PINCFG70_NCESRC70                                                    */
59060   GPIO_PINCFG70_NCESRC70_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59061   GPIO_PINCFG70_NCESRC70_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59062   GPIO_PINCFG70_NCESRC70_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59063   GPIO_PINCFG70_NCESRC70_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59064   GPIO_PINCFG70_NCESRC70_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59065   GPIO_PINCFG70_NCESRC70_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59066   GPIO_PINCFG70_NCESRC70_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59067   GPIO_PINCFG70_NCESRC70_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59068   GPIO_PINCFG70_NCESRC70_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59069   GPIO_PINCFG70_NCESRC70_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59070   GPIO_PINCFG70_NCESRC70_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59071   GPIO_PINCFG70_NCESRC70_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59072   GPIO_PINCFG70_NCESRC70_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59073   GPIO_PINCFG70_NCESRC70_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59074   GPIO_PINCFG70_NCESRC70_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59075   GPIO_PINCFG70_NCESRC70_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59076   GPIO_PINCFG70_NCESRC70_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59077   GPIO_PINCFG70_NCESRC70_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59078   GPIO_PINCFG70_NCESRC70_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59079   GPIO_PINCFG70_NCESRC70_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59080   GPIO_PINCFG70_NCESRC70_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59081   GPIO_PINCFG70_NCESRC70_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59082   GPIO_PINCFG70_NCESRC70_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59083   GPIO_PINCFG70_NCESRC70_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59084   GPIO_PINCFG70_NCESRC70_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59085   GPIO_PINCFG70_NCESRC70_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59086   GPIO_PINCFG70_NCESRC70_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59087   GPIO_PINCFG70_NCESRC70_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59088   GPIO_PINCFG70_NCESRC70_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59089   GPIO_PINCFG70_NCESRC70_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59090   GPIO_PINCFG70_NCESRC70_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59091   GPIO_PINCFG70_NCESRC70_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59092   GPIO_PINCFG70_NCESRC70_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59093   GPIO_PINCFG70_NCESRC70_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59094   GPIO_PINCFG70_NCESRC70_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59095   GPIO_PINCFG70_NCESRC70_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59096   GPIO_PINCFG70_NCESRC70_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59097   GPIO_PINCFG70_NCESRC70_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59098   GPIO_PINCFG70_NCESRC70_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59099   GPIO_PINCFG70_NCESRC70_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59100   GPIO_PINCFG70_NCESRC70_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59101   GPIO_PINCFG70_NCESRC70_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59102   GPIO_PINCFG70_NCESRC70_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59103 } GPIO_PINCFG70_NCESRC70_Enum;
59104 
59105 /* ===========================================  GPIO PINCFG70 PULLCFG70 [13..15]  ============================================ */
59106 typedef enum {                                  /*!< GPIO_PINCFG70_PULLCFG70                                                   */
59107   GPIO_PINCFG70_PULLCFG70_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59108   GPIO_PINCFG70_PULLCFG70_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59109   GPIO_PINCFG70_PULLCFG70_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59110   GPIO_PINCFG70_PULLCFG70_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59111   GPIO_PINCFG70_PULLCFG70_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59112   GPIO_PINCFG70_PULLCFG70_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59113   GPIO_PINCFG70_PULLCFG70_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59114   GPIO_PINCFG70_PULLCFG70_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59115 } GPIO_PINCFG70_PULLCFG70_Enum;
59116 
59117 /* ==============================================  GPIO PINCFG70 DS70 [10..11]  ============================================== */
59118 typedef enum {                                  /*!< GPIO_PINCFG70_DS70                                                        */
59119   GPIO_PINCFG70_DS70_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59120   GPIO_PINCFG70_DS70_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59121   GPIO_PINCFG70_DS70_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59122   GPIO_PINCFG70_DS70_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59123 } GPIO_PINCFG70_DS70_Enum;
59124 
59125 /* =============================================  GPIO PINCFG70 OUTCFG70 [8..9]  ============================================= */
59126 typedef enum {                                  /*!< GPIO_PINCFG70_OUTCFG70                                                    */
59127   GPIO_PINCFG70_OUTCFG70_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59128   GPIO_PINCFG70_OUTCFG70_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59129                                                      and 1 values on pin.                                                      */
59130   GPIO_PINCFG70_OUTCFG70_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59131                                                      low, tristate otherwise.                                                  */
59132   GPIO_PINCFG70_OUTCFG70_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59133                                                      drive 0, 1 of HiZ on pin.                                                 */
59134 } GPIO_PINCFG70_OUTCFG70_Enum;
59135 
59136 /* =============================================  GPIO PINCFG70 IRPTEN70 [6..7]  ============================================= */
59137 typedef enum {                                  /*!< GPIO_PINCFG70_IRPTEN70                                                    */
59138   GPIO_PINCFG70_IRPTEN70_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59139   GPIO_PINCFG70_IRPTEN70_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59140                                                      on this GPIO                                                              */
59141   GPIO_PINCFG70_IRPTEN70_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59142                                                      on this GPIO                                                              */
59143   GPIO_PINCFG70_IRPTEN70_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59144                                                      GPIO                                                                      */
59145 } GPIO_PINCFG70_IRPTEN70_Enum;
59146 
59147 /* =============================================  GPIO PINCFG70 FNCSEL70 [0..3]  ============================================= */
59148 typedef enum {                                  /*!< GPIO_PINCFG70_FNCSEL70                                                    */
59149   GPIO_PINCFG70_FNCSEL70_MSPI0_6       = 0,     /*!< MSPI0_6 : MSPI Master 0 Interface Signal                                  */
59150   GPIO_PINCFG70_FNCSEL70_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
59151   GPIO_PINCFG70_FNCSEL70_SWTRACE0      = 2,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
59152   GPIO_PINCFG70_FNCSEL70_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59153   GPIO_PINCFG70_FNCSEL70_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
59154   GPIO_PINCFG70_FNCSEL70_DISP_D6       = 5,     /*!< DISP_D6 : Display Data 6                                                  */
59155   GPIO_PINCFG70_FNCSEL70_CT70          = 6,     /*!< CT70 : Timer/Counter input or output; Selection of direction
59156                                                      is done via CTIMER register settings.                                     */
59157   GPIO_PINCFG70_FNCSEL70_NCE70         = 7,     /*!< NCE70 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59158                                                      CE_POLARITY field                                                         */
59159   GPIO_PINCFG70_FNCSEL70_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
59160   GPIO_PINCFG70_FNCSEL70_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59161   GPIO_PINCFG70_FNCSEL70_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59162   GPIO_PINCFG70_FNCSEL70_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59163   GPIO_PINCFG70_FNCSEL70_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59164   GPIO_PINCFG70_FNCSEL70_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59165   GPIO_PINCFG70_FNCSEL70_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59166   GPIO_PINCFG70_FNCSEL70_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59167 } GPIO_PINCFG70_FNCSEL70_Enum;
59168 
59169 /* =======================================================  PINCFG71  ======================================================== */
59170 /* ============================================  GPIO PINCFG71 NCEPOL71 [22..22]  ============================================ */
59171 typedef enum {                                  /*!< GPIO_PINCFG71_NCEPOL71                                                    */
59172   GPIO_PINCFG71_NCEPOL71_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59173   GPIO_PINCFG71_NCEPOL71_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59174 } GPIO_PINCFG71_NCEPOL71_Enum;
59175 
59176 /* ============================================  GPIO PINCFG71 NCESRC71 [16..21]  ============================================ */
59177 typedef enum {                                  /*!< GPIO_PINCFG71_NCESRC71                                                    */
59178   GPIO_PINCFG71_NCESRC71_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59179   GPIO_PINCFG71_NCESRC71_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59180   GPIO_PINCFG71_NCESRC71_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59181   GPIO_PINCFG71_NCESRC71_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59182   GPIO_PINCFG71_NCESRC71_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59183   GPIO_PINCFG71_NCESRC71_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59184   GPIO_PINCFG71_NCESRC71_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59185   GPIO_PINCFG71_NCESRC71_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59186   GPIO_PINCFG71_NCESRC71_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59187   GPIO_PINCFG71_NCESRC71_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59188   GPIO_PINCFG71_NCESRC71_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59189   GPIO_PINCFG71_NCESRC71_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59190   GPIO_PINCFG71_NCESRC71_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59191   GPIO_PINCFG71_NCESRC71_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59192   GPIO_PINCFG71_NCESRC71_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59193   GPIO_PINCFG71_NCESRC71_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59194   GPIO_PINCFG71_NCESRC71_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59195   GPIO_PINCFG71_NCESRC71_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59196   GPIO_PINCFG71_NCESRC71_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59197   GPIO_PINCFG71_NCESRC71_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59198   GPIO_PINCFG71_NCESRC71_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59199   GPIO_PINCFG71_NCESRC71_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59200   GPIO_PINCFG71_NCESRC71_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59201   GPIO_PINCFG71_NCESRC71_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59202   GPIO_PINCFG71_NCESRC71_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59203   GPIO_PINCFG71_NCESRC71_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59204   GPIO_PINCFG71_NCESRC71_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59205   GPIO_PINCFG71_NCESRC71_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59206   GPIO_PINCFG71_NCESRC71_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59207   GPIO_PINCFG71_NCESRC71_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59208   GPIO_PINCFG71_NCESRC71_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59209   GPIO_PINCFG71_NCESRC71_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59210   GPIO_PINCFG71_NCESRC71_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59211   GPIO_PINCFG71_NCESRC71_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59212   GPIO_PINCFG71_NCESRC71_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59213   GPIO_PINCFG71_NCESRC71_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59214   GPIO_PINCFG71_NCESRC71_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59215   GPIO_PINCFG71_NCESRC71_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59216   GPIO_PINCFG71_NCESRC71_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59217   GPIO_PINCFG71_NCESRC71_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59218   GPIO_PINCFG71_NCESRC71_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59219   GPIO_PINCFG71_NCESRC71_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59220   GPIO_PINCFG71_NCESRC71_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59221 } GPIO_PINCFG71_NCESRC71_Enum;
59222 
59223 /* ===========================================  GPIO PINCFG71 PULLCFG71 [13..15]  ============================================ */
59224 typedef enum {                                  /*!< GPIO_PINCFG71_PULLCFG71                                                   */
59225   GPIO_PINCFG71_PULLCFG71_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59226   GPIO_PINCFG71_PULLCFG71_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59227   GPIO_PINCFG71_PULLCFG71_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59228   GPIO_PINCFG71_PULLCFG71_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59229   GPIO_PINCFG71_PULLCFG71_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59230   GPIO_PINCFG71_PULLCFG71_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59231   GPIO_PINCFG71_PULLCFG71_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59232   GPIO_PINCFG71_PULLCFG71_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59233 } GPIO_PINCFG71_PULLCFG71_Enum;
59234 
59235 /* ==============================================  GPIO PINCFG71 DS71 [10..11]  ============================================== */
59236 typedef enum {                                  /*!< GPIO_PINCFG71_DS71                                                        */
59237   GPIO_PINCFG71_DS71_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59238   GPIO_PINCFG71_DS71_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59239   GPIO_PINCFG71_DS71_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59240   GPIO_PINCFG71_DS71_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59241 } GPIO_PINCFG71_DS71_Enum;
59242 
59243 /* =============================================  GPIO PINCFG71 OUTCFG71 [8..9]  ============================================= */
59244 typedef enum {                                  /*!< GPIO_PINCFG71_OUTCFG71                                                    */
59245   GPIO_PINCFG71_OUTCFG71_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59246   GPIO_PINCFG71_OUTCFG71_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59247                                                      and 1 values on pin.                                                      */
59248   GPIO_PINCFG71_OUTCFG71_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59249                                                      low, tristate otherwise.                                                  */
59250   GPIO_PINCFG71_OUTCFG71_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59251                                                      drive 0, 1 of HiZ on pin.                                                 */
59252 } GPIO_PINCFG71_OUTCFG71_Enum;
59253 
59254 /* =============================================  GPIO PINCFG71 IRPTEN71 [6..7]  ============================================= */
59255 typedef enum {                                  /*!< GPIO_PINCFG71_IRPTEN71                                                    */
59256   GPIO_PINCFG71_IRPTEN71_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59257   GPIO_PINCFG71_IRPTEN71_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59258                                                      on this GPIO                                                              */
59259   GPIO_PINCFG71_IRPTEN71_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59260                                                      on this GPIO                                                              */
59261   GPIO_PINCFG71_IRPTEN71_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59262                                                      GPIO                                                                      */
59263 } GPIO_PINCFG71_IRPTEN71_Enum;
59264 
59265 /* =============================================  GPIO PINCFG71 FNCSEL71 [0..3]  ============================================= */
59266 typedef enum {                                  /*!< GPIO_PINCFG71_FNCSEL71                                                    */
59267   GPIO_PINCFG71_FNCSEL71_MSPI0_7       = 0,     /*!< MSPI0_7 : MSPI Master 0 Interface Signal                                  */
59268   GPIO_PINCFG71_FNCSEL71_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
59269   GPIO_PINCFG71_FNCSEL71_SWTRACE1      = 2,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
59270   GPIO_PINCFG71_FNCSEL71_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59271   GPIO_PINCFG71_FNCSEL71_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
59272   GPIO_PINCFG71_FNCSEL71_DISP_D7       = 5,     /*!< DISP_D7 : Display Data 7                                                  */
59273   GPIO_PINCFG71_FNCSEL71_CT71          = 6,     /*!< CT71 : Timer/Counter input or output; Selection of direction
59274                                                      is done via CTIMER register settings.                                     */
59275   GPIO_PINCFG71_FNCSEL71_NCE71         = 7,     /*!< NCE71 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59276                                                      CE_POLARITY field                                                         */
59277   GPIO_PINCFG71_FNCSEL71_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
59278   GPIO_PINCFG71_FNCSEL71_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59279   GPIO_PINCFG71_FNCSEL71_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59280   GPIO_PINCFG71_FNCSEL71_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59281   GPIO_PINCFG71_FNCSEL71_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59282   GPIO_PINCFG71_FNCSEL71_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59283   GPIO_PINCFG71_FNCSEL71_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59284   GPIO_PINCFG71_FNCSEL71_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59285 } GPIO_PINCFG71_FNCSEL71_Enum;
59286 
59287 /* =======================================================  PINCFG72  ======================================================== */
59288 /* ============================================  GPIO PINCFG72 NCEPOL72 [22..22]  ============================================ */
59289 typedef enum {                                  /*!< GPIO_PINCFG72_NCEPOL72                                                    */
59290   GPIO_PINCFG72_NCEPOL72_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59291   GPIO_PINCFG72_NCEPOL72_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59292 } GPIO_PINCFG72_NCEPOL72_Enum;
59293 
59294 /* ============================================  GPIO PINCFG72 NCESRC72 [16..21]  ============================================ */
59295 typedef enum {                                  /*!< GPIO_PINCFG72_NCESRC72                                                    */
59296   GPIO_PINCFG72_NCESRC72_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59297   GPIO_PINCFG72_NCESRC72_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59298   GPIO_PINCFG72_NCESRC72_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59299   GPIO_PINCFG72_NCESRC72_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59300   GPIO_PINCFG72_NCESRC72_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59301   GPIO_PINCFG72_NCESRC72_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59302   GPIO_PINCFG72_NCESRC72_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59303   GPIO_PINCFG72_NCESRC72_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59304   GPIO_PINCFG72_NCESRC72_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59305   GPIO_PINCFG72_NCESRC72_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59306   GPIO_PINCFG72_NCESRC72_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59307   GPIO_PINCFG72_NCESRC72_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59308   GPIO_PINCFG72_NCESRC72_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59309   GPIO_PINCFG72_NCESRC72_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59310   GPIO_PINCFG72_NCESRC72_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59311   GPIO_PINCFG72_NCESRC72_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59312   GPIO_PINCFG72_NCESRC72_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59313   GPIO_PINCFG72_NCESRC72_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59314   GPIO_PINCFG72_NCESRC72_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59315   GPIO_PINCFG72_NCESRC72_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59316   GPIO_PINCFG72_NCESRC72_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59317   GPIO_PINCFG72_NCESRC72_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59318   GPIO_PINCFG72_NCESRC72_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59319   GPIO_PINCFG72_NCESRC72_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59320   GPIO_PINCFG72_NCESRC72_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59321   GPIO_PINCFG72_NCESRC72_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59322   GPIO_PINCFG72_NCESRC72_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59323   GPIO_PINCFG72_NCESRC72_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59324   GPIO_PINCFG72_NCESRC72_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59325   GPIO_PINCFG72_NCESRC72_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59326   GPIO_PINCFG72_NCESRC72_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59327   GPIO_PINCFG72_NCESRC72_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59328   GPIO_PINCFG72_NCESRC72_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59329   GPIO_PINCFG72_NCESRC72_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59330   GPIO_PINCFG72_NCESRC72_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59331   GPIO_PINCFG72_NCESRC72_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59332   GPIO_PINCFG72_NCESRC72_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59333   GPIO_PINCFG72_NCESRC72_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59334   GPIO_PINCFG72_NCESRC72_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59335   GPIO_PINCFG72_NCESRC72_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59336   GPIO_PINCFG72_NCESRC72_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59337   GPIO_PINCFG72_NCESRC72_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59338   GPIO_PINCFG72_NCESRC72_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59339 } GPIO_PINCFG72_NCESRC72_Enum;
59340 
59341 /* ===========================================  GPIO PINCFG72 PULLCFG72 [13..15]  ============================================ */
59342 typedef enum {                                  /*!< GPIO_PINCFG72_PULLCFG72                                                   */
59343   GPIO_PINCFG72_PULLCFG72_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59344   GPIO_PINCFG72_PULLCFG72_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59345   GPIO_PINCFG72_PULLCFG72_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59346   GPIO_PINCFG72_PULLCFG72_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59347   GPIO_PINCFG72_PULLCFG72_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59348   GPIO_PINCFG72_PULLCFG72_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59349   GPIO_PINCFG72_PULLCFG72_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59350   GPIO_PINCFG72_PULLCFG72_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59351 } GPIO_PINCFG72_PULLCFG72_Enum;
59352 
59353 /* ==============================================  GPIO PINCFG72 DS72 [10..11]  ============================================== */
59354 typedef enum {                                  /*!< GPIO_PINCFG72_DS72                                                        */
59355   GPIO_PINCFG72_DS72_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59356   GPIO_PINCFG72_DS72_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59357   GPIO_PINCFG72_DS72_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59358   GPIO_PINCFG72_DS72_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59359 } GPIO_PINCFG72_DS72_Enum;
59360 
59361 /* =============================================  GPIO PINCFG72 OUTCFG72 [8..9]  ============================================= */
59362 typedef enum {                                  /*!< GPIO_PINCFG72_OUTCFG72                                                    */
59363   GPIO_PINCFG72_OUTCFG72_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59364   GPIO_PINCFG72_OUTCFG72_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59365                                                      and 1 values on pin.                                                      */
59366   GPIO_PINCFG72_OUTCFG72_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59367                                                      low, tristate otherwise.                                                  */
59368   GPIO_PINCFG72_OUTCFG72_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59369                                                      drive 0, 1 of HiZ on pin.                                                 */
59370 } GPIO_PINCFG72_OUTCFG72_Enum;
59371 
59372 /* =============================================  GPIO PINCFG72 IRPTEN72 [6..7]  ============================================= */
59373 typedef enum {                                  /*!< GPIO_PINCFG72_IRPTEN72                                                    */
59374   GPIO_PINCFG72_IRPTEN72_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59375   GPIO_PINCFG72_IRPTEN72_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59376                                                      on this GPIO                                                              */
59377   GPIO_PINCFG72_IRPTEN72_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59378                                                      on this GPIO                                                              */
59379   GPIO_PINCFG72_IRPTEN72_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59380                                                      GPIO                                                                      */
59381 } GPIO_PINCFG72_IRPTEN72_Enum;
59382 
59383 /* =============================================  GPIO PINCFG72 FNCSEL72 [0..3]  ============================================= */
59384 typedef enum {                                  /*!< GPIO_PINCFG72_FNCSEL72                                                    */
59385   GPIO_PINCFG72_FNCSEL72_MSPI0_8       = 0,     /*!< MSPI0_8 : MSPI Master 0 Interface Signal                                  */
59386   GPIO_PINCFG72_FNCSEL72_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
59387   GPIO_PINCFG72_FNCSEL72_SWTRACE2      = 2,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
59388   GPIO_PINCFG72_FNCSEL72_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59389   GPIO_PINCFG72_FNCSEL72_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
59390   GPIO_PINCFG72_FNCSEL72_DISP_D8       = 5,     /*!< DISP_D8 : Display Data 8                                                  */
59391   GPIO_PINCFG72_FNCSEL72_CT72          = 6,     /*!< CT72 : Timer/Counter input or output; Selection of direction
59392                                                      is done via CTIMER register settings.                                     */
59393   GPIO_PINCFG72_FNCSEL72_NCE72         = 7,     /*!< NCE72 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59394                                                      CE_POLARITY field                                                         */
59395   GPIO_PINCFG72_FNCSEL72_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
59396   GPIO_PINCFG72_FNCSEL72_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
59397   GPIO_PINCFG72_FNCSEL72_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59398   GPIO_PINCFG72_FNCSEL72_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59399   GPIO_PINCFG72_FNCSEL72_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59400   GPIO_PINCFG72_FNCSEL72_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59401   GPIO_PINCFG72_FNCSEL72_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59402   GPIO_PINCFG72_FNCSEL72_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59403 } GPIO_PINCFG72_FNCSEL72_Enum;
59404 
59405 /* =======================================================  PINCFG73  ======================================================== */
59406 /* ============================================  GPIO PINCFG73 NCEPOL73 [22..22]  ============================================ */
59407 typedef enum {                                  /*!< GPIO_PINCFG73_NCEPOL73                                                    */
59408   GPIO_PINCFG73_NCEPOL73_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59409   GPIO_PINCFG73_NCEPOL73_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59410 } GPIO_PINCFG73_NCEPOL73_Enum;
59411 
59412 /* ============================================  GPIO PINCFG73 NCESRC73 [16..21]  ============================================ */
59413 typedef enum {                                  /*!< GPIO_PINCFG73_NCESRC73                                                    */
59414   GPIO_PINCFG73_NCESRC73_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59415   GPIO_PINCFG73_NCESRC73_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59416   GPIO_PINCFG73_NCESRC73_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59417   GPIO_PINCFG73_NCESRC73_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59418   GPIO_PINCFG73_NCESRC73_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59419   GPIO_PINCFG73_NCESRC73_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59420   GPIO_PINCFG73_NCESRC73_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59421   GPIO_PINCFG73_NCESRC73_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59422   GPIO_PINCFG73_NCESRC73_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59423   GPIO_PINCFG73_NCESRC73_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59424   GPIO_PINCFG73_NCESRC73_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59425   GPIO_PINCFG73_NCESRC73_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59426   GPIO_PINCFG73_NCESRC73_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59427   GPIO_PINCFG73_NCESRC73_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59428   GPIO_PINCFG73_NCESRC73_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59429   GPIO_PINCFG73_NCESRC73_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59430   GPIO_PINCFG73_NCESRC73_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59431   GPIO_PINCFG73_NCESRC73_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59432   GPIO_PINCFG73_NCESRC73_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59433   GPIO_PINCFG73_NCESRC73_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59434   GPIO_PINCFG73_NCESRC73_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59435   GPIO_PINCFG73_NCESRC73_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59436   GPIO_PINCFG73_NCESRC73_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59437   GPIO_PINCFG73_NCESRC73_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59438   GPIO_PINCFG73_NCESRC73_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59439   GPIO_PINCFG73_NCESRC73_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59440   GPIO_PINCFG73_NCESRC73_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59441   GPIO_PINCFG73_NCESRC73_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59442   GPIO_PINCFG73_NCESRC73_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59443   GPIO_PINCFG73_NCESRC73_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59444   GPIO_PINCFG73_NCESRC73_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59445   GPIO_PINCFG73_NCESRC73_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59446   GPIO_PINCFG73_NCESRC73_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59447   GPIO_PINCFG73_NCESRC73_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59448   GPIO_PINCFG73_NCESRC73_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59449   GPIO_PINCFG73_NCESRC73_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59450   GPIO_PINCFG73_NCESRC73_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59451   GPIO_PINCFG73_NCESRC73_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59452   GPIO_PINCFG73_NCESRC73_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59453   GPIO_PINCFG73_NCESRC73_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59454   GPIO_PINCFG73_NCESRC73_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59455   GPIO_PINCFG73_NCESRC73_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59456   GPIO_PINCFG73_NCESRC73_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59457 } GPIO_PINCFG73_NCESRC73_Enum;
59458 
59459 /* ===========================================  GPIO PINCFG73 PULLCFG73 [13..15]  ============================================ */
59460 typedef enum {                                  /*!< GPIO_PINCFG73_PULLCFG73                                                   */
59461   GPIO_PINCFG73_PULLCFG73_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59462   GPIO_PINCFG73_PULLCFG73_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59463   GPIO_PINCFG73_PULLCFG73_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59464   GPIO_PINCFG73_PULLCFG73_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59465   GPIO_PINCFG73_PULLCFG73_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59466   GPIO_PINCFG73_PULLCFG73_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59467   GPIO_PINCFG73_PULLCFG73_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59468   GPIO_PINCFG73_PULLCFG73_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59469 } GPIO_PINCFG73_PULLCFG73_Enum;
59470 
59471 /* ==============================================  GPIO PINCFG73 DS73 [10..11]  ============================================== */
59472 typedef enum {                                  /*!< GPIO_PINCFG73_DS73                                                        */
59473   GPIO_PINCFG73_DS73_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59474   GPIO_PINCFG73_DS73_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59475   GPIO_PINCFG73_DS73_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59476   GPIO_PINCFG73_DS73_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59477 } GPIO_PINCFG73_DS73_Enum;
59478 
59479 /* =============================================  GPIO PINCFG73 OUTCFG73 [8..9]  ============================================= */
59480 typedef enum {                                  /*!< GPIO_PINCFG73_OUTCFG73                                                    */
59481   GPIO_PINCFG73_OUTCFG73_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59482   GPIO_PINCFG73_OUTCFG73_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59483                                                      and 1 values on pin.                                                      */
59484   GPIO_PINCFG73_OUTCFG73_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59485                                                      low, tristate otherwise.                                                  */
59486   GPIO_PINCFG73_OUTCFG73_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59487                                                      drive 0, 1 of HiZ on pin.                                                 */
59488 } GPIO_PINCFG73_OUTCFG73_Enum;
59489 
59490 /* =============================================  GPIO PINCFG73 IRPTEN73 [6..7]  ============================================= */
59491 typedef enum {                                  /*!< GPIO_PINCFG73_IRPTEN73                                                    */
59492   GPIO_PINCFG73_IRPTEN73_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59493   GPIO_PINCFG73_IRPTEN73_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59494                                                      on this GPIO                                                              */
59495   GPIO_PINCFG73_IRPTEN73_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59496                                                      on this GPIO                                                              */
59497   GPIO_PINCFG73_IRPTEN73_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59498                                                      GPIO                                                                      */
59499 } GPIO_PINCFG73_IRPTEN73_Enum;
59500 
59501 /* =============================================  GPIO PINCFG73 FNCSEL73 [0..3]  ============================================= */
59502 typedef enum {                                  /*!< GPIO_PINCFG73_FNCSEL73                                                    */
59503   GPIO_PINCFG73_FNCSEL73_MSPI0_9       = 0,     /*!< MSPI0_9 : MSPI Master 0 Interface Signal                                  */
59504   GPIO_PINCFG73_FNCSEL73_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
59505   GPIO_PINCFG73_FNCSEL73_SWTRACE3      = 2,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
59506   GPIO_PINCFG73_FNCSEL73_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59507   GPIO_PINCFG73_FNCSEL73_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
59508   GPIO_PINCFG73_FNCSEL73_DISP_D9       = 5,     /*!< DISP_D9 : Display Data 9                                                  */
59509   GPIO_PINCFG73_FNCSEL73_CT73          = 6,     /*!< CT73 : Timer/Counter input or output; Selection of direction
59510                                                      is done via CTIMER register settings.                                     */
59511   GPIO_PINCFG73_FNCSEL73_NCE73         = 7,     /*!< NCE73 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59512                                                      CE_POLARITY field                                                         */
59513   GPIO_PINCFG73_FNCSEL73_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
59514   GPIO_PINCFG73_FNCSEL73_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59515   GPIO_PINCFG73_FNCSEL73_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59516   GPIO_PINCFG73_FNCSEL73_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59517   GPIO_PINCFG73_FNCSEL73_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59518   GPIO_PINCFG73_FNCSEL73_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59519   GPIO_PINCFG73_FNCSEL73_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59520   GPIO_PINCFG73_FNCSEL73_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59521 } GPIO_PINCFG73_FNCSEL73_Enum;
59522 
59523 /* =======================================================  PINCFG74  ======================================================== */
59524 /* ============================================  GPIO PINCFG74 NCEPOL74 [22..22]  ============================================ */
59525 typedef enum {                                  /*!< GPIO_PINCFG74_NCEPOL74                                                    */
59526   GPIO_PINCFG74_NCEPOL74_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59527   GPIO_PINCFG74_NCEPOL74_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59528 } GPIO_PINCFG74_NCEPOL74_Enum;
59529 
59530 /* ============================================  GPIO PINCFG74 NCESRC74 [16..21]  ============================================ */
59531 typedef enum {                                  /*!< GPIO_PINCFG74_NCESRC74                                                    */
59532   GPIO_PINCFG74_NCESRC74_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59533   GPIO_PINCFG74_NCESRC74_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59534   GPIO_PINCFG74_NCESRC74_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59535   GPIO_PINCFG74_NCESRC74_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59536   GPIO_PINCFG74_NCESRC74_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59537   GPIO_PINCFG74_NCESRC74_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59538   GPIO_PINCFG74_NCESRC74_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59539   GPIO_PINCFG74_NCESRC74_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59540   GPIO_PINCFG74_NCESRC74_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59541   GPIO_PINCFG74_NCESRC74_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59542   GPIO_PINCFG74_NCESRC74_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59543   GPIO_PINCFG74_NCESRC74_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59544   GPIO_PINCFG74_NCESRC74_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59545   GPIO_PINCFG74_NCESRC74_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59546   GPIO_PINCFG74_NCESRC74_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59547   GPIO_PINCFG74_NCESRC74_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59548   GPIO_PINCFG74_NCESRC74_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59549   GPIO_PINCFG74_NCESRC74_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59550   GPIO_PINCFG74_NCESRC74_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59551   GPIO_PINCFG74_NCESRC74_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59552   GPIO_PINCFG74_NCESRC74_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59553   GPIO_PINCFG74_NCESRC74_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59554   GPIO_PINCFG74_NCESRC74_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59555   GPIO_PINCFG74_NCESRC74_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59556   GPIO_PINCFG74_NCESRC74_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59557   GPIO_PINCFG74_NCESRC74_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59558   GPIO_PINCFG74_NCESRC74_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59559   GPIO_PINCFG74_NCESRC74_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59560   GPIO_PINCFG74_NCESRC74_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59561   GPIO_PINCFG74_NCESRC74_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59562   GPIO_PINCFG74_NCESRC74_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59563   GPIO_PINCFG74_NCESRC74_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59564   GPIO_PINCFG74_NCESRC74_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59565   GPIO_PINCFG74_NCESRC74_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59566   GPIO_PINCFG74_NCESRC74_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59567   GPIO_PINCFG74_NCESRC74_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59568   GPIO_PINCFG74_NCESRC74_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59569   GPIO_PINCFG74_NCESRC74_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59570   GPIO_PINCFG74_NCESRC74_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59571   GPIO_PINCFG74_NCESRC74_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59572   GPIO_PINCFG74_NCESRC74_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59573   GPIO_PINCFG74_NCESRC74_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59574   GPIO_PINCFG74_NCESRC74_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59575 } GPIO_PINCFG74_NCESRC74_Enum;
59576 
59577 /* ===========================================  GPIO PINCFG74 PULLCFG74 [13..15]  ============================================ */
59578 typedef enum {                                  /*!< GPIO_PINCFG74_PULLCFG74                                                   */
59579   GPIO_PINCFG74_PULLCFG74_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59580   GPIO_PINCFG74_PULLCFG74_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59581   GPIO_PINCFG74_PULLCFG74_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59582   GPIO_PINCFG74_PULLCFG74_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59583   GPIO_PINCFG74_PULLCFG74_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59584   GPIO_PINCFG74_PULLCFG74_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59585   GPIO_PINCFG74_PULLCFG74_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59586   GPIO_PINCFG74_PULLCFG74_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59587 } GPIO_PINCFG74_PULLCFG74_Enum;
59588 
59589 /* ==============================================  GPIO PINCFG74 DS74 [10..11]  ============================================== */
59590 typedef enum {                                  /*!< GPIO_PINCFG74_DS74                                                        */
59591   GPIO_PINCFG74_DS74_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59592   GPIO_PINCFG74_DS74_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59593   GPIO_PINCFG74_DS74_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59594   GPIO_PINCFG74_DS74_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59595 } GPIO_PINCFG74_DS74_Enum;
59596 
59597 /* =============================================  GPIO PINCFG74 OUTCFG74 [8..9]  ============================================= */
59598 typedef enum {                                  /*!< GPIO_PINCFG74_OUTCFG74                                                    */
59599   GPIO_PINCFG74_OUTCFG74_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59600   GPIO_PINCFG74_OUTCFG74_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59601                                                      and 1 values on pin.                                                      */
59602   GPIO_PINCFG74_OUTCFG74_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59603                                                      low, tristate otherwise.                                                  */
59604   GPIO_PINCFG74_OUTCFG74_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59605                                                      drive 0, 1 of HiZ on pin.                                                 */
59606 } GPIO_PINCFG74_OUTCFG74_Enum;
59607 
59608 /* =============================================  GPIO PINCFG74 IRPTEN74 [6..7]  ============================================= */
59609 typedef enum {                                  /*!< GPIO_PINCFG74_IRPTEN74                                                    */
59610   GPIO_PINCFG74_IRPTEN74_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59611   GPIO_PINCFG74_IRPTEN74_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59612                                                      on this GPIO                                                              */
59613   GPIO_PINCFG74_IRPTEN74_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59614                                                      on this GPIO                                                              */
59615   GPIO_PINCFG74_IRPTEN74_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59616                                                      GPIO                                                                      */
59617 } GPIO_PINCFG74_IRPTEN74_Enum;
59618 
59619 /* =============================================  GPIO PINCFG74 FNCSEL74 [0..3]  ============================================= */
59620 typedef enum {                                  /*!< GPIO_PINCFG74_FNCSEL74                                                    */
59621   GPIO_PINCFG74_FNCSEL74_MSPI2_0       = 0,     /*!< MSPI2_0 : MSPI Master 2 Interface Signal                                  */
59622   GPIO_PINCFG74_FNCSEL74_DISP_QSPI_D0_OUT = 1,  /*!< DISP_QSPI_D0_OUT : Display SPI Data0                                      */
59623   GPIO_PINCFG74_FNCSEL74_DISP_QSPI_D0  = 2,     /*!< DISP_QSPI_D0 : Display SPI Data0                                          */
59624   GPIO_PINCFG74_FNCSEL74_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59625   GPIO_PINCFG74_FNCSEL74_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
59626   GPIO_PINCFG74_FNCSEL74_DISP_D10      = 5,     /*!< DISP_D10 : Display Data 10                                                */
59627   GPIO_PINCFG74_FNCSEL74_CT74          = 6,     /*!< CT74 : Timer/Counter input or output; Selection of direction
59628                                                      is done via CTIMER register settings.                                     */
59629   GPIO_PINCFG74_FNCSEL74_NCE74         = 7,     /*!< NCE74 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59630                                                      CE_POLARITY field                                                         */
59631   GPIO_PINCFG74_FNCSEL74_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
59632   GPIO_PINCFG74_FNCSEL74_DISP_SPI_SD   = 9,     /*!< DISP_SPI_SD : Display SPI Data Out                                        */
59633   GPIO_PINCFG74_FNCSEL74_DISP_SPI_SDO  = 10,    /*!< DISP_SPI_SDO : Display SPI Data Out                                       */
59634   GPIO_PINCFG74_FNCSEL74_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59635   GPIO_PINCFG74_FNCSEL74_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59636   GPIO_PINCFG74_FNCSEL74_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59637   GPIO_PINCFG74_FNCSEL74_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59638   GPIO_PINCFG74_FNCSEL74_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59639 } GPIO_PINCFG74_FNCSEL74_Enum;
59640 
59641 /* =======================================================  PINCFG75  ======================================================== */
59642 /* ============================================  GPIO PINCFG75 NCEPOL75 [22..22]  ============================================ */
59643 typedef enum {                                  /*!< GPIO_PINCFG75_NCEPOL75                                                    */
59644   GPIO_PINCFG75_NCEPOL75_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59645   GPIO_PINCFG75_NCEPOL75_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59646 } GPIO_PINCFG75_NCEPOL75_Enum;
59647 
59648 /* ============================================  GPIO PINCFG75 NCESRC75 [16..21]  ============================================ */
59649 typedef enum {                                  /*!< GPIO_PINCFG75_NCESRC75                                                    */
59650   GPIO_PINCFG75_NCESRC75_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59651   GPIO_PINCFG75_NCESRC75_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59652   GPIO_PINCFG75_NCESRC75_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59653   GPIO_PINCFG75_NCESRC75_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59654   GPIO_PINCFG75_NCESRC75_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59655   GPIO_PINCFG75_NCESRC75_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59656   GPIO_PINCFG75_NCESRC75_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59657   GPIO_PINCFG75_NCESRC75_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59658   GPIO_PINCFG75_NCESRC75_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59659   GPIO_PINCFG75_NCESRC75_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59660   GPIO_PINCFG75_NCESRC75_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59661   GPIO_PINCFG75_NCESRC75_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59662   GPIO_PINCFG75_NCESRC75_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59663   GPIO_PINCFG75_NCESRC75_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59664   GPIO_PINCFG75_NCESRC75_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59665   GPIO_PINCFG75_NCESRC75_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59666   GPIO_PINCFG75_NCESRC75_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59667   GPIO_PINCFG75_NCESRC75_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59668   GPIO_PINCFG75_NCESRC75_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59669   GPIO_PINCFG75_NCESRC75_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59670   GPIO_PINCFG75_NCESRC75_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59671   GPIO_PINCFG75_NCESRC75_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59672   GPIO_PINCFG75_NCESRC75_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59673   GPIO_PINCFG75_NCESRC75_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59674   GPIO_PINCFG75_NCESRC75_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59675   GPIO_PINCFG75_NCESRC75_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59676   GPIO_PINCFG75_NCESRC75_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59677   GPIO_PINCFG75_NCESRC75_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59678   GPIO_PINCFG75_NCESRC75_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59679   GPIO_PINCFG75_NCESRC75_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59680   GPIO_PINCFG75_NCESRC75_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59681   GPIO_PINCFG75_NCESRC75_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59682   GPIO_PINCFG75_NCESRC75_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59683   GPIO_PINCFG75_NCESRC75_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59684   GPIO_PINCFG75_NCESRC75_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59685   GPIO_PINCFG75_NCESRC75_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59686   GPIO_PINCFG75_NCESRC75_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59687   GPIO_PINCFG75_NCESRC75_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59688   GPIO_PINCFG75_NCESRC75_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59689   GPIO_PINCFG75_NCESRC75_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59690   GPIO_PINCFG75_NCESRC75_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59691   GPIO_PINCFG75_NCESRC75_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59692   GPIO_PINCFG75_NCESRC75_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59693 } GPIO_PINCFG75_NCESRC75_Enum;
59694 
59695 /* ===========================================  GPIO PINCFG75 PULLCFG75 [13..15]  ============================================ */
59696 typedef enum {                                  /*!< GPIO_PINCFG75_PULLCFG75                                                   */
59697   GPIO_PINCFG75_PULLCFG75_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59698   GPIO_PINCFG75_PULLCFG75_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59699   GPIO_PINCFG75_PULLCFG75_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59700   GPIO_PINCFG75_PULLCFG75_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59701   GPIO_PINCFG75_PULLCFG75_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59702   GPIO_PINCFG75_PULLCFG75_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59703   GPIO_PINCFG75_PULLCFG75_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59704   GPIO_PINCFG75_PULLCFG75_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59705 } GPIO_PINCFG75_PULLCFG75_Enum;
59706 
59707 /* ==============================================  GPIO PINCFG75 DS75 [10..11]  ============================================== */
59708 typedef enum {                                  /*!< GPIO_PINCFG75_DS75                                                        */
59709   GPIO_PINCFG75_DS75_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59710   GPIO_PINCFG75_DS75_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59711   GPIO_PINCFG75_DS75_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59712   GPIO_PINCFG75_DS75_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59713 } GPIO_PINCFG75_DS75_Enum;
59714 
59715 /* =============================================  GPIO PINCFG75 OUTCFG75 [8..9]  ============================================= */
59716 typedef enum {                                  /*!< GPIO_PINCFG75_OUTCFG75                                                    */
59717   GPIO_PINCFG75_OUTCFG75_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59718   GPIO_PINCFG75_OUTCFG75_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59719                                                      and 1 values on pin.                                                      */
59720   GPIO_PINCFG75_OUTCFG75_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59721                                                      low, tristate otherwise.                                                  */
59722   GPIO_PINCFG75_OUTCFG75_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59723                                                      drive 0, 1 of HiZ on pin.                                                 */
59724 } GPIO_PINCFG75_OUTCFG75_Enum;
59725 
59726 /* =============================================  GPIO PINCFG75 IRPTEN75 [6..7]  ============================================= */
59727 typedef enum {                                  /*!< GPIO_PINCFG75_IRPTEN75                                                    */
59728   GPIO_PINCFG75_IRPTEN75_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59729   GPIO_PINCFG75_IRPTEN75_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59730                                                      on this GPIO                                                              */
59731   GPIO_PINCFG75_IRPTEN75_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59732                                                      on this GPIO                                                              */
59733   GPIO_PINCFG75_IRPTEN75_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59734                                                      GPIO                                                                      */
59735 } GPIO_PINCFG75_IRPTEN75_Enum;
59736 
59737 /* =============================================  GPIO PINCFG75 FNCSEL75 [0..3]  ============================================= */
59738 typedef enum {                                  /*!< GPIO_PINCFG75_FNCSEL75                                                    */
59739   GPIO_PINCFG75_FNCSEL75_MSPI2_1       = 0,     /*!< MSPI2_1 : MSPI Master 2 Interface Signal                                  */
59740   GPIO_PINCFG75_FNCSEL75_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
59741   GPIO_PINCFG75_FNCSEL75_DISP_QSPI_D1  = 2,     /*!< DISP_QSPI_D1 : Display SPI Data1                                          */
59742   GPIO_PINCFG75_FNCSEL75_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59743   GPIO_PINCFG75_FNCSEL75_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
59744   GPIO_PINCFG75_FNCSEL75_DISP_D11      = 5,     /*!< DISP_D11 : Display Data 11                                                */
59745   GPIO_PINCFG75_FNCSEL75_CT75          = 6,     /*!< CT75 : Timer/Counter input or output; Selection of direction
59746                                                      is done via CTIMER register settings.                                     */
59747   GPIO_PINCFG75_FNCSEL75_NCE75         = 7,     /*!< NCE75 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59748                                                      CE_POLARITY field                                                         */
59749   GPIO_PINCFG75_FNCSEL75_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
59750   GPIO_PINCFG75_FNCSEL75_DISP_SPI_DCX  = 9,     /*!< DISP_SPI_DCX : Display SPI DCx                                            */
59751   GPIO_PINCFG75_FNCSEL75_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59752   GPIO_PINCFG75_FNCSEL75_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59753   GPIO_PINCFG75_FNCSEL75_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59754   GPIO_PINCFG75_FNCSEL75_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59755   GPIO_PINCFG75_FNCSEL75_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59756   GPIO_PINCFG75_FNCSEL75_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59757 } GPIO_PINCFG75_FNCSEL75_Enum;
59758 
59759 /* =======================================================  PINCFG76  ======================================================== */
59760 /* ============================================  GPIO PINCFG76 NCEPOL76 [22..22]  ============================================ */
59761 typedef enum {                                  /*!< GPIO_PINCFG76_NCEPOL76                                                    */
59762   GPIO_PINCFG76_NCEPOL76_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59763   GPIO_PINCFG76_NCEPOL76_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59764 } GPIO_PINCFG76_NCEPOL76_Enum;
59765 
59766 /* ============================================  GPIO PINCFG76 NCESRC76 [16..21]  ============================================ */
59767 typedef enum {                                  /*!< GPIO_PINCFG76_NCESRC76                                                    */
59768   GPIO_PINCFG76_NCESRC76_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59769   GPIO_PINCFG76_NCESRC76_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59770   GPIO_PINCFG76_NCESRC76_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59771   GPIO_PINCFG76_NCESRC76_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59772   GPIO_PINCFG76_NCESRC76_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59773   GPIO_PINCFG76_NCESRC76_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59774   GPIO_PINCFG76_NCESRC76_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59775   GPIO_PINCFG76_NCESRC76_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59776   GPIO_PINCFG76_NCESRC76_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59777   GPIO_PINCFG76_NCESRC76_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59778   GPIO_PINCFG76_NCESRC76_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59779   GPIO_PINCFG76_NCESRC76_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59780   GPIO_PINCFG76_NCESRC76_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59781   GPIO_PINCFG76_NCESRC76_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59782   GPIO_PINCFG76_NCESRC76_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59783   GPIO_PINCFG76_NCESRC76_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59784   GPIO_PINCFG76_NCESRC76_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59785   GPIO_PINCFG76_NCESRC76_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59786   GPIO_PINCFG76_NCESRC76_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59787   GPIO_PINCFG76_NCESRC76_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59788   GPIO_PINCFG76_NCESRC76_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59789   GPIO_PINCFG76_NCESRC76_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59790   GPIO_PINCFG76_NCESRC76_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59791   GPIO_PINCFG76_NCESRC76_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59792   GPIO_PINCFG76_NCESRC76_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59793   GPIO_PINCFG76_NCESRC76_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59794   GPIO_PINCFG76_NCESRC76_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59795   GPIO_PINCFG76_NCESRC76_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59796   GPIO_PINCFG76_NCESRC76_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59797   GPIO_PINCFG76_NCESRC76_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59798   GPIO_PINCFG76_NCESRC76_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59799   GPIO_PINCFG76_NCESRC76_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59800   GPIO_PINCFG76_NCESRC76_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59801   GPIO_PINCFG76_NCESRC76_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59802   GPIO_PINCFG76_NCESRC76_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59803   GPIO_PINCFG76_NCESRC76_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59804   GPIO_PINCFG76_NCESRC76_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59805   GPIO_PINCFG76_NCESRC76_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59806   GPIO_PINCFG76_NCESRC76_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59807   GPIO_PINCFG76_NCESRC76_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59808   GPIO_PINCFG76_NCESRC76_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59809   GPIO_PINCFG76_NCESRC76_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59810   GPIO_PINCFG76_NCESRC76_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59811 } GPIO_PINCFG76_NCESRC76_Enum;
59812 
59813 /* ===========================================  GPIO PINCFG76 PULLCFG76 [13..15]  ============================================ */
59814 typedef enum {                                  /*!< GPIO_PINCFG76_PULLCFG76                                                   */
59815   GPIO_PINCFG76_PULLCFG76_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59816   GPIO_PINCFG76_PULLCFG76_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59817   GPIO_PINCFG76_PULLCFG76_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59818   GPIO_PINCFG76_PULLCFG76_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59819   GPIO_PINCFG76_PULLCFG76_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59820   GPIO_PINCFG76_PULLCFG76_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59821   GPIO_PINCFG76_PULLCFG76_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59822   GPIO_PINCFG76_PULLCFG76_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59823 } GPIO_PINCFG76_PULLCFG76_Enum;
59824 
59825 /* ==============================================  GPIO PINCFG76 DS76 [10..11]  ============================================== */
59826 typedef enum {                                  /*!< GPIO_PINCFG76_DS76                                                        */
59827   GPIO_PINCFG76_DS76_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59828   GPIO_PINCFG76_DS76_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59829   GPIO_PINCFG76_DS76_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59830   GPIO_PINCFG76_DS76_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59831 } GPIO_PINCFG76_DS76_Enum;
59832 
59833 /* =============================================  GPIO PINCFG76 OUTCFG76 [8..9]  ============================================= */
59834 typedef enum {                                  /*!< GPIO_PINCFG76_OUTCFG76                                                    */
59835   GPIO_PINCFG76_OUTCFG76_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59836   GPIO_PINCFG76_OUTCFG76_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59837                                                      and 1 values on pin.                                                      */
59838   GPIO_PINCFG76_OUTCFG76_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59839                                                      low, tristate otherwise.                                                  */
59840   GPIO_PINCFG76_OUTCFG76_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59841                                                      drive 0, 1 of HiZ on pin.                                                 */
59842 } GPIO_PINCFG76_OUTCFG76_Enum;
59843 
59844 /* =============================================  GPIO PINCFG76 IRPTEN76 [6..7]  ============================================= */
59845 typedef enum {                                  /*!< GPIO_PINCFG76_IRPTEN76                                                    */
59846   GPIO_PINCFG76_IRPTEN76_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59847   GPIO_PINCFG76_IRPTEN76_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59848                                                      on this GPIO                                                              */
59849   GPIO_PINCFG76_IRPTEN76_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59850                                                      on this GPIO                                                              */
59851   GPIO_PINCFG76_IRPTEN76_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59852                                                      GPIO                                                                      */
59853 } GPIO_PINCFG76_IRPTEN76_Enum;
59854 
59855 /* =============================================  GPIO PINCFG76 FNCSEL76 [0..3]  ============================================= */
59856 typedef enum {                                  /*!< GPIO_PINCFG76_FNCSEL76                                                    */
59857   GPIO_PINCFG76_FNCSEL76_MSPI2_2       = 0,     /*!< MSPI2_2 : MSPI Master 2 Interface Signal                                  */
59858   GPIO_PINCFG76_FNCSEL76_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
59859   GPIO_PINCFG76_FNCSEL76_DISP_QSPI_D2  = 2,     /*!< DISP_QSPI_D2 : Display SPI Data2                                          */
59860   GPIO_PINCFG76_FNCSEL76_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59861   GPIO_PINCFG76_FNCSEL76_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
59862   GPIO_PINCFG76_FNCSEL76_DISP_D12      = 5,     /*!< DISP_D12 : Display Data 12                                                */
59863   GPIO_PINCFG76_FNCSEL76_CT76          = 6,     /*!< CT76 : Timer/Counter input or output; Selection of direction
59864                                                      is done via CTIMER register settings.                                     */
59865   GPIO_PINCFG76_FNCSEL76_NCE76         = 7,     /*!< NCE76 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59866                                                      CE_POLARITY field                                                         */
59867   GPIO_PINCFG76_FNCSEL76_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
59868   GPIO_PINCFG76_FNCSEL76_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59869   GPIO_PINCFG76_FNCSEL76_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59870   GPIO_PINCFG76_FNCSEL76_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59871   GPIO_PINCFG76_FNCSEL76_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59872   GPIO_PINCFG76_FNCSEL76_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59873   GPIO_PINCFG76_FNCSEL76_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59874   GPIO_PINCFG76_FNCSEL76_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59875 } GPIO_PINCFG76_FNCSEL76_Enum;
59876 
59877 /* =======================================================  PINCFG77  ======================================================== */
59878 /* ============================================  GPIO PINCFG77 NCEPOL77 [22..22]  ============================================ */
59879 typedef enum {                                  /*!< GPIO_PINCFG77_NCEPOL77                                                    */
59880   GPIO_PINCFG77_NCEPOL77_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59881   GPIO_PINCFG77_NCEPOL77_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
59882 } GPIO_PINCFG77_NCEPOL77_Enum;
59883 
59884 /* ============================================  GPIO PINCFG77 NCESRC77 [16..21]  ============================================ */
59885 typedef enum {                                  /*!< GPIO_PINCFG77_NCESRC77                                                    */
59886   GPIO_PINCFG77_NCESRC77_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
59887   GPIO_PINCFG77_NCESRC77_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
59888   GPIO_PINCFG77_NCESRC77_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
59889   GPIO_PINCFG77_NCESRC77_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
59890   GPIO_PINCFG77_NCESRC77_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
59891   GPIO_PINCFG77_NCESRC77_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
59892   GPIO_PINCFG77_NCESRC77_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
59893   GPIO_PINCFG77_NCESRC77_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
59894   GPIO_PINCFG77_NCESRC77_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
59895   GPIO_PINCFG77_NCESRC77_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
59896   GPIO_PINCFG77_NCESRC77_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
59897   GPIO_PINCFG77_NCESRC77_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
59898   GPIO_PINCFG77_NCESRC77_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
59899   GPIO_PINCFG77_NCESRC77_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
59900   GPIO_PINCFG77_NCESRC77_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
59901   GPIO_PINCFG77_NCESRC77_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
59902   GPIO_PINCFG77_NCESRC77_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
59903   GPIO_PINCFG77_NCESRC77_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
59904   GPIO_PINCFG77_NCESRC77_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
59905   GPIO_PINCFG77_NCESRC77_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
59906   GPIO_PINCFG77_NCESRC77_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
59907   GPIO_PINCFG77_NCESRC77_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
59908   GPIO_PINCFG77_NCESRC77_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
59909   GPIO_PINCFG77_NCESRC77_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
59910   GPIO_PINCFG77_NCESRC77_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
59911   GPIO_PINCFG77_NCESRC77_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
59912   GPIO_PINCFG77_NCESRC77_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
59913   GPIO_PINCFG77_NCESRC77_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
59914   GPIO_PINCFG77_NCESRC77_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
59915   GPIO_PINCFG77_NCESRC77_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
59916   GPIO_PINCFG77_NCESRC77_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
59917   GPIO_PINCFG77_NCESRC77_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
59918   GPIO_PINCFG77_NCESRC77_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
59919   GPIO_PINCFG77_NCESRC77_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
59920   GPIO_PINCFG77_NCESRC77_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
59921   GPIO_PINCFG77_NCESRC77_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
59922   GPIO_PINCFG77_NCESRC77_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
59923   GPIO_PINCFG77_NCESRC77_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
59924   GPIO_PINCFG77_NCESRC77_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
59925   GPIO_PINCFG77_NCESRC77_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
59926   GPIO_PINCFG77_NCESRC77_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
59927   GPIO_PINCFG77_NCESRC77_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
59928   GPIO_PINCFG77_NCESRC77_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
59929 } GPIO_PINCFG77_NCESRC77_Enum;
59930 
59931 /* ===========================================  GPIO PINCFG77 PULLCFG77 [13..15]  ============================================ */
59932 typedef enum {                                  /*!< GPIO_PINCFG77_PULLCFG77                                                   */
59933   GPIO_PINCFG77_PULLCFG77_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
59934   GPIO_PINCFG77_PULLCFG77_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
59935   GPIO_PINCFG77_PULLCFG77_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
59936   GPIO_PINCFG77_PULLCFG77_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
59937   GPIO_PINCFG77_PULLCFG77_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
59938   GPIO_PINCFG77_PULLCFG77_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
59939   GPIO_PINCFG77_PULLCFG77_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
59940   GPIO_PINCFG77_PULLCFG77_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
59941 } GPIO_PINCFG77_PULLCFG77_Enum;
59942 
59943 /* ==============================================  GPIO PINCFG77 DS77 [10..11]  ============================================== */
59944 typedef enum {                                  /*!< GPIO_PINCFG77_DS77                                                        */
59945   GPIO_PINCFG77_DS77_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
59946   GPIO_PINCFG77_DS77_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
59947   GPIO_PINCFG77_DS77_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
59948   GPIO_PINCFG77_DS77_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
59949 } GPIO_PINCFG77_DS77_Enum;
59950 
59951 /* =============================================  GPIO PINCFG77 OUTCFG77 [8..9]  ============================================= */
59952 typedef enum {                                  /*!< GPIO_PINCFG77_OUTCFG77                                                    */
59953   GPIO_PINCFG77_OUTCFG77_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
59954   GPIO_PINCFG77_OUTCFG77_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
59955                                                      and 1 values on pin.                                                      */
59956   GPIO_PINCFG77_OUTCFG77_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
59957                                                      low, tristate otherwise.                                                  */
59958   GPIO_PINCFG77_OUTCFG77_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
59959                                                      drive 0, 1 of HiZ on pin.                                                 */
59960 } GPIO_PINCFG77_OUTCFG77_Enum;
59961 
59962 /* =============================================  GPIO PINCFG77 IRPTEN77 [6..7]  ============================================= */
59963 typedef enum {                                  /*!< GPIO_PINCFG77_IRPTEN77                                                    */
59964   GPIO_PINCFG77_IRPTEN77_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
59965   GPIO_PINCFG77_IRPTEN77_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
59966                                                      on this GPIO                                                              */
59967   GPIO_PINCFG77_IRPTEN77_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
59968                                                      on this GPIO                                                              */
59969   GPIO_PINCFG77_IRPTEN77_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
59970                                                      GPIO                                                                      */
59971 } GPIO_PINCFG77_IRPTEN77_Enum;
59972 
59973 /* =============================================  GPIO PINCFG77 FNCSEL77 [0..3]  ============================================= */
59974 typedef enum {                                  /*!< GPIO_PINCFG77_FNCSEL77                                                    */
59975   GPIO_PINCFG77_FNCSEL77_MSPI2_3       = 0,     /*!< MSPI2_3 : MSPI Master 2 Interface Signal                                  */
59976   GPIO_PINCFG77_FNCSEL77_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
59977   GPIO_PINCFG77_FNCSEL77_DISP_QSPI_D3  = 2,     /*!< DISP_QSPI_D3 : Display SPI Data3                                          */
59978   GPIO_PINCFG77_FNCSEL77_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
59979   GPIO_PINCFG77_FNCSEL77_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
59980   GPIO_PINCFG77_FNCSEL77_DISP_D13      = 5,     /*!< DISP_D13 : Display Data 13                                                */
59981   GPIO_PINCFG77_FNCSEL77_CT77          = 6,     /*!< CT77 : Timer/Counter input or output; Selection of direction
59982                                                      is done via CTIMER register settings.                                     */
59983   GPIO_PINCFG77_FNCSEL77_NCE77         = 7,     /*!< NCE77 : IOMSTR/MSPI N Chip Select. Polarity is determined by
59984                                                      CE_POLARITY field                                                         */
59985   GPIO_PINCFG77_FNCSEL77_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
59986   GPIO_PINCFG77_FNCSEL77_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
59987   GPIO_PINCFG77_FNCSEL77_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
59988   GPIO_PINCFG77_FNCSEL77_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
59989   GPIO_PINCFG77_FNCSEL77_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
59990   GPIO_PINCFG77_FNCSEL77_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
59991   GPIO_PINCFG77_FNCSEL77_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
59992   GPIO_PINCFG77_FNCSEL77_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
59993 } GPIO_PINCFG77_FNCSEL77_Enum;
59994 
59995 /* =======================================================  PINCFG78  ======================================================== */
59996 /* ============================================  GPIO PINCFG78 NCEPOL78 [22..22]  ============================================ */
59997 typedef enum {                                  /*!< GPIO_PINCFG78_NCEPOL78                                                    */
59998   GPIO_PINCFG78_NCEPOL78_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
59999   GPIO_PINCFG78_NCEPOL78_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60000 } GPIO_PINCFG78_NCEPOL78_Enum;
60001 
60002 /* ============================================  GPIO PINCFG78 NCESRC78 [16..21]  ============================================ */
60003 typedef enum {                                  /*!< GPIO_PINCFG78_NCESRC78                                                    */
60004   GPIO_PINCFG78_NCESRC78_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60005   GPIO_PINCFG78_NCESRC78_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60006   GPIO_PINCFG78_NCESRC78_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60007   GPIO_PINCFG78_NCESRC78_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60008   GPIO_PINCFG78_NCESRC78_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60009   GPIO_PINCFG78_NCESRC78_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60010   GPIO_PINCFG78_NCESRC78_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60011   GPIO_PINCFG78_NCESRC78_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60012   GPIO_PINCFG78_NCESRC78_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60013   GPIO_PINCFG78_NCESRC78_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60014   GPIO_PINCFG78_NCESRC78_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60015   GPIO_PINCFG78_NCESRC78_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60016   GPIO_PINCFG78_NCESRC78_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60017   GPIO_PINCFG78_NCESRC78_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60018   GPIO_PINCFG78_NCESRC78_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60019   GPIO_PINCFG78_NCESRC78_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60020   GPIO_PINCFG78_NCESRC78_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60021   GPIO_PINCFG78_NCESRC78_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60022   GPIO_PINCFG78_NCESRC78_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60023   GPIO_PINCFG78_NCESRC78_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60024   GPIO_PINCFG78_NCESRC78_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60025   GPIO_PINCFG78_NCESRC78_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60026   GPIO_PINCFG78_NCESRC78_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60027   GPIO_PINCFG78_NCESRC78_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60028   GPIO_PINCFG78_NCESRC78_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60029   GPIO_PINCFG78_NCESRC78_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60030   GPIO_PINCFG78_NCESRC78_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60031   GPIO_PINCFG78_NCESRC78_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60032   GPIO_PINCFG78_NCESRC78_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60033   GPIO_PINCFG78_NCESRC78_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60034   GPIO_PINCFG78_NCESRC78_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60035   GPIO_PINCFG78_NCESRC78_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60036   GPIO_PINCFG78_NCESRC78_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60037   GPIO_PINCFG78_NCESRC78_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60038   GPIO_PINCFG78_NCESRC78_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60039   GPIO_PINCFG78_NCESRC78_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60040   GPIO_PINCFG78_NCESRC78_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60041   GPIO_PINCFG78_NCESRC78_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60042   GPIO_PINCFG78_NCESRC78_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60043   GPIO_PINCFG78_NCESRC78_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60044   GPIO_PINCFG78_NCESRC78_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60045   GPIO_PINCFG78_NCESRC78_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60046   GPIO_PINCFG78_NCESRC78_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60047 } GPIO_PINCFG78_NCESRC78_Enum;
60048 
60049 /* ===========================================  GPIO PINCFG78 PULLCFG78 [13..15]  ============================================ */
60050 typedef enum {                                  /*!< GPIO_PINCFG78_PULLCFG78                                                   */
60051   GPIO_PINCFG78_PULLCFG78_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60052   GPIO_PINCFG78_PULLCFG78_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60053   GPIO_PINCFG78_PULLCFG78_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60054   GPIO_PINCFG78_PULLCFG78_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60055   GPIO_PINCFG78_PULLCFG78_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60056   GPIO_PINCFG78_PULLCFG78_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60057   GPIO_PINCFG78_PULLCFG78_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60058   GPIO_PINCFG78_PULLCFG78_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60059 } GPIO_PINCFG78_PULLCFG78_Enum;
60060 
60061 /* ==============================================  GPIO PINCFG78 DS78 [10..11]  ============================================== */
60062 typedef enum {                                  /*!< GPIO_PINCFG78_DS78                                                        */
60063   GPIO_PINCFG78_DS78_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60064   GPIO_PINCFG78_DS78_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60065   GPIO_PINCFG78_DS78_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60066   GPIO_PINCFG78_DS78_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60067 } GPIO_PINCFG78_DS78_Enum;
60068 
60069 /* =============================================  GPIO PINCFG78 OUTCFG78 [8..9]  ============================================= */
60070 typedef enum {                                  /*!< GPIO_PINCFG78_OUTCFG78                                                    */
60071   GPIO_PINCFG78_OUTCFG78_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60072   GPIO_PINCFG78_OUTCFG78_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60073                                                      and 1 values on pin.                                                      */
60074   GPIO_PINCFG78_OUTCFG78_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60075                                                      low, tristate otherwise.                                                  */
60076   GPIO_PINCFG78_OUTCFG78_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60077                                                      drive 0, 1 of HiZ on pin.                                                 */
60078 } GPIO_PINCFG78_OUTCFG78_Enum;
60079 
60080 /* =============================================  GPIO PINCFG78 IRPTEN78 [6..7]  ============================================= */
60081 typedef enum {                                  /*!< GPIO_PINCFG78_IRPTEN78                                                    */
60082   GPIO_PINCFG78_IRPTEN78_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60083   GPIO_PINCFG78_IRPTEN78_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60084                                                      on this GPIO                                                              */
60085   GPIO_PINCFG78_IRPTEN78_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60086                                                      on this GPIO                                                              */
60087   GPIO_PINCFG78_IRPTEN78_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60088                                                      GPIO                                                                      */
60089 } GPIO_PINCFG78_IRPTEN78_Enum;
60090 
60091 /* =============================================  GPIO PINCFG78 FNCSEL78 [0..3]  ============================================= */
60092 typedef enum {                                  /*!< GPIO_PINCFG78_FNCSEL78                                                    */
60093   GPIO_PINCFG78_FNCSEL78_MSPI2_4       = 0,     /*!< MSPI2_4 : MSPI Master 2 Interface Signal                                  */
60094   GPIO_PINCFG78_FNCSEL78_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60095   GPIO_PINCFG78_FNCSEL78_DISP_QSPI_SCK = 2,     /*!< DISP_QSPI_SCK : Display SPI CLK                                           */
60096   GPIO_PINCFG78_FNCSEL78_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60097   GPIO_PINCFG78_FNCSEL78_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
60098   GPIO_PINCFG78_FNCSEL78_DISP_D14      = 5,     /*!< DISP_D14 : Display Data 14                                                */
60099   GPIO_PINCFG78_FNCSEL78_CT78          = 6,     /*!< CT78 : Timer/Counter input or output; Selection of direction
60100                                                      is done via CTIMER register settings.                                     */
60101   GPIO_PINCFG78_FNCSEL78_NCE78         = 7,     /*!< NCE78 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60102                                                      CE_POLARITY field                                                         */
60103   GPIO_PINCFG78_FNCSEL78_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
60104   GPIO_PINCFG78_FNCSEL78_DISP_SPI_SCK  = 9,     /*!< DISP_SPI_SCK : Display SPI Clock                                          */
60105   GPIO_PINCFG78_FNCSEL78_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60106   GPIO_PINCFG78_FNCSEL78_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60107   GPIO_PINCFG78_FNCSEL78_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60108   GPIO_PINCFG78_FNCSEL78_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60109   GPIO_PINCFG78_FNCSEL78_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60110   GPIO_PINCFG78_FNCSEL78_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60111 } GPIO_PINCFG78_FNCSEL78_Enum;
60112 
60113 /* =======================================================  PINCFG79  ======================================================== */
60114 /* ============================================  GPIO PINCFG79 NCEPOL79 [22..22]  ============================================ */
60115 typedef enum {                                  /*!< GPIO_PINCFG79_NCEPOL79                                                    */
60116   GPIO_PINCFG79_NCEPOL79_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60117   GPIO_PINCFG79_NCEPOL79_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60118 } GPIO_PINCFG79_NCEPOL79_Enum;
60119 
60120 /* ============================================  GPIO PINCFG79 NCESRC79 [16..21]  ============================================ */
60121 typedef enum {                                  /*!< GPIO_PINCFG79_NCESRC79                                                    */
60122   GPIO_PINCFG79_NCESRC79_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60123   GPIO_PINCFG79_NCESRC79_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60124   GPIO_PINCFG79_NCESRC79_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60125   GPIO_PINCFG79_NCESRC79_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60126   GPIO_PINCFG79_NCESRC79_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60127   GPIO_PINCFG79_NCESRC79_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60128   GPIO_PINCFG79_NCESRC79_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60129   GPIO_PINCFG79_NCESRC79_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60130   GPIO_PINCFG79_NCESRC79_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60131   GPIO_PINCFG79_NCESRC79_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60132   GPIO_PINCFG79_NCESRC79_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60133   GPIO_PINCFG79_NCESRC79_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60134   GPIO_PINCFG79_NCESRC79_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60135   GPIO_PINCFG79_NCESRC79_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60136   GPIO_PINCFG79_NCESRC79_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60137   GPIO_PINCFG79_NCESRC79_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60138   GPIO_PINCFG79_NCESRC79_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60139   GPIO_PINCFG79_NCESRC79_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60140   GPIO_PINCFG79_NCESRC79_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60141   GPIO_PINCFG79_NCESRC79_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60142   GPIO_PINCFG79_NCESRC79_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60143   GPIO_PINCFG79_NCESRC79_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60144   GPIO_PINCFG79_NCESRC79_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60145   GPIO_PINCFG79_NCESRC79_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60146   GPIO_PINCFG79_NCESRC79_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60147   GPIO_PINCFG79_NCESRC79_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60148   GPIO_PINCFG79_NCESRC79_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60149   GPIO_PINCFG79_NCESRC79_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60150   GPIO_PINCFG79_NCESRC79_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60151   GPIO_PINCFG79_NCESRC79_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60152   GPIO_PINCFG79_NCESRC79_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60153   GPIO_PINCFG79_NCESRC79_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60154   GPIO_PINCFG79_NCESRC79_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60155   GPIO_PINCFG79_NCESRC79_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60156   GPIO_PINCFG79_NCESRC79_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60157   GPIO_PINCFG79_NCESRC79_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60158   GPIO_PINCFG79_NCESRC79_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60159   GPIO_PINCFG79_NCESRC79_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60160   GPIO_PINCFG79_NCESRC79_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60161   GPIO_PINCFG79_NCESRC79_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60162   GPIO_PINCFG79_NCESRC79_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60163   GPIO_PINCFG79_NCESRC79_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60164   GPIO_PINCFG79_NCESRC79_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60165 } GPIO_PINCFG79_NCESRC79_Enum;
60166 
60167 /* ===========================================  GPIO PINCFG79 PULLCFG79 [13..15]  ============================================ */
60168 typedef enum {                                  /*!< GPIO_PINCFG79_PULLCFG79                                                   */
60169   GPIO_PINCFG79_PULLCFG79_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60170   GPIO_PINCFG79_PULLCFG79_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60171   GPIO_PINCFG79_PULLCFG79_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60172   GPIO_PINCFG79_PULLCFG79_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60173   GPIO_PINCFG79_PULLCFG79_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60174   GPIO_PINCFG79_PULLCFG79_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60175   GPIO_PINCFG79_PULLCFG79_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60176   GPIO_PINCFG79_PULLCFG79_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60177 } GPIO_PINCFG79_PULLCFG79_Enum;
60178 
60179 /* ==============================================  GPIO PINCFG79 DS79 [10..11]  ============================================== */
60180 typedef enum {                                  /*!< GPIO_PINCFG79_DS79                                                        */
60181   GPIO_PINCFG79_DS79_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60182   GPIO_PINCFG79_DS79_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60183   GPIO_PINCFG79_DS79_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60184   GPIO_PINCFG79_DS79_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60185 } GPIO_PINCFG79_DS79_Enum;
60186 
60187 /* =============================================  GPIO PINCFG79 OUTCFG79 [8..9]  ============================================= */
60188 typedef enum {                                  /*!< GPIO_PINCFG79_OUTCFG79                                                    */
60189   GPIO_PINCFG79_OUTCFG79_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60190   GPIO_PINCFG79_OUTCFG79_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60191                                                      and 1 values on pin.                                                      */
60192   GPIO_PINCFG79_OUTCFG79_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60193                                                      low, tristate otherwise.                                                  */
60194   GPIO_PINCFG79_OUTCFG79_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60195                                                      drive 0, 1 of HiZ on pin.                                                 */
60196 } GPIO_PINCFG79_OUTCFG79_Enum;
60197 
60198 /* =============================================  GPIO PINCFG79 IRPTEN79 [6..7]  ============================================= */
60199 typedef enum {                                  /*!< GPIO_PINCFG79_IRPTEN79                                                    */
60200   GPIO_PINCFG79_IRPTEN79_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60201   GPIO_PINCFG79_IRPTEN79_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60202                                                      on this GPIO                                                              */
60203   GPIO_PINCFG79_IRPTEN79_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60204                                                      on this GPIO                                                              */
60205   GPIO_PINCFG79_IRPTEN79_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60206                                                      GPIO                                                                      */
60207 } GPIO_PINCFG79_IRPTEN79_Enum;
60208 
60209 /* =============================================  GPIO PINCFG79 FNCSEL79 [0..3]  ============================================= */
60210 typedef enum {                                  /*!< GPIO_PINCFG79_FNCSEL79                                                    */
60211   GPIO_PINCFG79_FNCSEL79_MSPI2_5       = 0,     /*!< MSPI2_5 : MSPI Master 2 Interface Signal                                  */
60212   GPIO_PINCFG79_FNCSEL79_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60213   GPIO_PINCFG79_FNCSEL79_SDIF_DAT4     = 2,     /*!< SDIF_DAT4 : SD/SDIO/MMC Data4 pin                                         */
60214   GPIO_PINCFG79_FNCSEL79_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60215   GPIO_PINCFG79_FNCSEL79_SWO           = 4,     /*!< SWO : Serial Wire Output                                                  */
60216   GPIO_PINCFG79_FNCSEL79_DISP_VS       = 5,     /*!< DISP_VS : Display RGB VSYNC                                               */
60217   GPIO_PINCFG79_FNCSEL79_CT79          = 6,     /*!< CT79 : Timer/Counter input or output; Selection of direction
60218                                                      is done via CTIMER register settings.                                     */
60219   GPIO_PINCFG79_FNCSEL79_NCE79         = 7,     /*!< NCE79 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60220                                                      CE_POLARITY field                                                         */
60221   GPIO_PINCFG79_FNCSEL79_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
60222   GPIO_PINCFG79_FNCSEL79_DISP_SPI_SDI  = 9,     /*!< DISP_SPI_SDI : Display SPI Data IN                                        */
60223   GPIO_PINCFG79_FNCSEL79_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60224   GPIO_PINCFG79_FNCSEL79_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60225   GPIO_PINCFG79_FNCSEL79_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60226   GPIO_PINCFG79_FNCSEL79_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60227   GPIO_PINCFG79_FNCSEL79_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60228   GPIO_PINCFG79_FNCSEL79_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60229 } GPIO_PINCFG79_FNCSEL79_Enum;
60230 
60231 /* =======================================================  PINCFG80  ======================================================== */
60232 /* ============================================  GPIO PINCFG80 NCEPOL80 [22..22]  ============================================ */
60233 typedef enum {                                  /*!< GPIO_PINCFG80_NCEPOL80                                                    */
60234   GPIO_PINCFG80_NCEPOL80_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60235   GPIO_PINCFG80_NCEPOL80_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60236 } GPIO_PINCFG80_NCEPOL80_Enum;
60237 
60238 /* ============================================  GPIO PINCFG80 NCESRC80 [16..21]  ============================================ */
60239 typedef enum {                                  /*!< GPIO_PINCFG80_NCESRC80                                                    */
60240   GPIO_PINCFG80_NCESRC80_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60241   GPIO_PINCFG80_NCESRC80_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60242   GPIO_PINCFG80_NCESRC80_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60243   GPIO_PINCFG80_NCESRC80_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60244   GPIO_PINCFG80_NCESRC80_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60245   GPIO_PINCFG80_NCESRC80_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60246   GPIO_PINCFG80_NCESRC80_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60247   GPIO_PINCFG80_NCESRC80_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60248   GPIO_PINCFG80_NCESRC80_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60249   GPIO_PINCFG80_NCESRC80_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60250   GPIO_PINCFG80_NCESRC80_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60251   GPIO_PINCFG80_NCESRC80_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60252   GPIO_PINCFG80_NCESRC80_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60253   GPIO_PINCFG80_NCESRC80_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60254   GPIO_PINCFG80_NCESRC80_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60255   GPIO_PINCFG80_NCESRC80_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60256   GPIO_PINCFG80_NCESRC80_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60257   GPIO_PINCFG80_NCESRC80_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60258   GPIO_PINCFG80_NCESRC80_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60259   GPIO_PINCFG80_NCESRC80_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60260   GPIO_PINCFG80_NCESRC80_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60261   GPIO_PINCFG80_NCESRC80_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60262   GPIO_PINCFG80_NCESRC80_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60263   GPIO_PINCFG80_NCESRC80_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60264   GPIO_PINCFG80_NCESRC80_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60265   GPIO_PINCFG80_NCESRC80_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60266   GPIO_PINCFG80_NCESRC80_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60267   GPIO_PINCFG80_NCESRC80_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60268   GPIO_PINCFG80_NCESRC80_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60269   GPIO_PINCFG80_NCESRC80_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60270   GPIO_PINCFG80_NCESRC80_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60271   GPIO_PINCFG80_NCESRC80_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60272   GPIO_PINCFG80_NCESRC80_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60273   GPIO_PINCFG80_NCESRC80_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60274   GPIO_PINCFG80_NCESRC80_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60275   GPIO_PINCFG80_NCESRC80_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60276   GPIO_PINCFG80_NCESRC80_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60277   GPIO_PINCFG80_NCESRC80_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60278   GPIO_PINCFG80_NCESRC80_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60279   GPIO_PINCFG80_NCESRC80_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60280   GPIO_PINCFG80_NCESRC80_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60281   GPIO_PINCFG80_NCESRC80_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60282   GPIO_PINCFG80_NCESRC80_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60283 } GPIO_PINCFG80_NCESRC80_Enum;
60284 
60285 /* ===========================================  GPIO PINCFG80 PULLCFG80 [13..15]  ============================================ */
60286 typedef enum {                                  /*!< GPIO_PINCFG80_PULLCFG80                                                   */
60287   GPIO_PINCFG80_PULLCFG80_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60288   GPIO_PINCFG80_PULLCFG80_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60289   GPIO_PINCFG80_PULLCFG80_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60290   GPIO_PINCFG80_PULLCFG80_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60291   GPIO_PINCFG80_PULLCFG80_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60292   GPIO_PINCFG80_PULLCFG80_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60293   GPIO_PINCFG80_PULLCFG80_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60294   GPIO_PINCFG80_PULLCFG80_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60295 } GPIO_PINCFG80_PULLCFG80_Enum;
60296 
60297 /* ==============================================  GPIO PINCFG80 DS80 [10..11]  ============================================== */
60298 typedef enum {                                  /*!< GPIO_PINCFG80_DS80                                                        */
60299   GPIO_PINCFG80_DS80_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60300   GPIO_PINCFG80_DS80_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60301   GPIO_PINCFG80_DS80_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60302   GPIO_PINCFG80_DS80_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60303 } GPIO_PINCFG80_DS80_Enum;
60304 
60305 /* =============================================  GPIO PINCFG80 OUTCFG80 [8..9]  ============================================= */
60306 typedef enum {                                  /*!< GPIO_PINCFG80_OUTCFG80                                                    */
60307   GPIO_PINCFG80_OUTCFG80_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60308   GPIO_PINCFG80_OUTCFG80_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60309                                                      and 1 values on pin.                                                      */
60310   GPIO_PINCFG80_OUTCFG80_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60311                                                      low, tristate otherwise.                                                  */
60312   GPIO_PINCFG80_OUTCFG80_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60313                                                      drive 0, 1 of HiZ on pin.                                                 */
60314 } GPIO_PINCFG80_OUTCFG80_Enum;
60315 
60316 /* =============================================  GPIO PINCFG80 IRPTEN80 [6..7]  ============================================= */
60317 typedef enum {                                  /*!< GPIO_PINCFG80_IRPTEN80                                                    */
60318   GPIO_PINCFG80_IRPTEN80_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60319   GPIO_PINCFG80_IRPTEN80_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60320                                                      on this GPIO                                                              */
60321   GPIO_PINCFG80_IRPTEN80_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60322                                                      on this GPIO                                                              */
60323   GPIO_PINCFG80_IRPTEN80_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60324                                                      GPIO                                                                      */
60325 } GPIO_PINCFG80_IRPTEN80_Enum;
60326 
60327 /* =============================================  GPIO PINCFG80 FNCSEL80 [0..3]  ============================================= */
60328 typedef enum {                                  /*!< GPIO_PINCFG80_FNCSEL80                                                    */
60329   GPIO_PINCFG80_FNCSEL80_MSPI2_6       = 0,     /*!< MSPI2_6 : MSPI Master 2 Interface Signal                                  */
60330   GPIO_PINCFG80_FNCSEL80_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
60331   GPIO_PINCFG80_FNCSEL80_SDIF_DAT5     = 2,     /*!< SDIF_DAT5 : SD/SDIO/MMC Data5 pin                                         */
60332   GPIO_PINCFG80_FNCSEL80_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60333   GPIO_PINCFG80_FNCSEL80_SWTRACE0      = 4,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
60334   GPIO_PINCFG80_FNCSEL80_DISP_HS       = 5,     /*!< DISP_HS : Display RGB HSYNC                                               */
60335   GPIO_PINCFG80_FNCSEL80_CT80          = 6,     /*!< CT80 : Timer/Counter input or output; Selection of direction
60336                                                      is done via CTIMER register settings.                                     */
60337   GPIO_PINCFG80_FNCSEL80_NCE80         = 7,     /*!< NCE80 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60338                                                      CE_POLARITY field                                                         */
60339   GPIO_PINCFG80_FNCSEL80_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
60340   GPIO_PINCFG80_FNCSEL80_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
60341   GPIO_PINCFG80_FNCSEL80_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60342   GPIO_PINCFG80_FNCSEL80_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60343   GPIO_PINCFG80_FNCSEL80_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60344   GPIO_PINCFG80_FNCSEL80_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60345   GPIO_PINCFG80_FNCSEL80_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60346   GPIO_PINCFG80_FNCSEL80_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60347 } GPIO_PINCFG80_FNCSEL80_Enum;
60348 
60349 /* =======================================================  PINCFG81  ======================================================== */
60350 /* ============================================  GPIO PINCFG81 NCEPOL81 [22..22]  ============================================ */
60351 typedef enum {                                  /*!< GPIO_PINCFG81_NCEPOL81                                                    */
60352   GPIO_PINCFG81_NCEPOL81_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60353   GPIO_PINCFG81_NCEPOL81_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60354 } GPIO_PINCFG81_NCEPOL81_Enum;
60355 
60356 /* ============================================  GPIO PINCFG81 NCESRC81 [16..21]  ============================================ */
60357 typedef enum {                                  /*!< GPIO_PINCFG81_NCESRC81                                                    */
60358   GPIO_PINCFG81_NCESRC81_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60359   GPIO_PINCFG81_NCESRC81_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60360   GPIO_PINCFG81_NCESRC81_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60361   GPIO_PINCFG81_NCESRC81_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60362   GPIO_PINCFG81_NCESRC81_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60363   GPIO_PINCFG81_NCESRC81_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60364   GPIO_PINCFG81_NCESRC81_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60365   GPIO_PINCFG81_NCESRC81_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60366   GPIO_PINCFG81_NCESRC81_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60367   GPIO_PINCFG81_NCESRC81_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60368   GPIO_PINCFG81_NCESRC81_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60369   GPIO_PINCFG81_NCESRC81_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60370   GPIO_PINCFG81_NCESRC81_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60371   GPIO_PINCFG81_NCESRC81_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60372   GPIO_PINCFG81_NCESRC81_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60373   GPIO_PINCFG81_NCESRC81_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60374   GPIO_PINCFG81_NCESRC81_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60375   GPIO_PINCFG81_NCESRC81_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60376   GPIO_PINCFG81_NCESRC81_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60377   GPIO_PINCFG81_NCESRC81_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60378   GPIO_PINCFG81_NCESRC81_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60379   GPIO_PINCFG81_NCESRC81_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60380   GPIO_PINCFG81_NCESRC81_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60381   GPIO_PINCFG81_NCESRC81_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60382   GPIO_PINCFG81_NCESRC81_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60383   GPIO_PINCFG81_NCESRC81_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60384   GPIO_PINCFG81_NCESRC81_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60385   GPIO_PINCFG81_NCESRC81_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60386   GPIO_PINCFG81_NCESRC81_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60387   GPIO_PINCFG81_NCESRC81_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60388   GPIO_PINCFG81_NCESRC81_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60389   GPIO_PINCFG81_NCESRC81_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60390   GPIO_PINCFG81_NCESRC81_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60391   GPIO_PINCFG81_NCESRC81_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60392   GPIO_PINCFG81_NCESRC81_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60393   GPIO_PINCFG81_NCESRC81_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60394   GPIO_PINCFG81_NCESRC81_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60395   GPIO_PINCFG81_NCESRC81_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60396   GPIO_PINCFG81_NCESRC81_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60397   GPIO_PINCFG81_NCESRC81_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60398   GPIO_PINCFG81_NCESRC81_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60399   GPIO_PINCFG81_NCESRC81_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60400   GPIO_PINCFG81_NCESRC81_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60401 } GPIO_PINCFG81_NCESRC81_Enum;
60402 
60403 /* ===========================================  GPIO PINCFG81 PULLCFG81 [13..15]  ============================================ */
60404 typedef enum {                                  /*!< GPIO_PINCFG81_PULLCFG81                                                   */
60405   GPIO_PINCFG81_PULLCFG81_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60406   GPIO_PINCFG81_PULLCFG81_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60407   GPIO_PINCFG81_PULLCFG81_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60408   GPIO_PINCFG81_PULLCFG81_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60409   GPIO_PINCFG81_PULLCFG81_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60410   GPIO_PINCFG81_PULLCFG81_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60411   GPIO_PINCFG81_PULLCFG81_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60412   GPIO_PINCFG81_PULLCFG81_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60413 } GPIO_PINCFG81_PULLCFG81_Enum;
60414 
60415 /* ==============================================  GPIO PINCFG81 DS81 [10..11]  ============================================== */
60416 typedef enum {                                  /*!< GPIO_PINCFG81_DS81                                                        */
60417   GPIO_PINCFG81_DS81_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60418   GPIO_PINCFG81_DS81_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60419   GPIO_PINCFG81_DS81_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60420   GPIO_PINCFG81_DS81_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60421 } GPIO_PINCFG81_DS81_Enum;
60422 
60423 /* =============================================  GPIO PINCFG81 OUTCFG81 [8..9]  ============================================= */
60424 typedef enum {                                  /*!< GPIO_PINCFG81_OUTCFG81                                                    */
60425   GPIO_PINCFG81_OUTCFG81_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60426   GPIO_PINCFG81_OUTCFG81_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60427                                                      and 1 values on pin.                                                      */
60428   GPIO_PINCFG81_OUTCFG81_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60429                                                      low, tristate otherwise.                                                  */
60430   GPIO_PINCFG81_OUTCFG81_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60431                                                      drive 0, 1 of HiZ on pin.                                                 */
60432 } GPIO_PINCFG81_OUTCFG81_Enum;
60433 
60434 /* =============================================  GPIO PINCFG81 IRPTEN81 [6..7]  ============================================= */
60435 typedef enum {                                  /*!< GPIO_PINCFG81_IRPTEN81                                                    */
60436   GPIO_PINCFG81_IRPTEN81_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60437   GPIO_PINCFG81_IRPTEN81_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60438                                                      on this GPIO                                                              */
60439   GPIO_PINCFG81_IRPTEN81_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60440                                                      on this GPIO                                                              */
60441   GPIO_PINCFG81_IRPTEN81_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60442                                                      GPIO                                                                      */
60443 } GPIO_PINCFG81_IRPTEN81_Enum;
60444 
60445 /* =============================================  GPIO PINCFG81 FNCSEL81 [0..3]  ============================================= */
60446 typedef enum {                                  /*!< GPIO_PINCFG81_FNCSEL81                                                    */
60447   GPIO_PINCFG81_FNCSEL81_MSPI2_7       = 0,     /*!< MSPI2_7 : MSPI Master 2 Interface Signal                                  */
60448   GPIO_PINCFG81_FNCSEL81_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
60449   GPIO_PINCFG81_FNCSEL81_SDIF_DAT6     = 2,     /*!< SDIF_DAT6 : SD/SDIO/MMC Data6 pin                                         */
60450   GPIO_PINCFG81_FNCSEL81_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60451   GPIO_PINCFG81_FNCSEL81_SWTRACE1      = 4,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
60452   GPIO_PINCFG81_FNCSEL81_DISP_DE       = 5,     /*!< DISP_DE : Display RGB Data Enable                                         */
60453   GPIO_PINCFG81_FNCSEL81_CT81          = 6,     /*!< CT81 : Timer/Counter input or output; Selection of direction
60454                                                      is done via CTIMER register settings.                                     */
60455   GPIO_PINCFG81_FNCSEL81_NCE81         = 7,     /*!< NCE81 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60456                                                      CE_POLARITY field                                                         */
60457   GPIO_PINCFG81_FNCSEL81_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
60458   GPIO_PINCFG81_FNCSEL81_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
60459   GPIO_PINCFG81_FNCSEL81_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60460   GPIO_PINCFG81_FNCSEL81_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60461   GPIO_PINCFG81_FNCSEL81_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60462   GPIO_PINCFG81_FNCSEL81_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60463   GPIO_PINCFG81_FNCSEL81_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60464   GPIO_PINCFG81_FNCSEL81_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60465 } GPIO_PINCFG81_FNCSEL81_Enum;
60466 
60467 /* =======================================================  PINCFG82  ======================================================== */
60468 /* ============================================  GPIO PINCFG82 NCEPOL82 [22..22]  ============================================ */
60469 typedef enum {                                  /*!< GPIO_PINCFG82_NCEPOL82                                                    */
60470   GPIO_PINCFG82_NCEPOL82_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60471   GPIO_PINCFG82_NCEPOL82_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60472 } GPIO_PINCFG82_NCEPOL82_Enum;
60473 
60474 /* ============================================  GPIO PINCFG82 NCESRC82 [16..21]  ============================================ */
60475 typedef enum {                                  /*!< GPIO_PINCFG82_NCESRC82                                                    */
60476   GPIO_PINCFG82_NCESRC82_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60477   GPIO_PINCFG82_NCESRC82_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60478   GPIO_PINCFG82_NCESRC82_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60479   GPIO_PINCFG82_NCESRC82_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60480   GPIO_PINCFG82_NCESRC82_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60481   GPIO_PINCFG82_NCESRC82_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60482   GPIO_PINCFG82_NCESRC82_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60483   GPIO_PINCFG82_NCESRC82_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60484   GPIO_PINCFG82_NCESRC82_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60485   GPIO_PINCFG82_NCESRC82_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60486   GPIO_PINCFG82_NCESRC82_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60487   GPIO_PINCFG82_NCESRC82_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60488   GPIO_PINCFG82_NCESRC82_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60489   GPIO_PINCFG82_NCESRC82_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60490   GPIO_PINCFG82_NCESRC82_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60491   GPIO_PINCFG82_NCESRC82_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60492   GPIO_PINCFG82_NCESRC82_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60493   GPIO_PINCFG82_NCESRC82_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60494   GPIO_PINCFG82_NCESRC82_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60495   GPIO_PINCFG82_NCESRC82_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60496   GPIO_PINCFG82_NCESRC82_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60497   GPIO_PINCFG82_NCESRC82_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60498   GPIO_PINCFG82_NCESRC82_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60499   GPIO_PINCFG82_NCESRC82_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60500   GPIO_PINCFG82_NCESRC82_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60501   GPIO_PINCFG82_NCESRC82_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60502   GPIO_PINCFG82_NCESRC82_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60503   GPIO_PINCFG82_NCESRC82_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60504   GPIO_PINCFG82_NCESRC82_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60505   GPIO_PINCFG82_NCESRC82_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60506   GPIO_PINCFG82_NCESRC82_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60507   GPIO_PINCFG82_NCESRC82_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60508   GPIO_PINCFG82_NCESRC82_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60509   GPIO_PINCFG82_NCESRC82_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60510   GPIO_PINCFG82_NCESRC82_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60511   GPIO_PINCFG82_NCESRC82_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60512   GPIO_PINCFG82_NCESRC82_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60513   GPIO_PINCFG82_NCESRC82_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60514   GPIO_PINCFG82_NCESRC82_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60515   GPIO_PINCFG82_NCESRC82_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60516   GPIO_PINCFG82_NCESRC82_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60517   GPIO_PINCFG82_NCESRC82_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60518   GPIO_PINCFG82_NCESRC82_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60519 } GPIO_PINCFG82_NCESRC82_Enum;
60520 
60521 /* ===========================================  GPIO PINCFG82 PULLCFG82 [13..15]  ============================================ */
60522 typedef enum {                                  /*!< GPIO_PINCFG82_PULLCFG82                                                   */
60523   GPIO_PINCFG82_PULLCFG82_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60524   GPIO_PINCFG82_PULLCFG82_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60525   GPIO_PINCFG82_PULLCFG82_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60526   GPIO_PINCFG82_PULLCFG82_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60527   GPIO_PINCFG82_PULLCFG82_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60528   GPIO_PINCFG82_PULLCFG82_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60529   GPIO_PINCFG82_PULLCFG82_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60530   GPIO_PINCFG82_PULLCFG82_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60531 } GPIO_PINCFG82_PULLCFG82_Enum;
60532 
60533 /* ==============================================  GPIO PINCFG82 DS82 [10..11]  ============================================== */
60534 typedef enum {                                  /*!< GPIO_PINCFG82_DS82                                                        */
60535   GPIO_PINCFG82_DS82_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60536   GPIO_PINCFG82_DS82_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60537   GPIO_PINCFG82_DS82_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60538   GPIO_PINCFG82_DS82_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60539 } GPIO_PINCFG82_DS82_Enum;
60540 
60541 /* =============================================  GPIO PINCFG82 OUTCFG82 [8..9]  ============================================= */
60542 typedef enum {                                  /*!< GPIO_PINCFG82_OUTCFG82                                                    */
60543   GPIO_PINCFG82_OUTCFG82_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60544   GPIO_PINCFG82_OUTCFG82_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60545                                                      and 1 values on pin.                                                      */
60546   GPIO_PINCFG82_OUTCFG82_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60547                                                      low, tristate otherwise.                                                  */
60548   GPIO_PINCFG82_OUTCFG82_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60549                                                      drive 0, 1 of HiZ on pin.                                                 */
60550 } GPIO_PINCFG82_OUTCFG82_Enum;
60551 
60552 /* =============================================  GPIO PINCFG82 IRPTEN82 [6..7]  ============================================= */
60553 typedef enum {                                  /*!< GPIO_PINCFG82_IRPTEN82                                                    */
60554   GPIO_PINCFG82_IRPTEN82_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60555   GPIO_PINCFG82_IRPTEN82_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60556                                                      on this GPIO                                                              */
60557   GPIO_PINCFG82_IRPTEN82_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60558                                                      on this GPIO                                                              */
60559   GPIO_PINCFG82_IRPTEN82_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60560                                                      GPIO                                                                      */
60561 } GPIO_PINCFG82_IRPTEN82_Enum;
60562 
60563 /* =============================================  GPIO PINCFG82 FNCSEL82 [0..3]  ============================================= */
60564 typedef enum {                                  /*!< GPIO_PINCFG82_FNCSEL82                                                    */
60565   GPIO_PINCFG82_FNCSEL82_MSPI2_8       = 0,     /*!< MSPI2_8 : MSPI Master 2 Interface Signal                                  */
60566   GPIO_PINCFG82_FNCSEL82_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
60567   GPIO_PINCFG82_FNCSEL82_SDIF_DAT7     = 2,     /*!< SDIF_DAT7 : SD/SDIO/MMC Data7 pin                                         */
60568   GPIO_PINCFG82_FNCSEL82_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60569   GPIO_PINCFG82_FNCSEL82_SWTRACE2      = 4,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
60570   GPIO_PINCFG82_FNCSEL82_DISP_PCLK     = 5,     /*!< DISP_PCLK : Display RGB Pixel Clock                                       */
60571   GPIO_PINCFG82_FNCSEL82_CT82          = 6,     /*!< CT82 : Timer/Counter input or output; Selection of direction
60572                                                      is done via CTIMER register settings.                                     */
60573   GPIO_PINCFG82_FNCSEL82_NCE82         = 7,     /*!< NCE82 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60574                                                      CE_POLARITY field                                                         */
60575   GPIO_PINCFG82_FNCSEL82_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
60576   GPIO_PINCFG82_FNCSEL82_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
60577   GPIO_PINCFG82_FNCSEL82_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60578   GPIO_PINCFG82_FNCSEL82_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60579   GPIO_PINCFG82_FNCSEL82_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60580   GPIO_PINCFG82_FNCSEL82_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60581   GPIO_PINCFG82_FNCSEL82_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60582   GPIO_PINCFG82_FNCSEL82_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60583 } GPIO_PINCFG82_FNCSEL82_Enum;
60584 
60585 /* =======================================================  PINCFG83  ======================================================== */
60586 /* ============================================  GPIO PINCFG83 NCEPOL83 [22..22]  ============================================ */
60587 typedef enum {                                  /*!< GPIO_PINCFG83_NCEPOL83                                                    */
60588   GPIO_PINCFG83_NCEPOL83_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60589   GPIO_PINCFG83_NCEPOL83_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60590 } GPIO_PINCFG83_NCEPOL83_Enum;
60591 
60592 /* ============================================  GPIO PINCFG83 NCESRC83 [16..21]  ============================================ */
60593 typedef enum {                                  /*!< GPIO_PINCFG83_NCESRC83                                                    */
60594   GPIO_PINCFG83_NCESRC83_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60595   GPIO_PINCFG83_NCESRC83_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60596   GPIO_PINCFG83_NCESRC83_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60597   GPIO_PINCFG83_NCESRC83_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60598   GPIO_PINCFG83_NCESRC83_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60599   GPIO_PINCFG83_NCESRC83_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60600   GPIO_PINCFG83_NCESRC83_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60601   GPIO_PINCFG83_NCESRC83_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60602   GPIO_PINCFG83_NCESRC83_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60603   GPIO_PINCFG83_NCESRC83_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60604   GPIO_PINCFG83_NCESRC83_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60605   GPIO_PINCFG83_NCESRC83_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60606   GPIO_PINCFG83_NCESRC83_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60607   GPIO_PINCFG83_NCESRC83_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60608   GPIO_PINCFG83_NCESRC83_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60609   GPIO_PINCFG83_NCESRC83_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60610   GPIO_PINCFG83_NCESRC83_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60611   GPIO_PINCFG83_NCESRC83_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60612   GPIO_PINCFG83_NCESRC83_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60613   GPIO_PINCFG83_NCESRC83_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60614   GPIO_PINCFG83_NCESRC83_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60615   GPIO_PINCFG83_NCESRC83_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60616   GPIO_PINCFG83_NCESRC83_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60617   GPIO_PINCFG83_NCESRC83_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60618   GPIO_PINCFG83_NCESRC83_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60619   GPIO_PINCFG83_NCESRC83_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60620   GPIO_PINCFG83_NCESRC83_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60621   GPIO_PINCFG83_NCESRC83_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60622   GPIO_PINCFG83_NCESRC83_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60623   GPIO_PINCFG83_NCESRC83_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60624   GPIO_PINCFG83_NCESRC83_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60625   GPIO_PINCFG83_NCESRC83_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60626   GPIO_PINCFG83_NCESRC83_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60627   GPIO_PINCFG83_NCESRC83_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60628   GPIO_PINCFG83_NCESRC83_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60629   GPIO_PINCFG83_NCESRC83_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60630   GPIO_PINCFG83_NCESRC83_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60631   GPIO_PINCFG83_NCESRC83_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60632   GPIO_PINCFG83_NCESRC83_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60633   GPIO_PINCFG83_NCESRC83_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60634   GPIO_PINCFG83_NCESRC83_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60635   GPIO_PINCFG83_NCESRC83_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60636   GPIO_PINCFG83_NCESRC83_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60637 } GPIO_PINCFG83_NCESRC83_Enum;
60638 
60639 /* ===========================================  GPIO PINCFG83 PULLCFG83 [13..15]  ============================================ */
60640 typedef enum {                                  /*!< GPIO_PINCFG83_PULLCFG83                                                   */
60641   GPIO_PINCFG83_PULLCFG83_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60642   GPIO_PINCFG83_PULLCFG83_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60643   GPIO_PINCFG83_PULLCFG83_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60644   GPIO_PINCFG83_PULLCFG83_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60645   GPIO_PINCFG83_PULLCFG83_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60646   GPIO_PINCFG83_PULLCFG83_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60647   GPIO_PINCFG83_PULLCFG83_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60648   GPIO_PINCFG83_PULLCFG83_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60649 } GPIO_PINCFG83_PULLCFG83_Enum;
60650 
60651 /* ==============================================  GPIO PINCFG83 DS83 [10..11]  ============================================== */
60652 typedef enum {                                  /*!< GPIO_PINCFG83_DS83                                                        */
60653   GPIO_PINCFG83_DS83_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60654   GPIO_PINCFG83_DS83_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60655   GPIO_PINCFG83_DS83_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60656   GPIO_PINCFG83_DS83_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60657 } GPIO_PINCFG83_DS83_Enum;
60658 
60659 /* =============================================  GPIO PINCFG83 OUTCFG83 [8..9]  ============================================= */
60660 typedef enum {                                  /*!< GPIO_PINCFG83_OUTCFG83                                                    */
60661   GPIO_PINCFG83_OUTCFG83_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60662   GPIO_PINCFG83_OUTCFG83_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60663                                                      and 1 values on pin.                                                      */
60664   GPIO_PINCFG83_OUTCFG83_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60665                                                      low, tristate otherwise.                                                  */
60666   GPIO_PINCFG83_OUTCFG83_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60667                                                      drive 0, 1 of HiZ on pin.                                                 */
60668 } GPIO_PINCFG83_OUTCFG83_Enum;
60669 
60670 /* =============================================  GPIO PINCFG83 IRPTEN83 [6..7]  ============================================= */
60671 typedef enum {                                  /*!< GPIO_PINCFG83_IRPTEN83                                                    */
60672   GPIO_PINCFG83_IRPTEN83_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60673   GPIO_PINCFG83_IRPTEN83_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60674                                                      on this GPIO                                                              */
60675   GPIO_PINCFG83_IRPTEN83_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60676                                                      on this GPIO                                                              */
60677   GPIO_PINCFG83_IRPTEN83_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60678                                                      GPIO                                                                      */
60679 } GPIO_PINCFG83_IRPTEN83_Enum;
60680 
60681 /* =============================================  GPIO PINCFG83 FNCSEL83 [0..3]  ============================================= */
60682 typedef enum {                                  /*!< GPIO_PINCFG83_FNCSEL83                                                    */
60683   GPIO_PINCFG83_FNCSEL83_MSPI2_9       = 0,     /*!< MSPI2_9 : MSPI Master 2 Interface Signal                                  */
60684   GPIO_PINCFG83_FNCSEL83_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
60685   GPIO_PINCFG83_FNCSEL83_SDIF_CMD      = 2,     /*!< SDIF_CMD : SD1/SD4/MMC Command pin                                        */
60686   GPIO_PINCFG83_FNCSEL83_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60687   GPIO_PINCFG83_FNCSEL83_SWTRACE3      = 4,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
60688   GPIO_PINCFG83_FNCSEL83_DISP_SD       = 5,     /*!< DISP_SD : Display RGB Shutdown                                            */
60689   GPIO_PINCFG83_FNCSEL83_CT83          = 6,     /*!< CT83 : Timer/Counter input or output; Selection of direction
60690                                                      is done via CTIMER register settings.                                     */
60691   GPIO_PINCFG83_FNCSEL83_NCE83         = 7,     /*!< NCE83 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60692                                                      CE_POLARITY field                                                         */
60693   GPIO_PINCFG83_FNCSEL83_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
60694   GPIO_PINCFG83_FNCSEL83_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
60695   GPIO_PINCFG83_FNCSEL83_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60696   GPIO_PINCFG83_FNCSEL83_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60697   GPIO_PINCFG83_FNCSEL83_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60698   GPIO_PINCFG83_FNCSEL83_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60699   GPIO_PINCFG83_FNCSEL83_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60700   GPIO_PINCFG83_FNCSEL83_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60701 } GPIO_PINCFG83_FNCSEL83_Enum;
60702 
60703 /* =======================================================  PINCFG84  ======================================================== */
60704 /* ============================================  GPIO PINCFG84 NCEPOL84 [22..22]  ============================================ */
60705 typedef enum {                                  /*!< GPIO_PINCFG84_NCEPOL84                                                    */
60706   GPIO_PINCFG84_NCEPOL84_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60707   GPIO_PINCFG84_NCEPOL84_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60708 } GPIO_PINCFG84_NCEPOL84_Enum;
60709 
60710 /* ============================================  GPIO PINCFG84 NCESRC84 [16..21]  ============================================ */
60711 typedef enum {                                  /*!< GPIO_PINCFG84_NCESRC84                                                    */
60712   GPIO_PINCFG84_NCESRC84_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60713   GPIO_PINCFG84_NCESRC84_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60714   GPIO_PINCFG84_NCESRC84_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60715   GPIO_PINCFG84_NCESRC84_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60716   GPIO_PINCFG84_NCESRC84_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60717   GPIO_PINCFG84_NCESRC84_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60718   GPIO_PINCFG84_NCESRC84_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60719   GPIO_PINCFG84_NCESRC84_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60720   GPIO_PINCFG84_NCESRC84_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60721   GPIO_PINCFG84_NCESRC84_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60722   GPIO_PINCFG84_NCESRC84_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60723   GPIO_PINCFG84_NCESRC84_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60724   GPIO_PINCFG84_NCESRC84_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60725   GPIO_PINCFG84_NCESRC84_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60726   GPIO_PINCFG84_NCESRC84_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60727   GPIO_PINCFG84_NCESRC84_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60728   GPIO_PINCFG84_NCESRC84_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60729   GPIO_PINCFG84_NCESRC84_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60730   GPIO_PINCFG84_NCESRC84_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60731   GPIO_PINCFG84_NCESRC84_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60732   GPIO_PINCFG84_NCESRC84_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60733   GPIO_PINCFG84_NCESRC84_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60734   GPIO_PINCFG84_NCESRC84_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60735   GPIO_PINCFG84_NCESRC84_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60736   GPIO_PINCFG84_NCESRC84_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60737   GPIO_PINCFG84_NCESRC84_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60738   GPIO_PINCFG84_NCESRC84_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60739   GPIO_PINCFG84_NCESRC84_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60740   GPIO_PINCFG84_NCESRC84_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60741   GPIO_PINCFG84_NCESRC84_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60742   GPIO_PINCFG84_NCESRC84_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60743   GPIO_PINCFG84_NCESRC84_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60744   GPIO_PINCFG84_NCESRC84_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60745   GPIO_PINCFG84_NCESRC84_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60746   GPIO_PINCFG84_NCESRC84_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60747   GPIO_PINCFG84_NCESRC84_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60748   GPIO_PINCFG84_NCESRC84_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60749   GPIO_PINCFG84_NCESRC84_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60750   GPIO_PINCFG84_NCESRC84_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60751   GPIO_PINCFG84_NCESRC84_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60752   GPIO_PINCFG84_NCESRC84_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60753   GPIO_PINCFG84_NCESRC84_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60754   GPIO_PINCFG84_NCESRC84_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60755 } GPIO_PINCFG84_NCESRC84_Enum;
60756 
60757 /* ===========================================  GPIO PINCFG84 PULLCFG84 [13..15]  ============================================ */
60758 typedef enum {                                  /*!< GPIO_PINCFG84_PULLCFG84                                                   */
60759   GPIO_PINCFG84_PULLCFG84_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60760   GPIO_PINCFG84_PULLCFG84_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60761   GPIO_PINCFG84_PULLCFG84_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60762   GPIO_PINCFG84_PULLCFG84_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60763   GPIO_PINCFG84_PULLCFG84_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60764   GPIO_PINCFG84_PULLCFG84_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60765   GPIO_PINCFG84_PULLCFG84_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60766   GPIO_PINCFG84_PULLCFG84_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60767 } GPIO_PINCFG84_PULLCFG84_Enum;
60768 
60769 /* ==============================================  GPIO PINCFG84 DS84 [10..11]  ============================================== */
60770 typedef enum {                                  /*!< GPIO_PINCFG84_DS84                                                        */
60771   GPIO_PINCFG84_DS84_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60772   GPIO_PINCFG84_DS84_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60773   GPIO_PINCFG84_DS84_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60774   GPIO_PINCFG84_DS84_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60775 } GPIO_PINCFG84_DS84_Enum;
60776 
60777 /* =============================================  GPIO PINCFG84 OUTCFG84 [8..9]  ============================================= */
60778 typedef enum {                                  /*!< GPIO_PINCFG84_OUTCFG84                                                    */
60779   GPIO_PINCFG84_OUTCFG84_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60780   GPIO_PINCFG84_OUTCFG84_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60781                                                      and 1 values on pin.                                                      */
60782   GPIO_PINCFG84_OUTCFG84_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60783                                                      low, tristate otherwise.                                                  */
60784   GPIO_PINCFG84_OUTCFG84_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60785                                                      drive 0, 1 of HiZ on pin.                                                 */
60786 } GPIO_PINCFG84_OUTCFG84_Enum;
60787 
60788 /* =============================================  GPIO PINCFG84 IRPTEN84 [6..7]  ============================================= */
60789 typedef enum {                                  /*!< GPIO_PINCFG84_IRPTEN84                                                    */
60790   GPIO_PINCFG84_IRPTEN84_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60791   GPIO_PINCFG84_IRPTEN84_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60792                                                      on this GPIO                                                              */
60793   GPIO_PINCFG84_IRPTEN84_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60794                                                      on this GPIO                                                              */
60795   GPIO_PINCFG84_IRPTEN84_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60796                                                      GPIO                                                                      */
60797 } GPIO_PINCFG84_IRPTEN84_Enum;
60798 
60799 /* =============================================  GPIO PINCFG84 FNCSEL84 [0..3]  ============================================= */
60800 typedef enum {                                  /*!< GPIO_PINCFG84_FNCSEL84                                                    */
60801   GPIO_PINCFG84_FNCSEL84_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60802   GPIO_PINCFG84_FNCSEL84_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60803   GPIO_PINCFG84_FNCSEL84_SDIF_DAT0     = 2,     /*!< SDIF_DAT0 : SD/SDIO/MMC Data0 pin                                         */
60804   GPIO_PINCFG84_FNCSEL84_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60805   GPIO_PINCFG84_FNCSEL84_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60806   GPIO_PINCFG84_FNCSEL84_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
60807   GPIO_PINCFG84_FNCSEL84_CT84          = 6,     /*!< CT84 : Timer/Counter input or output; Selection of direction
60808                                                      is done via CTIMER register settings.                                     */
60809   GPIO_PINCFG84_FNCSEL84_NCE84         = 7,     /*!< NCE84 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60810                                                      CE_POLARITY field                                                         */
60811   GPIO_PINCFG84_FNCSEL84_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
60812   GPIO_PINCFG84_FNCSEL84_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
60813   GPIO_PINCFG84_FNCSEL84_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60814   GPIO_PINCFG84_FNCSEL84_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60815   GPIO_PINCFG84_FNCSEL84_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60816   GPIO_PINCFG84_FNCSEL84_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60817   GPIO_PINCFG84_FNCSEL84_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60818   GPIO_PINCFG84_FNCSEL84_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60819 } GPIO_PINCFG84_FNCSEL84_Enum;
60820 
60821 /* =======================================================  PINCFG85  ======================================================== */
60822 /* ============================================  GPIO PINCFG85 NCEPOL85 [22..22]  ============================================ */
60823 typedef enum {                                  /*!< GPIO_PINCFG85_NCEPOL85                                                    */
60824   GPIO_PINCFG85_NCEPOL85_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60825   GPIO_PINCFG85_NCEPOL85_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60826 } GPIO_PINCFG85_NCEPOL85_Enum;
60827 
60828 /* ============================================  GPIO PINCFG85 NCESRC85 [16..21]  ============================================ */
60829 typedef enum {                                  /*!< GPIO_PINCFG85_NCESRC85                                                    */
60830   GPIO_PINCFG85_NCESRC85_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60831   GPIO_PINCFG85_NCESRC85_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60832   GPIO_PINCFG85_NCESRC85_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60833   GPIO_PINCFG85_NCESRC85_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60834   GPIO_PINCFG85_NCESRC85_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60835   GPIO_PINCFG85_NCESRC85_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60836   GPIO_PINCFG85_NCESRC85_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60837   GPIO_PINCFG85_NCESRC85_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60838   GPIO_PINCFG85_NCESRC85_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60839   GPIO_PINCFG85_NCESRC85_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60840   GPIO_PINCFG85_NCESRC85_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60841   GPIO_PINCFG85_NCESRC85_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60842   GPIO_PINCFG85_NCESRC85_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60843   GPIO_PINCFG85_NCESRC85_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60844   GPIO_PINCFG85_NCESRC85_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60845   GPIO_PINCFG85_NCESRC85_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60846   GPIO_PINCFG85_NCESRC85_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60847   GPIO_PINCFG85_NCESRC85_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60848   GPIO_PINCFG85_NCESRC85_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60849   GPIO_PINCFG85_NCESRC85_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60850   GPIO_PINCFG85_NCESRC85_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60851   GPIO_PINCFG85_NCESRC85_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60852   GPIO_PINCFG85_NCESRC85_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60853   GPIO_PINCFG85_NCESRC85_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60854   GPIO_PINCFG85_NCESRC85_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60855   GPIO_PINCFG85_NCESRC85_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60856   GPIO_PINCFG85_NCESRC85_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60857   GPIO_PINCFG85_NCESRC85_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60858   GPIO_PINCFG85_NCESRC85_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60859   GPIO_PINCFG85_NCESRC85_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60860   GPIO_PINCFG85_NCESRC85_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60861   GPIO_PINCFG85_NCESRC85_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60862   GPIO_PINCFG85_NCESRC85_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60863   GPIO_PINCFG85_NCESRC85_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60864   GPIO_PINCFG85_NCESRC85_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60865   GPIO_PINCFG85_NCESRC85_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60866   GPIO_PINCFG85_NCESRC85_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60867   GPIO_PINCFG85_NCESRC85_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60868   GPIO_PINCFG85_NCESRC85_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60869   GPIO_PINCFG85_NCESRC85_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60870   GPIO_PINCFG85_NCESRC85_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60871   GPIO_PINCFG85_NCESRC85_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60872   GPIO_PINCFG85_NCESRC85_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60873 } GPIO_PINCFG85_NCESRC85_Enum;
60874 
60875 /* ===========================================  GPIO PINCFG85 PULLCFG85 [13..15]  ============================================ */
60876 typedef enum {                                  /*!< GPIO_PINCFG85_PULLCFG85                                                   */
60877   GPIO_PINCFG85_PULLCFG85_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60878   GPIO_PINCFG85_PULLCFG85_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60879   GPIO_PINCFG85_PULLCFG85_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60880   GPIO_PINCFG85_PULLCFG85_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60881   GPIO_PINCFG85_PULLCFG85_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
60882   GPIO_PINCFG85_PULLCFG85_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
60883   GPIO_PINCFG85_PULLCFG85_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
60884   GPIO_PINCFG85_PULLCFG85_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
60885 } GPIO_PINCFG85_PULLCFG85_Enum;
60886 
60887 /* ==============================================  GPIO PINCFG85 DS85 [10..11]  ============================================== */
60888 typedef enum {                                  /*!< GPIO_PINCFG85_DS85                                                        */
60889   GPIO_PINCFG85_DS85_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
60890   GPIO_PINCFG85_DS85_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
60891   GPIO_PINCFG85_DS85_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
60892   GPIO_PINCFG85_DS85_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
60893 } GPIO_PINCFG85_DS85_Enum;
60894 
60895 /* =============================================  GPIO PINCFG85 OUTCFG85 [8..9]  ============================================= */
60896 typedef enum {                                  /*!< GPIO_PINCFG85_OUTCFG85                                                    */
60897   GPIO_PINCFG85_OUTCFG85_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
60898   GPIO_PINCFG85_OUTCFG85_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
60899                                                      and 1 values on pin.                                                      */
60900   GPIO_PINCFG85_OUTCFG85_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
60901                                                      low, tristate otherwise.                                                  */
60902   GPIO_PINCFG85_OUTCFG85_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
60903                                                      drive 0, 1 of HiZ on pin.                                                 */
60904 } GPIO_PINCFG85_OUTCFG85_Enum;
60905 
60906 /* =============================================  GPIO PINCFG85 IRPTEN85 [6..7]  ============================================= */
60907 typedef enum {                                  /*!< GPIO_PINCFG85_IRPTEN85                                                    */
60908   GPIO_PINCFG85_IRPTEN85_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
60909   GPIO_PINCFG85_IRPTEN85_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
60910                                                      on this GPIO                                                              */
60911   GPIO_PINCFG85_IRPTEN85_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
60912                                                      on this GPIO                                                              */
60913   GPIO_PINCFG85_IRPTEN85_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
60914                                                      GPIO                                                                      */
60915 } GPIO_PINCFG85_IRPTEN85_Enum;
60916 
60917 /* =============================================  GPIO PINCFG85 FNCSEL85 [0..3]  ============================================= */
60918 typedef enum {                                  /*!< GPIO_PINCFG85_FNCSEL85                                                    */
60919   GPIO_PINCFG85_FNCSEL85_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
60920   GPIO_PINCFG85_FNCSEL85_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
60921   GPIO_PINCFG85_FNCSEL85_SDIF_DAT1     = 2,     /*!< SDIF_DAT1 : SD/SDIO/MMC Data1 pin                                         */
60922   GPIO_PINCFG85_FNCSEL85_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
60923   GPIO_PINCFG85_FNCSEL85_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
60924   GPIO_PINCFG85_FNCSEL85_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
60925   GPIO_PINCFG85_FNCSEL85_CT85          = 6,     /*!< CT85 : Timer/Counter input or output; Selection of direction
60926                                                      is done via CTIMER register settings.                                     */
60927   GPIO_PINCFG85_FNCSEL85_NCE85         = 7,     /*!< NCE85 : IOMSTR/MSPI N Chip Select. Polarity is determined by
60928                                                      CE_POLARITY field                                                         */
60929   GPIO_PINCFG85_FNCSEL85_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
60930   GPIO_PINCFG85_FNCSEL85_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
60931   GPIO_PINCFG85_FNCSEL85_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
60932   GPIO_PINCFG85_FNCSEL85_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
60933   GPIO_PINCFG85_FNCSEL85_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
60934   GPIO_PINCFG85_FNCSEL85_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
60935   GPIO_PINCFG85_FNCSEL85_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
60936   GPIO_PINCFG85_FNCSEL85_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
60937 } GPIO_PINCFG85_FNCSEL85_Enum;
60938 
60939 /* =======================================================  PINCFG86  ======================================================== */
60940 /* ============================================  GPIO PINCFG86 NCEPOL86 [22..22]  ============================================ */
60941 typedef enum {                                  /*!< GPIO_PINCFG86_NCEPOL86                                                    */
60942   GPIO_PINCFG86_NCEPOL86_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
60943   GPIO_PINCFG86_NCEPOL86_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
60944 } GPIO_PINCFG86_NCEPOL86_Enum;
60945 
60946 /* ============================================  GPIO PINCFG86 NCESRC86 [16..21]  ============================================ */
60947 typedef enum {                                  /*!< GPIO_PINCFG86_NCESRC86                                                    */
60948   GPIO_PINCFG86_NCESRC86_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
60949   GPIO_PINCFG86_NCESRC86_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
60950   GPIO_PINCFG86_NCESRC86_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
60951   GPIO_PINCFG86_NCESRC86_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
60952   GPIO_PINCFG86_NCESRC86_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
60953   GPIO_PINCFG86_NCESRC86_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
60954   GPIO_PINCFG86_NCESRC86_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
60955   GPIO_PINCFG86_NCESRC86_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
60956   GPIO_PINCFG86_NCESRC86_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
60957   GPIO_PINCFG86_NCESRC86_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
60958   GPIO_PINCFG86_NCESRC86_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
60959   GPIO_PINCFG86_NCESRC86_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
60960   GPIO_PINCFG86_NCESRC86_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
60961   GPIO_PINCFG86_NCESRC86_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
60962   GPIO_PINCFG86_NCESRC86_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
60963   GPIO_PINCFG86_NCESRC86_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
60964   GPIO_PINCFG86_NCESRC86_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
60965   GPIO_PINCFG86_NCESRC86_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
60966   GPIO_PINCFG86_NCESRC86_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
60967   GPIO_PINCFG86_NCESRC86_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
60968   GPIO_PINCFG86_NCESRC86_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
60969   GPIO_PINCFG86_NCESRC86_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
60970   GPIO_PINCFG86_NCESRC86_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
60971   GPIO_PINCFG86_NCESRC86_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
60972   GPIO_PINCFG86_NCESRC86_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
60973   GPIO_PINCFG86_NCESRC86_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
60974   GPIO_PINCFG86_NCESRC86_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
60975   GPIO_PINCFG86_NCESRC86_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
60976   GPIO_PINCFG86_NCESRC86_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
60977   GPIO_PINCFG86_NCESRC86_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
60978   GPIO_PINCFG86_NCESRC86_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
60979   GPIO_PINCFG86_NCESRC86_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
60980   GPIO_PINCFG86_NCESRC86_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
60981   GPIO_PINCFG86_NCESRC86_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
60982   GPIO_PINCFG86_NCESRC86_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
60983   GPIO_PINCFG86_NCESRC86_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
60984   GPIO_PINCFG86_NCESRC86_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
60985   GPIO_PINCFG86_NCESRC86_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
60986   GPIO_PINCFG86_NCESRC86_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
60987   GPIO_PINCFG86_NCESRC86_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
60988   GPIO_PINCFG86_NCESRC86_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
60989   GPIO_PINCFG86_NCESRC86_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
60990   GPIO_PINCFG86_NCESRC86_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
60991 } GPIO_PINCFG86_NCESRC86_Enum;
60992 
60993 /* ===========================================  GPIO PINCFG86 PULLCFG86 [13..15]  ============================================ */
60994 typedef enum {                                  /*!< GPIO_PINCFG86_PULLCFG86                                                   */
60995   GPIO_PINCFG86_PULLCFG86_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
60996   GPIO_PINCFG86_PULLCFG86_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
60997   GPIO_PINCFG86_PULLCFG86_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
60998   GPIO_PINCFG86_PULLCFG86_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
60999   GPIO_PINCFG86_PULLCFG86_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61000   GPIO_PINCFG86_PULLCFG86_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61001   GPIO_PINCFG86_PULLCFG86_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61002   GPIO_PINCFG86_PULLCFG86_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61003 } GPIO_PINCFG86_PULLCFG86_Enum;
61004 
61005 /* ==============================================  GPIO PINCFG86 DS86 [10..11]  ============================================== */
61006 typedef enum {                                  /*!< GPIO_PINCFG86_DS86                                                        */
61007   GPIO_PINCFG86_DS86_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61008   GPIO_PINCFG86_DS86_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61009   GPIO_PINCFG86_DS86_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
61010   GPIO_PINCFG86_DS86_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
61011 } GPIO_PINCFG86_DS86_Enum;
61012 
61013 /* =============================================  GPIO PINCFG86 OUTCFG86 [8..9]  ============================================= */
61014 typedef enum {                                  /*!< GPIO_PINCFG86_OUTCFG86                                                    */
61015   GPIO_PINCFG86_OUTCFG86_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61016   GPIO_PINCFG86_OUTCFG86_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61017                                                      and 1 values on pin.                                                      */
61018   GPIO_PINCFG86_OUTCFG86_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61019                                                      low, tristate otherwise.                                                  */
61020   GPIO_PINCFG86_OUTCFG86_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61021                                                      drive 0, 1 of HiZ on pin.                                                 */
61022 } GPIO_PINCFG86_OUTCFG86_Enum;
61023 
61024 /* =============================================  GPIO PINCFG86 IRPTEN86 [6..7]  ============================================= */
61025 typedef enum {                                  /*!< GPIO_PINCFG86_IRPTEN86                                                    */
61026   GPIO_PINCFG86_IRPTEN86_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61027   GPIO_PINCFG86_IRPTEN86_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61028                                                      on this GPIO                                                              */
61029   GPIO_PINCFG86_IRPTEN86_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61030                                                      on this GPIO                                                              */
61031   GPIO_PINCFG86_IRPTEN86_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61032                                                      GPIO                                                                      */
61033 } GPIO_PINCFG86_IRPTEN86_Enum;
61034 
61035 /* =============================================  GPIO PINCFG86 FNCSEL86 [0..3]  ============================================= */
61036 typedef enum {                                  /*!< GPIO_PINCFG86_FNCSEL86                                                    */
61037   GPIO_PINCFG86_FNCSEL86_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61038   GPIO_PINCFG86_FNCSEL86_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61039   GPIO_PINCFG86_FNCSEL86_SDIF_DAT2     = 2,     /*!< SDIF_DAT2 : SD/SDIO/MMC Data2 pin                                         */
61040   GPIO_PINCFG86_FNCSEL86_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61041   GPIO_PINCFG86_FNCSEL86_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61042   GPIO_PINCFG86_FNCSEL86_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61043   GPIO_PINCFG86_FNCSEL86_CT86          = 6,     /*!< CT86 : Timer/Counter input or output; Selection of direction
61044                                                      is done via CTIMER register settings.                                     */
61045   GPIO_PINCFG86_FNCSEL86_NCE86         = 7,     /*!< NCE86 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61046                                                      CE_POLARITY field                                                         */
61047   GPIO_PINCFG86_FNCSEL86_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
61048   GPIO_PINCFG86_FNCSEL86_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61049   GPIO_PINCFG86_FNCSEL86_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61050   GPIO_PINCFG86_FNCSEL86_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61051   GPIO_PINCFG86_FNCSEL86_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61052   GPIO_PINCFG86_FNCSEL86_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61053   GPIO_PINCFG86_FNCSEL86_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61054   GPIO_PINCFG86_FNCSEL86_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61055 } GPIO_PINCFG86_FNCSEL86_Enum;
61056 
61057 /* =======================================================  PINCFG87  ======================================================== */
61058 /* ============================================  GPIO PINCFG87 NCEPOL87 [22..22]  ============================================ */
61059 typedef enum {                                  /*!< GPIO_PINCFG87_NCEPOL87                                                    */
61060   GPIO_PINCFG87_NCEPOL87_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61061   GPIO_PINCFG87_NCEPOL87_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61062 } GPIO_PINCFG87_NCEPOL87_Enum;
61063 
61064 /* ============================================  GPIO PINCFG87 NCESRC87 [16..21]  ============================================ */
61065 typedef enum {                                  /*!< GPIO_PINCFG87_NCESRC87                                                    */
61066   GPIO_PINCFG87_NCESRC87_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61067   GPIO_PINCFG87_NCESRC87_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61068   GPIO_PINCFG87_NCESRC87_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61069   GPIO_PINCFG87_NCESRC87_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61070   GPIO_PINCFG87_NCESRC87_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61071   GPIO_PINCFG87_NCESRC87_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61072   GPIO_PINCFG87_NCESRC87_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61073   GPIO_PINCFG87_NCESRC87_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61074   GPIO_PINCFG87_NCESRC87_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61075   GPIO_PINCFG87_NCESRC87_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61076   GPIO_PINCFG87_NCESRC87_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61077   GPIO_PINCFG87_NCESRC87_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61078   GPIO_PINCFG87_NCESRC87_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61079   GPIO_PINCFG87_NCESRC87_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61080   GPIO_PINCFG87_NCESRC87_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61081   GPIO_PINCFG87_NCESRC87_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61082   GPIO_PINCFG87_NCESRC87_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61083   GPIO_PINCFG87_NCESRC87_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61084   GPIO_PINCFG87_NCESRC87_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61085   GPIO_PINCFG87_NCESRC87_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61086   GPIO_PINCFG87_NCESRC87_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61087   GPIO_PINCFG87_NCESRC87_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61088   GPIO_PINCFG87_NCESRC87_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61089   GPIO_PINCFG87_NCESRC87_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61090   GPIO_PINCFG87_NCESRC87_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61091   GPIO_PINCFG87_NCESRC87_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61092   GPIO_PINCFG87_NCESRC87_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61093   GPIO_PINCFG87_NCESRC87_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61094   GPIO_PINCFG87_NCESRC87_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61095   GPIO_PINCFG87_NCESRC87_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61096   GPIO_PINCFG87_NCESRC87_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61097   GPIO_PINCFG87_NCESRC87_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61098   GPIO_PINCFG87_NCESRC87_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61099   GPIO_PINCFG87_NCESRC87_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61100   GPIO_PINCFG87_NCESRC87_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61101   GPIO_PINCFG87_NCESRC87_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61102   GPIO_PINCFG87_NCESRC87_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61103   GPIO_PINCFG87_NCESRC87_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61104   GPIO_PINCFG87_NCESRC87_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61105   GPIO_PINCFG87_NCESRC87_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61106   GPIO_PINCFG87_NCESRC87_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61107   GPIO_PINCFG87_NCESRC87_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61108   GPIO_PINCFG87_NCESRC87_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61109 } GPIO_PINCFG87_NCESRC87_Enum;
61110 
61111 /* ===========================================  GPIO PINCFG87 PULLCFG87 [13..15]  ============================================ */
61112 typedef enum {                                  /*!< GPIO_PINCFG87_PULLCFG87                                                   */
61113   GPIO_PINCFG87_PULLCFG87_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61114   GPIO_PINCFG87_PULLCFG87_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61115   GPIO_PINCFG87_PULLCFG87_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61116   GPIO_PINCFG87_PULLCFG87_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61117   GPIO_PINCFG87_PULLCFG87_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61118   GPIO_PINCFG87_PULLCFG87_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61119   GPIO_PINCFG87_PULLCFG87_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61120   GPIO_PINCFG87_PULLCFG87_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61121 } GPIO_PINCFG87_PULLCFG87_Enum;
61122 
61123 /* ==============================================  GPIO PINCFG87 DS87 [10..11]  ============================================== */
61124 typedef enum {                                  /*!< GPIO_PINCFG87_DS87                                                        */
61125   GPIO_PINCFG87_DS87_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61126   GPIO_PINCFG87_DS87_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61127   GPIO_PINCFG87_DS87_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
61128   GPIO_PINCFG87_DS87_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
61129 } GPIO_PINCFG87_DS87_Enum;
61130 
61131 /* =============================================  GPIO PINCFG87 OUTCFG87 [8..9]  ============================================= */
61132 typedef enum {                                  /*!< GPIO_PINCFG87_OUTCFG87                                                    */
61133   GPIO_PINCFG87_OUTCFG87_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61134   GPIO_PINCFG87_OUTCFG87_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61135                                                      and 1 values on pin.                                                      */
61136   GPIO_PINCFG87_OUTCFG87_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61137                                                      low, tristate otherwise.                                                  */
61138   GPIO_PINCFG87_OUTCFG87_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61139                                                      drive 0, 1 of HiZ on pin.                                                 */
61140 } GPIO_PINCFG87_OUTCFG87_Enum;
61141 
61142 /* =============================================  GPIO PINCFG87 IRPTEN87 [6..7]  ============================================= */
61143 typedef enum {                                  /*!< GPIO_PINCFG87_IRPTEN87                                                    */
61144   GPIO_PINCFG87_IRPTEN87_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61145   GPIO_PINCFG87_IRPTEN87_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61146                                                      on this GPIO                                                              */
61147   GPIO_PINCFG87_IRPTEN87_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61148                                                      on this GPIO                                                              */
61149   GPIO_PINCFG87_IRPTEN87_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61150                                                      GPIO                                                                      */
61151 } GPIO_PINCFG87_IRPTEN87_Enum;
61152 
61153 /* =============================================  GPIO PINCFG87 FNCSEL87 [0..3]  ============================================= */
61154 typedef enum {                                  /*!< GPIO_PINCFG87_FNCSEL87                                                    */
61155   GPIO_PINCFG87_FNCSEL87_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61156   GPIO_PINCFG87_FNCSEL87_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61157   GPIO_PINCFG87_FNCSEL87_SDIF_DAT3     = 2,     /*!< SDIF_DAT3 : SD/SDIO/MMC Data3 pin                                         */
61158   GPIO_PINCFG87_FNCSEL87_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61159   GPIO_PINCFG87_FNCSEL87_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61160   GPIO_PINCFG87_FNCSEL87_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61161   GPIO_PINCFG87_FNCSEL87_CT87          = 6,     /*!< CT87 : Timer/Counter input or output; Selection of direction
61162                                                      is done via CTIMER register settings.                                     */
61163   GPIO_PINCFG87_FNCSEL87_NCE87         = 7,     /*!< NCE87 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61164                                                      CE_POLARITY field                                                         */
61165   GPIO_PINCFG87_FNCSEL87_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
61166   GPIO_PINCFG87_FNCSEL87_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
61167   GPIO_PINCFG87_FNCSEL87_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61168   GPIO_PINCFG87_FNCSEL87_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61169   GPIO_PINCFG87_FNCSEL87_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61170   GPIO_PINCFG87_FNCSEL87_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61171   GPIO_PINCFG87_FNCSEL87_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61172   GPIO_PINCFG87_FNCSEL87_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61173 } GPIO_PINCFG87_FNCSEL87_Enum;
61174 
61175 /* =======================================================  PINCFG88  ======================================================== */
61176 /* ============================================  GPIO PINCFG88 NCEPOL88 [22..22]  ============================================ */
61177 typedef enum {                                  /*!< GPIO_PINCFG88_NCEPOL88                                                    */
61178   GPIO_PINCFG88_NCEPOL88_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61179   GPIO_PINCFG88_NCEPOL88_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61180 } GPIO_PINCFG88_NCEPOL88_Enum;
61181 
61182 /* ============================================  GPIO PINCFG88 NCESRC88 [16..21]  ============================================ */
61183 typedef enum {                                  /*!< GPIO_PINCFG88_NCESRC88                                                    */
61184   GPIO_PINCFG88_NCESRC88_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61185   GPIO_PINCFG88_NCESRC88_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61186   GPIO_PINCFG88_NCESRC88_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61187   GPIO_PINCFG88_NCESRC88_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61188   GPIO_PINCFG88_NCESRC88_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61189   GPIO_PINCFG88_NCESRC88_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61190   GPIO_PINCFG88_NCESRC88_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61191   GPIO_PINCFG88_NCESRC88_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61192   GPIO_PINCFG88_NCESRC88_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61193   GPIO_PINCFG88_NCESRC88_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61194   GPIO_PINCFG88_NCESRC88_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61195   GPIO_PINCFG88_NCESRC88_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61196   GPIO_PINCFG88_NCESRC88_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61197   GPIO_PINCFG88_NCESRC88_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61198   GPIO_PINCFG88_NCESRC88_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61199   GPIO_PINCFG88_NCESRC88_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61200   GPIO_PINCFG88_NCESRC88_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61201   GPIO_PINCFG88_NCESRC88_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61202   GPIO_PINCFG88_NCESRC88_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61203   GPIO_PINCFG88_NCESRC88_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61204   GPIO_PINCFG88_NCESRC88_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61205   GPIO_PINCFG88_NCESRC88_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61206   GPIO_PINCFG88_NCESRC88_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61207   GPIO_PINCFG88_NCESRC88_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61208   GPIO_PINCFG88_NCESRC88_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61209   GPIO_PINCFG88_NCESRC88_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61210   GPIO_PINCFG88_NCESRC88_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61211   GPIO_PINCFG88_NCESRC88_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61212   GPIO_PINCFG88_NCESRC88_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61213   GPIO_PINCFG88_NCESRC88_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61214   GPIO_PINCFG88_NCESRC88_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61215   GPIO_PINCFG88_NCESRC88_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61216   GPIO_PINCFG88_NCESRC88_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61217   GPIO_PINCFG88_NCESRC88_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61218   GPIO_PINCFG88_NCESRC88_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61219   GPIO_PINCFG88_NCESRC88_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61220   GPIO_PINCFG88_NCESRC88_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61221   GPIO_PINCFG88_NCESRC88_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61222   GPIO_PINCFG88_NCESRC88_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61223   GPIO_PINCFG88_NCESRC88_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61224   GPIO_PINCFG88_NCESRC88_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61225   GPIO_PINCFG88_NCESRC88_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61226   GPIO_PINCFG88_NCESRC88_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61227 } GPIO_PINCFG88_NCESRC88_Enum;
61228 
61229 /* ===========================================  GPIO PINCFG88 PULLCFG88 [13..15]  ============================================ */
61230 typedef enum {                                  /*!< GPIO_PINCFG88_PULLCFG88                                                   */
61231   GPIO_PINCFG88_PULLCFG88_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61232   GPIO_PINCFG88_PULLCFG88_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61233   GPIO_PINCFG88_PULLCFG88_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61234   GPIO_PINCFG88_PULLCFG88_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61235   GPIO_PINCFG88_PULLCFG88_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61236   GPIO_PINCFG88_PULLCFG88_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61237   GPIO_PINCFG88_PULLCFG88_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61238   GPIO_PINCFG88_PULLCFG88_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61239 } GPIO_PINCFG88_PULLCFG88_Enum;
61240 
61241 /* ==============================================  GPIO PINCFG88 DS88 [10..11]  ============================================== */
61242 typedef enum {                                  /*!< GPIO_PINCFG88_DS88                                                        */
61243   GPIO_PINCFG88_DS88_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61244   GPIO_PINCFG88_DS88_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61245   GPIO_PINCFG88_DS88_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
61246   GPIO_PINCFG88_DS88_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
61247 } GPIO_PINCFG88_DS88_Enum;
61248 
61249 /* =============================================  GPIO PINCFG88 OUTCFG88 [8..9]  ============================================= */
61250 typedef enum {                                  /*!< GPIO_PINCFG88_OUTCFG88                                                    */
61251   GPIO_PINCFG88_OUTCFG88_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61252   GPIO_PINCFG88_OUTCFG88_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61253                                                      and 1 values on pin.                                                      */
61254   GPIO_PINCFG88_OUTCFG88_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61255                                                      low, tristate otherwise.                                                  */
61256   GPIO_PINCFG88_OUTCFG88_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61257                                                      drive 0, 1 of HiZ on pin.                                                 */
61258 } GPIO_PINCFG88_OUTCFG88_Enum;
61259 
61260 /* =============================================  GPIO PINCFG88 IRPTEN88 [6..7]  ============================================= */
61261 typedef enum {                                  /*!< GPIO_PINCFG88_IRPTEN88                                                    */
61262   GPIO_PINCFG88_IRPTEN88_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61263   GPIO_PINCFG88_IRPTEN88_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61264                                                      on this GPIO                                                              */
61265   GPIO_PINCFG88_IRPTEN88_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61266                                                      on this GPIO                                                              */
61267   GPIO_PINCFG88_IRPTEN88_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61268                                                      GPIO                                                                      */
61269 } GPIO_PINCFG88_IRPTEN88_Enum;
61270 
61271 /* =============================================  GPIO PINCFG88 FNCSEL88 [0..3]  ============================================= */
61272 typedef enum {                                  /*!< GPIO_PINCFG88_FNCSEL88                                                    */
61273   GPIO_PINCFG88_FNCSEL88_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61274   GPIO_PINCFG88_FNCSEL88_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61275   GPIO_PINCFG88_FNCSEL88_SDIF_CLKOUT   = 2,     /*!< SDIF_CLKOUT : SD/SDIO/MMC Clock to Card (CLK)                             */
61276   GPIO_PINCFG88_FNCSEL88_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61277   GPIO_PINCFG88_FNCSEL88_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61278   GPIO_PINCFG88_FNCSEL88_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61279   GPIO_PINCFG88_FNCSEL88_CT88          = 6,     /*!< CT88 : Timer/Counter input or output; Selection of direction
61280                                                      is done via CTIMER register settings.                                     */
61281   GPIO_PINCFG88_FNCSEL88_NCE88         = 7,     /*!< NCE88 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61282                                                      CE_POLARITY field                                                         */
61283   GPIO_PINCFG88_FNCSEL88_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
61284   GPIO_PINCFG88_FNCSEL88_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61285   GPIO_PINCFG88_FNCSEL88_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61286   GPIO_PINCFG88_FNCSEL88_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61287   GPIO_PINCFG88_FNCSEL88_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61288   GPIO_PINCFG88_FNCSEL88_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61289   GPIO_PINCFG88_FNCSEL88_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61290   GPIO_PINCFG88_FNCSEL88_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61291 } GPIO_PINCFG88_FNCSEL88_Enum;
61292 
61293 /* =======================================================  PINCFG89  ======================================================== */
61294 /* ============================================  GPIO PINCFG89 NCEPOL89 [22..22]  ============================================ */
61295 typedef enum {                                  /*!< GPIO_PINCFG89_NCEPOL89                                                    */
61296   GPIO_PINCFG89_NCEPOL89_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61297   GPIO_PINCFG89_NCEPOL89_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61298 } GPIO_PINCFG89_NCEPOL89_Enum;
61299 
61300 /* ============================================  GPIO PINCFG89 NCESRC89 [16..21]  ============================================ */
61301 typedef enum {                                  /*!< GPIO_PINCFG89_NCESRC89                                                    */
61302   GPIO_PINCFG89_NCESRC89_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61303   GPIO_PINCFG89_NCESRC89_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61304   GPIO_PINCFG89_NCESRC89_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61305   GPIO_PINCFG89_NCESRC89_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61306   GPIO_PINCFG89_NCESRC89_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61307   GPIO_PINCFG89_NCESRC89_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61308   GPIO_PINCFG89_NCESRC89_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61309   GPIO_PINCFG89_NCESRC89_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61310   GPIO_PINCFG89_NCESRC89_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61311   GPIO_PINCFG89_NCESRC89_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61312   GPIO_PINCFG89_NCESRC89_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61313   GPIO_PINCFG89_NCESRC89_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61314   GPIO_PINCFG89_NCESRC89_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61315   GPIO_PINCFG89_NCESRC89_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61316   GPIO_PINCFG89_NCESRC89_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61317   GPIO_PINCFG89_NCESRC89_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61318   GPIO_PINCFG89_NCESRC89_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61319   GPIO_PINCFG89_NCESRC89_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61320   GPIO_PINCFG89_NCESRC89_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61321   GPIO_PINCFG89_NCESRC89_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61322   GPIO_PINCFG89_NCESRC89_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61323   GPIO_PINCFG89_NCESRC89_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61324   GPIO_PINCFG89_NCESRC89_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61325   GPIO_PINCFG89_NCESRC89_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61326   GPIO_PINCFG89_NCESRC89_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61327   GPIO_PINCFG89_NCESRC89_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61328   GPIO_PINCFG89_NCESRC89_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61329   GPIO_PINCFG89_NCESRC89_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61330   GPIO_PINCFG89_NCESRC89_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61331   GPIO_PINCFG89_NCESRC89_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61332   GPIO_PINCFG89_NCESRC89_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61333   GPIO_PINCFG89_NCESRC89_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61334   GPIO_PINCFG89_NCESRC89_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61335   GPIO_PINCFG89_NCESRC89_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61336   GPIO_PINCFG89_NCESRC89_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61337   GPIO_PINCFG89_NCESRC89_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61338   GPIO_PINCFG89_NCESRC89_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61339   GPIO_PINCFG89_NCESRC89_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61340   GPIO_PINCFG89_NCESRC89_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61341   GPIO_PINCFG89_NCESRC89_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61342   GPIO_PINCFG89_NCESRC89_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61343   GPIO_PINCFG89_NCESRC89_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61344   GPIO_PINCFG89_NCESRC89_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61345 } GPIO_PINCFG89_NCESRC89_Enum;
61346 
61347 /* ===========================================  GPIO PINCFG89 PULLCFG89 [13..15]  ============================================ */
61348 typedef enum {                                  /*!< GPIO_PINCFG89_PULLCFG89                                                   */
61349   GPIO_PINCFG89_PULLCFG89_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61350   GPIO_PINCFG89_PULLCFG89_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61351   GPIO_PINCFG89_PULLCFG89_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61352   GPIO_PINCFG89_PULLCFG89_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61353   GPIO_PINCFG89_PULLCFG89_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61354   GPIO_PINCFG89_PULLCFG89_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61355   GPIO_PINCFG89_PULLCFG89_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61356   GPIO_PINCFG89_PULLCFG89_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61357 } GPIO_PINCFG89_PULLCFG89_Enum;
61358 
61359 /* ==============================================  GPIO PINCFG89 DS89 [10..11]  ============================================== */
61360 typedef enum {                                  /*!< GPIO_PINCFG89_DS89                                                        */
61361   GPIO_PINCFG89_DS89_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61362   GPIO_PINCFG89_DS89_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61363 } GPIO_PINCFG89_DS89_Enum;
61364 
61365 /* =============================================  GPIO PINCFG89 OUTCFG89 [8..9]  ============================================= */
61366 typedef enum {                                  /*!< GPIO_PINCFG89_OUTCFG89                                                    */
61367   GPIO_PINCFG89_OUTCFG89_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61368   GPIO_PINCFG89_OUTCFG89_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61369                                                      and 1 values on pin.                                                      */
61370   GPIO_PINCFG89_OUTCFG89_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61371                                                      low, tristate otherwise.                                                  */
61372   GPIO_PINCFG89_OUTCFG89_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61373                                                      drive 0, 1 of HiZ on pin.                                                 */
61374 } GPIO_PINCFG89_OUTCFG89_Enum;
61375 
61376 /* =============================================  GPIO PINCFG89 IRPTEN89 [6..7]  ============================================= */
61377 typedef enum {                                  /*!< GPIO_PINCFG89_IRPTEN89                                                    */
61378   GPIO_PINCFG89_IRPTEN89_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61379   GPIO_PINCFG89_IRPTEN89_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61380                                                      on this GPIO                                                              */
61381   GPIO_PINCFG89_IRPTEN89_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61382                                                      on this GPIO                                                              */
61383   GPIO_PINCFG89_IRPTEN89_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61384                                                      GPIO                                                                      */
61385 } GPIO_PINCFG89_IRPTEN89_Enum;
61386 
61387 /* =============================================  GPIO PINCFG89 FNCSEL89 [0..3]  ============================================= */
61388 typedef enum {                                  /*!< GPIO_PINCFG89_FNCSEL89                                                    */
61389   GPIO_PINCFG89_FNCSEL89_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61390   GPIO_PINCFG89_FNCSEL89_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61391   GPIO_PINCFG89_FNCSEL89_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61392   GPIO_PINCFG89_FNCSEL89_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61393   GPIO_PINCFG89_FNCSEL89_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61394   GPIO_PINCFG89_FNCSEL89_DISP_CM       = 5,     /*!< DISP_CM : Display RGB Color Mode                                          */
61395   GPIO_PINCFG89_FNCSEL89_CT89          = 6,     /*!< CT89 : Timer/Counter input or output; Selection of direction
61396                                                      is done via CTIMER register settings.                                     */
61397   GPIO_PINCFG89_FNCSEL89_NCE89         = 7,     /*!< NCE89 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61398                                                      CE_POLARITY field                                                         */
61399   GPIO_PINCFG89_FNCSEL89_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
61400   GPIO_PINCFG89_FNCSEL89_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
61401   GPIO_PINCFG89_FNCSEL89_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61402   GPIO_PINCFG89_FNCSEL89_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61403   GPIO_PINCFG89_FNCSEL89_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61404   GPIO_PINCFG89_FNCSEL89_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61405   GPIO_PINCFG89_FNCSEL89_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61406   GPIO_PINCFG89_FNCSEL89_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61407 } GPIO_PINCFG89_FNCSEL89_Enum;
61408 
61409 /* =======================================================  PINCFG90  ======================================================== */
61410 /* ============================================  GPIO PINCFG90 NCEPOL90 [22..22]  ============================================ */
61411 typedef enum {                                  /*!< GPIO_PINCFG90_NCEPOL90                                                    */
61412   GPIO_PINCFG90_NCEPOL90_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61413   GPIO_PINCFG90_NCEPOL90_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61414 } GPIO_PINCFG90_NCEPOL90_Enum;
61415 
61416 /* ============================================  GPIO PINCFG90 NCESRC90 [16..21]  ============================================ */
61417 typedef enum {                                  /*!< GPIO_PINCFG90_NCESRC90                                                    */
61418   GPIO_PINCFG90_NCESRC90_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61419   GPIO_PINCFG90_NCESRC90_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61420   GPIO_PINCFG90_NCESRC90_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61421   GPIO_PINCFG90_NCESRC90_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61422   GPIO_PINCFG90_NCESRC90_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61423   GPIO_PINCFG90_NCESRC90_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61424   GPIO_PINCFG90_NCESRC90_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61425   GPIO_PINCFG90_NCESRC90_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61426   GPIO_PINCFG90_NCESRC90_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61427   GPIO_PINCFG90_NCESRC90_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61428   GPIO_PINCFG90_NCESRC90_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61429   GPIO_PINCFG90_NCESRC90_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61430   GPIO_PINCFG90_NCESRC90_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61431   GPIO_PINCFG90_NCESRC90_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61432   GPIO_PINCFG90_NCESRC90_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61433   GPIO_PINCFG90_NCESRC90_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61434   GPIO_PINCFG90_NCESRC90_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61435   GPIO_PINCFG90_NCESRC90_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61436   GPIO_PINCFG90_NCESRC90_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61437   GPIO_PINCFG90_NCESRC90_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61438   GPIO_PINCFG90_NCESRC90_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61439   GPIO_PINCFG90_NCESRC90_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61440   GPIO_PINCFG90_NCESRC90_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61441   GPIO_PINCFG90_NCESRC90_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61442   GPIO_PINCFG90_NCESRC90_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61443   GPIO_PINCFG90_NCESRC90_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61444   GPIO_PINCFG90_NCESRC90_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61445   GPIO_PINCFG90_NCESRC90_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61446   GPIO_PINCFG90_NCESRC90_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61447   GPIO_PINCFG90_NCESRC90_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61448   GPIO_PINCFG90_NCESRC90_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61449   GPIO_PINCFG90_NCESRC90_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61450   GPIO_PINCFG90_NCESRC90_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61451   GPIO_PINCFG90_NCESRC90_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61452   GPIO_PINCFG90_NCESRC90_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61453   GPIO_PINCFG90_NCESRC90_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61454   GPIO_PINCFG90_NCESRC90_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61455   GPIO_PINCFG90_NCESRC90_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61456   GPIO_PINCFG90_NCESRC90_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61457   GPIO_PINCFG90_NCESRC90_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61458   GPIO_PINCFG90_NCESRC90_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61459   GPIO_PINCFG90_NCESRC90_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61460   GPIO_PINCFG90_NCESRC90_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61461 } GPIO_PINCFG90_NCESRC90_Enum;
61462 
61463 /* ===========================================  GPIO PINCFG90 PULLCFG90 [13..15]  ============================================ */
61464 typedef enum {                                  /*!< GPIO_PINCFG90_PULLCFG90                                                   */
61465   GPIO_PINCFG90_PULLCFG90_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61466   GPIO_PINCFG90_PULLCFG90_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61467   GPIO_PINCFG90_PULLCFG90_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61468   GPIO_PINCFG90_PULLCFG90_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61469   GPIO_PINCFG90_PULLCFG90_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61470   GPIO_PINCFG90_PULLCFG90_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61471   GPIO_PINCFG90_PULLCFG90_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61472   GPIO_PINCFG90_PULLCFG90_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61473 } GPIO_PINCFG90_PULLCFG90_Enum;
61474 
61475 /* ==============================================  GPIO PINCFG90 DS90 [10..11]  ============================================== */
61476 typedef enum {                                  /*!< GPIO_PINCFG90_DS90                                                        */
61477   GPIO_PINCFG90_DS90_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61478   GPIO_PINCFG90_DS90_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61479 } GPIO_PINCFG90_DS90_Enum;
61480 
61481 /* =============================================  GPIO PINCFG90 OUTCFG90 [8..9]  ============================================= */
61482 typedef enum {                                  /*!< GPIO_PINCFG90_OUTCFG90                                                    */
61483   GPIO_PINCFG90_OUTCFG90_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61484   GPIO_PINCFG90_OUTCFG90_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61485                                                      and 1 values on pin.                                                      */
61486   GPIO_PINCFG90_OUTCFG90_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61487                                                      low, tristate otherwise.                                                  */
61488   GPIO_PINCFG90_OUTCFG90_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61489                                                      drive 0, 1 of HiZ on pin.                                                 */
61490 } GPIO_PINCFG90_OUTCFG90_Enum;
61491 
61492 /* =============================================  GPIO PINCFG90 IRPTEN90 [6..7]  ============================================= */
61493 typedef enum {                                  /*!< GPIO_PINCFG90_IRPTEN90                                                    */
61494   GPIO_PINCFG90_IRPTEN90_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61495   GPIO_PINCFG90_IRPTEN90_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61496                                                      on this GPIO                                                              */
61497   GPIO_PINCFG90_IRPTEN90_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61498                                                      on this GPIO                                                              */
61499   GPIO_PINCFG90_IRPTEN90_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61500                                                      GPIO                                                                      */
61501 } GPIO_PINCFG90_IRPTEN90_Enum;
61502 
61503 /* =============================================  GPIO PINCFG90 FNCSEL90 [0..3]  ============================================= */
61504 typedef enum {                                  /*!< GPIO_PINCFG90_FNCSEL90                                                    */
61505   GPIO_PINCFG90_FNCSEL90_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61506   GPIO_PINCFG90_FNCSEL90_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61507   GPIO_PINCFG90_FNCSEL90_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61508   GPIO_PINCFG90_FNCSEL90_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61509   GPIO_PINCFG90_FNCSEL90_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61510   GPIO_PINCFG90_FNCSEL90_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61511   GPIO_PINCFG90_FNCSEL90_CT90          = 6,     /*!< CT90 : Timer/Counter input or output; Selection of direction
61512                                                      is done via CTIMER register settings.                                     */
61513   GPIO_PINCFG90_FNCSEL90_NCE90         = 7,     /*!< NCE90 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61514                                                      CE_POLARITY field                                                         */
61515   GPIO_PINCFG90_FNCSEL90_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
61516   GPIO_PINCFG90_FNCSEL90_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
61517   GPIO_PINCFG90_FNCSEL90_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61518   GPIO_PINCFG90_FNCSEL90_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61519   GPIO_PINCFG90_FNCSEL90_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61520   GPIO_PINCFG90_FNCSEL90_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61521   GPIO_PINCFG90_FNCSEL90_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61522   GPIO_PINCFG90_FNCSEL90_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61523 } GPIO_PINCFG90_FNCSEL90_Enum;
61524 
61525 /* =======================================================  PINCFG91  ======================================================== */
61526 /* ============================================  GPIO PINCFG91 NCEPOL91 [22..22]  ============================================ */
61527 typedef enum {                                  /*!< GPIO_PINCFG91_NCEPOL91                                                    */
61528   GPIO_PINCFG91_NCEPOL91_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61529   GPIO_PINCFG91_NCEPOL91_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61530 } GPIO_PINCFG91_NCEPOL91_Enum;
61531 
61532 /* ============================================  GPIO PINCFG91 NCESRC91 [16..21]  ============================================ */
61533 typedef enum {                                  /*!< GPIO_PINCFG91_NCESRC91                                                    */
61534   GPIO_PINCFG91_NCESRC91_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61535   GPIO_PINCFG91_NCESRC91_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61536   GPIO_PINCFG91_NCESRC91_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61537   GPIO_PINCFG91_NCESRC91_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61538   GPIO_PINCFG91_NCESRC91_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61539   GPIO_PINCFG91_NCESRC91_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61540   GPIO_PINCFG91_NCESRC91_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61541   GPIO_PINCFG91_NCESRC91_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61542   GPIO_PINCFG91_NCESRC91_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61543   GPIO_PINCFG91_NCESRC91_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61544   GPIO_PINCFG91_NCESRC91_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61545   GPIO_PINCFG91_NCESRC91_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61546   GPIO_PINCFG91_NCESRC91_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61547   GPIO_PINCFG91_NCESRC91_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61548   GPIO_PINCFG91_NCESRC91_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61549   GPIO_PINCFG91_NCESRC91_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61550   GPIO_PINCFG91_NCESRC91_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61551   GPIO_PINCFG91_NCESRC91_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61552   GPIO_PINCFG91_NCESRC91_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61553   GPIO_PINCFG91_NCESRC91_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61554   GPIO_PINCFG91_NCESRC91_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61555   GPIO_PINCFG91_NCESRC91_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61556   GPIO_PINCFG91_NCESRC91_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61557   GPIO_PINCFG91_NCESRC91_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61558   GPIO_PINCFG91_NCESRC91_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61559   GPIO_PINCFG91_NCESRC91_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61560   GPIO_PINCFG91_NCESRC91_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61561   GPIO_PINCFG91_NCESRC91_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61562   GPIO_PINCFG91_NCESRC91_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61563   GPIO_PINCFG91_NCESRC91_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61564   GPIO_PINCFG91_NCESRC91_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61565   GPIO_PINCFG91_NCESRC91_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61566   GPIO_PINCFG91_NCESRC91_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61567   GPIO_PINCFG91_NCESRC91_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61568   GPIO_PINCFG91_NCESRC91_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61569   GPIO_PINCFG91_NCESRC91_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61570   GPIO_PINCFG91_NCESRC91_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61571   GPIO_PINCFG91_NCESRC91_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61572   GPIO_PINCFG91_NCESRC91_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61573   GPIO_PINCFG91_NCESRC91_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61574   GPIO_PINCFG91_NCESRC91_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61575   GPIO_PINCFG91_NCESRC91_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61576   GPIO_PINCFG91_NCESRC91_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61577 } GPIO_PINCFG91_NCESRC91_Enum;
61578 
61579 /* ===========================================  GPIO PINCFG91 PULLCFG91 [13..15]  ============================================ */
61580 typedef enum {                                  /*!< GPIO_PINCFG91_PULLCFG91                                                   */
61581   GPIO_PINCFG91_PULLCFG91_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61582   GPIO_PINCFG91_PULLCFG91_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61583   GPIO_PINCFG91_PULLCFG91_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61584   GPIO_PINCFG91_PULLCFG91_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61585   GPIO_PINCFG91_PULLCFG91_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61586   GPIO_PINCFG91_PULLCFG91_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61587   GPIO_PINCFG91_PULLCFG91_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61588   GPIO_PINCFG91_PULLCFG91_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61589 } GPIO_PINCFG91_PULLCFG91_Enum;
61590 
61591 /* ==============================================  GPIO PINCFG91 DS91 [10..11]  ============================================== */
61592 typedef enum {                                  /*!< GPIO_PINCFG91_DS91                                                        */
61593   GPIO_PINCFG91_DS91_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61594   GPIO_PINCFG91_DS91_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61595 } GPIO_PINCFG91_DS91_Enum;
61596 
61597 /* =============================================  GPIO PINCFG91 OUTCFG91 [8..9]  ============================================= */
61598 typedef enum {                                  /*!< GPIO_PINCFG91_OUTCFG91                                                    */
61599   GPIO_PINCFG91_OUTCFG91_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61600   GPIO_PINCFG91_OUTCFG91_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61601                                                      and 1 values on pin.                                                      */
61602   GPIO_PINCFG91_OUTCFG91_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61603                                                      low, tristate otherwise.                                                  */
61604   GPIO_PINCFG91_OUTCFG91_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61605                                                      drive 0, 1 of HiZ on pin.                                                 */
61606 } GPIO_PINCFG91_OUTCFG91_Enum;
61607 
61608 /* =============================================  GPIO PINCFG91 IRPTEN91 [6..7]  ============================================= */
61609 typedef enum {                                  /*!< GPIO_PINCFG91_IRPTEN91                                                    */
61610   GPIO_PINCFG91_IRPTEN91_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61611   GPIO_PINCFG91_IRPTEN91_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61612                                                      on this GPIO                                                              */
61613   GPIO_PINCFG91_IRPTEN91_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61614                                                      on this GPIO                                                              */
61615   GPIO_PINCFG91_IRPTEN91_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61616                                                      GPIO                                                                      */
61617 } GPIO_PINCFG91_IRPTEN91_Enum;
61618 
61619 /* =============================================  GPIO PINCFG91 FNCSEL91 [0..3]  ============================================= */
61620 typedef enum {                                  /*!< GPIO_PINCFG91_FNCSEL91                                                    */
61621   GPIO_PINCFG91_FNCSEL91_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61622   GPIO_PINCFG91_FNCSEL91_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61623   GPIO_PINCFG91_FNCSEL91_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61624   GPIO_PINCFG91_FNCSEL91_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61625   GPIO_PINCFG91_FNCSEL91_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61626   GPIO_PINCFG91_FNCSEL91_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61627   GPIO_PINCFG91_FNCSEL91_CT91          = 6,     /*!< CT91 : Timer/Counter input or output; Selection of direction
61628                                                      is done via CTIMER register settings.                                     */
61629   GPIO_PINCFG91_FNCSEL91_NCE91         = 7,     /*!< NCE91 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61630                                                      CE_POLARITY field                                                         */
61631   GPIO_PINCFG91_FNCSEL91_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
61632   GPIO_PINCFG91_FNCSEL91_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
61633   GPIO_PINCFG91_FNCSEL91_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61634   GPIO_PINCFG91_FNCSEL91_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61635   GPIO_PINCFG91_FNCSEL91_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61636   GPIO_PINCFG91_FNCSEL91_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61637   GPIO_PINCFG91_FNCSEL91_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61638   GPIO_PINCFG91_FNCSEL91_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61639 } GPIO_PINCFG91_FNCSEL91_Enum;
61640 
61641 /* =======================================================  PINCFG92  ======================================================== */
61642 /* ============================================  GPIO PINCFG92 NCEPOL92 [22..22]  ============================================ */
61643 typedef enum {                                  /*!< GPIO_PINCFG92_NCEPOL92                                                    */
61644   GPIO_PINCFG92_NCEPOL92_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61645   GPIO_PINCFG92_NCEPOL92_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61646 } GPIO_PINCFG92_NCEPOL92_Enum;
61647 
61648 /* ============================================  GPIO PINCFG92 NCESRC92 [16..21]  ============================================ */
61649 typedef enum {                                  /*!< GPIO_PINCFG92_NCESRC92                                                    */
61650   GPIO_PINCFG92_NCESRC92_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61651   GPIO_PINCFG92_NCESRC92_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61652   GPIO_PINCFG92_NCESRC92_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61653   GPIO_PINCFG92_NCESRC92_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61654   GPIO_PINCFG92_NCESRC92_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61655   GPIO_PINCFG92_NCESRC92_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61656   GPIO_PINCFG92_NCESRC92_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61657   GPIO_PINCFG92_NCESRC92_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61658   GPIO_PINCFG92_NCESRC92_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61659   GPIO_PINCFG92_NCESRC92_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61660   GPIO_PINCFG92_NCESRC92_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61661   GPIO_PINCFG92_NCESRC92_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61662   GPIO_PINCFG92_NCESRC92_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61663   GPIO_PINCFG92_NCESRC92_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61664   GPIO_PINCFG92_NCESRC92_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61665   GPIO_PINCFG92_NCESRC92_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61666   GPIO_PINCFG92_NCESRC92_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61667   GPIO_PINCFG92_NCESRC92_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61668   GPIO_PINCFG92_NCESRC92_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61669   GPIO_PINCFG92_NCESRC92_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61670   GPIO_PINCFG92_NCESRC92_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61671   GPIO_PINCFG92_NCESRC92_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61672   GPIO_PINCFG92_NCESRC92_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61673   GPIO_PINCFG92_NCESRC92_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61674   GPIO_PINCFG92_NCESRC92_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61675   GPIO_PINCFG92_NCESRC92_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61676   GPIO_PINCFG92_NCESRC92_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61677   GPIO_PINCFG92_NCESRC92_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61678   GPIO_PINCFG92_NCESRC92_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61679   GPIO_PINCFG92_NCESRC92_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61680   GPIO_PINCFG92_NCESRC92_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61681   GPIO_PINCFG92_NCESRC92_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61682   GPIO_PINCFG92_NCESRC92_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61683   GPIO_PINCFG92_NCESRC92_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61684   GPIO_PINCFG92_NCESRC92_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61685   GPIO_PINCFG92_NCESRC92_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61686   GPIO_PINCFG92_NCESRC92_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61687   GPIO_PINCFG92_NCESRC92_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61688   GPIO_PINCFG92_NCESRC92_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61689   GPIO_PINCFG92_NCESRC92_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61690   GPIO_PINCFG92_NCESRC92_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61691   GPIO_PINCFG92_NCESRC92_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61692   GPIO_PINCFG92_NCESRC92_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61693 } GPIO_PINCFG92_NCESRC92_Enum;
61694 
61695 /* ===========================================  GPIO PINCFG92 PULLCFG92 [13..15]  ============================================ */
61696 typedef enum {                                  /*!< GPIO_PINCFG92_PULLCFG92                                                   */
61697   GPIO_PINCFG92_PULLCFG92_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61698   GPIO_PINCFG92_PULLCFG92_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61699   GPIO_PINCFG92_PULLCFG92_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61700   GPIO_PINCFG92_PULLCFG92_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61701   GPIO_PINCFG92_PULLCFG92_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61702   GPIO_PINCFG92_PULLCFG92_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61703   GPIO_PINCFG92_PULLCFG92_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61704   GPIO_PINCFG92_PULLCFG92_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61705 } GPIO_PINCFG92_PULLCFG92_Enum;
61706 
61707 /* ==============================================  GPIO PINCFG92 DS92 [10..11]  ============================================== */
61708 typedef enum {                                  /*!< GPIO_PINCFG92_DS92                                                        */
61709   GPIO_PINCFG92_DS92_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61710   GPIO_PINCFG92_DS92_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61711 } GPIO_PINCFG92_DS92_Enum;
61712 
61713 /* =============================================  GPIO PINCFG92 OUTCFG92 [8..9]  ============================================= */
61714 typedef enum {                                  /*!< GPIO_PINCFG92_OUTCFG92                                                    */
61715   GPIO_PINCFG92_OUTCFG92_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61716   GPIO_PINCFG92_OUTCFG92_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61717                                                      and 1 values on pin.                                                      */
61718   GPIO_PINCFG92_OUTCFG92_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61719                                                      low, tristate otherwise.                                                  */
61720   GPIO_PINCFG92_OUTCFG92_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61721                                                      drive 0, 1 of HiZ on pin.                                                 */
61722 } GPIO_PINCFG92_OUTCFG92_Enum;
61723 
61724 /* =============================================  GPIO PINCFG92 IRPTEN92 [6..7]  ============================================= */
61725 typedef enum {                                  /*!< GPIO_PINCFG92_IRPTEN92                                                    */
61726   GPIO_PINCFG92_IRPTEN92_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61727   GPIO_PINCFG92_IRPTEN92_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61728                                                      on this GPIO                                                              */
61729   GPIO_PINCFG92_IRPTEN92_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61730                                                      on this GPIO                                                              */
61731   GPIO_PINCFG92_IRPTEN92_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61732                                                      GPIO                                                                      */
61733 } GPIO_PINCFG92_IRPTEN92_Enum;
61734 
61735 /* =============================================  GPIO PINCFG92 FNCSEL92 [0..3]  ============================================= */
61736 typedef enum {                                  /*!< GPIO_PINCFG92_FNCSEL92                                                    */
61737   GPIO_PINCFG92_FNCSEL92_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61738   GPIO_PINCFG92_FNCSEL92_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61739   GPIO_PINCFG92_FNCSEL92_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61740   GPIO_PINCFG92_FNCSEL92_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61741   GPIO_PINCFG92_FNCSEL92_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61742   GPIO_PINCFG92_FNCSEL92_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61743   GPIO_PINCFG92_FNCSEL92_CT92          = 6,     /*!< CT92 : Timer/Counter input or output; Selection of direction
61744                                                      is done via CTIMER register settings.                                     */
61745   GPIO_PINCFG92_FNCSEL92_NCE92         = 7,     /*!< NCE92 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61746                                                      CE_POLARITY field                                                         */
61747   GPIO_PINCFG92_FNCSEL92_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
61748   GPIO_PINCFG92_FNCSEL92_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
61749   GPIO_PINCFG92_FNCSEL92_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61750   GPIO_PINCFG92_FNCSEL92_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61751   GPIO_PINCFG92_FNCSEL92_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61752   GPIO_PINCFG92_FNCSEL92_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61753   GPIO_PINCFG92_FNCSEL92_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61754   GPIO_PINCFG92_FNCSEL92_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61755 } GPIO_PINCFG92_FNCSEL92_Enum;
61756 
61757 /* =======================================================  PINCFG93  ======================================================== */
61758 /* ============================================  GPIO PINCFG93 NCEPOL93 [22..22]  ============================================ */
61759 typedef enum {                                  /*!< GPIO_PINCFG93_NCEPOL93                                                    */
61760   GPIO_PINCFG93_NCEPOL93_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61761   GPIO_PINCFG93_NCEPOL93_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61762 } GPIO_PINCFG93_NCEPOL93_Enum;
61763 
61764 /* ============================================  GPIO PINCFG93 NCESRC93 [16..21]  ============================================ */
61765 typedef enum {                                  /*!< GPIO_PINCFG93_NCESRC93                                                    */
61766   GPIO_PINCFG93_NCESRC93_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61767   GPIO_PINCFG93_NCESRC93_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61768   GPIO_PINCFG93_NCESRC93_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61769   GPIO_PINCFG93_NCESRC93_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61770   GPIO_PINCFG93_NCESRC93_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61771   GPIO_PINCFG93_NCESRC93_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61772   GPIO_PINCFG93_NCESRC93_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61773   GPIO_PINCFG93_NCESRC93_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61774   GPIO_PINCFG93_NCESRC93_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61775   GPIO_PINCFG93_NCESRC93_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61776   GPIO_PINCFG93_NCESRC93_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61777   GPIO_PINCFG93_NCESRC93_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61778   GPIO_PINCFG93_NCESRC93_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61779   GPIO_PINCFG93_NCESRC93_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61780   GPIO_PINCFG93_NCESRC93_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61781   GPIO_PINCFG93_NCESRC93_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61782   GPIO_PINCFG93_NCESRC93_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61783   GPIO_PINCFG93_NCESRC93_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61784   GPIO_PINCFG93_NCESRC93_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61785   GPIO_PINCFG93_NCESRC93_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61786   GPIO_PINCFG93_NCESRC93_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61787   GPIO_PINCFG93_NCESRC93_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61788   GPIO_PINCFG93_NCESRC93_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61789   GPIO_PINCFG93_NCESRC93_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61790   GPIO_PINCFG93_NCESRC93_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61791   GPIO_PINCFG93_NCESRC93_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61792   GPIO_PINCFG93_NCESRC93_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61793   GPIO_PINCFG93_NCESRC93_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61794   GPIO_PINCFG93_NCESRC93_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61795   GPIO_PINCFG93_NCESRC93_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61796   GPIO_PINCFG93_NCESRC93_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61797   GPIO_PINCFG93_NCESRC93_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61798   GPIO_PINCFG93_NCESRC93_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61799   GPIO_PINCFG93_NCESRC93_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61800   GPIO_PINCFG93_NCESRC93_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61801   GPIO_PINCFG93_NCESRC93_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61802   GPIO_PINCFG93_NCESRC93_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61803   GPIO_PINCFG93_NCESRC93_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61804   GPIO_PINCFG93_NCESRC93_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61805   GPIO_PINCFG93_NCESRC93_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61806   GPIO_PINCFG93_NCESRC93_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61807   GPIO_PINCFG93_NCESRC93_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61808   GPIO_PINCFG93_NCESRC93_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61809 } GPIO_PINCFG93_NCESRC93_Enum;
61810 
61811 /* ===========================================  GPIO PINCFG93 PULLCFG93 [13..15]  ============================================ */
61812 typedef enum {                                  /*!< GPIO_PINCFG93_PULLCFG93                                                   */
61813   GPIO_PINCFG93_PULLCFG93_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61814   GPIO_PINCFG93_PULLCFG93_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61815   GPIO_PINCFG93_PULLCFG93_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61816   GPIO_PINCFG93_PULLCFG93_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61817   GPIO_PINCFG93_PULLCFG93_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61818   GPIO_PINCFG93_PULLCFG93_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61819   GPIO_PINCFG93_PULLCFG93_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61820   GPIO_PINCFG93_PULLCFG93_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61821 } GPIO_PINCFG93_PULLCFG93_Enum;
61822 
61823 /* ==============================================  GPIO PINCFG93 DS93 [10..11]  ============================================== */
61824 typedef enum {                                  /*!< GPIO_PINCFG93_DS93                                                        */
61825   GPIO_PINCFG93_DS93_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61826   GPIO_PINCFG93_DS93_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61827 } GPIO_PINCFG93_DS93_Enum;
61828 
61829 /* =============================================  GPIO PINCFG93 OUTCFG93 [8..9]  ============================================= */
61830 typedef enum {                                  /*!< GPIO_PINCFG93_OUTCFG93                                                    */
61831   GPIO_PINCFG93_OUTCFG93_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61832   GPIO_PINCFG93_OUTCFG93_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61833                                                      and 1 values on pin.                                                      */
61834   GPIO_PINCFG93_OUTCFG93_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61835                                                      low, tristate otherwise.                                                  */
61836   GPIO_PINCFG93_OUTCFG93_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61837                                                      drive 0, 1 of HiZ on pin.                                                 */
61838 } GPIO_PINCFG93_OUTCFG93_Enum;
61839 
61840 /* =============================================  GPIO PINCFG93 IRPTEN93 [6..7]  ============================================= */
61841 typedef enum {                                  /*!< GPIO_PINCFG93_IRPTEN93                                                    */
61842   GPIO_PINCFG93_IRPTEN93_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61843   GPIO_PINCFG93_IRPTEN93_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61844                                                      on this GPIO                                                              */
61845   GPIO_PINCFG93_IRPTEN93_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61846                                                      on this GPIO                                                              */
61847   GPIO_PINCFG93_IRPTEN93_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61848                                                      GPIO                                                                      */
61849 } GPIO_PINCFG93_IRPTEN93_Enum;
61850 
61851 /* =============================================  GPIO PINCFG93 FNCSEL93 [0..3]  ============================================= */
61852 typedef enum {                                  /*!< GPIO_PINCFG93_FNCSEL93                                                    */
61853   GPIO_PINCFG93_FNCSEL93_MSPI2_9       = 0,     /*!< MSPI2_9 : MSPI Master 2 Interface Signal                                  */
61854   GPIO_PINCFG93_FNCSEL93_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61855   GPIO_PINCFG93_FNCSEL93_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61856   GPIO_PINCFG93_FNCSEL93_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61857   GPIO_PINCFG93_FNCSEL93_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61858   GPIO_PINCFG93_FNCSEL93_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61859   GPIO_PINCFG93_FNCSEL93_CT93          = 6,     /*!< CT93 : Timer/Counter input or output; Selection of direction
61860                                                      is done via CTIMER register settings.                                     */
61861   GPIO_PINCFG93_FNCSEL93_NCE93         = 7,     /*!< NCE93 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61862                                                      CE_POLARITY field                                                         */
61863   GPIO_PINCFG93_FNCSEL93_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
61864   GPIO_PINCFG93_FNCSEL93_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
61865   GPIO_PINCFG93_FNCSEL93_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61866   GPIO_PINCFG93_FNCSEL93_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61867   GPIO_PINCFG93_FNCSEL93_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61868   GPIO_PINCFG93_FNCSEL93_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61869   GPIO_PINCFG93_FNCSEL93_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61870   GPIO_PINCFG93_FNCSEL93_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61871 } GPIO_PINCFG93_FNCSEL93_Enum;
61872 
61873 /* =======================================================  PINCFG94  ======================================================== */
61874 /* ============================================  GPIO PINCFG94 NCEPOL94 [22..22]  ============================================ */
61875 typedef enum {                                  /*!< GPIO_PINCFG94_NCEPOL94                                                    */
61876   GPIO_PINCFG94_NCEPOL94_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61877   GPIO_PINCFG94_NCEPOL94_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61878 } GPIO_PINCFG94_NCEPOL94_Enum;
61879 
61880 /* ============================================  GPIO PINCFG94 NCESRC94 [16..21]  ============================================ */
61881 typedef enum {                                  /*!< GPIO_PINCFG94_NCESRC94                                                    */
61882   GPIO_PINCFG94_NCESRC94_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61883   GPIO_PINCFG94_NCESRC94_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
61884   GPIO_PINCFG94_NCESRC94_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
61885   GPIO_PINCFG94_NCESRC94_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
61886   GPIO_PINCFG94_NCESRC94_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
61887   GPIO_PINCFG94_NCESRC94_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
61888   GPIO_PINCFG94_NCESRC94_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
61889   GPIO_PINCFG94_NCESRC94_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
61890   GPIO_PINCFG94_NCESRC94_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
61891   GPIO_PINCFG94_NCESRC94_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
61892   GPIO_PINCFG94_NCESRC94_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
61893   GPIO_PINCFG94_NCESRC94_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
61894   GPIO_PINCFG94_NCESRC94_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
61895   GPIO_PINCFG94_NCESRC94_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
61896   GPIO_PINCFG94_NCESRC94_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
61897   GPIO_PINCFG94_NCESRC94_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
61898   GPIO_PINCFG94_NCESRC94_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
61899   GPIO_PINCFG94_NCESRC94_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
61900   GPIO_PINCFG94_NCESRC94_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
61901   GPIO_PINCFG94_NCESRC94_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
61902   GPIO_PINCFG94_NCESRC94_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
61903   GPIO_PINCFG94_NCESRC94_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
61904   GPIO_PINCFG94_NCESRC94_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
61905   GPIO_PINCFG94_NCESRC94_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
61906   GPIO_PINCFG94_NCESRC94_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
61907   GPIO_PINCFG94_NCESRC94_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
61908   GPIO_PINCFG94_NCESRC94_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
61909   GPIO_PINCFG94_NCESRC94_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
61910   GPIO_PINCFG94_NCESRC94_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
61911   GPIO_PINCFG94_NCESRC94_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
61912   GPIO_PINCFG94_NCESRC94_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
61913   GPIO_PINCFG94_NCESRC94_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
61914   GPIO_PINCFG94_NCESRC94_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
61915   GPIO_PINCFG94_NCESRC94_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
61916   GPIO_PINCFG94_NCESRC94_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
61917   GPIO_PINCFG94_NCESRC94_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
61918   GPIO_PINCFG94_NCESRC94_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
61919   GPIO_PINCFG94_NCESRC94_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
61920   GPIO_PINCFG94_NCESRC94_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
61921   GPIO_PINCFG94_NCESRC94_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
61922   GPIO_PINCFG94_NCESRC94_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
61923   GPIO_PINCFG94_NCESRC94_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
61924   GPIO_PINCFG94_NCESRC94_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
61925 } GPIO_PINCFG94_NCESRC94_Enum;
61926 
61927 /* ===========================================  GPIO PINCFG94 PULLCFG94 [13..15]  ============================================ */
61928 typedef enum {                                  /*!< GPIO_PINCFG94_PULLCFG94                                                   */
61929   GPIO_PINCFG94_PULLCFG94_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
61930   GPIO_PINCFG94_PULLCFG94_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
61931   GPIO_PINCFG94_PULLCFG94_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
61932   GPIO_PINCFG94_PULLCFG94_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
61933   GPIO_PINCFG94_PULLCFG94_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
61934   GPIO_PINCFG94_PULLCFG94_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
61935   GPIO_PINCFG94_PULLCFG94_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
61936   GPIO_PINCFG94_PULLCFG94_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
61937 } GPIO_PINCFG94_PULLCFG94_Enum;
61938 
61939 /* ==============================================  GPIO PINCFG94 DS94 [10..11]  ============================================== */
61940 typedef enum {                                  /*!< GPIO_PINCFG94_DS94                                                        */
61941   GPIO_PINCFG94_DS94_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
61942   GPIO_PINCFG94_DS94_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
61943 } GPIO_PINCFG94_DS94_Enum;
61944 
61945 /* =============================================  GPIO PINCFG94 OUTCFG94 [8..9]  ============================================= */
61946 typedef enum {                                  /*!< GPIO_PINCFG94_OUTCFG94                                                    */
61947   GPIO_PINCFG94_OUTCFG94_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
61948   GPIO_PINCFG94_OUTCFG94_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
61949                                                      and 1 values on pin.                                                      */
61950   GPIO_PINCFG94_OUTCFG94_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
61951                                                      low, tristate otherwise.                                                  */
61952   GPIO_PINCFG94_OUTCFG94_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
61953                                                      drive 0, 1 of HiZ on pin.                                                 */
61954 } GPIO_PINCFG94_OUTCFG94_Enum;
61955 
61956 /* =============================================  GPIO PINCFG94 IRPTEN94 [6..7]  ============================================= */
61957 typedef enum {                                  /*!< GPIO_PINCFG94_IRPTEN94                                                    */
61958   GPIO_PINCFG94_IRPTEN94_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
61959   GPIO_PINCFG94_IRPTEN94_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
61960                                                      on this GPIO                                                              */
61961   GPIO_PINCFG94_IRPTEN94_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
61962                                                      on this GPIO                                                              */
61963   GPIO_PINCFG94_IRPTEN94_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
61964                                                      GPIO                                                                      */
61965 } GPIO_PINCFG94_IRPTEN94_Enum;
61966 
61967 /* =============================================  GPIO PINCFG94 FNCSEL94 [0..3]  ============================================= */
61968 typedef enum {                                  /*!< GPIO_PINCFG94_FNCSEL94                                                    */
61969   GPIO_PINCFG94_FNCSEL94_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
61970   GPIO_PINCFG94_FNCSEL94_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
61971   GPIO_PINCFG94_FNCSEL94_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
61972   GPIO_PINCFG94_FNCSEL94_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
61973   GPIO_PINCFG94_FNCSEL94_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
61974   GPIO_PINCFG94_FNCSEL94_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
61975   GPIO_PINCFG94_FNCSEL94_CT94          = 6,     /*!< CT94 : Timer/Counter input or output; Selection of direction
61976                                                      is done via CTIMER register settings.                                     */
61977   GPIO_PINCFG94_FNCSEL94_NCE94         = 7,     /*!< NCE94 : IOMSTR/MSPI N Chip Select. Polarity is determined by
61978                                                      CE_POLARITY field                                                         */
61979   GPIO_PINCFG94_FNCSEL94_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
61980   GPIO_PINCFG94_FNCSEL94_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
61981   GPIO_PINCFG94_FNCSEL94_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
61982   GPIO_PINCFG94_FNCSEL94_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
61983   GPIO_PINCFG94_FNCSEL94_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
61984   GPIO_PINCFG94_FNCSEL94_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
61985   GPIO_PINCFG94_FNCSEL94_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
61986   GPIO_PINCFG94_FNCSEL94_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
61987 } GPIO_PINCFG94_FNCSEL94_Enum;
61988 
61989 /* =======================================================  PINCFG95  ======================================================== */
61990 /* ============================================  GPIO PINCFG95 NCEPOL95 [22..22]  ============================================ */
61991 typedef enum {                                  /*!< GPIO_PINCFG95_NCEPOL95                                                    */
61992   GPIO_PINCFG95_NCEPOL95_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
61993   GPIO_PINCFG95_NCEPOL95_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
61994 } GPIO_PINCFG95_NCEPOL95_Enum;
61995 
61996 /* ============================================  GPIO PINCFG95 NCESRC95 [16..21]  ============================================ */
61997 typedef enum {                                  /*!< GPIO_PINCFG95_NCESRC95                                                    */
61998   GPIO_PINCFG95_NCESRC95_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
61999   GPIO_PINCFG95_NCESRC95_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
62000   GPIO_PINCFG95_NCESRC95_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
62001   GPIO_PINCFG95_NCESRC95_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
62002   GPIO_PINCFG95_NCESRC95_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
62003   GPIO_PINCFG95_NCESRC95_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
62004   GPIO_PINCFG95_NCESRC95_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
62005   GPIO_PINCFG95_NCESRC95_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
62006   GPIO_PINCFG95_NCESRC95_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
62007   GPIO_PINCFG95_NCESRC95_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
62008   GPIO_PINCFG95_NCESRC95_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
62009   GPIO_PINCFG95_NCESRC95_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
62010   GPIO_PINCFG95_NCESRC95_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
62011   GPIO_PINCFG95_NCESRC95_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
62012   GPIO_PINCFG95_NCESRC95_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
62013   GPIO_PINCFG95_NCESRC95_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
62014   GPIO_PINCFG95_NCESRC95_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
62015   GPIO_PINCFG95_NCESRC95_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
62016   GPIO_PINCFG95_NCESRC95_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
62017   GPIO_PINCFG95_NCESRC95_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
62018   GPIO_PINCFG95_NCESRC95_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
62019   GPIO_PINCFG95_NCESRC95_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
62020   GPIO_PINCFG95_NCESRC95_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
62021   GPIO_PINCFG95_NCESRC95_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
62022   GPIO_PINCFG95_NCESRC95_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
62023   GPIO_PINCFG95_NCESRC95_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
62024   GPIO_PINCFG95_NCESRC95_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
62025   GPIO_PINCFG95_NCESRC95_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
62026   GPIO_PINCFG95_NCESRC95_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
62027   GPIO_PINCFG95_NCESRC95_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
62028   GPIO_PINCFG95_NCESRC95_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
62029   GPIO_PINCFG95_NCESRC95_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
62030   GPIO_PINCFG95_NCESRC95_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
62031   GPIO_PINCFG95_NCESRC95_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
62032   GPIO_PINCFG95_NCESRC95_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
62033   GPIO_PINCFG95_NCESRC95_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
62034   GPIO_PINCFG95_NCESRC95_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
62035   GPIO_PINCFG95_NCESRC95_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62036   GPIO_PINCFG95_NCESRC95_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62037   GPIO_PINCFG95_NCESRC95_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62038   GPIO_PINCFG95_NCESRC95_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62039   GPIO_PINCFG95_NCESRC95_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62040   GPIO_PINCFG95_NCESRC95_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
62041 } GPIO_PINCFG95_NCESRC95_Enum;
62042 
62043 /* ===========================================  GPIO PINCFG95 PULLCFG95 [13..15]  ============================================ */
62044 typedef enum {                                  /*!< GPIO_PINCFG95_PULLCFG95                                                   */
62045   GPIO_PINCFG95_PULLCFG95_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62046   GPIO_PINCFG95_PULLCFG95_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62047   GPIO_PINCFG95_PULLCFG95_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62048   GPIO_PINCFG95_PULLCFG95_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62049   GPIO_PINCFG95_PULLCFG95_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
62050   GPIO_PINCFG95_PULLCFG95_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
62051   GPIO_PINCFG95_PULLCFG95_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
62052   GPIO_PINCFG95_PULLCFG95_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
62053 } GPIO_PINCFG95_PULLCFG95_Enum;
62054 
62055 /* ==============================================  GPIO PINCFG95 DS95 [10..11]  ============================================== */
62056 typedef enum {                                  /*!< GPIO_PINCFG95_DS95                                                        */
62057   GPIO_PINCFG95_DS95_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62058   GPIO_PINCFG95_DS95_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62059 } GPIO_PINCFG95_DS95_Enum;
62060 
62061 /* =============================================  GPIO PINCFG95 OUTCFG95 [8..9]  ============================================= */
62062 typedef enum {                                  /*!< GPIO_PINCFG95_OUTCFG95                                                    */
62063   GPIO_PINCFG95_OUTCFG95_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
62064   GPIO_PINCFG95_OUTCFG95_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62065                                                      and 1 values on pin.                                                      */
62066   GPIO_PINCFG95_OUTCFG95_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62067                                                      low, tristate otherwise.                                                  */
62068   GPIO_PINCFG95_OUTCFG95_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62069                                                      drive 0, 1 of HiZ on pin.                                                 */
62070 } GPIO_PINCFG95_OUTCFG95_Enum;
62071 
62072 /* =============================================  GPIO PINCFG95 IRPTEN95 [6..7]  ============================================= */
62073 typedef enum {                                  /*!< GPIO_PINCFG95_IRPTEN95                                                    */
62074   GPIO_PINCFG95_IRPTEN95_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62075   GPIO_PINCFG95_IRPTEN95_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62076                                                      on this GPIO                                                              */
62077   GPIO_PINCFG95_IRPTEN95_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62078                                                      on this GPIO                                                              */
62079   GPIO_PINCFG95_IRPTEN95_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62080                                                      GPIO                                                                      */
62081 } GPIO_PINCFG95_IRPTEN95_Enum;
62082 
62083 /* =============================================  GPIO PINCFG95 FNCSEL95 [0..3]  ============================================= */
62084 typedef enum {                                  /*!< GPIO_PINCFG95_FNCSEL95                                                    */
62085   GPIO_PINCFG95_FNCSEL95_MSPI1_0       = 0,     /*!< MSPI1_0 : MSPI Master 1 Interface Signal                                  */
62086   GPIO_PINCFG95_FNCSEL95_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62087   GPIO_PINCFG95_FNCSEL95_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62088   GPIO_PINCFG95_FNCSEL95_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
62089   GPIO_PINCFG95_FNCSEL95_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62090   GPIO_PINCFG95_FNCSEL95_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62091   GPIO_PINCFG95_FNCSEL95_CT95          = 6,     /*!< CT95 : Timer/Counter input or output; Selection of direction
62092                                                      is done via CTIMER register settings.                                     */
62093   GPIO_PINCFG95_FNCSEL95_NCE95         = 7,     /*!< NCE95 : IOMSTR/MSPI N Chip Select. Polarity is determined by
62094                                                      CE_POLARITY field                                                         */
62095   GPIO_PINCFG95_FNCSEL95_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
62096   GPIO_PINCFG95_FNCSEL95_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62097   GPIO_PINCFG95_FNCSEL95_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62098   GPIO_PINCFG95_FNCSEL95_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
62099   GPIO_PINCFG95_FNCSEL95_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62100   GPIO_PINCFG95_FNCSEL95_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62101   GPIO_PINCFG95_FNCSEL95_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62102   GPIO_PINCFG95_FNCSEL95_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62103 } GPIO_PINCFG95_FNCSEL95_Enum;
62104 
62105 /* =======================================================  PINCFG96  ======================================================== */
62106 /* ============================================  GPIO PINCFG96 NCEPOL96 [22..22]  ============================================ */
62107 typedef enum {                                  /*!< GPIO_PINCFG96_NCEPOL96                                                    */
62108   GPIO_PINCFG96_NCEPOL96_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
62109   GPIO_PINCFG96_NCEPOL96_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
62110 } GPIO_PINCFG96_NCEPOL96_Enum;
62111 
62112 /* ============================================  GPIO PINCFG96 NCESRC96 [16..21]  ============================================ */
62113 typedef enum {                                  /*!< GPIO_PINCFG96_NCESRC96                                                    */
62114   GPIO_PINCFG96_NCESRC96_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
62115   GPIO_PINCFG96_NCESRC96_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
62116   GPIO_PINCFG96_NCESRC96_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
62117   GPIO_PINCFG96_NCESRC96_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
62118   GPIO_PINCFG96_NCESRC96_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
62119   GPIO_PINCFG96_NCESRC96_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
62120   GPIO_PINCFG96_NCESRC96_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
62121   GPIO_PINCFG96_NCESRC96_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
62122   GPIO_PINCFG96_NCESRC96_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
62123   GPIO_PINCFG96_NCESRC96_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
62124   GPIO_PINCFG96_NCESRC96_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
62125   GPIO_PINCFG96_NCESRC96_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
62126   GPIO_PINCFG96_NCESRC96_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
62127   GPIO_PINCFG96_NCESRC96_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
62128   GPIO_PINCFG96_NCESRC96_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
62129   GPIO_PINCFG96_NCESRC96_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
62130   GPIO_PINCFG96_NCESRC96_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
62131   GPIO_PINCFG96_NCESRC96_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
62132   GPIO_PINCFG96_NCESRC96_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
62133   GPIO_PINCFG96_NCESRC96_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
62134   GPIO_PINCFG96_NCESRC96_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
62135   GPIO_PINCFG96_NCESRC96_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
62136   GPIO_PINCFG96_NCESRC96_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
62137   GPIO_PINCFG96_NCESRC96_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
62138   GPIO_PINCFG96_NCESRC96_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
62139   GPIO_PINCFG96_NCESRC96_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
62140   GPIO_PINCFG96_NCESRC96_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
62141   GPIO_PINCFG96_NCESRC96_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
62142   GPIO_PINCFG96_NCESRC96_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
62143   GPIO_PINCFG96_NCESRC96_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
62144   GPIO_PINCFG96_NCESRC96_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
62145   GPIO_PINCFG96_NCESRC96_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
62146   GPIO_PINCFG96_NCESRC96_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
62147   GPIO_PINCFG96_NCESRC96_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
62148   GPIO_PINCFG96_NCESRC96_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
62149   GPIO_PINCFG96_NCESRC96_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
62150   GPIO_PINCFG96_NCESRC96_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
62151   GPIO_PINCFG96_NCESRC96_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62152   GPIO_PINCFG96_NCESRC96_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62153   GPIO_PINCFG96_NCESRC96_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62154   GPIO_PINCFG96_NCESRC96_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62155   GPIO_PINCFG96_NCESRC96_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62156   GPIO_PINCFG96_NCESRC96_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
62157 } GPIO_PINCFG96_NCESRC96_Enum;
62158 
62159 /* ===========================================  GPIO PINCFG96 PULLCFG96 [13..15]  ============================================ */
62160 typedef enum {                                  /*!< GPIO_PINCFG96_PULLCFG96                                                   */
62161   GPIO_PINCFG96_PULLCFG96_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62162   GPIO_PINCFG96_PULLCFG96_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62163   GPIO_PINCFG96_PULLCFG96_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62164   GPIO_PINCFG96_PULLCFG96_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62165   GPIO_PINCFG96_PULLCFG96_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
62166   GPIO_PINCFG96_PULLCFG96_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
62167   GPIO_PINCFG96_PULLCFG96_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
62168   GPIO_PINCFG96_PULLCFG96_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
62169 } GPIO_PINCFG96_PULLCFG96_Enum;
62170 
62171 /* ==============================================  GPIO PINCFG96 DS96 [10..11]  ============================================== */
62172 typedef enum {                                  /*!< GPIO_PINCFG96_DS96                                                        */
62173   GPIO_PINCFG96_DS96_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62174   GPIO_PINCFG96_DS96_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62175 } GPIO_PINCFG96_DS96_Enum;
62176 
62177 /* =============================================  GPIO PINCFG96 OUTCFG96 [8..9]  ============================================= */
62178 typedef enum {                                  /*!< GPIO_PINCFG96_OUTCFG96                                                    */
62179   GPIO_PINCFG96_OUTCFG96_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
62180   GPIO_PINCFG96_OUTCFG96_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62181                                                      and 1 values on pin.                                                      */
62182   GPIO_PINCFG96_OUTCFG96_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62183                                                      low, tristate otherwise.                                                  */
62184   GPIO_PINCFG96_OUTCFG96_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62185                                                      drive 0, 1 of HiZ on pin.                                                 */
62186 } GPIO_PINCFG96_OUTCFG96_Enum;
62187 
62188 /* =============================================  GPIO PINCFG96 IRPTEN96 [6..7]  ============================================= */
62189 typedef enum {                                  /*!< GPIO_PINCFG96_IRPTEN96                                                    */
62190   GPIO_PINCFG96_IRPTEN96_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62191   GPIO_PINCFG96_IRPTEN96_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62192                                                      on this GPIO                                                              */
62193   GPIO_PINCFG96_IRPTEN96_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62194                                                      on this GPIO                                                              */
62195   GPIO_PINCFG96_IRPTEN96_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62196                                                      GPIO                                                                      */
62197 } GPIO_PINCFG96_IRPTEN96_Enum;
62198 
62199 /* =============================================  GPIO PINCFG96 FNCSEL96 [0..3]  ============================================= */
62200 typedef enum {                                  /*!< GPIO_PINCFG96_FNCSEL96                                                    */
62201   GPIO_PINCFG96_FNCSEL96_MSPI1_1       = 0,     /*!< MSPI1_1 : MSPI Master 1 Interface Signal                                  */
62202   GPIO_PINCFG96_FNCSEL96_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62203   GPIO_PINCFG96_FNCSEL96_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62204   GPIO_PINCFG96_FNCSEL96_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
62205   GPIO_PINCFG96_FNCSEL96_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62206   GPIO_PINCFG96_FNCSEL96_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62207   GPIO_PINCFG96_FNCSEL96_CT96          = 6,     /*!< CT96 : Timer/Counter input or output; Selection of direction
62208                                                      is done via CTIMER register settings.                                     */
62209   GPIO_PINCFG96_FNCSEL96_NCE96         = 7,     /*!< NCE96 : IOMSTR/MSPI N Chip Select. Polarity is determined by
62210                                                      CE_POLARITY field                                                         */
62211   GPIO_PINCFG96_FNCSEL96_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
62212   GPIO_PINCFG96_FNCSEL96_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62213   GPIO_PINCFG96_FNCSEL96_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62214   GPIO_PINCFG96_FNCSEL96_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
62215   GPIO_PINCFG96_FNCSEL96_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62216   GPIO_PINCFG96_FNCSEL96_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62217   GPIO_PINCFG96_FNCSEL96_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62218   GPIO_PINCFG96_FNCSEL96_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62219 } GPIO_PINCFG96_FNCSEL96_Enum;
62220 
62221 /* =======================================================  PINCFG97  ======================================================== */
62222 /* ============================================  GPIO PINCFG97 NCEPOL97 [22..22]  ============================================ */
62223 typedef enum {                                  /*!< GPIO_PINCFG97_NCEPOL97                                                    */
62224   GPIO_PINCFG97_NCEPOL97_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
62225   GPIO_PINCFG97_NCEPOL97_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
62226 } GPIO_PINCFG97_NCEPOL97_Enum;
62227 
62228 /* ============================================  GPIO PINCFG97 NCESRC97 [16..21]  ============================================ */
62229 typedef enum {                                  /*!< GPIO_PINCFG97_NCESRC97                                                    */
62230   GPIO_PINCFG97_NCESRC97_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
62231   GPIO_PINCFG97_NCESRC97_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
62232   GPIO_PINCFG97_NCESRC97_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
62233   GPIO_PINCFG97_NCESRC97_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
62234   GPIO_PINCFG97_NCESRC97_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
62235   GPIO_PINCFG97_NCESRC97_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
62236   GPIO_PINCFG97_NCESRC97_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
62237   GPIO_PINCFG97_NCESRC97_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
62238   GPIO_PINCFG97_NCESRC97_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
62239   GPIO_PINCFG97_NCESRC97_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
62240   GPIO_PINCFG97_NCESRC97_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
62241   GPIO_PINCFG97_NCESRC97_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
62242   GPIO_PINCFG97_NCESRC97_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
62243   GPIO_PINCFG97_NCESRC97_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
62244   GPIO_PINCFG97_NCESRC97_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
62245   GPIO_PINCFG97_NCESRC97_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
62246   GPIO_PINCFG97_NCESRC97_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
62247   GPIO_PINCFG97_NCESRC97_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
62248   GPIO_PINCFG97_NCESRC97_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
62249   GPIO_PINCFG97_NCESRC97_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
62250   GPIO_PINCFG97_NCESRC97_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
62251   GPIO_PINCFG97_NCESRC97_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
62252   GPIO_PINCFG97_NCESRC97_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
62253   GPIO_PINCFG97_NCESRC97_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
62254   GPIO_PINCFG97_NCESRC97_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
62255   GPIO_PINCFG97_NCESRC97_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
62256   GPIO_PINCFG97_NCESRC97_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
62257   GPIO_PINCFG97_NCESRC97_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
62258   GPIO_PINCFG97_NCESRC97_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
62259   GPIO_PINCFG97_NCESRC97_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
62260   GPIO_PINCFG97_NCESRC97_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
62261   GPIO_PINCFG97_NCESRC97_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
62262   GPIO_PINCFG97_NCESRC97_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
62263   GPIO_PINCFG97_NCESRC97_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
62264   GPIO_PINCFG97_NCESRC97_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
62265   GPIO_PINCFG97_NCESRC97_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
62266   GPIO_PINCFG97_NCESRC97_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
62267   GPIO_PINCFG97_NCESRC97_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62268   GPIO_PINCFG97_NCESRC97_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62269   GPIO_PINCFG97_NCESRC97_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62270   GPIO_PINCFG97_NCESRC97_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62271   GPIO_PINCFG97_NCESRC97_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62272   GPIO_PINCFG97_NCESRC97_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
62273 } GPIO_PINCFG97_NCESRC97_Enum;
62274 
62275 /* ===========================================  GPIO PINCFG97 PULLCFG97 [13..15]  ============================================ */
62276 typedef enum {                                  /*!< GPIO_PINCFG97_PULLCFG97                                                   */
62277   GPIO_PINCFG97_PULLCFG97_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62278   GPIO_PINCFG97_PULLCFG97_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62279   GPIO_PINCFG97_PULLCFG97_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62280   GPIO_PINCFG97_PULLCFG97_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62281   GPIO_PINCFG97_PULLCFG97_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
62282   GPIO_PINCFG97_PULLCFG97_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
62283   GPIO_PINCFG97_PULLCFG97_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
62284   GPIO_PINCFG97_PULLCFG97_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
62285 } GPIO_PINCFG97_PULLCFG97_Enum;
62286 
62287 /* ==============================================  GPIO PINCFG97 DS97 [10..11]  ============================================== */
62288 typedef enum {                                  /*!< GPIO_PINCFG97_DS97                                                        */
62289   GPIO_PINCFG97_DS97_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62290   GPIO_PINCFG97_DS97_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62291 } GPIO_PINCFG97_DS97_Enum;
62292 
62293 /* =============================================  GPIO PINCFG97 OUTCFG97 [8..9]  ============================================= */
62294 typedef enum {                                  /*!< GPIO_PINCFG97_OUTCFG97                                                    */
62295   GPIO_PINCFG97_OUTCFG97_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
62296   GPIO_PINCFG97_OUTCFG97_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62297                                                      and 1 values on pin.                                                      */
62298   GPIO_PINCFG97_OUTCFG97_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62299                                                      low, tristate otherwise.                                                  */
62300   GPIO_PINCFG97_OUTCFG97_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62301                                                      drive 0, 1 of HiZ on pin.                                                 */
62302 } GPIO_PINCFG97_OUTCFG97_Enum;
62303 
62304 /* =============================================  GPIO PINCFG97 IRPTEN97 [6..7]  ============================================= */
62305 typedef enum {                                  /*!< GPIO_PINCFG97_IRPTEN97                                                    */
62306   GPIO_PINCFG97_IRPTEN97_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62307   GPIO_PINCFG97_IRPTEN97_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62308                                                      on this GPIO                                                              */
62309   GPIO_PINCFG97_IRPTEN97_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62310                                                      on this GPIO                                                              */
62311   GPIO_PINCFG97_IRPTEN97_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62312                                                      GPIO                                                                      */
62313 } GPIO_PINCFG97_IRPTEN97_Enum;
62314 
62315 /* =============================================  GPIO PINCFG97 FNCSEL97 [0..3]  ============================================= */
62316 typedef enum {                                  /*!< GPIO_PINCFG97_FNCSEL97                                                    */
62317   GPIO_PINCFG97_FNCSEL97_MSPI1_2       = 0,     /*!< MSPI1_2 : MSPI Master 1 Interface Signal                                  */
62318   GPIO_PINCFG97_FNCSEL97_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62319   GPIO_PINCFG97_FNCSEL97_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62320   GPIO_PINCFG97_FNCSEL97_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
62321   GPIO_PINCFG97_FNCSEL97_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62322   GPIO_PINCFG97_FNCSEL97_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62323   GPIO_PINCFG97_FNCSEL97_CT97          = 6,     /*!< CT97 : Timer/Counter input or output; Selection of direction
62324                                                      is done via CTIMER register settings.                                     */
62325   GPIO_PINCFG97_FNCSEL97_NCE97         = 7,     /*!< NCE97 : IOMSTR/MSPI N Chip Select. Polarity is determined by
62326                                                      CE_POLARITY field                                                         */
62327   GPIO_PINCFG97_FNCSEL97_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
62328   GPIO_PINCFG97_FNCSEL97_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62329   GPIO_PINCFG97_FNCSEL97_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62330   GPIO_PINCFG97_FNCSEL97_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
62331   GPIO_PINCFG97_FNCSEL97_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62332   GPIO_PINCFG97_FNCSEL97_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62333   GPIO_PINCFG97_FNCSEL97_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62334   GPIO_PINCFG97_FNCSEL97_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62335 } GPIO_PINCFG97_FNCSEL97_Enum;
62336 
62337 /* =======================================================  PINCFG98  ======================================================== */
62338 /* ============================================  GPIO PINCFG98 NCEPOL98 [22..22]  ============================================ */
62339 typedef enum {                                  /*!< GPIO_PINCFG98_NCEPOL98                                                    */
62340   GPIO_PINCFG98_NCEPOL98_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
62341   GPIO_PINCFG98_NCEPOL98_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
62342 } GPIO_PINCFG98_NCEPOL98_Enum;
62343 
62344 /* ============================================  GPIO PINCFG98 NCESRC98 [16..21]  ============================================ */
62345 typedef enum {                                  /*!< GPIO_PINCFG98_NCESRC98                                                    */
62346   GPIO_PINCFG98_NCESRC98_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
62347   GPIO_PINCFG98_NCESRC98_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
62348   GPIO_PINCFG98_NCESRC98_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
62349   GPIO_PINCFG98_NCESRC98_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
62350   GPIO_PINCFG98_NCESRC98_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
62351   GPIO_PINCFG98_NCESRC98_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
62352   GPIO_PINCFG98_NCESRC98_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
62353   GPIO_PINCFG98_NCESRC98_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
62354   GPIO_PINCFG98_NCESRC98_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
62355   GPIO_PINCFG98_NCESRC98_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
62356   GPIO_PINCFG98_NCESRC98_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
62357   GPIO_PINCFG98_NCESRC98_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
62358   GPIO_PINCFG98_NCESRC98_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
62359   GPIO_PINCFG98_NCESRC98_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
62360   GPIO_PINCFG98_NCESRC98_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
62361   GPIO_PINCFG98_NCESRC98_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
62362   GPIO_PINCFG98_NCESRC98_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
62363   GPIO_PINCFG98_NCESRC98_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
62364   GPIO_PINCFG98_NCESRC98_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
62365   GPIO_PINCFG98_NCESRC98_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
62366   GPIO_PINCFG98_NCESRC98_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
62367   GPIO_PINCFG98_NCESRC98_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
62368   GPIO_PINCFG98_NCESRC98_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
62369   GPIO_PINCFG98_NCESRC98_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
62370   GPIO_PINCFG98_NCESRC98_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
62371   GPIO_PINCFG98_NCESRC98_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
62372   GPIO_PINCFG98_NCESRC98_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
62373   GPIO_PINCFG98_NCESRC98_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
62374   GPIO_PINCFG98_NCESRC98_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
62375   GPIO_PINCFG98_NCESRC98_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
62376   GPIO_PINCFG98_NCESRC98_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
62377   GPIO_PINCFG98_NCESRC98_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
62378   GPIO_PINCFG98_NCESRC98_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
62379   GPIO_PINCFG98_NCESRC98_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
62380   GPIO_PINCFG98_NCESRC98_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
62381   GPIO_PINCFG98_NCESRC98_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
62382   GPIO_PINCFG98_NCESRC98_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
62383   GPIO_PINCFG98_NCESRC98_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62384   GPIO_PINCFG98_NCESRC98_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62385   GPIO_PINCFG98_NCESRC98_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62386   GPIO_PINCFG98_NCESRC98_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62387   GPIO_PINCFG98_NCESRC98_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62388   GPIO_PINCFG98_NCESRC98_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
62389 } GPIO_PINCFG98_NCESRC98_Enum;
62390 
62391 /* ===========================================  GPIO PINCFG98 PULLCFG98 [13..15]  ============================================ */
62392 typedef enum {                                  /*!< GPIO_PINCFG98_PULLCFG98                                                   */
62393   GPIO_PINCFG98_PULLCFG98_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62394   GPIO_PINCFG98_PULLCFG98_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62395   GPIO_PINCFG98_PULLCFG98_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62396   GPIO_PINCFG98_PULLCFG98_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62397   GPIO_PINCFG98_PULLCFG98_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
62398   GPIO_PINCFG98_PULLCFG98_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
62399   GPIO_PINCFG98_PULLCFG98_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
62400   GPIO_PINCFG98_PULLCFG98_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
62401 } GPIO_PINCFG98_PULLCFG98_Enum;
62402 
62403 /* ==============================================  GPIO PINCFG98 DS98 [10..11]  ============================================== */
62404 typedef enum {                                  /*!< GPIO_PINCFG98_DS98                                                        */
62405   GPIO_PINCFG98_DS98_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62406   GPIO_PINCFG98_DS98_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62407 } GPIO_PINCFG98_DS98_Enum;
62408 
62409 /* =============================================  GPIO PINCFG98 OUTCFG98 [8..9]  ============================================= */
62410 typedef enum {                                  /*!< GPIO_PINCFG98_OUTCFG98                                                    */
62411   GPIO_PINCFG98_OUTCFG98_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
62412   GPIO_PINCFG98_OUTCFG98_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62413                                                      and 1 values on pin.                                                      */
62414   GPIO_PINCFG98_OUTCFG98_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62415                                                      low, tristate otherwise.                                                  */
62416   GPIO_PINCFG98_OUTCFG98_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62417                                                      drive 0, 1 of HiZ on pin.                                                 */
62418 } GPIO_PINCFG98_OUTCFG98_Enum;
62419 
62420 /* =============================================  GPIO PINCFG98 IRPTEN98 [6..7]  ============================================= */
62421 typedef enum {                                  /*!< GPIO_PINCFG98_IRPTEN98                                                    */
62422   GPIO_PINCFG98_IRPTEN98_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62423   GPIO_PINCFG98_IRPTEN98_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62424                                                      on this GPIO                                                              */
62425   GPIO_PINCFG98_IRPTEN98_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62426                                                      on this GPIO                                                              */
62427   GPIO_PINCFG98_IRPTEN98_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62428                                                      GPIO                                                                      */
62429 } GPIO_PINCFG98_IRPTEN98_Enum;
62430 
62431 /* =============================================  GPIO PINCFG98 FNCSEL98 [0..3]  ============================================= */
62432 typedef enum {                                  /*!< GPIO_PINCFG98_FNCSEL98                                                    */
62433   GPIO_PINCFG98_FNCSEL98_MSPI1_3       = 0,     /*!< MSPI1_3 : MSPI Master 1 Interface Signal                                  */
62434   GPIO_PINCFG98_FNCSEL98_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62435   GPIO_PINCFG98_FNCSEL98_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62436   GPIO_PINCFG98_FNCSEL98_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
62437   GPIO_PINCFG98_FNCSEL98_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62438   GPIO_PINCFG98_FNCSEL98_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62439   GPIO_PINCFG98_FNCSEL98_CT98          = 6,     /*!< CT98 : Timer/Counter input or output; Selection of direction
62440                                                      is done via CTIMER register settings.                                     */
62441   GPIO_PINCFG98_FNCSEL98_NCE98         = 7,     /*!< NCE98 : IOMSTR/MSPI N Chip Select. Polarity is determined by
62442                                                      CE_POLARITY field                                                         */
62443   GPIO_PINCFG98_FNCSEL98_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
62444   GPIO_PINCFG98_FNCSEL98_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62445   GPIO_PINCFG98_FNCSEL98_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62446   GPIO_PINCFG98_FNCSEL98_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
62447   GPIO_PINCFG98_FNCSEL98_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62448   GPIO_PINCFG98_FNCSEL98_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62449   GPIO_PINCFG98_FNCSEL98_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62450   GPIO_PINCFG98_FNCSEL98_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62451 } GPIO_PINCFG98_FNCSEL98_Enum;
62452 
62453 /* =======================================================  PINCFG99  ======================================================== */
62454 /* ============================================  GPIO PINCFG99 NCEPOL99 [22..22]  ============================================ */
62455 typedef enum {                                  /*!< GPIO_PINCFG99_NCEPOL99                                                    */
62456   GPIO_PINCFG99_NCEPOL99_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
62457   GPIO_PINCFG99_NCEPOL99_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
62458 } GPIO_PINCFG99_NCEPOL99_Enum;
62459 
62460 /* ============================================  GPIO PINCFG99 NCESRC99 [16..21]  ============================================ */
62461 typedef enum {                                  /*!< GPIO_PINCFG99_NCESRC99                                                    */
62462   GPIO_PINCFG99_NCESRC99_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
62463   GPIO_PINCFG99_NCESRC99_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
62464   GPIO_PINCFG99_NCESRC99_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
62465   GPIO_PINCFG99_NCESRC99_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
62466   GPIO_PINCFG99_NCESRC99_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
62467   GPIO_PINCFG99_NCESRC99_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
62468   GPIO_PINCFG99_NCESRC99_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
62469   GPIO_PINCFG99_NCESRC99_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
62470   GPIO_PINCFG99_NCESRC99_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
62471   GPIO_PINCFG99_NCESRC99_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
62472   GPIO_PINCFG99_NCESRC99_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
62473   GPIO_PINCFG99_NCESRC99_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
62474   GPIO_PINCFG99_NCESRC99_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
62475   GPIO_PINCFG99_NCESRC99_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
62476   GPIO_PINCFG99_NCESRC99_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
62477   GPIO_PINCFG99_NCESRC99_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
62478   GPIO_PINCFG99_NCESRC99_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
62479   GPIO_PINCFG99_NCESRC99_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
62480   GPIO_PINCFG99_NCESRC99_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
62481   GPIO_PINCFG99_NCESRC99_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
62482   GPIO_PINCFG99_NCESRC99_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
62483   GPIO_PINCFG99_NCESRC99_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
62484   GPIO_PINCFG99_NCESRC99_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
62485   GPIO_PINCFG99_NCESRC99_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
62486   GPIO_PINCFG99_NCESRC99_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
62487   GPIO_PINCFG99_NCESRC99_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
62488   GPIO_PINCFG99_NCESRC99_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
62489   GPIO_PINCFG99_NCESRC99_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
62490   GPIO_PINCFG99_NCESRC99_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
62491   GPIO_PINCFG99_NCESRC99_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
62492   GPIO_PINCFG99_NCESRC99_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
62493   GPIO_PINCFG99_NCESRC99_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
62494   GPIO_PINCFG99_NCESRC99_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
62495   GPIO_PINCFG99_NCESRC99_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
62496   GPIO_PINCFG99_NCESRC99_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
62497   GPIO_PINCFG99_NCESRC99_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
62498   GPIO_PINCFG99_NCESRC99_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
62499   GPIO_PINCFG99_NCESRC99_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62500   GPIO_PINCFG99_NCESRC99_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62501   GPIO_PINCFG99_NCESRC99_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62502   GPIO_PINCFG99_NCESRC99_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62503   GPIO_PINCFG99_NCESRC99_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62504   GPIO_PINCFG99_NCESRC99_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
62505 } GPIO_PINCFG99_NCESRC99_Enum;
62506 
62507 /* ===========================================  GPIO PINCFG99 PULLCFG99 [13..15]  ============================================ */
62508 typedef enum {                                  /*!< GPIO_PINCFG99_PULLCFG99                                                   */
62509   GPIO_PINCFG99_PULLCFG99_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62510   GPIO_PINCFG99_PULLCFG99_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62511   GPIO_PINCFG99_PULLCFG99_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62512   GPIO_PINCFG99_PULLCFG99_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62513   GPIO_PINCFG99_PULLCFG99_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
62514   GPIO_PINCFG99_PULLCFG99_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
62515   GPIO_PINCFG99_PULLCFG99_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
62516   GPIO_PINCFG99_PULLCFG99_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
62517 } GPIO_PINCFG99_PULLCFG99_Enum;
62518 
62519 /* ==============================================  GPIO PINCFG99 DS99 [10..11]  ============================================== */
62520 typedef enum {                                  /*!< GPIO_PINCFG99_DS99                                                        */
62521   GPIO_PINCFG99_DS99_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62522   GPIO_PINCFG99_DS99_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62523 } GPIO_PINCFG99_DS99_Enum;
62524 
62525 /* =============================================  GPIO PINCFG99 OUTCFG99 [8..9]  ============================================= */
62526 typedef enum {                                  /*!< GPIO_PINCFG99_OUTCFG99                                                    */
62527   GPIO_PINCFG99_OUTCFG99_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
62528   GPIO_PINCFG99_OUTCFG99_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62529                                                      and 1 values on pin.                                                      */
62530   GPIO_PINCFG99_OUTCFG99_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62531                                                      low, tristate otherwise.                                                  */
62532   GPIO_PINCFG99_OUTCFG99_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62533                                                      drive 0, 1 of HiZ on pin.                                                 */
62534 } GPIO_PINCFG99_OUTCFG99_Enum;
62535 
62536 /* =============================================  GPIO PINCFG99 IRPTEN99 [6..7]  ============================================= */
62537 typedef enum {                                  /*!< GPIO_PINCFG99_IRPTEN99                                                    */
62538   GPIO_PINCFG99_IRPTEN99_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62539   GPIO_PINCFG99_IRPTEN99_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62540                                                      on this GPIO                                                              */
62541   GPIO_PINCFG99_IRPTEN99_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62542                                                      on this GPIO                                                              */
62543   GPIO_PINCFG99_IRPTEN99_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62544                                                      GPIO                                                                      */
62545 } GPIO_PINCFG99_IRPTEN99_Enum;
62546 
62547 /* =============================================  GPIO PINCFG99 FNCSEL99 [0..3]  ============================================= */
62548 typedef enum {                                  /*!< GPIO_PINCFG99_FNCSEL99                                                    */
62549   GPIO_PINCFG99_FNCSEL99_MSPI1_4       = 0,     /*!< MSPI1_4 : MSPI Master 1 Interface Signal                                  */
62550   GPIO_PINCFG99_FNCSEL99_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62551   GPIO_PINCFG99_FNCSEL99_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62552   GPIO_PINCFG99_FNCSEL99_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
62553   GPIO_PINCFG99_FNCSEL99_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62554   GPIO_PINCFG99_FNCSEL99_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62555   GPIO_PINCFG99_FNCSEL99_CT99          = 6,     /*!< CT99 : Timer/Counter input or output; Selection of direction
62556                                                      is done via CTIMER register settings.                                     */
62557   GPIO_PINCFG99_FNCSEL99_NCE99         = 7,     /*!< NCE99 : IOMSTR/MSPI N Chip Select. Polarity is determined by
62558                                                      CE_POLARITY field                                                         */
62559   GPIO_PINCFG99_FNCSEL99_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
62560   GPIO_PINCFG99_FNCSEL99_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62561   GPIO_PINCFG99_FNCSEL99_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62562   GPIO_PINCFG99_FNCSEL99_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
62563   GPIO_PINCFG99_FNCSEL99_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62564   GPIO_PINCFG99_FNCSEL99_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62565   GPIO_PINCFG99_FNCSEL99_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62566   GPIO_PINCFG99_FNCSEL99_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62567 } GPIO_PINCFG99_FNCSEL99_Enum;
62568 
62569 /* =======================================================  PINCFG100  ======================================================= */
62570 /* ===========================================  GPIO PINCFG100 NCEPOL100 [22..22]  =========================================== */
62571 typedef enum {                                  /*!< GPIO_PINCFG100_NCEPOL100                                                  */
62572   GPIO_PINCFG100_NCEPOL100_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
62573   GPIO_PINCFG100_NCEPOL100_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
62574 } GPIO_PINCFG100_NCEPOL100_Enum;
62575 
62576 /* ===========================================  GPIO PINCFG100 NCESRC100 [16..21]  =========================================== */
62577 typedef enum {                                  /*!< GPIO_PINCFG100_NCESRC100                                                  */
62578   GPIO_PINCFG100_NCESRC100_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
62579   GPIO_PINCFG100_NCESRC100_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
62580   GPIO_PINCFG100_NCESRC100_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
62581   GPIO_PINCFG100_NCESRC100_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
62582   GPIO_PINCFG100_NCESRC100_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
62583   GPIO_PINCFG100_NCESRC100_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
62584   GPIO_PINCFG100_NCESRC100_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
62585   GPIO_PINCFG100_NCESRC100_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
62586   GPIO_PINCFG100_NCESRC100_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
62587   GPIO_PINCFG100_NCESRC100_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
62588   GPIO_PINCFG100_NCESRC100_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
62589   GPIO_PINCFG100_NCESRC100_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
62590   GPIO_PINCFG100_NCESRC100_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
62591   GPIO_PINCFG100_NCESRC100_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
62592   GPIO_PINCFG100_NCESRC100_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
62593   GPIO_PINCFG100_NCESRC100_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
62594   GPIO_PINCFG100_NCESRC100_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
62595   GPIO_PINCFG100_NCESRC100_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
62596   GPIO_PINCFG100_NCESRC100_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
62597   GPIO_PINCFG100_NCESRC100_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
62598   GPIO_PINCFG100_NCESRC100_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
62599   GPIO_PINCFG100_NCESRC100_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
62600   GPIO_PINCFG100_NCESRC100_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
62601   GPIO_PINCFG100_NCESRC100_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
62602   GPIO_PINCFG100_NCESRC100_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
62603   GPIO_PINCFG100_NCESRC100_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
62604   GPIO_PINCFG100_NCESRC100_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
62605   GPIO_PINCFG100_NCESRC100_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
62606   GPIO_PINCFG100_NCESRC100_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
62607   GPIO_PINCFG100_NCESRC100_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
62608   GPIO_PINCFG100_NCESRC100_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
62609   GPIO_PINCFG100_NCESRC100_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
62610   GPIO_PINCFG100_NCESRC100_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
62611   GPIO_PINCFG100_NCESRC100_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
62612   GPIO_PINCFG100_NCESRC100_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
62613   GPIO_PINCFG100_NCESRC100_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
62614   GPIO_PINCFG100_NCESRC100_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
62615   GPIO_PINCFG100_NCESRC100_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62616   GPIO_PINCFG100_NCESRC100_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62617   GPIO_PINCFG100_NCESRC100_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62618   GPIO_PINCFG100_NCESRC100_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62619   GPIO_PINCFG100_NCESRC100_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62620   GPIO_PINCFG100_NCESRC100_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
62621 } GPIO_PINCFG100_NCESRC100_Enum;
62622 
62623 /* ==========================================  GPIO PINCFG100 PULLCFG100 [13..15]  =========================================== */
62624 typedef enum {                                  /*!< GPIO_PINCFG100_PULLCFG100                                                 */
62625   GPIO_PINCFG100_PULLCFG100_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62626   GPIO_PINCFG100_PULLCFG100_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62627   GPIO_PINCFG100_PULLCFG100_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62628   GPIO_PINCFG100_PULLCFG100_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62629   GPIO_PINCFG100_PULLCFG100_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
62630   GPIO_PINCFG100_PULLCFG100_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
62631   GPIO_PINCFG100_PULLCFG100_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
62632   GPIO_PINCFG100_PULLCFG100_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
62633 } GPIO_PINCFG100_PULLCFG100_Enum;
62634 
62635 /* =============================================  GPIO PINCFG100 DS100 [10..11]  ============================================= */
62636 typedef enum {                                  /*!< GPIO_PINCFG100_DS100                                                      */
62637   GPIO_PINCFG100_DS100_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62638   GPIO_PINCFG100_DS100_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62639 } GPIO_PINCFG100_DS100_Enum;
62640 
62641 /* ============================================  GPIO PINCFG100 OUTCFG100 [8..9]  ============================================ */
62642 typedef enum {                                  /*!< GPIO_PINCFG100_OUTCFG100                                                  */
62643   GPIO_PINCFG100_OUTCFG100_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62644   GPIO_PINCFG100_OUTCFG100_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62645                                                      and 1 values on pin.                                                      */
62646   GPIO_PINCFG100_OUTCFG100_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62647                                                      low, tristate otherwise.                                                  */
62648   GPIO_PINCFG100_OUTCFG100_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62649                                                      drive 0, 1 of HiZ on pin.                                                 */
62650 } GPIO_PINCFG100_OUTCFG100_Enum;
62651 
62652 /* ============================================  GPIO PINCFG100 IRPTEN100 [6..7]  ============================================ */
62653 typedef enum {                                  /*!< GPIO_PINCFG100_IRPTEN100                                                  */
62654   GPIO_PINCFG100_IRPTEN100_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62655   GPIO_PINCFG100_IRPTEN100_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62656                                                      on this GPIO                                                              */
62657   GPIO_PINCFG100_IRPTEN100_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62658                                                      on this GPIO                                                              */
62659   GPIO_PINCFG100_IRPTEN100_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62660                                                      GPIO                                                                      */
62661 } GPIO_PINCFG100_IRPTEN100_Enum;
62662 
62663 /* ============================================  GPIO PINCFG100 FNCSEL100 [0..3]  ============================================ */
62664 typedef enum {                                  /*!< GPIO_PINCFG100_FNCSEL100                                                  */
62665   GPIO_PINCFG100_FNCSEL100_MSPI1_5     = 0,     /*!< MSPI1_5 : MSPI Master 1 Interface Signal                                  */
62666   GPIO_PINCFG100_FNCSEL100_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62667   GPIO_PINCFG100_FNCSEL100_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62668   GPIO_PINCFG100_FNCSEL100_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62669   GPIO_PINCFG100_FNCSEL100_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62670   GPIO_PINCFG100_FNCSEL100_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62671   GPIO_PINCFG100_FNCSEL100_CT100       = 6,     /*!< CT100 : Timer/Counter input or output; Selection of direction
62672                                                      is done via CTIMER register settings.                                     */
62673   GPIO_PINCFG100_FNCSEL100_NCE100      = 7,     /*!< NCE100 : IOMSTR/MSPI N Chip Select. Polarity is determined by
62674                                                      CE_POLARITY field                                                         */
62675   GPIO_PINCFG100_FNCSEL100_OBSBUS4     = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
62676   GPIO_PINCFG100_FNCSEL100_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62677   GPIO_PINCFG100_FNCSEL100_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62678   GPIO_PINCFG100_FNCSEL100_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
62679   GPIO_PINCFG100_FNCSEL100_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62680   GPIO_PINCFG100_FNCSEL100_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62681   GPIO_PINCFG100_FNCSEL100_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62682   GPIO_PINCFG100_FNCSEL100_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62683 } GPIO_PINCFG100_FNCSEL100_Enum;
62684 
62685 /* =======================================================  PINCFG101  ======================================================= */
62686 /* ===========================================  GPIO PINCFG101 NCEPOL101 [22..22]  =========================================== */
62687 typedef enum {                                  /*!< GPIO_PINCFG101_NCEPOL101                                                  */
62688   GPIO_PINCFG101_NCEPOL101_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
62689   GPIO_PINCFG101_NCEPOL101_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
62690 } GPIO_PINCFG101_NCEPOL101_Enum;
62691 
62692 /* ===========================================  GPIO PINCFG101 NCESRC101 [16..21]  =========================================== */
62693 typedef enum {                                  /*!< GPIO_PINCFG101_NCESRC101                                                  */
62694   GPIO_PINCFG101_NCESRC101_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
62695   GPIO_PINCFG101_NCESRC101_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
62696   GPIO_PINCFG101_NCESRC101_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
62697   GPIO_PINCFG101_NCESRC101_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
62698   GPIO_PINCFG101_NCESRC101_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
62699   GPIO_PINCFG101_NCESRC101_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
62700   GPIO_PINCFG101_NCESRC101_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
62701   GPIO_PINCFG101_NCESRC101_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
62702   GPIO_PINCFG101_NCESRC101_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
62703   GPIO_PINCFG101_NCESRC101_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
62704   GPIO_PINCFG101_NCESRC101_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
62705   GPIO_PINCFG101_NCESRC101_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
62706   GPIO_PINCFG101_NCESRC101_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
62707   GPIO_PINCFG101_NCESRC101_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
62708   GPIO_PINCFG101_NCESRC101_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
62709   GPIO_PINCFG101_NCESRC101_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
62710   GPIO_PINCFG101_NCESRC101_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
62711   GPIO_PINCFG101_NCESRC101_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
62712   GPIO_PINCFG101_NCESRC101_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
62713   GPIO_PINCFG101_NCESRC101_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
62714   GPIO_PINCFG101_NCESRC101_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
62715   GPIO_PINCFG101_NCESRC101_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
62716   GPIO_PINCFG101_NCESRC101_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
62717   GPIO_PINCFG101_NCESRC101_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
62718   GPIO_PINCFG101_NCESRC101_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
62719   GPIO_PINCFG101_NCESRC101_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
62720   GPIO_PINCFG101_NCESRC101_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
62721   GPIO_PINCFG101_NCESRC101_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
62722   GPIO_PINCFG101_NCESRC101_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
62723   GPIO_PINCFG101_NCESRC101_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
62724   GPIO_PINCFG101_NCESRC101_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
62725   GPIO_PINCFG101_NCESRC101_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
62726   GPIO_PINCFG101_NCESRC101_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
62727   GPIO_PINCFG101_NCESRC101_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
62728   GPIO_PINCFG101_NCESRC101_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
62729   GPIO_PINCFG101_NCESRC101_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
62730   GPIO_PINCFG101_NCESRC101_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
62731   GPIO_PINCFG101_NCESRC101_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62732   GPIO_PINCFG101_NCESRC101_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62733   GPIO_PINCFG101_NCESRC101_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62734   GPIO_PINCFG101_NCESRC101_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62735   GPIO_PINCFG101_NCESRC101_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62736   GPIO_PINCFG101_NCESRC101_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
62737 } GPIO_PINCFG101_NCESRC101_Enum;
62738 
62739 /* ==========================================  GPIO PINCFG101 PULLCFG101 [13..15]  =========================================== */
62740 typedef enum {                                  /*!< GPIO_PINCFG101_PULLCFG101                                                 */
62741   GPIO_PINCFG101_PULLCFG101_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62742   GPIO_PINCFG101_PULLCFG101_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62743   GPIO_PINCFG101_PULLCFG101_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62744   GPIO_PINCFG101_PULLCFG101_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62745   GPIO_PINCFG101_PULLCFG101_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
62746   GPIO_PINCFG101_PULLCFG101_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
62747   GPIO_PINCFG101_PULLCFG101_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
62748   GPIO_PINCFG101_PULLCFG101_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
62749 } GPIO_PINCFG101_PULLCFG101_Enum;
62750 
62751 /* =============================================  GPIO PINCFG101 DS101 [10..11]  ============================================= */
62752 typedef enum {                                  /*!< GPIO_PINCFG101_DS101                                                      */
62753   GPIO_PINCFG101_DS101_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62754   GPIO_PINCFG101_DS101_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62755 } GPIO_PINCFG101_DS101_Enum;
62756 
62757 /* ============================================  GPIO PINCFG101 OUTCFG101 [8..9]  ============================================ */
62758 typedef enum {                                  /*!< GPIO_PINCFG101_OUTCFG101                                                  */
62759   GPIO_PINCFG101_OUTCFG101_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62760   GPIO_PINCFG101_OUTCFG101_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62761                                                      and 1 values on pin.                                                      */
62762   GPIO_PINCFG101_OUTCFG101_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62763                                                      low, tristate otherwise.                                                  */
62764   GPIO_PINCFG101_OUTCFG101_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62765                                                      drive 0, 1 of HiZ on pin.                                                 */
62766 } GPIO_PINCFG101_OUTCFG101_Enum;
62767 
62768 /* ============================================  GPIO PINCFG101 IRPTEN101 [6..7]  ============================================ */
62769 typedef enum {                                  /*!< GPIO_PINCFG101_IRPTEN101                                                  */
62770   GPIO_PINCFG101_IRPTEN101_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62771   GPIO_PINCFG101_IRPTEN101_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62772                                                      on this GPIO                                                              */
62773   GPIO_PINCFG101_IRPTEN101_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62774                                                      on this GPIO                                                              */
62775   GPIO_PINCFG101_IRPTEN101_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62776                                                      GPIO                                                                      */
62777 } GPIO_PINCFG101_IRPTEN101_Enum;
62778 
62779 /* ============================================  GPIO PINCFG101 FNCSEL101 [0..3]  ============================================ */
62780 typedef enum {                                  /*!< GPIO_PINCFG101_FNCSEL101                                                  */
62781   GPIO_PINCFG101_FNCSEL101_MSPI1_6     = 0,     /*!< MSPI1_6 : MSPI Master 1 Interface Signal                                  */
62782   GPIO_PINCFG101_FNCSEL101_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62783   GPIO_PINCFG101_FNCSEL101_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62784   GPIO_PINCFG101_FNCSEL101_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62785   GPIO_PINCFG101_FNCSEL101_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62786   GPIO_PINCFG101_FNCSEL101_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62787   GPIO_PINCFG101_FNCSEL101_CT101       = 6,     /*!< CT101 : Timer/Counter input or output; Selection of direction
62788                                                      is done via CTIMER register settings.                                     */
62789   GPIO_PINCFG101_FNCSEL101_NCE101      = 7,     /*!< NCE101 : IOMSTR/MSPI N Chip Select. Polarity is determined by
62790                                                      CE_POLARITY field                                                         */
62791   GPIO_PINCFG101_FNCSEL101_OBSBUS5     = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
62792   GPIO_PINCFG101_FNCSEL101_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62793   GPIO_PINCFG101_FNCSEL101_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62794   GPIO_PINCFG101_FNCSEL101_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
62795   GPIO_PINCFG101_FNCSEL101_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62796   GPIO_PINCFG101_FNCSEL101_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62797   GPIO_PINCFG101_FNCSEL101_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62798   GPIO_PINCFG101_FNCSEL101_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62799 } GPIO_PINCFG101_FNCSEL101_Enum;
62800 
62801 /* =======================================================  PINCFG102  ======================================================= */
62802 /* ===========================================  GPIO PINCFG102 NCEPOL102 [22..22]  =========================================== */
62803 typedef enum {                                  /*!< GPIO_PINCFG102_NCEPOL102                                                  */
62804   GPIO_PINCFG102_NCEPOL102_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
62805   GPIO_PINCFG102_NCEPOL102_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
62806 } GPIO_PINCFG102_NCEPOL102_Enum;
62807 
62808 /* ===========================================  GPIO PINCFG102 NCESRC102 [16..21]  =========================================== */
62809 typedef enum {                                  /*!< GPIO_PINCFG102_NCESRC102                                                  */
62810   GPIO_PINCFG102_NCESRC102_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
62811   GPIO_PINCFG102_NCESRC102_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
62812   GPIO_PINCFG102_NCESRC102_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
62813   GPIO_PINCFG102_NCESRC102_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
62814   GPIO_PINCFG102_NCESRC102_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
62815   GPIO_PINCFG102_NCESRC102_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
62816   GPIO_PINCFG102_NCESRC102_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
62817   GPIO_PINCFG102_NCESRC102_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
62818   GPIO_PINCFG102_NCESRC102_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
62819   GPIO_PINCFG102_NCESRC102_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
62820   GPIO_PINCFG102_NCESRC102_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
62821   GPIO_PINCFG102_NCESRC102_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
62822   GPIO_PINCFG102_NCESRC102_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
62823   GPIO_PINCFG102_NCESRC102_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
62824   GPIO_PINCFG102_NCESRC102_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
62825   GPIO_PINCFG102_NCESRC102_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
62826   GPIO_PINCFG102_NCESRC102_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
62827   GPIO_PINCFG102_NCESRC102_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
62828   GPIO_PINCFG102_NCESRC102_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
62829   GPIO_PINCFG102_NCESRC102_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
62830   GPIO_PINCFG102_NCESRC102_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
62831   GPIO_PINCFG102_NCESRC102_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
62832   GPIO_PINCFG102_NCESRC102_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
62833   GPIO_PINCFG102_NCESRC102_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
62834   GPIO_PINCFG102_NCESRC102_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
62835   GPIO_PINCFG102_NCESRC102_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
62836   GPIO_PINCFG102_NCESRC102_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
62837   GPIO_PINCFG102_NCESRC102_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
62838   GPIO_PINCFG102_NCESRC102_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
62839   GPIO_PINCFG102_NCESRC102_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
62840   GPIO_PINCFG102_NCESRC102_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
62841   GPIO_PINCFG102_NCESRC102_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
62842   GPIO_PINCFG102_NCESRC102_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
62843   GPIO_PINCFG102_NCESRC102_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
62844   GPIO_PINCFG102_NCESRC102_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
62845   GPIO_PINCFG102_NCESRC102_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
62846   GPIO_PINCFG102_NCESRC102_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
62847   GPIO_PINCFG102_NCESRC102_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62848   GPIO_PINCFG102_NCESRC102_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62849   GPIO_PINCFG102_NCESRC102_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62850   GPIO_PINCFG102_NCESRC102_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62851   GPIO_PINCFG102_NCESRC102_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62852   GPIO_PINCFG102_NCESRC102_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
62853 } GPIO_PINCFG102_NCESRC102_Enum;
62854 
62855 /* ==========================================  GPIO PINCFG102 PULLCFG102 [13..15]  =========================================== */
62856 typedef enum {                                  /*!< GPIO_PINCFG102_PULLCFG102                                                 */
62857   GPIO_PINCFG102_PULLCFG102_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62858   GPIO_PINCFG102_PULLCFG102_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62859   GPIO_PINCFG102_PULLCFG102_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62860   GPIO_PINCFG102_PULLCFG102_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62861   GPIO_PINCFG102_PULLCFG102_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
62862   GPIO_PINCFG102_PULLCFG102_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
62863   GPIO_PINCFG102_PULLCFG102_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
62864   GPIO_PINCFG102_PULLCFG102_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
62865 } GPIO_PINCFG102_PULLCFG102_Enum;
62866 
62867 /* =============================================  GPIO PINCFG102 DS102 [10..11]  ============================================= */
62868 typedef enum {                                  /*!< GPIO_PINCFG102_DS102                                                      */
62869   GPIO_PINCFG102_DS102_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62870   GPIO_PINCFG102_DS102_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62871 } GPIO_PINCFG102_DS102_Enum;
62872 
62873 /* ============================================  GPIO PINCFG102 OUTCFG102 [8..9]  ============================================ */
62874 typedef enum {                                  /*!< GPIO_PINCFG102_OUTCFG102                                                  */
62875   GPIO_PINCFG102_OUTCFG102_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62876   GPIO_PINCFG102_OUTCFG102_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62877                                                      and 1 values on pin.                                                      */
62878   GPIO_PINCFG102_OUTCFG102_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62879                                                      low, tristate otherwise.                                                  */
62880   GPIO_PINCFG102_OUTCFG102_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62881                                                      drive 0, 1 of HiZ on pin.                                                 */
62882 } GPIO_PINCFG102_OUTCFG102_Enum;
62883 
62884 /* ============================================  GPIO PINCFG102 IRPTEN102 [6..7]  ============================================ */
62885 typedef enum {                                  /*!< GPIO_PINCFG102_IRPTEN102                                                  */
62886   GPIO_PINCFG102_IRPTEN102_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
62887   GPIO_PINCFG102_IRPTEN102_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
62888                                                      on this GPIO                                                              */
62889   GPIO_PINCFG102_IRPTEN102_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
62890                                                      on this GPIO                                                              */
62891   GPIO_PINCFG102_IRPTEN102_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
62892                                                      GPIO                                                                      */
62893 } GPIO_PINCFG102_IRPTEN102_Enum;
62894 
62895 /* ============================================  GPIO PINCFG102 FNCSEL102 [0..3]  ============================================ */
62896 typedef enum {                                  /*!< GPIO_PINCFG102_FNCSEL102                                                  */
62897   GPIO_PINCFG102_FNCSEL102_MSPI1_7     = 0,     /*!< MSPI1_7 : MSPI Master 1 Interface Signal                                  */
62898   GPIO_PINCFG102_FNCSEL102_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
62899   GPIO_PINCFG102_FNCSEL102_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
62900   GPIO_PINCFG102_FNCSEL102_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
62901   GPIO_PINCFG102_FNCSEL102_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
62902   GPIO_PINCFG102_FNCSEL102_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
62903   GPIO_PINCFG102_FNCSEL102_CT102       = 6,     /*!< CT102 : Timer/Counter input or output; Selection of direction
62904                                                      is done via CTIMER register settings.                                     */
62905   GPIO_PINCFG102_FNCSEL102_NCE102      = 7,     /*!< NCE102 : IOMSTR/MSPI N Chip Select. Polarity is determined by
62906                                                      CE_POLARITY field                                                         */
62907   GPIO_PINCFG102_FNCSEL102_OBSBUS6     = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
62908   GPIO_PINCFG102_FNCSEL102_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
62909   GPIO_PINCFG102_FNCSEL102_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
62910   GPIO_PINCFG102_FNCSEL102_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
62911   GPIO_PINCFG102_FNCSEL102_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
62912   GPIO_PINCFG102_FNCSEL102_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
62913   GPIO_PINCFG102_FNCSEL102_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
62914   GPIO_PINCFG102_FNCSEL102_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
62915 } GPIO_PINCFG102_FNCSEL102_Enum;
62916 
62917 /* =======================================================  PINCFG103  ======================================================= */
62918 /* ===========================================  GPIO PINCFG103 NCEPOL103 [22..22]  =========================================== */
62919 typedef enum {                                  /*!< GPIO_PINCFG103_NCEPOL103                                                  */
62920   GPIO_PINCFG103_NCEPOL103_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
62921   GPIO_PINCFG103_NCEPOL103_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
62922 } GPIO_PINCFG103_NCEPOL103_Enum;
62923 
62924 /* ===========================================  GPIO PINCFG103 NCESRC103 [16..21]  =========================================== */
62925 typedef enum {                                  /*!< GPIO_PINCFG103_NCESRC103                                                  */
62926   GPIO_PINCFG103_NCESRC103_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
62927   GPIO_PINCFG103_NCESRC103_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
62928   GPIO_PINCFG103_NCESRC103_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
62929   GPIO_PINCFG103_NCESRC103_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
62930   GPIO_PINCFG103_NCESRC103_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
62931   GPIO_PINCFG103_NCESRC103_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
62932   GPIO_PINCFG103_NCESRC103_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
62933   GPIO_PINCFG103_NCESRC103_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
62934   GPIO_PINCFG103_NCESRC103_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
62935   GPIO_PINCFG103_NCESRC103_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
62936   GPIO_PINCFG103_NCESRC103_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
62937   GPIO_PINCFG103_NCESRC103_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
62938   GPIO_PINCFG103_NCESRC103_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
62939   GPIO_PINCFG103_NCESRC103_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
62940   GPIO_PINCFG103_NCESRC103_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
62941   GPIO_PINCFG103_NCESRC103_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
62942   GPIO_PINCFG103_NCESRC103_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
62943   GPIO_PINCFG103_NCESRC103_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
62944   GPIO_PINCFG103_NCESRC103_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
62945   GPIO_PINCFG103_NCESRC103_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
62946   GPIO_PINCFG103_NCESRC103_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
62947   GPIO_PINCFG103_NCESRC103_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
62948   GPIO_PINCFG103_NCESRC103_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
62949   GPIO_PINCFG103_NCESRC103_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
62950   GPIO_PINCFG103_NCESRC103_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
62951   GPIO_PINCFG103_NCESRC103_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
62952   GPIO_PINCFG103_NCESRC103_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
62953   GPIO_PINCFG103_NCESRC103_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
62954   GPIO_PINCFG103_NCESRC103_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
62955   GPIO_PINCFG103_NCESRC103_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
62956   GPIO_PINCFG103_NCESRC103_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
62957   GPIO_PINCFG103_NCESRC103_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
62958   GPIO_PINCFG103_NCESRC103_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
62959   GPIO_PINCFG103_NCESRC103_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
62960   GPIO_PINCFG103_NCESRC103_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
62961   GPIO_PINCFG103_NCESRC103_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
62962   GPIO_PINCFG103_NCESRC103_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
62963   GPIO_PINCFG103_NCESRC103_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
62964   GPIO_PINCFG103_NCESRC103_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
62965   GPIO_PINCFG103_NCESRC103_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
62966   GPIO_PINCFG103_NCESRC103_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
62967   GPIO_PINCFG103_NCESRC103_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
62968   GPIO_PINCFG103_NCESRC103_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
62969 } GPIO_PINCFG103_NCESRC103_Enum;
62970 
62971 /* ==========================================  GPIO PINCFG103 PULLCFG103 [13..15]  =========================================== */
62972 typedef enum {                                  /*!< GPIO_PINCFG103_PULLCFG103                                                 */
62973   GPIO_PINCFG103_PULLCFG103_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
62974   GPIO_PINCFG103_PULLCFG103_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
62975   GPIO_PINCFG103_PULLCFG103_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
62976   GPIO_PINCFG103_PULLCFG103_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
62977   GPIO_PINCFG103_PULLCFG103_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
62978   GPIO_PINCFG103_PULLCFG103_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
62979   GPIO_PINCFG103_PULLCFG103_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
62980   GPIO_PINCFG103_PULLCFG103_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
62981 } GPIO_PINCFG103_PULLCFG103_Enum;
62982 
62983 /* =============================================  GPIO PINCFG103 DS103 [10..11]  ============================================= */
62984 typedef enum {                                  /*!< GPIO_PINCFG103_DS103                                                      */
62985   GPIO_PINCFG103_DS103_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
62986   GPIO_PINCFG103_DS103_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
62987 } GPIO_PINCFG103_DS103_Enum;
62988 
62989 /* ============================================  GPIO PINCFG103 OUTCFG103 [8..9]  ============================================ */
62990 typedef enum {                                  /*!< GPIO_PINCFG103_OUTCFG103                                                  */
62991   GPIO_PINCFG103_OUTCFG103_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
62992   GPIO_PINCFG103_OUTCFG103_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
62993                                                      and 1 values on pin.                                                      */
62994   GPIO_PINCFG103_OUTCFG103_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
62995                                                      low, tristate otherwise.                                                  */
62996   GPIO_PINCFG103_OUTCFG103_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
62997                                                      drive 0, 1 of HiZ on pin.                                                 */
62998 } GPIO_PINCFG103_OUTCFG103_Enum;
62999 
63000 /* ============================================  GPIO PINCFG103 IRPTEN103 [6..7]  ============================================ */
63001 typedef enum {                                  /*!< GPIO_PINCFG103_IRPTEN103                                                  */
63002   GPIO_PINCFG103_IRPTEN103_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63003   GPIO_PINCFG103_IRPTEN103_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63004                                                      on this GPIO                                                              */
63005   GPIO_PINCFG103_IRPTEN103_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63006                                                      on this GPIO                                                              */
63007   GPIO_PINCFG103_IRPTEN103_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63008                                                      GPIO                                                                      */
63009 } GPIO_PINCFG103_IRPTEN103_Enum;
63010 
63011 /* ============================================  GPIO PINCFG103 FNCSEL103 [0..3]  ============================================ */
63012 typedef enum {                                  /*!< GPIO_PINCFG103_FNCSEL103                                                  */
63013   GPIO_PINCFG103_FNCSEL103_MSPI1_8     = 0,     /*!< MSPI1_8 : MSPI Master 1 Interface Signal                                  */
63014   GPIO_PINCFG103_FNCSEL103_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63015   GPIO_PINCFG103_FNCSEL103_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63016   GPIO_PINCFG103_FNCSEL103_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63017   GPIO_PINCFG103_FNCSEL103_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63018   GPIO_PINCFG103_FNCSEL103_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63019   GPIO_PINCFG103_FNCSEL103_CT103       = 6,     /*!< CT103 : Timer/Counter input or output; Selection of direction
63020                                                      is done via CTIMER register settings.                                     */
63021   GPIO_PINCFG103_FNCSEL103_NCE103      = 7,     /*!< NCE103 : IOMSTR/MSPI N Chip Select. Polarity is determined by
63022                                                      CE_POLARITY field                                                         */
63023   GPIO_PINCFG103_FNCSEL103_OBSBUS7     = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
63024   GPIO_PINCFG103_FNCSEL103_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63025   GPIO_PINCFG103_FNCSEL103_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63026   GPIO_PINCFG103_FNCSEL103_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
63027   GPIO_PINCFG103_FNCSEL103_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63028   GPIO_PINCFG103_FNCSEL103_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63029   GPIO_PINCFG103_FNCSEL103_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63030   GPIO_PINCFG103_FNCSEL103_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63031 } GPIO_PINCFG103_FNCSEL103_Enum;
63032 
63033 /* =======================================================  PINCFG104  ======================================================= */
63034 /* ===========================================  GPIO PINCFG104 NCEPOL104 [22..22]  =========================================== */
63035 typedef enum {                                  /*!< GPIO_PINCFG104_NCEPOL104                                                  */
63036   GPIO_PINCFG104_NCEPOL104_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
63037   GPIO_PINCFG104_NCEPOL104_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
63038 } GPIO_PINCFG104_NCEPOL104_Enum;
63039 
63040 /* ===========================================  GPIO PINCFG104 NCESRC104 [16..21]  =========================================== */
63041 typedef enum {                                  /*!< GPIO_PINCFG104_NCESRC104                                                  */
63042   GPIO_PINCFG104_NCESRC104_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
63043   GPIO_PINCFG104_NCESRC104_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
63044   GPIO_PINCFG104_NCESRC104_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
63045   GPIO_PINCFG104_NCESRC104_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
63046   GPIO_PINCFG104_NCESRC104_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
63047   GPIO_PINCFG104_NCESRC104_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
63048   GPIO_PINCFG104_NCESRC104_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
63049   GPIO_PINCFG104_NCESRC104_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
63050   GPIO_PINCFG104_NCESRC104_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
63051   GPIO_PINCFG104_NCESRC104_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
63052   GPIO_PINCFG104_NCESRC104_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
63053   GPIO_PINCFG104_NCESRC104_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
63054   GPIO_PINCFG104_NCESRC104_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
63055   GPIO_PINCFG104_NCESRC104_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
63056   GPIO_PINCFG104_NCESRC104_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
63057   GPIO_PINCFG104_NCESRC104_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
63058   GPIO_PINCFG104_NCESRC104_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
63059   GPIO_PINCFG104_NCESRC104_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
63060   GPIO_PINCFG104_NCESRC104_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
63061   GPIO_PINCFG104_NCESRC104_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
63062   GPIO_PINCFG104_NCESRC104_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
63063   GPIO_PINCFG104_NCESRC104_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
63064   GPIO_PINCFG104_NCESRC104_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
63065   GPIO_PINCFG104_NCESRC104_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
63066   GPIO_PINCFG104_NCESRC104_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
63067   GPIO_PINCFG104_NCESRC104_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
63068   GPIO_PINCFG104_NCESRC104_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
63069   GPIO_PINCFG104_NCESRC104_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
63070   GPIO_PINCFG104_NCESRC104_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
63071   GPIO_PINCFG104_NCESRC104_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
63072   GPIO_PINCFG104_NCESRC104_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
63073   GPIO_PINCFG104_NCESRC104_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
63074   GPIO_PINCFG104_NCESRC104_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
63075   GPIO_PINCFG104_NCESRC104_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
63076   GPIO_PINCFG104_NCESRC104_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
63077   GPIO_PINCFG104_NCESRC104_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
63078   GPIO_PINCFG104_NCESRC104_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
63079   GPIO_PINCFG104_NCESRC104_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
63080   GPIO_PINCFG104_NCESRC104_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
63081   GPIO_PINCFG104_NCESRC104_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
63082   GPIO_PINCFG104_NCESRC104_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
63083   GPIO_PINCFG104_NCESRC104_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
63084   GPIO_PINCFG104_NCESRC104_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
63085 } GPIO_PINCFG104_NCESRC104_Enum;
63086 
63087 /* ==========================================  GPIO PINCFG104 PULLCFG104 [13..15]  =========================================== */
63088 typedef enum {                                  /*!< GPIO_PINCFG104_PULLCFG104                                                 */
63089   GPIO_PINCFG104_PULLCFG104_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
63090   GPIO_PINCFG104_PULLCFG104_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
63091   GPIO_PINCFG104_PULLCFG104_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
63092   GPIO_PINCFG104_PULLCFG104_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
63093   GPIO_PINCFG104_PULLCFG104_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
63094   GPIO_PINCFG104_PULLCFG104_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
63095   GPIO_PINCFG104_PULLCFG104_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
63096   GPIO_PINCFG104_PULLCFG104_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
63097 } GPIO_PINCFG104_PULLCFG104_Enum;
63098 
63099 /* =============================================  GPIO PINCFG104 DS104 [10..11]  ============================================= */
63100 typedef enum {                                  /*!< GPIO_PINCFG104_DS104                                                      */
63101   GPIO_PINCFG104_DS104_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
63102   GPIO_PINCFG104_DS104_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
63103 } GPIO_PINCFG104_DS104_Enum;
63104 
63105 /* ============================================  GPIO PINCFG104 OUTCFG104 [8..9]  ============================================ */
63106 typedef enum {                                  /*!< GPIO_PINCFG104_OUTCFG104                                                  */
63107   GPIO_PINCFG104_OUTCFG104_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63108   GPIO_PINCFG104_OUTCFG104_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63109                                                      and 1 values on pin.                                                      */
63110   GPIO_PINCFG104_OUTCFG104_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63111                                                      low, tristate otherwise.                                                  */
63112   GPIO_PINCFG104_OUTCFG104_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63113                                                      drive 0, 1 of HiZ on pin.                                                 */
63114 } GPIO_PINCFG104_OUTCFG104_Enum;
63115 
63116 /* ============================================  GPIO PINCFG104 IRPTEN104 [6..7]  ============================================ */
63117 typedef enum {                                  /*!< GPIO_PINCFG104_IRPTEN104                                                  */
63118   GPIO_PINCFG104_IRPTEN104_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63119   GPIO_PINCFG104_IRPTEN104_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63120                                                      on this GPIO                                                              */
63121   GPIO_PINCFG104_IRPTEN104_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63122                                                      on this GPIO                                                              */
63123   GPIO_PINCFG104_IRPTEN104_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63124                                                      GPIO                                                                      */
63125 } GPIO_PINCFG104_IRPTEN104_Enum;
63126 
63127 /* ============================================  GPIO PINCFG104 FNCSEL104 [0..3]  ============================================ */
63128 typedef enum {                                  /*!< GPIO_PINCFG104_FNCSEL104                                                  */
63129   GPIO_PINCFG104_FNCSEL104_MSPI1_9     = 0,     /*!< MSPI1_9 : MSPI Master 1 Interface Signal                                  */
63130   GPIO_PINCFG104_FNCSEL104_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63131   GPIO_PINCFG104_FNCSEL104_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63132   GPIO_PINCFG104_FNCSEL104_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63133   GPIO_PINCFG104_FNCSEL104_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63134   GPIO_PINCFG104_FNCSEL104_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63135   GPIO_PINCFG104_FNCSEL104_CT104       = 6,     /*!< CT104 : Timer/Counter input or output; Selection of direction
63136                                                      is done via CTIMER register settings.                                     */
63137   GPIO_PINCFG104_FNCSEL104_NCE104      = 7,     /*!< NCE104 : IOMSTR/MSPI N Chip Select. Polarity is determined by
63138                                                      CE_POLARITY field                                                         */
63139   GPIO_PINCFG104_FNCSEL104_OBSBUS8     = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
63140   GPIO_PINCFG104_FNCSEL104_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63141   GPIO_PINCFG104_FNCSEL104_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63142   GPIO_PINCFG104_FNCSEL104_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
63143   GPIO_PINCFG104_FNCSEL104_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63144   GPIO_PINCFG104_FNCSEL104_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63145   GPIO_PINCFG104_FNCSEL104_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63146   GPIO_PINCFG104_FNCSEL104_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63147 } GPIO_PINCFG104_FNCSEL104_Enum;
63148 
63149 /* =======================================================  PINCFG105  ======================================================= */
63150 /* ============================================  GPIO PINCFG105 OUTCFG105 [8..9]  ============================================ */
63151 typedef enum {                                  /*!< GPIO_PINCFG105_OUTCFG105                                                  */
63152   GPIO_PINCFG105_OUTCFG105_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63153   GPIO_PINCFG105_OUTCFG105_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63154                                                      and 1 values on pin.                                                      */
63155   GPIO_PINCFG105_OUTCFG105_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63156                                                      low, tristate otherwise.                                                  */
63157   GPIO_PINCFG105_OUTCFG105_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63158                                                      drive 0, 1 of HiZ on pin.                                                 */
63159 } GPIO_PINCFG105_OUTCFG105_Enum;
63160 
63161 /* ============================================  GPIO PINCFG105 IRPTEN105 [6..7]  ============================================ */
63162 typedef enum {                                  /*!< GPIO_PINCFG105_IRPTEN105                                                  */
63163   GPIO_PINCFG105_IRPTEN105_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63164   GPIO_PINCFG105_IRPTEN105_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63165                                                      on this GPIO                                                              */
63166   GPIO_PINCFG105_IRPTEN105_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63167                                                      on this GPIO                                                              */
63168   GPIO_PINCFG105_IRPTEN105_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63169                                                      GPIO                                                                      */
63170 } GPIO_PINCFG105_IRPTEN105_Enum;
63171 
63172 /* ============================================  GPIO PINCFG105 FNCSEL105 [0..3]  ============================================ */
63173 typedef enum {                                  /*!< GPIO_PINCFG105_FNCSEL105                                                  */
63174   GPIO_PINCFG105_FNCSEL105_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63175   GPIO_PINCFG105_FNCSEL105_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63176   GPIO_PINCFG105_FNCSEL105_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63177   GPIO_PINCFG105_FNCSEL105_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63178   GPIO_PINCFG105_FNCSEL105_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63179   GPIO_PINCFG105_FNCSEL105_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63180   GPIO_PINCFG105_FNCSEL105_CT105       = 6,     /*!< CT105 : Timer/Counter input or output; Selection of direction
63181                                                      is done via CTIMER register settings.                                     */
63182   GPIO_PINCFG105_FNCSEL105_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63183   GPIO_PINCFG105_FNCSEL105_OBSBUS9     = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
63184   GPIO_PINCFG105_FNCSEL105_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63185   GPIO_PINCFG105_FNCSEL105_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63186   GPIO_PINCFG105_FNCSEL105_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63187   GPIO_PINCFG105_FNCSEL105_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63188   GPIO_PINCFG105_FNCSEL105_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63189   GPIO_PINCFG105_FNCSEL105_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63190   GPIO_PINCFG105_FNCSEL105_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63191 } GPIO_PINCFG105_FNCSEL105_Enum;
63192 
63193 /* =======================================================  PINCFG106  ======================================================= */
63194 /* ============================================  GPIO PINCFG106 OUTCFG106 [8..9]  ============================================ */
63195 typedef enum {                                  /*!< GPIO_PINCFG106_OUTCFG106                                                  */
63196   GPIO_PINCFG106_OUTCFG106_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63197   GPIO_PINCFG106_OUTCFG106_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63198                                                      and 1 values on pin.                                                      */
63199   GPIO_PINCFG106_OUTCFG106_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63200                                                      low, tristate otherwise.                                                  */
63201   GPIO_PINCFG106_OUTCFG106_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63202                                                      drive 0, 1 of HiZ on pin.                                                 */
63203 } GPIO_PINCFG106_OUTCFG106_Enum;
63204 
63205 /* ============================================  GPIO PINCFG106 IRPTEN106 [6..7]  ============================================ */
63206 typedef enum {                                  /*!< GPIO_PINCFG106_IRPTEN106                                                  */
63207   GPIO_PINCFG106_IRPTEN106_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63208   GPIO_PINCFG106_IRPTEN106_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63209                                                      on this GPIO                                                              */
63210   GPIO_PINCFG106_IRPTEN106_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63211                                                      on this GPIO                                                              */
63212   GPIO_PINCFG106_IRPTEN106_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63213                                                      GPIO                                                                      */
63214 } GPIO_PINCFG106_IRPTEN106_Enum;
63215 
63216 /* ============================================  GPIO PINCFG106 FNCSEL106 [0..3]  ============================================ */
63217 typedef enum {                                  /*!< GPIO_PINCFG106_FNCSEL106                                                  */
63218   GPIO_PINCFG106_FNCSEL106_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63219   GPIO_PINCFG106_FNCSEL106_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63220   GPIO_PINCFG106_FNCSEL106_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63221   GPIO_PINCFG106_FNCSEL106_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63222   GPIO_PINCFG106_FNCSEL106_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63223   GPIO_PINCFG106_FNCSEL106_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63224   GPIO_PINCFG106_FNCSEL106_CT106       = 6,     /*!< CT106 : Timer/Counter input or output; Selection of direction
63225                                                      is done via CTIMER register settings.                                     */
63226   GPIO_PINCFG106_FNCSEL106_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63227   GPIO_PINCFG106_FNCSEL106_OBSBUS10    = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
63228   GPIO_PINCFG106_FNCSEL106_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63229   GPIO_PINCFG106_FNCSEL106_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63230   GPIO_PINCFG106_FNCSEL106_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63231   GPIO_PINCFG106_FNCSEL106_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63232   GPIO_PINCFG106_FNCSEL106_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63233   GPIO_PINCFG106_FNCSEL106_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63234   GPIO_PINCFG106_FNCSEL106_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63235 } GPIO_PINCFG106_FNCSEL106_Enum;
63236 
63237 /* =======================================================  PINCFG107  ======================================================= */
63238 /* ============================================  GPIO PINCFG107 OUTCFG107 [8..9]  ============================================ */
63239 typedef enum {                                  /*!< GPIO_PINCFG107_OUTCFG107                                                  */
63240   GPIO_PINCFG107_OUTCFG107_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63241   GPIO_PINCFG107_OUTCFG107_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63242                                                      and 1 values on pin.                                                      */
63243   GPIO_PINCFG107_OUTCFG107_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63244                                                      low, tristate otherwise.                                                  */
63245   GPIO_PINCFG107_OUTCFG107_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63246                                                      drive 0, 1 of HiZ on pin.                                                 */
63247 } GPIO_PINCFG107_OUTCFG107_Enum;
63248 
63249 /* ============================================  GPIO PINCFG107 IRPTEN107 [6..7]  ============================================ */
63250 typedef enum {                                  /*!< GPIO_PINCFG107_IRPTEN107                                                  */
63251   GPIO_PINCFG107_IRPTEN107_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63252   GPIO_PINCFG107_IRPTEN107_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63253                                                      on this GPIO                                                              */
63254   GPIO_PINCFG107_IRPTEN107_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63255                                                      on this GPIO                                                              */
63256   GPIO_PINCFG107_IRPTEN107_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63257                                                      GPIO                                                                      */
63258 } GPIO_PINCFG107_IRPTEN107_Enum;
63259 
63260 /* ============================================  GPIO PINCFG107 FNCSEL107 [0..3]  ============================================ */
63261 typedef enum {                                  /*!< GPIO_PINCFG107_FNCSEL107                                                  */
63262   GPIO_PINCFG107_FNCSEL107_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63263   GPIO_PINCFG107_FNCSEL107_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63264   GPIO_PINCFG107_FNCSEL107_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63265   GPIO_PINCFG107_FNCSEL107_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63266   GPIO_PINCFG107_FNCSEL107_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63267   GPIO_PINCFG107_FNCSEL107_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63268   GPIO_PINCFG107_FNCSEL107_CT107       = 6,     /*!< CT107 : Timer/Counter input or output; Selection of direction
63269                                                      is done via CTIMER register settings.                                     */
63270   GPIO_PINCFG107_FNCSEL107_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63271   GPIO_PINCFG107_FNCSEL107_OBSBUS11    = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
63272   GPIO_PINCFG107_FNCSEL107_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63273   GPIO_PINCFG107_FNCSEL107_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63274   GPIO_PINCFG107_FNCSEL107_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63275   GPIO_PINCFG107_FNCSEL107_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63276   GPIO_PINCFG107_FNCSEL107_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63277   GPIO_PINCFG107_FNCSEL107_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63278   GPIO_PINCFG107_FNCSEL107_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63279 } GPIO_PINCFG107_FNCSEL107_Enum;
63280 
63281 /* =======================================================  PINCFG108  ======================================================= */
63282 /* ============================================  GPIO PINCFG108 OUTCFG108 [8..9]  ============================================ */
63283 typedef enum {                                  /*!< GPIO_PINCFG108_OUTCFG108                                                  */
63284   GPIO_PINCFG108_OUTCFG108_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63285   GPIO_PINCFG108_OUTCFG108_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63286                                                      and 1 values on pin.                                                      */
63287   GPIO_PINCFG108_OUTCFG108_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63288                                                      low, tristate otherwise.                                                  */
63289   GPIO_PINCFG108_OUTCFG108_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63290                                                      drive 0, 1 of HiZ on pin.                                                 */
63291 } GPIO_PINCFG108_OUTCFG108_Enum;
63292 
63293 /* ============================================  GPIO PINCFG108 IRPTEN108 [6..7]  ============================================ */
63294 typedef enum {                                  /*!< GPIO_PINCFG108_IRPTEN108                                                  */
63295   GPIO_PINCFG108_IRPTEN108_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63296   GPIO_PINCFG108_IRPTEN108_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63297                                                      on this GPIO                                                              */
63298   GPIO_PINCFG108_IRPTEN108_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63299                                                      on this GPIO                                                              */
63300   GPIO_PINCFG108_IRPTEN108_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63301                                                      GPIO                                                                      */
63302 } GPIO_PINCFG108_IRPTEN108_Enum;
63303 
63304 /* ============================================  GPIO PINCFG108 FNCSEL108 [0..3]  ============================================ */
63305 typedef enum {                                  /*!< GPIO_PINCFG108_FNCSEL108                                                  */
63306   GPIO_PINCFG108_FNCSEL108_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63307   GPIO_PINCFG108_FNCSEL108_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63308   GPIO_PINCFG108_FNCSEL108_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63309   GPIO_PINCFG108_FNCSEL108_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63310   GPIO_PINCFG108_FNCSEL108_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63311   GPIO_PINCFG108_FNCSEL108_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63312   GPIO_PINCFG108_FNCSEL108_CT108       = 6,     /*!< CT108 : Timer/Counter input or output; Selection of direction
63313                                                      is done via CTIMER register settings.                                     */
63314   GPIO_PINCFG108_FNCSEL108_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63315   GPIO_PINCFG108_FNCSEL108_OBSBUS12    = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
63316   GPIO_PINCFG108_FNCSEL108_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63317   GPIO_PINCFG108_FNCSEL108_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63318   GPIO_PINCFG108_FNCSEL108_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63319   GPIO_PINCFG108_FNCSEL108_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63320   GPIO_PINCFG108_FNCSEL108_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63321   GPIO_PINCFG108_FNCSEL108_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63322   GPIO_PINCFG108_FNCSEL108_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63323 } GPIO_PINCFG108_FNCSEL108_Enum;
63324 
63325 /* =======================================================  PINCFG109  ======================================================= */
63326 /* ============================================  GPIO PINCFG109 OUTCFG109 [8..9]  ============================================ */
63327 typedef enum {                                  /*!< GPIO_PINCFG109_OUTCFG109                                                  */
63328   GPIO_PINCFG109_OUTCFG109_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63329   GPIO_PINCFG109_OUTCFG109_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63330                                                      and 1 values on pin.                                                      */
63331   GPIO_PINCFG109_OUTCFG109_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63332                                                      low, tristate otherwise.                                                  */
63333   GPIO_PINCFG109_OUTCFG109_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63334                                                      drive 0, 1 of HiZ on pin.                                                 */
63335 } GPIO_PINCFG109_OUTCFG109_Enum;
63336 
63337 /* ============================================  GPIO PINCFG109 IRPTEN109 [6..7]  ============================================ */
63338 typedef enum {                                  /*!< GPIO_PINCFG109_IRPTEN109                                                  */
63339   GPIO_PINCFG109_IRPTEN109_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63340   GPIO_PINCFG109_IRPTEN109_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63341                                                      on this GPIO                                                              */
63342   GPIO_PINCFG109_IRPTEN109_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63343                                                      on this GPIO                                                              */
63344   GPIO_PINCFG109_IRPTEN109_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63345                                                      GPIO                                                                      */
63346 } GPIO_PINCFG109_IRPTEN109_Enum;
63347 
63348 /* ============================================  GPIO PINCFG109 FNCSEL109 [0..3]  ============================================ */
63349 typedef enum {                                  /*!< GPIO_PINCFG109_FNCSEL109                                                  */
63350   GPIO_PINCFG109_FNCSEL109_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63351   GPIO_PINCFG109_FNCSEL109_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63352   GPIO_PINCFG109_FNCSEL109_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63353   GPIO_PINCFG109_FNCSEL109_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63354   GPIO_PINCFG109_FNCSEL109_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63355   GPIO_PINCFG109_FNCSEL109_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63356   GPIO_PINCFG109_FNCSEL109_CT109       = 6,     /*!< CT109 : Timer/Counter input or output; Selection of direction
63357                                                      is done via CTIMER register settings.                                     */
63358   GPIO_PINCFG109_FNCSEL109_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63359   GPIO_PINCFG109_FNCSEL109_OBSBUS13    = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
63360   GPIO_PINCFG109_FNCSEL109_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63361   GPIO_PINCFG109_FNCSEL109_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63362   GPIO_PINCFG109_FNCSEL109_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63363   GPIO_PINCFG109_FNCSEL109_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63364   GPIO_PINCFG109_FNCSEL109_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63365   GPIO_PINCFG109_FNCSEL109_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63366   GPIO_PINCFG109_FNCSEL109_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63367 } GPIO_PINCFG109_FNCSEL109_Enum;
63368 
63369 /* =======================================================  PINCFG110  ======================================================= */
63370 /* ============================================  GPIO PINCFG110 OUTCFG110 [8..9]  ============================================ */
63371 typedef enum {                                  /*!< GPIO_PINCFG110_OUTCFG110                                                  */
63372   GPIO_PINCFG110_OUTCFG110_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63373   GPIO_PINCFG110_OUTCFG110_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63374                                                      and 1 values on pin.                                                      */
63375   GPIO_PINCFG110_OUTCFG110_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63376                                                      low, tristate otherwise.                                                  */
63377   GPIO_PINCFG110_OUTCFG110_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63378                                                      drive 0, 1 of HiZ on pin.                                                 */
63379 } GPIO_PINCFG110_OUTCFG110_Enum;
63380 
63381 /* ============================================  GPIO PINCFG110 IRPTEN110 [6..7]  ============================================ */
63382 typedef enum {                                  /*!< GPIO_PINCFG110_IRPTEN110                                                  */
63383   GPIO_PINCFG110_IRPTEN110_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63384   GPIO_PINCFG110_IRPTEN110_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63385                                                      on this GPIO                                                              */
63386   GPIO_PINCFG110_IRPTEN110_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63387                                                      on this GPIO                                                              */
63388   GPIO_PINCFG110_IRPTEN110_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63389                                                      GPIO                                                                      */
63390 } GPIO_PINCFG110_IRPTEN110_Enum;
63391 
63392 /* ============================================  GPIO PINCFG110 FNCSEL110 [0..3]  ============================================ */
63393 typedef enum {                                  /*!< GPIO_PINCFG110_FNCSEL110                                                  */
63394   GPIO_PINCFG110_FNCSEL110_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63395   GPIO_PINCFG110_FNCSEL110_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63396   GPIO_PINCFG110_FNCSEL110_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63397   GPIO_PINCFG110_FNCSEL110_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63398   GPIO_PINCFG110_FNCSEL110_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63399   GPIO_PINCFG110_FNCSEL110_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63400   GPIO_PINCFG110_FNCSEL110_CT110       = 6,     /*!< CT110 : Timer/Counter input or output; Selection of direction
63401                                                      is done via CTIMER register settings.                                     */
63402   GPIO_PINCFG110_FNCSEL110_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63403   GPIO_PINCFG110_FNCSEL110_OBSBUS14    = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
63404   GPIO_PINCFG110_FNCSEL110_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63405   GPIO_PINCFG110_FNCSEL110_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63406   GPIO_PINCFG110_FNCSEL110_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63407   GPIO_PINCFG110_FNCSEL110_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63408   GPIO_PINCFG110_FNCSEL110_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63409   GPIO_PINCFG110_FNCSEL110_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63410   GPIO_PINCFG110_FNCSEL110_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63411 } GPIO_PINCFG110_FNCSEL110_Enum;
63412 
63413 /* =======================================================  PINCFG111  ======================================================= */
63414 /* ============================================  GPIO PINCFG111 OUTCFG111 [8..9]  ============================================ */
63415 typedef enum {                                  /*!< GPIO_PINCFG111_OUTCFG111                                                  */
63416   GPIO_PINCFG111_OUTCFG111_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63417   GPIO_PINCFG111_OUTCFG111_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63418                                                      and 1 values on pin.                                                      */
63419   GPIO_PINCFG111_OUTCFG111_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63420                                                      low, tristate otherwise.                                                  */
63421   GPIO_PINCFG111_OUTCFG111_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63422                                                      drive 0, 1 of HiZ on pin.                                                 */
63423 } GPIO_PINCFG111_OUTCFG111_Enum;
63424 
63425 /* ============================================  GPIO PINCFG111 IRPTEN111 [6..7]  ============================================ */
63426 typedef enum {                                  /*!< GPIO_PINCFG111_IRPTEN111                                                  */
63427   GPIO_PINCFG111_IRPTEN111_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63428   GPIO_PINCFG111_IRPTEN111_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63429                                                      on this GPIO                                                              */
63430   GPIO_PINCFG111_IRPTEN111_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63431                                                      on this GPIO                                                              */
63432   GPIO_PINCFG111_IRPTEN111_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63433                                                      GPIO                                                                      */
63434 } GPIO_PINCFG111_IRPTEN111_Enum;
63435 
63436 /* ============================================  GPIO PINCFG111 FNCSEL111 [0..3]  ============================================ */
63437 typedef enum {                                  /*!< GPIO_PINCFG111_FNCSEL111                                                  */
63438   GPIO_PINCFG111_FNCSEL111_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63439   GPIO_PINCFG111_FNCSEL111_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63440   GPIO_PINCFG111_FNCSEL111_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63441   GPIO_PINCFG111_FNCSEL111_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63442   GPIO_PINCFG111_FNCSEL111_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63443   GPIO_PINCFG111_FNCSEL111_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63444   GPIO_PINCFG111_FNCSEL111_CT111       = 6,     /*!< CT111 : Timer/Counter input or output; Selection of direction
63445                                                      is done via CTIMER register settings.                                     */
63446   GPIO_PINCFG111_FNCSEL111_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63447   GPIO_PINCFG111_FNCSEL111_OBSBUS15    = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
63448   GPIO_PINCFG111_FNCSEL111_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63449   GPIO_PINCFG111_FNCSEL111_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63450   GPIO_PINCFG111_FNCSEL111_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63451   GPIO_PINCFG111_FNCSEL111_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63452   GPIO_PINCFG111_FNCSEL111_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63453   GPIO_PINCFG111_FNCSEL111_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63454   GPIO_PINCFG111_FNCSEL111_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63455 } GPIO_PINCFG111_FNCSEL111_Enum;
63456 
63457 /* =======================================================  PINCFG112  ======================================================= */
63458 /* ============================================  GPIO PINCFG112 OUTCFG112 [8..9]  ============================================ */
63459 typedef enum {                                  /*!< GPIO_PINCFG112_OUTCFG112                                                  */
63460   GPIO_PINCFG112_OUTCFG112_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63461   GPIO_PINCFG112_OUTCFG112_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63462                                                      and 1 values on pin.                                                      */
63463   GPIO_PINCFG112_OUTCFG112_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63464                                                      low, tristate otherwise.                                                  */
63465   GPIO_PINCFG112_OUTCFG112_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63466                                                      drive 0, 1 of HiZ on pin.                                                 */
63467 } GPIO_PINCFG112_OUTCFG112_Enum;
63468 
63469 /* ============================================  GPIO PINCFG112 IRPTEN112 [6..7]  ============================================ */
63470 typedef enum {                                  /*!< GPIO_PINCFG112_IRPTEN112                                                  */
63471   GPIO_PINCFG112_IRPTEN112_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63472   GPIO_PINCFG112_IRPTEN112_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63473                                                      on this GPIO                                                              */
63474   GPIO_PINCFG112_IRPTEN112_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63475                                                      on this GPIO                                                              */
63476   GPIO_PINCFG112_IRPTEN112_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63477                                                      GPIO                                                                      */
63478 } GPIO_PINCFG112_IRPTEN112_Enum;
63479 
63480 /* ============================================  GPIO PINCFG112 FNCSEL112 [0..3]  ============================================ */
63481 typedef enum {                                  /*!< GPIO_PINCFG112_FNCSEL112                                                  */
63482   GPIO_PINCFG112_FNCSEL112_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63483   GPIO_PINCFG112_FNCSEL112_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63484   GPIO_PINCFG112_FNCSEL112_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63485   GPIO_PINCFG112_FNCSEL112_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63486   GPIO_PINCFG112_FNCSEL112_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63487   GPIO_PINCFG112_FNCSEL112_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63488   GPIO_PINCFG112_FNCSEL112_CT112       = 6,     /*!< CT112 : Timer/Counter input or output; Selection of direction
63489                                                      is done via CTIMER register settings.                                     */
63490   GPIO_PINCFG112_FNCSEL112_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63491   GPIO_PINCFG112_FNCSEL112_OBSBUS0     = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
63492   GPIO_PINCFG112_FNCSEL112_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63493   GPIO_PINCFG112_FNCSEL112_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63494   GPIO_PINCFG112_FNCSEL112_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63495   GPIO_PINCFG112_FNCSEL112_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63496   GPIO_PINCFG112_FNCSEL112_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63497   GPIO_PINCFG112_FNCSEL112_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63498   GPIO_PINCFG112_FNCSEL112_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63499 } GPIO_PINCFG112_FNCSEL112_Enum;
63500 
63501 /* =======================================================  PINCFG113  ======================================================= */
63502 /* ============================================  GPIO PINCFG113 OUTCFG113 [8..9]  ============================================ */
63503 typedef enum {                                  /*!< GPIO_PINCFG113_OUTCFG113                                                  */
63504   GPIO_PINCFG113_OUTCFG113_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63505   GPIO_PINCFG113_OUTCFG113_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63506                                                      and 1 values on pin.                                                      */
63507   GPIO_PINCFG113_OUTCFG113_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63508                                                      low, tristate otherwise.                                                  */
63509   GPIO_PINCFG113_OUTCFG113_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63510                                                      drive 0, 1 of HiZ on pin.                                                 */
63511 } GPIO_PINCFG113_OUTCFG113_Enum;
63512 
63513 /* ============================================  GPIO PINCFG113 IRPTEN113 [6..7]  ============================================ */
63514 typedef enum {                                  /*!< GPIO_PINCFG113_IRPTEN113                                                  */
63515   GPIO_PINCFG113_IRPTEN113_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63516   GPIO_PINCFG113_IRPTEN113_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63517                                                      on this GPIO                                                              */
63518   GPIO_PINCFG113_IRPTEN113_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63519                                                      on this GPIO                                                              */
63520   GPIO_PINCFG113_IRPTEN113_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63521                                                      GPIO                                                                      */
63522 } GPIO_PINCFG113_IRPTEN113_Enum;
63523 
63524 /* ============================================  GPIO PINCFG113 FNCSEL113 [0..3]  ============================================ */
63525 typedef enum {                                  /*!< GPIO_PINCFG113_FNCSEL113                                                  */
63526   GPIO_PINCFG113_FNCSEL113_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63527   GPIO_PINCFG113_FNCSEL113_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63528   GPIO_PINCFG113_FNCSEL113_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63529   GPIO_PINCFG113_FNCSEL113_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63530   GPIO_PINCFG113_FNCSEL113_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63531   GPIO_PINCFG113_FNCSEL113_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63532   GPIO_PINCFG113_FNCSEL113_CT113       = 6,     /*!< CT113 : Timer/Counter input or output; Selection of direction
63533                                                      is done via CTIMER register settings.                                     */
63534   GPIO_PINCFG113_FNCSEL113_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63535   GPIO_PINCFG113_FNCSEL113_OBSBUS1     = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
63536   GPIO_PINCFG113_FNCSEL113_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63537   GPIO_PINCFG113_FNCSEL113_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63538   GPIO_PINCFG113_FNCSEL113_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63539   GPIO_PINCFG113_FNCSEL113_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63540   GPIO_PINCFG113_FNCSEL113_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63541   GPIO_PINCFG113_FNCSEL113_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63542   GPIO_PINCFG113_FNCSEL113_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63543 } GPIO_PINCFG113_FNCSEL113_Enum;
63544 
63545 /* =======================================================  PINCFG114  ======================================================= */
63546 /* ============================================  GPIO PINCFG114 OUTCFG114 [8..9]  ============================================ */
63547 typedef enum {                                  /*!< GPIO_PINCFG114_OUTCFG114                                                  */
63548   GPIO_PINCFG114_OUTCFG114_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63549   GPIO_PINCFG114_OUTCFG114_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63550                                                      and 1 values on pin.                                                      */
63551   GPIO_PINCFG114_OUTCFG114_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63552                                                      low, tristate otherwise.                                                  */
63553   GPIO_PINCFG114_OUTCFG114_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63554                                                      drive 0, 1 of HiZ on pin.                                                 */
63555 } GPIO_PINCFG114_OUTCFG114_Enum;
63556 
63557 /* ============================================  GPIO PINCFG114 IRPTEN114 [6..7]  ============================================ */
63558 typedef enum {                                  /*!< GPIO_PINCFG114_IRPTEN114                                                  */
63559   GPIO_PINCFG114_IRPTEN114_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63560   GPIO_PINCFG114_IRPTEN114_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63561                                                      on this GPIO                                                              */
63562   GPIO_PINCFG114_IRPTEN114_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63563                                                      on this GPIO                                                              */
63564   GPIO_PINCFG114_IRPTEN114_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63565                                                      GPIO                                                                      */
63566 } GPIO_PINCFG114_IRPTEN114_Enum;
63567 
63568 /* ============================================  GPIO PINCFG114 FNCSEL114 [0..3]  ============================================ */
63569 typedef enum {                                  /*!< GPIO_PINCFG114_FNCSEL114                                                  */
63570   GPIO_PINCFG114_FNCSEL114_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63571   GPIO_PINCFG114_FNCSEL114_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63572   GPIO_PINCFG114_FNCSEL114_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63573   GPIO_PINCFG114_FNCSEL114_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63574   GPIO_PINCFG114_FNCSEL114_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63575   GPIO_PINCFG114_FNCSEL114_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63576   GPIO_PINCFG114_FNCSEL114_CT114       = 6,     /*!< CT114 : Timer/Counter input or output; Selection of direction
63577                                                      is done via CTIMER register settings.                                     */
63578   GPIO_PINCFG114_FNCSEL114_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63579   GPIO_PINCFG114_FNCSEL114_OBSBUS2     = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
63580   GPIO_PINCFG114_FNCSEL114_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63581   GPIO_PINCFG114_FNCSEL114_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63582   GPIO_PINCFG114_FNCSEL114_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63583   GPIO_PINCFG114_FNCSEL114_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63584   GPIO_PINCFG114_FNCSEL114_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63585   GPIO_PINCFG114_FNCSEL114_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63586   GPIO_PINCFG114_FNCSEL114_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63587 } GPIO_PINCFG114_FNCSEL114_Enum;
63588 
63589 /* =======================================================  PINCFG115  ======================================================= */
63590 /* ============================================  GPIO PINCFG115 OUTCFG115 [8..9]  ============================================ */
63591 typedef enum {                                  /*!< GPIO_PINCFG115_OUTCFG115                                                  */
63592   GPIO_PINCFG115_OUTCFG115_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63593   GPIO_PINCFG115_OUTCFG115_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63594                                                      and 1 values on pin.                                                      */
63595   GPIO_PINCFG115_OUTCFG115_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63596                                                      low, tristate otherwise.                                                  */
63597   GPIO_PINCFG115_OUTCFG115_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63598                                                      drive 0, 1 of HiZ on pin.                                                 */
63599 } GPIO_PINCFG115_OUTCFG115_Enum;
63600 
63601 /* ============================================  GPIO PINCFG115 IRPTEN115 [6..7]  ============================================ */
63602 typedef enum {                                  /*!< GPIO_PINCFG115_IRPTEN115                                                  */
63603   GPIO_PINCFG115_IRPTEN115_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63604   GPIO_PINCFG115_IRPTEN115_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63605                                                      on this GPIO                                                              */
63606   GPIO_PINCFG115_IRPTEN115_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63607                                                      on this GPIO                                                              */
63608   GPIO_PINCFG115_IRPTEN115_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63609                                                      GPIO                                                                      */
63610 } GPIO_PINCFG115_IRPTEN115_Enum;
63611 
63612 /* ============================================  GPIO PINCFG115 FNCSEL115 [0..3]  ============================================ */
63613 typedef enum {                                  /*!< GPIO_PINCFG115_FNCSEL115                                                  */
63614   GPIO_PINCFG115_FNCSEL115_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63615   GPIO_PINCFG115_FNCSEL115_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63616   GPIO_PINCFG115_FNCSEL115_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63617   GPIO_PINCFG115_FNCSEL115_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63618   GPIO_PINCFG115_FNCSEL115_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63619   GPIO_PINCFG115_FNCSEL115_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63620   GPIO_PINCFG115_FNCSEL115_CT115       = 6,     /*!< CT115 : Timer/Counter input or output; Selection of direction
63621                                                      is done via CTIMER register settings.                                     */
63622   GPIO_PINCFG115_FNCSEL115_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63623   GPIO_PINCFG115_FNCSEL115_OBSBUS3     = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
63624   GPIO_PINCFG115_FNCSEL115_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63625   GPIO_PINCFG115_FNCSEL115_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63626   GPIO_PINCFG115_FNCSEL115_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63627   GPIO_PINCFG115_FNCSEL115_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63628   GPIO_PINCFG115_FNCSEL115_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63629   GPIO_PINCFG115_FNCSEL115_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63630   GPIO_PINCFG115_FNCSEL115_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63631 } GPIO_PINCFG115_FNCSEL115_Enum;
63632 
63633 /* =======================================================  PINCFG116  ======================================================= */
63634 /* ============================================  GPIO PINCFG116 OUTCFG116 [8..9]  ============================================ */
63635 typedef enum {                                  /*!< GPIO_PINCFG116_OUTCFG116                                                  */
63636   GPIO_PINCFG116_OUTCFG116_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63637   GPIO_PINCFG116_OUTCFG116_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63638                                                      and 1 values on pin.                                                      */
63639   GPIO_PINCFG116_OUTCFG116_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63640                                                      low, tristate otherwise.                                                  */
63641   GPIO_PINCFG116_OUTCFG116_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63642                                                      drive 0, 1 of HiZ on pin.                                                 */
63643 } GPIO_PINCFG116_OUTCFG116_Enum;
63644 
63645 /* ============================================  GPIO PINCFG116 IRPTEN116 [6..7]  ============================================ */
63646 typedef enum {                                  /*!< GPIO_PINCFG116_IRPTEN116                                                  */
63647   GPIO_PINCFG116_IRPTEN116_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63648   GPIO_PINCFG116_IRPTEN116_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63649                                                      on this GPIO                                                              */
63650   GPIO_PINCFG116_IRPTEN116_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63651                                                      on this GPIO                                                              */
63652   GPIO_PINCFG116_IRPTEN116_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63653                                                      GPIO                                                                      */
63654 } GPIO_PINCFG116_IRPTEN116_Enum;
63655 
63656 /* ============================================  GPIO PINCFG116 FNCSEL116 [0..3]  ============================================ */
63657 typedef enum {                                  /*!< GPIO_PINCFG116_FNCSEL116                                                  */
63658   GPIO_PINCFG116_FNCSEL116_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63659   GPIO_PINCFG116_FNCSEL116_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63660   GPIO_PINCFG116_FNCSEL116_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63661   GPIO_PINCFG116_FNCSEL116_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63662   GPIO_PINCFG116_FNCSEL116_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63663   GPIO_PINCFG116_FNCSEL116_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63664   GPIO_PINCFG116_FNCSEL116_CT116       = 6,     /*!< CT116 : Timer/Counter input or output; Selection of direction
63665                                                      is done via CTIMER register settings.                                     */
63666   GPIO_PINCFG116_FNCSEL116_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63667   GPIO_PINCFG116_FNCSEL116_OBSBUS4     = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
63668   GPIO_PINCFG116_FNCSEL116_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63669   GPIO_PINCFG116_FNCSEL116_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63670   GPIO_PINCFG116_FNCSEL116_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63671   GPIO_PINCFG116_FNCSEL116_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63672   GPIO_PINCFG116_FNCSEL116_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63673   GPIO_PINCFG116_FNCSEL116_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63674   GPIO_PINCFG116_FNCSEL116_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63675 } GPIO_PINCFG116_FNCSEL116_Enum;
63676 
63677 /* =======================================================  PINCFG117  ======================================================= */
63678 /* ============================================  GPIO PINCFG117 OUTCFG117 [8..9]  ============================================ */
63679 typedef enum {                                  /*!< GPIO_PINCFG117_OUTCFG117                                                  */
63680   GPIO_PINCFG117_OUTCFG117_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63681   GPIO_PINCFG117_OUTCFG117_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63682                                                      and 1 values on pin.                                                      */
63683   GPIO_PINCFG117_OUTCFG117_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63684                                                      low, tristate otherwise.                                                  */
63685   GPIO_PINCFG117_OUTCFG117_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63686                                                      drive 0, 1 of HiZ on pin.                                                 */
63687 } GPIO_PINCFG117_OUTCFG117_Enum;
63688 
63689 /* ============================================  GPIO PINCFG117 IRPTEN117 [6..7]  ============================================ */
63690 typedef enum {                                  /*!< GPIO_PINCFG117_IRPTEN117                                                  */
63691   GPIO_PINCFG117_IRPTEN117_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63692   GPIO_PINCFG117_IRPTEN117_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63693                                                      on this GPIO                                                              */
63694   GPIO_PINCFG117_IRPTEN117_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63695                                                      on this GPIO                                                              */
63696   GPIO_PINCFG117_IRPTEN117_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63697                                                      GPIO                                                                      */
63698 } GPIO_PINCFG117_IRPTEN117_Enum;
63699 
63700 /* ============================================  GPIO PINCFG117 FNCSEL117 [0..3]  ============================================ */
63701 typedef enum {                                  /*!< GPIO_PINCFG117_FNCSEL117                                                  */
63702   GPIO_PINCFG117_FNCSEL117_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63703   GPIO_PINCFG117_FNCSEL117_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63704   GPIO_PINCFG117_FNCSEL117_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63705   GPIO_PINCFG117_FNCSEL117_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63706   GPIO_PINCFG117_FNCSEL117_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63707   GPIO_PINCFG117_FNCSEL117_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63708   GPIO_PINCFG117_FNCSEL117_CT117       = 6,     /*!< CT117 : Timer/Counter input or output; Selection of direction
63709                                                      is done via CTIMER register settings.                                     */
63710   GPIO_PINCFG117_FNCSEL117_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63711   GPIO_PINCFG117_FNCSEL117_OBSBUS5     = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
63712   GPIO_PINCFG117_FNCSEL117_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63713   GPIO_PINCFG117_FNCSEL117_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63714   GPIO_PINCFG117_FNCSEL117_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63715   GPIO_PINCFG117_FNCSEL117_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63716   GPIO_PINCFG117_FNCSEL117_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63717   GPIO_PINCFG117_FNCSEL117_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63718   GPIO_PINCFG117_FNCSEL117_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63719 } GPIO_PINCFG117_FNCSEL117_Enum;
63720 
63721 /* =======================================================  PINCFG118  ======================================================= */
63722 /* ============================================  GPIO PINCFG118 OUTCFG118 [8..9]  ============================================ */
63723 typedef enum {                                  /*!< GPIO_PINCFG118_OUTCFG118                                                  */
63724   GPIO_PINCFG118_OUTCFG118_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63725   GPIO_PINCFG118_OUTCFG118_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63726                                                      and 1 values on pin.                                                      */
63727   GPIO_PINCFG118_OUTCFG118_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63728                                                      low, tristate otherwise.                                                  */
63729   GPIO_PINCFG118_OUTCFG118_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63730                                                      drive 0, 1 of HiZ on pin.                                                 */
63731 } GPIO_PINCFG118_OUTCFG118_Enum;
63732 
63733 /* ============================================  GPIO PINCFG118 IRPTEN118 [6..7]  ============================================ */
63734 typedef enum {                                  /*!< GPIO_PINCFG118_IRPTEN118                                                  */
63735   GPIO_PINCFG118_IRPTEN118_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63736   GPIO_PINCFG118_IRPTEN118_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63737                                                      on this GPIO                                                              */
63738   GPIO_PINCFG118_IRPTEN118_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63739                                                      on this GPIO                                                              */
63740   GPIO_PINCFG118_IRPTEN118_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63741                                                      GPIO                                                                      */
63742 } GPIO_PINCFG118_IRPTEN118_Enum;
63743 
63744 /* ============================================  GPIO PINCFG118 FNCSEL118 [0..3]  ============================================ */
63745 typedef enum {                                  /*!< GPIO_PINCFG118_FNCSEL118                                                  */
63746   GPIO_PINCFG118_FNCSEL118_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63747   GPIO_PINCFG118_FNCSEL118_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63748   GPIO_PINCFG118_FNCSEL118_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63749   GPIO_PINCFG118_FNCSEL118_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63750   GPIO_PINCFG118_FNCSEL118_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63751   GPIO_PINCFG118_FNCSEL118_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63752   GPIO_PINCFG118_FNCSEL118_CT118       = 6,     /*!< CT118 : Timer/Counter input or output; Selection of direction
63753                                                      is done via CTIMER register settings.                                     */
63754   GPIO_PINCFG118_FNCSEL118_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63755   GPIO_PINCFG118_FNCSEL118_OBSBUS6     = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
63756   GPIO_PINCFG118_FNCSEL118_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63757   GPIO_PINCFG118_FNCSEL118_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63758   GPIO_PINCFG118_FNCSEL118_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63759   GPIO_PINCFG118_FNCSEL118_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63760   GPIO_PINCFG118_FNCSEL118_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63761   GPIO_PINCFG118_FNCSEL118_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63762   GPIO_PINCFG118_FNCSEL118_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63763 } GPIO_PINCFG118_FNCSEL118_Enum;
63764 
63765 /* =======================================================  PINCFG119  ======================================================= */
63766 /* ============================================  GPIO PINCFG119 OUTCFG119 [8..9]  ============================================ */
63767 typedef enum {                                  /*!< GPIO_PINCFG119_OUTCFG119                                                  */
63768   GPIO_PINCFG119_OUTCFG119_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63769   GPIO_PINCFG119_OUTCFG119_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63770                                                      and 1 values on pin.                                                      */
63771   GPIO_PINCFG119_OUTCFG119_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63772                                                      low, tristate otherwise.                                                  */
63773   GPIO_PINCFG119_OUTCFG119_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63774                                                      drive 0, 1 of HiZ on pin.                                                 */
63775 } GPIO_PINCFG119_OUTCFG119_Enum;
63776 
63777 /* ============================================  GPIO PINCFG119 IRPTEN119 [6..7]  ============================================ */
63778 typedef enum {                                  /*!< GPIO_PINCFG119_IRPTEN119                                                  */
63779   GPIO_PINCFG119_IRPTEN119_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63780   GPIO_PINCFG119_IRPTEN119_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63781                                                      on this GPIO                                                              */
63782   GPIO_PINCFG119_IRPTEN119_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63783                                                      on this GPIO                                                              */
63784   GPIO_PINCFG119_IRPTEN119_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63785                                                      GPIO                                                                      */
63786 } GPIO_PINCFG119_IRPTEN119_Enum;
63787 
63788 /* ============================================  GPIO PINCFG119 FNCSEL119 [0..3]  ============================================ */
63789 typedef enum {                                  /*!< GPIO_PINCFG119_FNCSEL119                                                  */
63790   GPIO_PINCFG119_FNCSEL119_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63791   GPIO_PINCFG119_FNCSEL119_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63792   GPIO_PINCFG119_FNCSEL119_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63793   GPIO_PINCFG119_FNCSEL119_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63794   GPIO_PINCFG119_FNCSEL119_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63795   GPIO_PINCFG119_FNCSEL119_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63796   GPIO_PINCFG119_FNCSEL119_CT119       = 6,     /*!< CT119 : Timer/Counter input or output; Selection of direction
63797                                                      is done via CTIMER register settings.                                     */
63798   GPIO_PINCFG119_FNCSEL119_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63799   GPIO_PINCFG119_FNCSEL119_OBSBUS7     = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
63800   GPIO_PINCFG119_FNCSEL119_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63801   GPIO_PINCFG119_FNCSEL119_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63802   GPIO_PINCFG119_FNCSEL119_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63803   GPIO_PINCFG119_FNCSEL119_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63804   GPIO_PINCFG119_FNCSEL119_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63805   GPIO_PINCFG119_FNCSEL119_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63806   GPIO_PINCFG119_FNCSEL119_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63807 } GPIO_PINCFG119_FNCSEL119_Enum;
63808 
63809 /* =======================================================  PINCFG120  ======================================================= */
63810 /* ============================================  GPIO PINCFG120 OUTCFG120 [8..9]  ============================================ */
63811 typedef enum {                                  /*!< GPIO_PINCFG120_OUTCFG120                                                  */
63812   GPIO_PINCFG120_OUTCFG120_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63813   GPIO_PINCFG120_OUTCFG120_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63814                                                      and 1 values on pin.                                                      */
63815   GPIO_PINCFG120_OUTCFG120_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63816                                                      low, tristate otherwise.                                                  */
63817   GPIO_PINCFG120_OUTCFG120_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63818                                                      drive 0, 1 of HiZ on pin.                                                 */
63819 } GPIO_PINCFG120_OUTCFG120_Enum;
63820 
63821 /* ============================================  GPIO PINCFG120 IRPTEN120 [6..7]  ============================================ */
63822 typedef enum {                                  /*!< GPIO_PINCFG120_IRPTEN120                                                  */
63823   GPIO_PINCFG120_IRPTEN120_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63824   GPIO_PINCFG120_IRPTEN120_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63825                                                      on this GPIO                                                              */
63826   GPIO_PINCFG120_IRPTEN120_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63827                                                      on this GPIO                                                              */
63828   GPIO_PINCFG120_IRPTEN120_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63829                                                      GPIO                                                                      */
63830 } GPIO_PINCFG120_IRPTEN120_Enum;
63831 
63832 /* ============================================  GPIO PINCFG120 FNCSEL120 [0..3]  ============================================ */
63833 typedef enum {                                  /*!< GPIO_PINCFG120_FNCSEL120                                                  */
63834   GPIO_PINCFG120_FNCSEL120_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63835   GPIO_PINCFG120_FNCSEL120_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63836   GPIO_PINCFG120_FNCSEL120_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63837   GPIO_PINCFG120_FNCSEL120_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63838   GPIO_PINCFG120_FNCSEL120_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63839   GPIO_PINCFG120_FNCSEL120_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63840   GPIO_PINCFG120_FNCSEL120_CT120       = 6,     /*!< CT120 : Timer/Counter input or output; Selection of direction
63841                                                      is done via CTIMER register settings.                                     */
63842   GPIO_PINCFG120_FNCSEL120_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63843   GPIO_PINCFG120_FNCSEL120_OBSBUS8     = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
63844   GPIO_PINCFG120_FNCSEL120_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63845   GPIO_PINCFG120_FNCSEL120_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63846   GPIO_PINCFG120_FNCSEL120_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63847   GPIO_PINCFG120_FNCSEL120_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63848   GPIO_PINCFG120_FNCSEL120_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63849   GPIO_PINCFG120_FNCSEL120_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63850   GPIO_PINCFG120_FNCSEL120_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63851 } GPIO_PINCFG120_FNCSEL120_Enum;
63852 
63853 /* =======================================================  PINCFG121  ======================================================= */
63854 /* ============================================  GPIO PINCFG121 OUTCFG121 [8..9]  ============================================ */
63855 typedef enum {                                  /*!< GPIO_PINCFG121_OUTCFG121                                                  */
63856   GPIO_PINCFG121_OUTCFG121_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63857   GPIO_PINCFG121_OUTCFG121_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63858                                                      and 1 values on pin.                                                      */
63859   GPIO_PINCFG121_OUTCFG121_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63860                                                      low, tristate otherwise.                                                  */
63861   GPIO_PINCFG121_OUTCFG121_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63862                                                      drive 0, 1 of HiZ on pin.                                                 */
63863 } GPIO_PINCFG121_OUTCFG121_Enum;
63864 
63865 /* ============================================  GPIO PINCFG121 IRPTEN121 [6..7]  ============================================ */
63866 typedef enum {                                  /*!< GPIO_PINCFG121_IRPTEN121                                                  */
63867   GPIO_PINCFG121_IRPTEN121_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63868   GPIO_PINCFG121_IRPTEN121_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63869                                                      on this GPIO                                                              */
63870   GPIO_PINCFG121_IRPTEN121_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63871                                                      on this GPIO                                                              */
63872   GPIO_PINCFG121_IRPTEN121_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63873                                                      GPIO                                                                      */
63874 } GPIO_PINCFG121_IRPTEN121_Enum;
63875 
63876 /* ============================================  GPIO PINCFG121 FNCSEL121 [0..3]  ============================================ */
63877 typedef enum {                                  /*!< GPIO_PINCFG121_FNCSEL121                                                  */
63878   GPIO_PINCFG121_FNCSEL121_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63879   GPIO_PINCFG121_FNCSEL121_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63880   GPIO_PINCFG121_FNCSEL121_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63881   GPIO_PINCFG121_FNCSEL121_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63882   GPIO_PINCFG121_FNCSEL121_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63883   GPIO_PINCFG121_FNCSEL121_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63884   GPIO_PINCFG121_FNCSEL121_CT121       = 6,     /*!< CT121 : Timer/Counter input or output; Selection of direction
63885                                                      is done via CTIMER register settings.                                     */
63886   GPIO_PINCFG121_FNCSEL121_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63887   GPIO_PINCFG121_FNCSEL121_OBSBUS9     = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
63888   GPIO_PINCFG121_FNCSEL121_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63889   GPIO_PINCFG121_FNCSEL121_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63890   GPIO_PINCFG121_FNCSEL121_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63891   GPIO_PINCFG121_FNCSEL121_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63892   GPIO_PINCFG121_FNCSEL121_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63893   GPIO_PINCFG121_FNCSEL121_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63894   GPIO_PINCFG121_FNCSEL121_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63895 } GPIO_PINCFG121_FNCSEL121_Enum;
63896 
63897 /* =======================================================  PINCFG122  ======================================================= */
63898 /* ============================================  GPIO PINCFG122 OUTCFG122 [8..9]  ============================================ */
63899 typedef enum {                                  /*!< GPIO_PINCFG122_OUTCFG122                                                  */
63900   GPIO_PINCFG122_OUTCFG122_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63901   GPIO_PINCFG122_OUTCFG122_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63902                                                      and 1 values on pin.                                                      */
63903   GPIO_PINCFG122_OUTCFG122_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63904                                                      low, tristate otherwise.                                                  */
63905   GPIO_PINCFG122_OUTCFG122_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63906                                                      drive 0, 1 of HiZ on pin.                                                 */
63907 } GPIO_PINCFG122_OUTCFG122_Enum;
63908 
63909 /* ============================================  GPIO PINCFG122 IRPTEN122 [6..7]  ============================================ */
63910 typedef enum {                                  /*!< GPIO_PINCFG122_IRPTEN122                                                  */
63911   GPIO_PINCFG122_IRPTEN122_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63912   GPIO_PINCFG122_IRPTEN122_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63913                                                      on this GPIO                                                              */
63914   GPIO_PINCFG122_IRPTEN122_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63915                                                      on this GPIO                                                              */
63916   GPIO_PINCFG122_IRPTEN122_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63917                                                      GPIO                                                                      */
63918 } GPIO_PINCFG122_IRPTEN122_Enum;
63919 
63920 /* ============================================  GPIO PINCFG122 FNCSEL122 [0..3]  ============================================ */
63921 typedef enum {                                  /*!< GPIO_PINCFG122_FNCSEL122                                                  */
63922   GPIO_PINCFG122_FNCSEL122_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63923   GPIO_PINCFG122_FNCSEL122_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63924   GPIO_PINCFG122_FNCSEL122_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63925   GPIO_PINCFG122_FNCSEL122_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63926   GPIO_PINCFG122_FNCSEL122_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63927   GPIO_PINCFG122_FNCSEL122_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63928   GPIO_PINCFG122_FNCSEL122_CT122       = 6,     /*!< CT122 : Timer/Counter input or output; Selection of direction
63929                                                      is done via CTIMER register settings.                                     */
63930   GPIO_PINCFG122_FNCSEL122_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63931   GPIO_PINCFG122_FNCSEL122_OBSBUS10    = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
63932   GPIO_PINCFG122_FNCSEL122_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63933   GPIO_PINCFG122_FNCSEL122_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63934   GPIO_PINCFG122_FNCSEL122_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63935   GPIO_PINCFG122_FNCSEL122_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63936   GPIO_PINCFG122_FNCSEL122_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63937   GPIO_PINCFG122_FNCSEL122_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63938   GPIO_PINCFG122_FNCSEL122_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63939 } GPIO_PINCFG122_FNCSEL122_Enum;
63940 
63941 /* =======================================================  PINCFG123  ======================================================= */
63942 /* ============================================  GPIO PINCFG123 OUTCFG123 [8..9]  ============================================ */
63943 typedef enum {                                  /*!< GPIO_PINCFG123_OUTCFG123                                                  */
63944   GPIO_PINCFG123_OUTCFG123_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63945   GPIO_PINCFG123_OUTCFG123_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63946                                                      and 1 values on pin.                                                      */
63947   GPIO_PINCFG123_OUTCFG123_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63948                                                      low, tristate otherwise.                                                  */
63949   GPIO_PINCFG123_OUTCFG123_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63950                                                      drive 0, 1 of HiZ on pin.                                                 */
63951 } GPIO_PINCFG123_OUTCFG123_Enum;
63952 
63953 /* ============================================  GPIO PINCFG123 IRPTEN123 [6..7]  ============================================ */
63954 typedef enum {                                  /*!< GPIO_PINCFG123_IRPTEN123                                                  */
63955   GPIO_PINCFG123_IRPTEN123_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
63956   GPIO_PINCFG123_IRPTEN123_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
63957                                                      on this GPIO                                                              */
63958   GPIO_PINCFG123_IRPTEN123_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
63959                                                      on this GPIO                                                              */
63960   GPIO_PINCFG123_IRPTEN123_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
63961                                                      GPIO                                                                      */
63962 } GPIO_PINCFG123_IRPTEN123_Enum;
63963 
63964 /* ============================================  GPIO PINCFG123 FNCSEL123 [0..3]  ============================================ */
63965 typedef enum {                                  /*!< GPIO_PINCFG123_FNCSEL123                                                  */
63966   GPIO_PINCFG123_FNCSEL123_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
63967   GPIO_PINCFG123_FNCSEL123_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
63968   GPIO_PINCFG123_FNCSEL123_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
63969   GPIO_PINCFG123_FNCSEL123_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
63970   GPIO_PINCFG123_FNCSEL123_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
63971   GPIO_PINCFG123_FNCSEL123_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
63972   GPIO_PINCFG123_FNCSEL123_CT123       = 6,     /*!< CT123 : Timer/Counter input or output; Selection of direction
63973                                                      is done via CTIMER register settings.                                     */
63974   GPIO_PINCFG123_FNCSEL123_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
63975   GPIO_PINCFG123_FNCSEL123_OBSBUS11    = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
63976   GPIO_PINCFG123_FNCSEL123_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
63977   GPIO_PINCFG123_FNCSEL123_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
63978   GPIO_PINCFG123_FNCSEL123_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
63979   GPIO_PINCFG123_FNCSEL123_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
63980   GPIO_PINCFG123_FNCSEL123_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
63981   GPIO_PINCFG123_FNCSEL123_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
63982   GPIO_PINCFG123_FNCSEL123_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
63983 } GPIO_PINCFG123_FNCSEL123_Enum;
63984 
63985 /* =======================================================  PINCFG124  ======================================================= */
63986 /* ============================================  GPIO PINCFG124 OUTCFG124 [8..9]  ============================================ */
63987 typedef enum {                                  /*!< GPIO_PINCFG124_OUTCFG124                                                  */
63988   GPIO_PINCFG124_OUTCFG124_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
63989   GPIO_PINCFG124_OUTCFG124_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
63990                                                      and 1 values on pin.                                                      */
63991   GPIO_PINCFG124_OUTCFG124_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
63992                                                      low, tristate otherwise.                                                  */
63993   GPIO_PINCFG124_OUTCFG124_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
63994                                                      drive 0, 1 of HiZ on pin.                                                 */
63995 } GPIO_PINCFG124_OUTCFG124_Enum;
63996 
63997 /* ============================================  GPIO PINCFG124 IRPTEN124 [6..7]  ============================================ */
63998 typedef enum {                                  /*!< GPIO_PINCFG124_IRPTEN124                                                  */
63999   GPIO_PINCFG124_IRPTEN124_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
64000   GPIO_PINCFG124_IRPTEN124_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
64001                                                      on this GPIO                                                              */
64002   GPIO_PINCFG124_IRPTEN124_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
64003                                                      on this GPIO                                                              */
64004   GPIO_PINCFG124_IRPTEN124_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
64005                                                      GPIO                                                                      */
64006 } GPIO_PINCFG124_IRPTEN124_Enum;
64007 
64008 /* ============================================  GPIO PINCFG124 FNCSEL124 [0..3]  ============================================ */
64009 typedef enum {                                  /*!< GPIO_PINCFG124_FNCSEL124                                                  */
64010   GPIO_PINCFG124_FNCSEL124_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
64011   GPIO_PINCFG124_FNCSEL124_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
64012   GPIO_PINCFG124_FNCSEL124_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
64013   GPIO_PINCFG124_FNCSEL124_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
64014   GPIO_PINCFG124_FNCSEL124_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
64015   GPIO_PINCFG124_FNCSEL124_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
64016   GPIO_PINCFG124_FNCSEL124_CT124       = 6,     /*!< CT124 : Timer/Counter input or output; Selection of direction
64017                                                      is done via CTIMER register settings.                                     */
64018   GPIO_PINCFG124_FNCSEL124_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
64019   GPIO_PINCFG124_FNCSEL124_OBSBUS12    = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
64020   GPIO_PINCFG124_FNCSEL124_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
64021   GPIO_PINCFG124_FNCSEL124_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
64022   GPIO_PINCFG124_FNCSEL124_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
64023   GPIO_PINCFG124_FNCSEL124_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
64024   GPIO_PINCFG124_FNCSEL124_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
64025   GPIO_PINCFG124_FNCSEL124_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
64026   GPIO_PINCFG124_FNCSEL124_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
64027 } GPIO_PINCFG124_FNCSEL124_Enum;
64028 
64029 /* =======================================================  PINCFG125  ======================================================= */
64030 /* ============================================  GPIO PINCFG125 OUTCFG125 [8..9]  ============================================ */
64031 typedef enum {                                  /*!< GPIO_PINCFG125_OUTCFG125                                                  */
64032   GPIO_PINCFG125_OUTCFG125_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
64033   GPIO_PINCFG125_OUTCFG125_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
64034                                                      and 1 values on pin.                                                      */
64035   GPIO_PINCFG125_OUTCFG125_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
64036                                                      low, tristate otherwise.                                                  */
64037   GPIO_PINCFG125_OUTCFG125_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
64038                                                      drive 0, 1 of HiZ on pin.                                                 */
64039 } GPIO_PINCFG125_OUTCFG125_Enum;
64040 
64041 /* ============================================  GPIO PINCFG125 IRPTEN125 [6..7]  ============================================ */
64042 typedef enum {                                  /*!< GPIO_PINCFG125_IRPTEN125                                                  */
64043   GPIO_PINCFG125_IRPTEN125_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
64044   GPIO_PINCFG125_IRPTEN125_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
64045                                                      on this GPIO                                                              */
64046   GPIO_PINCFG125_IRPTEN125_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
64047                                                      on this GPIO                                                              */
64048   GPIO_PINCFG125_IRPTEN125_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
64049                                                      GPIO                                                                      */
64050 } GPIO_PINCFG125_IRPTEN125_Enum;
64051 
64052 /* ============================================  GPIO PINCFG125 FNCSEL125 [0..3]  ============================================ */
64053 typedef enum {                                  /*!< GPIO_PINCFG125_FNCSEL125                                                  */
64054   GPIO_PINCFG125_FNCSEL125_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
64055   GPIO_PINCFG125_FNCSEL125_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
64056   GPIO_PINCFG125_FNCSEL125_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
64057   GPIO_PINCFG125_FNCSEL125_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
64058   GPIO_PINCFG125_FNCSEL125_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
64059   GPIO_PINCFG125_FNCSEL125_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
64060   GPIO_PINCFG125_FNCSEL125_CT125       = 6,     /*!< CT125 : Timer/Counter input or output; Selection of direction
64061                                                      is done via CTIMER register settings.                                     */
64062   GPIO_PINCFG125_FNCSEL125_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
64063   GPIO_PINCFG125_FNCSEL125_OBSBUS13    = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
64064   GPIO_PINCFG125_FNCSEL125_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
64065   GPIO_PINCFG125_FNCSEL125_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
64066   GPIO_PINCFG125_FNCSEL125_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
64067   GPIO_PINCFG125_FNCSEL125_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
64068   GPIO_PINCFG125_FNCSEL125_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
64069   GPIO_PINCFG125_FNCSEL125_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
64070   GPIO_PINCFG125_FNCSEL125_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
64071 } GPIO_PINCFG125_FNCSEL125_Enum;
64072 
64073 /* =======================================================  PINCFG126  ======================================================= */
64074 /* ============================================  GPIO PINCFG126 OUTCFG126 [8..9]  ============================================ */
64075 typedef enum {                                  /*!< GPIO_PINCFG126_OUTCFG126                                                  */
64076   GPIO_PINCFG126_OUTCFG126_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
64077   GPIO_PINCFG126_OUTCFG126_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
64078                                                      and 1 values on pin.                                                      */
64079   GPIO_PINCFG126_OUTCFG126_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
64080                                                      low, tristate otherwise.                                                  */
64081   GPIO_PINCFG126_OUTCFG126_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
64082                                                      drive 0, 1 of HiZ on pin.                                                 */
64083 } GPIO_PINCFG126_OUTCFG126_Enum;
64084 
64085 /* ============================================  GPIO PINCFG126 IRPTEN126 [6..7]  ============================================ */
64086 typedef enum {                                  /*!< GPIO_PINCFG126_IRPTEN126                                                  */
64087   GPIO_PINCFG126_IRPTEN126_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
64088   GPIO_PINCFG126_IRPTEN126_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
64089                                                      on this GPIO                                                              */
64090   GPIO_PINCFG126_IRPTEN126_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
64091                                                      on this GPIO                                                              */
64092   GPIO_PINCFG126_IRPTEN126_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
64093                                                      GPIO                                                                      */
64094 } GPIO_PINCFG126_IRPTEN126_Enum;
64095 
64096 /* ============================================  GPIO PINCFG126 FNCSEL126 [0..3]  ============================================ */
64097 typedef enum {                                  /*!< GPIO_PINCFG126_FNCSEL126                                                  */
64098   GPIO_PINCFG126_FNCSEL126_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
64099   GPIO_PINCFG126_FNCSEL126_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
64100   GPIO_PINCFG126_FNCSEL126_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
64101   GPIO_PINCFG126_FNCSEL126_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
64102   GPIO_PINCFG126_FNCSEL126_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
64103   GPIO_PINCFG126_FNCSEL126_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
64104   GPIO_PINCFG126_FNCSEL126_CT126       = 6,     /*!< CT126 : Timer/Counter input or output; Selection of direction
64105                                                      is done via CTIMER register settings.                                     */
64106   GPIO_PINCFG126_FNCSEL126_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
64107   GPIO_PINCFG126_FNCSEL126_OBSBUS14    = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
64108   GPIO_PINCFG126_FNCSEL126_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
64109   GPIO_PINCFG126_FNCSEL126_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
64110   GPIO_PINCFG126_FNCSEL126_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
64111   GPIO_PINCFG126_FNCSEL126_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
64112   GPIO_PINCFG126_FNCSEL126_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
64113   GPIO_PINCFG126_FNCSEL126_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
64114   GPIO_PINCFG126_FNCSEL126_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
64115 } GPIO_PINCFG126_FNCSEL126_Enum;
64116 
64117 /* =======================================================  PINCFG127  ======================================================= */
64118 /* ============================================  GPIO PINCFG127 OUTCFG127 [8..9]  ============================================ */
64119 typedef enum {                                  /*!< GPIO_PINCFG127_OUTCFG127                                                  */
64120   GPIO_PINCFG127_OUTCFG127_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
64121   GPIO_PINCFG127_OUTCFG127_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
64122                                                      and 1 values on pin.                                                      */
64123   GPIO_PINCFG127_OUTCFG127_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
64124                                                      low, tristate otherwise.                                                  */
64125   GPIO_PINCFG127_OUTCFG127_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
64126                                                      drive 0, 1 of HiZ on pin.                                                 */
64127 } GPIO_PINCFG127_OUTCFG127_Enum;
64128 
64129 /* ============================================  GPIO PINCFG127 IRPTEN127 [6..7]  ============================================ */
64130 typedef enum {                                  /*!< GPIO_PINCFG127_IRPTEN127                                                  */
64131   GPIO_PINCFG127_IRPTEN127_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
64132   GPIO_PINCFG127_IRPTEN127_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
64133                                                      on this GPIO                                                              */
64134   GPIO_PINCFG127_IRPTEN127_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
64135                                                      on this GPIO                                                              */
64136   GPIO_PINCFG127_IRPTEN127_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
64137                                                      GPIO                                                                      */
64138 } GPIO_PINCFG127_IRPTEN127_Enum;
64139 
64140 /* ============================================  GPIO PINCFG127 FNCSEL127 [0..3]  ============================================ */
64141 typedef enum {                                  /*!< GPIO_PINCFG127_FNCSEL127                                                  */
64142   GPIO_PINCFG127_FNCSEL127_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
64143   GPIO_PINCFG127_FNCSEL127_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
64144   GPIO_PINCFG127_FNCSEL127_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
64145   GPIO_PINCFG127_FNCSEL127_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
64146   GPIO_PINCFG127_FNCSEL127_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
64147   GPIO_PINCFG127_FNCSEL127_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
64148   GPIO_PINCFG127_FNCSEL127_CT127       = 6,     /*!< CT127 : Timer/Counter input or output; Selection of direction
64149                                                      is done via CTIMER register settings.                                     */
64150   GPIO_PINCFG127_FNCSEL127_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
64151   GPIO_PINCFG127_FNCSEL127_OBSBUS15    = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
64152   GPIO_PINCFG127_FNCSEL127_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
64153   GPIO_PINCFG127_FNCSEL127_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
64154   GPIO_PINCFG127_FNCSEL127_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
64155   GPIO_PINCFG127_FNCSEL127_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
64156   GPIO_PINCFG127_FNCSEL127_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
64157   GPIO_PINCFG127_FNCSEL127_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
64158   GPIO_PINCFG127_FNCSEL127_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
64159 } GPIO_PINCFG127_FNCSEL127_Enum;
64160 
64161 /* ========================================================  PADKEY  ========================================================= */
64162 /* ==============================================  GPIO PADKEY PADKEY [0..31]  =============================================== */
64163 typedef enum {                                  /*!< GPIO_PADKEY_PADKEY                                                        */
64164   GPIO_PADKEY_PADKEY_Key               = 115,   /*!< Key : Key value to unlock the register.                                   */
64165 } GPIO_PADKEY_PADKEY_Enum;
64166 
64167 /* ==========================================================  RD0  ========================================================== */
64168 /* ==========================================================  RD1  ========================================================== */
64169 /* ==========================================================  RD2  ========================================================== */
64170 /* ==========================================================  RD3  ========================================================== */
64171 /* ==========================================================  WT0  ========================================================== */
64172 /* ==========================================================  WT1  ========================================================== */
64173 /* ==========================================================  WT2  ========================================================== */
64174 /* ==========================================================  WT3  ========================================================== */
64175 /* =========================================================  WTS0  ========================================================== */
64176 /* =========================================================  WTS1  ========================================================== */
64177 /* =========================================================  WTS2  ========================================================== */
64178 /* =========================================================  WTS3  ========================================================== */
64179 /* =========================================================  WTC0  ========================================================== */
64180 /* =========================================================  WTC1  ========================================================== */
64181 /* =========================================================  WTC2  ========================================================== */
64182 /* =========================================================  WTC3  ========================================================== */
64183 /* ==========================================================  EN0  ========================================================== */
64184 /* ==========================================================  EN1  ========================================================== */
64185 /* ==========================================================  EN2  ========================================================== */
64186 /* ==========================================================  EN3  ========================================================== */
64187 /* =========================================================  ENS0  ========================================================== */
64188 /* =========================================================  ENS1  ========================================================== */
64189 /* =========================================================  ENS2  ========================================================== */
64190 /* =========================================================  ENS3  ========================================================== */
64191 /* =========================================================  ENC0  ========================================================== */
64192 /* =========================================================  ENC1  ========================================================== */
64193 /* =========================================================  ENC2  ========================================================== */
64194 /* =========================================================  ENC3  ========================================================== */
64195 /* ========================================================  IOM0IRQ  ======================================================== */
64196 /* ========================================================  IOM1IRQ  ======================================================== */
64197 /* ========================================================  IOM2IRQ  ======================================================== */
64198 /* ========================================================  IOM3IRQ  ======================================================== */
64199 /* ========================================================  IOM4IRQ  ======================================================== */
64200 /* ========================================================  IOM5IRQ  ======================================================== */
64201 /* ========================================================  IOM6IRQ  ======================================================== */
64202 /* ========================================================  IOM7IRQ  ======================================================== */
64203 /* =======================================================  SDIFCDWP  ======================================================== */
64204 /* ========================================================  OBSDATA  ======================================================== */
64205 /* ========================================================  IEOBS0  ========================================================= */
64206 /* ========================================================  IEOBS1  ========================================================= */
64207 /* ========================================================  IEOBS2  ========================================================= */
64208 /* ========================================================  IEOBS3  ========================================================= */
64209 /* ========================================================  OEOBS0  ========================================================= */
64210 /* ========================================================  OEOBS1  ========================================================= */
64211 /* ========================================================  OEOBS2  ========================================================= */
64212 /* ========================================================  OEOBS3  ========================================================= */
64213 /* ======================================================  MCUN0INT0EN  ====================================================== */
64214 /* =====================================================  MCUN0INT0STAT  ===================================================== */
64215 /* =====================================================  MCUN0INT0CLR  ====================================================== */
64216 /* =====================================================  MCUN0INT0SET  ====================================================== */
64217 /* ======================================================  MCUN0INT1EN  ====================================================== */
64218 /* =====================================================  MCUN0INT1STAT  ===================================================== */
64219 /* =====================================================  MCUN0INT1CLR  ====================================================== */
64220 /* =====================================================  MCUN0INT1SET  ====================================================== */
64221 /* ======================================================  MCUN0INT2EN  ====================================================== */
64222 /* =====================================================  MCUN0INT2STAT  ===================================================== */
64223 /* =====================================================  MCUN0INT2CLR  ====================================================== */
64224 /* =====================================================  MCUN0INT2SET  ====================================================== */
64225 /* ======================================================  MCUN0INT3EN  ====================================================== */
64226 /* =====================================================  MCUN0INT3STAT  ===================================================== */
64227 /* =====================================================  MCUN0INT3CLR  ====================================================== */
64228 /* =====================================================  MCUN0INT3SET  ====================================================== */
64229 /* ======================================================  MCUN1INT0EN  ====================================================== */
64230 /* =====================================================  MCUN1INT0STAT  ===================================================== */
64231 /* =====================================================  MCUN1INT0CLR  ====================================================== */
64232 /* =====================================================  MCUN1INT0SET  ====================================================== */
64233 /* ======================================================  MCUN1INT1EN  ====================================================== */
64234 /* =====================================================  MCUN1INT1STAT  ===================================================== */
64235 /* =====================================================  MCUN1INT1CLR  ====================================================== */
64236 /* =====================================================  MCUN1INT1SET  ====================================================== */
64237 /* ======================================================  MCUN1INT2EN  ====================================================== */
64238 /* =====================================================  MCUN1INT2STAT  ===================================================== */
64239 /* =====================================================  MCUN1INT2CLR  ====================================================== */
64240 /* =====================================================  MCUN1INT2SET  ====================================================== */
64241 /* ======================================================  MCUN1INT3EN  ====================================================== */
64242 /* =====================================================  MCUN1INT3STAT  ===================================================== */
64243 /* =====================================================  MCUN1INT3CLR  ====================================================== */
64244 /* =====================================================  MCUN1INT3SET  ====================================================== */
64245 /* =====================================================  DSP0N0INT0EN  ====================================================== */
64246 /* ====================================================  DSP0N0INT0STAT  ===================================================== */
64247 /* =====================================================  DSP0N0INT0CLR  ===================================================== */
64248 /* =====================================================  DSP0N0INT0SET  ===================================================== */
64249 /* =====================================================  DSP0N0INT1EN  ====================================================== */
64250 /* ====================================================  DSP0N0INT1STAT  ===================================================== */
64251 /* =====================================================  DSP0N0INT1CLR  ===================================================== */
64252 /* =====================================================  DSP0N0INT1SET  ===================================================== */
64253 /* =====================================================  DSP0N0INT2EN  ====================================================== */
64254 /* ====================================================  DSP0N0INT2STAT  ===================================================== */
64255 /* =====================================================  DSP0N0INT2CLR  ===================================================== */
64256 /* =====================================================  DSP0N0INT2SET  ===================================================== */
64257 /* =====================================================  DSP0N0INT3EN  ====================================================== */
64258 /* ====================================================  DSP0N0INT3STAT  ===================================================== */
64259 /* =====================================================  DSP0N0INT3CLR  ===================================================== */
64260 /* =====================================================  DSP0N0INT3SET  ===================================================== */
64261 /* =====================================================  DSP0N1INT0EN  ====================================================== */
64262 /* ====================================================  DSP0N1INT0STAT  ===================================================== */
64263 /* =====================================================  DSP0N1INT0CLR  ===================================================== */
64264 /* =====================================================  DSP0N1INT0SET  ===================================================== */
64265 /* =====================================================  DSP0N1INT1EN  ====================================================== */
64266 /* ====================================================  DSP0N1INT1STAT  ===================================================== */
64267 /* =====================================================  DSP0N1INT1CLR  ===================================================== */
64268 /* =====================================================  DSP0N1INT1SET  ===================================================== */
64269 /* =====================================================  DSP0N1INT2EN  ====================================================== */
64270 /* ====================================================  DSP0N1INT2STAT  ===================================================== */
64271 /* =====================================================  DSP0N1INT2CLR  ===================================================== */
64272 /* =====================================================  DSP0N1INT2SET  ===================================================== */
64273 /* =====================================================  DSP0N1INT3EN  ====================================================== */
64274 /* ====================================================  DSP0N1INT3STAT  ===================================================== */
64275 /* =====================================================  DSP0N1INT3CLR  ===================================================== */
64276 /* =====================================================  DSP0N1INT3SET  ===================================================== */
64277 /* =====================================================  DSP1N0INT0EN  ====================================================== */
64278 /* ====================================================  DSP1N0INT0STAT  ===================================================== */
64279 /* =====================================================  DSP1N0INT0CLR  ===================================================== */
64280 /* =====================================================  DSP1N0INT0SET  ===================================================== */
64281 /* =====================================================  DSP1N0INT1EN  ====================================================== */
64282 /* ====================================================  DSP1N0INT1STAT  ===================================================== */
64283 /* =====================================================  DSP1N0INT1CLR  ===================================================== */
64284 /* =====================================================  DSP1N0INT1SET  ===================================================== */
64285 /* =====================================================  DSP1N0INT2EN  ====================================================== */
64286 /* ====================================================  DSP1N0INT2STAT  ===================================================== */
64287 /* =====================================================  DSP1N0INT2CLR  ===================================================== */
64288 /* =====================================================  DSP1N0INT2SET  ===================================================== */
64289 /* =====================================================  DSP1N0INT3EN  ====================================================== */
64290 /* ====================================================  DSP1N0INT3STAT  ===================================================== */
64291 /* =====================================================  DSP1N0INT3CLR  ===================================================== */
64292 /* =====================================================  DSP1N0INT3SET  ===================================================== */
64293 /* =====================================================  DSP1N1INT0EN  ====================================================== */
64294 /* ====================================================  DSP1N1INT0STAT  ===================================================== */
64295 /* =====================================================  DSP1N1INT0CLR  ===================================================== */
64296 /* =====================================================  DSP1N1INT0SET  ===================================================== */
64297 /* =====================================================  DSP1N1INT1EN  ====================================================== */
64298 /* ====================================================  DSP1N1INT1STAT  ===================================================== */
64299 /* =====================================================  DSP1N1INT1CLR  ===================================================== */
64300 /* =====================================================  DSP1N1INT1SET  ===================================================== */
64301 /* =====================================================  DSP1N1INT2EN  ====================================================== */
64302 /* ====================================================  DSP1N1INT2STAT  ===================================================== */
64303 /* =====================================================  DSP1N1INT2CLR  ===================================================== */
64304 /* =====================================================  DSP1N1INT2SET  ===================================================== */
64305 /* =====================================================  DSP1N1INT3EN  ====================================================== */
64306 /* ====================================================  DSP1N1INT3STAT  ===================================================== */
64307 /* =====================================================  DSP1N1INT3CLR  ===================================================== */
64308 /* =====================================================  DSP1N1INT3SET  ===================================================== */
64309 
64310 
64311 /* =========================================================================================================================== */
64312 /* ================                                            GPU                                            ================ */
64313 /* =========================================================================================================================== */
64314 
64315 /* =======================================================  TEX0BASE  ======================================================== */
64316 /* ======================================================  TEX0STRIDE  ======================================================= */
64317 /* ============================================  GPU TEX0STRIDE IMGFMT [24..31]  ============================================= */
64318 typedef enum {                                  /*!< GPU_TEX0STRIDE_IMGFMT                                                     */
64319   GPU_TEX0STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
64320                                                      has an alpha channel, but it is ignored, and is always
64321                                                      set to 255. The RGBX 32 bit RGB format is stored in memory
64322                                                      as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
64323                                                      bits.                                                                     */
64324   GPU_TEX0STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
64325                                                      is always on: 32-bit)                                                     */
64326   GPU_TEX0STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
64327   GPU_TEX0STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
64328                                                      intensity of each channel sample is defined by 8 bits,
64329                                                      and are arranged in memory in such manner that a single
64330                                                      32-bit unsigned integer has the alpha sample in the highest
64331                                                      8 bits, followed by the red sample, green sample and finally
64332                                                      the blue sample in the lowest 8 bits                                      */
64333   GPU_TEX0STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
64334   GPU_TEX0STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
64335   GPU_TEX0STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
64336   GPU_TEX0STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
64337   GPU_TEX0STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
64338   GPU_TEX0STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
64339 } GPU_TEX0STRIDE_IMGFMT_Enum;
64340 
64341 /* ============================================  GPU TEX0STRIDE IMGMODE [16..23]  ============================================ */
64342 typedef enum {                                  /*!< GPU_TEX0STRIDE_IMGMODE                                                    */
64343   GPU_TEX0STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
64344                                                      bitmap image. Nearest neighbor sampling.                                  */
64345   GPU_TEX0STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
64346                                                      a bitmap image. A method used to smooth textures when displayed
64347                                                      larger or smaller than they actually are.                                 */
64348 } GPU_TEX0STRIDE_IMGMODE_Enum;
64349 
64350 /* ========================================================  TEX0RES  ======================================================== */
64351 /* =======================================================  TEX1BASE  ======================================================== */
64352 /* ======================================================  TEX1STRIDE  ======================================================= */
64353 /* ============================================  GPU TEX1STRIDE IMGFMT [24..31]  ============================================= */
64354 typedef enum {                                  /*!< GPU_TEX1STRIDE_IMGFMT                                                     */
64355   GPU_TEX1STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
64356                                                      has an alpha channel, but it is ignored, and is always
64357                                                      set to 255. The RGBX 32 bit RGB format is stored in memory
64358                                                      as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
64359                                                      bits.                                                                     */
64360   GPU_TEX1STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
64361                                                      is always on: 32-bit)                                                     */
64362   GPU_TEX1STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
64363   GPU_TEX1STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
64364                                                      intensity of each channel sample is defined by 8 bits,
64365                                                      and are arranged in memory in such manner that a single
64366                                                      32-bit unsigned integer has the alpha sample in the highest
64367                                                      8 bits, followed by the red sample, green sample and finally
64368                                                      the blue sample in the lowest 8 bits                                      */
64369   GPU_TEX1STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
64370   GPU_TEX1STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
64371   GPU_TEX1STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
64372   GPU_TEX1STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
64373   GPU_TEX1STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
64374   GPU_TEX1STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
64375 } GPU_TEX1STRIDE_IMGFMT_Enum;
64376 
64377 /* ============================================  GPU TEX1STRIDE IMGMODE [16..23]  ============================================ */
64378 typedef enum {                                  /*!< GPU_TEX1STRIDE_IMGMODE                                                    */
64379   GPU_TEX1STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
64380                                                      bitmap image. Nearest neighbor sampling.                                  */
64381   GPU_TEX1STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
64382                                                      a bitmap image. A method used to smooth textures when displayed
64383                                                      larger or smaller than they actually are.                                 */
64384 } GPU_TEX1STRIDE_IMGMODE_Enum;
64385 
64386 /* ========================================================  TEX1RES  ======================================================== */
64387 /* =======================================================  TEX1COLOR  ======================================================= */
64388 /* =======================================================  TEX2BASE  ======================================================== */
64389 /* ======================================================  TEX2STRIDE  ======================================================= */
64390 /* ============================================  GPU TEX2STRIDE IMGFMT [24..31]  ============================================= */
64391 typedef enum {                                  /*!< GPU_TEX2STRIDE_IMGFMT                                                     */
64392   GPU_TEX2STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
64393                                                      has an alpha channel, but it is ignored, and is always
64394                                                      set to 255. The RGBX 32 bit RGB format is stored in memory
64395                                                      as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
64396                                                      bits.                                                                     */
64397   GPU_TEX2STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
64398                                                      is always on: 32-bit)                                                     */
64399   GPU_TEX2STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
64400   GPU_TEX2STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
64401                                                      intensity of each channel sample is defined by 8 bits,
64402                                                      and are arranged in memory in such manner that a single
64403                                                      32-bit unsigned integer has the alpha sample in the highest
64404                                                      8 bits, followed by the red sample, green sample and finally
64405                                                      the blue sample in the lowest 8 bits                                      */
64406   GPU_TEX2STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
64407   GPU_TEX2STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
64408   GPU_TEX2STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
64409   GPU_TEX2STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
64410   GPU_TEX2STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
64411   GPU_TEX2STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
64412 } GPU_TEX2STRIDE_IMGFMT_Enum;
64413 
64414 /* ============================================  GPU TEX2STRIDE IMGMODE [16..23]  ============================================ */
64415 typedef enum {                                  /*!< GPU_TEX2STRIDE_IMGMODE                                                    */
64416   GPU_TEX2STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
64417                                                      bitmap image. Nearest neighbor sampling.                                  */
64418   GPU_TEX2STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
64419                                                      a bitmap image. A method used to smooth textures when displayed
64420                                                      larger or smaller than they actually are.                                 */
64421 } GPU_TEX2STRIDE_IMGMODE_Enum;
64422 
64423 /* ========================================================  TEX2RES  ======================================================== */
64424 /* =======================================================  TEX3BASE  ======================================================== */
64425 /* ======================================================  TEX3STRIDE  ======================================================= */
64426 /* ============================================  GPU TEX3STRIDE IMGFMT [24..31]  ============================================= */
64427 typedef enum {                                  /*!< GPU_TEX3STRIDE_IMGFMT                                                     */
64428   GPU_TEX3STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
64429                                                      has an alpha channel, but it is ignored, and is always
64430                                                      set to 255. The RGBX 32 bit RGB format is stored in memory
64431                                                      as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
64432                                                      bits.                                                                     */
64433   GPU_TEX3STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
64434                                                      is always on: 32-bit)                                                     */
64435   GPU_TEX3STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
64436   GPU_TEX3STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
64437                                                      intensity of each channel sample is defined by 8 bits,
64438                                                      and are arranged in memory in such manner that a single
64439                                                      32-bit unsigned integer has the alpha sample in the highest
64440                                                      8 bits, followed by the red sample, green sample and finally
64441                                                      the blue sample in the lowest 8 bits                                      */
64442   GPU_TEX3STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
64443   GPU_TEX3STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
64444   GPU_TEX3STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
64445   GPU_TEX3STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
64446   GPU_TEX3STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
64447   GPU_TEX3STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
64448 } GPU_TEX3STRIDE_IMGFMT_Enum;
64449 
64450 /* ============================================  GPU TEX3STRIDE IMGMODE [16..23]  ============================================ */
64451 typedef enum {                                  /*!< GPU_TEX3STRIDE_IMGMODE                                                    */
64452   GPU_TEX3STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
64453                                                      bitmap image.                                                             */
64454   GPU_TEX3STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
64455                                                      a bitmap image. A method used to smooth textures when displayed
64456                                                      larger or smaller than they actually are.                                 */
64457 } GPU_TEX3STRIDE_IMGMODE_Enum;
64458 
64459 /* ========================================================  TEX3RES  ======================================================== */
64460 /* =========================================================  CGCMD  ========================================================= */
64461 /* ========================================================  CGCTRL  ========================================================= */
64462 /* =====================================================  DIRTYTRIGMIN  ====================================================== */
64463 /* =====================================================  DIRTYTRIGMAX  ====================================================== */
64464 /* ========================================================  STATUS  ========================================================= */
64465 /* ========================================================  BUSCTRL  ======================================================== */
64466 /* ======================================================  IMEMLDIADDR  ====================================================== */
64467 /* =====================================================  IMEMLDIDATAHL  ===================================================== */
64468 /* =====================================================  IMEMLDIDATAHH  ===================================================== */
64469 /* =====================================================  CMDLISTSTATUS  ===================================================== */
64470 /* ====================================================  CMDLISTRINGSTOP  ==================================================== */
64471 /* ======================================================  CMDLISTADDR  ====================================================== */
64472 /* ======================================================  CMDLISTSIZE  ====================================================== */
64473 /* =====================================================  INTERRUPTCTRL  ===================================================== */
64474 /* =======================================================  SYSCLEAR  ======================================================== */
64475 /* ========================================================  DRAWCMD  ======================================================== */
64476 /* ===============================================  GPU DRAWCMD START [0..2]  ================================================ */
64477 typedef enum {                                  /*!< GPU_DRAWCMD_START                                                         */
64478   GPU_DRAWCMD_START_PIXEL              = 0,     /*!< PIXEL : draw pixel using STARTXY                                          */
64479   GPU_DRAWCMD_START_LINE               = 1,     /*!< LINE : draw line from STARTXY to ENDXY                                    */
64480   GPU_DRAWCMD_START_RECT               = 2,     /*!< RECT : fill rectangle from STARTXY to ENDXY                               */
64481   GPU_DRAWCMD_START_TRI                = 3,     /*!< TRI : draw triangle (if enabled)                                          */
64482   GPU_DRAWCMD_START_QUAD               = 4,     /*!< QUAD : draw quadrilateral (if enabled)                                    */
64483 } GPU_DRAWCMD_START_Enum;
64484 
64485 /* ========================================================  DRAWPT0  ======================================================== */
64486 /* ========================================================  DRAWPT1  ======================================================== */
64487 /* ========================================================  CLIPMIN  ======================================================== */
64488 /* ========================================================  CLIPMAX  ======================================================== */
64489 /* =======================================================  RASTCTRL  ======================================================== */
64490 /* ======================================================  DRAWCODEPTR  ====================================================== */
64491 /* =======================================================  DRAWPT0X  ======================================================== */
64492 /* =======================================================  DRAWPT0Y  ======================================================== */
64493 /* =======================================================  DRAWPT0Z  ======================================================== */
64494 /* =======================================================  DRAWCOLOR  ======================================================= */
64495 /* =======================================================  DRAWPT1X  ======================================================== */
64496 /* =======================================================  DRAWPT1Y  ======================================================== */
64497 /* =======================================================  DRAWPT1Z  ======================================================== */
64498 /* =======================================================  DRAWPT2X  ======================================================== */
64499 /* =======================================================  DRAWPT2Y  ======================================================== */
64500 /* =======================================================  DRAWPT2Z  ======================================================== */
64501 /* =======================================================  DRAWPT3X  ======================================================== */
64502 /* =======================================================  DRAWPT3Y  ======================================================== */
64503 /* =======================================================  DRAWPT3Z  ======================================================== */
64504 /* =========================================================  MM00  ========================================================== */
64505 /* =========================================================  MM01  ========================================================== */
64506 /* =========================================================  MM02  ========================================================== */
64507 /* =========================================================  MM10  ========================================================== */
64508 /* =========================================================  MM11  ========================================================== */
64509 /* =========================================================  MM12  ========================================================== */
64510 /* =========================================================  MM20  ========================================================== */
64511 /* =========================================================  MM21  ========================================================== */
64512 /* =========================================================  MM22  ========================================================== */
64513 /* ======================================================  DEPTHSTARTL  ====================================================== */
64514 /* ======================================================  DEPTHSTARTH  ====================================================== */
64515 /* =======================================================  DEPTHDXL  ======================================================== */
64516 /* =======================================================  DEPTHDXH  ======================================================== */
64517 /* =======================================================  DEPTHDYL  ======================================================== */
64518 /* =======================================================  DEPTHDYH  ======================================================== */
64519 /* =========================================================  REDX  ========================================================== */
64520 /* =========================================================  REDY  ========================================================== */
64521 /* ========================================================  GREENX  ========================================================= */
64522 /* ========================================================  GREENY  ========================================================= */
64523 /* =========================================================  BLUEX  ========================================================= */
64524 /* =========================================================  BLUEY  ========================================================= */
64525 /* =========================================================  ALFX  ========================================================== */
64526 /* =========================================================  ALFY  ========================================================== */
64527 /* ========================================================  REDINIT  ======================================================== */
64528 /* ========================================================  GREINIT  ======================================================== */
64529 /* ========================================================  BLUINIT  ======================================================== */
64530 /* ========================================================  ALFINIT  ======================================================== */
64531 /* =========================================================  IDREG  ========================================================= */
64532 /* =======================================================  LOADCTRL  ======================================================== */
64533 /* =========================================================  C0REG  ========================================================= */
64534 /* =========================================================  C1REG  ========================================================= */
64535 /* =========================================================  C2REG  ========================================================= */
64536 /* =========================================================  C3REG  ========================================================= */
64537 /* =========================================================  IRQID  ========================================================= */
64538 
64539 
64540 /* =========================================================================================================================== */
64541 /* ================                                           I2S0                                            ================ */
64542 /* =========================================================================================================================== */
64543 
64544 /* ========================================================  RXDATA  ========================================================= */
64545 /* =======================================================  RXCHANID  ======================================================== */
64546 /* =====================================================  RXFIFOSTATUS  ====================================================== */
64547 /* ======================================================  RXFIFOSIZE  ======================================================= */
64548 /* =====================================================  RXUPPERLIMIT  ====================================================== */
64549 /* ========================================================  TXDATA  ========================================================= */
64550 /* =======================================================  TXCHANID  ======================================================== */
64551 /* =====================================================  TXFIFOSTATUS  ====================================================== */
64552 /* ======================================================  TXFIFOSIZE  ======================================================= */
64553 /* =====================================================  TXLOWERLIMIT  ====================================================== */
64554 /* ======================================================  I2SDATACFG  ======================================================= */
64555 /* ============================================  I2S0 I2SDATACFG FRLEN2 [24..30]  ============================================ */
64556 typedef enum {                                  /*!< I2S0_I2SDATACFG_FRLEN2                                                    */
64557   I2S0_I2SDATACFG_FRLEN2_1CHLS         = 0,     /*!< 1CHLS : One channel in phase 2.                                           */
64558   I2S0_I2SDATACFG_FRLEN2_2CHLS         = 1,     /*!< 2CHLS : Two channels in phase 2.                                          */
64559   I2S0_I2SDATACFG_FRLEN2_3CHLS         = 2,     /*!< 3CHLS : Three channels in phase 2.                                        */
64560   I2S0_I2SDATACFG_FRLEN2_4CHLS         = 3,     /*!< 4CHLS : Four channels in phase 2.                                         */
64561   I2S0_I2SDATACFG_FRLEN2_5CHLS         = 4,     /*!< 5CHLS : Five channels in phase 2.                                         */
64562   I2S0_I2SDATACFG_FRLEN2_6CHLS         = 5,     /*!< 6CHLS : Six channels in phase 2.                                          */
64563   I2S0_I2SDATACFG_FRLEN2_7CHLS         = 6,     /*!< 7CHLS : Seven channels in phase 2.                                        */
64564   I2S0_I2SDATACFG_FRLEN2_8CHLS         = 7,     /*!< 8CHLS : Eight channels in phase 2.                                        */
64565 } I2S0_I2SDATACFG_FRLEN2_Enum;
64566 
64567 /* ============================================  I2S0 I2SDATACFG WDLEN2 [21..23]  ============================================ */
64568 typedef enum {                                  /*!< I2S0_I2SDATACFG_WDLEN2                                                    */
64569   I2S0_I2SDATACFG_WDLEN2_8b            = 0,     /*!< 8b : Receive channel length is 8 bits for phase 2.                        */
64570   I2S0_I2SDATACFG_WDLEN2_16b           = 2,     /*!< 16b : Receive channel length is 16 bits for phase 2.                      */
64571   I2S0_I2SDATACFG_WDLEN2_24b           = 4,     /*!< 24b : Receive channel length is 24 bits for phase 2.                      */
64572   I2S0_I2SDATACFG_WDLEN2_32b           = 5,     /*!< 32b : Receive channel length is 32 bits for phase 2.                      */
64573 } I2S0_I2SDATACFG_WDLEN2_Enum;
64574 
64575 /* =============================================  I2S0 I2SDATACFG SSZ2 [16..18]  ============================================= */
64576 typedef enum {                                  /*!< I2S0_I2SDATACFG_SSZ2                                                      */
64577   I2S0_I2SDATACFG_SSZ2_8b              = 0,     /*!< 8b : Receive audio sample length is 8 bits for phase 2.                   */
64578   I2S0_I2SDATACFG_SSZ2_16b             = 2,     /*!< 16b : Receive audio sample length is 16 bits for phase 2.                 */
64579   I2S0_I2SDATACFG_SSZ2_24b             = 4,     /*!< 24b : Receive audio sample length is 24 bits for phase 2.                 */
64580   I2S0_I2SDATACFG_SSZ2_32b             = 5,     /*!< 32b : Receive audio sample length is 32 bits for phase 2.                 */
64581 } I2S0_I2SDATACFG_SSZ2_Enum;
64582 
64583 /* ============================================  I2S0 I2SDATACFG FRLEN1 [8..14]  ============================================= */
64584 typedef enum {                                  /*!< I2S0_I2SDATACFG_FRLEN1                                                    */
64585   I2S0_I2SDATACFG_FRLEN1_1CHLS         = 0,     /*!< 1CHLS : One channel in phase 1.                                           */
64586   I2S0_I2SDATACFG_FRLEN1_2CHLS         = 1,     /*!< 2CHLS : Two channels in phase 1.                                          */
64587   I2S0_I2SDATACFG_FRLEN1_3CHLS         = 2,     /*!< 3CHLS : Three channels in phase 1.                                        */
64588   I2S0_I2SDATACFG_FRLEN1_4CHLS         = 3,     /*!< 4CHLS : Four channels in phase 1.                                         */
64589   I2S0_I2SDATACFG_FRLEN1_5CHLS         = 4,     /*!< 5CHLS : Five channels in phase 1.                                         */
64590   I2S0_I2SDATACFG_FRLEN1_6CHLS         = 5,     /*!< 6CHLS : Six channels in phase 1.                                          */
64591   I2S0_I2SDATACFG_FRLEN1_7CHLS         = 6,     /*!< 7CHLS : Seven channels in phase 1.                                        */
64592   I2S0_I2SDATACFG_FRLEN1_8CHLS         = 7,     /*!< 8CHLS : Eight channels in phase 1.                                        */
64593 } I2S0_I2SDATACFG_FRLEN1_Enum;
64594 
64595 /* =============================================  I2S0 I2SDATACFG WDLEN1 [5..7]  ============================================= */
64596 typedef enum {                                  /*!< I2S0_I2SDATACFG_WDLEN1                                                    */
64597   I2S0_I2SDATACFG_WDLEN1_8b            = 0,     /*!< 8b : Receive channel length is 8 bits for phase 1.                        */
64598   I2S0_I2SDATACFG_WDLEN1_16b           = 2,     /*!< 16b : Receive channel length is 16 bits for phase 1.                      */
64599   I2S0_I2SDATACFG_WDLEN1_24b           = 4,     /*!< 24b : Receive channel length is 24 bits for phase 1.                      */
64600   I2S0_I2SDATACFG_WDLEN1_32b           = 5,     /*!< 32b : Receive channel length is 32 bits for phase 1.                      */
64601 } I2S0_I2SDATACFG_WDLEN1_Enum;
64602 
64603 /* ==============================================  I2S0 I2SDATACFG SSZ1 [0..2]  ============================================== */
64604 typedef enum {                                  /*!< I2S0_I2SDATACFG_SSZ1                                                      */
64605   I2S0_I2SDATACFG_SSZ1_8b              = 0,     /*!< 8b : Receive audio sample length is 8 bits for phase 1.                   */
64606   I2S0_I2SDATACFG_SSZ1_16b             = 2,     /*!< 16b : Receive audio sample length is 16 bits for phase 1.                 */
64607   I2S0_I2SDATACFG_SSZ1_24b             = 4,     /*!< 24b : Receive audio sample length is 24 bits for phase 1.                 */
64608   I2S0_I2SDATACFG_SSZ1_32b             = 5,     /*!< 32b : Receive audio sample length is 32 bits for phase 1.                 */
64609 } I2S0_I2SDATACFG_SSZ1_Enum;
64610 
64611 /* =======================================================  I2SIOCFG  ======================================================== */
64612 /* ========================================================  I2SCTL  ========================================================= */
64613 /* ========================================================  IPBIRPT  ======================================================== */
64614 /* =======================================================  IPCOREID  ======================================================== */
64615 /* ========================================================  AMQCFG  ========================================================= */
64616 /* ========================================================  INTDIV  ========================================================= */
64617 /* ========================================================  FRACDIV  ======================================================== */
64618 /* ========================================================  CLKCFG  ========================================================= */
64619 /* ========================================================  DMACFG  ========================================================= */
64620 /* ==============================================  I2S0 DMACFG TXDMAPRI [5..5]  ============================================== */
64621 typedef enum {                                  /*!< I2S0_DMACFG_TXDMAPRI                                                      */
64622   I2S0_DMACFG_TXDMAPRI_LOW             = 0,     /*!< LOW : Low Priority (service as best effort)                               */
64623   I2S0_DMACFG_TXDMAPRI_HIGH            = 1,     /*!< HIGH : High Priority (service immediately)                                */
64624 } I2S0_DMACFG_TXDMAPRI_Enum;
64625 
64626 /* ==============================================  I2S0 DMACFG TXDMAEN [4..4]  =============================================== */
64627 typedef enum {                                  /*!< I2S0_DMACFG_TXDMAEN                                                       */
64628   I2S0_DMACFG_TXDMAEN_DIS              = 0,     /*!< DIS : Disable TXDMA Function                                              */
64629   I2S0_DMACFG_TXDMAEN_EN               = 1,     /*!< EN : Enable TXDMA Function                                                */
64630 } I2S0_DMACFG_TXDMAEN_Enum;
64631 
64632 /* ==============================================  I2S0 DMACFG RXDMAPRI [1..1]  ============================================== */
64633 typedef enum {                                  /*!< I2S0_DMACFG_RXDMAPRI                                                      */
64634   I2S0_DMACFG_RXDMAPRI_LOW             = 0,     /*!< LOW : Low Priority (service as best effort)                               */
64635   I2S0_DMACFG_RXDMAPRI_HIGH            = 1,     /*!< HIGH : High Priority (service immediately)                                */
64636 } I2S0_DMACFG_RXDMAPRI_Enum;
64637 
64638 /* ==============================================  I2S0 DMACFG RXDMAEN [0..0]  =============================================== */
64639 typedef enum {                                  /*!< I2S0_DMACFG_RXDMAEN                                                       */
64640   I2S0_DMACFG_RXDMAEN_DIS              = 0,     /*!< DIS : Disable RXDMA Function                                              */
64641   I2S0_DMACFG_RXDMAEN_EN               = 1,     /*!< EN : Enable RXDMA Function                                                */
64642 } I2S0_DMACFG_RXDMAEN_Enum;
64643 
64644 /* ======================================================  RXDMATOTCNT  ====================================================== */
64645 /* =======================================================  RXDMAADDR  ======================================================= */
64646 /* =======================================================  RXDMASTAT  ======================================================= */
64647 /* ======================================================  TXDMATOTCNT  ====================================================== */
64648 /* =======================================================  TXDMAADDR  ======================================================= */
64649 /* =======================================================  TXDMASTAT  ======================================================= */
64650 /* ========================================================  STATUS  ========================================================= */
64651 /* =========================================================  INTEN  ========================================================= */
64652 /* ========================================================  INTSTAT  ======================================================== */
64653 /* ========================================================  INTCLR  ========================================================= */
64654 /* ========================================================  INTSET  ========================================================= */
64655 /* ========================================================  I2SDBG  ========================================================= */
64656 
64657 
64658 /* =========================================================================================================================== */
64659 /* ================                                           IOM0                                            ================ */
64660 /* =========================================================================================================================== */
64661 
64662 /* =========================================================  FIFO  ========================================================== */
64663 /* ========================================================  FIFOPTR  ======================================================== */
64664 /* ========================================================  FIFOTHR  ======================================================== */
64665 /* ========================================================  FIFOPOP  ======================================================== */
64666 /* =======================================================  FIFOPUSH  ======================================================== */
64667 /* =======================================================  FIFOCTRL  ======================================================== */
64668 /* ========================================================  FIFOLOC  ======================================================== */
64669 /* ========================================================  CLKCFG  ========================================================= */
64670 /* ==============================================  IOM0 CLKCFG DIVEN [12..12]  =============================================== */
64671 typedef enum {                                  /*!< IOM0_CLKCFG_DIVEN                                                         */
64672   IOM0_CLKCFG_DIVEN_DIS                = 0,     /*!< DIS : Disable TOTPER division.                                            */
64673   IOM0_CLKCFG_DIVEN_EN                 = 1,     /*!< EN : Enable TOTPER division.                                              */
64674 } IOM0_CLKCFG_DIVEN_Enum;
64675 
64676 /* ===============================================  IOM0 CLKCFG DIV3 [11..11]  =============================================== */
64677 typedef enum {                                  /*!< IOM0_CLKCFG_DIV3                                                          */
64678   IOM0_CLKCFG_DIV3_DIS                 = 0,     /*!< DIS : Select divide by 1.                                                 */
64679   IOM0_CLKCFG_DIV3_EN                  = 1,     /*!< EN : Select divide by 3.                                                  */
64680 } IOM0_CLKCFG_DIV3_Enum;
64681 
64682 /* ===============================================  IOM0 CLKCFG FSEL [8..10]  ================================================ */
64683 typedef enum {                                  /*!< IOM0_CLKCFG_FSEL                                                          */
64684   IOM0_CLKCFG_FSEL_MIN_PWR             = 0,     /*!< MIN_PWR : Selects the minimum power clock. This setting should
64685                                                      be used whenever the IOM is not active.                                   */
64686   IOM0_CLKCFG_FSEL_OFF                 = 1,     /*!< OFF : Selects static 0 as the input clock. Previously 96Mhz
64687                                                      setting                                                                   */
64688   IOM0_CLKCFG_FSEL_HFRC48MHZ           = 2,     /*!< HFRC48MHZ : Selects the HFRC 48MHz as the input clock.                    */
64689   IOM0_CLKCFG_FSEL_HFRC24MHZ           = 3,     /*!< HFRC24MHZ : Selects the HFRC 24MHz as the input clock.                    */
64690   IOM0_CLKCFG_FSEL_HFRC12MHZ           = 4,     /*!< HFRC12MHZ : Selects the HFRC 12MHz as the input clock.                    */
64691   IOM0_CLKCFG_FSEL_HFRC6MHZ            = 5,     /*!< HFRC6MHZ : Selects the HFRC 6MHz as the input clock.                      */
64692   IOM0_CLKCFG_FSEL_HFRC3MHZ            = 6,     /*!< HFRC3MHZ : Selects the HFRC 3MHz as the input clock.                      */
64693   IOM0_CLKCFG_FSEL_HFRC1p5MHZ          = 7,     /*!< HFRC1p5MHZ : Selects the HFRC 1.5MHz as the input clock.                  */
64694 } IOM0_CLKCFG_FSEL_Enum;
64695 
64696 /* ======================================================  SUBMODCTRL  ======================================================= */
64697 /* ===========================================  IOM0 SUBMODCTRL SMOD2TYPE [9..11]  =========================================== */
64698 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD2TYPE                                                 */
64699   IOM0_SUBMODCTRL_SMOD2TYPE_MSPI       = 0,     /*!< MSPI : SPI Master submodule                                               */
64700   IOM0_SUBMODCTRL_SMOD2TYPE_MI2C       = 1,     /*!< MI2C : MI2C submodule                                                     */
64701   IOM0_SUBMODCTRL_SMOD2TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
64702   IOM0_SUBMODCTRL_SMOD2TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
64703   IOM0_SUBMODCTRL_SMOD2TYPE_MSI2S      = 4,     /*!< MSI2S : Master/Slave submodule                                            */
64704   IOM0_SUBMODCTRL_SMOD2TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
64705 } IOM0_SUBMODCTRL_SMOD2TYPE_Enum;
64706 
64707 /* ===========================================  IOM0 SUBMODCTRL SMOD1TYPE [5..7]  ============================================ */
64708 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD1TYPE                                                 */
64709   IOM0_SUBMODCTRL_SMOD1TYPE_MSPI       = 0,     /*!< MSPI : SPI Master submodule                                               */
64710   IOM0_SUBMODCTRL_SMOD1TYPE_MI2C       = 1,     /*!< MI2C : MI2C submodule                                                     */
64711   IOM0_SUBMODCTRL_SMOD1TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
64712   IOM0_SUBMODCTRL_SMOD1TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
64713   IOM0_SUBMODCTRL_SMOD1TYPE_MSI2S      = 4,     /*!< MSI2S : Master/Slave submodule                                            */
64714   IOM0_SUBMODCTRL_SMOD1TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
64715 } IOM0_SUBMODCTRL_SMOD1TYPE_Enum;
64716 
64717 /* ===========================================  IOM0 SUBMODCTRL SMOD0TYPE [1..3]  ============================================ */
64718 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD0TYPE                                                 */
64719   IOM0_SUBMODCTRL_SMOD0TYPE_MSPI       = 0,     /*!< MSPI : MSPI submodule                                                     */
64720   IOM0_SUBMODCTRL_SMOD0TYPE_MI2C       = 1,     /*!< MI2C : I2C Master submodule                                               */
64721   IOM0_SUBMODCTRL_SMOD0TYPE_MSI2S      = 2,     /*!< MSI2S : I2S Master/Slave Module                                           */
64722   IOM0_SUBMODCTRL_SMOD0TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
64723 } IOM0_SUBMODCTRL_SMOD0TYPE_Enum;
64724 
64725 /* ==========================================================  CMD  ========================================================== */
64726 /* ==================================================  IOM0 CMD CMD [0..3]  ================================================== */
64727 typedef enum {                                  /*!< IOM0_CMD_CMD                                                              */
64728   IOM0_CMD_CMD_WRITE                   = 1,     /*!< WRITE : Write command using count of offset bytes specified
64729                                                      in the OFFSETCNT field                                                    */
64730   IOM0_CMD_CMD_READ                    = 2,     /*!< READ : Read command using count of offset bytes specified in
64731                                                      the OFFSETCNT field                                                       */
64732   IOM0_CMD_CMD_TMW                     = 3,     /*!< TMW : SPI only. Test mode to do constant write operations. Useful
64733                                                      for debug and power measurements. Will continually send
64734                                                      data in OFFSET field                                                      */
64735   IOM0_CMD_CMD_TMR                     = 4,     /*!< TMR : SPI Only. Test mode to do constant read operations. Useful
64736                                                      for debug and power measurements. Will continually read
64737                                                      data from external input                                                  */
64738 } IOM0_CMD_CMD_Enum;
64739 
64740 /* ========================================================  DCXCTRL  ======================================================== */
64741 /* =======================================================  OFFSETHI  ======================================================== */
64742 /* ========================================================  CMDSTAT  ======================================================== */
64743 /* ==============================================  IOM0 CMDSTAT CMDSTAT [5..7]  ============================================== */
64744 typedef enum {                                  /*!< IOM0_CMDSTAT_CMDSTAT                                                      */
64745   IOM0_CMDSTAT_CMDSTAT_ERR             = 1,     /*!< ERR : Error encountered with command                                      */
64746   IOM0_CMDSTAT_CMDSTAT_ACTIVE          = 2,     /*!< ACTIVE : Actively processing command                                      */
64747   IOM0_CMDSTAT_CMDSTAT_IDLE            = 4,     /*!< IDLE : Idle state, no active command, no error                            */
64748   IOM0_CMDSTAT_CMDSTAT_WAIT            = 6,     /*!< WAIT : Command in progress, but waiting on data from host                 */
64749 } IOM0_CMDSTAT_CMDSTAT_Enum;
64750 
64751 /* =========================================================  INTEN  ========================================================= */
64752 /* ========================================================  INTSTAT  ======================================================== */
64753 /* ========================================================  INTCLR  ========================================================= */
64754 /* ========================================================  INTSET  ========================================================= */
64755 /* =======================================================  DMATRIGEN  ======================================================= */
64756 /* ======================================================  DMATRIGSTAT  ====================================================== */
64757 /* ========================================================  DMACFG  ========================================================= */
64758 /* ==============================================  IOM0 DMACFG DPWROFF [9..9]  =============================================== */
64759 typedef enum {                                  /*!< IOM0_DMACFG_DPWROFF                                                       */
64760   IOM0_DMACFG_DPWROFF_DIS              = 0,     /*!< DIS : Power off disabled                                                  */
64761   IOM0_DMACFG_DPWROFF_EN               = 1,     /*!< EN : Power off enabled                                                    */
64762 } IOM0_DMACFG_DPWROFF_Enum;
64763 
64764 /* ===============================================  IOM0 DMACFG DMAPRI [8..8]  =============================================== */
64765 typedef enum {                                  /*!< IOM0_DMACFG_DMAPRI                                                        */
64766   IOM0_DMACFG_DMAPRI_LOW               = 0,     /*!< LOW : Low Priority (service as best effort)                               */
64767   IOM0_DMACFG_DMAPRI_HIGH              = 1,     /*!< HIGH : High Priority (service immediately)                                */
64768 } IOM0_DMACFG_DMAPRI_Enum;
64769 
64770 /* ===============================================  IOM0 DMACFG DMADIR [1..1]  =============================================== */
64771 typedef enum {                                  /*!< IOM0_DMACFG_DMADIR                                                        */
64772   IOM0_DMACFG_DMADIR_P2M               = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when
64773                                                      doing IOM read operations, ie reading data from external
64774                                                      devices.                                                                  */
64775   IOM0_DMACFG_DMADIR_M2P               = 1,     /*!< M2P : Memory to Peripheral transaction. To be set when doing
64776                                                      IOM write operations, ie writing data to external devices.                */
64777 } IOM0_DMACFG_DMADIR_Enum;
64778 
64779 /* ===============================================  IOM0 DMACFG DMAEN [0..0]  ================================================ */
64780 typedef enum {                                  /*!< IOM0_DMACFG_DMAEN                                                         */
64781   IOM0_DMACFG_DMAEN_DIS                = 0,     /*!< DIS : Disable DMA Function                                                */
64782   IOM0_DMACFG_DMAEN_EN                 = 1,     /*!< EN : Enable DMA Function                                                  */
64783 } IOM0_DMACFG_DMAEN_Enum;
64784 
64785 /* ======================================================  DMATOTCOUNT  ====================================================== */
64786 /* ======================================================  DMATARGADDR  ====================================================== */
64787 /* ========================================================  DMASTAT  ======================================================== */
64788 /* =========================================================  CQCFG  ========================================================= */
64789 /* =============================================  IOM0 CQCFG MSPIFLGSEL [2..3]  ============================================== */
64790 typedef enum {                                  /*!< IOM0_CQCFG_MSPIFLGSEL                                                     */
64791   IOM0_CQCFG_MSPIFLGSEL_MSPI0FLGSEL    = 0,     /*!< MSPI0FLGSEL : Selects MPSI0 as source of signals used in CGFLAG[11:8].    */
64792   IOM0_CQCFG_MSPIFLGSEL_MSPI1FLGSEL    = 1,     /*!< MSPI1FLGSEL : Selects MPSI1 as source of signals used in CGFLAG[11:8].    */
64793   IOM0_CQCFG_MSPIFLGSEL_MSPI2FLGSEL    = 2,     /*!< MSPI2FLGSEL : Selects MPSI2 as source of signals used in CGFLAG[11:8].    */
64794 } IOM0_CQCFG_MSPIFLGSEL_Enum;
64795 
64796 /* ================================================  IOM0 CQCFG CQPRI [1..1]  ================================================ */
64797 typedef enum {                                  /*!< IOM0_CQCFG_CQPRI                                                          */
64798   IOM0_CQCFG_CQPRI_LOW                 = 0,     /*!< LOW : Low Priority (service as best effort)                               */
64799   IOM0_CQCFG_CQPRI_HIGH                = 1,     /*!< HIGH : High Priority (service immediately)                                */
64800 } IOM0_CQCFG_CQPRI_Enum;
64801 
64802 /* ================================================  IOM0 CQCFG CQEN [0..0]  ================================================= */
64803 typedef enum {                                  /*!< IOM0_CQCFG_CQEN                                                           */
64804   IOM0_CQCFG_CQEN_DIS                  = 0,     /*!< DIS : Disable CQ Function                                                 */
64805   IOM0_CQCFG_CQEN_EN                   = 1,     /*!< EN : Enable CQ Function                                                   */
64806 } IOM0_CQCFG_CQEN_Enum;
64807 
64808 /* ========================================================  CQADDR  ========================================================= */
64809 /* ========================================================  CQSTAT  ========================================================= */
64810 /* ========================================================  CQFLAGS  ======================================================== */
64811 /* ======================================================  CQSETCLEAR  ======================================================= */
64812 /* =======================================================  CQPAUSEEN  ======================================================= */
64813 /* =============================================  IOM0 CQPAUSEEN CQPEN [0..15]  ============================================== */
64814 typedef enum {                                  /*!< IOM0_CQPAUSEEN_CQPEN                                                      */
64815   IOM0_CQPAUSEEN_CQPEN_IDXEQ           = 32768, /*!< IDXEQ : Pauses the command queue when the current index matches
64816                                                      the last index                                                            */
64817   IOM0_CQPAUSEEN_CQPEN_BLEXOREN        = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with
64818                                                      SWFLAG4 is '1'                                                            */
64819   IOM0_CQPAUSEEN_CQPEN_IOMXOREN        = 8192,  /*!< IOMXOREN : Pause command queue when input IOM bit XORed with
64820                                                      SWFLAG3 is '1'                                                            */
64821   IOM0_CQPAUSEEN_CQPEN_GPIOXOREN       = 4096,  /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed
64822                                                      with SWFLAG2 is '1'                                                       */
64823   IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN     = 2048,  /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed
64824                                                      with SWFLAG1 is '1'                                                       */
64825   IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN     = 1024,  /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed
64826                                                      with SWFLAG0 is '1'                                                       */
64827   IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN      = 512,   /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed
64828                                                      with SWFLAG1 is '1'                                                       */
64829   IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN      = 256,   /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed
64830                                                      with SWFLAG0 is '1'                                                       */
64831   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7       = 128,   /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7
64832                                                      is '1'.                                                                   */
64833   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6       = 64,    /*!< SWFLAGEN6 : Pause the command queue when software flag bit 6
64834                                                      is '1'                                                                    */
64835   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5       = 32,    /*!< SWFLAGEN5 : Pause the command queue when software flag bit 5
64836                                                      is '1'                                                                    */
64837   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4       = 16,    /*!< SWFLAGEN4 : Pause the command queue when software flag bit 4
64838                                                      is '1'                                                                    */
64839   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3       = 8,     /*!< SWFLAGEN3 : Pause the command queue when software flag bit 3
64840                                                      is '1'                                                                    */
64841   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2       = 4,     /*!< SWFLAGEN2 : Pause the command queue when software flag bit 2
64842                                                      is '1'                                                                    */
64843   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1       = 2,     /*!< SWFLAGEN1 : Pause the command queue when software flag bit 1
64844                                                      is '1'                                                                    */
64845   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0       = 1,     /*!< SWFLAGEN0 : Pause the command queue when software flag bit 0
64846                                                      is '1'                                                                    */
64847 } IOM0_CQPAUSEEN_CQPEN_Enum;
64848 
64849 /* =======================================================  CQCURIDX  ======================================================== */
64850 /* =======================================================  CQENDIDX  ======================================================== */
64851 /* ========================================================  STATUS  ========================================================= */
64852 /* ===============================================  IOM0 STATUS IDLEST [2..2]  =============================================== */
64853 typedef enum {                                  /*!< IOM0_STATUS_IDLEST                                                        */
64854   IOM0_STATUS_IDLEST_IDLE              = 1,     /*!< IDLE : The I/O state machine is in the idle state.                        */
64855   IOM0_STATUS_IDLEST_RUN               = 0,     /*!< RUN : The I/O state machine is in the non-idle/run state.                 */
64856 } IOM0_STATUS_IDLEST_Enum;
64857 
64858 /* ===============================================  IOM0 STATUS CMDACT [1..1]  =============================================== */
64859 typedef enum {                                  /*!< IOM0_STATUS_CMDACT                                                        */
64860   IOM0_STATUS_CMDACT_ACTIVE            = 1,     /*!< ACTIVE : An I/O command is active. Indicates the active module
64861                                                      has an active command and is processing this. De-asserted
64862                                                      when the command is completed.                                            */
64863   IOM0_STATUS_CMDACT_INACTIVE          = 0,     /*!< INACTIVE : An I/O command is inactive. Indicating that the command
64864                                                      is complete.                                                              */
64865 } IOM0_STATUS_CMDACT_Enum;
64866 
64867 /* ================================================  IOM0 STATUS ERR [0..0]  ================================================= */
64868 typedef enum {                                  /*!< IOM0_STATUS_ERR                                                           */
64869   IOM0_STATUS_ERR_ERROR                = 1,     /*!< ERROR : Bit has been deprecated and will always return 0.                 */
64870   IOM0_STATUS_ERR_DEFAULT              = 0,     /*!< DEFAULT : Default value.                                                  */
64871 } IOM0_STATUS_ERR_Enum;
64872 
64873 /* ========================================================  MSPICFG  ======================================================== */
64874 /* =============================================  IOM0 MSPICFG SPILSB [23..23]  ============================================== */
64875 typedef enum {                                  /*!< IOM0_MSPICFG_SPILSB                                                       */
64876   IOM0_MSPICFG_SPILSB_MSB              = 0,     /*!< MSB : Send and receive MSB bit first                                      */
64877   IOM0_MSPICFG_SPILSB_LSB              = 1,     /*!< LSB : Send and receive LSB bit first                                      */
64878 } IOM0_MSPICFG_SPILSB_Enum;
64879 
64880 /* =============================================  IOM0 MSPICFG RDFCPOL [22..22]  ============================================= */
64881 typedef enum {                                  /*!< IOM0_MSPICFG_RDFCPOL                                                      */
64882   IOM0_MSPICFG_RDFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high creates flow control.                     */
64883   IOM0_MSPICFG_RDFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low creates flow control.                       */
64884 } IOM0_MSPICFG_RDFCPOL_Enum;
64885 
64886 /* =============================================  IOM0 MSPICFG WTFCPOL [21..21]  ============================================= */
64887 typedef enum {                                  /*!< IOM0_MSPICFG_WTFCPOL                                                      */
64888   IOM0_MSPICFG_WTFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high(1) creates flow control and
64889                                                      byte transfers will stop until the flow control signal
64890                                                      goes low.                                                                 */
64891   IOM0_MSPICFG_WTFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low(0) creates flow control and byte
64892                                                      transfers will stop until the flow control signal goes
64893                                                      high(1).                                                                  */
64894 } IOM0_MSPICFG_WTFCPOL_Enum;
64895 
64896 /* =============================================  IOM0 MSPICFG WTFCIRQ [20..20]  ============================================= */
64897 typedef enum {                                  /*!< IOM0_MSPICFG_WTFCIRQ                                                      */
64898   IOM0_MSPICFG_WTFCIRQ_MISO            = 0,     /*!< MISO : MISO is used as the write mode flow control signal.                */
64899   IOM0_MSPICFG_WTFCIRQ_IRQ             = 1,     /*!< IRQ : IRQ is used as the write mode flow control signal.                  */
64900 } IOM0_MSPICFG_WTFCIRQ_Enum;
64901 
64902 /* =============================================  IOM0 MSPICFG MOSIINV [18..18]  ============================================= */
64903 typedef enum {                                  /*!< IOM0_MSPICFG_MOSIINV                                                      */
64904   IOM0_MSPICFG_MOSIINV_NORMAL          = 0,     /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode.               */
64905   IOM0_MSPICFG_MOSIINV_INVERT          = 1,     /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode.               */
64906 } IOM0_MSPICFG_MOSIINV_Enum;
64907 
64908 /* ==============================================  IOM0 MSPICFG RDFC [17..17]  =============================================== */
64909 typedef enum {                                  /*!< IOM0_MSPICFG_RDFC                                                         */
64910   IOM0_MSPICFG_RDFC_DIS                = 0,     /*!< DIS : Read mode flow control disabled.                                    */
64911   IOM0_MSPICFG_RDFC_EN                 = 1,     /*!< EN : Read mode flow control enabled.                                      */
64912 } IOM0_MSPICFG_RDFC_Enum;
64913 
64914 /* ==============================================  IOM0 MSPICFG WTFC [16..16]  =============================================== */
64915 typedef enum {                                  /*!< IOM0_MSPICFG_WTFC                                                         */
64916   IOM0_MSPICFG_WTFC_DIS                = 0,     /*!< DIS : Write mode flow control disabled.                                   */
64917   IOM0_MSPICFG_WTFC_EN                 = 1,     /*!< EN : Write mode flow control enabled.                                     */
64918 } IOM0_MSPICFG_WTFC_Enum;
64919 
64920 /* ===============================================  IOM0 MSPICFG SPHA [1..1]  ================================================ */
64921 typedef enum {                                  /*!< IOM0_MSPICFG_SPHA                                                         */
64922   IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0,    /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge.           */
64923   IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1,   /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
64924                                                      edge.                                                                     */
64925 } IOM0_MSPICFG_SPHA_Enum;
64926 
64927 /* ===============================================  IOM0 MSPICFG SPOL [0..0]  ================================================ */
64928 typedef enum {                                  /*!< IOM0_MSPICFG_SPOL                                                         */
64929   IOM0_MSPICFG_SPOL_CLK_BASE_0         = 0,     /*!< CLK_BASE_0 : The base value of the clock is 0.                            */
64930   IOM0_MSPICFG_SPOL_CLK_BASE_1         = 1,     /*!< CLK_BASE_1 : The base value of the clock is 1.                            */
64931 } IOM0_MSPICFG_SPOL_Enum;
64932 
64933 /* ========================================================  MI2CCFG  ======================================================== */
64934 /* ===============================================  IOM0 MI2CCFG ARBEN [2..2]  =============================================== */
64935 typedef enum {                                  /*!< IOM0_MI2CCFG_ARBEN                                                        */
64936   IOM0_MI2CCFG_ARBEN_ARBENABLE         = 1,     /*!< ARBENABLE : Enable multi-master bus arbitration support for
64937                                                      this i2c master                                                           */
64938   IOM0_MI2CCFG_ARBEN_ARBDISABLE        = 0,     /*!< ARBDISABLE : Disable multi-master bus arbitration support for
64939                                                      this i2c master                                                           */
64940 } IOM0_MI2CCFG_ARBEN_Enum;
64941 
64942 /* ==============================================  IOM0 MI2CCFG I2CLSB [1..1]  =============================================== */
64943 typedef enum {                                  /*!< IOM0_MI2CCFG_I2CLSB                                                       */
64944   IOM0_MI2CCFG_I2CLSB_MSBFIRST         = 0,     /*!< MSBFIRST : Byte data is transmitted MSB first onto the bus/read
64945                                                      from the bus                                                              */
64946   IOM0_MI2CCFG_I2CLSB_LSBFIRST         = 1,     /*!< LSBFIRST : Byte data is transmitted LSB first onto the bus/read
64947                                                      from the bus                                                              */
64948 } IOM0_MI2CCFG_I2CLSB_Enum;
64949 
64950 /* ==============================================  IOM0 MI2CCFG ADDRSZ [0..0]  =============================================== */
64951 typedef enum {                                  /*!< IOM0_MI2CCFG_ADDRSZ                                                       */
64952   IOM0_MI2CCFG_ADDRSZ_ADDRSZ7          = 0,     /*!< ADDRSZ7 : Use 7b addressing for I2C master transactions                   */
64953   IOM0_MI2CCFG_ADDRSZ_ADDRSZ10         = 1,     /*!< ADDRSZ10 : Use 10b addressing for I2C master transactions                 */
64954 } IOM0_MI2CCFG_ADDRSZ_Enum;
64955 
64956 /* ========================================================  DEVCFG  ========================================================= */
64957 /* ========================================================  IOMDBG  ========================================================= */
64958 
64959 
64960 /* =========================================================================================================================== */
64961 /* ================                                          IOSLAVE                                          ================ */
64962 /* =========================================================================================================================== */
64963 
64964 /* ========================================================  FIFOPTR  ======================================================== */
64965 /* ========================================================  FIFOCFG  ======================================================== */
64966 /* ========================================================  FIFOTHR  ======================================================== */
64967 /* =========================================================  FUPD  ========================================================== */
64968 /* ========================================================  FIFOCTR  ======================================================== */
64969 /* ========================================================  FIFOINC  ======================================================== */
64970 /* ==========================================================  CFG  ========================================================== */
64971 /* ==============================================  IOSLAVE CFG IFCEN [31..31]  =============================================== */
64972 typedef enum {                                  /*!< IOSLAVE_CFG_IFCEN                                                         */
64973   IOSLAVE_CFG_IFCEN_DIS                = 0,     /*!< DIS : Disable the IOSLAVE                                                 */
64974   IOSLAVE_CFG_IFCEN_EN                 = 1,     /*!< EN : Enable the IOSLAVE                                                   */
64975 } IOSLAVE_CFG_IFCEN_Enum;
64976 
64977 /* =============================================  IOSLAVE CFG WRAPPTR [20..20]  ============================================== */
64978 typedef enum {                                  /*!< IOSLAVE_CFG_WRAPPTR                                                       */
64979   IOSLAVE_CFG_WRAPPTR_NOWRAP           = 0,     /*!< NOWRAP : Address pointer does not wrap around to FIFOBASE*8
64980                                                      after it reaches FIFOMAX*8-1. Additionally, the address
64981                                                      pointer does not automatically skip Direct Area locations
64982                                                      0x78 to 0x7F, so care must be taken that the host does
64983                                                      not inadvertently write to the Host Registers during a
64984                                                      data transfer.                                                            */
64985   IOSLAVE_CFG_WRAPPTR_WRAP             = 1,     /*!< WRAP : Address pointer wraps around to FIFOBASE*8 after it reaches
64986                                                      FIFOMAX*8-1 to accommodate any length transfers. In addition,
64987                                                      the address pointer automatically skips Direct Area locations
64988                                                      0x78 to 0x7F (if the FIFO Area encompasses these locations)
64989                                                      to avoid writing to the Host Registers.                                   */
64990 } IOSLAVE_CFG_WRAPPTR_Enum;
64991 
64992 /* ==============================================  IOSLAVE CFG STARTRD [4..4]  =============================================== */
64993 typedef enum {                                  /*!< IOSLAVE_CFG_STARTRD                                                       */
64994   IOSLAVE_CFG_STARTRD_LATE             = 0,     /*!< LATE : Initiate I/O RAM read late in each transferred byte.               */
64995   IOSLAVE_CFG_STARTRD_EARLY            = 1,     /*!< EARLY : Initiate I/O RAM read early in each transferred byte.             */
64996 } IOSLAVE_CFG_STARTRD_Enum;
64997 
64998 /* ================================================  IOSLAVE CFG LSB [2..2]  ================================================= */
64999 typedef enum {                                  /*!< IOSLAVE_CFG_LSB                                                           */
65000   IOSLAVE_CFG_LSB_MSB_FIRST            = 0,     /*!< MSB_FIRST : Data is assumed to be sent and received with MSB
65001                                                      first.                                                                    */
65002   IOSLAVE_CFG_LSB_LSB_FIRST            = 1,     /*!< LSB_FIRST : Data is assumed to be sent and received with LSB
65003                                                      first.                                                                    */
65004 } IOSLAVE_CFG_LSB_Enum;
65005 
65006 /* ================================================  IOSLAVE CFG SPOL [1..1]  ================================================ */
65007 typedef enum {                                  /*!< IOSLAVE_CFG_SPOL                                                          */
65008   IOSLAVE_CFG_SPOL_SPI_MODES_0_3       = 0,     /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3.                    */
65009   IOSLAVE_CFG_SPOL_SPI_MODES_1_2       = 1,     /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2.                    */
65010 } IOSLAVE_CFG_SPOL_Enum;
65011 
65012 /* ===============================================  IOSLAVE CFG IFCSEL [0..0]  =============================================== */
65013 typedef enum {                                  /*!< IOSLAVE_CFG_IFCSEL                                                        */
65014   IOSLAVE_CFG_IFCSEL_I2C               = 0,     /*!< I2C : Selects I2C interface for the IO Slave.                             */
65015   IOSLAVE_CFG_IFCSEL_SPI               = 1,     /*!< SPI : Selects SPI interface for the IO Slave.                             */
65016 } IOSLAVE_CFG_IFCSEL_Enum;
65017 
65018 /* =========================================================  PRENC  ========================================================= */
65019 /* =======================================================  IOINTCTL  ======================================================== */
65020 /* ========================================================  GENADD  ========================================================= */
65021 /* ========================================================  ADDPTR  ========================================================= */
65022 /* =========================================================  INTEN  ========================================================= */
65023 /* ========================================================  INTSTAT  ======================================================== */
65024 /* ========================================================  INTCLR  ========================================================= */
65025 /* ========================================================  INTSET  ========================================================= */
65026 /* ======================================================  REGACCINTEN  ====================================================== */
65027 /* =====================================================  REGACCINTSTAT  ===================================================== */
65028 /* =====================================================  REGACCINTCLR  ====================================================== */
65029 /* =====================================================  REGACCINTSET  ====================================================== */
65030 
65031 
65032 /* =========================================================================================================================== */
65033 /* ================                                          MCUCTRL                                          ================ */
65034 /* =========================================================================================================================== */
65035 
65036 /* ========================================================  CHIPPN  ========================================================= */
65037 /* ==============================================  MCUCTRL CHIPPN PN [24..31]  =============================================== */
65038 typedef enum {                                  /*!< MCUCTRL_CHIPPN_PN                                                         */
65039   MCUCTRL_CHIPPN_PN_APOLLO4L           = 9,     /*!< APOLLO4L : Apollo4L part number is 0x09xxxxxx.                            */
65040   MCUCTRL_CHIPPN_PN_APOLLO4            = 8,     /*!< APOLLO4 : Apollo4 part number is 0x08xxxxxx.                              */
65041   MCUCTRL_CHIPPN_PN_APOLLO3P           = 7,     /*!< APOLLO3P : Apollo3P part number is 0x07xxxxxx.                            */
65042   MCUCTRL_CHIPPN_PN_APOLLO3            = 6,     /*!< APOLLO3 : Apollo3 part number is 0x06xxxxxx.                              */
65043   MCUCTRL_CHIPPN_PN_APOLLO2            = 3,     /*!< APOLLO2 : Apollo2 part number is 0x03xxxxxx.                              */
65044   MCUCTRL_CHIPPN_PN_APOLLO             = 1,     /*!< APOLLO : Apollo part number is 0x01xxxxxx.                                */
65045 } MCUCTRL_CHIPPN_PN_Enum;
65046 
65047 /* ===========================================  MCUCTRL CHIPPN MRAMSIZE [20..23]  ============================================ */
65048 typedef enum {                                  /*!< MCUCTRL_CHIPPN_MRAMSIZE                                                   */
65049   MCUCTRL_CHIPPN_MRAMSIZE_0P5MB        = 0,     /*!< 0P5MB : MRAM size is 0.5MB                                                */
65050   MCUCTRL_CHIPPN_MRAMSIZE_1P0MB        = 1,     /*!< 1P0MB : MRAM size is 1.0MB                                                */
65051   MCUCTRL_CHIPPN_MRAMSIZE_1P5MB        = 2,     /*!< 1P5MB : MRAM size is 1.5MB                                                */
65052   MCUCTRL_CHIPPN_MRAMSIZE_2P0MB        = 3,     /*!< 2P0MB : MRAM size is 2.0MB                                                */
65053 } MCUCTRL_CHIPPN_MRAMSIZE_Enum;
65054 
65055 /* ===========================================  MCUCTRL CHIPPN SRAMSIZE [16..19]  ============================================ */
65056 typedef enum {                                  /*!< MCUCTRL_CHIPPN_SRAMSIZE                                                   */
65057   MCUCTRL_CHIPPN_SRAMSIZE_384_512      = 0,     /*!< 384_512 : SRAM size is 384KB+512KB                                        */
65058   MCUCTRL_CHIPPN_SRAMSIZE_384_1024     = 1,     /*!< 384_1024 : SRAM size is 384KB+1MB                                         */
65059   MCUCTRL_CHIPPN_SRAMSIZE_384_1024_384_96 = 2,  /*!< 384_1024_384_96 : SRAM size is 384KB+1MB+384KB+96KB                       */
65060 } MCUCTRL_CHIPPN_SRAMSIZE_Enum;
65061 
65062 /* ============================================  MCUCTRL CHIPPN REVMAJ [12..15]  ============================================= */
65063 typedef enum {                                  /*!< MCUCTRL_CHIPPN_REVMAJ                                                     */
65064   MCUCTRL_CHIPPN_REVMAJ_A              = 0,     /*!< A : Major Rev A                                                           */
65065   MCUCTRL_CHIPPN_REVMAJ_B              = 1,     /*!< B : Major Rev B                                                           */
65066   MCUCTRL_CHIPPN_REVMAJ_C              = 2,     /*!< C : Major Rev C                                                           */
65067 } MCUCTRL_CHIPPN_REVMAJ_Enum;
65068 
65069 /* =============================================  MCUCTRL CHIPPN REVMIN [8..11]  ============================================= */
65070 typedef enum {                                  /*!< MCUCTRL_CHIPPN_REVMIN                                                     */
65071   MCUCTRL_CHIPPN_REVMIN_0              = 0,     /*!< 0 : Minor Rev 0                                                           */
65072   MCUCTRL_CHIPPN_REVMIN_1              = 1,     /*!< 1 : Minor Rev 1                                                           */
65073 } MCUCTRL_CHIPPN_REVMIN_Enum;
65074 
65075 /* ===============================================  MCUCTRL CHIPPN PKG [6..7]  =============================================== */
65076 typedef enum {                                  /*!< MCUCTRL_CHIPPN_PKG                                                        */
65077   MCUCTRL_CHIPPN_PKG_SIP               = 0,     /*!< SIP : SIP package.                                                        */
65078   MCUCTRL_CHIPPN_PKG_SIP2              = 1,     /*!< SIP2 : SIP2 package.                                                      */
65079   MCUCTRL_CHIPPN_PKG_BGA               = 2,     /*!< BGA : BGA package.                                                        */
65080   MCUCTRL_CHIPPN_PKG_CSP               = 3,     /*!< CSP : CSP package.                                                        */
65081 } MCUCTRL_CHIPPN_PKG_Enum;
65082 
65083 /* ==============================================  MCUCTRL CHIPPN PINS [3..5]  =============================================== */
65084 typedef enum {                                  /*!< MCUCTRL_CHIPPN_PINS                                                       */
65085   MCUCTRL_CHIPPN_PINS_25               = 0,     /*!< 25 : 25 pins                                                              */
65086   MCUCTRL_CHIPPN_PINS_49               = 1,     /*!< 49 : 49 pins                                                              */
65087   MCUCTRL_CHIPPN_PINS_64               = 2,     /*!< 64 : 64 pins                                                              */
65088   MCUCTRL_CHIPPN_PINS_81               = 3,     /*!< 81 : 81 pins                                                              */
65089 } MCUCTRL_CHIPPN_PINS_Enum;
65090 
65091 /* ==============================================  MCUCTRL CHIPPN TEMP [1..2]  =============================================== */
65092 typedef enum {                                  /*!< MCUCTRL_CHIPPN_TEMP                                                       */
65093   MCUCTRL_CHIPPN_TEMP_COM              = 0,     /*!< COM : Commercial temperature                                              */
65094   MCUCTRL_CHIPPN_TEMP_MIL              = 1,     /*!< MIL : Military temperature                                                */
65095   MCUCTRL_CHIPPN_TEMP_AUTO             = 2,     /*!< AUTO : Automotive temperature                                             */
65096   MCUCTRL_CHIPPN_TEMP_IND              = 3,     /*!< IND : Industrial temperature                                              */
65097 } MCUCTRL_CHIPPN_TEMP_Enum;
65098 
65099 /* ========================================================  CHIPID0  ======================================================== */
65100 /* ========================================================  CHIPID1  ======================================================== */
65101 /* ========================================================  CHIPREV  ======================================================== */
65102 /* =============================================  MCUCTRL CHIPREV REVMAJ [4..7]  ============================================= */
65103 typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMAJ                                                    */
65104   MCUCTRL_CHIPREV_REVMAJ_C             = 3,     /*!< C : Apollo4 revision C                                                    */
65105   MCUCTRL_CHIPREV_REVMAJ_B             = 2,     /*!< B : Apollo4 revision B                                                    */
65106   MCUCTRL_CHIPREV_REVMAJ_A             = 1,     /*!< A : Apollo4 revision A                                                    */
65107 } MCUCTRL_CHIPREV_REVMAJ_Enum;
65108 
65109 /* =============================================  MCUCTRL CHIPREV REVMIN [0..3]  ============================================= */
65110 typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMIN                                                    */
65111   MCUCTRL_CHIPREV_REVMIN_REV2          = 3,     /*!< REV2 : Apollo4 minor rev 2.                                               */
65112   MCUCTRL_CHIPREV_REVMIN_REV1          = 2,     /*!< REV1 : Apollo4 minor rev 1.                                               */
65113   MCUCTRL_CHIPREV_REVMIN_REV0          = 1,     /*!< REV0 : Apollo4 minor rev 0. Minor revision value, succeeding
65114                                                      minor revisions will increment from this value.                           */
65115 } MCUCTRL_CHIPREV_REVMIN_Enum;
65116 
65117 /* =======================================================  VENDORID  ======================================================== */
65118 /* ===========================================  MCUCTRL VENDORID VENDORID [0..31]  =========================================== */
65119 typedef enum {                                  /*!< MCUCTRL_VENDORID_VENDORID                                                 */
65120   MCUCTRL_VENDORID_VENDORID_AMBIQ      = 1095582289,/*!< AMBIQ : Ambiq Vendor ID 'AMBQ'                                        */
65121   MCUCTRL_VENDORID_VENDORID_DEFAULT    = 0,     /*!< DEFAULT : Default Vendor ID                                               */
65122 } MCUCTRL_VENDORID_VENDORID_Enum;
65123 
65124 /* ==========================================================  SKU  ========================================================== */
65125 /* =======================================================  DEBUGGER  ======================================================== */
65126 /* =========================================================  ACRG  ========================================================== */
65127 /* ===========================================  MCUCTRL ACRG ACRGIBIASSEL [2..2]  ============================================ */
65128 typedef enum {                                  /*!< MCUCTRL_ACRG_ACRGIBIASSEL                                                 */
65129   MCUCTRL_ACRG_ACRGIBIASSEL_BGSEL      = 0,     /*!< BGSEL : Selects the bandgap                                               */
65130   MCUCTRL_ACRG_ACRGIBIASSEL_CCRGSEL    = 1,     /*!< CCRGSEL : Selects the CCRG                                                */
65131 } MCUCTRL_ACRG_ACRGIBIASSEL_Enum;
65132 
65133 /* ==============================================  MCUCTRL ACRG ACRGPWD [1..1]  ============================================== */
65134 typedef enum {                                  /*!< MCUCTRL_ACRG_ACRGPWD                                                      */
65135   MCUCTRL_ACRG_ACRGPWD_ACRG_PWR_DN     = 1,     /*!< ACRG_PWR_DN : Powers down the ACRG trim.                                  */
65136   MCUCTRL_ACRG_ACRGPWD_ACRG_PWR_UP     = 0,     /*!< ACRG_PWR_UP : Power up the ACRG trim.                                     */
65137 } MCUCTRL_ACRG_ACRGPWD_Enum;
65138 
65139 /* =======================================================  VREFGEN2  ======================================================== */
65140 /* ==========================================  MCUCTRL VREFGEN2 TVRG2PWD [19..19]  =========================================== */
65141 typedef enum {                                  /*!< MCUCTRL_VREFGEN2_TVRG2PWD                                                 */
65142   MCUCTRL_VREFGEN2_TVRG2PWD_PWR_DN     = 1,     /*!< PWR_DN : Powers down the CVRG.                                            */
65143   MCUCTRL_VREFGEN2_TVRG2PWD_PWR_UP     = 0,     /*!< PWR_UP : Power up the CVRG.                                               */
65144 } MCUCTRL_VREFGEN2_TVRG2PWD_Enum;
65145 
65146 /* ============================================  MCUCTRL VREFGEN2 TVRGPWD [5..5]  ============================================ */
65147 typedef enum {                                  /*!< MCUCTRL_VREFGEN2_TVRGPWD                                                  */
65148   MCUCTRL_VREFGEN2_TVRGPWD_PWR_DN      = 1,     /*!< PWR_DN : Powers down the CVRG.                                            */
65149   MCUCTRL_VREFGEN2_TVRGPWD_PWR_UP      = 0,     /*!< PWR_UP : Power up the CVRG.                                               */
65150 } MCUCTRL_VREFGEN2_TVRGPWD_Enum;
65151 
65152 /* ========================================================  VRCTRL  ========================================================= */
65153 /* ========================================================  LDOREG1  ======================================================== */
65154 /* ========================================================  LDOREG2  ======================================================== */
65155 /* =========================================================  LFRC  ========================================================== */
65156 /* =========================================  MCUCTRL LFRC LFRCSIMOCLKDIV [10..12]  ========================================== */
65157 typedef enum {                                  /*!< MCUCTRL_LFRC_LFRCSIMOCLKDIV                                               */
65158   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV1     = 0,     /*!< DIV1 : Divide by 1                                                        */
65159   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV2     = 1,     /*!< DIV2 : Divide by 2                                                        */
65160   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV4     = 2,     /*!< DIV4 : Divide by 4                                                        */
65161   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV8     = 3,     /*!< DIV8 : Divide by 8                                                        */
65162   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV16    = 4,     /*!< DIV16 : Divide by 16                                                      */
65163   MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV32    = 5,     /*!< DIV32 : Divide by 32                                                      */
65164 } MCUCTRL_LFRC_LFRCSIMOCLKDIV_Enum;
65165 
65166 /* =============================================  MCUCTRL LFRC RESETLFRC [7..7]  ============================================= */
65167 typedef enum {                                  /*!< MCUCTRL_LFRC_RESETLFRC                                                    */
65168   MCUCTRL_LFRC_RESETLFRC_EN            = 0,     /*!< EN : Enable LFRC.                                                         */
65169   MCUCTRL_LFRC_RESETLFRC_RESET         = 1,     /*!< RESET : Reset LFRC.                                                       */
65170 } MCUCTRL_LFRC_RESETLFRC_Enum;
65171 
65172 /* ==============================================  MCUCTRL LFRC PWDLFRC [6..6]  ============================================== */
65173 typedef enum {                                  /*!< MCUCTRL_LFRC_PWDLFRC                                                      */
65174   MCUCTRL_LFRC_PWDLFRC_PWRUP           = 0,     /*!< PWRUP : Power up LFRC.                                                    */
65175   MCUCTRL_LFRC_PWDLFRC_PWRDN           = 1,     /*!< PWRDN : Power down LFRC.                                                  */
65176 } MCUCTRL_LFRC_PWDLFRC_Enum;
65177 
65178 /* ==============================================  MCUCTRL LFRC LFRCSWE [0..0]  ============================================== */
65179 typedef enum {                                  /*!< MCUCTRL_LFRC_LFRCSWE                                                      */
65180   MCUCTRL_LFRC_LFRCSWE_OVERRIDE_DIS    = 0,     /*!< OVERRIDE_DIS : LFRC Software Override Disable.                            */
65181   MCUCTRL_LFRC_LFRCSWE_OVERRIDE_EN     = 1,     /*!< OVERRIDE_EN : LFRC Software Override Enable.                              */
65182 } MCUCTRL_LFRC_LFRCSWE_Enum;
65183 
65184 /* ========================================================  BODCTRL  ======================================================== */
65185 /* =======================================================  ADCPWRDLY  ======================================================= */
65186 /* ======================================================  ADCPWRCTRL  ======================================================= */
65187 /* ========================================  MCUCTRL ADCPWRCTRL VDDADCRESETN [9..9]  ========================================= */
65188 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_VDDADCRESETN                                           */
65189   MCUCTRL_ADCPWRCTRL_VDDADCRESETN_ASSERT = 0,   /*!< ASSERT : Resetn is asserted                                               */
65190   MCUCTRL_ADCPWRCTRL_VDDADCRESETN_DEASSERT = 1, /*!< DEASSERT : Resetn is de-asserted                                          */
65191 } MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Enum;
65192 
65193 /* ======================================  MCUCTRL ADCPWRCTRL VDDADCDIGISOLATE [8..8]  ======================================= */
65194 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE                                       */
65195   MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_DIS = 0,  /*!< DIS : No Isolation                                                        */
65196   MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_EN = 1,   /*!< EN : Isolate                                                              */
65197 } MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Enum;
65198 
65199 /* ======================================  MCUCTRL ADCPWRCTRL VDDADCSARISOLATE [7..7]  ======================================= */
65200 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE                                       */
65201   MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_DIS = 0,  /*!< DIS : No Isolation                                                        */
65202   MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_EN = 1,   /*!< EN : Isolate                                                              */
65203 } MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Enum;
65204 
65205 /* =========================================  MCUCTRL ADCPWRCTRL REFKEEPPEN [6..6]  ========================================== */
65206 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_REFKEEPPEN                                             */
65207   MCUCTRL_ADCPWRCTRL_REFKEEPPEN_DIS    = 0,     /*!< DIS : Reference Buffer Keeper Power Switch disable.                       */
65208   MCUCTRL_ADCPWRCTRL_REFKEEPPEN_EN     = 1,     /*!< EN : Reference Buffer Keeper Power Switch enable.                         */
65209 } MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Enum;
65210 
65211 /* ==========================================  MCUCTRL ADCPWRCTRL REFBUFPEN [5..5]  ========================================== */
65212 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_REFBUFPEN                                              */
65213   MCUCTRL_ADCPWRCTRL_REFBUFPEN_DIS     = 0,     /*!< DIS : Reference Buffer Power Switch disable.                              */
65214   MCUCTRL_ADCPWRCTRL_REFBUFPEN_EN      = 1,     /*!< EN : Reference Buffer Power Switch enable.                                */
65215 } MCUCTRL_ADCPWRCTRL_REFBUFPEN_Enum;
65216 
65217 /* ==========================================  MCUCTRL ADCPWRCTRL BGTLPPEN [4..4]  =========================================== */
65218 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_BGTLPPEN                                               */
65219   MCUCTRL_ADCPWRCTRL_BGTLPPEN_DIS      = 0,     /*!< DIS : Bandgap and temperature sensor disable.                             */
65220   MCUCTRL_ADCPWRCTRL_BGTLPPEN_EN       = 1,     /*!< EN : Bandgap and temperature sensor enable.                               */
65221 } MCUCTRL_ADCPWRCTRL_BGTLPPEN_Enum;
65222 
65223 /* ===========================================  MCUCTRL ADCPWRCTRL BGTPEN [3..3]  ============================================ */
65224 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_BGTPEN                                                 */
65225   MCUCTRL_ADCPWRCTRL_BGTPEN_DIS        = 0,     /*!< DIS : Bandgap and temperature sensor disable.                             */
65226   MCUCTRL_ADCPWRCTRL_BGTPEN_EN         = 1,     /*!< EN : Bandgap and temperature sensor enable.                               */
65227 } MCUCTRL_ADCPWRCTRL_BGTPEN_Enum;
65228 
65229 /* ==========================================  MCUCTRL ADCPWRCTRL ADCBPSEN [2..2]  =========================================== */
65230 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_ADCBPSEN                                               */
65231   MCUCTRL_ADCPWRCTRL_ADCBPSEN_DIS      = 0,     /*!< DIS : ADC power switch software power disable.                            */
65232   MCUCTRL_ADCPWRCTRL_ADCBPSEN_EN       = 1,     /*!< EN : ADC power switch software power enable.                              */
65233 } MCUCTRL_ADCPWRCTRL_ADCBPSEN_Enum;
65234 
65235 /* ==========================================  MCUCTRL ADCPWRCTRL ADCAPSEN [1..1]  =========================================== */
65236 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_ADCAPSEN                                               */
65237   MCUCTRL_ADCPWRCTRL_ADCAPSEN_DIS      = 0,     /*!< DIS : ADC power switch software power disable.                            */
65238   MCUCTRL_ADCPWRCTRL_ADCAPSEN_EN       = 1,     /*!< EN : ADC power switch software power enable.                              */
65239 } MCUCTRL_ADCPWRCTRL_ADCAPSEN_Enum;
65240 
65241 /* ========================================  MCUCTRL ADCPWRCTRL ADCPWRCTRLSWE [0..0]  ======================================== */
65242 typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE                                          */
65243   MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_OVERRIDE_DIS = 0,/*!< OVERRIDE_DIS : ADC temperature sensor and bandgap Software Override
65244                                                      Disable.                                                                  */
65245   MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_OVERRIDE_EN = 1,/*!< OVERRIDE_EN : ADC temperature sensor and bandgap Software Override
65246                                                      Enable.                                                                   */
65247 } MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Enum;
65248 
65249 /* ========================================================  ADCCAL  ========================================================= */
65250 /* ==========================================  MCUCTRL ADCCAL ADCCALIBRATED [1..1]  ========================================== */
65251 typedef enum {                                  /*!< MCUCTRL_ADCCAL_ADCCALIBRATED                                              */
65252   MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE   = 0,     /*!< FALSE : ADC is not calibrated                                             */
65253   MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE    = 1,     /*!< TRUE : ADC is calibrated                                                  */
65254 } MCUCTRL_ADCCAL_ADCCALIBRATED_Enum;
65255 
65256 /* ===========================================  MCUCTRL ADCCAL CALONPWRUP [0..0]  ============================================ */
65257 typedef enum {                                  /*!< MCUCTRL_ADCCAL_CALONPWRUP                                                 */
65258   MCUCTRL_ADCCAL_CALONPWRUP_DIS        = 0,     /*!< DIS : Disable automatic calibration on initial power up                   */
65259   MCUCTRL_ADCCAL_CALONPWRUP_EN         = 1,     /*!< EN : Enable automatic calibration on initial power up                     */
65260 } MCUCTRL_ADCCAL_CALONPWRUP_Enum;
65261 
65262 /* ======================================================  ADCBATTLOAD  ====================================================== */
65263 /* ==========================================  MCUCTRL ADCBATTLOAD BATTLOAD [0..0]  ========================================== */
65264 typedef enum {                                  /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD                                              */
65265   MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS     = 0,     /*!< DIS : Battery load is disconnected                                        */
65266   MCUCTRL_ADCBATTLOAD_BATTLOAD_EN      = 1,     /*!< EN : Battery load is enabled                                              */
65267 } MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum;
65268 
65269 /* =======================================================  XTALCTRL  ======================================================== */
65270 /* =========================================  MCUCTRL XTALCTRL XTALCOMPPDNB [4..4]  ========================================== */
65271 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALCOMPPDNB                                             */
65272   MCUCTRL_XTALCTRL_XTALCOMPPDNB_PWRUPCOMP = 1,  /*!< PWRUPCOMP : Power up XTAL oscillator comparator.                          */
65273   MCUCTRL_XTALCTRL_XTALCOMPPDNB_PWRDNCOMP = 0,  /*!< PWRDNCOMP : Power down XTAL oscillator comparator.                        */
65274 } MCUCTRL_XTALCTRL_XTALCOMPPDNB_Enum;
65275 
65276 /* ===========================================  MCUCTRL XTALCTRL XTALPDNB [3..3]  ============================================ */
65277 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALPDNB                                                 */
65278   MCUCTRL_XTALCTRL_XTALPDNB_PWRUPCORE  = 1,     /*!< PWRUPCORE : Power up XTAL oscillator core.                                */
65279   MCUCTRL_XTALCTRL_XTALPDNB_PWRDNCORE  = 0,     /*!< PWRDNCORE : Power down XTAL oscillator core.                              */
65280 } MCUCTRL_XTALCTRL_XTALPDNB_Enum;
65281 
65282 /* ========================================  MCUCTRL XTALCTRL XTALCOMPBYPASS [2..2]  ========================================= */
65283 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALCOMPBYPASS                                           */
65284   MCUCTRL_XTALCTRL_XTALCOMPBYPASS_USECOMP = 0,  /*!< USECOMP : Use the XTAL oscillator comparator.                             */
65285   MCUCTRL_XTALCTRL_XTALCOMPBYPASS_BYPCOMP = 1,  /*!< BYPCOMP : Bypass the XTAL oscillator comparator.                          */
65286 } MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Enum;
65287 
65288 /* =========================================  MCUCTRL XTALCTRL XTALCOREDISFB [1..1]  ========================================= */
65289 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALCOREDISFB                                            */
65290   MCUCTRL_XTALCTRL_XTALCOREDISFB_EN    = 0,     /*!< EN : Enable XTAL oscillator comparator.                                   */
65291   MCUCTRL_XTALCTRL_XTALCOREDISFB_DIS   = 1,     /*!< DIS : Disable XTAL oscillator comparator.                                 */
65292 } MCUCTRL_XTALCTRL_XTALCOREDISFB_Enum;
65293 
65294 /* ============================================  MCUCTRL XTALCTRL XTALSWE [0..0]  ============================================ */
65295 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALSWE                                                  */
65296   MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0,    /*!< OVERRIDE_DIS : XTAL Software Override Disable.                            */
65297   MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1,     /*!< OVERRIDE_EN : XTAL Software Override Enable.                              */
65298 } MCUCTRL_XTALCTRL_XTALSWE_Enum;
65299 
65300 /* ======================================================  XTALGENCTRL  ====================================================== */
65301 /* ==========================================  MCUCTRL XTALGENCTRL ACWARMUP [0..1]  ========================================== */
65302 typedef enum {                                  /*!< MCUCTRL_XTALGENCTRL_ACWARMUP                                              */
65303   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1    = 0,     /*!< SEC1 : Warmup period of 1-2 seconds                                       */
65304   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2    = 1,     /*!< SEC2 : Warmup period of 2-4 seconds                                       */
65305   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4    = 2,     /*!< SEC4 : Warmup period of 4-8 seconds                                       */
65306   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8    = 3,     /*!< SEC8 : Warmup period of 8-16 seconds                                      */
65307 } MCUCTRL_XTALGENCTRL_ACWARMUP_Enum;
65308 
65309 /* ======================================================  XTALHSTRIMS  ====================================================== */
65310 /* ======================================================  XTALHSCTRL  ======================================================= */
65311 /* ======================================================  MRAMPWRCTRL  ====================================================== */
65312 /* =======================================================  BODISABLE  ======================================================= */
65313 /* ==========================================  MCUCTRL BODISABLE BODCLVREN [4..4]  =========================================== */
65314 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODCLVREN                                               */
65315   MCUCTRL_BODISABLE_BODCLVREN_EN       = 1,     /*!< EN : Enable VDDC_LV Brown Out reset.                                      */
65316   MCUCTRL_BODISABLE_BODCLVREN_DIS      = 0,     /*!< DIS : Disable VDDC_LV Brown Out reset.                                    */
65317 } MCUCTRL_BODISABLE_BODCLVREN_Enum;
65318 
65319 /* ===========================================  MCUCTRL BODISABLE BODSREN [3..3]  ============================================ */
65320 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODSREN                                                 */
65321   MCUCTRL_BODISABLE_BODSREN_EN         = 1,     /*!< EN : Enable VDDS Brown Out reset.                                         */
65322   MCUCTRL_BODISABLE_BODSREN_DIS        = 0,     /*!< DIS : Disable VDDS Brown Out reset.                                       */
65323 } MCUCTRL_BODISABLE_BODSREN_Enum;
65324 
65325 /* ===========================================  MCUCTRL BODISABLE BODFREN [2..2]  ============================================ */
65326 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODFREN                                                 */
65327   MCUCTRL_BODISABLE_BODFREN_EN         = 1,     /*!< EN : Enable VDDF Brown Out reset.                                         */
65328   MCUCTRL_BODISABLE_BODFREN_DIS        = 0,     /*!< DIS : Disable VDDF Brown Out reset.                                       */
65329 } MCUCTRL_BODISABLE_BODFREN_Enum;
65330 
65331 /* ===========================================  MCUCTRL BODISABLE BODCREN [1..1]  ============================================ */
65332 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODCREN                                                 */
65333   MCUCTRL_BODISABLE_BODCREN_EN         = 1,     /*!< EN : Enable VDDC Brown Out reset.                                         */
65334   MCUCTRL_BODISABLE_BODCREN_DIS        = 0,     /*!< DIS : Disable VDDC Brown Out reset.                                       */
65335 } MCUCTRL_BODISABLE_BODCREN_Enum;
65336 
65337 /* ===========================================  MCUCTRL BODISABLE BODLRDE [0..0]  ============================================ */
65338 typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODLRDE                                                 */
65339   MCUCTRL_BODISABLE_BODLRDE_EN         = 0,     /*!< EN : Enable Unregulated 1.8v brown out reset.                             */
65340   MCUCTRL_BODISABLE_BODLRDE_DIS        = 1,     /*!< DIS : Disable Unregulated 1.8v brown out reset.                           */
65341 } MCUCTRL_BODISABLE_BODLRDE_Enum;
65342 
65343 /* =======================================================  D2ASPARE  ======================================================== */
65344 /* ======================================================  BOOTLOADER  ======================================================= */
65345 /* =======================================  MCUCTRL BOOTLOADER SECBOOTONRST [30..31]  ======================================== */
65346 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTONRST                                           */
65347   MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0, /*!< DISABLED : Secure boot disabled                                           */
65348   MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1,  /*!< ENABLED : Secure boot enabled                                             */
65349   MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2,    /*!< ERROR : Error in secure boot configuration                                */
65350 } MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum;
65351 
65352 /* ==========================================  MCUCTRL BOOTLOADER SECBOOT [28..29]  ========================================== */
65353 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOT                                                */
65354   MCUCTRL_BOOTLOADER_SECBOOT_DISABLED  = 0,     /*!< DISABLED : Secure boot disabled                                           */
65355   MCUCTRL_BOOTLOADER_SECBOOT_ENABLED   = 1,     /*!< ENABLED : Secure boot enabled                                             */
65356   MCUCTRL_BOOTLOADER_SECBOOT_ERROR     = 2,     /*!< ERROR : Error in secure boot configuration                                */
65357 } MCUCTRL_BOOTLOADER_SECBOOT_Enum;
65358 
65359 /* ======================================  MCUCTRL BOOTLOADER SECBOOTFEATURE [26..27]  ======================================= */
65360 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTFEATURE                                         */
65361   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0,/*!< DISABLED : Secure boot disabled                                          */
65362   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1,/*!< ENABLED : Secure boot enabled                                             */
65363   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2,  /*!< ERROR : Error in secure boot configuration                                */
65364 } MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum;
65365 
65366 /* ===========================================  MCUCTRL BOOTLOADER SBLLOCK [3..3]  =========================================== */
65367 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SBLLOCK                                                */
65368   MCUCTRL_BOOTLOADER_SBLLOCK_LOCK      = 1,     /*!< LOCK : Enable the secure boot lock                                        */
65369   MCUCTRL_BOOTLOADER_SBLLOCK_UNLOCK    = 0,     /*!< UNLOCK : Disable the secure boot lock                                     */
65370 } MCUCTRL_BOOTLOADER_SBLLOCK_Enum;
65371 
65372 /* ==========================================  MCUCTRL BOOTLOADER PROTLOCK [2..2]  =========================================== */
65373 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_PROTLOCK                                               */
65374   MCUCTRL_BOOTLOADER_PROTLOCK_LOCK     = 1,     /*!< LOCK : Enable the secure boot lock                                        */
65375   MCUCTRL_BOOTLOADER_PROTLOCK_DEFAULT  = 0,     /*!< DEFAULT : Default value.                                                  */
65376 } MCUCTRL_BOOTLOADER_PROTLOCK_Enum;
65377 
65378 /* ===========================================  MCUCTRL BOOTLOADER SBRLOCK [1..1]  =========================================== */
65379 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SBRLOCK                                                */
65380   MCUCTRL_BOOTLOADER_SBRLOCK_LOCK      = 1,     /*!< LOCK : Enable the secure boot lock                                        */
65381   MCUCTRL_BOOTLOADER_SBRLOCK_DEFAULT   = 0,     /*!< DEFAULT : Default value.                                                  */
65382 } MCUCTRL_BOOTLOADER_SBRLOCK_Enum;
65383 
65384 /* ========================================  MCUCTRL BOOTLOADER BOOTLOADERLOW [0..0]  ======================================== */
65385 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_BOOTLOADERLOW                                          */
65386   MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1,   /*!< ADDR0 : Bootloader code at 0x00000000.                                    */
65387   MCUCTRL_BOOTLOADER_BOOTLOADERLOW_NOADDR0 = 0, /*!< NOADDR0 : Bootloader code is not visible at address                       */
65388 } MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum;
65389 
65390 /* ======================================================  SHADOWVALID  ====================================================== */
65391 /* =========================================  MCUCTRL SHADOWVALID INFO0VALID [2..2]  ========================================= */
65392 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_INFO0VALID                                            */
65393   MCUCTRL_SHADOWVALID_INFO0VALID_VALID = 1,     /*!< VALID : Flash info0 (customer) space contains valid data.                 */
65394   MCUCTRL_SHADOWVALID_INFO0VALID_DEFAULT = 0,   /*!< DEFAULT : Default value.                                                  */
65395 } MCUCTRL_SHADOWVALID_INFO0VALID_Enum;
65396 
65397 /* ==========================================  MCUCTRL SHADOWVALID BLDSLEEP [1..1]  ========================================== */
65398 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_BLDSLEEP                                              */
65399   MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1,   /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image
65400                                                      loaded                                                                    */
65401   MCUCTRL_SHADOWVALID_BLDSLEEP_SLEEP   = 0,     /*!< SLEEP : Bootloader will go to normalsleep if no flash image
65402                                                      loaded                                                                    */
65403 } MCUCTRL_SHADOWVALID_BLDSLEEP_Enum;
65404 
65405 /* ===========================================  MCUCTRL SHADOWVALID VALID [0..0]  ============================================ */
65406 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_VALID                                                 */
65407   MCUCTRL_SHADOWVALID_VALID_VALID      = 1,     /*!< VALID : Flash information space contains valid data.                      */
65408   MCUCTRL_SHADOWVALID_VALID_DEFAULT    = 0,     /*!< DEFAULT : Default value.                                                  */
65409 } MCUCTRL_SHADOWVALID_VALID_Enum;
65410 
65411 /* =======================================================  SCRATCH0  ======================================================== */
65412 /* =======================================================  SCRATCH1  ======================================================== */
65413 /* =========================================================  DBGR1  ========================================================= */
65414 /* =========================================================  DBGR2  ========================================================= */
65415 /* =======================================================  PMUENABLE  ======================================================= */
65416 /* ============================================  MCUCTRL PMUENABLE ENABLE [0..0]  ============================================ */
65417 typedef enum {                                  /*!< MCUCTRL_PMUENABLE_ENABLE                                                  */
65418   MCUCTRL_PMUENABLE_ENABLE_DIS         = 0,     /*!< DIS : Disable MCU power management.                                       */
65419   MCUCTRL_PMUENABLE_ENABLE_EN          = 1,     /*!< EN : Enable MCU power management.                                         */
65420 } MCUCTRL_PMUENABLE_ENABLE_Enum;
65421 
65422 /* ========================================================  DBGCTRL  ======================================================== */
65423 /* =====================================  MCUCTRL DBGCTRL DBGDSP1OCDHALTONRST [17..17]  ====================================== */
65424 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST                                       */
65425   MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_DIS = 0,  /*!< DIS : Disable DSP1 OCD Halt on Reset.                                     */
65426   MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_EN = 1,   /*!< EN : Enable DSP1 OCD Halt on Reset.                                       */
65427 } MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Enum;
65428 
65429 /* =====================================  MCUCTRL DBGCTRL DBGDSP0OCDHALTONRST [16..16]  ====================================== */
65430 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST                                       */
65431   MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_DIS = 0,  /*!< DIS : Disable DSP0 OCD Halt on Reset.                                     */
65432   MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_EN = 1,   /*!< EN : Enable DSP0 OCD Halt on Reset.                                       */
65433 } MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Enum;
65434 
65435 /* =========================================  MCUCTRL DBGCTRL DBGTSCLKSEL [12..14]  ========================================== */
65436 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGTSCLKSEL                                               */
65437   MCUCTRL_DBGCTRL_DBGTSCLKSEL_LOWPWR   = 0,     /*!< LOWPWR : Low power state.                                                 */
65438   MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV2 = 1,     /*!< HFRCDIV2 : Selects HFRC divided by 2 as the source dbg ts clk             */
65439   MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV8 = 2,     /*!< HFRCDIV8 : Selects HFRC divided by 8 as the source dbg ts clk             */
65440   MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV16 = 3,    /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source dbg ts
65441                                                      clk                                                                       */
65442   MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV32 = 4,    /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source dbg ts
65443                                                      clk                                                                       */
65444 } MCUCTRL_DBGCTRL_DBGTSCLKSEL_Enum;
65445 
65446 /* ========================================  MCUCTRL DBGCTRL DBGDSP1TRACEEN [11..11]  ======================================== */
65447 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP1TRACEEN                                            */
65448   MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_DIS   = 0,     /*!< DIS : Disable DSP1 trace.                                                 */
65449   MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_EN    = 1,     /*!< EN : Enable DSP1 trace.                                                   */
65450 } MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Enum;
65451 
65452 /* ========================================  MCUCTRL DBGCTRL DBGDSP0TRACEEN [10..10]  ======================================== */
65453 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP0TRACEEN                                            */
65454   MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_DIS   = 0,     /*!< DIS : Disable DSP0 trace.                                                 */
65455   MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_EN    = 1,     /*!< EN : Enable DSP0 trace.                                                   */
65456 } MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Enum;
65457 
65458 /* =========================================  MCUCTRL DBGCTRL DBGETMTRACEEN [9..9]  ========================================== */
65459 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGETMTRACEEN                                             */
65460   MCUCTRL_DBGCTRL_DBGETMTRACEEN_DIS    = 0,     /*!< DIS : Disable ETM trace.                                                  */
65461   MCUCTRL_DBGCTRL_DBGETMTRACEEN_EN     = 1,     /*!< EN : Enable ETM trace.                                                    */
65462 } MCUCTRL_DBGCTRL_DBGETMTRACEEN_Enum;
65463 
65464 /* ==========================================  MCUCTRL DBGCTRL DBGETBENABLE [8..8]  ========================================== */
65465 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGETBENABLE                                              */
65466   MCUCTRL_DBGCTRL_DBGETBENABLE_DIS     = 0,     /*!< DIS : Disable ETB.                                                        */
65467   MCUCTRL_DBGCTRL_DBGETBENABLE_EN      = 1,     /*!< EN : Enable ETB.                                                          */
65468 } MCUCTRL_DBGCTRL_DBGETBENABLE_Enum;
65469 
65470 /* ===========================================  MCUCTRL DBGCTRL CM4CLKSEL [1..3]  ============================================ */
65471 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_CM4CLKSEL                                                 */
65472   MCUCTRL_DBGCTRL_CM4CLKSEL_LOWPWR     = 0,     /*!< LOWPWR : Low power state.                                                 */
65473   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC96     = 1,     /*!< HFRC96 : Selects HFRC 96Mhz as the source TPIU clk                        */
65474   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC48     = 2,     /*!< HFRC48 : Selects HFRC 48Mhz as the source TPIU clk                        */
65475   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC24     = 3,     /*!< HFRC24 : Selects HFRC 24Mhz as the source TPIU clk                        */
65476   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC6      = 4,     /*!< HFRC6 : Selects HFRC 6Mhz as the source TPIU clk                          */
65477   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC3      = 5,     /*!< HFRC3 : Selects HFRC 3Mhz as the source TPIU clk                          */
65478   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC1P5    = 6,     /*!< HFRC1P5 : Selects HFRC 1.5Mhz as the source TPIU clk                      */
65479   MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC2_192  = 7,     /*!< HFRC2_192 : Selects HFRC2 192Mhz as the source TPIU clk. Note
65480                                                      that this setting requires CLKGEN.MISC.HFRC2 be enabled.                  */
65481 } MCUCTRL_DBGCTRL_CM4CLKSEL_Enum;
65482 
65483 /* =========================================  MCUCTRL DBGCTRL CM4TPIUENABLE [0..0]  ========================================== */
65484 typedef enum {                                  /*!< MCUCTRL_DBGCTRL_CM4TPIUENABLE                                             */
65485   MCUCTRL_DBGCTRL_CM4TPIUENABLE_DIS    = 0,     /*!< DIS : Disable the TPIU.                                                   */
65486   MCUCTRL_DBGCTRL_CM4TPIUENABLE_EN     = 1,     /*!< EN : Enable the TPIU.                                                     */
65487 } MCUCTRL_DBGCTRL_CM4TPIUENABLE_Enum;
65488 
65489 /* ======================================================  OTAPOINTER  ======================================================= */
65490 /* ======================================================  APBDMACTRL  ======================================================= */
65491 /* =========================================  MCUCTRL APBDMACTRL DECODEABORT [1..1]  ========================================= */
65492 typedef enum {                                  /*!< MCUCTRL_APBDMACTRL_DECODEABORT                                            */
65493   MCUCTRL_APBDMACTRL_DECODEABORT_DISABLE = 0,   /*!< DISABLE : Bus operations to powered down peripherals are quietly
65494                                                      discarded                                                                 */
65495   MCUCTRL_APBDMACTRL_DECODEABORT_ENABLE = 1,    /*!< ENABLE : Bus operations to powered down peripherals result in
65496                                                      a bus fault.                                                              */
65497 } MCUCTRL_APBDMACTRL_DECODEABORT_Enum;
65498 
65499 /* ==========================================  MCUCTRL APBDMACTRL DMAENABLE [0..0]  ========================================== */
65500 typedef enum {                                  /*!< MCUCTRL_APBDMACTRL_DMAENABLE                                              */
65501   MCUCTRL_APBDMACTRL_DMAENABLE_DISABLE = 0,     /*!< DISABLE : DMA operations disabled                                         */
65502   MCUCTRL_APBDMACTRL_DMAENABLE_ENABLE  = 1,     /*!< ENABLE : DMA operations enabled                                           */
65503 } MCUCTRL_APBDMACTRL_DMAENABLE_Enum;
65504 
65505 /* ======================================================  KEXTCLKSEL  ======================================================= */
65506 /* =========================================  MCUCTRL KEXTCLKSEL KEXTCLKSEL [0..31]  ========================================= */
65507 typedef enum {                                  /*!< MCUCTRL_KEXTCLKSEL_KEXTCLKSEL                                             */
65508   MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key    = 83,    /*!< Key : Key value to unlock the register.                                   */
65509 } MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum;
65510 
65511 /* =======================================================  SIMOBUCK0  ======================================================= */
65512 /* =======================================================  SIMOBUCK1  ======================================================= */
65513 /* =======================================================  SIMOBUCK2  ======================================================= */
65514 /* =======================================================  SIMOBUCK3  ======================================================= */
65515 /* =======================================================  SIMOBUCK6  ======================================================= */
65516 /* =======================================================  SIMOBUCK7  ======================================================= */
65517 /* =======================================================  SIMOBUCK8  ======================================================= */
65518 /* =======================================================  SIMOBUCK9  ======================================================= */
65519 /* ======================================================  SIMOBUCK12  ======================================================= */
65520 /* ======================================================  SIMOBUCK13  ======================================================= */
65521 /* ======================================================  SIMOBUCK15  ======================================================= */
65522 /* ========================================================  PWRSW0  ========================================================= */
65523 /* ======================================  MCUCTRL PWRSW0 PWRSWVDDRCPUSTATSEL [30..30]  ====================================== */
65524 typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL                                        */
65525   MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_VDDC = 1,  /*!< VDDC : Select VDDC rail                                                   */
65526   MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_VDDFLP = 0,/*!< VDDFLP : Select VDDFLP rail                                               */
65527 } MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Enum;
65528 
65529 /* =======================================  MCUCTRL PWRSW0 PWRSWVDDMLSTATSEL [25..25]  ======================================= */
65530 typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL                                          */
65531   MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_VDDC = 0,    /*!< VDDC : Select VDDC rail                                                   */
65532   MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_VDDF = 1,    /*!< VDDF : Select VDDF rail                                                   */
65533 } MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_Enum;
65534 
65535 /* =====================================  MCUCTRL PWRSW0 PWRSWVDDMDSP1STATSEL [22..22]  ====================================== */
65536 typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL                                       */
65537   MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_VDDC = 0, /*!< VDDC : Select VDDC rail                                                   */
65538   MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_VDDF = 1, /*!< VDDF : Select VDDF rail                                                   */
65539 } MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Enum;
65540 
65541 /* =====================================  MCUCTRL PWRSW0 PWRSWVDDMDSP0STATSEL [19..19]  ====================================== */
65542 typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL                                       */
65543   MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_VDDC = 0, /*!< VDDC : Select VDDC rail                                                   */
65544   MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_VDDF = 1, /*!< VDDF : Select VDDF rail                                                   */
65545 } MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Enum;
65546 
65547 /* ======================================  MCUCTRL PWRSW0 PWRSWVDDMCPUSTATSEL [16..16]  ====================================== */
65548 typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL                                        */
65549   MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_VDDC = 0,  /*!< VDDC : Select VDDC rail                                                   */
65550   MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_VDDF = 1,  /*!< VDDF : Select VDDF rail                                                   */
65551 } MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Enum;
65552 
65553 /* ========================================================  PWRSW1  ========================================================= */
65554 /* =======================================  MCUCTRL PWRSW1 PWRSWVDDRMSTATSEL [16..16]  ======================================= */
65555 typedef enum {                                  /*!< MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL                                          */
65556   MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_VDDC = 1,    /*!< VDDC : Select VDDC rail                                                   */
65557   MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_VDDFLP = 0,  /*!< VDDFLP : Select VDDFLP rail                                               */
65558 } MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_Enum;
65559 
65560 /* =======================================  MCUCTRL PWRSW1 PWRSWVDDRLSTATSEL [12..12]  ======================================= */
65561 typedef enum {                                  /*!< MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL                                          */
65562   MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_VDDC = 1,    /*!< VDDC : Select VDDC rail                                                   */
65563   MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_VDDFLP = 0,  /*!< VDDFLP : Select VDDFLP rail                                               */
65564 } MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_Enum;
65565 
65566 /* ======================================  MCUCTRL PWRSW1 PWRSWVDDRDSP1STATSEL [8..8]  ======================================= */
65567 typedef enum {                                  /*!< MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL                                       */
65568   MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_VDDC = 1, /*!< VDDC : Select VDDC rail                                                   */
65569   MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_VDDFLP = 0,/*!< VDDFLP : Select VDDFLP rail                                              */
65570 } MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_Enum;
65571 
65572 /* ======================================  MCUCTRL PWRSW1 PWRSWVDDRDSP0STATSEL [3..3]  ======================================= */
65573 typedef enum {                                  /*!< MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL                                       */
65574   MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_VDDC = 1, /*!< VDDC : Select VDDC rail                                                   */
65575   MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_VDDFLP = 0,/*!< VDDFLP : Select VDDFLP rail                                              */
65576 } MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_Enum;
65577 
65578 /* ======================================================  USBRSTCTRL  ======================================================= */
65579 /* ======================================================  FLASHWPROT0  ====================================================== */
65580 /* ======================================================  FLASHWPROT1  ====================================================== */
65581 /* ======================================================  FLASHWPROT2  ====================================================== */
65582 /* ======================================================  FLASHWPROT3  ====================================================== */
65583 /* ======================================================  FLASHRPROT0  ====================================================== */
65584 /* ======================================================  FLASHRPROT1  ====================================================== */
65585 /* ======================================================  FLASHRPROT2  ====================================================== */
65586 /* ======================================================  FLASHRPROT3  ====================================================== */
65587 /* =====================================================  DMASRAMWPROT0  ===================================================== */
65588 /* =====================================================  DMASRAMWPROT1  ===================================================== */
65589 /* =====================================================  DMASRAMRPROT0  ===================================================== */
65590 /* =====================================================  DMASRAMRPROT1  ===================================================== */
65591 /* ======================================================  USBPHYRESET  ====================================================== */
65592 /* =====================================================  AUDADCPWRCTRL  ===================================================== */
65593 /* ====================================  MCUCTRL AUDADCPWRCTRL VDDAUDADCRESETN [10..10]  ===================================== */
65594 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN                                     */
65595   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_ASSERT = 0,/*!< ASSERT : Resetn is asserted                                            */
65596   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_DEASSERT = 1,/*!< DEASSERT : Resetn is de-asserted                                     */
65597 } MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Enum;
65598 
65599 /* ===================================  MCUCTRL AUDADCPWRCTRL VDDAUDADCDIGISOLATE [9..9]  ==================================== */
65600 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE                                 */
65601   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_DIS = 0,/*!< DIS : No Isolation                                                    */
65602   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_EN = 1,/*!< EN : Isolate                                                           */
65603 } MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Enum;
65604 
65605 /* ===================================  MCUCTRL AUDADCPWRCTRL VDDAUDADCSARISOLATE [8..8]  ==================================== */
65606 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE                                 */
65607   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_DIS = 0,/*!< DIS : No Isolation                                                    */
65608   MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_EN = 1,/*!< EN : Isolate                                                           */
65609 } MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Enum;
65610 
65611 /* ======================================  MCUCTRL AUDADCPWRCTRL AUDREFKEEPPEN [5..5]  ======================================= */
65612 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN                                       */
65613   MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_DIS = 0,  /*!< DIS : Reference Buffer Keeper Power Switch disable.                       */
65614   MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_EN = 1,   /*!< EN : Reference Buffer Keeper Power Switch enable.                         */
65615 } MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Enum;
65616 
65617 /* =======================================  MCUCTRL AUDADCPWRCTRL AUDREFBUFPEN [4..4]  ======================================= */
65618 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN                                        */
65619   MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_DIS = 0,   /*!< DIS : Reference Buffer Power Switch disable.                              */
65620   MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_EN = 1,    /*!< EN : Reference Buffer Power Switch enable.                                */
65621 } MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Enum;
65622 
65623 /* ========================================  MCUCTRL AUDADCPWRCTRL AUDBGTPEN [3..3]  ========================================= */
65624 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN                                           */
65625   MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_DIS  = 0,     /*!< DIS : Bandgap and temperature sensor disable.                             */
65626   MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_EN   = 1,     /*!< EN : Bandgap and temperature sensor enable.                               */
65627 } MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Enum;
65628 
65629 /* =======================================  MCUCTRL AUDADCPWRCTRL AUDADCBPSEN [2..2]  ======================================== */
65630 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN                                         */
65631   MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_DIS = 0,    /*!< DIS : AUDADC power switch software power disable.                         */
65632   MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_EN = 1,     /*!< EN : AUDADC power switch software power enable.                           */
65633 } MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Enum;
65634 
65635 /* =======================================  MCUCTRL AUDADCPWRCTRL AUDADCAPSEN [1..1]  ======================================== */
65636 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN                                         */
65637   MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_DIS = 0,    /*!< DIS : AUDADC power switch software power disable.                         */
65638   MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_EN = 1,     /*!< EN : AUDADC power switch software power enable.                           */
65639 } MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Enum;
65640 
65641 /* =====================================  MCUCTRL AUDADCPWRCTRL AUDADCPWRCTRLSWE [0..0]  ===================================== */
65642 typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE                                    */
65643   MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_OVERRIDE_DIS = 0,/*!< OVERRIDE_DIS : Audio ADC temperature sensor and bandgap Software
65644                                                      Override Disable.                                                         */
65645   MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_OVERRIDE_EN = 1,/*!< OVERRIDE_EN : Audio ADC temperature sensor and bandgap Software
65646                                                      Override Enable.                                                          */
65647 } MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Enum;
65648 
65649 /* ========================================================  AUDIO1  ========================================================= */
65650 /* =====================================================  PGAADCIFCTRL  ====================================================== */
65651 /* =======================================================  PGACTRL1  ======================================================== */
65652 /* =======================================================  PGACTRL2  ======================================================== */
65653 /* =====================================================  AUDADCPWRDLY  ====================================================== */
65654 /* =======================================================  SDIOCTRL  ======================================================== */
65655 /* ========================================================  PDMCTRL  ======================================================== */
65656 
65657 
65658 /* =========================================================================================================================== */
65659 /* ================                                           MSPI0                                           ================ */
65660 /* =========================================================================================================================== */
65661 
65662 /* =========================================================  CTRL  ========================================================== */
65663 /* ===============================================  MSPI0 CTRL PIODEV [4..4]  ================================================ */
65664 typedef enum {                                  /*!< MSPI0_CTRL_PIODEV                                                         */
65665   MSPI0_CTRL_PIODEV_DEVICE0            = 0,     /*!< DEVICE0 : Use DEVICE0 Configuration                                       */
65666   MSPI0_CTRL_PIODEV_DEVICE1            = 1,     /*!< DEVICE1 : Use DEVICE1 CONFIGURATION                                       */
65667 } MSPI0_CTRL_PIODEV_Enum;
65668 
65669 /* =========================================================  CTRL1  ========================================================= */
65670 /* ==============================================  MSPI0 CTRL1 PIOMIXED [0..3]  ============================================== */
65671 typedef enum {                                  /*!< MSPI0_CTRL1_PIOMIXED                                                      */
65672   MSPI0_CTRL1_PIOMIXED_NORMAL          = 0,     /*!< NORMAL : Transfers all proceed using the settings in DEVCFG
65673                                                      register (everything in the same data rate)                               */
65674   MSPI0_CTRL1_PIOMIXED_D2              = 1,     /*!< D2 : Data operations proceed in dual data rate                            */
65675   MSPI0_CTRL1_PIOMIXED_AD2             = 3,     /*!< AD2 : Address and Data operations proceed in dual data rate               */
65676   MSPI0_CTRL1_PIOMIXED_D4              = 5,     /*!< D4 : Data operations proceed in quad data rate                            */
65677   MSPI0_CTRL1_PIOMIXED_AD4             = 7,     /*!< AD4 : Address and Data operations proceed in quad data rate               */
65678   MSPI0_CTRL1_PIOMIXED_D8              = 9,     /*!< D8 : Data operations proceed in octal data rate                           */
65679   MSPI0_CTRL1_PIOMIXED_AD8             = 11,    /*!< AD8 : Address and Data operations proceed in octal data rate              */
65680 } MSPI0_CTRL1_PIOMIXED_Enum;
65681 
65682 /* =========================================================  ADDR  ========================================================== */
65683 /* =========================================================  INSTR  ========================================================= */
65684 /* ========================================================  TXFIFO  ========================================================= */
65685 /* ========================================================  RXFIFO  ========================================================= */
65686 /* =======================================================  TXENTRIES  ======================================================= */
65687 /* =======================================================  RXENTRIES  ======================================================= */
65688 /* =======================================================  THRESHOLD  ======================================================= */
65689 /* ========================================================  MSPICFG  ======================================================== */
65690 /* ==============================================  MSPI0 MSPICFG IOMSEL [4..7]  ============================================== */
65691 typedef enum {                                  /*!< MSPI0_MSPICFG_IOMSEL                                                      */
65692   MSPI0_MSPICFG_IOMSEL_IOM0            = 0,     /*!< IOM0 : ERROR: desc VALUE MISSING                                          */
65693   MSPI0_MSPICFG_IOMSEL_IOM1            = 1,     /*!< IOM1 : ERROR: desc VALUE MISSING                                          */
65694   MSPI0_MSPICFG_IOMSEL_IOM2            = 2,     /*!< IOM2 : ERROR: desc VALUE MISSING                                          */
65695   MSPI0_MSPICFG_IOMSEL_IOM3            = 3,     /*!< IOM3 : ERROR: desc VALUE MISSING                                          */
65696   MSPI0_MSPICFG_IOMSEL_IOM4            = 4,     /*!< IOM4 : ERROR: desc VALUE MISSING                                          */
65697   MSPI0_MSPICFG_IOMSEL_IOM5            = 5,     /*!< IOM5 : ERROR: desc VALUE MISSING                                          */
65698   MSPI0_MSPICFG_IOMSEL_IOM6            = 6,     /*!< IOM6 : ERROR: desc VALUE MISSING                                          */
65699   MSPI0_MSPICFG_IOMSEL_IOM7            = 7,     /*!< IOM7 : ERROR: desc VALUE MISSING                                          */
65700   MSPI0_MSPICFG_IOMSEL_MSPI0           = 8,     /*!< MSPI0 : ERROR: desc VALUE MISSING                                         */
65701   MSPI0_MSPICFG_IOMSEL_MSPI1           = 9,     /*!< MSPI1 : ERROR: desc VALUE MISSING                                         */
65702   MSPI0_MSPICFG_IOMSEL_MSPI2           = 10,    /*!< MSPI2 : ERROR: desc VALUE MISSING                                         */
65703 } MSPI0_MSPICFG_IOMSEL_Enum;
65704 
65705 /* ==============================================  MSPI0 MSPICFG APBCLK [0..0]  ============================================== */
65706 typedef enum {                                  /*!< MSPI0_MSPICFG_APBCLK                                                      */
65707   MSPI0_MSPICFG_APBCLK_DIS             = 0,     /*!< DIS : Disable continuous clock.                                           */
65708   MSPI0_MSPICFG_APBCLK_EN              = 1,     /*!< EN : Enable continuous clock.                                             */
65709 } MSPI0_MSPICFG_APBCLK_Enum;
65710 
65711 /* =======================================================  PADOUTEN  ======================================================== */
65712 /* =============================================  MSPI0 PADOUTEN OUTEN [0..19]  ============================================== */
65713 typedef enum {                                  /*!< MSPI0_PADOUTEN_OUTEN                                                      */
65714   MSPI0_PADOUTEN_OUTEN_QUAD0           = 271,   /*!< QUAD0 : Quad0 (4 data + 1 clock)                                          */
65715   MSPI0_PADOUTEN_OUTEN_QUAD1           = 496,   /*!< QUAD1 : Quad1 (4 data + 1 clock)                                          */
65716   MSPI0_PADOUTEN_OUTEN_OCTAL           = 1023,  /*!< OCTAL : Octal (8 data + 1 clock)                                          */
65717   MSPI0_PADOUTEN_OUTEN_SERIAL0         = 259,   /*!< SERIAL0 : Serial (2 data + 1 clock)                                       */
65718   MSPI0_PADOUTEN_OUTEN_SERIAL1         = 304,   /*!< SERIAL1 : Serial (2 data + 1 clock)                                       */
65719   MSPI0_PADOUTEN_OUTEN_HEX             = 524287,/*!< HEX : Octal (16 data + 1 clock + 2 bytemask)                              */
65720 } MSPI0_PADOUTEN_OUTEN_Enum;
65721 
65722 /* =======================================================  PADOVEREN  ======================================================= */
65723 /* ========================================================  PADOVER  ======================================================== */
65724 /* ========================================================  DEV0AXI  ======================================================== */
65725 /* ============================================  MSPI0 DEV0AXI READONLY0 [4..4]  ============================================= */
65726 typedef enum {                                  /*!< MSPI0_DEV0AXI_READONLY0                                                   */
65727   MSPI0_DEV0AXI_READONLY0_READONLY     = 1,     /*!< READONLY : Indicates AXI aperture only supports read operations           */
65728   MSPI0_DEV0AXI_READONLY0_READWRITE    = 0,     /*!< READWRITE : Indicates AXI aperture supports read and write operations     */
65729 } MSPI0_DEV0AXI_READONLY0_Enum;
65730 
65731 /* ==============================================  MSPI0 DEV0AXI SIZE0 [0..3]  =============================================== */
65732 typedef enum {                                  /*!< MSPI0_DEV0AXI_SIZE0                                                       */
65733   MSPI0_DEV0AXI_SIZE0_SIZE64K          = 0,     /*!< SIZE64K : 64KB Aperture                                                   */
65734   MSPI0_DEV0AXI_SIZE0_SIZE128K         = 1,     /*!< SIZE128K : 128KB Aperture                                                 */
65735   MSPI0_DEV0AXI_SIZE0_SIZE256K         = 2,     /*!< SIZE256K : 256KB Aperture                                                 */
65736   MSPI0_DEV0AXI_SIZE0_SIZE512K         = 3,     /*!< SIZE512K : 512KB Aperture                                                 */
65737   MSPI0_DEV0AXI_SIZE0_SIZE1M           = 4,     /*!< SIZE1M : 1MB Aperture                                                     */
65738   MSPI0_DEV0AXI_SIZE0_SIZE2M           = 5,     /*!< SIZE2M : 2MB Aperture                                                     */
65739   MSPI0_DEV0AXI_SIZE0_SIZE4M           = 6,     /*!< SIZE4M : 4MB Aperture                                                     */
65740   MSPI0_DEV0AXI_SIZE0_SIZE8M           = 7,     /*!< SIZE8M : 8MB Aperture                                                     */
65741   MSPI0_DEV0AXI_SIZE0_SIZE16M          = 8,     /*!< SIZE16M : 16MB Aperture                                                   */
65742   MSPI0_DEV0AXI_SIZE0_SIZE32M          = 9,     /*!< SIZE32M : 32MB Aperture                                                   */
65743   MSPI0_DEV0AXI_SIZE0_SIZE64M          = 10,    /*!< SIZE64M : 64MB Aperture                                                   */
65744 } MSPI0_DEV0AXI_SIZE0_Enum;
65745 
65746 /* ========================================================  DEV0CFG  ======================================================== */
65747 /* =============================================  MSPI0 DEV0CFG TXNEG0 [24..24]  ============================================= */
65748 typedef enum {                                  /*!< MSPI0_DEV0CFG_TXNEG0                                                      */
65749   MSPI0_DEV0CFG_TXNEG0_NORMAL          = 0,     /*!< NORMAL : TX launched from posedge internal clock                          */
65750   MSPI0_DEV0CFG_TXNEG0_NEGEDGE         = 1,     /*!< NEGEDGE : TX data launched from negedge of internal clock                 */
65751 } MSPI0_DEV0CFG_TXNEG0_Enum;
65752 
65753 /* =============================================  MSPI0 DEV0CFG RXNEG0 [23..23]  ============================================= */
65754 typedef enum {                                  /*!< MSPI0_DEV0CFG_RXNEG0                                                      */
65755   MSPI0_DEV0CFG_RXNEG0_NORMAL          = 0,     /*!< NORMAL : RX data sampled on posedge of internal clock                     */
65756   MSPI0_DEV0CFG_RXNEG0_NEGEDGE         = 1,     /*!< NEGEDGE : RX data sampled on negedge of internal clock                    */
65757 } MSPI0_DEV0CFG_RXNEG0_Enum;
65758 
65759 /* =============================================  MSPI0 DEV0CFG RXCAP0 [22..22]  ============================================= */
65760 typedef enum {                                  /*!< MSPI0_DEV0CFG_RXCAP0                                                      */
65761   MSPI0_DEV0CFG_RXCAP0_NORMAL          = 0,     /*!< NORMAL : RX Capture phase aligns with CPHA setting                        */
65762   MSPI0_DEV0CFG_RXCAP0_DELAY           = 1,     /*!< DELAY : RX Capture phase is delayed from CPHA setting by one
65763                                                      clock edge                                                                */
65764 } MSPI0_DEV0CFG_RXCAP0_Enum;
65765 
65766 /* ============================================  MSPI0 DEV0CFG CLKDIV0 [16..21]  ============================================= */
65767 typedef enum {                                  /*!< MSPI0_DEV0CFG_CLKDIV0                                                     */
65768   MSPI0_DEV0CFG_CLKDIV0_CLK96          = 1,     /*!< CLK96 : 96 MHz MSPI clock                                                 */
65769   MSPI0_DEV0CFG_CLKDIV0_CLK48          = 2,     /*!< CLK48 : 48 MHz MSPI clock                                                 */
65770   MSPI0_DEV0CFG_CLKDIV0_CLK32          = 3,     /*!< CLK32 : 32 MHz MSPI clock                                                 */
65771   MSPI0_DEV0CFG_CLKDIV0_CLK24          = 4,     /*!< CLK24 : 24 MHz MSPI clock                                                 */
65772   MSPI0_DEV0CFG_CLKDIV0_CLK16          = 6,     /*!< CLK16 : 16 MHz MSPI clock                                                 */
65773   MSPI0_DEV0CFG_CLKDIV0_CLK12          = 8,     /*!< CLK12 : 12 MHz MSPI clock                                                 */
65774   MSPI0_DEV0CFG_CLKDIV0_CLK8           = 12,    /*!< CLK8 : 8 MHz MSPI clock                                                   */
65775   MSPI0_DEV0CFG_CLKDIV0_CLK6           = 16,    /*!< CLK6 : 6 MHz MSPI clock                                                   */
65776   MSPI0_DEV0CFG_CLKDIV0_CLK4           = 24,    /*!< CLK4 : 4 MHz MSPI clock                                                   */
65777   MSPI0_DEV0CFG_CLKDIV0_CLK3           = 32,    /*!< CLK3 : 3 MHz MSPI clock                                                   */
65778 } MSPI0_DEV0CFG_CLKDIV0_Enum;
65779 
65780 /* =============================================  MSPI0 DEV0CFG CPOL0 [15..15]  ============================================== */
65781 typedef enum {                                  /*!< MSPI0_DEV0CFG_CPOL0                                                       */
65782   MSPI0_DEV0CFG_CPOL0_LOW              = 0,     /*!< LOW : Clock inactive state is low.                                        */
65783   MSPI0_DEV0CFG_CPOL0_HIGH             = 1,     /*!< HIGH : Clock inactive state is high.                                      */
65784 } MSPI0_DEV0CFG_CPOL0_Enum;
65785 
65786 /* =============================================  MSPI0 DEV0CFG CPHA0 [14..14]  ============================================== */
65787 typedef enum {                                  /*!< MSPI0_DEV0CFG_CPHA0                                                       */
65788   MSPI0_DEV0CFG_CPHA0_MIDDLE           = 0,     /*!< MIDDLE : Clock toggles in middle of data bit.                             */
65789   MSPI0_DEV0CFG_CPHA0_START            = 1,     /*!< START : Clock toggles at start of data bit.                               */
65790 } MSPI0_DEV0CFG_CPHA0_Enum;
65791 
65792 /* ==============================================  MSPI0 DEV0CFG ISIZE0 [7..7]  ============================================== */
65793 typedef enum {                                  /*!< MSPI0_DEV0CFG_ISIZE0                                                      */
65794   MSPI0_DEV0CFG_ISIZE0_I8              = 0,     /*!< I8 : Instruction is 1 byte                                                */
65795   MSPI0_DEV0CFG_ISIZE0_I16             = 1,     /*!< I16 : Instruction is 2 bytes                                              */
65796 } MSPI0_DEV0CFG_ISIZE0_Enum;
65797 
65798 /* ==============================================  MSPI0 DEV0CFG ASIZE0 [5..6]  ============================================== */
65799 typedef enum {                                  /*!< MSPI0_DEV0CFG_ASIZE0                                                      */
65800   MSPI0_DEV0CFG_ASIZE0_A1              = 0,     /*!< A1 : Send one address byte                                                */
65801   MSPI0_DEV0CFG_ASIZE0_A2              = 1,     /*!< A2 : Send two address bytes                                               */
65802   MSPI0_DEV0CFG_ASIZE0_A3              = 2,     /*!< A3 : Send three address bytes                                             */
65803   MSPI0_DEV0CFG_ASIZE0_A4              = 3,     /*!< A4 : Send four address bytes                                              */
65804 } MSPI0_DEV0CFG_ASIZE0_Enum;
65805 
65806 /* =============================================  MSPI0 DEV0CFG DEVCFG0 [0..4]  ============================================== */
65807 typedef enum {                                  /*!< MSPI0_DEV0CFG_DEVCFG0                                                     */
65808   MSPI0_DEV0CFG_DEVCFG0_SERIAL0        = 1,     /*!< SERIAL0 : Single bit SPI flash on chip select 0                           */
65809   MSPI0_DEV0CFG_DEVCFG0_SERIAL1        = 2,     /*!< SERIAL1 : Single bit SPI flash on chip select 1                           */
65810   MSPI0_DEV0CFG_DEVCFG0_DUAL0          = 5,     /*!< DUAL0 : Dual SPI flash on chip select 0                                   */
65811   MSPI0_DEV0CFG_DEVCFG0_DUAL1          = 6,     /*!< DUAL1 : Dual bit SPI flash on chip select 1                               */
65812   MSPI0_DEV0CFG_DEVCFG0_QUAD0          = 9,     /*!< QUAD0 : Quad SPI flash on chip select 0                                   */
65813   MSPI0_DEV0CFG_DEVCFG0_QUAD1          = 10,    /*!< QUAD1 : Quad SPI flash on chip select 1                                   */
65814   MSPI0_DEV0CFG_DEVCFG0_OCTAL0         = 13,    /*!< OCTAL0 : Octal SPI flash on chip select 0                                 */
65815   MSPI0_DEV0CFG_DEVCFG0_OCTAL1         = 14,    /*!< OCTAL1 : Octal SPI flash on chip select 1                                 */
65816   MSPI0_DEV0CFG_DEVCFG0_QUADPAIRED     = 15,    /*!< QUADPAIRED : Dual Quad SPI flash on chip selects 0/1.                     */
65817   MSPI0_DEV0CFG_DEVCFG0_QUADPAIRED_SERIAL = 3,  /*!< QUADPAIRED_SERIAL : Dual Quad SPI flash on chip selects 0/1,
65818                                                      but transmit in serial mode for initialization operations                 */
65819   MSPI0_DEV0CFG_DEVCFG0_HEX0           = 17,    /*!< HEX0 : Hex SPI flash on chip selects 0.                                   */
65820   MSPI0_DEV0CFG_DEVCFG0_HEX1           = 18,    /*!< HEX1 : Hex SPI flash on chip selects 1.                                   */
65821 } MSPI0_DEV0CFG_DEVCFG0_Enum;
65822 
65823 /* ========================================================  DEV0DDR  ======================================================== */
65824 /* =======================================================  DEV0CFG1  ======================================================== */
65825 /* ========================================================  DEV0XIP  ======================================================== */
65826 /* ============================================  MSPI0 DEV0XIP XIPMIXED0 [8..11]  ============================================ */
65827 typedef enum {                                  /*!< MSPI0_DEV0XIP_XIPMIXED0                                                   */
65828   MSPI0_DEV0XIP_XIPMIXED0_NORMAL       = 0,     /*!< NORMAL : Transfers all proceed using the settings in DEVCFG
65829                                                      register (everything in the same data rate)                               */
65830   MSPI0_DEV0XIP_XIPMIXED0_D2           = 1,     /*!< D2 : Data operations proceed in dual data rate                            */
65831   MSPI0_DEV0XIP_XIPMIXED0_AD2          = 3,     /*!< AD2 : Address and Data operations proceed in dual data rate               */
65832   MSPI0_DEV0XIP_XIPMIXED0_D4           = 5,     /*!< D4 : Data operations proceed in quad data rate                            */
65833   MSPI0_DEV0XIP_XIPMIXED0_AD4          = 7,     /*!< AD4 : Address and Data operations proceed in quad data rate               */
65834   MSPI0_DEV0XIP_XIPMIXED0_D8           = 9,     /*!< D8 : Data operations proceed in octal data rate                           */
65835   MSPI0_DEV0XIP_XIPMIXED0_AD8          = 11,    /*!< AD8 : Address and Data operations proceed in octal data rate              */
65836 } MSPI0_DEV0XIP_XIPMIXED0_Enum;
65837 
65838 /* =============================================  MSPI0 DEV0XIP XIPACK0 [2..3]  ============================================== */
65839 typedef enum {                                  /*!< MSPI0_DEV0XIP_XIPACK0                                                     */
65840   MSPI0_DEV0XIP_XIPACK0_NOACK          = 0,     /*!< NOACK : No acknowledege sent. Data IOs are tristated the first
65841                                                      turnaround cycle                                                          */
65842   MSPI0_DEV0XIP_XIPACK0_ACK            = 2,     /*!< ACK : Positive acknowledege sent. Data IOs are driven to 0 the
65843                                                      first turnaround cycle to acknowledge XIP mode                            */
65844   MSPI0_DEV0XIP_XIPACK0_TERMINATE      = 3,     /*!< TERMINATE : Negative acknowledege sent. Data IOs are driven
65845                                                      to 1 the first turnaround cycle to terminate XIP mode.
65846                                                      XIPSENDI should be reenabled for the next transfer                        */
65847 } MSPI0_DEV0XIP_XIPACK0_Enum;
65848 
65849 /* =======================================================  DEV0INSTR  ======================================================= */
65850 /* =====================================================  DEV0BOUNDARY  ====================================================== */
65851 /* =========================================  MSPI0 DEV0BOUNDARY DMABOUND0 [12..15]  ========================================= */
65852 typedef enum {                                  /*!< MSPI0_DEV0BOUNDARY_DMABOUND0                                              */
65853   MSPI0_DEV0BOUNDARY_DMABOUND0_NONE    = 0,     /*!< NONE : Disable DMA address boundary breaks                                */
65854   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK32 = 1,     /*!< BREAK32 : Break at 32 byte boundary (0x20 increments)                     */
65855   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK64 = 2,     /*!< BREAK64 : Break at 64 byte boundary (0x40 increments)                     */
65856   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK128 = 3,    /*!< BREAK128 : Break at 128 byte boundary (0x80 increments)                   */
65857   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK256 = 4,    /*!< BREAK256 : Break at 256 byte boundary (0x100 increments)                  */
65858   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK512 = 5,    /*!< BREAK512 : Break at 512 byte boundary (0x200 increments)                  */
65859   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK1K = 6,     /*!< BREAK1K : Break at 1KB boundary (0x400 increments)                        */
65860   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK2K = 7,     /*!< BREAK2K : Break at 2KB boundary (0x800 increments)                        */
65861   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK4K = 8,     /*!< BREAK4K : Break at 4KB boundary (0x1000 increments)                       */
65862   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK8K = 9,     /*!< BREAK8K : Break at 8KB boundary (0x2000 increments)                       */
65863   MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK16K = 10,   /*!< BREAK16K : Break at 16KB boundary (0x4000 increments)                     */
65864 } MSPI0_DEV0BOUNDARY_DMABOUND0_Enum;
65865 
65866 /* ====================================================  DEV0SCRAMBLING  ===================================================== */
65867 /* ======================================================  DEV0XIPMISC  ====================================================== */
65868 /* ==========================================  MSPI0 DEV0XIPMISC APNDODD0 [21..21]  ========================================== */
65869 typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_APNDODD0                                                */
65870   MSPI0_DEV0XIPMISC_APNDODD0_DIS       = 0,     /*!< DIS : No appending byte                                                   */
65871   MSPI0_DEV0XIPMISC_APNDODD0_EN        = 1,     /*!< EN : Append one dummy byte                                                */
65872 } MSPI0_DEV0XIPMISC_APNDODD0_Enum;
65873 
65874 /* ========================================  MSPI0 DEV0XIPMISC XIPBOUNDARY0 [15..15]  ======================================== */
65875 typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_XIPBOUNDARY0                                            */
65876   MSPI0_DEV0XIPMISC_XIPBOUNDARY0_DIS   = 0,     /*!< DIS : ERROR: desc VALUE MISSING                                           */
65877   MSPI0_DEV0XIPMISC_XIPBOUNDARY0_EN    = 1,     /*!< EN : ERROR: desc VALUE MISSING                                            */
65878 } MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Enum;
65879 
65880 /* ===========================================  MSPI0 DEV0XIPMISC BEON0 [14..14]  ============================================ */
65881 typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_BEON0                                                   */
65882   MSPI0_DEV0XIPMISC_BEON0_DIS          = 0,     /*!< DIS : Byte enable is calculated on the fly                                */
65883   MSPI0_DEV0XIPMISC_BEON0_EN           = 1,     /*!< EN : Byte enable of all bytes are always on                               */
65884 } MSPI0_DEV0XIPMISC_BEON0_Enum;
65885 
65886 /* ==========================================  MSPI0 DEV0XIPMISC XIPODD0 [12..12]  =========================================== */
65887 typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_XIPODD0                                                 */
65888   MSPI0_DEV0XIPMISC_XIPODD0_DIS        = 0,     /*!< DIS : No conversion                                                       */
65889   MSPI0_DEV0XIPMISC_XIPODD0_EN         = 1,     /*!< EN : Enable the conversion                                                */
65890 } MSPI0_DEV0XIPMISC_XIPODD0_Enum;
65891 
65892 /* ========================================================  DMACFG  ========================================================= */
65893 /* ==============================================  MSPI0 DMACFG DMAPRI [4..5]  =============================================== */
65894 typedef enum {                                  /*!< MSPI0_DMACFG_DMAPRI                                                       */
65895   MSPI0_DMACFG_DMAPRI_LOW              = 0,     /*!< LOW : Low Priority (service as best effort)                               */
65896   MSPI0_DMACFG_DMAPRI_HIGH             = 1,     /*!< HIGH : High Priority (service immediately)                                */
65897   MSPI0_DMACFG_DMAPRI_AUTO             = 2,     /*!< AUTO : Auto Priority (priority raised once TX FIFO empties or
65898                                                      RX FIFO fills)                                                            */
65899 } MSPI0_DMACFG_DMAPRI_Enum;
65900 
65901 /* ==============================================  MSPI0 DMACFG DMADEV [3..3]  =============================================== */
65902 typedef enum {                                  /*!< MSPI0_DMACFG_DMADEV                                                       */
65903   MSPI0_DMACFG_DMADEV_DEV0             = 0,     /*!< DEV0 : Select Device 0 for DMA                                            */
65904 } MSPI0_DMACFG_DMADEV_Enum;
65905 
65906 /* ==============================================  MSPI0 DMACFG DMADIR [2..2]  =============================================== */
65907 typedef enum {                                  /*!< MSPI0_DMACFG_DMADIR                                                       */
65908   MSPI0_DMACFG_DMADIR_P2M              = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
65909   MSPI0_DMACFG_DMADIR_M2P              = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
65910 } MSPI0_DMACFG_DMADIR_Enum;
65911 
65912 /* ===============================================  MSPI0 DMACFG DMAEN [0..1]  =============================================== */
65913 typedef enum {                                  /*!< MSPI0_DMACFG_DMAEN                                                        */
65914   MSPI0_DMACFG_DMAEN_DIS               = 0,     /*!< DIS : Disable DMA Function                                                */
65915   MSPI0_DMACFG_DMAEN_EN                = 3,     /*!< EN : Enable HW controlled DMA Function to manage DMA to flash
65916                                                      devices. HW will automatically handle issuance of instruction/address
65917                                                      bytes based on settings in the FLASH register.                            */
65918 } MSPI0_DMACFG_DMAEN_Enum;
65919 
65920 /* ========================================================  DMASTAT  ======================================================== */
65921 /* ======================================================  DMATARGADDR  ====================================================== */
65922 /* ======================================================  DMADEVADDR  ======================================================= */
65923 /* ======================================================  DMATOTCOUNT  ====================================================== */
65924 /* =======================================================  DMABCOUNT  ======================================================= */
65925 /* =======================================================  DMATHRESH  ======================================================= */
65926 /* =========================================================  INTEN  ========================================================= */
65927 /* ========================================================  INTSTAT  ======================================================== */
65928 /* ========================================================  INTCLR  ========================================================= */
65929 /* ========================================================  INTSET  ========================================================= */
65930 /* =========================================================  CQCFG  ========================================================= */
65931 /* ===============================================  MSPI0 CQCFG CQPRI [1..1]  ================================================ */
65932 typedef enum {                                  /*!< MSPI0_CQCFG_CQPRI                                                         */
65933   MSPI0_CQCFG_CQPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
65934   MSPI0_CQCFG_CQPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
65935 } MSPI0_CQCFG_CQPRI_Enum;
65936 
65937 /* ================================================  MSPI0 CQCFG CQEN [0..0]  ================================================ */
65938 typedef enum {                                  /*!< MSPI0_CQCFG_CQEN                                                          */
65939   MSPI0_CQCFG_CQEN_DIS                 = 0,     /*!< DIS : Disable CQ Function                                                 */
65940   MSPI0_CQCFG_CQEN_EN                  = 1,     /*!< EN : Enable CQ Function                                                   */
65941 } MSPI0_CQCFG_CQEN_Enum;
65942 
65943 /* ========================================================  CQADDR  ========================================================= */
65944 /* ========================================================  CQSTAT  ========================================================= */
65945 /* ========================================================  CQFLAGS  ======================================================== */
65946 /* =============================================  MSPI0 CQFLAGS CQFLAGS [0..15]  ============================================= */
65947 typedef enum {                                  /*!< MSPI0_CQFLAGS_CQFLAGS                                                     */
65948   MSPI0_CQFLAGS_CQFLAGS_STOP           = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
65949   MSPI0_CQFLAGS_CQFLAGS_CQIDX          = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
65950   MSPI0_CQFLAGS_CQFLAGS_BUF1XOREN      = 8192,  /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI).
65951                                                      This status is the result of XOR'ing the IOM1START with
65952                                                      the incoming status from the IOM. When high, MSPI can transfer
65953                                                      the buffer.                                                               */
65954   MSPI0_CQFLAGS_CQFLAGS_BUF0XOREN      = 4096,  /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI).
65955                                                      This status is the result of XOR'ing the IOM0START with
65956                                                      the incoming status from the IOM. When high, MSPI can transfer
65957                                                      the buffer.                                                               */
65958   MSPI0_CQFLAGS_CQFLAGS_DMACPL         = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
65959   MSPI0_CQFLAGS_CQFLAGS_CMDCPL         = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
65960   MSPI0_CQFLAGS_CQFLAGS_IOM1READY      = 512,   /*!< IOM1READY : (BUF1XNOREN) IOM Buffer 1 Ready Status (from selected
65961                                                      IOM). This status is the result of XNOR'ing the IOM0START
65962                                                      with the incoming status from the IOM. When high, MSPI
65963                                                      can send to the buffer.                                                   */
65964   MSPI0_CQFLAGS_CQFLAGS_IOM0READY      = 256,   /*!< IOM0READY : (BUF0XNOREN) IOM Buffer 0 Ready Status (from selected
65965                                                      IOM). This status is the result of XNOR'ing the IOM0START
65966                                                      with the incoming status from the IOM. When high, MSPI
65967                                                      can send to the buffer.                                                   */
65968   MSPI0_CQFLAGS_CQFLAGS_SWFLAG7        = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
65969                                                      operations.                                                               */
65970   MSPI0_CQFLAGS_CQFLAGS_SWFLAG6        = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
65971                                                      operations.                                                               */
65972   MSPI0_CQFLAGS_CQFLAGS_SWFLAG5        = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
65973                                                      operations.                                                               */
65974   MSPI0_CQFLAGS_CQFLAGS_SWFLAG4        = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
65975                                                      operations.                                                               */
65976   MSPI0_CQFLAGS_CQFLAGS_SWFLAG3        = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
65977                                                      operations.                                                               */
65978   MSPI0_CQFLAGS_CQFLAGS_SWFLAG2        = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
65979                                                      operations.                                                               */
65980   MSPI0_CQFLAGS_CQFLAGS_SWFLAG1        = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
65981                                                      operations. Also, IOM Buffer 1 status. When linked to IOM,
65982                                                      indicates to IOM that buffer 1 is ready.                                  */
65983   MSPI0_CQFLAGS_CQFLAGS_SWFLAG0        = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
65984                                                      operations. Also, IOM Buffer 0 status. When linked to IOM,
65985                                                      indicates to IOM that buffer 0 is ready.                                  */
65986 } MSPI0_CQFLAGS_CQFLAGS_Enum;
65987 
65988 /* ======================================================  CQSETCLEAR  ======================================================= */
65989 /* ========================================================  CQPAUSE  ======================================================== */
65990 /* =============================================  MSPI0 CQPAUSE CQMASK [0..15]  ============================================== */
65991 typedef enum {                                  /*!< MSPI0_CQPAUSE_CQMASK                                                      */
65992   MSPI0_CQPAUSE_CQMASK_STOP            = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
65993   MSPI0_CQPAUSE_CQMASK_CQIDX           = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
65994   MSPI0_CQPAUSE_CQMASK_BUF1XOREN       = 8192,  /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI).
65995                                                      This status is the result of XOR'ing the IOM1START with
65996                                                      the incoming status from the IOM. When high, MSPI can transfer
65997                                                      the buffer.                                                               */
65998   MSPI0_CQPAUSE_CQMASK_BUF0XOREN       = 4096,  /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI).
65999                                                      This status is the result of XOR'ing the IOM0START with
66000                                                      the incoming status from the IOM. When high, MSPI can transfer
66001                                                      the buffer.                                                               */
66002   MSPI0_CQPAUSE_CQMASK_DMACPL          = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
66003   MSPI0_CQPAUSE_CQMASK_CMDCPL          = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
66004   MSPI0_CQPAUSE_CQMASK_IOM1READY       = 512,   /*!< IOM1READY : (BUF1XNOREN) IOM Buffer 1 Ready Status (from selected
66005                                                      IOM). This status is the result of XNOR'ing the IOM0START
66006                                                      with the incoming status from the IOM. When high, MSPI
66007                                                      can send to the buffer.                                                   */
66008   MSPI0_CQPAUSE_CQMASK_IOM0READY       = 256,   /*!< IOM0READY : (BUF0XNOREN) IOM Buffer 0 Ready Status (from selected
66009                                                      IOM). This status is the result of XNOR'ing the IOM0START
66010                                                      with the incoming status from the IOM. When high, MSPI
66011                                                      can send to the buffer.                                                   */
66012   MSPI0_CQPAUSE_CQMASK_SWFLAG7         = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
66013                                                      operations.                                                               */
66014   MSPI0_CQPAUSE_CQMASK_SWFLAG6         = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
66015                                                      operations.                                                               */
66016   MSPI0_CQPAUSE_CQMASK_SWFLAG5         = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
66017                                                      operations.                                                               */
66018   MSPI0_CQPAUSE_CQMASK_SWFLAG4         = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
66019                                                      operations.                                                               */
66020   MSPI0_CQPAUSE_CQMASK_SWFLAG3         = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
66021                                                      operations.                                                               */
66022   MSPI0_CQPAUSE_CQMASK_SWFLAG2         = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
66023                                                      operations.                                                               */
66024   MSPI0_CQPAUSE_CQMASK_SWFLAG1         = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
66025                                                      operations. Also, IOM Buffer 1 status (same as SWFLAG1).
66026                                                      When linked to IOM, indicates to IOM that buffer 1 is ready.              */
66027   MSPI0_CQPAUSE_CQMASK_SWFLAG0         = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
66028                                                      operations. Also, IOM Buffer 0 status (same as SWFLAG0).
66029                                                      When linked to IOM, indicates to IOM that buffer 0 is ready.              */
66030 } MSPI0_CQPAUSE_CQMASK_Enum;
66031 
66032 /* =======================================================  CQCURIDX  ======================================================== */
66033 /* =======================================================  CQENDIDX  ======================================================== */
66034 /* ======================================================  STATXIPDMA  ======================================================= */
66035 /* ============================================  MSPI0 STATXIPDMA FLD32 [0..31]  ============================================= */
66036 typedef enum {                                  /*!< MSPI0_STATXIPDMA_FLD32                                                    */
66037   MSPI0_STATXIPDMA_FLD32_XIPDMAIDLE    = 2048,  /*!< XIPDMAIDLE : This bit indicates the idle status of XIPDMA.                */
66038 } MSPI0_STATXIPDMA_FLD32_Enum;
66039 
66040 
66041 
66042 /* =========================================================================================================================== */
66043 /* ================                                           PDM0                                            ================ */
66044 /* =========================================================================================================================== */
66045 
66046 /* =========================================================  CTRL  ========================================================== */
66047 /* ==================================================  PDM0 CTRL EN [6..6]  ================================================== */
66048 typedef enum {                                  /*!< PDM0_CTRL_EN                                                              */
66049   PDM0_CTRL_EN_DIS                     = 0,     /*!< DIS : Disable PDM.                                                        */
66050   PDM0_CTRL_EN_EN                      = 1,     /*!< EN : Enable PDM.                                                          */
66051 } PDM0_CTRL_EN_Enum;
66052 
66053 /* ===============================================  PDM0 CTRL PCMPACK [5..5]  ================================================ */
66054 typedef enum {                                  /*!< PDM0_CTRL_PCMPACK                                                         */
66055   PDM0_CTRL_PCMPACK_DIS                = 0,     /*!< DIS : Disable PCM packing.                                                */
66056   PDM0_CTRL_PCMPACK_EN                 = 1,     /*!< EN : Enable PCM packing.                                                  */
66057 } PDM0_CTRL_PCMPACK_Enum;
66058 
66059 /* =================================================  PDM0 CTRL RSTB [4..4]  ================================================= */
66060 typedef enum {                                  /*!< PDM0_CTRL_RSTB                                                            */
66061   PDM0_CTRL_RSTB_RESET                 = 0,     /*!< RESET : Put the core in reset.                                            */
66062   PDM0_CTRL_RSTB_NORMAL                = 1,     /*!< NORMAL : Core not in reset.                                               */
66063 } PDM0_CTRL_RSTB_Enum;
66064 
66065 /* ================================================  PDM0 CTRL CLKEN [0..0]  ================================================= */
66066 typedef enum {                                  /*!< PDM0_CTRL_CLKEN                                                           */
66067   PDM0_CTRL_CLKEN_DIS                  = 0,     /*!< DIS : Disable serial clock                                                */
66068   PDM0_CTRL_CLKEN_EN                   = 1,     /*!< EN : Enable serial clock                                                  */
66069 } PDM0_CTRL_CLKEN_Enum;
66070 
66071 /* =======================================================  CORECFG0  ======================================================== */
66072 /* ==============================================  PDM0 CORECFG0 PGAR [26..30]  ============================================== */
66073 typedef enum {                                  /*!< PDM0_CORECFG0_PGAR                                                        */
66074   PDM0_CORECFG0_PGAR_M12_0DB           = 0,     /*!< M12_0DB : Right channel PGA gain = -12.0 dB                               */
66075   PDM0_CORECFG0_PGAR_M10_5DB           = 1,     /*!< M10_5DB : Right channel PGA gain = -10.5 dB                               */
66076   PDM0_CORECFG0_PGAR_M9_0DB            = 2,     /*!< M9_0DB : Right channel PGA gain = -9.0 dB                                 */
66077   PDM0_CORECFG0_PGAR_M7_5DB            = 3,     /*!< M7_5DB : Right channel PGA gain = -7.5 dB                                 */
66078   PDM0_CORECFG0_PGAR_M6_0DB            = 4,     /*!< M6_0DB : Right channel PGA gain = -6.0 dB                                 */
66079   PDM0_CORECFG0_PGAR_M4_5DB            = 5,     /*!< M4_5DB : Right channel PGA gain = -4.5 dB                                 */
66080   PDM0_CORECFG0_PGAR_M3_0DB            = 6,     /*!< M3_0DB : Right channel PGA gain = -3.0 dB                                 */
66081   PDM0_CORECFG0_PGAR_M1_5DB            = 7,     /*!< M1_5DB : Right channel PGA gain = -1.5 dB                                 */
66082   PDM0_CORECFG0_PGAR_0DB               = 8,     /*!< 0DB : Right channel PGA gain = 0 DB                                       */
66083   PDM0_CORECFG0_PGAR_P1_5DB            = 9,     /*!< P1_5DB : Right channel PGA gain = 1.5 dB                                  */
66084   PDM0_CORECFG0_PGAR_P3_0DB            = 10,    /*!< P3_0DB : Right channel PGA gain = 3.0 dB                                  */
66085   PDM0_CORECFG0_PGAR_P4_5DB            = 11,    /*!< P4_5DB : Right channel PGA gain = 4.5 dB                                  */
66086   PDM0_CORECFG0_PGAR_P6_0DB            = 12,    /*!< P6_0DB : Right channel PGA gain = 6.0 DB                                  */
66087   PDM0_CORECFG0_PGAR_P7_5DB            = 13,    /*!< P7_5DB : Right channel PGA gain = 7.5 dB                                  */
66088   PDM0_CORECFG0_PGAR_P9_0DB            = 14,    /*!< P9_0DB : Right channel PGA gain = 9.0 dB                                  */
66089   PDM0_CORECFG0_PGAR_P10_5DB           = 15,    /*!< P10_5DB : Right channel PGA gain = 10.5 dB                                */
66090   PDM0_CORECFG0_PGAR_P12_0DB           = 16,    /*!< P12_0DB : Right channel PGA gain = 12.0 DB                                */
66091   PDM0_CORECFG0_PGAR_P13_5DB           = 17,    /*!< P13_5DB : Right channel PGA gain = 13.5 dB                                */
66092   PDM0_CORECFG0_PGAR_P15_0DB           = 18,    /*!< P15_0DB : Right channel PGA gain = 15.0 dB                                */
66093   PDM0_CORECFG0_PGAR_P16_5DB           = 19,    /*!< P16_5DB : Right channel PGA gain = 16.5 dB                                */
66094   PDM0_CORECFG0_PGAR_P18_0DB           = 20,    /*!< P18_0DB : Right channel PGA gain = 18.0 DB                                */
66095   PDM0_CORECFG0_PGAR_P19_5DB           = 21,    /*!< P19_5DB : Right channel PGA gain = 19.5 dB                                */
66096   PDM0_CORECFG0_PGAR_P21_0DB           = 22,    /*!< P21_0DB : Right channel PGA gain = 21.0 dB                                */
66097   PDM0_CORECFG0_PGAR_P22_5DB           = 23,    /*!< P22_5DB : Right channel PGA gain = 22.5 dB                                */
66098   PDM0_CORECFG0_PGAR_P24_0DB           = 24,    /*!< P24_0DB : Right channel PGA gain = 24.0 DB                                */
66099   PDM0_CORECFG0_PGAR_P25_5DB           = 25,    /*!< P25_5DB : Right channel PGA gain = 25.5 dB                                */
66100   PDM0_CORECFG0_PGAR_P27_0DB           = 26,    /*!< P27_0DB : Right channel PGA gain = 27.0 dB                                */
66101   PDM0_CORECFG0_PGAR_P28_5DB           = 27,    /*!< P28_5DB : Right channel PGA gain = 28.5 dB                                */
66102   PDM0_CORECFG0_PGAR_P30_0DB           = 28,    /*!< P30_0DB : Right channel PGA gain = 30.0 DB                                */
66103   PDM0_CORECFG0_PGAR_P31_5DB           = 29,    /*!< P31_5DB : Right channel PGA gain = 31.5 dB                                */
66104   PDM0_CORECFG0_PGAR_P33_0DB           = 30,    /*!< P33_0DB : Right channel PGA gain = 33.0 dB                                */
66105   PDM0_CORECFG0_PGAR_P34_5DB           = 31,    /*!< P34_5DB : Right channel PGA gain = 34.5 dB                                */
66106 } PDM0_CORECFG0_PGAR_Enum;
66107 
66108 /* ==============================================  PDM0 CORECFG0 PGAL [21..25]  ============================================== */
66109 typedef enum {                                  /*!< PDM0_CORECFG0_PGAL                                                        */
66110   PDM0_CORECFG0_PGAL_M10_5DB           = 1,     /*!< M10_5DB : Left channel PGA gain = -10.5 dB                                */
66111   PDM0_CORECFG0_PGAL_M9_0DB            = 2,     /*!< M9_0DB : Left channel PGA gain = -9.0 dB                                  */
66112   PDM0_CORECFG0_PGAL_M7_5DB            = 3,     /*!< M7_5DB : Left channel PGA gain = -7.5 dB                                  */
66113   PDM0_CORECFG0_PGAL_M6_0DB            = 4,     /*!< M6_0DB : Left channel PGA gain = -6.0 dB                                  */
66114   PDM0_CORECFG0_PGAL_M4_5DB            = 5,     /*!< M4_5DB : Left channel PGA gain = -4.5 dB                                  */
66115   PDM0_CORECFG0_PGAL_M3_0DB            = 6,     /*!< M3_0DB : Left channel PGA gain = -3.0 dB                                  */
66116   PDM0_CORECFG0_PGAL_M1_5DB            = 7,     /*!< M1_5DB : Left channel PGA gain = -1.5 dB                                  */
66117   PDM0_CORECFG0_PGAL_0DB               = 8,     /*!< 0DB : Left channel PGA gain = 0 DB                                        */
66118   PDM0_CORECFG0_PGAL_P1_5DB            = 9,     /*!< P1_5DB : Left channel PGA gain = 1.5 dB                                   */
66119   PDM0_CORECFG0_PGAL_P3_0DB            = 10,    /*!< P3_0DB : Left channel PGA gain = 3.0 dB                                   */
66120   PDM0_CORECFG0_PGAL_P4_5DB            = 11,    /*!< P4_5DB : Left channel PGA gain = 4.5 dB                                   */
66121   PDM0_CORECFG0_PGAL_P6_0DB            = 12,    /*!< P6_0DB : Left channel PGA gain = 6.0 DB                                   */
66122   PDM0_CORECFG0_PGAL_P7_5DB            = 13,    /*!< P7_5DB : Left channel PGA gain = 7.5 dB                                   */
66123   PDM0_CORECFG0_PGAL_P9_0DB            = 14,    /*!< P9_0DB : Left channel PGA gain = 9.0 dB                                   */
66124   PDM0_CORECFG0_PGAL_P10_5DB           = 15,    /*!< P10_5DB : Left channel PGA gain = 10.5 dB                                 */
66125   PDM0_CORECFG0_PGAL_P12_0DB           = 16,    /*!< P12_0DB : Left channel PGA gain = 12.0 DB                                 */
66126   PDM0_CORECFG0_PGAL_P13_5DB           = 17,    /*!< P13_5DB : Left channel PGA gain = 13.5 dB                                 */
66127   PDM0_CORECFG0_PGAL_P15_0DB           = 18,    /*!< P15_0DB : Left channel PGA gain = 15.0 dB                                 */
66128   PDM0_CORECFG0_PGAL_P16_5DB           = 19,    /*!< P16_5DB : Left channel PGA gain = 16.5 dB                                 */
66129   PDM0_CORECFG0_PGAL_P18_0DB           = 20,    /*!< P18_0DB : Left channel PGA gain = 18.0 DB                                 */
66130   PDM0_CORECFG0_PGAL_P19_5DB           = 21,    /*!< P19_5DB : Left channel PGA gain = 19.5 dB                                 */
66131   PDM0_CORECFG0_PGAL_P21_0DB           = 22,    /*!< P21_0DB : Left channel PGA gain = 21.0 dB                                 */
66132   PDM0_CORECFG0_PGAL_P22_5DB           = 23,    /*!< P22_5DB : Left channel PGA gain = 22.5 dB                                 */
66133   PDM0_CORECFG0_PGAL_P24_0DB           = 24,    /*!< P24_0DB : Left channel PGA gain = 24.0 DB                                 */
66134   PDM0_CORECFG0_PGAL_P25_5DB           = 25,    /*!< P25_5DB : Left channel PGA gain = 25.5 dB                                 */
66135   PDM0_CORECFG0_PGAL_P27_0DB           = 26,    /*!< P27_0DB : Left channel PGA gain = 27.0 dB                                 */
66136   PDM0_CORECFG0_PGAL_P28_5DB           = 27,    /*!< P28_5DB : Left channel PGA gain = 28.5 dB                                 */
66137   PDM0_CORECFG0_PGAL_P30_0DB           = 28,    /*!< P30_0DB : Left channel PGA gain = 30.0 DB                                 */
66138   PDM0_CORECFG0_PGAL_P31_5DB           = 29,    /*!< P31_5DB : Left channel PGA gain = 31.5 dB                                 */
66139   PDM0_CORECFG0_PGAL_P33_0DB           = 30,    /*!< P33_0DB : Left channel PGA gain = 33.0 dB                                 */
66140   PDM0_CORECFG0_PGAL_P34_5DB           = 31,    /*!< P34_5DB : Left channel PGA gain = 34.5 dB                                 */
66141 } PDM0_CORECFG0_PGAL_Enum;
66142 
66143 /* ==============================================  PDM0 CORECFG0 ADCHPD [9..9]  ============================================== */
66144 typedef enum {                                  /*!< PDM0_CORECFG0_ADCHPD                                                      */
66145   PDM0_CORECFG0_ADCHPD_DIS             = 0,     /*!< DIS : Disable high pass filter.                                           */
66146   PDM0_CORECFG0_ADCHPD_EN              = 1,     /*!< EN : Enable high pass filter.                                             */
66147 } PDM0_CORECFG0_ADCHPD_Enum;
66148 
66149 /* =============================================  PDM0 CORECFG0 SCYCLES [2..4]  ============================================== */
66150 typedef enum {                                  /*!< PDM0_CORECFG0_SCYCLES                                                     */
66151   PDM0_CORECFG0_SCYCLES_0CYCLES        = 0,     /*!< 0CYCLES : Zero PDMA_CK0 clock cycles during gain setting changes
66152                                                      or soft mute.                                                             */
66153   PDM0_CORECFG0_SCYCLES_1CYCLES        = 1,     /*!< 1CYCLES : One PDMA_CK0 clock cycle during gain setting changes
66154                                                      or soft mute.                                                             */
66155   PDM0_CORECFG0_SCYCLES_2CYCLES        = 2,     /*!< 2CYCLES : Two PDMA_CK0 clock cycles during gain setting changes
66156                                                      or soft mute.                                                             */
66157   PDM0_CORECFG0_SCYCLES_3CYCLES        = 3,     /*!< 3CYCLES : Three PDMA_CK0 clock cycles during gain setting changes
66158                                                      or soft mute.                                                             */
66159   PDM0_CORECFG0_SCYCLES_4CYCLES        = 4,     /*!< 4CYCLES : Four PDMA_CK0 clock cycles during gain setting changes
66160                                                      or soft mute.                                                             */
66161   PDM0_CORECFG0_SCYCLES_5CYCLES        = 5,     /*!< 5CYCLES : Five PDMA_CK0 clock cycles during gain setting changes
66162                                                      or soft mute.                                                             */
66163   PDM0_CORECFG0_SCYCLES_6CYCLES        = 6,     /*!< 6CYCLES : Six PDMA_CK0 clock cycles during gain setting changes
66164                                                      or soft mute.                                                             */
66165   PDM0_CORECFG0_SCYCLES_7CYCLES        = 7,     /*!< 7CYCLES : Seven PDMA_CK0 clock cycles during gain setting changes
66166                                                      or soft mute.                                                             */
66167 } PDM0_CORECFG0_SCYCLES_Enum;
66168 
66169 /* ==============================================  PDM0 CORECFG0 LRSWAP [0..0]  ============================================== */
66170 typedef enum {                                  /*!< PDM0_CORECFG0_LRSWAP                                                      */
66171   PDM0_CORECFG0_LRSWAP_DIS             = 0,     /*!< DIS : Disable left/right channel swapping.                                */
66172   PDM0_CORECFG0_LRSWAP_EN              = 1,     /*!< EN : Enable left/right channel swapping.                                  */
66173 } PDM0_CORECFG0_LRSWAP_Enum;
66174 
66175 /* =======================================================  CORECFG1  ======================================================== */
66176 /* =============================================  PDM0 CORECFG1 SELSTEP [7..7]  ============================================== */
66177 typedef enum {                                  /*!< PDM0_CORECFG1_SELSTEP                                                     */
66178   PDM0_CORECFG1_SELSTEP_0_13DB         = 0,     /*!< 0_13DB : 0.13dB fine grain step size.                                     */
66179   PDM0_CORECFG1_SELSTEP_0_26DB         = 1,     /*!< 0_26DB : 0.26dB fine grain step size.                                     */
66180 } PDM0_CORECFG1_SELSTEP_Enum;
66181 
66182 /* ==============================================  PDM0 CORECFG1 CKODLY [4..6]  ============================================== */
66183 typedef enum {                                  /*!< PDM0_CORECFG1_CKODLY                                                      */
66184   PDM0_CORECFG1_CKODLY_0CYCLES         = 0,     /*!< 0CYCLES : No extra PDMCLK cycle delays.                                   */
66185   PDM0_CORECFG1_CKODLY_1CYCLES         = 1,     /*!< 1CYCLES : One xtra PDMCLK cycle delay.                                    */
66186   PDM0_CORECFG1_CKODLY_2CYCLES         = 2,     /*!< 2CYCLES : Two extra PDMCLK cycle delays.                                  */
66187   PDM0_CORECFG1_CKODLY_3CYCLES         = 3,     /*!< 3CYCLES : Three extra PDMCLK cycle delays.                                */
66188   PDM0_CORECFG1_CKODLY_4CYCLES         = 4,     /*!< 4CYCLES : Four extra PDMCLK cycle delays.                                 */
66189   PDM0_CORECFG1_CKODLY_5CYCLES         = 5,     /*!< 5CYCLES : Five extra PDMCLK cycle delays.                                 */
66190   PDM0_CORECFG1_CKODLY_6CYCLES         = 6,     /*!< 6CYCLES : Six extra PDMCLK cycle delays.                                  */
66191   PDM0_CORECFG1_CKODLY_7CYCLES         = 7,     /*!< 7CYCLES : Seven extra PDMCLK cycle delays.                                */
66192 } PDM0_CORECFG1_CKODLY_Enum;
66193 
66194 /* =============================================  PDM0 CORECFG1 PCMCHSET [0..1]  ============================================= */
66195 typedef enum {                                  /*!< PDM0_CORECFG1_PCMCHSET                                                    */
66196   PDM0_CORECFG1_PCMCHSET_CHANDIS       = 0,     /*!< CHANDIS : Channel Disabled                                                */
66197   PDM0_CORECFG1_PCMCHSET_MONOL         = 1,     /*!< MONOL : MONO Left                                                         */
66198   PDM0_CORECFG1_PCMCHSET_MONOR         = 2,     /*!< MONOR : MONO right                                                        */
66199   PDM0_CORECFG1_PCMCHSET_STEREO        = 3,     /*!< STEREO : Stereo                                                           */
66200 } PDM0_CORECFG1_PCMCHSET_Enum;
66201 
66202 /* =======================================================  CORECTRL  ======================================================== */
66203 /* ========================================================  FIFOCNT  ======================================================== */
66204 /* =======================================================  FIFOREAD  ======================================================== */
66205 /* =======================================================  FIFOFLUSH  ======================================================= */
66206 /* ========================================================  FIFOTHR  ======================================================== */
66207 /* =========================================================  INTEN  ========================================================= */
66208 /* ========================================================  INTSTAT  ======================================================== */
66209 /* ========================================================  INTCLR  ========================================================= */
66210 /* ========================================================  INTSET  ========================================================= */
66211 /* =======================================================  DMATRIGEN  ======================================================= */
66212 /* ======================================================  DMATRIGSTAT  ====================================================== */
66213 /* ========================================================  DMACFG  ========================================================= */
66214 /* ===============================================  PDM0 DMACFG DMAPRI [8..8]  =============================================== */
66215 typedef enum {                                  /*!< PDM0_DMACFG_DMAPRI                                                        */
66216   PDM0_DMACFG_DMAPRI_LOW               = 0,     /*!< LOW : Low Priority (service as best effort)                               */
66217   PDM0_DMACFG_DMAPRI_HIGH              = 1,     /*!< HIGH : High Priority (service immediately)                                */
66218 } PDM0_DMACFG_DMAPRI_Enum;
66219 
66220 /* ===============================================  PDM0 DMACFG DMADIR [2..2]  =============================================== */
66221 typedef enum {                                  /*!< PDM0_DMACFG_DMADIR                                                        */
66222   PDM0_DMACFG_DMADIR_P2M               = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. THe PDM module
66223                                                      will only DMA to memory.                                                  */
66224   PDM0_DMACFG_DMADIR_M2P               = 1,     /*!< M2P : Memory to Peripheral transaction. Not available for PDM
66225                                                      module                                                                    */
66226 } PDM0_DMACFG_DMADIR_Enum;
66227 
66228 /* ===============================================  PDM0 DMACFG DMAEN [0..0]  ================================================ */
66229 typedef enum {                                  /*!< PDM0_DMACFG_DMAEN                                                         */
66230   PDM0_DMACFG_DMAEN_DIS                = 0,     /*!< DIS : Disable DMA Function                                                */
66231   PDM0_DMACFG_DMAEN_EN                 = 1,     /*!< EN : Enable DMA Function                                                  */
66232 } PDM0_DMACFG_DMAEN_Enum;
66233 
66234 /* ======================================================  DMATARGADDR  ====================================================== */
66235 /* ========================================================  DMASTAT  ======================================================== */
66236 /* ======================================================  DMATOTCOUNT  ====================================================== */
66237 
66238 
66239 /* =========================================================================================================================== */
66240 /* ================                                          PWRCTRL                                          ================ */
66241 /* =========================================================================================================================== */
66242 
66243 /* ======================================================  MCUPERFREQ  ======================================================= */
66244 /* ========================================  PWRCTRL MCUPERFREQ MCUPERFSTATUS [3..4]  ======================================== */
66245 typedef enum {                                  /*!< PWRCTRL_MCUPERFREQ_MCUPERFSTATUS                                          */
66246   PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_ULP = 0,     /*!< ULP : MCU is in ULP mode (freq=24MHz)                                     */
66247   PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_LP  = 1,     /*!< LP : MCU is in LP mode (freq=96MHz)                                       */
66248   PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_HP  = 2,     /*!< HP : MCU is in HP mode (freq=192MHz)                                      */
66249 } PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Enum;
66250 
66251 /* =========================================  PWRCTRL MCUPERFREQ MCUPERFREQ [0..1]  ========================================== */
66252 typedef enum {                                  /*!< PWRCTRL_MCUPERFREQ_MCUPERFREQ                                             */
66253   PWRCTRL_MCUPERFREQ_MCUPERFREQ_ULP    = 0,     /*!< ULP : MCU to be run in ULP mode (freq=24MHz)                              */
66254   PWRCTRL_MCUPERFREQ_MCUPERFREQ_LP     = 1,     /*!< LP : MCU to be run in LP mode (freq=96MHz)                                */
66255   PWRCTRL_MCUPERFREQ_MCUPERFREQ_HP     = 2,     /*!< HP : MCU to be run in HP mode (freq=192MHz)                               */
66256 } PWRCTRL_MCUPERFREQ_MCUPERFREQ_Enum;
66257 
66258 /* =======================================================  DEVPWREN  ======================================================== */
66259 /* ==========================================  PWRCTRL DEVPWREN PWRENI3C1 [26..26]  ========================================== */
66260 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENI3C1                                                */
66261   PWRCTRL_DEVPWREN_PWRENI3C1_EN        = 1,     /*!< EN : Enable                                                               */
66262   PWRCTRL_DEVPWREN_PWRENI3C1_DIS       = 0,     /*!< DIS : Disable                                                             */
66263 } PWRCTRL_DEVPWREN_PWRENI3C1_Enum;
66264 
66265 /* ==========================================  PWRCTRL DEVPWREN PWRENI3C0 [25..25]  ========================================== */
66266 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENI3C0                                                */
66267   PWRCTRL_DEVPWREN_PWRENI3C0_EN        = 1,     /*!< EN : Enable                                                               */
66268   PWRCTRL_DEVPWREN_PWRENI3C0_DIS       = 0,     /*!< DIS : Disable                                                             */
66269 } PWRCTRL_DEVPWREN_PWRENI3C0_Enum;
66270 
66271 /* ==========================================  PWRCTRL DEVPWREN PWRENDBG [24..24]  =========================================== */
66272 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENDBG                                                 */
66273   PWRCTRL_DEVPWREN_PWRENDBG_EN         = 1,     /*!< EN : Enable                                                               */
66274   PWRCTRL_DEVPWREN_PWRENDBG_DIS        = 0,     /*!< DIS : Disable                                                             */
66275 } PWRCTRL_DEVPWREN_PWRENDBG_Enum;
66276 
66277 /* =========================================  PWRCTRL DEVPWREN PWRENUSBPHY [23..23]  ========================================= */
66278 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUSBPHY                                              */
66279   PWRCTRL_DEVPWREN_PWRENUSBPHY_EN      = 1,     /*!< EN : Power up USB PHY                                                     */
66280   PWRCTRL_DEVPWREN_PWRENUSBPHY_DIS     = 0,     /*!< DIS : Power down USB PHY                                                  */
66281 } PWRCTRL_DEVPWREN_PWRENUSBPHY_Enum;
66282 
66283 /* ==========================================  PWRCTRL DEVPWREN PWRENUSB [22..22]  =========================================== */
66284 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUSB                                                 */
66285   PWRCTRL_DEVPWREN_PWRENUSB_EN         = 1,     /*!< EN : Power up USB                                                         */
66286   PWRCTRL_DEVPWREN_PWRENUSB_DIS        = 0,     /*!< DIS : Power down USB                                                      */
66287 } PWRCTRL_DEVPWREN_PWRENUSB_Enum;
66288 
66289 /* ==========================================  PWRCTRL DEVPWREN PWRENSDIO [21..21]  ========================================== */
66290 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENSDIO                                                */
66291   PWRCTRL_DEVPWREN_PWRENSDIO_EN        = 1,     /*!< EN : Power up SDIO                                                        */
66292   PWRCTRL_DEVPWREN_PWRENSDIO_DIS       = 0,     /*!< DIS : Power down SDIO                                                     */
66293 } PWRCTRL_DEVPWREN_PWRENSDIO_Enum;
66294 
66295 /* =========================================  PWRCTRL DEVPWREN PWRENCRYPTO [20..20]  ========================================= */
66296 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENCRYPTO                                              */
66297   PWRCTRL_DEVPWREN_PWRENCRYPTO_EN      = 1,     /*!< EN : Power up CRYPTO                                                      */
66298   PWRCTRL_DEVPWREN_PWRENCRYPTO_DIS     = 0,     /*!< DIS : Power down CRYPTO                                                   */
66299 } PWRCTRL_DEVPWREN_PWRENCRYPTO_Enum;
66300 
66301 /* ========================================  PWRCTRL DEVPWREN PWRENDISPPHY [19..19]  ========================================= */
66302 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENDISPPHY                                             */
66303   PWRCTRL_DEVPWREN_PWRENDISPPHY_EN     = 1,     /*!< EN : Power up DISP PHY                                                    */
66304   PWRCTRL_DEVPWREN_PWRENDISPPHY_DIS    = 0,     /*!< DIS : Power down DISP PHY                                                 */
66305 } PWRCTRL_DEVPWREN_PWRENDISPPHY_Enum;
66306 
66307 /* ==========================================  PWRCTRL DEVPWREN PWRENDISP [18..18]  ========================================== */
66308 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENDISP                                                */
66309   PWRCTRL_DEVPWREN_PWRENDISP_EN        = 1,     /*!< EN : Power up DISP                                                        */
66310   PWRCTRL_DEVPWREN_PWRENDISP_DIS       = 0,     /*!< DIS : Power down DISP                                                     */
66311 } PWRCTRL_DEVPWREN_PWRENDISP_Enum;
66312 
66313 /* ==========================================  PWRCTRL DEVPWREN PWRENGFX [17..17]  =========================================== */
66314 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENGFX                                                 */
66315   PWRCTRL_DEVPWREN_PWRENGFX_EN         = 1,     /*!< EN : Power up GFX                                                         */
66316   PWRCTRL_DEVPWREN_PWRENGFX_DIS        = 0,     /*!< DIS : Power down GFX                                                      */
66317 } PWRCTRL_DEVPWREN_PWRENGFX_Enum;
66318 
66319 /* =========================================  PWRCTRL DEVPWREN PWRENMSPI2 [16..16]  ========================================== */
66320 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENMSPI2                                               */
66321   PWRCTRL_DEVPWREN_PWRENMSPI2_EN       = 1,     /*!< EN : Power up MSPI2                                                       */
66322   PWRCTRL_DEVPWREN_PWRENMSPI2_DIS      = 0,     /*!< DIS : Power down MSPI2                                                    */
66323 } PWRCTRL_DEVPWREN_PWRENMSPI2_Enum;
66324 
66325 /* =========================================  PWRCTRL DEVPWREN PWRENMSPI1 [15..15]  ========================================== */
66326 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENMSPI1                                               */
66327   PWRCTRL_DEVPWREN_PWRENMSPI1_EN       = 1,     /*!< EN : Power up MSPI1                                                       */
66328   PWRCTRL_DEVPWREN_PWRENMSPI1_DIS      = 0,     /*!< DIS : Power down MSPI1                                                    */
66329 } PWRCTRL_DEVPWREN_PWRENMSPI1_Enum;
66330 
66331 /* =========================================  PWRCTRL DEVPWREN PWRENMSPI0 [14..14]  ========================================== */
66332 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENMSPI0                                               */
66333   PWRCTRL_DEVPWREN_PWRENMSPI0_EN       = 1,     /*!< EN : Power up MSPI0                                                       */
66334   PWRCTRL_DEVPWREN_PWRENMSPI0_DIS      = 0,     /*!< DIS : Power down MSPI0                                                    */
66335 } PWRCTRL_DEVPWREN_PWRENMSPI0_Enum;
66336 
66337 /* ==========================================  PWRCTRL DEVPWREN PWRENADC [13..13]  =========================================== */
66338 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENADC                                                 */
66339   PWRCTRL_DEVPWREN_PWRENADC_EN         = 1,     /*!< EN : Power up ADC                                                         */
66340   PWRCTRL_DEVPWREN_PWRENADC_DIS        = 0,     /*!< DIS : Power Down ADC                                                      */
66341 } PWRCTRL_DEVPWREN_PWRENADC_Enum;
66342 
66343 /* =========================================  PWRCTRL DEVPWREN PWRENUART3 [12..12]  ========================================== */
66344 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART3                                               */
66345   PWRCTRL_DEVPWREN_PWRENUART3_EN       = 1,     /*!< EN : Power up UART 3                                                      */
66346   PWRCTRL_DEVPWREN_PWRENUART3_DIS      = 0,     /*!< DIS : Power down UART 3                                                   */
66347 } PWRCTRL_DEVPWREN_PWRENUART3_Enum;
66348 
66349 /* =========================================  PWRCTRL DEVPWREN PWRENUART2 [11..11]  ========================================== */
66350 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART2                                               */
66351   PWRCTRL_DEVPWREN_PWRENUART2_EN       = 1,     /*!< EN : Power up UART 2                                                      */
66352   PWRCTRL_DEVPWREN_PWRENUART2_DIS      = 0,     /*!< DIS : Power down UART 2                                                   */
66353 } PWRCTRL_DEVPWREN_PWRENUART2_Enum;
66354 
66355 /* =========================================  PWRCTRL DEVPWREN PWRENUART1 [10..10]  ========================================== */
66356 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART1                                               */
66357   PWRCTRL_DEVPWREN_PWRENUART1_EN       = 1,     /*!< EN : Power up UART 1                                                      */
66358   PWRCTRL_DEVPWREN_PWRENUART1_DIS      = 0,     /*!< DIS : Power down UART 1                                                   */
66359 } PWRCTRL_DEVPWREN_PWRENUART1_Enum;
66360 
66361 /* ==========================================  PWRCTRL DEVPWREN PWRENUART0 [9..9]  =========================================== */
66362 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART0                                               */
66363   PWRCTRL_DEVPWREN_PWRENUART0_EN       = 1,     /*!< EN : Power up UART 0                                                      */
66364   PWRCTRL_DEVPWREN_PWRENUART0_DIS      = 0,     /*!< DIS : Power down UART 0                                                   */
66365 } PWRCTRL_DEVPWREN_PWRENUART0_Enum;
66366 
66367 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM7 [8..8]  =========================================== */
66368 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM7                                                */
66369   PWRCTRL_DEVPWREN_PWRENIOM7_EN        = 1,     /*!< EN : Power up IO Master 7                                                 */
66370   PWRCTRL_DEVPWREN_PWRENIOM7_DIS       = 0,     /*!< DIS : Power down IO Master 7                                              */
66371 } PWRCTRL_DEVPWREN_PWRENIOM7_Enum;
66372 
66373 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM6 [7..7]  =========================================== */
66374 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM6                                                */
66375   PWRCTRL_DEVPWREN_PWRENIOM6_EN        = 1,     /*!< EN : Power up IO Master 6                                                 */
66376   PWRCTRL_DEVPWREN_PWRENIOM6_DIS       = 0,     /*!< DIS : Power down IO Master 6                                              */
66377 } PWRCTRL_DEVPWREN_PWRENIOM6_Enum;
66378 
66379 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM5 [6..6]  =========================================== */
66380 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM5                                                */
66381   PWRCTRL_DEVPWREN_PWRENIOM5_EN        = 1,     /*!< EN : Power up IO Master 5                                                 */
66382   PWRCTRL_DEVPWREN_PWRENIOM5_DIS       = 0,     /*!< DIS : Power down IO Master 5                                              */
66383 } PWRCTRL_DEVPWREN_PWRENIOM5_Enum;
66384 
66385 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM4 [5..5]  =========================================== */
66386 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM4                                                */
66387   PWRCTRL_DEVPWREN_PWRENIOM4_EN        = 1,     /*!< EN : Power up IO Master 4                                                 */
66388   PWRCTRL_DEVPWREN_PWRENIOM4_DIS       = 0,     /*!< DIS : Power down IO Master 4                                              */
66389 } PWRCTRL_DEVPWREN_PWRENIOM4_Enum;
66390 
66391 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM3 [4..4]  =========================================== */
66392 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM3                                                */
66393   PWRCTRL_DEVPWREN_PWRENIOM3_EN        = 1,     /*!< EN : Power up IO Master 3                                                 */
66394   PWRCTRL_DEVPWREN_PWRENIOM3_DIS       = 0,     /*!< DIS : Power down IO Master 3                                              */
66395 } PWRCTRL_DEVPWREN_PWRENIOM3_Enum;
66396 
66397 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM2 [3..3]  =========================================== */
66398 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM2                                                */
66399   PWRCTRL_DEVPWREN_PWRENIOM2_EN        = 1,     /*!< EN : Power up IO Master 2                                                 */
66400   PWRCTRL_DEVPWREN_PWRENIOM2_DIS       = 0,     /*!< DIS : Power down IO Master 2                                              */
66401 } PWRCTRL_DEVPWREN_PWRENIOM2_Enum;
66402 
66403 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM1 [2..2]  =========================================== */
66404 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM1                                                */
66405   PWRCTRL_DEVPWREN_PWRENIOM1_EN        = 1,     /*!< EN : Power up IO Master 1                                                 */
66406   PWRCTRL_DEVPWREN_PWRENIOM1_DIS       = 0,     /*!< DIS : Power down IO Master 1                                              */
66407 } PWRCTRL_DEVPWREN_PWRENIOM1_Enum;
66408 
66409 /* ===========================================  PWRCTRL DEVPWREN PWRENIOM0 [1..1]  =========================================== */
66410 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM0                                                */
66411   PWRCTRL_DEVPWREN_PWRENIOM0_EN        = 1,     /*!< EN : Power up IO Master 0                                                 */
66412   PWRCTRL_DEVPWREN_PWRENIOM0_DIS       = 0,     /*!< DIS : Power down IO Master 0                                              */
66413 } PWRCTRL_DEVPWREN_PWRENIOM0_Enum;
66414 
66415 /* ===========================================  PWRCTRL DEVPWREN PWRENIOS [0..0]  ============================================ */
66416 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOS                                                 */
66417   PWRCTRL_DEVPWREN_PWRENIOS_EN         = 1,     /*!< EN : Power up IO slave                                                    */
66418   PWRCTRL_DEVPWREN_PWRENIOS_DIS        = 0,     /*!< DIS : Power down IO slave                                                 */
66419 } PWRCTRL_DEVPWREN_PWRENIOS_Enum;
66420 
66421 /* =====================================================  DEVPWRSTATUS  ====================================================== */
66422 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTI3C1 [26..26]  ======================================== */
66423 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTI3C1                                            */
66424   PWRCTRL_DEVPWRSTATUS_PWRSTI3C1_ON    = 1,     /*!< ON : Domain powered on                                                    */
66425   PWRCTRL_DEVPWRSTATUS_PWRSTI3C1_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66426 } PWRCTRL_DEVPWRSTATUS_PWRSTI3C1_Enum;
66427 
66428 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTI3C0 [25..25]  ======================================== */
66429 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTI3C0                                            */
66430   PWRCTRL_DEVPWRSTATUS_PWRSTI3C0_ON    = 1,     /*!< ON : Domain powered on                                                    */
66431   PWRCTRL_DEVPWRSTATUS_PWRSTI3C0_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66432 } PWRCTRL_DEVPWRSTATUS_PWRSTI3C0_Enum;
66433 
66434 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTDBG [24..24]  ========================================= */
66435 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTDBG                                             */
66436   PWRCTRL_DEVPWRSTATUS_PWRSTDBG_ON     = 1,     /*!< ON : Domain powered on                                                    */
66437   PWRCTRL_DEVPWRSTATUS_PWRSTDBG_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
66438 } PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Enum;
66439 
66440 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUSBPHY [23..23]  ======================================= */
66441 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY                                          */
66442   PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_ON  = 1,     /*!< ON : Domain powered on                                                    */
66443   PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_OFF = 0,     /*!< OFF : Domain powered off                                                  */
66444 } PWRCTRL_DEVPWRSTATUS_PWRSTUSBPHY_Enum;
66445 
66446 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTUSB [22..22]  ========================================= */
66447 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUSB                                             */
66448   PWRCTRL_DEVPWRSTATUS_PWRSTUSB_ON     = 1,     /*!< ON : Domain powered on                                                    */
66449   PWRCTRL_DEVPWRSTATUS_PWRSTUSB_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
66450 } PWRCTRL_DEVPWRSTATUS_PWRSTUSB_Enum;
66451 
66452 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTSDIO [21..21]  ======================================== */
66453 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTSDIO                                            */
66454   PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_ON    = 1,     /*!< ON : Domain powered on                                                    */
66455   PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66456 } PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Enum;
66457 
66458 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTCRYPTO [20..20]  ======================================= */
66459 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO                                          */
66460   PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_ON  = 1,     /*!< ON : Domain powered on                                                    */
66461   PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_OFF = 0,     /*!< OFF : Domain powered off                                                  */
66462 } PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Enum;
66463 
66464 /* ======================================  PWRCTRL DEVPWRSTATUS PWRSTDISPPHY [19..19]  ======================================= */
66465 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY                                         */
66466   PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_ON = 1,     /*!< ON : Domain powered on                                                    */
66467   PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_OFF = 0,    /*!< OFF : Domain powered off                                                  */
66468 } PWRCTRL_DEVPWRSTATUS_PWRSTDISPPHY_Enum;
66469 
66470 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTDISP [18..18]  ======================================== */
66471 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTDISP                                            */
66472   PWRCTRL_DEVPWRSTATUS_PWRSTDISP_ON    = 1,     /*!< ON : Domain powered on                                                    */
66473   PWRCTRL_DEVPWRSTATUS_PWRSTDISP_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66474 } PWRCTRL_DEVPWRSTATUS_PWRSTDISP_Enum;
66475 
66476 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTGFX [17..17]  ========================================= */
66477 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTGFX                                             */
66478   PWRCTRL_DEVPWRSTATUS_PWRSTGFX_ON     = 1,     /*!< ON : Domain powered on                                                    */
66479   PWRCTRL_DEVPWRSTATUS_PWRSTGFX_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
66480 } PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Enum;
66481 
66482 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTMSPI2 [16..16]  ======================================== */
66483 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2                                           */
66484   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_ON   = 1,     /*!< ON : Domain powered on                                                    */
66485   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
66486 } PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Enum;
66487 
66488 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTMSPI1 [15..15]  ======================================== */
66489 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1                                           */
66490   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_ON   = 1,     /*!< ON : Domain powered on                                                    */
66491   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
66492 } PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Enum;
66493 
66494 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTMSPI0 [14..14]  ======================================== */
66495 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0                                           */
66496   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_ON   = 1,     /*!< ON : Domain powered on                                                    */
66497   PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
66498 } PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Enum;
66499 
66500 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTADC [13..13]  ========================================= */
66501 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTADC                                             */
66502   PWRCTRL_DEVPWRSTATUS_PWRSTADC_ON     = 1,     /*!< ON : Domain powered on                                                    */
66503   PWRCTRL_DEVPWRSTATUS_PWRSTADC_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
66504 } PWRCTRL_DEVPWRSTATUS_PWRSTADC_Enum;
66505 
66506 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUART3 [12..12]  ======================================== */
66507 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART3                                           */
66508   PWRCTRL_DEVPWRSTATUS_PWRSTUART3_ON   = 1,     /*!< ON : Domain powered on                                                    */
66509   PWRCTRL_DEVPWRSTATUS_PWRSTUART3_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
66510 } PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Enum;
66511 
66512 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUART2 [11..11]  ======================================== */
66513 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART2                                           */
66514   PWRCTRL_DEVPWRSTATUS_PWRSTUART2_ON   = 1,     /*!< ON : Domain powered on                                                    */
66515   PWRCTRL_DEVPWRSTATUS_PWRSTUART2_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
66516 } PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Enum;
66517 
66518 /* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUART1 [10..10]  ======================================== */
66519 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART1                                           */
66520   PWRCTRL_DEVPWRSTATUS_PWRSTUART1_ON   = 1,     /*!< ON : Domain powered on                                                    */
66521   PWRCTRL_DEVPWRSTATUS_PWRSTUART1_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
66522 } PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Enum;
66523 
66524 /* ========================================  PWRCTRL DEVPWRSTATUS PWRSTUART0 [9..9]  ========================================= */
66525 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART0                                           */
66526   PWRCTRL_DEVPWRSTATUS_PWRSTUART0_ON   = 1,     /*!< ON : Domain powered on                                                    */
66527   PWRCTRL_DEVPWRSTATUS_PWRSTUART0_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
66528 } PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Enum;
66529 
66530 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM7 [8..8]  ========================================= */
66531 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM7                                            */
66532   PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_ON    = 1,     /*!< ON : Domain powered on                                                    */
66533   PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66534 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Enum;
66535 
66536 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM6 [7..7]  ========================================= */
66537 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM6                                            */
66538   PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_ON    = 1,     /*!< ON : Domain powered on                                                    */
66539   PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66540 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Enum;
66541 
66542 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM5 [6..6]  ========================================= */
66543 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM5                                            */
66544   PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_ON    = 1,     /*!< ON : Domain powered on                                                    */
66545   PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66546 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Enum;
66547 
66548 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM4 [5..5]  ========================================= */
66549 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM4                                            */
66550   PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_ON    = 1,     /*!< ON : Domain powered on                                                    */
66551   PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66552 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Enum;
66553 
66554 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM3 [4..4]  ========================================= */
66555 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM3                                            */
66556   PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_ON    = 1,     /*!< ON : Domain powered on                                                    */
66557   PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66558 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Enum;
66559 
66560 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM2 [3..3]  ========================================= */
66561 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM2                                            */
66562   PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_ON    = 1,     /*!< ON : Domain powered on                                                    */
66563   PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66564 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Enum;
66565 
66566 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM1 [2..2]  ========================================= */
66567 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM1                                            */
66568   PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_ON    = 1,     /*!< ON : Domain powered on                                                    */
66569   PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66570 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Enum;
66571 
66572 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM0 [1..1]  ========================================= */
66573 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM0                                            */
66574   PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_ON    = 1,     /*!< ON : Domain powered on                                                    */
66575   PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
66576 } PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Enum;
66577 
66578 /* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOS [0..0]  ========================================== */
66579 typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOS                                             */
66580   PWRCTRL_DEVPWRSTATUS_PWRSTIOS_ON     = 1,     /*!< ON : Domain powered on                                                    */
66581   PWRCTRL_DEVPWRSTATUS_PWRSTIOS_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
66582 } PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Enum;
66583 
66584 /* ======================================================  AUDSSPWREN  ======================================================= */
66585 /* =========================================  PWRCTRL AUDSSPWREN PWRENDSPA [11..11]  ========================================= */
66586 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENDSPA                                              */
66587   PWRCTRL_AUDSSPWREN_PWRENDSPA_EN      = 1,     /*!< EN : Enable                                                               */
66588   PWRCTRL_AUDSSPWREN_PWRENDSPA_DIS     = 0,     /*!< DIS : Disable                                                             */
66589 } PWRCTRL_AUDSSPWREN_PWRENDSPA_Enum;
66590 
66591 /* ========================================  PWRCTRL AUDSSPWREN PWRENAUDADC [10..10]  ======================================== */
66592 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENAUDADC                                            */
66593   PWRCTRL_AUDSSPWREN_PWRENAUDADC_EN    = 1,     /*!< EN : Power up AUDADC                                                      */
66594   PWRCTRL_AUDSSPWREN_PWRENAUDADC_DIS   = 0,     /*!< DIS : Power down AUDADC                                                   */
66595 } PWRCTRL_AUDSSPWREN_PWRENAUDADC_Enum;
66596 
66597 /* ==========================================  PWRCTRL AUDSSPWREN PWRENI2S1 [7..7]  ========================================== */
66598 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENI2S1                                              */
66599   PWRCTRL_AUDSSPWREN_PWRENI2S1_EN      = 1,     /*!< EN : Power up I2S1                                                        */
66600   PWRCTRL_AUDSSPWREN_PWRENI2S1_DIS     = 0,     /*!< DIS : Power down I2S1                                                     */
66601 } PWRCTRL_AUDSSPWREN_PWRENI2S1_Enum;
66602 
66603 /* ==========================================  PWRCTRL AUDSSPWREN PWRENI2S0 [6..6]  ========================================== */
66604 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENI2S0                                              */
66605   PWRCTRL_AUDSSPWREN_PWRENI2S0_EN      = 1,     /*!< EN : Power up I2S0                                                        */
66606   PWRCTRL_AUDSSPWREN_PWRENI2S0_DIS     = 0,     /*!< DIS : Power down I2S0                                                     */
66607 } PWRCTRL_AUDSSPWREN_PWRENI2S0_Enum;
66608 
66609 /* ==========================================  PWRCTRL AUDSSPWREN PWRENPDM3 [5..5]  ========================================== */
66610 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENPDM3                                              */
66611   PWRCTRL_AUDSSPWREN_PWRENPDM3_EN      = 1,     /*!< EN : Power up PDM3                                                        */
66612   PWRCTRL_AUDSSPWREN_PWRENPDM3_DIS     = 0,     /*!< DIS : Power down PDM3                                                     */
66613 } PWRCTRL_AUDSSPWREN_PWRENPDM3_Enum;
66614 
66615 /* ==========================================  PWRCTRL AUDSSPWREN PWRENPDM2 [4..4]  ========================================== */
66616 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENPDM2                                              */
66617   PWRCTRL_AUDSSPWREN_PWRENPDM2_EN      = 1,     /*!< EN : Power up PDM2                                                        */
66618   PWRCTRL_AUDSSPWREN_PWRENPDM2_DIS     = 0,     /*!< DIS : Power down PDM2                                                     */
66619 } PWRCTRL_AUDSSPWREN_PWRENPDM2_Enum;
66620 
66621 /* ==========================================  PWRCTRL AUDSSPWREN PWRENPDM1 [3..3]  ========================================== */
66622 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENPDM1                                              */
66623   PWRCTRL_AUDSSPWREN_PWRENPDM1_EN      = 1,     /*!< EN : Power up PDM1                                                        */
66624   PWRCTRL_AUDSSPWREN_PWRENPDM1_DIS     = 0,     /*!< DIS : Power down PDM1                                                     */
66625 } PWRCTRL_AUDSSPWREN_PWRENPDM1_Enum;
66626 
66627 /* ==========================================  PWRCTRL AUDSSPWREN PWRENPDM0 [2..2]  ========================================== */
66628 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENPDM0                                              */
66629   PWRCTRL_AUDSSPWREN_PWRENPDM0_EN      = 1,     /*!< EN : Power up PDM0                                                        */
66630   PWRCTRL_AUDSSPWREN_PWRENPDM0_DIS     = 0,     /*!< DIS : Power down PDM0                                                     */
66631 } PWRCTRL_AUDSSPWREN_PWRENPDM0_Enum;
66632 
66633 /* =========================================  PWRCTRL AUDSSPWREN PWRENAUDPB [1..1]  ========================================== */
66634 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENAUDPB                                             */
66635   PWRCTRL_AUDSSPWREN_PWRENAUDPB_EN     = 1,     /*!< EN : Power up AUDPB                                                       */
66636   PWRCTRL_AUDSSPWREN_PWRENAUDPB_DIS    = 0,     /*!< DIS : Power down AUDPB                                                    */
66637 } PWRCTRL_AUDSSPWREN_PWRENAUDPB_Enum;
66638 
66639 /* =========================================  PWRCTRL AUDSSPWREN PWRENAUDREC [0..0]  ========================================= */
66640 typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENAUDREC                                            */
66641   PWRCTRL_AUDSSPWREN_PWRENAUDREC_EN    = 1,     /*!< EN : Power up AUDREC                                                      */
66642   PWRCTRL_AUDSSPWREN_PWRENAUDREC_DIS   = 0,     /*!< DIS : Power down AUDREC                                                   */
66643 } PWRCTRL_AUDSSPWREN_PWRENAUDREC_Enum;
66644 
66645 /* ====================================================  AUDSSPWRSTATUS  ===================================================== */
66646 /* =======================================  PWRCTRL AUDSSPWRSTATUS PWRSTDSPA [11..11]  ======================================= */
66647 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA                                          */
66648   PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_ON  = 1,     /*!< ON : Domain powered on                                                    */
66649   PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_OFF = 0,     /*!< OFF : Domain powered off                                                  */
66650 } PWRCTRL_AUDSSPWRSTATUS_PWRSTDSPA_Enum;
66651 
66652 /* ======================================  PWRCTRL AUDSSPWRSTATUS PWRSTAUDADC [10..10]  ====================================== */
66653 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC                                        */
66654   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_ON = 1,    /*!< ON : Domain powered on                                                    */
66655   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_OFF = 0,   /*!< OFF : Domain powered off                                                  */
66656 } PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDADC_Enum;
66657 
66658 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTI2S1 [7..7]  ======================================== */
66659 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1                                          */
66660   PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_ON  = 1,     /*!< ON : Domain powered on                                                    */
66661   PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_OFF = 0,     /*!< OFF : Domain powered off                                                  */
66662 } PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Enum;
66663 
66664 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTI2S0 [6..6]  ======================================== */
66665 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0                                          */
66666   PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_ON  = 1,     /*!< ON : Domain powered on                                                    */
66667   PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_OFF = 0,     /*!< OFF : Domain powered off                                                  */
66668 } PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Enum;
66669 
66670 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTPDM3 [5..5]  ======================================== */
66671 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3                                          */
66672   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_ON  = 1,     /*!< ON : Domain powered on                                                    */
66673   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_OFF = 0,     /*!< OFF : Domain powered off                                                  */
66674 } PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM3_Enum;
66675 
66676 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTPDM2 [4..4]  ======================================== */
66677 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2                                          */
66678   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_ON  = 1,     /*!< ON : Domain powered on                                                    */
66679   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_OFF = 0,     /*!< OFF : Domain powered off                                                  */
66680 } PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM2_Enum;
66681 
66682 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTPDM1 [3..3]  ======================================== */
66683 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1                                          */
66684   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_ON  = 1,     /*!< ON : Domain powered on                                                    */
66685   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_OFF = 0,     /*!< OFF : Domain powered off                                                  */
66686 } PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM1_Enum;
66687 
66688 /* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTPDM0 [2..2]  ======================================== */
66689 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0                                          */
66690   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_ON  = 1,     /*!< ON : Domain powered on                                                    */
66691   PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_OFF = 0,     /*!< OFF : Domain powered off                                                  */
66692 } PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Enum;
66693 
66694 /* =======================================  PWRCTRL AUDSSPWRSTATUS PWRSTAUDPB [1..1]  ======================================== */
66695 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB                                         */
66696   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_ON = 1,     /*!< ON : Domain powered on                                                    */
66697   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_OFF = 0,    /*!< OFF : Domain powered off                                                  */
66698 } PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Enum;
66699 
66700 /* =======================================  PWRCTRL AUDSSPWRSTATUS PWRSTAUDREC [0..0]  ======================================= */
66701 typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC                                        */
66702   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_ON = 1,    /*!< ON : Domain powered on                                                    */
66703   PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_OFF = 0,   /*!< OFF : Domain powered off                                                  */
66704 } PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Enum;
66705 
66706 /* =======================================================  MEMPWREN  ======================================================== */
66707 /* =========================================  PWRCTRL MEMPWREN PWRENCACHEB2 [5..5]  ========================================== */
66708 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENCACHEB2                                             */
66709   PWRCTRL_MEMPWREN_PWRENCACHEB2_EN     = 1,     /*!< EN : Power up Cache Bank 2                                                */
66710   PWRCTRL_MEMPWREN_PWRENCACHEB2_DIS    = 0,     /*!< DIS : Power down Cache Bank 2                                             */
66711 } PWRCTRL_MEMPWREN_PWRENCACHEB2_Enum;
66712 
66713 /* =========================================  PWRCTRL MEMPWREN PWRENCACHEB0 [4..4]  ========================================== */
66714 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENCACHEB0                                             */
66715   PWRCTRL_MEMPWREN_PWRENCACHEB0_EN     = 1,     /*!< EN : Power up Cache Bank 0                                                */
66716   PWRCTRL_MEMPWREN_PWRENCACHEB0_DIS    = 0,     /*!< DIS : Power down Cache Bank 0                                             */
66717 } PWRCTRL_MEMPWREN_PWRENCACHEB0_Enum;
66718 
66719 /* ===========================================  PWRCTRL MEMPWREN PWRENNVM0 [3..3]  =========================================== */
66720 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENNVM0                                                */
66721   PWRCTRL_MEMPWREN_PWRENNVM0_EN        = 1,     /*!< EN : Power up NVM0                                                        */
66722   PWRCTRL_MEMPWREN_PWRENNVM0_DIS       = 0,     /*!< DIS : Power down NVM0                                                     */
66723 } PWRCTRL_MEMPWREN_PWRENNVM0_Enum;
66724 
66725 /* ===========================================  PWRCTRL MEMPWREN PWRENDTCM [0..2]  =========================================== */
66726 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENDTCM                                                */
66727   PWRCTRL_MEMPWREN_PWRENDTCM_NONE      = 0,     /*!< NONE : Do not enable power to any DTCMs                                   */
66728   PWRCTRL_MEMPWREN_PWRENDTCM_TCM8K     = 1,     /*!< TCM8K : Power ON only lower 8k                                            */
66729   PWRCTRL_MEMPWREN_PWRENDTCM_TCM128K   = 3,     /*!< TCM128K : Power ON only lower 128k                                        */
66730   PWRCTRL_MEMPWREN_PWRENDTCM_TCM384K   = 7,     /*!< TCM384K : Power ON 384k                                                   */
66731 } PWRCTRL_MEMPWREN_PWRENDTCM_Enum;
66732 
66733 /* =====================================================  MEMPWRSTATUS  ====================================================== */
66734 /* =========================================  PWRCTRL MEMPWRSTATUS PWRSTDTCM [0..2]  ========================================= */
66735 typedef enum {                                  /*!< PWRCTRL_MEMPWRSTATUS_PWRSTDTCM                                            */
66736   PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_NONE  = 0,     /*!< NONE : Do not enable power to any DTCMs                                   */
66737   PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM8K = 1,     /*!< TCM8K : Only lower 8k is powered up                                       */
66738   PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM128K = 3,   /*!< TCM128K : Only lower 128k is powered up                                   */
66739   PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM384K = 7,   /*!< TCM384K : All 384k is powered up                                          */
66740 } PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Enum;
66741 
66742 /* =======================================================  MEMRETCFG  ======================================================= */
66743 /* =========================================  PWRCTRL MEMRETCFG CACHEPWDSLP [4..4]  ========================================== */
66744 typedef enum {                                  /*!< PWRCTRL_MEMRETCFG_CACHEPWDSLP                                             */
66745   PWRCTRL_MEMRETCFG_CACHEPWDSLP_EN     = 1,     /*!< EN : Power down cache in deep sleep                                       */
66746   PWRCTRL_MEMRETCFG_CACHEPWDSLP_DIS    = 0,     /*!< DIS : Retain cache in deep sleep                                          */
66747 } PWRCTRL_MEMRETCFG_CACHEPWDSLP_Enum;
66748 
66749 /* ==========================================  PWRCTRL MEMRETCFG NVM0PWDSLP [3..3]  ========================================== */
66750 typedef enum {                                  /*!< PWRCTRL_MEMRETCFG_NVM0PWDSLP                                              */
66751   PWRCTRL_MEMRETCFG_NVM0PWDSLP_EN      = 1,     /*!< EN : NVM0 is powered down during deepsleep                                */
66752   PWRCTRL_MEMRETCFG_NVM0PWDSLP_DIS     = 0,     /*!< DIS : NVM0 is kept powered on during deepsleep                            */
66753 } PWRCTRL_MEMRETCFG_NVM0PWDSLP_Enum;
66754 
66755 /* ==========================================  PWRCTRL MEMRETCFG DTCMPWDSLP [0..2]  ========================================== */
66756 typedef enum {                                  /*!< PWRCTRL_MEMRETCFG_DTCMPWDSLP                                              */
66757   PWRCTRL_MEMRETCFG_DTCMPWDSLP_NONE    = 0,     /*!< NONE : All DTCM retained                                                  */
66758   PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0DTCM0 = 1, /*!< GROUP0DTCM0 : Group0_DTCM0 powered down in deep sleep (0KB-8KB)           */
66759   PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0DTCM1 = 2, /*!< GROUP0DTCM1 : Group0_DTCM1 powered down in deep sleep (8KB-128KB)         */
66760   PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0  = 3,     /*!< GROUP0 : Both DTCMs in group0 are powered down in deep sleep
66761                                                      (0KB-128KB)                                                               */
66762   PWRCTRL_MEMRETCFG_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6,/*!< ALLBUTGROUP0DTCM0 : Group1 and Group0_DTCM1 are powered down
66763                                                      in deep sleep (8KB-384KB)                                                 */
66764   PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP1  = 4,     /*!< GROUP1 : Group1 DTCM powered down in deep sleep (128KB-384KB)             */
66765   PWRCTRL_MEMRETCFG_DTCMPWDSLP_ALL     = 7,     /*!< ALL : All DTCMs powered down in deep sleep (0KB-384KB)                    */
66766 } PWRCTRL_MEMRETCFG_DTCMPWDSLP_Enum;
66767 
66768 /* =====================================================  SYSPWRSTATUS  ====================================================== */
66769 /* ======================================================  SSRAMPWREN  ======================================================= */
66770 /* =========================================  PWRCTRL SSRAMPWREN PWRENSSRAM [0..1]  ========================================== */
66771 typedef enum {                                  /*!< PWRCTRL_SSRAMPWREN_PWRENSSRAM                                             */
66772   PWRCTRL_SSRAMPWREN_PWRENSSRAM_NONE   = 0,     /*!< NONE : Do not power ON any of the SRAM banks                              */
66773   PWRCTRL_SSRAMPWREN_PWRENSSRAM_GROUP0 = 1,     /*!< GROUP0 : Power ON only SRAM0 group (lower 1M)                             */
66774   PWRCTRL_SSRAMPWREN_PWRENSSRAM_GROUP1 = 2,     /*!< GROUP1 : Power ON only SRAM1 group (upper 1M)                             */
66775   PWRCTRL_SSRAMPWREN_PWRENSSRAM_ALL    = 3,     /*!< ALL : All shared SRAM banks (SSRAM0 1M + SSRAM1 1M) powered
66776                                                      ON                                                                        */
66777 } PWRCTRL_SSRAMPWREN_PWRENSSRAM_Enum;
66778 
66779 /* ======================================================  SSRAMPWRST  ======================================================= */
66780 /* ======================================================  SSRAMRETCFG  ====================================================== */
66781 /* ========================================  PWRCTRL SSRAMRETCFG SSRAMPWDSLP [0..1]  ========================================= */
66782 typedef enum {                                  /*!< PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP                                           */
66783   PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_NONE = 0,     /*!< NONE : All banks retained                                                 */
66784   PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_GROUP0 = 1,   /*!< GROUP0 : Power down only SRAM group0                                      */
66785   PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_GROUP1 = 2,   /*!< GROUP1 : Power down only SRAM group1                                      */
66786   PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_ALL  = 3,     /*!< ALL : All shared SRAM banks powered down                                  */
66787 } PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Enum;
66788 
66789 /* =====================================================  DEVPWREVENTEN  ===================================================== */
66790 /* =========================================  PWRCTRL DEVPWREVENTEN AUDEVEN [7..7]  ========================================== */
66791 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_AUDEVEN                                             */
66792   PWRCTRL_DEVPWREVENTEN_AUDEVEN_EN     = 1,     /*!< EN : Enable AUD power-on status event                                     */
66793   PWRCTRL_DEVPWREVENTEN_AUDEVEN_DIS    = 0,     /*!< DIS : Disable AUD power-on status event                                   */
66794 } PWRCTRL_DEVPWREVENTEN_AUDEVEN_Enum;
66795 
66796 /* =========================================  PWRCTRL DEVPWREVENTEN MSPIEVEN [6..6]  ========================================= */
66797 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MSPIEVEN                                            */
66798   PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN    = 1,     /*!< EN : Enable MSPI power-on status event                                    */
66799   PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS   = 0,     /*!< DIS : Disable MSPI power-on status event                                  */
66800 } PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum;
66801 
66802 /* =========================================  PWRCTRL DEVPWREVENTEN ADCEVEN [5..5]  ========================================== */
66803 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_ADCEVEN                                             */
66804   PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN     = 1,     /*!< EN : Enable ADC power-on status event                                     */
66805   PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS    = 0,     /*!< DIS : Disable ADC power-on status event                                   */
66806 } PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum;
66807 
66808 /* =========================================  PWRCTRL DEVPWREVENTEN HCPCEVEN [4..4]  ========================================= */
66809 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPCEVEN                                            */
66810   PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN    = 1,     /*!< EN : Enable HCPC power-on status event                                    */
66811   PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS   = 0,     /*!< DIS : Disable HCPC power-on status event                                  */
66812 } PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum;
66813 
66814 /* =========================================  PWRCTRL DEVPWREVENTEN HCPBEVEN [3..3]  ========================================= */
66815 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPBEVEN                                            */
66816   PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN    = 1,     /*!< EN : Enable HCPB power-on status event                                    */
66817   PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS   = 0,     /*!< DIS : Disable HCPB power-on status event                                  */
66818 } PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum;
66819 
66820 /* =========================================  PWRCTRL DEVPWREVENTEN HCPAEVEN [2..2]  ========================================= */
66821 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPAEVEN                                            */
66822   PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN    = 1,     /*!< EN : Enable HCPA power-on status event                                    */
66823   PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS   = 0,     /*!< DIS : Disable HCPA power-on status event                                  */
66824 } PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum;
66825 
66826 /* =========================================  PWRCTRL DEVPWREVENTEN MCUHEVEN [1..1]  ========================================= */
66827 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCUHEVEN                                            */
66828   PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN    = 1,     /*!< EN : Enable MCHU power-on status event                                    */
66829   PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS   = 0,     /*!< DIS : Disable MCUH power-on status event                                  */
66830 } PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum;
66831 
66832 /* =========================================  PWRCTRL DEVPWREVENTEN MCULEVEN [0..0]  ========================================= */
66833 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCULEVEN                                            */
66834   PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN    = 1,     /*!< EN : Enable MCUL power-on status event                                    */
66835   PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS   = 0,     /*!< DIS : Disable MCUL power-on status event                                  */
66836 } PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum;
66837 
66838 /* =====================================================  MEMPWREVENTEN  ===================================================== */
66839 /* ========================================  PWRCTRL MEMPWREVENTEN CACHEB2EN [5..5]  ========================================= */
66840 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB2EN                                           */
66841   PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN   = 1,     /*!< EN : Enable CACHE BANK 2 status event                                     */
66842   PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 2 status event                                   */
66843 } PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum;
66844 
66845 /* ========================================  PWRCTRL MEMPWREVENTEN CACHEB0EN [4..4]  ========================================= */
66846 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB0EN                                           */
66847   PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN   = 1,     /*!< EN : Enable CACHE BANK 0 status event                                     */
66848   PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 0 status event                                   */
66849 } PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum;
66850 
66851 /* ==========================================  PWRCTRL MEMPWREVENTEN NVM0EN [3..3]  ========================================== */
66852 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_NVM0EN                                              */
66853   PWRCTRL_MEMPWREVENTEN_NVM0EN_EN      = 1,     /*!< EN : Enable NVM status event                                              */
66854   PWRCTRL_MEMPWREVENTEN_NVM0EN_DIS     = 0,     /*!< DIS : Disables NVM status event                                           */
66855 } PWRCTRL_MEMPWREVENTEN_NVM0EN_Enum;
66856 
66857 /* ==========================================  PWRCTRL MEMPWREVENTEN DTCMEN [0..2]  ========================================== */
66858 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_DTCMEN                                              */
66859   PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE    = 0,     /*!< NONE : Do not enable DTCM power-on status event                           */
66860   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1,/*!< GROUP0DTCM0EN : Enable GROUP0_DTCM0 power on status event                */
66861   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2,/*!< GROUP0DTCM1EN : Enable GROUP0_DTCM1 power on status event                */
66862   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3,    /*!< GROUP0EN : Enable DTCMs in group0 power on status event                   */
66863   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4,    /*!< GROUP1EN : Enable DTCMs in group1 power on status event                   */
66864   PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL     = 7,     /*!< ALL : Enable all DTCM power on status event                               */
66865 } PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum;
66866 
66867 /* ======================================================  MMSOVERRIDE  ====================================================== */
66868 /* ====================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMRETGFX [10..11]  ===================================== */
66869 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX                                     */
66870   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_ALWAYSON = 1,/*!< ALWAYSON : When PD_GFX is off, retention is always okay for
66871                                                      PD_GFX domain.                                                            */
66872   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_PGSTATE = 0,/*!< PGSTATE : When PD_GFX is off, retention is okay based on the
66873                                                      state of PD_GFX domain and SSRAMRETCFG.                                   */
66874 } PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Enum;
66875 
66876 /* =====================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMRETDISP [8..9]  ===================================== */
66877 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP                                    */
66878   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_ALWAYSON = 1,/*!< ALWAYSON : When PD_DISP is off, retention is always okay for
66879                                                      PD_DISP domain.                                                           */
66880   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_PGSTATE = 0,/*!< PGSTATE : When PD_DISP is off, retention is okay based on the
66881                                                      state of PD_DISP domain and SSRAMRETCFG.                                  */
66882 } PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Enum;
66883 
66884 /* =====================================  PWRCTRL MMSOVERRIDE MMSOVRDSPRAMRETGFX [6..7]  ===================================== */
66885 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX                                    */
66886   PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_ALWAYSON = 1,/*!< ALWAYSON : When PD_GFX is off, retention is always okay for
66887                                                      PD_GFX domain.                                                            */
66888   PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_PGSTATE = 0,/*!< PGSTATE : When PD_GFX is off, retention is okay based on the
66889                                                      state of PD_GFX domain and DSP[1|0]MEMRETCFG.                             */
66890 } PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Enum;
66891 
66892 /* ====================================  PWRCTRL MMSOVERRIDE MMSOVRDSPRAMRETDISP [4..5]  ===================================== */
66893 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP                                   */
66894   PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_ALWAYSON = 1,/*!< ALWAYSON : When PD_DISP is off, retention is always okay for
66895                                                      PD_DISP domain.                                                           */
66896   PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_PGSTATE = 0,/*!< PGSTATE : When PD_DISP is off, retention is okay based on the
66897                                                      state of PD_DISP domain and DSP[1|0]MEMRETCFG.                            */
66898 } PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Enum;
66899 
66900 /* =======================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMGFX [3..3]  ======================================= */
66901 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX                                        */
66902   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_NOGFX = 1, /*!< NOGFX : SSRAM power state is not affected by PD_GFX setting.              */
66903   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_PD_GFX = 0,/*!< PD_GFX : SSRAM power state set by SSRAMPWREN_PWRENSSRAM is overridden
66904                                                      by PD_GFX setting.                                                        */
66905 } PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Enum;
66906 
66907 /* ======================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMDISP [2..2]  ======================================= */
66908 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP                                       */
66909   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_NODISP = 1,/*!< NODISP : SSRAM power state is not affected by PD_DISP setting.           */
66910   PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_PD_DISP = 0,/*!< PD_DISP : SSRAM power state set by SSRAMPWREN_PWRENSSRAM is
66911                                                      overridden by PD_DISP setting.                                            */
66912 } PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Enum;
66913 
66914 /* =======================================  PWRCTRL MMSOVERRIDE MMSOVRMCULGFX [1..1]  ======================================== */
66915 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX                                         */
66916   PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_MCULON = 0, /*!< MCULON : When PD_GFX is on, MCUL is on.                                   */
66917   PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_MCULOFF = 1,/*!< MCULOFF : When PD_GFX is on, MCUL is still off.                           */
66918 } PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Enum;
66919 
66920 /* =======================================  PWRCTRL MMSOVERRIDE MMSOVRMCULDISP [0..0]  ======================================= */
66921 typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP                                        */
66922   PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_MCULON = 0,/*!< MCULON : When PD_DISP is on, MCUL is on.                                  */
66923   PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_MCULOFF = 1,/*!< MCULOFF : When PD_DISP is on, MCUL is still off.                         */
66924 } PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Enum;
66925 
66926 /* ======================================================  DSP0PWRCTRL  ====================================================== */
66927 /* ========================================  PWRCTRL DSP0PWRCTRL DSP0PCMRSTOR [4..4]  ======================================== */
66928 typedef enum {                                  /*!< PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR                                          */
66929   PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_EN  = 1,     /*!< EN : Keep DSP0 PCM in Reset                                               */
66930   PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_DIS = 0,     /*!< DIS : Remove DSP0 PCM Reset override                                      */
66931 } PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Enum;
66932 
66933 /* ======================================================  DSP0PERFREQ  ====================================================== */
66934 /* =======================================  PWRCTRL DSP0PERFREQ DSP0PERFSTATUS [3..4]  ======================================= */
66935 typedef enum {                                  /*!< PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS                                        */
66936   PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_ULP = 0,   /*!< ULP : DSP0 is in ULP mode (freq=48MHz)                                    */
66937   PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_LP = 1,    /*!< LP : DSP0 is in LP mode (freq=192MHz)                                     */
66938   PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_HP = 2,    /*!< HP : DSP0 is in HP mode (freq=384MHz)                                     */
66939 } PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Enum;
66940 
66941 /* ========================================  PWRCTRL DSP0PERFREQ DSP0PERFREQ [0..1]  ========================================= */
66942 typedef enum {                                  /*!< PWRCTRL_DSP0PERFREQ_DSP0PERFREQ                                           */
66943   PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_ULP  = 0,     /*!< ULP : DSP0 to be run in ULP mode (freq=48MHz)                             */
66944   PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_LP   = 1,     /*!< LP : DSP0 to be run in LP mode (freq=192MHz)                              */
66945   PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_HP   = 2,     /*!< HP : DSP0 to be run in HP mode (freq=384MHz)                              */
66946 } PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Enum;
66947 
66948 /* =====================================================  DSP0MEMPWREN  ====================================================== */
66949 /* ======================================  PWRCTRL DSP0MEMPWREN PWRENDSP0ICACHE [1..1]  ====================================== */
66950 typedef enum {                                  /*!< PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE                                      */
66951   PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_OFF = 0, /*!< OFF : Do not power up ICACHE                                              */
66952   PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_ON = 1,  /*!< ON : Power up ICACHE                                                      */
66953 } PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Enum;
66954 
66955 /* =======================================  PWRCTRL DSP0MEMPWREN PWRENDSP0RAM [0..0]  ======================================== */
66956 typedef enum {                                  /*!< PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM                                         */
66957   PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_OFF = 0,    /*!< OFF : Do not power ON any of the IRAM/DRAM                                */
66958   PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_ON = 1,     /*!< ON : Power up all IRAM (128K) and DRAM (256K)                             */
66959 } PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Enum;
66960 
66961 /* =====================================================  DSP0MEMPWRST  ====================================================== */
66962 /* =====================================================  DSP0MEMRETCFG  ===================================================== */
66963 /* ======================================  PWRCTRL DSP0MEMRETCFG DSP0RAMACTGFX [4..4]  ======================================= */
66964 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX                                       */
66965   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
66966   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of GFX state                          */
66967 } PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Enum;
66968 
66969 /* ======================================  PWRCTRL DSP0MEMRETCFG DSP0RAMACTDISP [3..3]  ====================================== */
66970 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP                                      */
66971   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                   */
66972   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_ACT = 1, /*!< ACT : Keep RAMs active irrespective of DISP state                         */
66973 } PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Enum;
66974 
66975 /* =====================================  PWRCTRL DSP0MEMRETCFG ICACHEPWDDSP0OFF [2..2]  ===================================== */
66976 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF                                    */
66977   PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_RET = 0,/*!< RET : ICACHE retained                                                    */
66978   PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_PWD = 1,/*!< PWD : Power down ICACHE                                                  */
66979 } PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Enum;
66980 
66981 /* ======================================  PWRCTRL DSP0MEMRETCFG DSP0RAMACTMCU [1..1]  ======================================= */
66982 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU                                       */
66983   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
66984   PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of MCU state                          */
66985 } PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Enum;
66986 
66987 /* ======================================  PWRCTRL DSP0MEMRETCFG RAMPWDDSP0OFF [0..0]  ======================================= */
66988 typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF                                       */
66989   PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_RET = 0,  /*!< RET : IRAM and DRAM retained                                              */
66990   PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_PWD = 1,  /*!< PWD : Power down all IRAM and DRAM                                        */
66991 } PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Enum;
66992 
66993 /* ======================================================  DSP1PWRCTRL  ====================================================== */
66994 /* ========================================  PWRCTRL DSP1PWRCTRL DSP1PCMRSTOR [4..4]  ======================================== */
66995 typedef enum {                                  /*!< PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR                                          */
66996   PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_EN  = 1,     /*!< EN : Keep DSP1 PCM in Reset                                               */
66997   PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_DIS = 0,     /*!< DIS : Remove DSP1 PCM Reset override                                      */
66998 } PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Enum;
66999 
67000 /* ======================================================  DSP1PERFREQ  ====================================================== */
67001 /* =======================================  PWRCTRL DSP1PERFREQ DSP1PERFSTATUS [3..4]  ======================================= */
67002 typedef enum {                                  /*!< PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS                                        */
67003   PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_ULP = 0,   /*!< ULP : DSP1 is in ULP mode (freq=48MHz)                                    */
67004   PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_LP = 1,    /*!< LP : DSP1 is in LP mode (freq=192MHz)                                     */
67005   PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_HP = 2,    /*!< HP : DSP1 is in HP mode (freq=384MHz)                                     */
67006 } PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Enum;
67007 
67008 /* ========================================  PWRCTRL DSP1PERFREQ DSP1PERFREQ [0..1]  ========================================= */
67009 typedef enum {                                  /*!< PWRCTRL_DSP1PERFREQ_DSP1PERFREQ                                           */
67010   PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_ULP  = 0,     /*!< ULP : DSP1 to be run in ULP mode (freq=48MHz)                             */
67011   PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_LP   = 1,     /*!< LP : DSP1 to be run in LP mode (freq=192MHz)                              */
67012   PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_HP   = 2,     /*!< HP : DSP1 to be run in HP mode (freq=384MHz)                              */
67013 } PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Enum;
67014 
67015 /* =====================================================  DSP1MEMPWREN  ====================================================== */
67016 /* ======================================  PWRCTRL DSP1MEMPWREN PWRENDSP1ICACHE [1..1]  ====================================== */
67017 typedef enum {                                  /*!< PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE                                      */
67018   PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_OFF = 0, /*!< OFF : Do not power up ICACHE                                              */
67019   PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_ON = 1,  /*!< ON : Power up ICACHE                                                      */
67020 } PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Enum;
67021 
67022 /* =======================================  PWRCTRL DSP1MEMPWREN PWRENDSP1RAM [0..0]  ======================================== */
67023 typedef enum {                                  /*!< PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM                                         */
67024   PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_OFF = 0,    /*!< OFF : Do not power ON any of the IRAM/DRAM                                */
67025   PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_ON = 1,     /*!< ON : Power up all IRAM (32K) and DRAM (64K)                               */
67026 } PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Enum;
67027 
67028 /* =====================================================  DSP1MEMPWRST  ====================================================== */
67029 /* =====================================================  DSP1MEMRETCFG  ===================================================== */
67030 /* ======================================  PWRCTRL DSP1MEMRETCFG DSP1RAMACTGFX [4..4]  ======================================= */
67031 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX                                       */
67032   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
67033   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of GFX state                          */
67034 } PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Enum;
67035 
67036 /* ======================================  PWRCTRL DSP1MEMRETCFG DSP1RAMACTDISP [3..3]  ====================================== */
67037 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP                                      */
67038   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                   */
67039   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_ACT = 1, /*!< ACT : Keep RAMs active irrespective of DISP state                         */
67040 } PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Enum;
67041 
67042 /* =====================================  PWRCTRL DSP1MEMRETCFG ICACHEPWDDSP1OFF [2..2]  ===================================== */
67043 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF                                    */
67044   PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_RET = 0,/*!< RET : ICACHE retained                                                    */
67045   PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_PWD = 1,/*!< PWD : Power down ICACHE                                                  */
67046 } PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Enum;
67047 
67048 /* ======================================  PWRCTRL DSP1MEMRETCFG DSP1RAMACTMCU [1..1]  ======================================= */
67049 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU                                       */
67050   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
67051   PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of MCU state                          */
67052 } PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Enum;
67053 
67054 /* ======================================  PWRCTRL DSP1MEMRETCFG RAMPWDDSP1OFF [0..0]  ======================================= */
67055 typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF                                       */
67056   PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_RET = 0,  /*!< RET : IRAM and DRAM retained                                              */
67057   PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_PWD = 1,  /*!< PWD : Power down all IRAM and DRAM                                        */
67058 } PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Enum;
67059 
67060 /* =======================================================  PWRACKOVR  ======================================================= */
67061 /* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEDSPA [17..17]  ===================================== */
67062 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA                                      */
67063   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
67064   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67065                                                      HW generated power ack                                                    */
67066 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_Enum;
67067 
67068 /* ====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEUSBPHY [16..16]  ==================================== */
67069 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY                                    */
67070   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                        */
67071   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67072                                                      HW generated power ack                                                    */
67073 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_Enum;
67074 
67075 /* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEUSB [15..15]  ====================================== */
67076 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB                                       */
67077   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
67078   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67079                                                      HW generated power ack                                                    */
67080 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_Enum;
67081 
67082 /* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDESDIO [14..14]  ===================================== */
67083 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO                                      */
67084   PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
67085   PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67086                                                      HW generated power ack                                                    */
67087 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_Enum;
67088 
67089 /* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEMSPI [13..13]  ===================================== */
67090 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI                                      */
67091   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
67092   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67093                                                      HW generated power ack                                                    */
67094 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_Enum;
67095 
67096 /* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEMCUL [12..12]  ===================================== */
67097 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL                                      */
67098   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
67099   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67100                                                      HW generated power ack                                                    */
67101 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_Enum;
67102 
67103 /* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEIOS [11..11]  ====================================== */
67104 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS                                       */
67105   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
67106   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67107                                                      HW generated power ack                                                    */
67108 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_Enum;
67109 
67110 /* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEHCPC [10..10]  ===================================== */
67111 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC                                      */
67112   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
67113   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67114                                                      HW generated power ack                                                    */
67115 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_Enum;
67116 
67117 /* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEHCPB [9..9]  ====================================== */
67118 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB                                      */
67119   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
67120   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67121                                                      HW generated power ack                                                    */
67122 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_Enum;
67123 
67124 /* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEHCPA [8..8]  ====================================== */
67125 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA                                      */
67126   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
67127   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67128                                                      HW generated power ack                                                    */
67129 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_Enum;
67130 
67131 /* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEGFX [7..7]  ======================================= */
67132 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX                                       */
67133   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
67134   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67135                                                      HW generated power ack                                                    */
67136 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_Enum;
67137 
67138 /* ====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEDISPPHY [6..6]  ===================================== */
67139 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY                                   */
67140   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                       */
67141   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67142                                                      HW generated power ack                                                    */
67143 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_Enum;
67144 
67145 /* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEDISP [5..5]  ====================================== */
67146 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP                                      */
67147   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
67148   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67149                                                      HW generated power ack                                                    */
67150 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_Enum;
67151 
67152 /* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEDBG [4..4]  ======================================= */
67153 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG                                       */
67154   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
67155   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67156                                                      HW generated power ack                                                    */
67157 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_Enum;
67158 
67159 /* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDECRYPTO [3..3]  ===================================== */
67160 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO                                    */
67161   PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                        */
67162   PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67163                                                      HW generated power ack                                                    */
67164 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_Enum;
67165 
67166 /* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEAUDADC [2..2]  ===================================== */
67167 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC                                    */
67168   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                        */
67169   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67170                                                      HW generated power ack                                                    */
67171 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_Enum;
67172 
67173 /* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEAUD [1..1]  ======================================= */
67174 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD                                       */
67175   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
67176   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67177                                                      HW generated power ack                                                    */
67178 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_Enum;
67179 
67180 /* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEADC [0..0]  ======================================= */
67181 typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC                                       */
67182   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
67183   PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
67184                                                      HW generated power ack                                                    */
67185 } PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_Enum;
67186 
67187 /* =====================================================  PWRCNTDEFVAL  ====================================================== */
67188 /* ========================================================  VRCTRL  ========================================================= */
67189 /* ===========================================  PWRCTRL VRCTRL SIMOBUCKEN [0..0]  ============================================ */
67190 typedef enum {                                  /*!< PWRCTRL_VRCTRL_SIMOBUCKEN                                                 */
67191   PWRCTRL_VRCTRL_SIMOBUCKEN_EN         = 1,     /*!< EN : Enable the SIMO Buck                                                 */
67192   PWRCTRL_VRCTRL_SIMOBUCKEN_DIS        = 0,     /*!< DIS : Disable the SIMO Buck                                               */
67193 } PWRCTRL_VRCTRL_SIMOBUCKEN_Enum;
67194 
67195 /* =====================================================  LEGACYVRLPOVR  ===================================================== */
67196 /* =======================================================  VRSTATUS  ======================================================== */
67197 /* ==========================================  PWRCTRL VRSTATUS SIMOBUCKST [4..5]  =========================================== */
67198 typedef enum {                                  /*!< PWRCTRL_VRSTATUS_SIMOBUCKST                                               */
67199   PWRCTRL_VRSTATUS_SIMOBUCKST_OFF      = 0,     /*!< OFF : Indicates the the SIMO BUCK is OFF.                                 */
67200   PWRCTRL_VRSTATUS_SIMOBUCKST_LP       = 2,     /*!< LP : Indicates the the SIMO BUCK is ON and in LP mode.                    */
67201   PWRCTRL_VRSTATUS_SIMOBUCKST_ACT      = 3,     /*!< ACT : Indicates the the SIMO BUCK is ON and in ACT mode.                  */
67202 } PWRCTRL_VRSTATUS_SIMOBUCKST_Enum;
67203 
67204 /* ===========================================  PWRCTRL VRSTATUS MEMLDOST [2..3]  ============================================ */
67205 typedef enum {                                  /*!< PWRCTRL_VRSTATUS_MEMLDOST                                                 */
67206   PWRCTRL_VRSTATUS_MEMLDOST_OFF        = 0,     /*!< OFF : Indicates the the MEMLDO is OFF.                                    */
67207   PWRCTRL_VRSTATUS_MEMLDOST_LP         = 2,     /*!< LP : Indicates the the MEMLDO is ON and in LP mode.                       */
67208   PWRCTRL_VRSTATUS_MEMLDOST_ACT        = 3,     /*!< ACT : Indicates the the MEMLDO is ON and in ACT mode.                     */
67209 } PWRCTRL_VRSTATUS_MEMLDOST_Enum;
67210 
67211 /* ===========================================  PWRCTRL VRSTATUS CORELDOST [0..1]  =========================================== */
67212 typedef enum {                                  /*!< PWRCTRL_VRSTATUS_CORELDOST                                                */
67213   PWRCTRL_VRSTATUS_CORELDOST_OFF       = 0,     /*!< OFF : Indicates the the CORELDO is OFF.                                   */
67214   PWRCTRL_VRSTATUS_CORELDOST_LP        = 2,     /*!< LP : Indicates the the CORELDO is ON and in LP mode.                      */
67215   PWRCTRL_VRSTATUS_CORELDOST_ACT       = 3,     /*!< ACT : Indicates the the CORELDO is ON and in ACT mode.                    */
67216 } PWRCTRL_VRSTATUS_CORELDOST_Enum;
67217 
67218 /* =====================================================  PWRWEIGHTULP0  ===================================================== */
67219 /* =====================================================  PWRWEIGHTULP1  ===================================================== */
67220 /* =====================================================  PWRWEIGHTULP2  ===================================================== */
67221 /* =====================================================  PWRWEIGHTULP3  ===================================================== */
67222 /* =====================================================  PWRWEIGHTULP4  ===================================================== */
67223 /* =====================================================  PWRWEIGHTULP5  ===================================================== */
67224 /* =====================================================  PWRWEIGHTLP0  ====================================================== */
67225 /* =====================================================  PWRWEIGHTLP1  ====================================================== */
67226 /* =====================================================  PWRWEIGHTLP2  ====================================================== */
67227 /* =====================================================  PWRWEIGHTLP3  ====================================================== */
67228 /* =====================================================  PWRWEIGHTLP4  ====================================================== */
67229 /* =====================================================  PWRWEIGHTLP5  ====================================================== */
67230 /* =====================================================  PWRWEIGHTHP0  ====================================================== */
67231 /* =====================================================  PWRWEIGHTHP1  ====================================================== */
67232 /* =====================================================  PWRWEIGHTHP2  ====================================================== */
67233 /* =====================================================  PWRWEIGHTHP3  ====================================================== */
67234 /* =====================================================  PWRWEIGHTHP4  ====================================================== */
67235 /* =====================================================  PWRWEIGHTHP5  ====================================================== */
67236 /* =====================================================  PWRWEIGHTSLP  ====================================================== */
67237 /* =====================================================  VRDEMOTIONTHR  ===================================================== */
67238 /* =======================================================  SRAMCTRL  ======================================================== */
67239 /* ========================================  PWRCTRL SRAMCTRL SRAMLIGHTSLEEP [8..19]  ======================================== */
67240 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP                                           */
67241   PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL  = 4095,  /*!< ALL : Enable LIGHT SLEEP for ALL SRAMs                                    */
67242   PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS  = 0,     /*!< DIS : Disables LIGHT SLEEP for ALL SRAMs                                  */
67243 } PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum;
67244 
67245 /* =======================================  PWRCTRL SRAMCTRL SRAMMASTERCLKGATE [2..2]  ======================================= */
67246 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE                                        */
67247   PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1,    /*!< EN : Enable Master SRAM Clock Gate                                        */
67248   PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0,   /*!< DIS : Disables Master SRAM Clock Gating                                   */
67249 } PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum;
67250 
67251 /* ==========================================  PWRCTRL SRAMCTRL SRAMCLKGATE [1..1]  ========================================== */
67252 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMCLKGATE                                              */
67253   PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN      = 1,     /*!< EN : Enable Individual SRAM Clock Gating                                  */
67254   PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS     = 0,     /*!< DIS : Disables Individual SRAM Clock Gating                               */
67255 } PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum;
67256 
67257 /* =======================================================  ADCSTATUS  ======================================================= */
67258 /* =====================================================  AUDADCSTATUS  ====================================================== */
67259 /* =======================================================  EMONCTRL  ======================================================== */
67260 /* =======================================================  EMONCFG0  ======================================================== */
67261 /* ===========================================  PWRCTRL EMONCFG0 EMONSEL0 [0..7]  ============================================ */
67262 typedef enum {                                  /*!< PWRCTRL_EMONCFG0_EMONSEL0                                                 */
67263   PWRCTRL_EMONCFG0_EMONSEL0_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
67264   PWRCTRL_EMONCFG0_EMONSEL0_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
67265   PWRCTRL_EMONCFG0_EMONSEL0_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
67266   PWRCTRL_EMONCFG0_EMONSEL0_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
67267   PWRCTRL_EMONCFG0_EMONSEL0_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
67268   PWRCTRL_EMONCFG0_EMONSEL0_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
67269   PWRCTRL_EMONCFG0_EMONSEL0_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
67270   PWRCTRL_EMONCFG0_EMONSEL0_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
67271   PWRCTRL_EMONCFG0_EMONSEL0_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
67272   PWRCTRL_EMONCFG0_EMONSEL0_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
67273   PWRCTRL_EMONCFG0_EMONSEL0_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
67274   PWRCTRL_EMONCFG0_EMONSEL0_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
67275   PWRCTRL_EMONCFG0_EMONSEL0_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
67276   PWRCTRL_EMONCFG0_EMONSEL0_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
67277   PWRCTRL_EMONCFG0_EMONSEL0_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
67278   PWRCTRL_EMONCFG0_EMONSEL0_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
67279   PWRCTRL_EMONCFG0_EMONSEL0_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
67280   PWRCTRL_EMONCFG0_EMONSEL0_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
67281   PWRCTRL_EMONCFG0_EMONSEL0_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
67282   PWRCTRL_EMONCFG0_EMONSEL0_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
67283   PWRCTRL_EMONCFG0_EMONSEL0_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
67284   PWRCTRL_EMONCFG0_EMONSEL0_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
67285   PWRCTRL_EMONCFG0_EMONSEL0_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
67286   PWRCTRL_EMONCFG0_EMONSEL0_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
67287   PWRCTRL_EMONCFG0_EMONSEL0_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
67288   PWRCTRL_EMONCFG0_EMONSEL0_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
67289   PWRCTRL_EMONCFG0_EMONSEL0_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
67290   PWRCTRL_EMONCFG0_EMONSEL0_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
67291   PWRCTRL_EMONCFG0_EMONSEL0_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
67292   PWRCTRL_EMONCFG0_EMONSEL0_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
67293   PWRCTRL_EMONCFG0_EMONSEL0_I3C0ON     = 30,    /*!< I3C0ON : Increment the counter when I3C0 is powered on                    */
67294   PWRCTRL_EMONCFG0_EMONSEL0_I3C1ON     = 31,    /*!< I3C1ON : Increment the counter when I3C1 is powered on                    */
67295   PWRCTRL_EMONCFG0_EMONSEL0_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
67296   PWRCTRL_EMONCFG0_EMONSEL0_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
67297   PWRCTRL_EMONCFG0_EMONSEL0_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
67298   PWRCTRL_EMONCFG0_EMONSEL0_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
67299   PWRCTRL_EMONCFG0_EMONSEL0_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
67300   PWRCTRL_EMONCFG0_EMONSEL0_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
67301   PWRCTRL_EMONCFG0_EMONSEL0_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
67302   PWRCTRL_EMONCFG0_EMONSEL0_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
67303   PWRCTRL_EMONCFG0_EMONSEL0_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
67304   PWRCTRL_EMONCFG0_EMONSEL0_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
67305   PWRCTRL_EMONCFG0_EMONSEL0_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
67306 } PWRCTRL_EMONCFG0_EMONSEL0_Enum;
67307 
67308 /* =======================================================  EMONCFG1  ======================================================== */
67309 /* ===========================================  PWRCTRL EMONCFG1 EMONSEL1 [0..7]  ============================================ */
67310 typedef enum {                                  /*!< PWRCTRL_EMONCFG1_EMONSEL1                                                 */
67311   PWRCTRL_EMONCFG1_EMONSEL1_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
67312   PWRCTRL_EMONCFG1_EMONSEL1_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
67313   PWRCTRL_EMONCFG1_EMONSEL1_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
67314   PWRCTRL_EMONCFG1_EMONSEL1_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
67315   PWRCTRL_EMONCFG1_EMONSEL1_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
67316   PWRCTRL_EMONCFG1_EMONSEL1_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
67317   PWRCTRL_EMONCFG1_EMONSEL1_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
67318   PWRCTRL_EMONCFG1_EMONSEL1_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
67319   PWRCTRL_EMONCFG1_EMONSEL1_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
67320   PWRCTRL_EMONCFG1_EMONSEL1_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
67321   PWRCTRL_EMONCFG1_EMONSEL1_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
67322   PWRCTRL_EMONCFG1_EMONSEL1_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
67323   PWRCTRL_EMONCFG1_EMONSEL1_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
67324   PWRCTRL_EMONCFG1_EMONSEL1_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
67325   PWRCTRL_EMONCFG1_EMONSEL1_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
67326   PWRCTRL_EMONCFG1_EMONSEL1_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
67327   PWRCTRL_EMONCFG1_EMONSEL1_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
67328   PWRCTRL_EMONCFG1_EMONSEL1_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
67329   PWRCTRL_EMONCFG1_EMONSEL1_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
67330   PWRCTRL_EMONCFG1_EMONSEL1_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
67331   PWRCTRL_EMONCFG1_EMONSEL1_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
67332   PWRCTRL_EMONCFG1_EMONSEL1_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
67333   PWRCTRL_EMONCFG1_EMONSEL1_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
67334   PWRCTRL_EMONCFG1_EMONSEL1_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
67335   PWRCTRL_EMONCFG1_EMONSEL1_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
67336   PWRCTRL_EMONCFG1_EMONSEL1_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
67337   PWRCTRL_EMONCFG1_EMONSEL1_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
67338   PWRCTRL_EMONCFG1_EMONSEL1_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
67339   PWRCTRL_EMONCFG1_EMONSEL1_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
67340   PWRCTRL_EMONCFG1_EMONSEL1_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
67341   PWRCTRL_EMONCFG1_EMONSEL1_I3C0ON     = 30,    /*!< I3C0ON : Increment the counter when I3C0 is powered on                    */
67342   PWRCTRL_EMONCFG1_EMONSEL1_I3C1ON     = 31,    /*!< I3C1ON : Increment the counter when I3C1 is powered on                    */
67343   PWRCTRL_EMONCFG1_EMONSEL1_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
67344   PWRCTRL_EMONCFG1_EMONSEL1_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
67345   PWRCTRL_EMONCFG1_EMONSEL1_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
67346   PWRCTRL_EMONCFG1_EMONSEL1_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
67347   PWRCTRL_EMONCFG1_EMONSEL1_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
67348   PWRCTRL_EMONCFG1_EMONSEL1_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
67349   PWRCTRL_EMONCFG1_EMONSEL1_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
67350   PWRCTRL_EMONCFG1_EMONSEL1_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
67351   PWRCTRL_EMONCFG1_EMONSEL1_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
67352   PWRCTRL_EMONCFG1_EMONSEL1_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
67353   PWRCTRL_EMONCFG1_EMONSEL1_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
67354 } PWRCTRL_EMONCFG1_EMONSEL1_Enum;
67355 
67356 /* =======================================================  EMONCFG2  ======================================================== */
67357 /* ===========================================  PWRCTRL EMONCFG2 EMONSEL2 [0..7]  ============================================ */
67358 typedef enum {                                  /*!< PWRCTRL_EMONCFG2_EMONSEL2                                                 */
67359   PWRCTRL_EMONCFG2_EMONSEL2_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
67360   PWRCTRL_EMONCFG2_EMONSEL2_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
67361   PWRCTRL_EMONCFG2_EMONSEL2_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
67362   PWRCTRL_EMONCFG2_EMONSEL2_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
67363   PWRCTRL_EMONCFG2_EMONSEL2_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
67364   PWRCTRL_EMONCFG2_EMONSEL2_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
67365   PWRCTRL_EMONCFG2_EMONSEL2_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
67366   PWRCTRL_EMONCFG2_EMONSEL2_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
67367   PWRCTRL_EMONCFG2_EMONSEL2_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
67368   PWRCTRL_EMONCFG2_EMONSEL2_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
67369   PWRCTRL_EMONCFG2_EMONSEL2_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
67370   PWRCTRL_EMONCFG2_EMONSEL2_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
67371   PWRCTRL_EMONCFG2_EMONSEL2_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
67372   PWRCTRL_EMONCFG2_EMONSEL2_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
67373   PWRCTRL_EMONCFG2_EMONSEL2_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
67374   PWRCTRL_EMONCFG2_EMONSEL2_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
67375   PWRCTRL_EMONCFG2_EMONSEL2_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
67376   PWRCTRL_EMONCFG2_EMONSEL2_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
67377   PWRCTRL_EMONCFG2_EMONSEL2_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
67378   PWRCTRL_EMONCFG2_EMONSEL2_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
67379   PWRCTRL_EMONCFG2_EMONSEL2_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
67380   PWRCTRL_EMONCFG2_EMONSEL2_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
67381   PWRCTRL_EMONCFG2_EMONSEL2_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
67382   PWRCTRL_EMONCFG2_EMONSEL2_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
67383   PWRCTRL_EMONCFG2_EMONSEL2_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
67384   PWRCTRL_EMONCFG2_EMONSEL2_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
67385   PWRCTRL_EMONCFG2_EMONSEL2_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
67386   PWRCTRL_EMONCFG2_EMONSEL2_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
67387   PWRCTRL_EMONCFG2_EMONSEL2_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
67388   PWRCTRL_EMONCFG2_EMONSEL2_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
67389   PWRCTRL_EMONCFG2_EMONSEL2_I3C0ON     = 30,    /*!< I3C0ON : Increment the counter when I3C0 is powered on                    */
67390   PWRCTRL_EMONCFG2_EMONSEL2_I3C1ON     = 31,    /*!< I3C1ON : Increment the counter when I3C1 is powered on                    */
67391   PWRCTRL_EMONCFG2_EMONSEL2_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
67392   PWRCTRL_EMONCFG2_EMONSEL2_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
67393   PWRCTRL_EMONCFG2_EMONSEL2_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
67394   PWRCTRL_EMONCFG2_EMONSEL2_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
67395   PWRCTRL_EMONCFG2_EMONSEL2_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
67396   PWRCTRL_EMONCFG2_EMONSEL2_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
67397   PWRCTRL_EMONCFG2_EMONSEL2_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
67398   PWRCTRL_EMONCFG2_EMONSEL2_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
67399   PWRCTRL_EMONCFG2_EMONSEL2_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
67400   PWRCTRL_EMONCFG2_EMONSEL2_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
67401   PWRCTRL_EMONCFG2_EMONSEL2_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
67402 } PWRCTRL_EMONCFG2_EMONSEL2_Enum;
67403 
67404 /* =======================================================  EMONCFG3  ======================================================== */
67405 /* ===========================================  PWRCTRL EMONCFG3 EMONSEL3 [0..7]  ============================================ */
67406 typedef enum {                                  /*!< PWRCTRL_EMONCFG3_EMONSEL3                                                 */
67407   PWRCTRL_EMONCFG3_EMONSEL3_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
67408   PWRCTRL_EMONCFG3_EMONSEL3_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
67409   PWRCTRL_EMONCFG3_EMONSEL3_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
67410   PWRCTRL_EMONCFG3_EMONSEL3_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
67411   PWRCTRL_EMONCFG3_EMONSEL3_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
67412   PWRCTRL_EMONCFG3_EMONSEL3_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
67413   PWRCTRL_EMONCFG3_EMONSEL3_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
67414   PWRCTRL_EMONCFG3_EMONSEL3_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
67415   PWRCTRL_EMONCFG3_EMONSEL3_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
67416   PWRCTRL_EMONCFG3_EMONSEL3_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
67417   PWRCTRL_EMONCFG3_EMONSEL3_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
67418   PWRCTRL_EMONCFG3_EMONSEL3_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
67419   PWRCTRL_EMONCFG3_EMONSEL3_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
67420   PWRCTRL_EMONCFG3_EMONSEL3_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
67421   PWRCTRL_EMONCFG3_EMONSEL3_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
67422   PWRCTRL_EMONCFG3_EMONSEL3_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
67423   PWRCTRL_EMONCFG3_EMONSEL3_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
67424   PWRCTRL_EMONCFG3_EMONSEL3_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
67425   PWRCTRL_EMONCFG3_EMONSEL3_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
67426   PWRCTRL_EMONCFG3_EMONSEL3_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
67427   PWRCTRL_EMONCFG3_EMONSEL3_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
67428   PWRCTRL_EMONCFG3_EMONSEL3_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
67429   PWRCTRL_EMONCFG3_EMONSEL3_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
67430   PWRCTRL_EMONCFG3_EMONSEL3_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
67431   PWRCTRL_EMONCFG3_EMONSEL3_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
67432   PWRCTRL_EMONCFG3_EMONSEL3_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
67433   PWRCTRL_EMONCFG3_EMONSEL3_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
67434   PWRCTRL_EMONCFG3_EMONSEL3_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
67435   PWRCTRL_EMONCFG3_EMONSEL3_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
67436   PWRCTRL_EMONCFG3_EMONSEL3_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
67437   PWRCTRL_EMONCFG3_EMONSEL3_I3C0ON     = 30,    /*!< I3C0ON : Increment the counter when I3C0 is powered on                    */
67438   PWRCTRL_EMONCFG3_EMONSEL3_I3C1ON     = 31,    /*!< I3C1ON : Increment the counter when I3C1 is powered on                    */
67439   PWRCTRL_EMONCFG3_EMONSEL3_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
67440   PWRCTRL_EMONCFG3_EMONSEL3_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
67441   PWRCTRL_EMONCFG3_EMONSEL3_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
67442   PWRCTRL_EMONCFG3_EMONSEL3_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
67443   PWRCTRL_EMONCFG3_EMONSEL3_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
67444   PWRCTRL_EMONCFG3_EMONSEL3_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
67445   PWRCTRL_EMONCFG3_EMONSEL3_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
67446   PWRCTRL_EMONCFG3_EMONSEL3_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
67447   PWRCTRL_EMONCFG3_EMONSEL3_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
67448   PWRCTRL_EMONCFG3_EMONSEL3_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
67449   PWRCTRL_EMONCFG3_EMONSEL3_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
67450 } PWRCTRL_EMONCFG3_EMONSEL3_Enum;
67451 
67452 /* =======================================================  EMONCFG4  ======================================================== */
67453 /* ===========================================  PWRCTRL EMONCFG4 EMONSEL4 [0..7]  ============================================ */
67454 typedef enum {                                  /*!< PWRCTRL_EMONCFG4_EMONSEL4                                                 */
67455   PWRCTRL_EMONCFG4_EMONSEL4_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
67456   PWRCTRL_EMONCFG4_EMONSEL4_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
67457   PWRCTRL_EMONCFG4_EMONSEL4_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
67458   PWRCTRL_EMONCFG4_EMONSEL4_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
67459   PWRCTRL_EMONCFG4_EMONSEL4_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
67460   PWRCTRL_EMONCFG4_EMONSEL4_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
67461   PWRCTRL_EMONCFG4_EMONSEL4_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
67462   PWRCTRL_EMONCFG4_EMONSEL4_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
67463   PWRCTRL_EMONCFG4_EMONSEL4_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
67464   PWRCTRL_EMONCFG4_EMONSEL4_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
67465   PWRCTRL_EMONCFG4_EMONSEL4_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
67466   PWRCTRL_EMONCFG4_EMONSEL4_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
67467   PWRCTRL_EMONCFG4_EMONSEL4_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
67468   PWRCTRL_EMONCFG4_EMONSEL4_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
67469   PWRCTRL_EMONCFG4_EMONSEL4_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
67470   PWRCTRL_EMONCFG4_EMONSEL4_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
67471   PWRCTRL_EMONCFG4_EMONSEL4_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
67472   PWRCTRL_EMONCFG4_EMONSEL4_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
67473   PWRCTRL_EMONCFG4_EMONSEL4_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
67474   PWRCTRL_EMONCFG4_EMONSEL4_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
67475   PWRCTRL_EMONCFG4_EMONSEL4_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
67476   PWRCTRL_EMONCFG4_EMONSEL4_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
67477   PWRCTRL_EMONCFG4_EMONSEL4_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
67478   PWRCTRL_EMONCFG4_EMONSEL4_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
67479   PWRCTRL_EMONCFG4_EMONSEL4_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
67480   PWRCTRL_EMONCFG4_EMONSEL4_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
67481   PWRCTRL_EMONCFG4_EMONSEL4_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
67482   PWRCTRL_EMONCFG4_EMONSEL4_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
67483   PWRCTRL_EMONCFG4_EMONSEL4_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
67484   PWRCTRL_EMONCFG4_EMONSEL4_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
67485   PWRCTRL_EMONCFG4_EMONSEL4_I3C0ON     = 30,    /*!< I3C0ON : Increment the counter when I3C0 is powered on                    */
67486   PWRCTRL_EMONCFG4_EMONSEL4_I3C1ON     = 31,    /*!< I3C1ON : Increment the counter when I3C1 is powered on                    */
67487   PWRCTRL_EMONCFG4_EMONSEL4_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
67488   PWRCTRL_EMONCFG4_EMONSEL4_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
67489   PWRCTRL_EMONCFG4_EMONSEL4_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
67490   PWRCTRL_EMONCFG4_EMONSEL4_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
67491   PWRCTRL_EMONCFG4_EMONSEL4_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
67492   PWRCTRL_EMONCFG4_EMONSEL4_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
67493   PWRCTRL_EMONCFG4_EMONSEL4_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
67494   PWRCTRL_EMONCFG4_EMONSEL4_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
67495   PWRCTRL_EMONCFG4_EMONSEL4_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
67496   PWRCTRL_EMONCFG4_EMONSEL4_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
67497   PWRCTRL_EMONCFG4_EMONSEL4_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
67498 } PWRCTRL_EMONCFG4_EMONSEL4_Enum;
67499 
67500 /* =======================================================  EMONCFG5  ======================================================== */
67501 /* ===========================================  PWRCTRL EMONCFG5 EMONSEL5 [0..7]  ============================================ */
67502 typedef enum {                                  /*!< PWRCTRL_EMONCFG5_EMONSEL5                                                 */
67503   PWRCTRL_EMONCFG5_EMONSEL5_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
67504   PWRCTRL_EMONCFG5_EMONSEL5_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
67505   PWRCTRL_EMONCFG5_EMONSEL5_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
67506   PWRCTRL_EMONCFG5_EMONSEL5_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
67507   PWRCTRL_EMONCFG5_EMONSEL5_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
67508   PWRCTRL_EMONCFG5_EMONSEL5_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
67509   PWRCTRL_EMONCFG5_EMONSEL5_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
67510   PWRCTRL_EMONCFG5_EMONSEL5_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
67511   PWRCTRL_EMONCFG5_EMONSEL5_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
67512   PWRCTRL_EMONCFG5_EMONSEL5_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
67513   PWRCTRL_EMONCFG5_EMONSEL5_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
67514   PWRCTRL_EMONCFG5_EMONSEL5_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
67515   PWRCTRL_EMONCFG5_EMONSEL5_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
67516   PWRCTRL_EMONCFG5_EMONSEL5_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
67517   PWRCTRL_EMONCFG5_EMONSEL5_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
67518   PWRCTRL_EMONCFG5_EMONSEL5_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
67519   PWRCTRL_EMONCFG5_EMONSEL5_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
67520   PWRCTRL_EMONCFG5_EMONSEL5_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
67521   PWRCTRL_EMONCFG5_EMONSEL5_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
67522   PWRCTRL_EMONCFG5_EMONSEL5_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
67523   PWRCTRL_EMONCFG5_EMONSEL5_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
67524   PWRCTRL_EMONCFG5_EMONSEL5_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
67525   PWRCTRL_EMONCFG5_EMONSEL5_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
67526   PWRCTRL_EMONCFG5_EMONSEL5_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
67527   PWRCTRL_EMONCFG5_EMONSEL5_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
67528   PWRCTRL_EMONCFG5_EMONSEL5_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
67529   PWRCTRL_EMONCFG5_EMONSEL5_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
67530   PWRCTRL_EMONCFG5_EMONSEL5_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
67531   PWRCTRL_EMONCFG5_EMONSEL5_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
67532   PWRCTRL_EMONCFG5_EMONSEL5_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
67533   PWRCTRL_EMONCFG5_EMONSEL5_I3C0ON     = 30,    /*!< I3C0ON : Increment the counter when I3C0 is powered on                    */
67534   PWRCTRL_EMONCFG5_EMONSEL5_I3C1ON     = 31,    /*!< I3C1ON : Increment the counter when I3C1 is powered on                    */
67535   PWRCTRL_EMONCFG5_EMONSEL5_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
67536   PWRCTRL_EMONCFG5_EMONSEL5_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
67537   PWRCTRL_EMONCFG5_EMONSEL5_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
67538   PWRCTRL_EMONCFG5_EMONSEL5_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
67539   PWRCTRL_EMONCFG5_EMONSEL5_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
67540   PWRCTRL_EMONCFG5_EMONSEL5_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
67541   PWRCTRL_EMONCFG5_EMONSEL5_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
67542   PWRCTRL_EMONCFG5_EMONSEL5_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
67543   PWRCTRL_EMONCFG5_EMONSEL5_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
67544   PWRCTRL_EMONCFG5_EMONSEL5_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
67545   PWRCTRL_EMONCFG5_EMONSEL5_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
67546 } PWRCTRL_EMONCFG5_EMONSEL5_Enum;
67547 
67548 /* =======================================================  EMONCFG6  ======================================================== */
67549 /* ===========================================  PWRCTRL EMONCFG6 EMONSEL6 [0..7]  ============================================ */
67550 typedef enum {                                  /*!< PWRCTRL_EMONCFG6_EMONSEL6                                                 */
67551   PWRCTRL_EMONCFG6_EMONSEL6_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
67552   PWRCTRL_EMONCFG6_EMONSEL6_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
67553   PWRCTRL_EMONCFG6_EMONSEL6_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
67554   PWRCTRL_EMONCFG6_EMONSEL6_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
67555   PWRCTRL_EMONCFG6_EMONSEL6_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
67556   PWRCTRL_EMONCFG6_EMONSEL6_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
67557   PWRCTRL_EMONCFG6_EMONSEL6_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
67558   PWRCTRL_EMONCFG6_EMONSEL6_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
67559   PWRCTRL_EMONCFG6_EMONSEL6_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
67560   PWRCTRL_EMONCFG6_EMONSEL6_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
67561   PWRCTRL_EMONCFG6_EMONSEL6_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
67562   PWRCTRL_EMONCFG6_EMONSEL6_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
67563   PWRCTRL_EMONCFG6_EMONSEL6_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
67564   PWRCTRL_EMONCFG6_EMONSEL6_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
67565   PWRCTRL_EMONCFG6_EMONSEL6_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
67566   PWRCTRL_EMONCFG6_EMONSEL6_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
67567   PWRCTRL_EMONCFG6_EMONSEL6_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
67568   PWRCTRL_EMONCFG6_EMONSEL6_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
67569   PWRCTRL_EMONCFG6_EMONSEL6_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
67570   PWRCTRL_EMONCFG6_EMONSEL6_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
67571   PWRCTRL_EMONCFG6_EMONSEL6_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
67572   PWRCTRL_EMONCFG6_EMONSEL6_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
67573   PWRCTRL_EMONCFG6_EMONSEL6_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
67574   PWRCTRL_EMONCFG6_EMONSEL6_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
67575   PWRCTRL_EMONCFG6_EMONSEL6_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
67576   PWRCTRL_EMONCFG6_EMONSEL6_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
67577   PWRCTRL_EMONCFG6_EMONSEL6_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
67578   PWRCTRL_EMONCFG6_EMONSEL6_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
67579   PWRCTRL_EMONCFG6_EMONSEL6_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
67580   PWRCTRL_EMONCFG6_EMONSEL6_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
67581   PWRCTRL_EMONCFG6_EMONSEL6_I3C0ON     = 30,    /*!< I3C0ON : Increment the counter when I3C0 is powered on                    */
67582   PWRCTRL_EMONCFG6_EMONSEL6_I3C1ON     = 31,    /*!< I3C1ON : Increment the counter when I3C1 is powered on                    */
67583   PWRCTRL_EMONCFG6_EMONSEL6_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
67584   PWRCTRL_EMONCFG6_EMONSEL6_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
67585   PWRCTRL_EMONCFG6_EMONSEL6_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
67586   PWRCTRL_EMONCFG6_EMONSEL6_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
67587   PWRCTRL_EMONCFG6_EMONSEL6_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
67588   PWRCTRL_EMONCFG6_EMONSEL6_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
67589   PWRCTRL_EMONCFG6_EMONSEL6_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
67590   PWRCTRL_EMONCFG6_EMONSEL6_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
67591   PWRCTRL_EMONCFG6_EMONSEL6_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
67592   PWRCTRL_EMONCFG6_EMONSEL6_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
67593   PWRCTRL_EMONCFG6_EMONSEL6_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
67594 } PWRCTRL_EMONCFG6_EMONSEL6_Enum;
67595 
67596 /* =======================================================  EMONCFG7  ======================================================== */
67597 /* ===========================================  PWRCTRL EMONCFG7 EMONSEL7 [0..7]  ============================================ */
67598 typedef enum {                                  /*!< PWRCTRL_EMONCFG7_EMONSEL7                                                 */
67599   PWRCTRL_EMONCFG7_EMONSEL7_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
67600   PWRCTRL_EMONCFG7_EMONSEL7_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
67601   PWRCTRL_EMONCFG7_EMONSEL7_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
67602   PWRCTRL_EMONCFG7_EMONSEL7_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
67603   PWRCTRL_EMONCFG7_EMONSEL7_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
67604   PWRCTRL_EMONCFG7_EMONSEL7_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
67605   PWRCTRL_EMONCFG7_EMONSEL7_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
67606   PWRCTRL_EMONCFG7_EMONSEL7_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
67607   PWRCTRL_EMONCFG7_EMONSEL7_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
67608   PWRCTRL_EMONCFG7_EMONSEL7_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
67609   PWRCTRL_EMONCFG7_EMONSEL7_I2S1ON     = 10,    /*!< I2S1ON : Increment the counter when I2S1 is powered on                    */
67610   PWRCTRL_EMONCFG7_EMONSEL7_PDM0ON     = 11,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
67611   PWRCTRL_EMONCFG7_EMONSEL7_PDM1ON     = 12,    /*!< PDM1ON : Increment the counter when PDM1 is powered on                    */
67612   PWRCTRL_EMONCFG7_EMONSEL7_PDM2ON     = 13,    /*!< PDM2ON : Increment the counter when PDM2 is powered on                    */
67613   PWRCTRL_EMONCFG7_EMONSEL7_PDM3ON     = 14,    /*!< PDM3ON : Increment the counter when PDM3 is powered on                    */
67614   PWRCTRL_EMONCFG7_EMONSEL7_AUDADCON   = 15,    /*!< AUDADCON : Increment the counter when AUDADC is powered on                */
67615   PWRCTRL_EMONCFG7_EMONSEL7_CRYPTOON   = 16,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
67616   PWRCTRL_EMONCFG7_EMONSEL7_DBGON      = 17,    /*!< DBGON : Increment the counter when DBG is powered on                      */
67617   PWRCTRL_EMONCFG7_EMONSEL7_DISPON     = 18,    /*!< DISPON : Increment the counter when DISP is powered on                    */
67618   PWRCTRL_EMONCFG7_EMONSEL7_DISPPHYON  = 19,    /*!< DISPPHYON : Increment the counter when DISPPHY is powered on              */
67619   PWRCTRL_EMONCFG7_EMONSEL7_DSPAON     = 20,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
67620   PWRCTRL_EMONCFG7_EMONSEL7_GFXON      = 21,    /*!< GFXON : Increment the counter when GFX is powered on                      */
67621   PWRCTRL_EMONCFG7_EMONSEL7_UART0ON    = 22,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
67622   PWRCTRL_EMONCFG7_EMONSEL7_UART1ON    = 23,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
67623   PWRCTRL_EMONCFG7_EMONSEL7_UART2ON    = 24,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
67624   PWRCTRL_EMONCFG7_EMONSEL7_UART3ON    = 25,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
67625   PWRCTRL_EMONCFG7_EMONSEL7_IOM0ON     = 26,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
67626   PWRCTRL_EMONCFG7_EMONSEL7_IOM1ON     = 27,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
67627   PWRCTRL_EMONCFG7_EMONSEL7_IOM2ON     = 28,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
67628   PWRCTRL_EMONCFG7_EMONSEL7_IOM3ON     = 29,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
67629   PWRCTRL_EMONCFG7_EMONSEL7_I3C0ON     = 30,    /*!< I3C0ON : Increment the counter when I3C0 is powered on                    */
67630   PWRCTRL_EMONCFG7_EMONSEL7_I3C1ON     = 31,    /*!< I3C1ON : Increment the counter when I3C1 is powered on                    */
67631   PWRCTRL_EMONCFG7_EMONSEL7_IOM4ON     = 32,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
67632   PWRCTRL_EMONCFG7_EMONSEL7_IOM5ON     = 33,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
67633   PWRCTRL_EMONCFG7_EMONSEL7_IOM6ON     = 34,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
67634   PWRCTRL_EMONCFG7_EMONSEL7_IOM7ON     = 35,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
67635   PWRCTRL_EMONCFG7_EMONSEL7_IOSON      = 36,    /*!< IOSON : Increment the counter when IOS is powered on                      */
67636   PWRCTRL_EMONCFG7_EMONSEL7_MSPI0ON    = 37,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
67637   PWRCTRL_EMONCFG7_EMONSEL7_MSPI1ON    = 38,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
67638   PWRCTRL_EMONCFG7_EMONSEL7_MSPI2ON    = 39,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
67639   PWRCTRL_EMONCFG7_EMONSEL7_SDIOON     = 40,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
67640   PWRCTRL_EMONCFG7_EMONSEL7_USBON      = 41,    /*!< USBON : Increment the counter when USB is powered on                      */
67641   PWRCTRL_EMONCFG7_EMONSEL7_USBPHYON   = 42,    /*!< USBPHYON : Increment the counter when USBPHY is powered on                */
67642 } PWRCTRL_EMONCFG7_EMONSEL7_Enum;
67643 
67644 /* ======================================================  EMONCOUNT0  ======================================================= */
67645 /* ======================================================  EMONCOUNT1  ======================================================= */
67646 /* ======================================================  EMONCOUNT2  ======================================================= */
67647 /* ======================================================  EMONCOUNT3  ======================================================= */
67648 /* ======================================================  EMONCOUNT4  ======================================================= */
67649 /* ======================================================  EMONCOUNT5  ======================================================= */
67650 /* ======================================================  EMONCOUNT6  ======================================================= */
67651 /* ======================================================  EMONCOUNT7  ======================================================= */
67652 /* ======================================================  EMONSTATUS  ======================================================= */
67653 
67654 
67655 /* =========================================================================================================================== */
67656 /* ================                                          RSTGEN                                           ================ */
67657 /* =========================================================================================================================== */
67658 
67659 /* ==========================================================  CFG  ========================================================== */
67660 /* =========================================================  SWPOI  ========================================================= */
67661 /* =============================================  RSTGEN SWPOI SWPOIKEY [0..7]  ============================================== */
67662 typedef enum {                                  /*!< RSTGEN_SWPOI_SWPOIKEY                                                     */
67663   RSTGEN_SWPOI_SWPOIKEY_KEYVALUE       = 27,    /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset.         */
67664   RSTGEN_SWPOI_SWPOIKEY_DEFAULT        = 0,     /*!< DEFAULT : Default value.                                                  */
67665 } RSTGEN_SWPOI_SWPOIKEY_Enum;
67666 
67667 /* =========================================================  SWPOR  ========================================================= */
67668 /* =============================================  RSTGEN SWPOR SWPORKEY [0..7]  ============================================== */
67669 typedef enum {                                  /*!< RSTGEN_SWPOR_SWPORKEY                                                     */
67670   RSTGEN_SWPOR_SWPORKEY_KEYVALUE       = 212,   /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset.         */
67671   RSTGEN_SWPOR_SWPORKEY_DEFAULT        = 0,     /*!< DEFAULT : Default value.                                                  */
67672 } RSTGEN_SWPOR_SWPORKEY_Enum;
67673 
67674 /* =======================================================  SIMOBODM  ======================================================== */
67675 /* ===========================================  RSTGEN SIMOBODM DIGBOECLV [3..3]  ============================================ */
67676 typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOECLV                                                 */
67677   RSTGEN_SIMOBODM_DIGBOECLV_BOM        = 0,     /*!< BOM : Mask the VDDC_LV digital brownout detection into the interrupt
67678                                                      block.                                                                    */
67679   RSTGEN_SIMOBODM_DIGBOECLV_BOE        = 1,     /*!< BOE : Enable brown VDDC_LV digital brownout detection into the
67680                                                      interrupt block.                                                          */
67681 } RSTGEN_SIMOBODM_DIGBOECLV_Enum;
67682 
67683 /* ============================================  RSTGEN SIMOBODM DIGBOES [2..2]  ============================================= */
67684 typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOES                                                   */
67685   RSTGEN_SIMOBODM_DIGBOES_BOM          = 0,     /*!< BOM : Mask the VDDS digital brownout detection into the interrupt
67686                                                      block.                                                                    */
67687   RSTGEN_SIMOBODM_DIGBOES_BOE          = 1,     /*!< BOE : Enable the VDDS digital brownout detection into the interrupt
67688                                                      block.                                                                    */
67689 } RSTGEN_SIMOBODM_DIGBOES_Enum;
67690 
67691 /* ============================================  RSTGEN SIMOBODM DIGBOEF [1..1]  ============================================= */
67692 typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOEF                                                   */
67693   RSTGEN_SIMOBODM_DIGBOEF_BOM          = 0,     /*!< BOM : Mask the VDDF digital brownout detection into the interrupt
67694                                                      block.                                                                    */
67695   RSTGEN_SIMOBODM_DIGBOEF_BOE          = 1,     /*!< BOE : Enable the VDDF digital brownout detection into the interrupt
67696                                                      block.                                                                    */
67697 } RSTGEN_SIMOBODM_DIGBOEF_Enum;
67698 
67699 /* ============================================  RSTGEN SIMOBODM DIGBOEC [0..0]  ============================================= */
67700 typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOEC                                                   */
67701   RSTGEN_SIMOBODM_DIGBOEC_BOA          = 0,     /*!< BOA : Enable brown out detection for VDDF using the analog method.        */
67702   RSTGEN_SIMOBODM_DIGBOEC_BOD          = 1,     /*!< BOD : Enable brown out detection for VDDF using the digital
67703                                                      method.                                                                   */
67704 } RSTGEN_SIMOBODM_DIGBOEC_Enum;
67705 
67706 /* =========================================================  INTEN  ========================================================= */
67707 /* ========================================================  INTSTAT  ======================================================== */
67708 /* ========================================================  INTCLR  ========================================================= */
67709 /* ========================================================  INTSET  ========================================================= */
67710 /* =========================================================  STAT  ========================================================== */
67711 
67712 
67713 /* =========================================================================================================================== */
67714 /* ================                                            RTC                                            ================ */
67715 /* =========================================================================================================================== */
67716 
67717 /* ========================================================  RTCCTL  ========================================================= */
67718 /* ===============================================  RTC RTCCTL HR1224 [5..5]  ================================================ */
67719 typedef enum {                                  /*!< RTC_RTCCTL_HR1224                                                         */
67720   RTC_RTCCTL_HR1224_24HR               = 0,     /*!< 24HR : Hours in 24 hour mode                                              */
67721   RTC_RTCCTL_HR1224_DISABLED           = 1,     /*!< DISABLED : Disable the 24 hour mode                                       */
67722 } RTC_RTCCTL_HR1224_Enum;
67723 
67724 /* ================================================  RTC RTCCTL RSTOP [4..4]  ================================================ */
67725 typedef enum {                                  /*!< RTC_RTCCTL_RSTOP                                                          */
67726   RTC_RTCCTL_RSTOP_RUN                 = 0,     /*!< RUN : Allow the RTC input clock to run                                    */
67727   RTC_RTCCTL_RSTOP_STOP                = 1,     /*!< STOP : Stop the RTC input clock                                           */
67728 } RTC_RTCCTL_RSTOP_Enum;
67729 
67730 /* =================================================  RTC RTCCTL RPT [1..3]  ================================================= */
67731 typedef enum {                                  /*!< RTC_RTCCTL_RPT                                                            */
67732   RTC_RTCCTL_RPT_DIS                   = 0,     /*!< DIS : Alarm interrupt disabled                                            */
67733   RTC_RTCCTL_RPT_YEAR                  = 1,     /*!< YEAR : Interrupt every year                                               */
67734   RTC_RTCCTL_RPT_MONTH                 = 2,     /*!< MONTH : Interrupt every month                                             */
67735   RTC_RTCCTL_RPT_WEEK                  = 3,     /*!< WEEK : Interrupt every week                                               */
67736   RTC_RTCCTL_RPT_DAY                   = 4,     /*!< DAY : Interrupt every day                                                 */
67737   RTC_RTCCTL_RPT_HR                    = 5,     /*!< HR : Interrupt every hour                                                 */
67738   RTC_RTCCTL_RPT_MIN                   = 6,     /*!< MIN : Interrupt every minute                                              */
67739   RTC_RTCCTL_RPT_SEC                   = 7,     /*!< SEC : Interrupt every second/10th/100th                                   */
67740 } RTC_RTCCTL_RPT_Enum;
67741 
67742 /* ================================================  RTC RTCCTL WRTC [0..0]  ================================================= */
67743 typedef enum {                                  /*!< RTC_RTCCTL_WRTC                                                           */
67744   RTC_RTCCTL_WRTC_DIS                  = 0,     /*!< DIS : Counter writes are disabled                                         */
67745   RTC_RTCCTL_WRTC_EN                   = 1,     /*!< EN : Counter writes are enabled                                           */
67746 } RTC_RTCCTL_WRTC_Enum;
67747 
67748 /* ========================================================  RTCSTAT  ======================================================== */
67749 /* ========================================================  CTRLOW  ========================================================= */
67750 /* =========================================================  CTRUP  ========================================================= */
67751 /* ===============================================  RTC CTRUP CTERR [31..31]  ================================================ */
67752 typedef enum {                                  /*!< RTC_CTRUP_CTERR                                                           */
67753   RTC_CTRUP_CTERR_NOERR                = 0,     /*!< NOERR : No read error occurred                                            */
67754   RTC_CTRUP_CTERR_RDERR                = 1,     /*!< RDERR : Read error occurred                                               */
67755 } RTC_CTRUP_CTERR_Enum;
67756 
67757 /* ================================================  RTC CTRUP CEB [29..29]  ================================================= */
67758 typedef enum {                                  /*!< RTC_CTRUP_CEB                                                             */
67759   RTC_CTRUP_CEB_DIS                    = 0,     /*!< DIS : Disable the Century bit from changing                               */
67760   RTC_CTRUP_CEB_EN                     = 1,     /*!< EN : Enable the Century bit to change                                     */
67761 } RTC_CTRUP_CEB_Enum;
67762 
67763 /* =================================================  RTC CTRUP CB [28..28]  ================================================= */
67764 typedef enum {                                  /*!< RTC_CTRUP_CB                                                              */
67765   RTC_CTRUP_CB_2000                    = 0,     /*!< 2000 : Century is 2000s                                                   */
67766   RTC_CTRUP_CB_1900_2100               = 1,     /*!< 1900_2100 : Century is 1900s/2100s                                        */
67767 } RTC_CTRUP_CB_Enum;
67768 
67769 /* ========================================================  ALMLOW  ========================================================= */
67770 /* =========================================================  ALMUP  ========================================================= */
67771 /* =========================================================  INTEN  ========================================================= */
67772 /* ========================================================  INTSTAT  ======================================================== */
67773 /* ========================================================  INTCLR  ========================================================= */
67774 /* ========================================================  INTSET  ========================================================= */
67775 
67776 
67777 /* =========================================================================================================================== */
67778 /* ================                                           SDIO                                            ================ */
67779 /* =========================================================================================================================== */
67780 
67781 /* =========================================================  SDMA  ========================================================== */
67782 /* =========================================================  BLOCK  ========================================================= */
67783 /* ==============================================  SDIO BLOCK BLKCNT [16..31]  =============================================== */
67784 typedef enum {                                  /*!< SDIO_BLOCK_BLKCNT                                                         */
67785   SDIO_BLOCK_BLKCNT_STOPCNT            = 0,     /*!< STOPCNT : Stop Count                                                      */
67786   SDIO_BLOCK_BLKCNT_1BLOCK             = 1,     /*!< 1BLOCK : 1 block                                                          */
67787   SDIO_BLOCK_BLKCNT_2BLOCKS            = 2,     /*!< 2BLOCKS : 2 blocks (and so on from 1-65535)                               */
67788   SDIO_BLOCK_BLKCNT_65535BLOCKS        = 65535, /*!< 65535BLOCKS : 65535 blocks                                                */
67789 } SDIO_BLOCK_BLKCNT_Enum;
67790 
67791 /* ===========================================  SDIO BLOCK HOSTSDMABUFSZ [12..14]  =========================================== */
67792 typedef enum {                                  /*!< SDIO_BLOCK_HOSTSDMABUFSZ                                                  */
67793   SDIO_BLOCK_HOSTSDMABUFSZ_4KB         = 0,     /*!< 4KB : 4KB(Detects A11 Carry out)                                          */
67794   SDIO_BLOCK_HOSTSDMABUFSZ_8KB         = 1,     /*!< 8KB : 8KB(Detects A12 Carry out)                                          */
67795   SDIO_BLOCK_HOSTSDMABUFSZ_16KB        = 2,     /*!< 16KB : 16KB(Detects A13 Carry out)                                        */
67796   SDIO_BLOCK_HOSTSDMABUFSZ_32KB        = 3,     /*!< 32KB : 32KB(Detects A14 Carry out)                                        */
67797   SDIO_BLOCK_HOSTSDMABUFSZ_64KB        = 4,     /*!< 64KB : 64KB(Detects A15 Carry out)                                        */
67798   SDIO_BLOCK_HOSTSDMABUFSZ_128KB       = 5,     /*!< 128KB : 128KB(Detects A16 Carry out)                                      */
67799   SDIO_BLOCK_HOSTSDMABUFSZ_256KB       = 6,     /*!< 256KB : 256KB(Detects A17 Carry out)                                      */
67800   SDIO_BLOCK_HOSTSDMABUFSZ_512KB       = 7,     /*!< 512KB : 512KB(Detects A18 Carry out)                                      */
67801 } SDIO_BLOCK_HOSTSDMABUFSZ_Enum;
67802 
67803 /* =========================================  SDIO BLOCK TRANSFERBLOCKSIZE [0..11]  ========================================== */
67804 typedef enum {                                  /*!< SDIO_BLOCK_TRANSFERBLOCKSIZE                                              */
67805   SDIO_BLOCK_TRANSFERBLOCKSIZE_NODATAXFER = 0,  /*!< NODATAXFER : No Data Transfer                                             */
67806   SDIO_BLOCK_TRANSFERBLOCKSIZE_1BYTE   = 1,     /*!< 1BYTE : 1 Byte                                                            */
67807   SDIO_BLOCK_TRANSFERBLOCKSIZE_2BYTES  = 2,     /*!< 2BYTES : 2 Bytes                                                          */
67808   SDIO_BLOCK_TRANSFERBLOCKSIZE_3BYTES  = 3,     /*!< 3BYTES : 3 Bytes                                                          */
67809   SDIO_BLOCK_TRANSFERBLOCKSIZE_4BYTES  = 4,     /*!< 4BYTES : 4 Bytes (and so on from 1-2048)                                  */
67810   SDIO_BLOCK_TRANSFERBLOCKSIZE_511BYTES = 511,  /*!< 511BYTES : 511 Bytes                                                      */
67811   SDIO_BLOCK_TRANSFERBLOCKSIZE_512BYTES = 512,  /*!< 512BYTES : 512 Bytes                                                      */
67812   SDIO_BLOCK_TRANSFERBLOCKSIZE_2048BYTES = 2048,/*!< 2048BYTES : 2048 Bytes                                                    */
67813 } SDIO_BLOCK_TRANSFERBLOCKSIZE_Enum;
67814 
67815 /* =======================================================  ARGUMENT1  ======================================================= */
67816 /* =======================================================  TRANSFER  ======================================================== */
67817 /* ============================================  SDIO TRANSFER CMDTYPE [22..23]  ============================================= */
67818 typedef enum {                                  /*!< SDIO_TRANSFER_CMDTYPE                                                     */
67819   SDIO_TRANSFER_CMDTYPE_NORMAL         = 0,     /*!< NORMAL : Normal                                                           */
67820   SDIO_TRANSFER_CMDTYPE_SUSPEND        = 1,     /*!< SUSPEND : Suspend                                                         */
67821   SDIO_TRANSFER_CMDTYPE_RESUME         = 2,     /*!< RESUME : Resume                                                           */
67822   SDIO_TRANSFER_CMDTYPE_ABORT          = 3,     /*!< ABORT : Abort                                                             */
67823 } SDIO_TRANSFER_CMDTYPE_Enum;
67824 
67825 /* ==========================================  SDIO TRANSFER DATAPRSNTSEL [21..21]  ========================================== */
67826 typedef enum {                                  /*!< SDIO_TRANSFER_DATAPRSNTSEL                                                */
67827   SDIO_TRANSFER_DATAPRSNTSEL_NODATAPRESENT = 0, /*!< NODATAPRESENT : No Data Present                                           */
67828   SDIO_TRANSFER_DATAPRSNTSEL_DATAPRESENT = 1,   /*!< DATAPRESENT : Data Present                                                */
67829 } SDIO_TRANSFER_DATAPRSNTSEL_Enum;
67830 
67831 /* ==========================================  SDIO TRANSFER CMDIDXCHKEN [20..20]  =========================================== */
67832 typedef enum {                                  /*!< SDIO_TRANSFER_CMDIDXCHKEN                                                 */
67833   SDIO_TRANSFER_CMDIDXCHKEN_DISABLE    = 0,     /*!< DISABLE : Disable                                                         */
67834   SDIO_TRANSFER_CMDIDXCHKEN_ENABLE     = 1,     /*!< ENABLE : Enable                                                           */
67835 } SDIO_TRANSFER_CMDIDXCHKEN_Enum;
67836 
67837 /* ==========================================  SDIO TRANSFER CMDCRCCHKEN [19..19]  =========================================== */
67838 typedef enum {                                  /*!< SDIO_TRANSFER_CMDCRCCHKEN                                                 */
67839   SDIO_TRANSFER_CMDCRCCHKEN_DISABLE    = 0,     /*!< DISABLE : Disable                                                         */
67840   SDIO_TRANSFER_CMDCRCCHKEN_ENABLE     = 1,     /*!< ENABLE : Enable                                                           */
67841 } SDIO_TRANSFER_CMDCRCCHKEN_Enum;
67842 
67843 /* ==========================================  SDIO TRANSFER RESPTYPESEL [16..17]  =========================================== */
67844 typedef enum {                                  /*!< SDIO_TRANSFER_RESPTYPESEL                                                 */
67845   SDIO_TRANSFER_RESPTYPESEL_NORESPONSE = 0,     /*!< NORESPONSE : No Response                                                  */
67846   SDIO_TRANSFER_RESPTYPESEL_LEN136     = 1,     /*!< LEN136 : Response length 136                                              */
67847   SDIO_TRANSFER_RESPTYPESEL_LEN48      = 2,     /*!< LEN48 : Response length 48                                                */
67848   SDIO_TRANSFER_RESPTYPESEL_LEN48CHKBUSY = 3,   /*!< LEN48CHKBUSY : Response length 48 check Busy after response               */
67849 } SDIO_TRANSFER_RESPTYPESEL_Enum;
67850 
67851 /* ==============================================  SDIO TRANSFER BLKSEL [5..5]  ============================================== */
67852 typedef enum {                                  /*!< SDIO_TRANSFER_BLKSEL                                                      */
67853   SDIO_TRANSFER_BLKSEL_SINGLEBLOCK     = 0,     /*!< SINGLEBLOCK : Single Block                                                */
67854   SDIO_TRANSFER_BLKSEL_MULTIPLEBLOCK   = 1,     /*!< MULTIPLEBLOCK : Multiple Block                                            */
67855 } SDIO_TRANSFER_BLKSEL_Enum;
67856 
67857 /* ===========================================  SDIO TRANSFER DXFERDIRSEL [4..4]  ============================================ */
67858 typedef enum {                                  /*!< SDIO_TRANSFER_DXFERDIRSEL                                                 */
67859   SDIO_TRANSFER_DXFERDIRSEL_WRITE      = 0,     /*!< WRITE : Write (Host to Card)                                              */
67860   SDIO_TRANSFER_DXFERDIRSEL_READ       = 1,     /*!< READ : Read (Card to Host)                                                */
67861 } SDIO_TRANSFER_DXFERDIRSEL_Enum;
67862 
67863 /* ==============================================  SDIO TRANSFER ACMDEN [2..3]  ============================================== */
67864 typedef enum {                                  /*!< SDIO_TRANSFER_ACMDEN                                                      */
67865   SDIO_TRANSFER_ACMDEN_DISABLED        = 0,     /*!< DISABLED : Auto Command Disabled                                          */
67866   SDIO_TRANSFER_ACMDEN_CMD12ENABLE     = 1,     /*!< CMD12ENABLE : Auto CMD12 Enable                                           */
67867   SDIO_TRANSFER_ACMDEN_CMD23ENABLE     = 2,     /*!< CMD23ENABLE : Auto CMD23 Enable                                           */
67868 } SDIO_TRANSFER_ACMDEN_Enum;
67869 
67870 /* =============================================  SDIO TRANSFER BLKCNTEN [1..1]  ============================================= */
67871 typedef enum {                                  /*!< SDIO_TRANSFER_BLKCNTEN                                                    */
67872   SDIO_TRANSFER_BLKCNTEN_DISABLE       = 0,     /*!< DISABLE : Disable                                                         */
67873   SDIO_TRANSFER_BLKCNTEN_ENABLE        = 1,     /*!< ENABLE : Enable                                                           */
67874 } SDIO_TRANSFER_BLKCNTEN_Enum;
67875 
67876 /* ==============================================  SDIO TRANSFER DMAEN [0..0]  =============================================== */
67877 typedef enum {                                  /*!< SDIO_TRANSFER_DMAEN                                                       */
67878   SDIO_TRANSFER_DMAEN_DISABLE          = 0,     /*!< DISABLE : Disable                                                         */
67879   SDIO_TRANSFER_DMAEN_ENABLE           = 1,     /*!< ENABLE : Enable                                                           */
67880 } SDIO_TRANSFER_DMAEN_Enum;
67881 
67882 /* =======================================================  RESPONSE0  ======================================================= */
67883 /* =======================================================  RESPONSE1  ======================================================= */
67884 /* =======================================================  RESPONSE2  ======================================================= */
67885 /* =======================================================  RESPONSE3  ======================================================= */
67886 /* ========================================================  BUFFER  ========================================================= */
67887 /* ========================================================  PRESENT  ======================================================== */
67888 /* ============================================  SDIO PRESENT DAT74LINE [25..28]  ============================================ */
67889 typedef enum {                                  /*!< SDIO_PRESENT_DAT74LINE                                                    */
67890   SDIO_PRESENT_DAT74LINE_DAT7          = 8,     /*!< DAT7 : DAT[7]                                                             */
67891   SDIO_PRESENT_DAT74LINE_DAT6          = 4,     /*!< DAT6 : DAT[6]                                                             */
67892   SDIO_PRESENT_DAT74LINE_DAT5          = 2,     /*!< DAT5 : DAT[5]                                                             */
67893   SDIO_PRESENT_DAT74LINE_DAT4          = 1,     /*!< DAT4 : DAT[4]                                                             */
67894 } SDIO_PRESENT_DAT74LINE_Enum;
67895 
67896 /* ============================================  SDIO PRESENT DAT30LINE [20..23]  ============================================ */
67897 typedef enum {                                  /*!< SDIO_PRESENT_DAT30LINE                                                    */
67898   SDIO_PRESENT_DAT30LINE_DAT3          = 8,     /*!< DAT3 : DAT[3]                                                             */
67899   SDIO_PRESENT_DAT30LINE_DAT2          = 4,     /*!< DAT2 : DAT[2]                                                             */
67900   SDIO_PRESENT_DAT30LINE_DAT1          = 2,     /*!< DAT1 : DAT[1]                                                             */
67901   SDIO_PRESENT_DAT30LINE_DAT0          = 1,     /*!< DAT0 : DAT[0]                                                             */
67902 } SDIO_PRESENT_DAT30LINE_Enum;
67903 
67904 /* ============================================  SDIO PRESENT WRPROTSW [19..19]  ============================================= */
67905 typedef enum {                                  /*!< SDIO_PRESENT_WRPROTSW                                                     */
67906   SDIO_PRESENT_WRPROTSW_WRITEPROTECTED = 0,     /*!< WRITEPROTECTED : Write protected (SDWP# = 0)                              */
67907   SDIO_PRESENT_WRPROTSW_WRITEENABLED   = 1,     /*!< WRITEENABLED : Write enabled (SDWP# = 1)                                  */
67908 } SDIO_PRESENT_WRPROTSW_Enum;
67909 
67910 /* =============================================  SDIO PRESENT CARDDET [18..18]  ============================================= */
67911 typedef enum {                                  /*!< SDIO_PRESENT_CARDDET                                                      */
67912   SDIO_PRESENT_CARDDET_NOCARDPRESENT   = 0,     /*!< NOCARDPRESENT : No Card present (SDCD# = 1)                               */
67913   SDIO_PRESENT_CARDDET_CARDPRESENT     = 1,     /*!< CARDPRESENT : Card present (SDCD# = 0)                                    */
67914 } SDIO_PRESENT_CARDDET_Enum;
67915 
67916 /* ===========================================  SDIO PRESENT CARDSTABLE [17..17]  ============================================ */
67917 typedef enum {                                  /*!< SDIO_PRESENT_CARDSTABLE                                                   */
67918   SDIO_PRESENT_CARDSTABLE_RESET_DEBOUNCING_NOCARD = 0,/*!< RESET_DEBOUNCING_NOCARD : Reset or Debouncing or No Card            */
67919   SDIO_PRESENT_CARDSTABLE_CARDINSERTED = 1,     /*!< CARDINSERTED : Card Inserted                                              */
67920 } SDIO_PRESENT_CARDSTABLE_Enum;
67921 
67922 /* ==========================================  SDIO PRESENT CARDINSERTED [16..16]  =========================================== */
67923 typedef enum {                                  /*!< SDIO_PRESENT_CARDINSERTED                                                 */
67924   SDIO_PRESENT_CARDINSERTED_RESET_DEBOUNCING_NOCARD = 0,/*!< RESET_DEBOUNCING_NOCARD : Reset or Debouncing or No Card          */
67925   SDIO_PRESENT_CARDINSERTED_CARDINSERTED = 1,   /*!< CARDINSERTED : Card Inserted                                              */
67926 } SDIO_PRESENT_CARDINSERTED_Enum;
67927 
67928 /* =============================================  SDIO PRESENT BUFRDEN [11..11]  ============================================= */
67929 typedef enum {                                  /*!< SDIO_PRESENT_BUFRDEN                                                      */
67930   SDIO_PRESENT_BUFRDEN_DISABLE         = 0,     /*!< DISABLE : Read Disable                                                    */
67931   SDIO_PRESENT_BUFRDEN_ENABLE          = 1,     /*!< ENABLE : Read Enable.                                                     */
67932 } SDIO_PRESENT_BUFRDEN_Enum;
67933 
67934 /* =============================================  SDIO PRESENT BUFWREN [10..10]  ============================================= */
67935 typedef enum {                                  /*!< SDIO_PRESENT_BUFWREN                                                      */
67936   SDIO_PRESENT_BUFWREN_DISABLE         = 0,     /*!< DISABLE : Write Disable                                                   */
67937   SDIO_PRESENT_BUFWREN_ENABLE          = 1,     /*!< ENABLE : Write Enable.                                                    */
67938 } SDIO_PRESENT_BUFWREN_Enum;
67939 
67940 /* =============================================  SDIO PRESENT RDXFERACT [9..9]  ============================================= */
67941 typedef enum {                                  /*!< SDIO_PRESENT_RDXFERACT                                                    */
67942   SDIO_PRESENT_RDXFERACT_TRANSFERRING  = 1,     /*!< TRANSFERRING : Transferring data                                          */
67943   SDIO_PRESENT_RDXFERACT_NOVALIDATA    = 0,     /*!< NOVALIDATA : No valid data                                                */
67944 } SDIO_PRESENT_RDXFERACT_Enum;
67945 
67946 /* =============================================  SDIO PRESENT WRXFERACT [8..8]  ============================================= */
67947 typedef enum {                                  /*!< SDIO_PRESENT_WRXFERACT                                                    */
67948   SDIO_PRESENT_WRXFERACT_TRANSFERRING  = 1,     /*!< TRANSFERRING : transferring data                                          */
67949   SDIO_PRESENT_WRXFERACT_NOVALIDDATA   = 0,     /*!< NOVALIDDATA : No valid data                                               */
67950 } SDIO_PRESENT_WRXFERACT_Enum;
67951 
67952 /* ==========================================  SDIO PRESENT RETUNINGREQUEST [3..3]  ========================================== */
67953 typedef enum {                                  /*!< SDIO_PRESENT_RETUNINGREQUEST                                              */
67954   SDIO_PRESENT_RETUNINGREQUEST_RETUNENEEDED = 1,/*!< RETUNENEEDED : Sampling clock needs re-tuning                             */
67955   SDIO_PRESENT_RETUNINGREQUEST_WELLTUNED = 0,   /*!< WELLTUNED : Fixed or well tuned sampling clock                            */
67956 } SDIO_PRESENT_RETUNINGREQUEST_Enum;
67957 
67958 /* =============================================  SDIO PRESENT DLINEACT [2..2]  ============================================== */
67959 typedef enum {                                  /*!< SDIO_PRESENT_DLINEACT                                                     */
67960   SDIO_PRESENT_DLINEACT_ACTIVE         = 1,     /*!< ACTIVE : DAT line active                                                  */
67961   SDIO_PRESENT_DLINEACT_INACTIVE       = 0,     /*!< INACTIVE : DAT line inactive                                              */
67962 } SDIO_PRESENT_DLINEACT_Enum;
67963 
67964 /* =============================================  SDIO PRESENT CMDINHDAT [1..1]  ============================================= */
67965 typedef enum {                                  /*!< SDIO_PRESENT_CMDINHDAT                                                    */
67966   SDIO_PRESENT_CMDINHDAT_DONTISSUE     = 1,     /*!< DONTISSUE : cannot issue command which uses the DAT line                  */
67967   SDIO_PRESENT_CMDINHDAT_ISSUE         = 0,     /*!< ISSUE : Can issue command which uses the DAT line                         */
67968 } SDIO_PRESENT_CMDINHDAT_Enum;
67969 
67970 /* =============================================  SDIO PRESENT CMDINHCMD [0..0]  ============================================= */
67971 typedef enum {                                  /*!< SDIO_PRESENT_CMDINHCMD                                                    */
67972   SDIO_PRESENT_CMDINHCMD_DONTISSUE     = 1,     /*!< DONTISSUE : CMD line is in use                                            */
67973   SDIO_PRESENT_CMDINHCMD_ISSUE         = 0,     /*!< ISSUE : Indicates that the CMD line is not in use and the HC
67974                                                      can issue a SD command using the CMD line.                                */
67975 } SDIO_PRESENT_CMDINHCMD_Enum;
67976 
67977 /* =======================================================  HOSTCTRL1  ======================================================= */
67978 /* ========================================  SDIO HOSTCTRL1 WUENCARDREMOVL [26..26]  ========================================= */
67979 typedef enum {                                  /*!< SDIO_HOSTCTRL1_WUENCARDREMOVL                                             */
67980   SDIO_HOSTCTRL1_WUENCARDREMOVL_ENABLE = 1,     /*!< ENABLE : Enable                                                           */
67981   SDIO_HOSTCTRL1_WUENCARDREMOVL_DISABLE = 0,    /*!< DISABLE : Disable                                                         */
67982 } SDIO_HOSTCTRL1_WUENCARDREMOVL_Enum;
67983 
67984 /* ========================================  SDIO HOSTCTRL1 WUENCARDINSERT [25..25]  ========================================= */
67985 typedef enum {                                  /*!< SDIO_HOSTCTRL1_WUENCARDINSERT                                             */
67986   SDIO_HOSTCTRL1_WUENCARDINSERT_ENABLE = 1,     /*!< ENABLE : Enable                                                           */
67987   SDIO_HOSTCTRL1_WUENCARDINSERT_DISABLE = 0,    /*!< DISABLE : Disable                                                         */
67988 } SDIO_HOSTCTRL1_WUENCARDINSERT_Enum;
67989 
67990 /* ==========================================  SDIO HOSTCTRL1 WUENCARDINT [24..24]  ========================================== */
67991 typedef enum {                                  /*!< SDIO_HOSTCTRL1_WUENCARDINT                                                */
67992   SDIO_HOSTCTRL1_WUENCARDINT_ENABLE    = 1,     /*!< ENABLE : Enable                                                           */
67993   SDIO_HOSTCTRL1_WUENCARDINT_DISABLE   = 0,     /*!< DISABLE : Disable                                                         */
67994 } SDIO_HOSTCTRL1_WUENCARDINT_Enum;
67995 
67996 /* ==========================================  SDIO HOSTCTRL1 BOOTACKCHK [23..23]  =========================================== */
67997 typedef enum {                                  /*!< SDIO_HOSTCTRL1_BOOTACKCHK                                                 */
67998   SDIO_HOSTCTRL1_BOOTACKCHK_WAIT       = 1,     /*!< WAIT : wait for boot ack from eMMC card                                   */
67999   SDIO_HOSTCTRL1_BOOTACKCHK_NOWAIT     = 0,     /*!< NOWAIT : Will not wait for boot ack from eMMC card                        */
68000 } SDIO_HOSTCTRL1_BOOTACKCHK_Enum;
68001 
68002 /* ===========================================  SDIO HOSTCTRL1 ALTBOOTEN [22..22]  =========================================== */
68003 typedef enum {                                  /*!< SDIO_HOSTCTRL1_ALTBOOTEN                                                  */
68004   SDIO_HOSTCTRL1_ALTBOOTEN_START       = 1,     /*!< START : To start alternate boot mode access                               */
68005   SDIO_HOSTCTRL1_ALTBOOTEN_STOP        = 0,     /*!< STOP : To stop alternate boot mode access                                 */
68006 } SDIO_HOSTCTRL1_ALTBOOTEN_Enum;
68007 
68008 /* ============================================  SDIO HOSTCTRL1 BOOTEN [21..21]  ============================================= */
68009 typedef enum {                                  /*!< SDIO_HOSTCTRL1_BOOTEN                                                     */
68010   SDIO_HOSTCTRL1_BOOTEN_START          = 1,     /*!< START : To start boot code access                                         */
68011   SDIO_HOSTCTRL1_BOOTEN_STOP           = 0,     /*!< STOP : To stop boot code access                                           */
68012 } SDIO_HOSTCTRL1_BOOTEN_Enum;
68013 
68014 /* ============================================  SDIO HOSTCTRL1 SPIMODE [20..20]  ============================================ */
68015 typedef enum {                                  /*!< SDIO_HOSTCTRL1_SPIMODE                                                    */
68016   SDIO_HOSTCTRL1_SPIMODE_SPI           = 1,     /*!< SPI : SPI mode                                                            */
68017   SDIO_HOSTCTRL1_SPIMODE_SD            = 0,     /*!< SD : SD mode                                                              */
68018 } SDIO_HOSTCTRL1_SPIMODE_Enum;
68019 
68020 /* =========================================  SDIO HOSTCTRL1 READWAITCTRL [18..18]  ========================================== */
68021 typedef enum {                                  /*!< SDIO_HOSTCTRL1_READWAITCTRL                                               */
68022   SDIO_HOSTCTRL1_READWAITCTRL_ENABLE   = 1,     /*!< ENABLE : Enable Read Wait Control                                         */
68023   SDIO_HOSTCTRL1_READWAITCTRL_DISABLE  = 0,     /*!< DISABLE : Disable Read Wait Control                                       */
68024 } SDIO_HOSTCTRL1_READWAITCTRL_Enum;
68025 
68026 /* ============================================  SDIO HOSTCTRL1 CONTREQ [17..17]  ============================================ */
68027 typedef enum {                                  /*!< SDIO_HOSTCTRL1_CONTREQ                                                    */
68028   SDIO_HOSTCTRL1_CONTREQ_RESTART       = 1,     /*!< RESTART : Restart                                                         */
68029   SDIO_HOSTCTRL1_CONTREQ_IGNORED       = 0,     /*!< IGNORED : Ignored                                                         */
68030 } SDIO_HOSTCTRL1_CONTREQ_Enum;
68031 
68032 /* =====================================  SDIO HOSTCTRL1 STOPATBLOCKGAPREQUEST [16..16]  ===================================== */
68033 typedef enum {                                  /*!< SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST                                      */
68034   SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_STOP = 1,/*!< STOP : Stop                                                               */
68035   SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_TRANSFER = 0,/*!< TRANSFER : Transfer                                                   */
68036 } SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Enum;
68037 
68038 /* ============================================  SDIO HOSTCTRL1 HWRESET [12..12]  ============================================ */
68039 typedef enum {                                  /*!< SDIO_HOSTCTRL1_HWRESET                                                    */
68040   SDIO_HOSTCTRL1_HWRESET_ASSERT        = 1,     /*!< ASSERT : Drives the hardware reset pin as ZERO (Active LOW to
68041                                                      eMMC card)                                                                */
68042   SDIO_HOSTCTRL1_HWRESET_DEASSERT      = 0,     /*!< DEASSERT : Deassert the hardware reset pin                                */
68043 } SDIO_HOSTCTRL1_HWRESET_Enum;
68044 
68045 /* ===========================================  SDIO HOSTCTRL1 VOLTSELECT [9..11]  =========================================== */
68046 typedef enum {                                  /*!< SDIO_HOSTCTRL1_VOLTSELECT                                                 */
68047   SDIO_HOSTCTRL1_VOLTSELECT_3_3V       = 7,     /*!< 3_3V : 3.3 V(Typ.)                                                        */
68048   SDIO_HOSTCTRL1_VOLTSELECT_3_0V       = 6,     /*!< 3_0V : 3.0 V(Typ.)                                                        */
68049   SDIO_HOSTCTRL1_VOLTSELECT_1_8V       = 5,     /*!< 1_8V : 1.8 V(Typ.)                                                        */
68050 } SDIO_HOSTCTRL1_VOLTSELECT_Enum;
68051 
68052 /* ===========================================  SDIO HOSTCTRL1 SDBUSPOWER [8..8]  ============================================ */
68053 typedef enum {                                  /*!< SDIO_HOSTCTRL1_SDBUSPOWER                                                 */
68054   SDIO_HOSTCTRL1_SDBUSPOWER_POWERON    = 1,     /*!< POWERON : Power on                                                        */
68055   SDIO_HOSTCTRL1_SDBUSPOWER_POWEROFF   = 0,     /*!< POWEROFF : Power off                                                      */
68056 } SDIO_HOSTCTRL1_SDBUSPOWER_Enum;
68057 
68058 /* =============================================  SDIO HOSTCTRL1 CARDSRC [7..7]  ============================================= */
68059 typedef enum {                                  /*!< SDIO_HOSTCTRL1_CARDSRC                                                    */
68060   SDIO_HOSTCTRL1_CARDSRC_TEST          = 1,     /*!< TEST : The card detect test level is selected                             */
68061   SDIO_HOSTCTRL1_CARDSRC_SDCD          = 0,     /*!< SDCD : SDCD is selected (for normal use)                                  */
68062 } SDIO_HOSTCTRL1_CARDSRC_Enum;
68063 
68064 /* ============================================  SDIO HOSTCTRL1 TESTLEVEL [6..6]  ============================================ */
68065 typedef enum {                                  /*!< SDIO_HOSTCTRL1_TESTLEVEL                                                  */
68066   SDIO_HOSTCTRL1_TESTLEVEL_CARDINSERTED = 1,    /*!< CARDINSERTED : Card Inserted                                              */
68067   SDIO_HOSTCTRL1_TESTLEVEL_NOCARD      = 0,     /*!< NOCARD : No Card                                                          */
68068 } SDIO_HOSTCTRL1_TESTLEVEL_Enum;
68069 
68070 /* ============================================  SDIO HOSTCTRL1 XFERWIDTH [5..5]  ============================================ */
68071 typedef enum {                                  /*!< SDIO_HOSTCTRL1_XFERWIDTH                                                  */
68072   SDIO_HOSTCTRL1_XFERWIDTH_8BIT        = 1,     /*!< 8BIT : 8-bit Bus Width                                                    */
68073   SDIO_HOSTCTRL1_XFERWIDTH_XFER        = 0,     /*!< XFER : Bus Width is selected by Data Transfer Width                       */
68074 } SDIO_HOSTCTRL1_XFERWIDTH_Enum;
68075 
68076 /* ============================================  SDIO HOSTCTRL1 DMASELECT [3..4]  ============================================ */
68077 typedef enum {                                  /*!< SDIO_HOSTCTRL1_DMASELECT                                                  */
68078   SDIO_HOSTCTRL1_DMASELECT_SDMA        = 0,     /*!< SDMA : SDMA is selected                                                   */
68079   SDIO_HOSTCTRL1_DMASELECT_ADMA132     = 1,     /*!< ADMA132 : 32-bit Address ADMA1 is selected                                */
68080   SDIO_HOSTCTRL1_DMASELECT_ADMA232     = 2,     /*!< ADMA232 : 32-bit Address ADMA2 is selected                                */
68081   SDIO_HOSTCTRL1_DMASELECT_ADMA264     = 3,     /*!< ADMA264 : 64-bit Address ADMA2 is selected                                */
68082 } SDIO_HOSTCTRL1_DMASELECT_Enum;
68083 
68084 /* ============================================  SDIO HOSTCTRL1 HISPEEDEN [2..2]  ============================================ */
68085 typedef enum {                                  /*!< SDIO_HOSTCTRL1_HISPEEDEN                                                  */
68086   SDIO_HOSTCTRL1_HISPEEDEN_HIGH        = 1,     /*!< HIGH : High Speed Mode                                                    */
68087   SDIO_HOSTCTRL1_HISPEEDEN_NORMAL      = 0,     /*!< NORMAL : Normal Speed Mode                                                */
68088 } SDIO_HOSTCTRL1_HISPEEDEN_Enum;
68089 
68090 /* ========================================  SDIO HOSTCTRL1 DATATRANSFERWIDTH [1..1]  ======================================== */
68091 typedef enum {                                  /*!< SDIO_HOSTCTRL1_DATATRANSFERWIDTH                                          */
68092   SDIO_HOSTCTRL1_DATATRANSFERWIDTH_SD4 = 1,     /*!< SD4 : 4 bit mode                                                          */
68093   SDIO_HOSTCTRL1_DATATRANSFERWIDTH_SD1 = 0,     /*!< SD1 : 1 bit mode                                                          */
68094 } SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Enum;
68095 
68096 /* ===========================================  SDIO HOSTCTRL1 LEDCONTROL [0..0]  ============================================ */
68097 typedef enum {                                  /*!< SDIO_HOSTCTRL1_LEDCONTROL                                                 */
68098   SDIO_HOSTCTRL1_LEDCONTROL_ON         = 1,     /*!< ON : LED on                                                               */
68099   SDIO_HOSTCTRL1_LEDCONTROL_OFF        = 0,     /*!< OFF : LED off                                                             */
68100 } SDIO_HOSTCTRL1_LEDCONTROL_Enum;
68101 
68102 /* =======================================================  CLOCKCTRL  ======================================================= */
68103 /* ===========================================  SDIO CLOCKCTRL SWRSTDAT [26..26]  ============================================ */
68104 typedef enum {                                  /*!< SDIO_CLOCKCTRL_SWRSTDAT                                                   */
68105   SDIO_CLOCKCTRL_SWRSTDAT_RESET        = 1,     /*!< RESET : Reset                                                             */
68106   SDIO_CLOCKCTRL_SWRSTDAT_WORK         = 0,     /*!< WORK : Work                                                               */
68107 } SDIO_CLOCKCTRL_SWRSTDAT_Enum;
68108 
68109 /* ===========================================  SDIO CLOCKCTRL SWRSTCMD [25..25]  ============================================ */
68110 typedef enum {                                  /*!< SDIO_CLOCKCTRL_SWRSTCMD                                                   */
68111   SDIO_CLOCKCTRL_SWRSTCMD_RESET        = 1,     /*!< RESET : Reset                                                             */
68112   SDIO_CLOCKCTRL_SWRSTCMD_WORK         = 0,     /*!< WORK : Work                                                               */
68113 } SDIO_CLOCKCTRL_SWRSTCMD_Enum;
68114 
68115 /* ===========================================  SDIO CLOCKCTRL SWRSTALL [24..24]  ============================================ */
68116 typedef enum {                                  /*!< SDIO_CLOCKCTRL_SWRSTALL                                                   */
68117   SDIO_CLOCKCTRL_SWRSTALL_RESET        = 1,     /*!< RESET : Reset                                                             */
68118   SDIO_CLOCKCTRL_SWRSTALL_WORK         = 0,     /*!< WORK : Work                                                               */
68119 } SDIO_CLOCKCTRL_SWRSTALL_Enum;
68120 
68121 /* ==========================================  SDIO CLOCKCTRL TIMEOUTCNT [16..19]  =========================================== */
68122 typedef enum {                                  /*!< SDIO_CLOCKCTRL_TIMEOUTCNT                                                 */
68123   SDIO_CLOCKCTRL_TIMEOUTCNT_27         = 14,    /*!< 27 : TMCLK * 2^27                                                         */
68124   SDIO_CLOCKCTRL_TIMEOUTCNT_26         = 0,     /*!< 26 : TMCLK * 2^26                                                         */
68125 } SDIO_CLOCKCTRL_TIMEOUTCNT_Enum;
68126 
68127 /* ============================================  SDIO CLOCKCTRL FREQSEL [8..15]  ============================================= */
68128 typedef enum {                                  /*!< SDIO_CLOCKCTRL_FREQSEL                                                    */
68129   SDIO_CLOCKCTRL_FREQSEL_DIV256        = 128,   /*!< DIV256 : base clock divided by 256                                        */
68130   SDIO_CLOCKCTRL_FREQSEL_DIV128        = 64,    /*!< DIV128 : base clock divided by 128                                        */
68131   SDIO_CLOCKCTRL_FREQSEL_DIV64         = 32,    /*!< DIV64 : base clock divided by 64                                          */
68132   SDIO_CLOCKCTRL_FREQSEL_DIV32         = 16,    /*!< DIV32 : base clock divided by 32                                          */
68133   SDIO_CLOCKCTRL_FREQSEL_DIV16         = 8,     /*!< DIV16 : base clock divided by 16                                          */
68134   SDIO_CLOCKCTRL_FREQSEL_DIV8          = 4,     /*!< DIV8 : base clock divided by 8                                            */
68135   SDIO_CLOCKCTRL_FREQSEL_DIV4          = 2,     /*!< DIV4 : base clock divided by 4                                            */
68136   SDIO_CLOCKCTRL_FREQSEL_DIV2          = 1,     /*!< DIV2 : base clock divided by 2                                            */
68137   SDIO_CLOCKCTRL_FREQSEL_BASECLK       = 0,     /*!< BASECLK : Base clock (10MHz - 63MHz)                                      */
68138 } SDIO_CLOCKCTRL_FREQSEL_Enum;
68139 
68140 /* ============================================  SDIO CLOCKCTRL CLKGENSEL [5..5]  ============================================ */
68141 typedef enum {                                  /*!< SDIO_CLOCKCTRL_CLKGENSEL                                                  */
68142   SDIO_CLOCKCTRL_CLKGENSEL_PROGCLK     = 1,     /*!< PROGCLK : Programmable Clock Mode                                         */
68143   SDIO_CLOCKCTRL_CLKGENSEL_DIVCLK      = 0,     /*!< DIVCLK : Divided Clock Mode                                               */
68144 } SDIO_CLOCKCTRL_CLKGENSEL_Enum;
68145 
68146 /* =============================================  SDIO CLOCKCTRL SDCLKEN [2..2]  ============================================= */
68147 typedef enum {                                  /*!< SDIO_CLOCKCTRL_SDCLKEN                                                    */
68148   SDIO_CLOCKCTRL_SDCLKEN_ENABLE        = 1,     /*!< ENABLE : Enable                                                           */
68149   SDIO_CLOCKCTRL_SDCLKEN_DISABLE       = 0,     /*!< DISABLE : Disable                                                         */
68150 } SDIO_CLOCKCTRL_SDCLKEN_Enum;
68151 
68152 /* ============================================  SDIO CLOCKCTRL CLKSTABLE [1..1]  ============================================ */
68153 typedef enum {                                  /*!< SDIO_CLOCKCTRL_CLKSTABLE                                                  */
68154   SDIO_CLOCKCTRL_CLKSTABLE_READY       = 1,     /*!< READY : Ready                                                             */
68155   SDIO_CLOCKCTRL_CLKSTABLE_NOTREADY    = 0,     /*!< NOTREADY : Not Ready                                                      */
68156 } SDIO_CLOCKCTRL_CLKSTABLE_Enum;
68157 
68158 /* ==============================================  SDIO CLOCKCTRL CLKEN [0..0]  ============================================== */
68159 typedef enum {                                  /*!< SDIO_CLOCKCTRL_CLKEN                                                      */
68160   SDIO_CLOCKCTRL_CLKEN_OSC             = 1,     /*!< OSC : Oscillate                                                           */
68161   SDIO_CLOCKCTRL_CLKEN_STOP            = 0,     /*!< STOP : Stop                                                               */
68162 } SDIO_CLOCKCTRL_CLKEN_Enum;
68163 
68164 /* ========================================================  INTSTAT  ======================================================== */
68165 /* ===========================================  SDIO INTSTAT VNDERRSTAT [29..31]  ============================================ */
68166 typedef enum {                                  /*!< SDIO_INTSTAT_VNDERRSTAT                                                   */
68167   SDIO_INTSTAT_VNDERRSTAT_READY        = 1,     /*!< READY : Ready                                                             */
68168   SDIO_INTSTAT_VNDERRSTAT_NOTREADY     = 0,     /*!< NOTREADY : Not Ready                                                      */
68169 } SDIO_INTSTAT_VNDERRSTAT_Enum;
68170 
68171 /* ===========================================  SDIO INTSTAT TGTRESPERR [28..28]  ============================================ */
68172 typedef enum {                                  /*!< SDIO_INTSTAT_TGTRESPERR                                                   */
68173   SDIO_INTSTAT_TGTRESPERR_NOERROR      = 0,     /*!< NOERROR : no error                                                        */
68174   SDIO_INTSTAT_TGTRESPERR_ERROR        = 1,     /*!< ERROR : error                                                             */
68175 } SDIO_INTSTAT_TGTRESPERR_Enum;
68176 
68177 /* ============================================  SDIO INTSTAT ADMAERROR [25..25]  ============================================ */
68178 typedef enum {                                  /*!< SDIO_INTSTAT_ADMAERROR                                                    */
68179   SDIO_INTSTAT_ADMAERROR_ERROR         = 1,     /*!< ERROR : Error                                                             */
68180   SDIO_INTSTAT_ADMAERROR_NOERROR       = 0,     /*!< NOERROR : No error                                                        */
68181 } SDIO_INTSTAT_ADMAERROR_Enum;
68182 
68183 /* ==========================================  SDIO INTSTAT AUTOCMDERROR [24..24]  =========================================== */
68184 typedef enum {                                  /*!< SDIO_INTSTAT_AUTOCMDERROR                                                 */
68185   SDIO_INTSTAT_AUTOCMDERROR_NOERROR    = 0,     /*!< NOERROR : No Error                                                        */
68186   SDIO_INTSTAT_AUTOCMDERROR_ERROR      = 1,     /*!< ERROR : Error                                                             */
68187 } SDIO_INTSTAT_AUTOCMDERROR_Enum;
68188 
68189 /* ========================================  SDIO INTSTAT CURRENTLIMITERROR [23..23]  ======================================== */
68190 typedef enum {                                  /*!< SDIO_INTSTAT_CURRENTLIMITERROR                                            */
68191   SDIO_INTSTAT_CURRENTLIMITERROR_NOERROR = 0,   /*!< NOERROR : No Error                                                        */
68192   SDIO_INTSTAT_CURRENTLIMITERROR_ERROR = 1,     /*!< ERROR : Power Fail                                                        */
68193 } SDIO_INTSTAT_CURRENTLIMITERROR_Enum;
68194 
68195 /* =========================================  SDIO INTSTAT DATAENDBITERROR [22..22]  ========================================= */
68196 typedef enum {                                  /*!< SDIO_INTSTAT_DATAENDBITERROR                                              */
68197   SDIO_INTSTAT_DATAENDBITERROR_NOERROR = 0,     /*!< NOERROR : No Error                                                        */
68198   SDIO_INTSTAT_DATAENDBITERROR_ERROR   = 1,     /*!< ERROR : Error                                                             */
68199 } SDIO_INTSTAT_DATAENDBITERROR_Enum;
68200 
68201 /* ==========================================  SDIO INTSTAT DATACRCERROR [21..21]  =========================================== */
68202 typedef enum {                                  /*!< SDIO_INTSTAT_DATACRCERROR                                                 */
68203   SDIO_INTSTAT_DATACRCERROR_NOERROR    = 0,     /*!< NOERROR : No Error                                                        */
68204   SDIO_INTSTAT_DATACRCERROR_ERROR      = 1,     /*!< ERROR : Error                                                             */
68205 } SDIO_INTSTAT_DATACRCERROR_Enum;
68206 
68207 /* ========================================  SDIO INTSTAT DATATIMEOUTERROR [20..20]  ========================================= */
68208 typedef enum {                                  /*!< SDIO_INTSTAT_DATATIMEOUTERROR                                             */
68209   SDIO_INTSTAT_DATATIMEOUTERROR_NOERROR = 0,    /*!< NOERROR : No Error                                                        */
68210   SDIO_INTSTAT_DATATIMEOUTERROR_ERROR  = 1,     /*!< ERROR : Timeout                                                           */
68211 } SDIO_INTSTAT_DATATIMEOUTERROR_Enum;
68212 
68213 /* ========================================  SDIO INTSTAT COMMANDINDEXERROR [19..19]  ======================================== */
68214 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDINDEXERROR                                            */
68215   SDIO_INTSTAT_COMMANDINDEXERROR_NOERROR = 0,   /*!< NOERROR : No Error                                                        */
68216   SDIO_INTSTAT_COMMANDINDEXERROR_ERROR = 1,     /*!< ERROR : Error                                                             */
68217 } SDIO_INTSTAT_COMMANDINDEXERROR_Enum;
68218 
68219 /* =======================================  SDIO INTSTAT COMMANDENDBITERROR [18..18]  ======================================== */
68220 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDENDBITERROR                                           */
68221   SDIO_INTSTAT_COMMANDENDBITERROR_NOERROR = 0,  /*!< NOERROR : No Error                                                        */
68222   SDIO_INTSTAT_COMMANDENDBITERROR_ERROR = 1,    /*!< ERROR : Timeout                                                           */
68223 } SDIO_INTSTAT_COMMANDENDBITERROR_Enum;
68224 
68225 /* =========================================  SDIO INTSTAT COMMANDCRCERROR [17..17]  ========================================= */
68226 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDCRCERROR                                              */
68227   SDIO_INTSTAT_COMMANDCRCERROR_NOERROR = 0,     /*!< NOERROR : No Error                                                        */
68228   SDIO_INTSTAT_COMMANDCRCERROR_ERROR   = 1,     /*!< ERROR : End Bit Error Generated                                           */
68229 } SDIO_INTSTAT_COMMANDCRCERROR_Enum;
68230 
68231 /* =======================================  SDIO INTSTAT COMMANDTIMEOUTERROR [16..16]  ======================================= */
68232 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDTIMEOUTERROR                                          */
68233   SDIO_INTSTAT_COMMANDTIMEOUTERROR_NOERROR = 0, /*!< NOERROR : No Error                                                        */
68234   SDIO_INTSTAT_COMMANDTIMEOUTERROR_ERROR = 1,   /*!< ERROR : CRC Error Generated                                               */
68235 } SDIO_INTSTAT_COMMANDTIMEOUTERROR_Enum;
68236 
68237 /* =========================================  SDIO INTSTAT ERRORINTERRUPT [15..15]  ========================================== */
68238 typedef enum {                                  /*!< SDIO_INTSTAT_ERRORINTERRUPT                                               */
68239   SDIO_INTSTAT_ERRORINTERRUPT_NOERROR  = 0,     /*!< NOERROR : No Error.                                                       */
68240   SDIO_INTSTAT_ERRORINTERRUPT_ERROR    = 1,     /*!< ERROR : Error.                                                            */
68241 } SDIO_INTSTAT_ERRORINTERRUPT_Enum;
68242 
68243 /* ==========================================  SDIO INTSTAT BOOTTERMINATE [14..14]  ========================================== */
68244 typedef enum {                                  /*!< SDIO_INTSTAT_BOOTTERMINATE                                                */
68245   SDIO_INTSTAT_BOOTTERMINATE_OK        = 0,     /*!< OK : Boot operation is not terminated.                                    */
68246   SDIO_INTSTAT_BOOTTERMINATE_BOOTTERM  = 1,     /*!< BOOTTERM : Boot operation is terminated                                   */
68247 } SDIO_INTSTAT_BOOTTERMINATE_Enum;
68248 
68249 /* ===========================================  SDIO INTSTAT BOOTACKRCV [13..13]  ============================================ */
68250 typedef enum {                                  /*!< SDIO_INTSTAT_BOOTACKRCV                                                   */
68251   SDIO_INTSTAT_BOOTACKRCV_NOACK        = 0,     /*!< NOACK : Boot ack is not received.                                         */
68252   SDIO_INTSTAT_BOOTACKRCV_ACK          = 1,     /*!< ACK : Boot ack is received.                                               */
68253 } SDIO_INTSTAT_BOOTACKRCV_Enum;
68254 
68255 /* ==========================================  SDIO INTSTAT RETUNINGEVENT [12..12]  ========================================== */
68256 typedef enum {                                  /*!< SDIO_INTSTAT_RETUNINGEVENT                                                */
68257   SDIO_INTSTAT_RETUNINGEVENT_RETUNE    = 1,     /*!< RETUNE : ReTuning should be performed                                     */
68258   SDIO_INTSTAT_RETUNINGEVENT_NORETUNE  = 0,     /*!< NORETUNE : ReTuning is not required                                       */
68259 } SDIO_INTSTAT_RETUNINGEVENT_Enum;
68260 
68261 /* ===========================================  SDIO INTSTAT CARDINTERRUPT [8..8]  =========================================== */
68262 typedef enum {                                  /*!< SDIO_INTSTAT_CARDINTERRUPT                                                */
68263   SDIO_INTSTAT_CARDINTERRUPT_NOINT     = 0,     /*!< NOINT : No Card Interrupt                                                 */
68264   SDIO_INTSTAT_CARDINTERRUPT_INT       = 1,     /*!< INT : Generate Card Interrupt                                             */
68265 } SDIO_INTSTAT_CARDINTERRUPT_Enum;
68266 
68267 /* ============================================  SDIO INTSTAT CARDREMOVAL [7..7]  ============================================ */
68268 typedef enum {                                  /*!< SDIO_INTSTAT_CARDREMOVAL                                                  */
68269   SDIO_INTSTAT_CARDREMOVAL_STABLE      = 0,     /*!< STABLE : Card State Stable or Debouncing                                  */
68270   SDIO_INTSTAT_CARDREMOVAL_REMOVED     = 1,     /*!< REMOVED : Card Removed                                                    */
68271 } SDIO_INTSTAT_CARDREMOVAL_Enum;
68272 
68273 /* ===========================================  SDIO INTSTAT CARDINSERTION [6..6]  =========================================== */
68274 typedef enum {                                  /*!< SDIO_INTSTAT_CARDINSERTION                                                */
68275   SDIO_INTSTAT_CARDINSERTION_STABLE    = 0,     /*!< STABLE : Card State Stable or Debouncing                                  */
68276   SDIO_INTSTAT_CARDINSERTION_INSERTED  = 1,     /*!< INSERTED : Card Inserted                                                  */
68277 } SDIO_INTSTAT_CARDINSERTION_Enum;
68278 
68279 /* ==========================================  SDIO INTSTAT BUFFERREADREADY [5..5]  ========================================== */
68280 typedef enum {                                  /*!< SDIO_INTSTAT_BUFFERREADREADY                                              */
68281   SDIO_INTSTAT_BUFFERREADREADY_NOREADY = 0,     /*!< NOREADY : Not Ready to read Buffer.                                       */
68282   SDIO_INTSTAT_BUFFERREADREADY_READY   = 1,     /*!< READY : Ready to read Buffer.                                             */
68283 } SDIO_INTSTAT_BUFFERREADREADY_Enum;
68284 
68285 /* =========================================  SDIO INTSTAT BUFFERWRITEREADY [4..4]  ========================================== */
68286 typedef enum {                                  /*!< SDIO_INTSTAT_BUFFERWRITEREADY                                             */
68287   SDIO_INTSTAT_BUFFERWRITEREADY_NOTREADY = 0,   /*!< NOTREADY : Not Ready to Write Buffer.                                     */
68288   SDIO_INTSTAT_BUFFERWRITEREADY_READY  = 1,     /*!< READY : Ready to Write Buffer.                                            */
68289 } SDIO_INTSTAT_BUFFERWRITEREADY_Enum;
68290 
68291 /* ===========================================  SDIO INTSTAT DMAINTERRUPT [3..3]  ============================================ */
68292 typedef enum {                                  /*!< SDIO_INTSTAT_DMAINTERRUPT                                                 */
68293   SDIO_INTSTAT_DMAINTERRUPT_NOINT      = 0,     /*!< NOINT : No DMA Interrupt                                                  */
68294   SDIO_INTSTAT_DMAINTERRUPT_INT        = 1,     /*!< INT : DMA Interrupt is Generated                                          */
68295 } SDIO_INTSTAT_DMAINTERRUPT_Enum;
68296 
68297 /* ===========================================  SDIO INTSTAT BLOCKGAPEVENT [2..2]  =========================================== */
68298 typedef enum {                                  /*!< SDIO_INTSTAT_BLOCKGAPEVENT                                                */
68299   SDIO_INTSTAT_BLOCKGAPEVENT_NOEVENT   = 0,     /*!< NOEVENT : No Block Gap Event                                              */
68300   SDIO_INTSTAT_BLOCKGAPEVENT_STOPPED   = 1,     /*!< STOPPED : Transaction stopped at Block Gap                                */
68301 } SDIO_INTSTAT_BLOCKGAPEVENT_Enum;
68302 
68303 /* =========================================  SDIO INTSTAT TRANSFERCOMPLETE [1..1]  ========================================== */
68304 typedef enum {                                  /*!< SDIO_INTSTAT_TRANSFERCOMPLETE                                             */
68305   SDIO_INTSTAT_TRANSFERCOMPLETE_NODATA = 0,     /*!< NODATA : No Data Transfer Complete                                        */
68306   SDIO_INTSTAT_TRANSFERCOMPLETE_COMPLETE = 1,   /*!< COMPLETE : Data Transfer Complete                                         */
68307 } SDIO_INTSTAT_TRANSFERCOMPLETE_Enum;
68308 
68309 /* ==========================================  SDIO INTSTAT COMMANDCOMPLETE [0..0]  ========================================== */
68310 typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDCOMPLETE                                              */
68311   SDIO_INTSTAT_COMMANDCOMPLETE_NOCMP   = 0,     /*!< NOCMP : No Command Complete                                               */
68312   SDIO_INTSTAT_COMMANDCOMPLETE_CMDCMP  = 1,     /*!< CMDCMP : Command Complete                                                 */
68313 } SDIO_INTSTAT_COMMANDCOMPLETE_Enum;
68314 
68315 /* =======================================================  INTENABLE  ======================================================= */
68316 /* ========================================================  INTSIG  ========================================================= */
68317 /* ============================================  SDIO INTSIG TGTRESPEN [28..28]  ============================================= */
68318 typedef enum {                                  /*!< SDIO_INTSIG_TGTRESPEN                                                     */
68319   SDIO_INTSIG_TGTRESPEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
68320   SDIO_INTSIG_TGTRESPEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
68321 } SDIO_INTSIG_TGTRESPEN_Enum;
68322 
68323 /* ===========================================  SDIO INTSIG TUNINGERREN [26..26]  ============================================ */
68324 typedef enum {                                  /*!< SDIO_INTSIG_TUNINGERREN                                                   */
68325   SDIO_INTSIG_TUNINGERREN_MASKED       = 0,     /*!< MASKED : Masked                                                           */
68326   SDIO_INTSIG_TUNINGERREN_ENABLED      = 1,     /*!< ENABLED : Enabled                                                         */
68327 } SDIO_INTSIG_TUNINGERREN_Enum;
68328 
68329 /* ============================================  SDIO INTSIG ADMAERREN [25..25]  ============================================= */
68330 typedef enum {                                  /*!< SDIO_INTSIG_ADMAERREN                                                     */
68331   SDIO_INTSIG_ADMAERREN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
68332   SDIO_INTSIG_ADMAERREN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
68333 } SDIO_INTSIG_ADMAERREN_Enum;
68334 
68335 /* ==========================================  SDIO INTSIG AUTOCMD12ERREN [24..24]  ========================================== */
68336 typedef enum {                                  /*!< SDIO_INTSIG_AUTOCMD12ERREN                                                */
68337   SDIO_INTSIG_AUTOCMD12ERREN_MASKED    = 0,     /*!< MASKED : Masked                                                           */
68338   SDIO_INTSIG_AUTOCMD12ERREN_ENABLED   = 1,     /*!< ENABLED : Enabled                                                         */
68339 } SDIO_INTSIG_AUTOCMD12ERREN_Enum;
68340 
68341 /* ===========================================  SDIO INTSIG CURRLMTERREN [23..23]  =========================================== */
68342 typedef enum {                                  /*!< SDIO_INTSIG_CURRLMTERREN                                                  */
68343   SDIO_INTSIG_CURRLMTERREN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
68344   SDIO_INTSIG_CURRLMTERREN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
68345 } SDIO_INTSIG_CURRLMTERREN_Enum;
68346 
68347 /* ===========================================  SDIO INTSIG DATAENDERREN [22..22]  =========================================== */
68348 typedef enum {                                  /*!< SDIO_INTSIG_DATAENDERREN                                                  */
68349   SDIO_INTSIG_DATAENDERREN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
68350   SDIO_INTSIG_DATAENDERREN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
68351 } SDIO_INTSIG_DATAENDERREN_Enum;
68352 
68353 /* ===========================================  SDIO INTSIG DATACRCERREN [21..21]  =========================================== */
68354 typedef enum {                                  /*!< SDIO_INTSIG_DATACRCERREN                                                  */
68355   SDIO_INTSIG_DATACRCERREN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
68356   SDIO_INTSIG_DATACRCERREN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
68357 } SDIO_INTSIG_DATACRCERREN_Enum;
68358 
68359 /* ==========================================  SDIO INTSIG DATATOERROREN [20..20]  =========================================== */
68360 typedef enum {                                  /*!< SDIO_INTSIG_DATATOERROREN                                                 */
68361   SDIO_INTSIG_DATATOERROREN_MASKED     = 0,     /*!< MASKED : Masked                                                           */
68362   SDIO_INTSIG_DATATOERROREN_ENABLED    = 1,     /*!< ENABLED : Enabled                                                         */
68363 } SDIO_INTSIG_DATATOERROREN_Enum;
68364 
68365 /* ===========================================  SDIO INTSIG CMDIDXERREN [19..19]  ============================================ */
68366 typedef enum {                                  /*!< SDIO_INTSIG_CMDIDXERREN                                                   */
68367   SDIO_INTSIG_CMDIDXERREN_MASKED       = 0,     /*!< MASKED : Masked                                                           */
68368   SDIO_INTSIG_CMDIDXERREN_ENABLED      = 1,     /*!< ENABLED : Enabled                                                         */
68369 } SDIO_INTSIG_CMDIDXERREN_Enum;
68370 
68371 /* ==========================================  SDIO INTSIG CMDENDBITERREN [18..18]  ========================================== */
68372 typedef enum {                                  /*!< SDIO_INTSIG_CMDENDBITERREN                                                */
68373   SDIO_INTSIG_CMDENDBITERREN_MASKED    = 0,     /*!< MASKED : Masked                                                           */
68374   SDIO_INTSIG_CMDENDBITERREN_ENABLED   = 1,     /*!< ENABLED : Enabled                                                         */
68375 } SDIO_INTSIG_CMDENDBITERREN_Enum;
68376 
68377 /* ===========================================  SDIO INTSIG CMDCRCERREN [17..17]  ============================================ */
68378 typedef enum {                                  /*!< SDIO_INTSIG_CMDCRCERREN                                                   */
68379   SDIO_INTSIG_CMDCRCERREN_MASKED       = 0,     /*!< MASKED : Masked                                                           */
68380   SDIO_INTSIG_CMDCRCERREN_ENABLED      = 1,     /*!< ENABLED : Enabled                                                         */
68381 } SDIO_INTSIG_CMDCRCERREN_Enum;
68382 
68383 /* ============================================  SDIO INTSIG CMDTOERREN [16..16]  ============================================ */
68384 typedef enum {                                  /*!< SDIO_INTSIG_CMDTOERREN                                                    */
68385   SDIO_INTSIG_CMDTOERREN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
68386   SDIO_INTSIG_CMDTOERREN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
68387 } SDIO_INTSIG_CMDTOERREN_Enum;
68388 
68389 /* ==============================================  SDIO INTSIG FIXED0 [15..15]  ============================================== */
68390 typedef enum {                                  /*!< SDIO_INTSIG_FIXED0                                                        */
68391   SDIO_INTSIG_FIXED0_MASKED            = 0,     /*!< MASKED : Masked                                                           */
68392   SDIO_INTSIG_FIXED0_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
68393 } SDIO_INTSIG_FIXED0_Enum;
68394 
68395 /* =============================================  SDIO INTSIG BOOTTERM [14..14]  ============================================= */
68396 typedef enum {                                  /*!< SDIO_INTSIG_BOOTTERM                                                      */
68397   SDIO_INTSIG_BOOTTERM_MASKED          = 0,     /*!< MASKED : Masked                                                           */
68398   SDIO_INTSIG_BOOTTERM_ENABLED         = 1,     /*!< ENABLED : Enabled                                                         */
68399 } SDIO_INTSIG_BOOTTERM_Enum;
68400 
68401 /* ============================================  SDIO INTSIG BOOTACKEN [13..13]  ============================================= */
68402 typedef enum {                                  /*!< SDIO_INTSIG_BOOTACKEN                                                     */
68403   SDIO_INTSIG_BOOTACKEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
68404   SDIO_INTSIG_BOOTACKEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
68405 } SDIO_INTSIG_BOOTACKEN_Enum;
68406 
68407 /* ==========================================  SDIO INTSIG RETUNEEVENTEN [12..12]  =========================================== */
68408 typedef enum {                                  /*!< SDIO_INTSIG_RETUNEEVENTEN                                                 */
68409   SDIO_INTSIG_RETUNEEVENTEN_MASKED     = 0,     /*!< MASKED : Masked                                                           */
68410   SDIO_INTSIG_RETUNEEVENTEN_ENABLED    = 1,     /*!< ENABLED : Enabled                                                         */
68411 } SDIO_INTSIG_RETUNEEVENTEN_Enum;
68412 
68413 /* ==============================================  SDIO INTSIG INTCEN [11..11]  ============================================== */
68414 typedef enum {                                  /*!< SDIO_INTSIG_INTCEN                                                        */
68415   SDIO_INTSIG_INTCEN_MASKED            = 0,     /*!< MASKED : Masked                                                           */
68416   SDIO_INTSIG_INTCEN_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
68417 } SDIO_INTSIG_INTCEN_Enum;
68418 
68419 /* ==============================================  SDIO INTSIG INTBEN [10..10]  ============================================== */
68420 typedef enum {                                  /*!< SDIO_INTSIG_INTBEN                                                        */
68421   SDIO_INTSIG_INTBEN_MASKED            = 0,     /*!< MASKED : Masked                                                           */
68422   SDIO_INTSIG_INTBEN_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
68423 } SDIO_INTSIG_INTBEN_Enum;
68424 
68425 /* ===============================================  SDIO INTSIG INTAEN [9..9]  =============================================== */
68426 typedef enum {                                  /*!< SDIO_INTSIG_INTAEN                                                        */
68427   SDIO_INTSIG_INTAEN_MASKED            = 0,     /*!< MASKED : Masked                                                           */
68428   SDIO_INTSIG_INTAEN_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
68429 } SDIO_INTSIG_INTAEN_Enum;
68430 
68431 /* =============================================  SDIO INTSIG CARDINTEN [8..8]  ============================================== */
68432 typedef enum {                                  /*!< SDIO_INTSIG_CARDINTEN                                                     */
68433   SDIO_INTSIG_CARDINTEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
68434   SDIO_INTSIG_CARDINTEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
68435 } SDIO_INTSIG_CARDINTEN_Enum;
68436 
68437 /* ===========================================  SDIO INTSIG CARDREMOVALEN [7..7]  ============================================ */
68438 typedef enum {                                  /*!< SDIO_INTSIG_CARDREMOVALEN                                                 */
68439   SDIO_INTSIG_CARDREMOVALEN_MASKED     = 0,     /*!< MASKED : Masked                                                           */
68440   SDIO_INTSIG_CARDREMOVALEN_ENABLED    = 1,     /*!< ENABLED : Enabled                                                         */
68441 } SDIO_INTSIG_CARDREMOVALEN_Enum;
68442 
68443 /* ============================================  SDIO INTSIG CARDINSERTEN [6..6]  ============================================ */
68444 typedef enum {                                  /*!< SDIO_INTSIG_CARDINSERTEN                                                  */
68445   SDIO_INTSIG_CARDINSERTEN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
68446   SDIO_INTSIG_CARDINSERTEN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
68447 } SDIO_INTSIG_CARDINSERTEN_Enum;
68448 
68449 /* =============================================  SDIO INTSIG BUFFERRDEN [5..5]  ============================================= */
68450 typedef enum {                                  /*!< SDIO_INTSIG_BUFFERRDEN                                                    */
68451   SDIO_INTSIG_BUFFERRDEN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
68452   SDIO_INTSIG_BUFFERRDEN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
68453 } SDIO_INTSIG_BUFFERRDEN_Enum;
68454 
68455 /* =============================================  SDIO INTSIG BUFFERWREN [4..4]  ============================================= */
68456 typedef enum {                                  /*!< SDIO_INTSIG_BUFFERWREN                                                    */
68457   SDIO_INTSIG_BUFFERWREN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
68458   SDIO_INTSIG_BUFFERWREN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
68459 } SDIO_INTSIG_BUFFERWREN_Enum;
68460 
68461 /* ==============================================  SDIO INTSIG DMAINTEN [3..3]  ============================================== */
68462 typedef enum {                                  /*!< SDIO_INTSIG_DMAINTEN                                                      */
68463   SDIO_INTSIG_DMAINTEN_MASKED          = 0,     /*!< MASKED : Masked                                                           */
68464   SDIO_INTSIG_DMAINTEN_ENABLED         = 1,     /*!< ENABLED : Enabled                                                         */
68465 } SDIO_INTSIG_DMAINTEN_Enum;
68466 
68467 /* =============================================  SDIO INTSIG BLOCKGAPEN [2..2]  ============================================= */
68468 typedef enum {                                  /*!< SDIO_INTSIG_BLOCKGAPEN                                                    */
68469   SDIO_INTSIG_BLOCKGAPEN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
68470   SDIO_INTSIG_BLOCKGAPEN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
68471 } SDIO_INTSIG_BLOCKGAPEN_Enum;
68472 
68473 /* =============================================  SDIO INTSIG XFERCMPEN [1..1]  ============================================== */
68474 typedef enum {                                  /*!< SDIO_INTSIG_XFERCMPEN                                                     */
68475   SDIO_INTSIG_XFERCMPEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
68476   SDIO_INTSIG_XFERCMPEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
68477 } SDIO_INTSIG_XFERCMPEN_Enum;
68478 
68479 /* ==============================================  SDIO INTSIG CMDCMPEN [0..0]  ============================================== */
68480 typedef enum {                                  /*!< SDIO_INTSIG_CMDCMPEN                                                      */
68481   SDIO_INTSIG_CMDCMPEN_MASKED          = 0,     /*!< MASKED : Masked                                                           */
68482   SDIO_INTSIG_CMDCMPEN_ENABLED         = 1,     /*!< ENABLED : Enabled                                                         */
68483 } SDIO_INTSIG_CMDCMPEN_Enum;
68484 
68485 /* =========================================================  AUTO  ========================================================== */
68486 /* ==============================================  SDIO AUTO PRESETEN [31..31]  ============================================== */
68487 typedef enum {                                  /*!< SDIO_AUTO_PRESETEN                                                        */
68488   SDIO_AUTO_PRESETEN_AUTOEN            = 1,     /*!< AUTOEN : Automatic Selection by Preset Value are Enabled                  */
68489   SDIO_AUTO_PRESETEN_HOSTCTRL          = 0,     /*!< HOSTCTRL : SDCLK and Driver Strength are controlled by Host
68490                                                      Driver                                                                    */
68491 } SDIO_AUTO_PRESETEN_Enum;
68492 
68493 /* =============================================  SDIO AUTO ASYNCINTEN [30..30]  ============================================= */
68494 typedef enum {                                  /*!< SDIO_AUTO_ASYNCINTEN                                                      */
68495   SDIO_AUTO_ASYNCINTEN_ENABLED         = 1,     /*!< ENABLED : Enabled,                                                        */
68496   SDIO_AUTO_ASYNCINTEN_DISABLED        = 0,     /*!< DISABLED : Disabled                                                       */
68497 } SDIO_AUTO_ASYNCINTEN_Enum;
68498 
68499 /* ============================================  SDIO AUTO SAMPLCLKSEL [23..23]  ============================================= */
68500 typedef enum {                                  /*!< SDIO_AUTO_SAMPLCLKSEL                                                     */
68501   SDIO_AUTO_SAMPLCLKSEL_TUNEDCLK       = 1,     /*!< TUNEDCLK : Tuned clock is used to sample data                             */
68502   SDIO_AUTO_SAMPLCLKSEL_FIXEDCLK       = 0,     /*!< FIXEDCLK : Fixed clock is used to sample data                             */
68503 } SDIO_AUTO_SAMPLCLKSEL_Enum;
68504 
68505 /* ============================================  SDIO AUTO STARTTUNING [22..22]  ============================================= */
68506 typedef enum {                                  /*!< SDIO_AUTO_STARTTUNING                                                     */
68507   SDIO_AUTO_STARTTUNING_TUNESTART      = 1,     /*!< TUNESTART : Execute Tuning,                                               */
68508   SDIO_AUTO_STARTTUNING_TUNECMP        = 0,     /*!< TUNECMP : Not Tuned or Tuning Completed                                   */
68509 } SDIO_AUTO_STARTTUNING_Enum;
68510 
68511 /* =============================================  SDIO AUTO DRVRSTRSEL [20..21]  ============================================= */
68512 typedef enum {                                  /*!< SDIO_AUTO_DRVRSTRSEL                                                      */
68513   SDIO_AUTO_DRVRSTRSEL_DRVRB           = 0,     /*!< DRVRB : Driver Type B is Selected (Default)                               */
68514   SDIO_AUTO_DRVRSTRSEL_DRVRA           = 1,     /*!< DRVRA : Driver Type A is Selected                                         */
68515   SDIO_AUTO_DRVRSTRSEL_DRVRC           = 2,     /*!< DRVRC : Driver Type C is Selected                                         */
68516   SDIO_AUTO_DRVRSTRSEL_DRVRD           = 3,     /*!< DRVRD : Driver Type D is Selected                                         */
68517 } SDIO_AUTO_DRVRSTRSEL_Enum;
68518 
68519 /* =============================================  SDIO AUTO SIGNALVOLT [19..19]  ============================================= */
68520 typedef enum {                                  /*!< SDIO_AUTO_SIGNALVOLT                                                      */
68521   SDIO_AUTO_SIGNALVOLT_1_8V            = 1,     /*!< 1_8V : 1.8V Signaling                                                     */
68522   SDIO_AUTO_SIGNALVOLT_3_3V            = 0,     /*!< 3_3V : 3.3V Signaling                                                     */
68523 } SDIO_AUTO_SIGNALVOLT_Enum;
68524 
68525 /* =============================================  SDIO AUTO UHSMODESEL [16..18]  ============================================= */
68526 typedef enum {                                  /*!< SDIO_AUTO_UHSMODESEL                                                      */
68527   SDIO_AUTO_UHSMODESEL_SDR12           = 0,     /*!< SDR12 : UHS-I mode SDR12                                                  */
68528   SDIO_AUTO_UHSMODESEL_SDR25           = 1,     /*!< SDR25 : UHS-I mode SDR25                                                  */
68529   SDIO_AUTO_UHSMODESEL_SDR50           = 2,     /*!< SDR50 : UHS-I mode SDR50                                                  */
68530   SDIO_AUTO_UHSMODESEL_SDR104          = 3,     /*!< SDR104 : UHS-I mode SDR104                                                */
68531   SDIO_AUTO_UHSMODESEL_DDR50           = 4,     /*!< DDR50 : UHS-I mode DDR50                                                  */
68532 } SDIO_AUTO_UHSMODESEL_Enum;
68533 
68534 /* ===========================================  SDIO AUTO NOTAUTOCMD12ERR [7..7]  ============================================ */
68535 typedef enum {                                  /*!< SDIO_AUTO_NOTAUTOCMD12ERR                                                 */
68536   SDIO_AUTO_NOTAUTOCMD12ERR_NOERROR    = 0,     /*!< NOERROR : No Error                                                        */
68537   SDIO_AUTO_NOTAUTOCMD12ERR_ERROR      = 1,     /*!< ERROR : Not Issued                                                        */
68538 } SDIO_AUTO_NOTAUTOCMD12ERR_Enum;
68539 
68540 /* ==============================================  SDIO AUTO CMDIDXERR [4..4]  =============================================== */
68541 typedef enum {                                  /*!< SDIO_AUTO_CMDIDXERR                                                       */
68542   SDIO_AUTO_CMDIDXERR_NOERROR          = 0,     /*!< NOERROR : No Error                                                        */
68543   SDIO_AUTO_CMDIDXERR_ERROR            = 1,     /*!< ERROR : Error                                                             */
68544 } SDIO_AUTO_CMDIDXERR_Enum;
68545 
68546 /* ==============================================  SDIO AUTO CMDENDERR [3..3]  =============================================== */
68547 typedef enum {                                  /*!< SDIO_AUTO_CMDENDERR                                                       */
68548   SDIO_AUTO_CMDENDERR_NOERROR          = 0,     /*!< NOERROR : No Error                                                        */
68549   SDIO_AUTO_CMDENDERR_ERROR            = 1,     /*!< ERROR : End Bit Error Generated                                           */
68550 } SDIO_AUTO_CMDENDERR_Enum;
68551 
68552 /* ==============================================  SDIO AUTO CMDCRCERR [2..2]  =============================================== */
68553 typedef enum {                                  /*!< SDIO_AUTO_CMDCRCERR                                                       */
68554   SDIO_AUTO_CMDCRCERR_NOERROR          = 0,     /*!< NOERROR : No Error                                                        */
68555   SDIO_AUTO_CMDCRCERR_ERROR            = 1,     /*!< ERROR : CRC Error Generated                                               */
68556 } SDIO_AUTO_CMDCRCERR_Enum;
68557 
68558 /* ===============================================  SDIO AUTO CMDTOERR [1..1]  =============================================== */
68559 typedef enum {                                  /*!< SDIO_AUTO_CMDTOERR                                                        */
68560   SDIO_AUTO_CMDTOERR_NOERROR           = 0,     /*!< NOERROR : No Error                                                        */
68561   SDIO_AUTO_CMDTOERR_ERROR             = 1,     /*!< ERROR : Timeout                                                           */
68562 } SDIO_AUTO_CMDTOERR_Enum;
68563 
68564 /* =============================================  SDIO AUTO CMD12NOTEXEC [0..0]  ============================================= */
68565 typedef enum {                                  /*!< SDIO_AUTO_CMD12NOTEXEC                                                    */
68566   SDIO_AUTO_CMD12NOTEXEC_EXECUTED      = 0,     /*!< EXECUTED : Executed                                                       */
68567   SDIO_AUTO_CMD12NOTEXEC_NOTEXECUTED   = 1,     /*!< NOTEXECUTED : Not Executed                                                */
68568 } SDIO_AUTO_CMD12NOTEXEC_Enum;
68569 
68570 /* =====================================================  CAPABILITIES0  ===================================================== */
68571 /* =========================================  SDIO CAPABILITIES0 SLOTTYPE [30..31]  ========================================== */
68572 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SLOTTYPE                                               */
68573   SDIO_CAPABILITIES0_SLOTTYPE_REMOVABLE = 0,    /*!< REMOVABLE : Removable card slot                                           */
68574   SDIO_CAPABILITIES0_SLOTTYPE_EMBEDDED = 1,     /*!< EMBEDDED : Embedded Slot for One Device                                   */
68575   SDIO_CAPABILITIES0_SLOTTYPE_SHARED   = 2,     /*!< SHARED : Shared Bus Slot                                                  */
68576 } SDIO_CAPABILITIES0_SLOTTYPE_Enum;
68577 
68578 /* =========================================  SDIO CAPABILITIES0 ASYNCINT [29..29]  ========================================== */
68579 typedef enum {                                  /*!< SDIO_CAPABILITIES0_ASYNCINT                                               */
68580   SDIO_CAPABILITIES0_ASYNCINT_SUPPORTED = 1,    /*!< SUPPORTED : Asynchronous Interrupt Supported                              */
68581   SDIO_CAPABILITIES0_ASYNCINT_NOTSUPPORTED = 0, /*!< NOTSUPPORTED : Asynchronous Interrupt Not Supported                       */
68582 } SDIO_CAPABILITIES0_ASYNCINT_Enum;
68583 
68584 /* =========================================  SDIO CAPABILITIES0 SYSBUS64 [28..28]  ========================================== */
68585 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SYSBUS64                                               */
68586   SDIO_CAPABILITIES0_SYSBUS64_SUPPORTED = 1,    /*!< SUPPORTED : Supports 64 bit system address                                */
68587   SDIO_CAPABILITIES0_SYSBUS64_NOTSUPPORTED = 0, /*!< NOTSUPPORTED : Does not support 64 bit system address                     */
68588 } SDIO_CAPABILITIES0_SYSBUS64_Enum;
68589 
68590 /* ==========================================  SDIO CAPABILITIES0 VOLT18V [26..26]  ========================================== */
68591 typedef enum {                                  /*!< SDIO_CAPABILITIES0_VOLT18V                                                */
68592   SDIO_CAPABILITIES0_VOLT18V_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : 1.8 V Not Supported                                        */
68593   SDIO_CAPABILITIES0_VOLT18V_SUPPORTED = 1,     /*!< SUPPORTED : 1.8 V Supported                                               */
68594 } SDIO_CAPABILITIES0_VOLT18V_Enum;
68595 
68596 /* ==========================================  SDIO CAPABILITIES0 VOLT30V [25..25]  ========================================== */
68597 typedef enum {                                  /*!< SDIO_CAPABILITIES0_VOLT30V                                                */
68598   SDIO_CAPABILITIES0_VOLT30V_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : 3.0 V Not Supported                                        */
68599   SDIO_CAPABILITIES0_VOLT30V_SUPPORTED = 1,     /*!< SUPPORTED : 3.0 V Supported                                               */
68600 } SDIO_CAPABILITIES0_VOLT30V_Enum;
68601 
68602 /* ==========================================  SDIO CAPABILITIES0 VOLT33V [24..24]  ========================================== */
68603 typedef enum {                                  /*!< SDIO_CAPABILITIES0_VOLT33V                                                */
68604   SDIO_CAPABILITIES0_VOLT33V_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : 3.3 V Not Supported                                        */
68605   SDIO_CAPABILITIES0_VOLT33V_SUPPORTED = 1,     /*!< SUPPORTED : 3.3 V Supported                                               */
68606 } SDIO_CAPABILITIES0_VOLT33V_Enum;
68607 
68608 /* ==========================================  SDIO CAPABILITIES0 SUSPRES [23..23]  ========================================== */
68609 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SUSPRES                                                */
68610   SDIO_CAPABILITIES0_SUSPRES_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : Suspend / Resume Not Supported                             */
68611   SDIO_CAPABILITIES0_SUSPRES_SUPPORTED = 1,     /*!< SUPPORTED : Suspend / Resume Supported                                    */
68612 } SDIO_CAPABILITIES0_SUSPRES_Enum;
68613 
68614 /* ===========================================  SDIO CAPABILITIES0 SDMA [22..22]  ============================================ */
68615 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SDMA                                                   */
68616   SDIO_CAPABILITIES0_SDMA_NOTSUPPORTED = 0,     /*!< NOTSUPPORTED : SDMA Not Supported                                         */
68617   SDIO_CAPABILITIES0_SDMA_SUPPORTED    = 1,     /*!< SUPPORTED : SDMA Supported.                                               */
68618 } SDIO_CAPABILITIES0_SDMA_Enum;
68619 
68620 /* =========================================  SDIO CAPABILITIES0 HIGHSPEED [21..21]  ========================================= */
68621 typedef enum {                                  /*!< SDIO_CAPABILITIES0_HIGHSPEED                                              */
68622   SDIO_CAPABILITIES0_HIGHSPEED_NOTSUPPORTED = 0,/*!< NOTSUPPORTED : High Speed Not Supported                                   */
68623   SDIO_CAPABILITIES0_HIGHSPEED_SUPPORTED = 1,   /*!< SUPPORTED : High Speed Supported                                          */
68624 } SDIO_CAPABILITIES0_HIGHSPEED_Enum;
68625 
68626 /* ===========================================  SDIO CAPABILITIES0 ADMA2 [19..19]  =========================================== */
68627 typedef enum {                                  /*!< SDIO_CAPABILITIES0_ADMA2                                                  */
68628   SDIO_CAPABILITIES0_ADMA2_SUPPORTED   = 1,     /*!< SUPPORTED : ADMA2 support.                                                */
68629   SDIO_CAPABILITIES0_ADMA2_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : ADMA2 not support                                          */
68630 } SDIO_CAPABILITIES0_ADMA2_Enum;
68631 
68632 /* =========================================  SDIO CAPABILITIES0 EXTMEDIA [18..18]  ========================================== */
68633 typedef enum {                                  /*!< SDIO_CAPABILITIES0_EXTMEDIA                                               */
68634   SDIO_CAPABILITIES0_EXTMEDIA_SUPPORTED = 1,    /*!< SUPPORTED : Extended Media Bus Supported                                  */
68635   SDIO_CAPABILITIES0_EXTMEDIA_NOTSUPPORTED = 0, /*!< NOTSUPPORTED : Extended Media Bus not supported                           */
68636 } SDIO_CAPABILITIES0_EXTMEDIA_Enum;
68637 
68638 /* =========================================  SDIO CAPABILITIES0 MAXBLKLEN [16..17]  ========================================= */
68639 typedef enum {                                  /*!< SDIO_CAPABILITIES0_MAXBLKLEN                                              */
68640   SDIO_CAPABILITIES0_MAXBLKLEN_512     = 0,     /*!< 512 : 512 byte                                                            */
68641   SDIO_CAPABILITIES0_MAXBLKLEN_1024    = 1,     /*!< 1024 : 1024 byte                                                          */
68642   SDIO_CAPABILITIES0_MAXBLKLEN_2048    = 2,     /*!< 2048 : 2048 byte                                                          */
68643   SDIO_CAPABILITIES0_MAXBLKLEN_4096    = 3,     /*!< 4096 : 4096 byte                                                          */
68644 } SDIO_CAPABILITIES0_MAXBLKLEN_Enum;
68645 
68646 /* =========================================  SDIO CAPABILITIES0 SDCLKFREQ [8..15]  ========================================== */
68647 typedef enum {                                  /*!< SDIO_CAPABILITIES0_SDCLKFREQ                                              */
68648   SDIO_CAPABILITIES0_SDCLKFREQ_255MHZ  = 255,   /*!< 255MHZ : 2) 8-bit base clock frequency supports frequencies
68649                                                      10MHz-255MHz.                                                             */
68650   SDIO_CAPABILITIES0_SDCLKFREQ_63MHZ   = 63,    /*!< 63MHZ : 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz.
68651                                                      2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.          */
68652   SDIO_CAPABILITIES0_SDCLKFREQ_2MHZ    = 2,     /*!< 2MHZ : 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz.
68653                                                      2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.          */
68654   SDIO_CAPABILITIES0_SDCLKFREQ_1MHZ    = 1,     /*!< 1MHZ : 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz.
68655                                                      2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.          */
68656   SDIO_CAPABILITIES0_SDCLKFREQ_OTHER   = 0,     /*!< OTHER : Get information via another method                                */
68657 } SDIO_CAPABILITIES0_SDCLKFREQ_Enum;
68658 
68659 /* ==========================================  SDIO CAPABILITIES0 TOCLKUNIT [7..7]  ========================================== */
68660 typedef enum {                                  /*!< SDIO_CAPABILITIES0_TOCLKUNIT                                              */
68661   SDIO_CAPABILITIES0_TOCLKUNIT_KHZ     = 0,     /*!< KHZ : Khz                                                                 */
68662   SDIO_CAPABILITIES0_TOCLKUNIT_MHZ     = 1,     /*!< MHZ : Mhz                                                                 */
68663 } SDIO_CAPABILITIES0_TOCLKUNIT_Enum;
68664 
68665 /* ==========================================  SDIO CAPABILITIES0 TOCLKFREQ [0..5]  ========================================== */
68666 typedef enum {                                  /*!< SDIO_CAPABILITIES0_TOCLKFREQ                                              */
68667   SDIO_CAPABILITIES0_TOCLKFREQ_1       = 1,     /*!< 1 : 1KHZ or 1MHZ                                                          */
68668   SDIO_CAPABILITIES0_TOCLKFREQ_2       = 2,     /*!< 2 : 2KHZ or 2MHZ                                                          */
68669   SDIO_CAPABILITIES0_TOCLKFREQ_63      = 63,    /*!< 63 : 63KHZ or 63MHZ                                                       */
68670   SDIO_CAPABILITIES0_TOCLKFREQ_OTHER   = 0,     /*!< OTHER : Get Information via another method.                               */
68671 } SDIO_CAPABILITIES0_TOCLKFREQ_Enum;
68672 
68673 /* =====================================================  CAPABILITIES1  ===================================================== */
68674 /* =======================================  SDIO CAPABILITIES1 SPIBLOCKMODE [25..25]  ======================================== */
68675 typedef enum {                                  /*!< SDIO_CAPABILITIES1_SPIBLOCKMODE                                           */
68676   SDIO_CAPABILITIES1_SPIBLOCKMODE_NOTSUPPORTED = 0,/*!< NOTSUPPORTED : Not Supported                                           */
68677   SDIO_CAPABILITIES1_SPIBLOCKMODE_SUPPORTED = 1,/*!< SUPPORTED : Supported                                                     */
68678 } SDIO_CAPABILITIES1_SPIBLOCKMODE_Enum;
68679 
68680 /* ==========================================  SDIO CAPABILITIES1 SPIMODE [24..24]  ========================================== */
68681 typedef enum {                                  /*!< SDIO_CAPABILITIES1_SPIMODE                                                */
68682   SDIO_CAPABILITIES1_SPIMODE_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : Not Supported                                              */
68683   SDIO_CAPABILITIES1_SPIMODE_SUPPORTED = 1,     /*!< SUPPORTED : Supported                                                     */
68684 } SDIO_CAPABILITIES1_SPIMODE_Enum;
68685 
68686 /* ==========================================  SDIO CAPABILITIES1 CLKMULT [16..23]  ========================================== */
68687 typedef enum {                                  /*!< SDIO_CAPABILITIES1_CLKMULT                                                */
68688   SDIO_CAPABILITIES1_CLKMULT_MULTX256  = 255,   /*!< MULTX256 : Clock Multiplier M = 256                                       */
68689   SDIO_CAPABILITIES1_CLKMULT_MULTX3    = 2,     /*!< MULTX3 : Clock Multiplier M = 3                                           */
68690   SDIO_CAPABILITIES1_CLKMULT_MULTX2    = 1,     /*!< MULTX2 : Clock Multiplier M = 2                                           */
68691   SDIO_CAPABILITIES1_CLKMULT_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : Clock Multiplier is Not Supported                          */
68692 } SDIO_CAPABILITIES1_CLKMULT_Enum;
68693 
68694 /* =======================================  SDIO CAPABILITIES1 RETUNINGMODES [14..15]  ======================================= */
68695 typedef enum {                                  /*!< SDIO_CAPABILITIES1_RETUNINGMODES                                          */
68696   SDIO_CAPABILITIES1_RETUNINGMODES_MODE1 = 0,   /*!< MODE1 : Mode1                                                             */
68697   SDIO_CAPABILITIES1_RETUNINGMODES_MODE2 = 1,   /*!< MODE2 : Mode2                                                             */
68698   SDIO_CAPABILITIES1_RETUNINGMODES_MODE3 = 2,   /*!< MODE3 : Mode3                                                             */
68699   SDIO_CAPABILITIES1_RETUNINGMODES_NOTSUPPORTED = 3,/*!< NOTSUPPORTED : Clock Multiplier is not supported.                     */
68700 } SDIO_CAPABILITIES1_RETUNINGMODES_Enum;
68701 
68702 /* ========================================  SDIO CAPABILITIES1 TUNINGSDR50 [13..13]  ======================================== */
68703 typedef enum {                                  /*!< SDIO_CAPABILITIES1_TUNINGSDR50                                            */
68704   SDIO_CAPABILITIES1_TUNINGSDR50_TUNINGREQD = 1,/*!< TUNINGREQD : SDR50 requires tuning                                        */
68705   SDIO_CAPABILITIES1_TUNINGSDR50_NOTUNINGREQD = 0,/*!< NOTUNINGREQD : SDR50 does not require tuning                            */
68706 } SDIO_CAPABILITIES1_TUNINGSDR50_Enum;
68707 
68708 /* =======================================  SDIO CAPABILITIES1 RETUNINGTMRCNT [8..11]  ======================================= */
68709 typedef enum {                                  /*!< SDIO_CAPABILITIES1_RETUNINGTMRCNT                                         */
68710   SDIO_CAPABILITIES1_RETUNINGTMRCNT_OTHER = 0,  /*!< OTHER : 0h Get information via other source.                              */
68711   SDIO_CAPABILITIES1_RETUNINGTMRCNT_1SEC = 1,   /*!< 1SEC : 1 seconds                                                          */
68712   SDIO_CAPABILITIES1_RETUNINGTMRCNT_2SEC = 2,   /*!< 2SEC : 2 seconds                                                          */
68713   SDIO_CAPABILITIES1_RETUNINGTMRCNT_4SEC = 3,   /*!< 4SEC : 4 seconds                                                          */
68714   SDIO_CAPABILITIES1_RETUNINGTMRCNT_8S = 4,     /*!< 8S : 8 seconds                                                            */
68715   SDIO_CAPABILITIES1_RETUNINGTMRCNT_16S = 5,    /*!< 16S : 16 seconds                                                          */
68716   SDIO_CAPABILITIES1_RETUNINGTMRCNT_32S = 6,    /*!< 32S : 32 seconds                                                          */
68717   SDIO_CAPABILITIES1_RETUNINGTMRCNT_64S = 7,    /*!< 64S : 64 seconds                                                          */
68718   SDIO_CAPABILITIES1_RETUNINGTMRCNT_128S = 8,   /*!< 128S : 128 seconds                                                        */
68719   SDIO_CAPABILITIES1_RETUNINGTMRCNT_256S = 9,   /*!< 256S : 256 seconds                                                        */
68720   SDIO_CAPABILITIES1_RETUNINGTMRCNT_512S = 10,  /*!< 512S : 512 seconds                                                        */
68721   SDIO_CAPABILITIES1_RETUNINGTMRCNT_1024S = 11, /*!< 1024S : 1024 seconds                                                      */
68722 } SDIO_CAPABILITIES1_RETUNINGTMRCNT_Enum;
68723 
68724 /* ============================================  SDIO CAPABILITIES1 TYPED [6..6]  ============================================ */
68725 typedef enum {                                  /*!< SDIO_CAPABILITIES1_TYPED                                                  */
68726   SDIO_CAPABILITIES1_TYPED_SUPPORTED   = 1,     /*!< SUPPORTED : Driver Type D is Supported                                    */
68727   SDIO_CAPABILITIES1_TYPED_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : Driver Type D is Not Supported                             */
68728 } SDIO_CAPABILITIES1_TYPED_Enum;
68729 
68730 /* ============================================  SDIO CAPABILITIES1 TYPEC [5..5]  ============================================ */
68731 typedef enum {                                  /*!< SDIO_CAPABILITIES1_TYPEC                                                  */
68732   SDIO_CAPABILITIES1_TYPEC_SUPPORTED   = 1,     /*!< SUPPORTED : Driver Type C is Supported                                    */
68733   SDIO_CAPABILITIES1_TYPEC_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : Driver Type C is Not Supported                             */
68734 } SDIO_CAPABILITIES1_TYPEC_Enum;
68735 
68736 /* ============================================  SDIO CAPABILITIES1 TYPEA [4..4]  ============================================ */
68737 typedef enum {                                  /*!< SDIO_CAPABILITIES1_TYPEA                                                  */
68738   SDIO_CAPABILITIES1_TYPEA_SUPPORTED   = 1,     /*!< SUPPORTED : Driver Type A is Supported                                    */
68739   SDIO_CAPABILITIES1_TYPEA_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : Driver Type A is Not Supported                             */
68740 } SDIO_CAPABILITIES1_TYPEA_Enum;
68741 
68742 /* ============================================  SDIO CAPABILITIES1 DDR50 [2..2]  ============================================ */
68743 typedef enum {                                  /*!< SDIO_CAPABILITIES1_DDR50                                                  */
68744   SDIO_CAPABILITIES1_DDR50_SUPPORTED   = 1,     /*!< SUPPORTED : DDR50 is Supported                                            */
68745   SDIO_CAPABILITIES1_DDR50_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : DDR50 is Not Supported                                     */
68746 } SDIO_CAPABILITIES1_DDR50_Enum;
68747 
68748 /* ===========================================  SDIO CAPABILITIES1 SDR104 [1..1]  ============================================ */
68749 typedef enum {                                  /*!< SDIO_CAPABILITIES1_SDR104                                                 */
68750   SDIO_CAPABILITIES1_SDR104_SUPPORTED  = 1,     /*!< SUPPORTED : SDR104 is Not Supported                                       */
68751   SDIO_CAPABILITIES1_SDR104_NOTSUPPORTED = 0,   /*!< NOTSUPPORTED : SDR104 is Not Supported                                    */
68752 } SDIO_CAPABILITIES1_SDR104_Enum;
68753 
68754 /* ============================================  SDIO CAPABILITIES1 SDR50 [0..0]  ============================================ */
68755 typedef enum {                                  /*!< SDIO_CAPABILITIES1_SDR50                                                  */
68756   SDIO_CAPABILITIES1_SDR50_SUPPORTED   = 1,     /*!< SUPPORTED : SDR50 is Not Supported                                        */
68757   SDIO_CAPABILITIES1_SDR50_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : SDR50 is Not Supported                                     */
68758 } SDIO_CAPABILITIES1_SDR50_Enum;
68759 
68760 /* =======================================================  MAXIMUM0  ======================================================== */
68761 /* =======================================================  MAXIMUM1  ======================================================== */
68762 /* ===========================================  SDIO MAXIMUM1 MAXCURR18V [16..23]  =========================================== */
68763 typedef enum {                                  /*!< SDIO_MAXIMUM1_MAXCURR18V                                                  */
68764   SDIO_MAXIMUM1_MAXCURR18V_1020mA      = 255,   /*!< 1020mA : 1020mA = 255 * 4mA                                               */
68765   SDIO_MAXIMUM1_MAXCURR18V_4mA         = 1,     /*!< 4mA : 1020mA, 255 * 4mA                                                   */
68766 } SDIO_MAXIMUM1_MAXCURR18V_Enum;
68767 
68768 /* ===========================================  SDIO MAXIMUM1 MAXCURR30V [8..15]  ============================================ */
68769 typedef enum {                                  /*!< SDIO_MAXIMUM1_MAXCURR30V                                                  */
68770   SDIO_MAXIMUM1_MAXCURR30V_1020mA      = 255,   /*!< 1020mA : 1020mA = 255 * 4mA                                               */
68771   SDIO_MAXIMUM1_MAXCURR30V_4mA         = 1,     /*!< 4mA : 1020mA, 255 * 4mA                                                   */
68772 } SDIO_MAXIMUM1_MAXCURR30V_Enum;
68773 
68774 /* ============================================  SDIO MAXIMUM1 MAXCURR33V [0..7]  ============================================ */
68775 typedef enum {                                  /*!< SDIO_MAXIMUM1_MAXCURR33V                                                  */
68776   SDIO_MAXIMUM1_MAXCURR33V_1020mA      = 255,   /*!< 1020mA : 1020mA = 255 * 4mA                                               */
68777   SDIO_MAXIMUM1_MAXCURR33V_4mA         = 1,     /*!< 4mA : 1020mA, 255 * 4mA                                                   */
68778 } SDIO_MAXIMUM1_MAXCURR33V_Enum;
68779 
68780 /* =========================================================  FORCE  ========================================================= */
68781 /* ===========================================  SDIO FORCE FORCEADMAERR [25..25]  ============================================ */
68782 typedef enum {                                  /*!< SDIO_FORCE_FORCEADMAERR                                                   */
68783   SDIO_FORCE_FORCEADMAERR_INT          = 1,     /*!< INT : Interrupt is generated                                              */
68784   SDIO_FORCE_FORCEADMAERR_NOINT        = 0,     /*!< NOINT : No interrupt                                                      */
68785 } SDIO_FORCE_FORCEADMAERR_Enum;
68786 
68787 /* ===========================================  SDIO FORCE FORCEACMDERR [24..24]  ============================================ */
68788 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDERR                                                   */
68789   SDIO_FORCE_FORCEACMDERR_INT          = 1,     /*!< INT : Interrupt is generated                                              */
68790   SDIO_FORCE_FORCEACMDERR_NOINT        = 0,     /*!< NOINT : No interrupt                                                      */
68791 } SDIO_FORCE_FORCEACMDERR_Enum;
68792 
68793 /* =========================================  SDIO FORCE FORCECURRLIMITERR [23..23]  ========================================= */
68794 typedef enum {                                  /*!< SDIO_FORCE_FORCECURRLIMITERR                                              */
68795   SDIO_FORCE_FORCECURRLIMITERR_INT     = 1,     /*!< INT : Interrupt is generated                                              */
68796   SDIO_FORCE_FORCECURRLIMITERR_NOINT   = 0,     /*!< NOINT : No interrupt                                                      */
68797 } SDIO_FORCE_FORCECURRLIMITERR_Enum;
68798 
68799 /* ==========================================  SDIO FORCE FORCEDATAENDERR [22..22]  ========================================== */
68800 typedef enum {                                  /*!< SDIO_FORCE_FORCEDATAENDERR                                                */
68801   SDIO_FORCE_FORCEDATAENDERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
68802   SDIO_FORCE_FORCEDATAENDERR_NOINT     = 0,     /*!< NOINT : No interrupt                                                      */
68803 } SDIO_FORCE_FORCEDATAENDERR_Enum;
68804 
68805 /* ==========================================  SDIO FORCE FORCEDATACRCERR [21..21]  ========================================== */
68806 typedef enum {                                  /*!< SDIO_FORCE_FORCEDATACRCERR                                                */
68807   SDIO_FORCE_FORCEDATACRCERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
68808   SDIO_FORCE_FORCEDATACRCERR_NOINT     = 0,     /*!< NOINT : No interrupt                                                      */
68809 } SDIO_FORCE_FORCEDATACRCERR_Enum;
68810 
68811 /* ==========================================  SDIO FORCE FORCEDATATOERR [20..20]  =========================================== */
68812 typedef enum {                                  /*!< SDIO_FORCE_FORCEDATATOERR                                                 */
68813   SDIO_FORCE_FORCEDATATOERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
68814   SDIO_FORCE_FORCEDATATOERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
68815 } SDIO_FORCE_FORCEDATATOERR_Enum;
68816 
68817 /* ==========================================  SDIO FORCE FORCECMDIDXERR [19..19]  =========================================== */
68818 typedef enum {                                  /*!< SDIO_FORCE_FORCECMDIDXERR                                                 */
68819   SDIO_FORCE_FORCECMDIDXERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
68820   SDIO_FORCE_FORCECMDIDXERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
68821 } SDIO_FORCE_FORCECMDIDXERR_Enum;
68822 
68823 /* ==========================================  SDIO FORCE FORCECMDENDERR [18..18]  =========================================== */
68824 typedef enum {                                  /*!< SDIO_FORCE_FORCECMDENDERR                                                 */
68825   SDIO_FORCE_FORCECMDENDERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
68826   SDIO_FORCE_FORCECMDENDERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
68827 } SDIO_FORCE_FORCECMDENDERR_Enum;
68828 
68829 /* ==========================================  SDIO FORCE FORCECMDCRCERR [17..17]  =========================================== */
68830 typedef enum {                                  /*!< SDIO_FORCE_FORCECMDCRCERR                                                 */
68831   SDIO_FORCE_FORCECMDCRCERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
68832   SDIO_FORCE_FORCECMDCRCERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
68833 } SDIO_FORCE_FORCECMDCRCERR_Enum;
68834 
68835 /* ===========================================  SDIO FORCE FORCECMDTOERR [16..16]  =========================================== */
68836 typedef enum {                                  /*!< SDIO_FORCE_FORCECMDTOERR                                                  */
68837   SDIO_FORCE_FORCECMDTOERR_INT         = 1,     /*!< INT : Interrupt is generated                                              */
68838   SDIO_FORCE_FORCECMDTOERR_NOINT       = 0,     /*!< NOINT : No interrupt                                                      */
68839 } SDIO_FORCE_FORCECMDTOERR_Enum;
68840 
68841 /* =========================================  SDIO FORCE FORCEACMDISSUEDERR [7..7]  ========================================== */
68842 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDISSUEDERR                                             */
68843   SDIO_FORCE_FORCEACMDISSUEDERR_INT    = 1,     /*!< INT : Interrupt is generated                                              */
68844   SDIO_FORCE_FORCEACMDISSUEDERR_NOINT  = 0,     /*!< NOINT : no interrupt                                                      */
68845 } SDIO_FORCE_FORCEACMDISSUEDERR_Enum;
68846 
68847 /* ===========================================  SDIO FORCE FORCEACMDIDXERR [4..4]  =========================================== */
68848 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDIDXERR                                                */
68849   SDIO_FORCE_FORCEACMDIDXERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
68850   SDIO_FORCE_FORCEACMDIDXERR_NOINT     = 0,     /*!< NOINT : no interrupt                                                      */
68851 } SDIO_FORCE_FORCEACMDIDXERR_Enum;
68852 
68853 /* ===========================================  SDIO FORCE FORCEACMDENDERR [3..3]  =========================================== */
68854 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDENDERR                                                */
68855   SDIO_FORCE_FORCEACMDENDERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
68856   SDIO_FORCE_FORCEACMDENDERR_NOINT     = 0,     /*!< NOINT : no interrupt                                                      */
68857 } SDIO_FORCE_FORCEACMDENDERR_Enum;
68858 
68859 /* ===========================================  SDIO FORCE FORCEACMDCRCERR [2..2]  =========================================== */
68860 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDCRCERR                                                */
68861   SDIO_FORCE_FORCEACMDCRCERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
68862   SDIO_FORCE_FORCEACMDCRCERR_NOINT     = 0,     /*!< NOINT : no interrupt                                                      */
68863 } SDIO_FORCE_FORCEACMDCRCERR_Enum;
68864 
68865 /* ===========================================  SDIO FORCE FORCEACMDTOERR [1..1]  ============================================ */
68866 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDTOERR                                                 */
68867   SDIO_FORCE_FORCEACMDTOERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
68868   SDIO_FORCE_FORCEACMDTOERR_NOINT      = 0,     /*!< NOINT : no interrupt                                                      */
68869 } SDIO_FORCE_FORCEACMDTOERR_Enum;
68870 
68871 /* ===========================================  SDIO FORCE FORCEACMD12NOT [0..0]  ============================================ */
68872 typedef enum {                                  /*!< SDIO_FORCE_FORCEACMD12NOT                                                 */
68873   SDIO_FORCE_FORCEACMD12NOT_INT        = 1,     /*!< INT : Interrupt is generated                                              */
68874   SDIO_FORCE_FORCEACMD12NOT_NOINT      = 0,     /*!< NOINT : no interrupt                                                      */
68875 } SDIO_FORCE_FORCEACMD12NOT_Enum;
68876 
68877 /* =========================================================  ADMA  ========================================================== */
68878 /* ==========================================  SDIO ADMA ADMALENMISMATCHERR [2..2]  ========================================== */
68879 typedef enum {                                  /*!< SDIO_ADMA_ADMALENMISMATCHERR                                              */
68880   SDIO_ADMA_ADMALENMISMATCHERR_ERROR   = 1,     /*!< ERROR : Error                                                             */
68881   SDIO_ADMA_ADMALENMISMATCHERR_NOERROR = 0,     /*!< NOERROR : No error                                                        */
68882 } SDIO_ADMA_ADMALENMISMATCHERR_Enum;
68883 
68884 /* ============================================  SDIO ADMA ADMAERRORSTATE [0..1]  ============================================ */
68885 typedef enum {                                  /*!< SDIO_ADMA_ADMAERRORSTATE                                                  */
68886   SDIO_ADMA_ADMAERRORSTATE_STDMA       = 0,     /*!< STDMA : ST_STOP (Stop DMA) Points to next of the error descriptor         */
68887   SDIO_ADMA_ADMAERRORSTATE_FETCHDESC   = 1,     /*!< FETCHDESC : ST_FDS (Fetch Descriptor) Points to the error descriptor      */
68888   SDIO_ADMA_ADMAERRORSTATE_INVALID     = 2,     /*!< INVALID : Never set this state (Not used)                                 */
68889   SDIO_ADMA_ADMAERRORSTATE_XFERDATA    = 3,     /*!< XFERDATA : ST_TFR (Transfer Data) Points to the next of the
68890                                                      error descriptor                                                          */
68891 } SDIO_ADMA_ADMAERRORSTATE_Enum;
68892 
68893 /* =======================================================  ADMALOWD  ======================================================== */
68894 /* =======================================================  ADMAHIWD  ======================================================== */
68895 /* ========================================================  PRESET0  ======================================================== */
68896 /* =========================================  SDIO PRESET0 DEFSPDRVRSTRSEL [30..31]  ========================================= */
68897 typedef enum {                                  /*!< SDIO_PRESET0_DEFSPDRVRSTRSEL                                              */
68898   SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
68899   SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
68900   SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
68901   SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
68902 } SDIO_PRESET0_DEFSPDRVRSTRSEL_Enum;
68903 
68904 /* =========================================  SDIO PRESET0 DEFSPCLKGENSEL [26..26]  ========================================== */
68905 typedef enum {                                  /*!< SDIO_PRESET0_DEFSPCLKGENSEL                                               */
68906   SDIO_PRESET0_DEFSPCLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
68907   SDIO_PRESET0_DEFSPCLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
68908 } SDIO_PRESET0_DEFSPCLKGENSEL_Enum;
68909 
68910 /* =========================================  SDIO PRESET0 HISPDRVRSTRSEL [14..15]  ========================================== */
68911 typedef enum {                                  /*!< SDIO_PRESET0_HISPDRVRSTRSEL                                               */
68912   SDIO_PRESET0_HISPDRVRSTRSEL_TYPED    = 3,     /*!< TYPED : Driver Type D is Selected                                         */
68913   SDIO_PRESET0_HISPDRVRSTRSEL_TYPEC    = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
68914   SDIO_PRESET0_HISPDRVRSTRSEL_TYPEA    = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
68915   SDIO_PRESET0_HISPDRVRSTRSEL_TYPEB    = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
68916 } SDIO_PRESET0_HISPDRVRSTRSEL_Enum;
68917 
68918 /* ==========================================  SDIO PRESET0 HISPCLKGENSEL [10..10]  ========================================== */
68919 typedef enum {                                  /*!< SDIO_PRESET0_HISPCLKGENSEL                                                */
68920   SDIO_PRESET0_HISPCLKGENSEL_PROGCLK   = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
68921   SDIO_PRESET0_HISPCLKGENSEL_HOSTCTLR  = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
68922 } SDIO_PRESET0_HISPCLKGENSEL_Enum;
68923 
68924 /* ========================================================  PRESET1  ======================================================== */
68925 /* =========================================  SDIO PRESET1 SDR12DRVRSTRSEL [30..31]  ========================================= */
68926 typedef enum {                                  /*!< SDIO_PRESET1_SDR12DRVRSTRSEL                                              */
68927   SDIO_PRESET1_SDR12DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
68928   SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
68929   SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
68930   SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
68931 } SDIO_PRESET1_SDR12DRVRSTRSEL_Enum;
68932 
68933 /* =========================================  SDIO PRESET1 SDR12CLKGENSEL [26..26]  ========================================== */
68934 typedef enum {                                  /*!< SDIO_PRESET1_SDR12CLKGENSEL                                               */
68935   SDIO_PRESET1_SDR12CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
68936   SDIO_PRESET1_SDR12CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
68937 } SDIO_PRESET1_SDR12CLKGENSEL_Enum;
68938 
68939 /* ==========================================  SDIO PRESET1 HSDRVRSTRSEL [14..15]  =========================================== */
68940 typedef enum {                                  /*!< SDIO_PRESET1_HSDRVRSTRSEL                                                 */
68941   SDIO_PRESET1_HSDRVRSTRSEL_TYPED      = 3,     /*!< TYPED : Driver Type D is Selected                                         */
68942   SDIO_PRESET1_HSDRVRSTRSEL_TYPEC      = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
68943   SDIO_PRESET1_HSDRVRSTRSEL_TYPEA      = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
68944   SDIO_PRESET1_HSDRVRSTRSEL_TYPEB      = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
68945 } SDIO_PRESET1_HSDRVRSTRSEL_Enum;
68946 
68947 /* ===========================================  SDIO PRESET1 HSCLKGENSEL [10..10]  =========================================== */
68948 typedef enum {                                  /*!< SDIO_PRESET1_HSCLKGENSEL                                                  */
68949   SDIO_PRESET1_HSCLKGENSEL_PROGCLK     = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
68950   SDIO_PRESET1_HSCLKGENSEL_HOSTCTLR    = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
68951 } SDIO_PRESET1_HSCLKGENSEL_Enum;
68952 
68953 /* ========================================================  PRESET2  ======================================================== */
68954 /* =========================================  SDIO PRESET2 SDR50DRVRSTRSEL [30..31]  ========================================= */
68955 typedef enum {                                  /*!< SDIO_PRESET2_SDR50DRVRSTRSEL                                              */
68956   SDIO_PRESET2_SDR50DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
68957   SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
68958   SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
68959   SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
68960 } SDIO_PRESET2_SDR50DRVRSTRSEL_Enum;
68961 
68962 /* =========================================  SDIO PRESET2 SDR50CLKGENSEL [26..26]  ========================================== */
68963 typedef enum {                                  /*!< SDIO_PRESET2_SDR50CLKGENSEL                                               */
68964   SDIO_PRESET2_SDR50CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
68965   SDIO_PRESET2_SDR50CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
68966 } SDIO_PRESET2_SDR50CLKGENSEL_Enum;
68967 
68968 /* =========================================  SDIO PRESET2 SDR25DRVRSTRSEL [14..15]  ========================================= */
68969 typedef enum {                                  /*!< SDIO_PRESET2_SDR25DRVRSTRSEL                                              */
68970   SDIO_PRESET2_SDR25DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
68971   SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
68972   SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
68973   SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
68974 } SDIO_PRESET2_SDR25DRVRSTRSEL_Enum;
68975 
68976 /* =========================================  SDIO PRESET2 SDR25CLKGENSEL [10..10]  ========================================== */
68977 typedef enum {                                  /*!< SDIO_PRESET2_SDR25CLKGENSEL                                               */
68978   SDIO_PRESET2_SDR25CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
68979   SDIO_PRESET2_SDR25CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
68980 } SDIO_PRESET2_SDR25CLKGENSEL_Enum;
68981 
68982 /* ========================================================  PRESET3  ======================================================== */
68983 /* =========================================  SDIO PRESET3 DDR50DRVRSTRSEL [30..31]  ========================================= */
68984 typedef enum {                                  /*!< SDIO_PRESET3_DDR50DRVRSTRSEL                                              */
68985   SDIO_PRESET3_DDR50DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
68986   SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
68987   SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
68988   SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
68989 } SDIO_PRESET3_DDR50DRVRSTRSEL_Enum;
68990 
68991 /* =========================================  SDIO PRESET3 DDR50CLKGENSEL [26..26]  ========================================== */
68992 typedef enum {                                  /*!< SDIO_PRESET3_DDR50CLKGENSEL                                               */
68993   SDIO_PRESET3_DDR50CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
68994   SDIO_PRESET3_DDR50CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
68995 } SDIO_PRESET3_DDR50CLKGENSEL_Enum;
68996 
68997 /* ========================================  SDIO PRESET3 SDR104DRVRSTRSEL [14..15]  ========================================= */
68998 typedef enum {                                  /*!< SDIO_PRESET3_SDR104DRVRSTRSEL                                             */
68999   SDIO_PRESET3_SDR104DRVRSTRSEL_TYPED  = 3,     /*!< TYPED : Driver Type D is Selected                                         */
69000   SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEC  = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
69001   SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEA  = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
69002   SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEB  = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
69003 } SDIO_PRESET3_SDR104DRVRSTRSEL_Enum;
69004 
69005 /* =========================================  SDIO PRESET3 SDR104CLKGENSEL [10..10]  ========================================= */
69006 typedef enum {                                  /*!< SDIO_PRESET3_SDR104CLKGENSEL                                              */
69007   SDIO_PRESET3_SDR104CLKGENSEL_PROGCLK = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
69008   SDIO_PRESET3_SDR104CLKGENSEL_HOSTCTLR = 0,    /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
69009 } SDIO_PRESET3_SDR104CLKGENSEL_Enum;
69010 
69011 /* ======================================================  BOOTTOCTRL  ======================================================= */
69012 /* ========================================================  VENDOR  ========================================================= */
69013 /* ===============================================  SDIO VENDOR DLYDIS [1..1]  =============================================== */
69014 typedef enum {                                  /*!< SDIO_VENDOR_DLYDIS                                                        */
69015   SDIO_VENDOR_DLYDIS_DISABLE           = 1,     /*!< DISABLE : Disable the rtl fix made to delay the sampling of
69016                                                      cmd_in and data_in                                                        */
69017   SDIO_VENDOR_DLYDIS_ENABLE            = 0,     /*!< ENABLE : Enable the rtl fix made to delay the sampling of cmd_in
69018                                                      and data_in                                                               */
69019 } SDIO_VENDOR_DLYDIS_Enum;
69020 
69021 /* ============================================  SDIO VENDOR GATESDCLKEN [0..0]  ============================================= */
69022 typedef enum {                                  /*!< SDIO_VENDOR_GATESDCLKEN                                                   */
69023   SDIO_VENDOR_GATESDCLKEN_GATE         = 1,     /*!< GATE : SD_CLK to card will be gated automatically when there
69024                                                      is no transfer.                                                           */
69025   SDIO_VENDOR_GATESDCLKEN_NOGATE       = 0,     /*!< NOGATE : SD_CLK to card will NOT be gated automatically when
69026                                                      there is no transfer.                                                     */
69027 } SDIO_VENDOR_GATESDCLKEN_Enum;
69028 
69029 /* =======================================================  SLOTSTAT  ======================================================== */
69030 
69031 
69032 /* =========================================================================================================================== */
69033 /* ================                                         SECURITY                                          ================ */
69034 /* =========================================================================================================================== */
69035 
69036 /* =========================================================  CTRL  ========================================================== */
69037 /* =============================================  SECURITY CTRL FUNCTION [4..7]  ============================================= */
69038 typedef enum {                                  /*!< SECURITY_CTRL_FUNCTION                                                    */
69039   SECURITY_CTRL_FUNCTION_CRC32         = 0,     /*!< CRC32 : Perform CRC32 operation                                           */
69040   SECURITY_CTRL_FUNCTION_RAND          = 1,     /*!< RAND : DMA pseudo-random number stream based on CRC value                 */
69041   SECURITY_CTRL_FUNCTION_GENADDR       = 2,     /*!< GENADDR : Generate DMA stream based on address                            */
69042 } SECURITY_CTRL_FUNCTION_Enum;
69043 
69044 /* ========================================================  SRCADDR  ======================================================== */
69045 /* ==========================================================  LEN  ========================================================== */
69046 /* ========================================================  RESULT  ========================================================= */
69047 /* =======================================================  LOCKCTRL  ======================================================== */
69048 /* ============================================  SECURITY LOCKCTRL SELECT [0..7]  ============================================ */
69049 typedef enum {                                  /*!< SECURITY_LOCKCTRL_SELECT                                                  */
69050   SECURITY_LOCKCTRL_SELECT_LOCK01      = 1,     /*!< LOCK01 : Enable customer OTP program.                                     */
69051   SECURITY_LOCKCTRL_SELECT_LOCK02      = 2,     /*!< LOCK02 : Enable customer OTP read.                                        */
69052   SECURITY_LOCKCTRL_SELECT_LOCK11      = 17,    /*!< LOCK11 : Enable Ambiq OTP program.                                        */
69053   SECURITY_LOCKCTRL_SELECT_LOCK12      = 18,    /*!< LOCK12 : Enable Ambiq OTP read.                                           */
69054   SECURITY_LOCKCTRL_SELECT_LOCK9D      = 157,   /*!< LOCK9D : Enable Bootloader Recovery.                                      */
69055   SECURITY_LOCKCTRL_SELECT_LOCK9E      = 158,   /*!< LOCK9E : Enable Bootloader info1.                                         */
69056   SECURITY_LOCKCTRL_SELECT_RESET       = 0,     /*!< RESET : Reset all.                                                        */
69057 } SECURITY_LOCKCTRL_SELECT_Enum;
69058 
69059 /* =======================================================  LOCKSTAT  ======================================================== */
69060 /* ===========================================  SECURITY LOCKSTAT STATUS [0..31]  ============================================ */
69061 typedef enum {                                  /*!< SECURITY_LOCKSTAT_STATUS                                                  */
69062   SECURITY_LOCKSTAT_STATUS_LOCK01      = 1,     /*!< LOCK01 : Enabled customer OTP program.                                    */
69063   SECURITY_LOCKSTAT_STATUS_LOCK02      = 2,     /*!< LOCK02 : Enabled customer OTP read.                                       */
69064   SECURITY_LOCKSTAT_STATUS_LOCK11      = 16,    /*!< LOCK11 : Enabled Ambiq OTP program.                                       */
69065   SECURITY_LOCKSTAT_STATUS_LOCK12      = 32,    /*!< LOCK12 : Enabled Ambiq OTP read.                                          */
69066   SECURITY_LOCKSTAT_STATUS_LOCK9D      = 1073741824,/*!< LOCK9D : Enabled Bootloader Recovery.                                 */
69067   SECURITY_LOCKSTAT_STATUS_LOCK9E      = -2147483648,/*!< LOCK9E : Enabled Bootloader info1.                                   */
69068   SECURITY_LOCKSTAT_STATUS_RESET       = 0,     /*!< RESET : All Reset.                                                        */
69069 } SECURITY_LOCKSTAT_STATUS_Enum;
69070 
69071 /* =========================================================  KEY0  ========================================================== */
69072 /* =========================================================  KEY1  ========================================================== */
69073 /* =========================================================  KEY2  ========================================================== */
69074 /* =========================================================  KEY3  ========================================================== */
69075 
69076 
69077 /* =========================================================================================================================== */
69078 /* ================                                          STIMER                                           ================ */
69079 /* =========================================================================================================================== */
69080 
69081 /* =========================================================  STCFG  ========================================================= */
69082 /* =============================================  STIMER STCFG FREEZE [31..31]  ============================================== */
69083 typedef enum {                                  /*!< STIMER_STCFG_FREEZE                                                       */
69084   STIMER_STCFG_FREEZE_THAW             = 0,     /*!< THAW : Let the COUNTER register run on its input clock.                   */
69085   STIMER_STCFG_FREEZE_FREEZE           = 1,     /*!< FREEZE : Stop the COUNTER register for loading.                           */
69086 } STIMER_STCFG_FREEZE_Enum;
69087 
69088 /* ==============================================  STIMER STCFG CLEAR [30..30]  ============================================== */
69089 typedef enum {                                  /*!< STIMER_STCFG_CLEAR                                                        */
69090   STIMER_STCFG_CLEAR_RUN               = 0,     /*!< RUN : Let the COUNTER register run on its input clock.                    */
69091   STIMER_STCFG_CLEAR_CLEAR             = 1,     /*!< CLEAR : Stop the COUNTER register for loading.                            */
69092 } STIMER_STCFG_CLEAR_Enum;
69093 
69094 /* ===========================================  STIMER STCFG COMPAREHEN [15..15]  ============================================ */
69095 typedef enum {                                  /*!< STIMER_STCFG_COMPAREHEN                                                   */
69096   STIMER_STCFG_COMPAREHEN_DISABLE      = 0,     /*!< DISABLE : Compare H disabled.                                             */
69097   STIMER_STCFG_COMPAREHEN_ENABLE       = 1,     /*!< ENABLE : Compare H enabled.                                               */
69098 } STIMER_STCFG_COMPAREHEN_Enum;
69099 
69100 /* ===========================================  STIMER STCFG COMPAREGEN [14..14]  ============================================ */
69101 typedef enum {                                  /*!< STIMER_STCFG_COMPAREGEN                                                   */
69102   STIMER_STCFG_COMPAREGEN_DISABLE      = 0,     /*!< DISABLE : Compare G disabled.                                             */
69103   STIMER_STCFG_COMPAREGEN_ENABLE       = 1,     /*!< ENABLE : Compare G enabled.                                               */
69104 } STIMER_STCFG_COMPAREGEN_Enum;
69105 
69106 /* ===========================================  STIMER STCFG COMPAREFEN [13..13]  ============================================ */
69107 typedef enum {                                  /*!< STIMER_STCFG_COMPAREFEN                                                   */
69108   STIMER_STCFG_COMPAREFEN_DISABLE      = 0,     /*!< DISABLE : Compare F disabled.                                             */
69109   STIMER_STCFG_COMPAREFEN_ENABLE       = 1,     /*!< ENABLE : Compare F enabled.                                               */
69110 } STIMER_STCFG_COMPAREFEN_Enum;
69111 
69112 /* ===========================================  STIMER STCFG COMPAREEEN [12..12]  ============================================ */
69113 typedef enum {                                  /*!< STIMER_STCFG_COMPAREEEN                                                   */
69114   STIMER_STCFG_COMPAREEEN_DISABLE      = 0,     /*!< DISABLE : Compare E disabled.                                             */
69115   STIMER_STCFG_COMPAREEEN_ENABLE       = 1,     /*!< ENABLE : Compare E enabled.                                               */
69116 } STIMER_STCFG_COMPAREEEN_Enum;
69117 
69118 /* ===========================================  STIMER STCFG COMPAREDEN [11..11]  ============================================ */
69119 typedef enum {                                  /*!< STIMER_STCFG_COMPAREDEN                                                   */
69120   STIMER_STCFG_COMPAREDEN_DISABLE      = 0,     /*!< DISABLE : Compare D disabled.                                             */
69121   STIMER_STCFG_COMPAREDEN_ENABLE       = 1,     /*!< ENABLE : Compare D enabled.                                               */
69122 } STIMER_STCFG_COMPAREDEN_Enum;
69123 
69124 /* ===========================================  STIMER STCFG COMPARECEN [10..10]  ============================================ */
69125 typedef enum {                                  /*!< STIMER_STCFG_COMPARECEN                                                   */
69126   STIMER_STCFG_COMPARECEN_DISABLE      = 0,     /*!< DISABLE : Compare C disabled.                                             */
69127   STIMER_STCFG_COMPARECEN_ENABLE       = 1,     /*!< ENABLE : Compare C enabled.                                               */
69128 } STIMER_STCFG_COMPARECEN_Enum;
69129 
69130 /* ============================================  STIMER STCFG COMPAREBEN [9..9]  ============================================= */
69131 typedef enum {                                  /*!< STIMER_STCFG_COMPAREBEN                                                   */
69132   STIMER_STCFG_COMPAREBEN_DISABLE      = 0,     /*!< DISABLE : Compare B disabled.                                             */
69133   STIMER_STCFG_COMPAREBEN_ENABLE       = 1,     /*!< ENABLE : Compare B enabled.                                               */
69134 } STIMER_STCFG_COMPAREBEN_Enum;
69135 
69136 /* ============================================  STIMER STCFG COMPAREAEN [8..8]  ============================================= */
69137 typedef enum {                                  /*!< STIMER_STCFG_COMPAREAEN                                                   */
69138   STIMER_STCFG_COMPAREAEN_DISABLE      = 0,     /*!< DISABLE : Compare A disabled.                                             */
69139   STIMER_STCFG_COMPAREAEN_ENABLE       = 1,     /*!< ENABLE : Compare A enabled.                                               */
69140 } STIMER_STCFG_COMPAREAEN_Enum;
69141 
69142 /* ==============================================  STIMER STCFG CLKSEL [0..3]  =============================================== */
69143 typedef enum {                                  /*!< STIMER_STCFG_CLKSEL                                                       */
69144   STIMER_STCFG_CLKSEL_NOCLK            = 0,     /*!< NOCLK : No clock enabled.                                                 */
69145   STIMER_STCFG_CLKSEL_HFRC_6MHZ        = 1,     /*!< HFRC_6MHZ : 6MHz from the HFRC clock divider.                             */
69146   STIMER_STCFG_CLKSEL_HFRC_375KHZ      = 2,     /*!< HFRC_375KHZ : 375KHz from the HFRC clock divider.                         */
69147   STIMER_STCFG_CLKSEL_XTAL_32KHZ       = 3,     /*!< XTAL_32KHZ : 32768Hz from the crystal oscillator.                         */
69148   STIMER_STCFG_CLKSEL_XTAL_16KHZ       = 4,     /*!< XTAL_16KHZ : 16384Hz from the crystal oscillator.                         */
69149   STIMER_STCFG_CLKSEL_XTAL_1KHZ        = 5,     /*!< XTAL_1KHZ : 1024Hz from the crystal oscillator.                           */
69150   STIMER_STCFG_CLKSEL_LFRC_1KHZ        = 6,     /*!< LFRC_1KHZ : Approximately 1KHz from the LFRC oscillator (uncalibrated).   */
69151   STIMER_STCFG_CLKSEL_CTIMER0          = 7,     /*!< CTIMER0 : Use CTIMER 0 for the clock source (allows prescaling
69152                                                      from other system clocks).                                                */
69153   STIMER_STCFG_CLKSEL_CTIMER1          = 8,     /*!< CTIMER1 : Use CTIMER 1 for the clock source (allows prescaling
69154                                                      from other system clocks).                                                */
69155 } STIMER_STCFG_CLKSEL_Enum;
69156 
69157 /* =========================================================  STTMR  ========================================================= */
69158 /* =======================================================  SCAPCTRL0  ======================================================= */
69159 /* ===========================================  STIMER SCAPCTRL0 CAPTURE0 [9..9]  ============================================ */
69160 typedef enum {                                  /*!< STIMER_SCAPCTRL0_CAPTURE0                                                 */
69161   STIMER_SCAPCTRL0_CAPTURE0_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
69162   STIMER_SCAPCTRL0_CAPTURE0_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
69163 } STIMER_SCAPCTRL0_CAPTURE0_Enum;
69164 
69165 /* ============================================  STIMER SCAPCTRL0 STPOL0 [8..8]  ============================================= */
69166 typedef enum {                                  /*!< STIMER_SCAPCTRL0_STPOL0                                                   */
69167   STIMER_SCAPCTRL0_STPOL0_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
69168   STIMER_SCAPCTRL0_STPOL0_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
69169 } STIMER_SCAPCTRL0_STPOL0_Enum;
69170 
69171 /* =======================================================  SCAPCTRL1  ======================================================= */
69172 /* ===========================================  STIMER SCAPCTRL1 CAPTURE1 [9..9]  ============================================ */
69173 typedef enum {                                  /*!< STIMER_SCAPCTRL1_CAPTURE1                                                 */
69174   STIMER_SCAPCTRL1_CAPTURE1_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
69175   STIMER_SCAPCTRL1_CAPTURE1_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
69176 } STIMER_SCAPCTRL1_CAPTURE1_Enum;
69177 
69178 /* ============================================  STIMER SCAPCTRL1 STPOL1 [8..8]  ============================================= */
69179 typedef enum {                                  /*!< STIMER_SCAPCTRL1_STPOL1                                                   */
69180   STIMER_SCAPCTRL1_STPOL1_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
69181   STIMER_SCAPCTRL1_STPOL1_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
69182 } STIMER_SCAPCTRL1_STPOL1_Enum;
69183 
69184 /* =======================================================  SCAPCTRL2  ======================================================= */
69185 /* ===========================================  STIMER SCAPCTRL2 CAPTURE2 [9..9]  ============================================ */
69186 typedef enum {                                  /*!< STIMER_SCAPCTRL2_CAPTURE2                                                 */
69187   STIMER_SCAPCTRL2_CAPTURE2_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
69188   STIMER_SCAPCTRL2_CAPTURE2_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
69189 } STIMER_SCAPCTRL2_CAPTURE2_Enum;
69190 
69191 /* ============================================  STIMER SCAPCTRL2 STPOL2 [8..8]  ============================================= */
69192 typedef enum {                                  /*!< STIMER_SCAPCTRL2_STPOL2                                                   */
69193   STIMER_SCAPCTRL2_STPOL2_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
69194   STIMER_SCAPCTRL2_STPOL2_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
69195 } STIMER_SCAPCTRL2_STPOL2_Enum;
69196 
69197 /* =======================================================  SCAPCTRL3  ======================================================= */
69198 /* ===========================================  STIMER SCAPCTRL3 CAPTURE3 [9..9]  ============================================ */
69199 typedef enum {                                  /*!< STIMER_SCAPCTRL3_CAPTURE3                                                 */
69200   STIMER_SCAPCTRL3_CAPTURE3_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
69201   STIMER_SCAPCTRL3_CAPTURE3_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
69202 } STIMER_SCAPCTRL3_CAPTURE3_Enum;
69203 
69204 /* ============================================  STIMER SCAPCTRL3 STPOL3 [8..8]  ============================================= */
69205 typedef enum {                                  /*!< STIMER_SCAPCTRL3_STPOL3                                                   */
69206   STIMER_SCAPCTRL3_STPOL3_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
69207   STIMER_SCAPCTRL3_STPOL3_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
69208 } STIMER_SCAPCTRL3_STPOL3_Enum;
69209 
69210 /* ========================================================  SCMPR0  ========================================================= */
69211 /* ========================================================  SCMPR1  ========================================================= */
69212 /* ========================================================  SCMPR2  ========================================================= */
69213 /* ========================================================  SCMPR3  ========================================================= */
69214 /* ========================================================  SCMPR4  ========================================================= */
69215 /* ========================================================  SCMPR5  ========================================================= */
69216 /* ========================================================  SCMPR6  ========================================================= */
69217 /* ========================================================  SCMPR7  ========================================================= */
69218 /* ========================================================  SCAPT0  ========================================================= */
69219 /* ========================================================  SCAPT1  ========================================================= */
69220 /* ========================================================  SCAPT2  ========================================================= */
69221 /* ========================================================  SCAPT3  ========================================================= */
69222 /* =========================================================  SNVR0  ========================================================= */
69223 /* =========================================================  SNVR1  ========================================================= */
69224 /* =========================================================  SNVR2  ========================================================= */
69225 /* =======================================================  STMINTEN  ======================================================== */
69226 /* ===========================================  STIMER STMINTEN CAPTURED [12..12]  =========================================== */
69227 typedef enum {                                  /*!< STIMER_STMINTEN_CAPTURED                                                  */
69228   STIMER_STMINTEN_CAPTURED_CAPD_INT    = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
69229   STIMER_STMINTEN_CAPTURED_CAPD_DEFAULT = 0,    /*!< CAPD_DEFAULT : Capture D interrupt status default/not set.                */
69230 } STIMER_STMINTEN_CAPTURED_Enum;
69231 
69232 /* ===========================================  STIMER STMINTEN CAPTUREC [11..11]  =========================================== */
69233 typedef enum {                                  /*!< STIMER_STMINTEN_CAPTUREC                                                  */
69234   STIMER_STMINTEN_CAPTUREC_CAPC_INT    = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
69235   STIMER_STMINTEN_CAPTUREC_CAPC_DEFAULT = 0,    /*!< CAPC_DEFAULT : CAPTURE C interrupt status default/not set.                */
69236 } STIMER_STMINTEN_CAPTUREC_Enum;
69237 
69238 /* ===========================================  STIMER STMINTEN CAPTUREB [10..10]  =========================================== */
69239 typedef enum {                                  /*!< STIMER_STMINTEN_CAPTUREB                                                  */
69240   STIMER_STMINTEN_CAPTUREB_CAPB_INT    = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
69241   STIMER_STMINTEN_CAPTUREB_CAPB_DEFAULT = 0,    /*!< CAPB_DEFAULT : CAPTURE B interrupt status default/not set.                */
69242 } STIMER_STMINTEN_CAPTUREB_Enum;
69243 
69244 /* ============================================  STIMER STMINTEN CAPTUREA [9..9]  ============================================ */
69245 typedef enum {                                  /*!< STIMER_STMINTEN_CAPTUREA                                                  */
69246   STIMER_STMINTEN_CAPTUREA_CAPA_INT    = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
69247   STIMER_STMINTEN_CAPTUREA_CAPA_DEFAULT = 0,    /*!< CAPA_DEFAULT : CAPTURE A interrupt status default/not set.                */
69248 } STIMER_STMINTEN_CAPTUREA_Enum;
69249 
69250 /* ============================================  STIMER STMINTEN OVERFLOW [8..8]  ============================================ */
69251 typedef enum {                                  /*!< STIMER_STMINTEN_OVERFLOW                                                  */
69252   STIMER_STMINTEN_OVERFLOW_OFLOW_INT   = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
69253   STIMER_STMINTEN_OVERFLOW_OFLOW_DEFAULT = 0,   /*!< OFLOW_DEFAULT : Overflow interrupt status bit default/not set.            */
69254 } STIMER_STMINTEN_OVERFLOW_Enum;
69255 
69256 /* ============================================  STIMER STMINTEN COMPAREH [7..7]  ============================================ */
69257 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREH                                                  */
69258   STIMER_STMINTEN_COMPAREH_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69259   STIMER_STMINTEN_COMPAREH_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69260 } STIMER_STMINTEN_COMPAREH_Enum;
69261 
69262 /* ============================================  STIMER STMINTEN COMPAREG [6..6]  ============================================ */
69263 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREG                                                  */
69264   STIMER_STMINTEN_COMPAREG_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69265   STIMER_STMINTEN_COMPAREG_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69266 } STIMER_STMINTEN_COMPAREG_Enum;
69267 
69268 /* ============================================  STIMER STMINTEN COMPAREF [5..5]  ============================================ */
69269 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREF                                                  */
69270   STIMER_STMINTEN_COMPAREF_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69271   STIMER_STMINTEN_COMPAREF_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69272 } STIMER_STMINTEN_COMPAREF_Enum;
69273 
69274 /* ============================================  STIMER STMINTEN COMPAREE [4..4]  ============================================ */
69275 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREE                                                  */
69276   STIMER_STMINTEN_COMPAREE_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69277   STIMER_STMINTEN_COMPAREE_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69278 } STIMER_STMINTEN_COMPAREE_Enum;
69279 
69280 /* ============================================  STIMER STMINTEN COMPARED [3..3]  ============================================ */
69281 typedef enum {                                  /*!< STIMER_STMINTEN_COMPARED                                                  */
69282   STIMER_STMINTEN_COMPARED_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69283   STIMER_STMINTEN_COMPARED_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69284 } STIMER_STMINTEN_COMPARED_Enum;
69285 
69286 /* ============================================  STIMER STMINTEN COMPAREC [2..2]  ============================================ */
69287 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREC                                                  */
69288   STIMER_STMINTEN_COMPAREC_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69289   STIMER_STMINTEN_COMPAREC_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69290 } STIMER_STMINTEN_COMPAREC_Enum;
69291 
69292 /* ============================================  STIMER STMINTEN COMPAREB [1..1]  ============================================ */
69293 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREB                                                  */
69294   STIMER_STMINTEN_COMPAREB_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69295   STIMER_STMINTEN_COMPAREB_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69296 } STIMER_STMINTEN_COMPAREB_Enum;
69297 
69298 /* ============================================  STIMER STMINTEN COMPAREA [0..0]  ============================================ */
69299 typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREA                                                  */
69300   STIMER_STMINTEN_COMPAREA_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69301   STIMER_STMINTEN_COMPAREA_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69302 } STIMER_STMINTEN_COMPAREA_Enum;
69303 
69304 /* ======================================================  STMINTSTAT  ======================================================= */
69305 /* ==========================================  STIMER STMINTSTAT CAPTURED [12..12]  ========================================== */
69306 typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTURED                                                */
69307   STIMER_STMINTSTAT_CAPTURED_CAPD_INT  = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
69308   STIMER_STMINTSTAT_CAPTURED_CAPD_DEFAULT = 0,  /*!< CAPD_DEFAULT : Capture D interrupt status default/not set.                */
69309 } STIMER_STMINTSTAT_CAPTURED_Enum;
69310 
69311 /* ==========================================  STIMER STMINTSTAT CAPTUREC [11..11]  ========================================== */
69312 typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTUREC                                                */
69313   STIMER_STMINTSTAT_CAPTUREC_CAPC_INT  = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
69314   STIMER_STMINTSTAT_CAPTUREC_CAPC_DEFAULT = 0,  /*!< CAPC_DEFAULT : CAPTURE C interrupt status default/not set.                */
69315 } STIMER_STMINTSTAT_CAPTUREC_Enum;
69316 
69317 /* ==========================================  STIMER STMINTSTAT CAPTUREB [10..10]  ========================================== */
69318 typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTUREB                                                */
69319   STIMER_STMINTSTAT_CAPTUREB_CAPB_INT  = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
69320   STIMER_STMINTSTAT_CAPTUREB_CAPB_DEFAULT = 0,  /*!< CAPB_DEFAULT : CAPTURE B interrupt status default/not set.                */
69321 } STIMER_STMINTSTAT_CAPTUREB_Enum;
69322 
69323 /* ===========================================  STIMER STMINTSTAT CAPTUREA [9..9]  =========================================== */
69324 typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTUREA                                                */
69325   STIMER_STMINTSTAT_CAPTUREA_CAPA_INT  = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
69326   STIMER_STMINTSTAT_CAPTUREA_CAPA_DEFAULT = 0,  /*!< CAPA_DEFAULT : CAPTURE A interrupt status default/not set.                */
69327 } STIMER_STMINTSTAT_CAPTUREA_Enum;
69328 
69329 /* ===========================================  STIMER STMINTSTAT OVERFLOW [8..8]  =========================================== */
69330 typedef enum {                                  /*!< STIMER_STMINTSTAT_OVERFLOW                                                */
69331   STIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
69332   STIMER_STMINTSTAT_OVERFLOW_OFLOW_DEFAULT = 0, /*!< OFLOW_DEFAULT : Overflow interrupt status bit default/not set.            */
69333 } STIMER_STMINTSTAT_OVERFLOW_Enum;
69334 
69335 /* ===========================================  STIMER STMINTSTAT COMPAREH [7..7]  =========================================== */
69336 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREH                                                */
69337   STIMER_STMINTSTAT_COMPAREH_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69338   STIMER_STMINTSTAT_COMPAREH_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69339 } STIMER_STMINTSTAT_COMPAREH_Enum;
69340 
69341 /* ===========================================  STIMER STMINTSTAT COMPAREG [6..6]  =========================================== */
69342 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREG                                                */
69343   STIMER_STMINTSTAT_COMPAREG_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69344   STIMER_STMINTSTAT_COMPAREG_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69345 } STIMER_STMINTSTAT_COMPAREG_Enum;
69346 
69347 /* ===========================================  STIMER STMINTSTAT COMPAREF [5..5]  =========================================== */
69348 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREF                                                */
69349   STIMER_STMINTSTAT_COMPAREF_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69350   STIMER_STMINTSTAT_COMPAREF_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69351 } STIMER_STMINTSTAT_COMPAREF_Enum;
69352 
69353 /* ===========================================  STIMER STMINTSTAT COMPAREE [4..4]  =========================================== */
69354 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREE                                                */
69355   STIMER_STMINTSTAT_COMPAREE_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69356   STIMER_STMINTSTAT_COMPAREE_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69357 } STIMER_STMINTSTAT_COMPAREE_Enum;
69358 
69359 /* ===========================================  STIMER STMINTSTAT COMPARED [3..3]  =========================================== */
69360 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPARED                                                */
69361   STIMER_STMINTSTAT_COMPARED_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69362   STIMER_STMINTSTAT_COMPARED_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69363 } STIMER_STMINTSTAT_COMPARED_Enum;
69364 
69365 /* ===========================================  STIMER STMINTSTAT COMPAREC [2..2]  =========================================== */
69366 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREC                                                */
69367   STIMER_STMINTSTAT_COMPAREC_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69368   STIMER_STMINTSTAT_COMPAREC_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69369 } STIMER_STMINTSTAT_COMPAREC_Enum;
69370 
69371 /* ===========================================  STIMER STMINTSTAT COMPAREB [1..1]  =========================================== */
69372 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREB                                                */
69373   STIMER_STMINTSTAT_COMPAREB_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69374   STIMER_STMINTSTAT_COMPAREB_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69375 } STIMER_STMINTSTAT_COMPAREB_Enum;
69376 
69377 /* ===========================================  STIMER STMINTSTAT COMPAREA [0..0]  =========================================== */
69378 typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREA                                                */
69379   STIMER_STMINTSTAT_COMPAREA_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69380   STIMER_STMINTSTAT_COMPAREA_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69381 } STIMER_STMINTSTAT_COMPAREA_Enum;
69382 
69383 /* =======================================================  STMINTCLR  ======================================================= */
69384 /* ==========================================  STIMER STMINTCLR CAPTURED [12..12]  =========================================== */
69385 typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTURED                                                 */
69386   STIMER_STMINTCLR_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
69387   STIMER_STMINTCLR_CAPTURED_CAPD_DEFAULT = 0,   /*!< CAPD_DEFAULT : Capture D interrupt status default/not set.                */
69388 } STIMER_STMINTCLR_CAPTURED_Enum;
69389 
69390 /* ==========================================  STIMER STMINTCLR CAPTUREC [11..11]  =========================================== */
69391 typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTUREC                                                 */
69392   STIMER_STMINTCLR_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
69393   STIMER_STMINTCLR_CAPTUREC_CAPC_DEFAULT = 0,   /*!< CAPC_DEFAULT : CAPTURE C interrupt status default/not set.                */
69394 } STIMER_STMINTCLR_CAPTUREC_Enum;
69395 
69396 /* ==========================================  STIMER STMINTCLR CAPTUREB [10..10]  =========================================== */
69397 typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTUREB                                                 */
69398   STIMER_STMINTCLR_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
69399   STIMER_STMINTCLR_CAPTUREB_CAPB_DEFAULT = 0,   /*!< CAPB_DEFAULT : CAPTURE B interrupt status default/not set.                */
69400 } STIMER_STMINTCLR_CAPTUREB_Enum;
69401 
69402 /* ===========================================  STIMER STMINTCLR CAPTUREA [9..9]  ============================================ */
69403 typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTUREA                                                 */
69404   STIMER_STMINTCLR_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
69405   STIMER_STMINTCLR_CAPTUREA_CAPA_DEFAULT = 0,   /*!< CAPA_DEFAULT : CAPTURE A interrupt status default/not set.                */
69406 } STIMER_STMINTCLR_CAPTUREA_Enum;
69407 
69408 /* ===========================================  STIMER STMINTCLR OVERFLOW [8..8]  ============================================ */
69409 typedef enum {                                  /*!< STIMER_STMINTCLR_OVERFLOW                                                 */
69410   STIMER_STMINTCLR_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
69411   STIMER_STMINTCLR_OVERFLOW_OFLOW_DEFAULT = 0,  /*!< OFLOW_DEFAULT : Overflow interrupt status bit default/not set.            */
69412 } STIMER_STMINTCLR_OVERFLOW_Enum;
69413 
69414 /* ===========================================  STIMER STMINTCLR COMPAREH [7..7]  ============================================ */
69415 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREH                                                 */
69416   STIMER_STMINTCLR_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69417   STIMER_STMINTCLR_COMPAREH_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69418 } STIMER_STMINTCLR_COMPAREH_Enum;
69419 
69420 /* ===========================================  STIMER STMINTCLR COMPAREG [6..6]  ============================================ */
69421 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREG                                                 */
69422   STIMER_STMINTCLR_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69423   STIMER_STMINTCLR_COMPAREG_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69424 } STIMER_STMINTCLR_COMPAREG_Enum;
69425 
69426 /* ===========================================  STIMER STMINTCLR COMPAREF [5..5]  ============================================ */
69427 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREF                                                 */
69428   STIMER_STMINTCLR_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69429   STIMER_STMINTCLR_COMPAREF_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69430 } STIMER_STMINTCLR_COMPAREF_Enum;
69431 
69432 /* ===========================================  STIMER STMINTCLR COMPAREE [4..4]  ============================================ */
69433 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREE                                                 */
69434   STIMER_STMINTCLR_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69435   STIMER_STMINTCLR_COMPAREE_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69436 } STIMER_STMINTCLR_COMPAREE_Enum;
69437 
69438 /* ===========================================  STIMER STMINTCLR COMPARED [3..3]  ============================================ */
69439 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPARED                                                 */
69440   STIMER_STMINTCLR_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69441   STIMER_STMINTCLR_COMPARED_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69442 } STIMER_STMINTCLR_COMPARED_Enum;
69443 
69444 /* ===========================================  STIMER STMINTCLR COMPAREC [2..2]  ============================================ */
69445 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREC                                                 */
69446   STIMER_STMINTCLR_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69447   STIMER_STMINTCLR_COMPAREC_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69448 } STIMER_STMINTCLR_COMPAREC_Enum;
69449 
69450 /* ===========================================  STIMER STMINTCLR COMPAREB [1..1]  ============================================ */
69451 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREB                                                 */
69452   STIMER_STMINTCLR_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69453   STIMER_STMINTCLR_COMPAREB_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69454 } STIMER_STMINTCLR_COMPAREB_Enum;
69455 
69456 /* ===========================================  STIMER STMINTCLR COMPAREA [0..0]  ============================================ */
69457 typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREA                                                 */
69458   STIMER_STMINTCLR_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69459   STIMER_STMINTCLR_COMPAREA_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69460 } STIMER_STMINTCLR_COMPAREA_Enum;
69461 
69462 /* =======================================================  STMINTSET  ======================================================= */
69463 /* ==========================================  STIMER STMINTSET CAPTURED [12..12]  =========================================== */
69464 typedef enum {                                  /*!< STIMER_STMINTSET_CAPTURED                                                 */
69465   STIMER_STMINTSET_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
69466   STIMER_STMINTSET_CAPTURED_CAPD_DEFAULT = 0,   /*!< CAPD_DEFAULT : Capture D interrupt status default/not set.                */
69467 } STIMER_STMINTSET_CAPTURED_Enum;
69468 
69469 /* ==========================================  STIMER STMINTSET CAPTUREC [11..11]  =========================================== */
69470 typedef enum {                                  /*!< STIMER_STMINTSET_CAPTUREC                                                 */
69471   STIMER_STMINTSET_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
69472   STIMER_STMINTSET_CAPTUREC_CAPC_DEFAULT = 0,   /*!< CAPC_DEFAULT : CAPTURE C interrupt status default/not set.                */
69473 } STIMER_STMINTSET_CAPTUREC_Enum;
69474 
69475 /* ==========================================  STIMER STMINTSET CAPTUREB [10..10]  =========================================== */
69476 typedef enum {                                  /*!< STIMER_STMINTSET_CAPTUREB                                                 */
69477   STIMER_STMINTSET_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
69478   STIMER_STMINTSET_CAPTUREB_CAPB_DEFAULT = 0,   /*!< CAPB_DEFAULT : CAPTURE B interrupt status default/not set.                */
69479 } STIMER_STMINTSET_CAPTUREB_Enum;
69480 
69481 /* ===========================================  STIMER STMINTSET CAPTUREA [9..9]  ============================================ */
69482 typedef enum {                                  /*!< STIMER_STMINTSET_CAPTUREA                                                 */
69483   STIMER_STMINTSET_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
69484   STIMER_STMINTSET_CAPTUREA_CAPA_DEFAULT = 0,   /*!< CAPA_DEFAULT : CAPTURE A interrupt status default/not set.                */
69485 } STIMER_STMINTSET_CAPTUREA_Enum;
69486 
69487 /* ===========================================  STIMER STMINTSET OVERFLOW [8..8]  ============================================ */
69488 typedef enum {                                  /*!< STIMER_STMINTSET_OVERFLOW                                                 */
69489   STIMER_STMINTSET_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
69490   STIMER_STMINTSET_OVERFLOW_OFLOW_DEFAULT = 0,  /*!< OFLOW_DEFAULT : Overflow interrupt status bit default/not set.            */
69491 } STIMER_STMINTSET_OVERFLOW_Enum;
69492 
69493 /* ===========================================  STIMER STMINTSET COMPAREH [7..7]  ============================================ */
69494 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREH                                                 */
69495   STIMER_STMINTSET_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69496   STIMER_STMINTSET_COMPAREH_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69497 } STIMER_STMINTSET_COMPAREH_Enum;
69498 
69499 /* ===========================================  STIMER STMINTSET COMPAREG [6..6]  ============================================ */
69500 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREG                                                 */
69501   STIMER_STMINTSET_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69502   STIMER_STMINTSET_COMPAREG_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69503 } STIMER_STMINTSET_COMPAREG_Enum;
69504 
69505 /* ===========================================  STIMER STMINTSET COMPAREF [5..5]  ============================================ */
69506 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREF                                                 */
69507   STIMER_STMINTSET_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69508   STIMER_STMINTSET_COMPAREF_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69509 } STIMER_STMINTSET_COMPAREF_Enum;
69510 
69511 /* ===========================================  STIMER STMINTSET COMPAREE [4..4]  ============================================ */
69512 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREE                                                 */
69513   STIMER_STMINTSET_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69514   STIMER_STMINTSET_COMPAREE_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69515 } STIMER_STMINTSET_COMPAREE_Enum;
69516 
69517 /* ===========================================  STIMER STMINTSET COMPARED [3..3]  ============================================ */
69518 typedef enum {                                  /*!< STIMER_STMINTSET_COMPARED                                                 */
69519   STIMER_STMINTSET_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69520   STIMER_STMINTSET_COMPARED_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69521 } STIMER_STMINTSET_COMPARED_Enum;
69522 
69523 /* ===========================================  STIMER STMINTSET COMPAREC [2..2]  ============================================ */
69524 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREC                                                 */
69525   STIMER_STMINTSET_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69526   STIMER_STMINTSET_COMPAREC_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69527 } STIMER_STMINTSET_COMPAREC_Enum;
69528 
69529 /* ===========================================  STIMER STMINTSET COMPAREB [1..1]  ============================================ */
69530 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREB                                                 */
69531   STIMER_STMINTSET_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69532   STIMER_STMINTSET_COMPAREB_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69533 } STIMER_STMINTSET_COMPAREB_Enum;
69534 
69535 /* ===========================================  STIMER STMINTSET COMPAREA [0..0]  ============================================ */
69536 typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREA                                                 */
69537   STIMER_STMINTSET_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
69538   STIMER_STMINTSET_COMPAREA_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
69539 } STIMER_STMINTSET_COMPAREA_Enum;
69540 
69541 
69542 
69543 /* =========================================================================================================================== */
69544 /* ================                                           TIMER                                           ================ */
69545 /* =========================================================================================================================== */
69546 
69547 /* =========================================================  CTRL  ========================================================== */
69548 /* ========================================================  STATUS  ========================================================= */
69549 /* ========================================================  GLOBEN  ========================================================= */
69550 /* ==============================================  TIMER GLOBEN ADCEN [31..31]  ============================================== */
69551 typedef enum {                                  /*!< TIMER_GLOBEN_ADCEN                                                        */
69552   TIMER_GLOBEN_ADCEN_EN                = 1,     /*!< EN : Timer Enabled. TMREN enable is used.                                 */
69553   TIMER_GLOBEN_ADCEN_DIS               = 0,     /*!< DIS : Disable TIMER .                                                     */
69554 } TIMER_GLOBEN_ADCEN_Enum;
69555 
69556 /* ============================================  TIMER GLOBEN AUDADCEN [30..30]  ============================================= */
69557 typedef enum {                                  /*!< TIMER_GLOBEN_AUDADCEN                                                     */
69558   TIMER_GLOBEN_AUDADCEN_EN             = 1,     /*!< EN : Timer Enabled. TMREN enable is used.                                 */
69559   TIMER_GLOBEN_AUDADCEN_DIS            = 0,     /*!< DIS : Disable TIMER .                                                     */
69560 } TIMER_GLOBEN_AUDADCEN_Enum;
69561 
69562 /* =========================================  TIMER GLOBEN ENABLEALLINPUTS [29..29]  ========================================= */
69563 typedef enum {                                  /*!< TIMER_GLOBEN_ENABLEALLINPUTS                                              */
69564   TIMER_GLOBEN_ENABLEALLINPUTS_EN      = 1,     /*!< EN : Override to enable all inputs from GPIO                              */
69565   TIMER_GLOBEN_ENABLEALLINPUTS_DIS     = 0,     /*!< DIS : Normal mode where inputs from GPIO are enabled based on
69566                                                      enabled clock and triggers.                                               */
69567 } TIMER_GLOBEN_ENABLEALLINPUTS_Enum;
69568 
69569 /* ==============================================  TIMER GLOBEN ENB15 [15..15]  ============================================== */
69570 typedef enum {                                  /*!< TIMER_GLOBEN_ENB15                                                        */
69571   TIMER_GLOBEN_ENB15_EN                = 1,     /*!< EN : Timer Enabled. TMR15EN enable is used.                               */
69572   TIMER_GLOBEN_ENB15_DIS               = 0,     /*!< DIS : Disable TIMER 15.                                                   */
69573 } TIMER_GLOBEN_ENB15_Enum;
69574 
69575 /* ==============================================  TIMER GLOBEN ENB14 [14..14]  ============================================== */
69576 typedef enum {                                  /*!< TIMER_GLOBEN_ENB14                                                        */
69577   TIMER_GLOBEN_ENB14_EN                = 1,     /*!< EN : Timer Enabled. TMR14EN enable is used.                               */
69578   TIMER_GLOBEN_ENB14_DIS               = 0,     /*!< DIS : Disable TIMER 14.                                                   */
69579 } TIMER_GLOBEN_ENB14_Enum;
69580 
69581 /* ==============================================  TIMER GLOBEN ENB13 [13..13]  ============================================== */
69582 typedef enum {                                  /*!< TIMER_GLOBEN_ENB13                                                        */
69583   TIMER_GLOBEN_ENB13_EN                = 1,     /*!< EN : Timer Enabled. TMR13EN enable is used.                               */
69584   TIMER_GLOBEN_ENB13_DIS               = 0,     /*!< DIS : Disable TIMER 13.                                                   */
69585 } TIMER_GLOBEN_ENB13_Enum;
69586 
69587 /* ==============================================  TIMER GLOBEN ENB12 [12..12]  ============================================== */
69588 typedef enum {                                  /*!< TIMER_GLOBEN_ENB12                                                        */
69589   TIMER_GLOBEN_ENB12_EN                = 1,     /*!< EN : Timer Enabled. TMR12EN enable is used.                               */
69590   TIMER_GLOBEN_ENB12_DIS               = 0,     /*!< DIS : Disable TIMER 12.                                                   */
69591 } TIMER_GLOBEN_ENB12_Enum;
69592 
69593 /* ==============================================  TIMER GLOBEN ENB11 [11..11]  ============================================== */
69594 typedef enum {                                  /*!< TIMER_GLOBEN_ENB11                                                        */
69595   TIMER_GLOBEN_ENB11_EN                = 1,     /*!< EN : Timer Enabled. TMR11EN enable is used.                               */
69596   TIMER_GLOBEN_ENB11_DIS               = 0,     /*!< DIS : Disable TIMER 11.                                                   */
69597 } TIMER_GLOBEN_ENB11_Enum;
69598 
69599 /* ==============================================  TIMER GLOBEN ENB10 [10..10]  ============================================== */
69600 typedef enum {                                  /*!< TIMER_GLOBEN_ENB10                                                        */
69601   TIMER_GLOBEN_ENB10_EN                = 1,     /*!< EN : Timer Enabled. TMR10EN enable is used.                               */
69602   TIMER_GLOBEN_ENB10_DIS               = 0,     /*!< DIS : Disable TIMER 10.                                                   */
69603 } TIMER_GLOBEN_ENB10_Enum;
69604 
69605 /* ===============================================  TIMER GLOBEN ENB9 [9..9]  ================================================ */
69606 typedef enum {                                  /*!< TIMER_GLOBEN_ENB9                                                         */
69607   TIMER_GLOBEN_ENB9_EN                 = 1,     /*!< EN : Timer Enabled. TMR9EN enable is used.                                */
69608   TIMER_GLOBEN_ENB9_DIS                = 0,     /*!< DIS : Disable TIMER 9.                                                    */
69609 } TIMER_GLOBEN_ENB9_Enum;
69610 
69611 /* ===============================================  TIMER GLOBEN ENB8 [8..8]  ================================================ */
69612 typedef enum {                                  /*!< TIMER_GLOBEN_ENB8                                                         */
69613   TIMER_GLOBEN_ENB8_EN                 = 1,     /*!< EN : Timer Enabled. TMR8EN enable is used.                                */
69614   TIMER_GLOBEN_ENB8_DIS                = 0,     /*!< DIS : Disable TIMER 8.                                                    */
69615 } TIMER_GLOBEN_ENB8_Enum;
69616 
69617 /* ===============================================  TIMER GLOBEN ENB7 [7..7]  ================================================ */
69618 typedef enum {                                  /*!< TIMER_GLOBEN_ENB7                                                         */
69619   TIMER_GLOBEN_ENB7_EN                 = 1,     /*!< EN : Timer Enabled. TMR7EN enable is used.                                */
69620   TIMER_GLOBEN_ENB7_DIS                = 0,     /*!< DIS : Disable TIMER 7.                                                    */
69621 } TIMER_GLOBEN_ENB7_Enum;
69622 
69623 /* ===============================================  TIMER GLOBEN ENB6 [6..6]  ================================================ */
69624 typedef enum {                                  /*!< TIMER_GLOBEN_ENB6                                                         */
69625   TIMER_GLOBEN_ENB6_EN                 = 1,     /*!< EN : Timer Enabled. TMR6EN enable is used.                                */
69626   TIMER_GLOBEN_ENB6_DIS                = 0,     /*!< DIS : Disable TIMER 6.                                                    */
69627 } TIMER_GLOBEN_ENB6_Enum;
69628 
69629 /* ===============================================  TIMER GLOBEN ENB5 [5..5]  ================================================ */
69630 typedef enum {                                  /*!< TIMER_GLOBEN_ENB5                                                         */
69631   TIMER_GLOBEN_ENB5_EN                 = 1,     /*!< EN : Timer Enabled. TMR5EN enable is used.                                */
69632   TIMER_GLOBEN_ENB5_DIS                = 0,     /*!< DIS : Disable TIMER 5.                                                    */
69633 } TIMER_GLOBEN_ENB5_Enum;
69634 
69635 /* ===============================================  TIMER GLOBEN ENB4 [4..4]  ================================================ */
69636 typedef enum {                                  /*!< TIMER_GLOBEN_ENB4                                                         */
69637   TIMER_GLOBEN_ENB4_EN                 = 1,     /*!< EN : Timer Enabled. TMR4EN enable is used.                                */
69638   TIMER_GLOBEN_ENB4_DIS                = 0,     /*!< DIS : Disable TIMER 4.                                                    */
69639 } TIMER_GLOBEN_ENB4_Enum;
69640 
69641 /* ===============================================  TIMER GLOBEN ENB3 [3..3]  ================================================ */
69642 typedef enum {                                  /*!< TIMER_GLOBEN_ENB3                                                         */
69643   TIMER_GLOBEN_ENB3_EN                 = 1,     /*!< EN : Timer Enabled. TMR3EN enable is used.                                */
69644   TIMER_GLOBEN_ENB3_DIS                = 0,     /*!< DIS : Disable TIMER 3.                                                    */
69645 } TIMER_GLOBEN_ENB3_Enum;
69646 
69647 /* ===============================================  TIMER GLOBEN ENB2 [2..2]  ================================================ */
69648 typedef enum {                                  /*!< TIMER_GLOBEN_ENB2                                                         */
69649   TIMER_GLOBEN_ENB2_EN                 = 1,     /*!< EN : Timer Enabled. TMR2EN enable is used.                                */
69650   TIMER_GLOBEN_ENB2_DIS                = 0,     /*!< DIS : Disable TIMER 2.                                                    */
69651 } TIMER_GLOBEN_ENB2_Enum;
69652 
69653 /* ===============================================  TIMER GLOBEN ENB1 [1..1]  ================================================ */
69654 typedef enum {                                  /*!< TIMER_GLOBEN_ENB1                                                         */
69655   TIMER_GLOBEN_ENB1_EN                 = 1,     /*!< EN : Timer Enabled. TMR1EN enable is used.                                */
69656   TIMER_GLOBEN_ENB1_DIS                = 0,     /*!< DIS : Disable TIMER 1.                                                    */
69657 } TIMER_GLOBEN_ENB1_Enum;
69658 
69659 /* ===============================================  TIMER GLOBEN ENB0 [0..0]  ================================================ */
69660 typedef enum {                                  /*!< TIMER_GLOBEN_ENB0                                                         */
69661   TIMER_GLOBEN_ENB0_EN                 = 1,     /*!< EN : Timer Enabled. TMR0EN enable is used.                                */
69662   TIMER_GLOBEN_ENB0_DIS                = 0,     /*!< DIS : Disable TIMER 0.                                                    */
69663 } TIMER_GLOBEN_ENB0_Enum;
69664 
69665 /* =========================================================  INTEN  ========================================================= */
69666 /* ========================================================  INTSTAT  ======================================================== */
69667 /* ========================================================  INTCLR  ========================================================= */
69668 /* ========================================================  INTSET  ========================================================= */
69669 /* ========================================================  OUTCFG0  ======================================================== */
69670 /* ============================================  TIMER OUTCFG0 OUTCFG3 [24..29]  ============================================= */
69671 typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG3                                                     */
69672   TIMER_OUTCFG0_OUTCFG3_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69673   TIMER_OUTCFG0_OUTCFG3_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69674   TIMER_OUTCFG0_OUTCFG3_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69675   TIMER_OUTCFG0_OUTCFG3_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69676   TIMER_OUTCFG0_OUTCFG3_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69677   TIMER_OUTCFG0_OUTCFG3_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69678   TIMER_OUTCFG0_OUTCFG3_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69679   TIMER_OUTCFG0_OUTCFG3_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69680   TIMER_OUTCFG0_OUTCFG3_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69681   TIMER_OUTCFG0_OUTCFG3_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69682   TIMER_OUTCFG0_OUTCFG3_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69683   TIMER_OUTCFG0_OUTCFG3_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69684   TIMER_OUTCFG0_OUTCFG3_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69685   TIMER_OUTCFG0_OUTCFG3_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69686   TIMER_OUTCFG0_OUTCFG3_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69687   TIMER_OUTCFG0_OUTCFG3_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69688   TIMER_OUTCFG0_OUTCFG3_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69689   TIMER_OUTCFG0_OUTCFG3_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69690   TIMER_OUTCFG0_OUTCFG3_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69691   TIMER_OUTCFG0_OUTCFG3_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69692   TIMER_OUTCFG0_OUTCFG3_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69693   TIMER_OUTCFG0_OUTCFG3_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69694   TIMER_OUTCFG0_OUTCFG3_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69695   TIMER_OUTCFG0_OUTCFG3_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69696   TIMER_OUTCFG0_OUTCFG3_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69697   TIMER_OUTCFG0_OUTCFG3_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69698   TIMER_OUTCFG0_OUTCFG3_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69699   TIMER_OUTCFG0_OUTCFG3_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69700   TIMER_OUTCFG0_OUTCFG3_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69701   TIMER_OUTCFG0_OUTCFG3_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69702   TIMER_OUTCFG0_OUTCFG3_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69703   TIMER_OUTCFG0_OUTCFG3_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69704   TIMER_OUTCFG0_OUTCFG3_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69705   TIMER_OUTCFG0_OUTCFG3_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69706   TIMER_OUTCFG0_OUTCFG3_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69707   TIMER_OUTCFG0_OUTCFG3_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69708   TIMER_OUTCFG0_OUTCFG3_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69709   TIMER_OUTCFG0_OUTCFG3_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69710   TIMER_OUTCFG0_OUTCFG3_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69711   TIMER_OUTCFG0_OUTCFG3_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69712   TIMER_OUTCFG0_OUTCFG3_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
69713 } TIMER_OUTCFG0_OUTCFG3_Enum;
69714 
69715 /* ============================================  TIMER OUTCFG0 OUTCFG2 [16..21]  ============================================= */
69716 typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG2                                                     */
69717   TIMER_OUTCFG0_OUTCFG2_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69718   TIMER_OUTCFG0_OUTCFG2_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69719   TIMER_OUTCFG0_OUTCFG2_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69720   TIMER_OUTCFG0_OUTCFG2_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69721   TIMER_OUTCFG0_OUTCFG2_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69722   TIMER_OUTCFG0_OUTCFG2_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69723   TIMER_OUTCFG0_OUTCFG2_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69724   TIMER_OUTCFG0_OUTCFG2_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69725   TIMER_OUTCFG0_OUTCFG2_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69726   TIMER_OUTCFG0_OUTCFG2_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69727   TIMER_OUTCFG0_OUTCFG2_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69728   TIMER_OUTCFG0_OUTCFG2_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69729   TIMER_OUTCFG0_OUTCFG2_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69730   TIMER_OUTCFG0_OUTCFG2_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69731   TIMER_OUTCFG0_OUTCFG2_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69732   TIMER_OUTCFG0_OUTCFG2_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69733   TIMER_OUTCFG0_OUTCFG2_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69734   TIMER_OUTCFG0_OUTCFG2_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69735   TIMER_OUTCFG0_OUTCFG2_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69736   TIMER_OUTCFG0_OUTCFG2_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69737   TIMER_OUTCFG0_OUTCFG2_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69738   TIMER_OUTCFG0_OUTCFG2_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69739   TIMER_OUTCFG0_OUTCFG2_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69740   TIMER_OUTCFG0_OUTCFG2_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69741   TIMER_OUTCFG0_OUTCFG2_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69742   TIMER_OUTCFG0_OUTCFG2_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69743   TIMER_OUTCFG0_OUTCFG2_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69744   TIMER_OUTCFG0_OUTCFG2_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69745   TIMER_OUTCFG0_OUTCFG2_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69746   TIMER_OUTCFG0_OUTCFG2_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69747   TIMER_OUTCFG0_OUTCFG2_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69748   TIMER_OUTCFG0_OUTCFG2_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69749   TIMER_OUTCFG0_OUTCFG2_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69750   TIMER_OUTCFG0_OUTCFG2_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69751   TIMER_OUTCFG0_OUTCFG2_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69752   TIMER_OUTCFG0_OUTCFG2_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69753   TIMER_OUTCFG0_OUTCFG2_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69754   TIMER_OUTCFG0_OUTCFG2_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69755   TIMER_OUTCFG0_OUTCFG2_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69756   TIMER_OUTCFG0_OUTCFG2_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69757   TIMER_OUTCFG0_OUTCFG2_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
69758 } TIMER_OUTCFG0_OUTCFG2_Enum;
69759 
69760 /* =============================================  TIMER OUTCFG0 OUTCFG1 [8..13]  ============================================= */
69761 typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG1                                                     */
69762   TIMER_OUTCFG0_OUTCFG1_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69763   TIMER_OUTCFG0_OUTCFG1_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69764   TIMER_OUTCFG0_OUTCFG1_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69765   TIMER_OUTCFG0_OUTCFG1_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69766   TIMER_OUTCFG0_OUTCFG1_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69767   TIMER_OUTCFG0_OUTCFG1_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69768   TIMER_OUTCFG0_OUTCFG1_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69769   TIMER_OUTCFG0_OUTCFG1_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69770   TIMER_OUTCFG0_OUTCFG1_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69771   TIMER_OUTCFG0_OUTCFG1_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69772   TIMER_OUTCFG0_OUTCFG1_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69773   TIMER_OUTCFG0_OUTCFG1_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69774   TIMER_OUTCFG0_OUTCFG1_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69775   TIMER_OUTCFG0_OUTCFG1_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69776   TIMER_OUTCFG0_OUTCFG1_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69777   TIMER_OUTCFG0_OUTCFG1_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69778   TIMER_OUTCFG0_OUTCFG1_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69779   TIMER_OUTCFG0_OUTCFG1_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69780   TIMER_OUTCFG0_OUTCFG1_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69781   TIMER_OUTCFG0_OUTCFG1_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69782   TIMER_OUTCFG0_OUTCFG1_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69783   TIMER_OUTCFG0_OUTCFG1_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69784   TIMER_OUTCFG0_OUTCFG1_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69785   TIMER_OUTCFG0_OUTCFG1_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69786   TIMER_OUTCFG0_OUTCFG1_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69787   TIMER_OUTCFG0_OUTCFG1_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69788   TIMER_OUTCFG0_OUTCFG1_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69789   TIMER_OUTCFG0_OUTCFG1_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69790   TIMER_OUTCFG0_OUTCFG1_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69791   TIMER_OUTCFG0_OUTCFG1_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69792   TIMER_OUTCFG0_OUTCFG1_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69793   TIMER_OUTCFG0_OUTCFG1_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69794   TIMER_OUTCFG0_OUTCFG1_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69795   TIMER_OUTCFG0_OUTCFG1_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69796   TIMER_OUTCFG0_OUTCFG1_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69797   TIMER_OUTCFG0_OUTCFG1_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69798   TIMER_OUTCFG0_OUTCFG1_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69799   TIMER_OUTCFG0_OUTCFG1_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69800   TIMER_OUTCFG0_OUTCFG1_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69801   TIMER_OUTCFG0_OUTCFG1_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69802   TIMER_OUTCFG0_OUTCFG1_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
69803 } TIMER_OUTCFG0_OUTCFG1_Enum;
69804 
69805 /* =============================================  TIMER OUTCFG0 OUTCFG0 [0..5]  ============================================== */
69806 typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG0                                                     */
69807   TIMER_OUTCFG0_OUTCFG0_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69808   TIMER_OUTCFG0_OUTCFG0_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69809   TIMER_OUTCFG0_OUTCFG0_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69810   TIMER_OUTCFG0_OUTCFG0_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69811   TIMER_OUTCFG0_OUTCFG0_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69812   TIMER_OUTCFG0_OUTCFG0_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69813   TIMER_OUTCFG0_OUTCFG0_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69814   TIMER_OUTCFG0_OUTCFG0_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69815   TIMER_OUTCFG0_OUTCFG0_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69816   TIMER_OUTCFG0_OUTCFG0_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69817   TIMER_OUTCFG0_OUTCFG0_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69818   TIMER_OUTCFG0_OUTCFG0_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69819   TIMER_OUTCFG0_OUTCFG0_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69820   TIMER_OUTCFG0_OUTCFG0_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69821   TIMER_OUTCFG0_OUTCFG0_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69822   TIMER_OUTCFG0_OUTCFG0_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69823   TIMER_OUTCFG0_OUTCFG0_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69824   TIMER_OUTCFG0_OUTCFG0_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69825   TIMER_OUTCFG0_OUTCFG0_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69826   TIMER_OUTCFG0_OUTCFG0_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69827   TIMER_OUTCFG0_OUTCFG0_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69828   TIMER_OUTCFG0_OUTCFG0_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69829   TIMER_OUTCFG0_OUTCFG0_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69830   TIMER_OUTCFG0_OUTCFG0_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69831   TIMER_OUTCFG0_OUTCFG0_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69832   TIMER_OUTCFG0_OUTCFG0_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69833   TIMER_OUTCFG0_OUTCFG0_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69834   TIMER_OUTCFG0_OUTCFG0_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69835   TIMER_OUTCFG0_OUTCFG0_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69836   TIMER_OUTCFG0_OUTCFG0_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69837   TIMER_OUTCFG0_OUTCFG0_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69838   TIMER_OUTCFG0_OUTCFG0_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69839   TIMER_OUTCFG0_OUTCFG0_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69840   TIMER_OUTCFG0_OUTCFG0_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69841   TIMER_OUTCFG0_OUTCFG0_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69842   TIMER_OUTCFG0_OUTCFG0_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69843   TIMER_OUTCFG0_OUTCFG0_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69844   TIMER_OUTCFG0_OUTCFG0_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69845   TIMER_OUTCFG0_OUTCFG0_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69846   TIMER_OUTCFG0_OUTCFG0_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69847   TIMER_OUTCFG0_OUTCFG0_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
69848 } TIMER_OUTCFG0_OUTCFG0_Enum;
69849 
69850 /* ========================================================  OUTCFG1  ======================================================== */
69851 /* ============================================  TIMER OUTCFG1 OUTCFG7 [24..29]  ============================================= */
69852 typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG7                                                     */
69853   TIMER_OUTCFG1_OUTCFG7_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69854   TIMER_OUTCFG1_OUTCFG7_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69855   TIMER_OUTCFG1_OUTCFG7_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69856   TIMER_OUTCFG1_OUTCFG7_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69857   TIMER_OUTCFG1_OUTCFG7_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69858   TIMER_OUTCFG1_OUTCFG7_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69859   TIMER_OUTCFG1_OUTCFG7_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69860   TIMER_OUTCFG1_OUTCFG7_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69861   TIMER_OUTCFG1_OUTCFG7_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69862   TIMER_OUTCFG1_OUTCFG7_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69863   TIMER_OUTCFG1_OUTCFG7_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69864   TIMER_OUTCFG1_OUTCFG7_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69865   TIMER_OUTCFG1_OUTCFG7_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69866   TIMER_OUTCFG1_OUTCFG7_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69867   TIMER_OUTCFG1_OUTCFG7_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69868   TIMER_OUTCFG1_OUTCFG7_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69869   TIMER_OUTCFG1_OUTCFG7_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69870   TIMER_OUTCFG1_OUTCFG7_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69871   TIMER_OUTCFG1_OUTCFG7_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69872   TIMER_OUTCFG1_OUTCFG7_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69873   TIMER_OUTCFG1_OUTCFG7_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69874   TIMER_OUTCFG1_OUTCFG7_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69875   TIMER_OUTCFG1_OUTCFG7_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69876   TIMER_OUTCFG1_OUTCFG7_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69877   TIMER_OUTCFG1_OUTCFG7_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69878   TIMER_OUTCFG1_OUTCFG7_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69879   TIMER_OUTCFG1_OUTCFG7_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69880   TIMER_OUTCFG1_OUTCFG7_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69881   TIMER_OUTCFG1_OUTCFG7_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69882   TIMER_OUTCFG1_OUTCFG7_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69883   TIMER_OUTCFG1_OUTCFG7_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69884   TIMER_OUTCFG1_OUTCFG7_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69885   TIMER_OUTCFG1_OUTCFG7_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69886   TIMER_OUTCFG1_OUTCFG7_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69887   TIMER_OUTCFG1_OUTCFG7_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69888   TIMER_OUTCFG1_OUTCFG7_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69889   TIMER_OUTCFG1_OUTCFG7_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69890   TIMER_OUTCFG1_OUTCFG7_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69891   TIMER_OUTCFG1_OUTCFG7_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69892   TIMER_OUTCFG1_OUTCFG7_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69893   TIMER_OUTCFG1_OUTCFG7_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
69894 } TIMER_OUTCFG1_OUTCFG7_Enum;
69895 
69896 /* ============================================  TIMER OUTCFG1 OUTCFG6 [16..21]  ============================================= */
69897 typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG6                                                     */
69898   TIMER_OUTCFG1_OUTCFG6_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69899   TIMER_OUTCFG1_OUTCFG6_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69900   TIMER_OUTCFG1_OUTCFG6_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69901   TIMER_OUTCFG1_OUTCFG6_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69902   TIMER_OUTCFG1_OUTCFG6_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69903   TIMER_OUTCFG1_OUTCFG6_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69904   TIMER_OUTCFG1_OUTCFG6_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69905   TIMER_OUTCFG1_OUTCFG6_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69906   TIMER_OUTCFG1_OUTCFG6_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69907   TIMER_OUTCFG1_OUTCFG6_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69908   TIMER_OUTCFG1_OUTCFG6_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69909   TIMER_OUTCFG1_OUTCFG6_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69910   TIMER_OUTCFG1_OUTCFG6_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69911   TIMER_OUTCFG1_OUTCFG6_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69912   TIMER_OUTCFG1_OUTCFG6_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69913   TIMER_OUTCFG1_OUTCFG6_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69914   TIMER_OUTCFG1_OUTCFG6_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69915   TIMER_OUTCFG1_OUTCFG6_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69916   TIMER_OUTCFG1_OUTCFG6_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69917   TIMER_OUTCFG1_OUTCFG6_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69918   TIMER_OUTCFG1_OUTCFG6_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69919   TIMER_OUTCFG1_OUTCFG6_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69920   TIMER_OUTCFG1_OUTCFG6_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69921   TIMER_OUTCFG1_OUTCFG6_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69922   TIMER_OUTCFG1_OUTCFG6_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69923   TIMER_OUTCFG1_OUTCFG6_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69924   TIMER_OUTCFG1_OUTCFG6_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69925   TIMER_OUTCFG1_OUTCFG6_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69926   TIMER_OUTCFG1_OUTCFG6_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69927   TIMER_OUTCFG1_OUTCFG6_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69928   TIMER_OUTCFG1_OUTCFG6_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69929   TIMER_OUTCFG1_OUTCFG6_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69930   TIMER_OUTCFG1_OUTCFG6_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69931   TIMER_OUTCFG1_OUTCFG6_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69932   TIMER_OUTCFG1_OUTCFG6_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69933   TIMER_OUTCFG1_OUTCFG6_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69934   TIMER_OUTCFG1_OUTCFG6_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69935   TIMER_OUTCFG1_OUTCFG6_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69936   TIMER_OUTCFG1_OUTCFG6_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69937   TIMER_OUTCFG1_OUTCFG6_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69938   TIMER_OUTCFG1_OUTCFG6_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
69939 } TIMER_OUTCFG1_OUTCFG6_Enum;
69940 
69941 /* =============================================  TIMER OUTCFG1 OUTCFG5 [8..13]  ============================================= */
69942 typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG5                                                     */
69943   TIMER_OUTCFG1_OUTCFG5_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69944   TIMER_OUTCFG1_OUTCFG5_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69945   TIMER_OUTCFG1_OUTCFG5_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69946   TIMER_OUTCFG1_OUTCFG5_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69947   TIMER_OUTCFG1_OUTCFG5_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69948   TIMER_OUTCFG1_OUTCFG5_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69949   TIMER_OUTCFG1_OUTCFG5_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69950   TIMER_OUTCFG1_OUTCFG5_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69951   TIMER_OUTCFG1_OUTCFG5_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69952   TIMER_OUTCFG1_OUTCFG5_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69953   TIMER_OUTCFG1_OUTCFG5_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69954   TIMER_OUTCFG1_OUTCFG5_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
69955   TIMER_OUTCFG1_OUTCFG5_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
69956   TIMER_OUTCFG1_OUTCFG5_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
69957   TIMER_OUTCFG1_OUTCFG5_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
69958   TIMER_OUTCFG1_OUTCFG5_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
69959   TIMER_OUTCFG1_OUTCFG5_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
69960   TIMER_OUTCFG1_OUTCFG5_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
69961   TIMER_OUTCFG1_OUTCFG5_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
69962   TIMER_OUTCFG1_OUTCFG5_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
69963   TIMER_OUTCFG1_OUTCFG5_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
69964   TIMER_OUTCFG1_OUTCFG5_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
69965   TIMER_OUTCFG1_OUTCFG5_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
69966   TIMER_OUTCFG1_OUTCFG5_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
69967   TIMER_OUTCFG1_OUTCFG5_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
69968   TIMER_OUTCFG1_OUTCFG5_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
69969   TIMER_OUTCFG1_OUTCFG5_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
69970   TIMER_OUTCFG1_OUTCFG5_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
69971   TIMER_OUTCFG1_OUTCFG5_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
69972   TIMER_OUTCFG1_OUTCFG5_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
69973   TIMER_OUTCFG1_OUTCFG5_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
69974   TIMER_OUTCFG1_OUTCFG5_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
69975   TIMER_OUTCFG1_OUTCFG5_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
69976   TIMER_OUTCFG1_OUTCFG5_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
69977   TIMER_OUTCFG1_OUTCFG5_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
69978   TIMER_OUTCFG1_OUTCFG5_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
69979   TIMER_OUTCFG1_OUTCFG5_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
69980   TIMER_OUTCFG1_OUTCFG5_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
69981   TIMER_OUTCFG1_OUTCFG5_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
69982   TIMER_OUTCFG1_OUTCFG5_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
69983   TIMER_OUTCFG1_OUTCFG5_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
69984 } TIMER_OUTCFG1_OUTCFG5_Enum;
69985 
69986 /* =============================================  TIMER OUTCFG1 OUTCFG4 [0..5]  ============================================== */
69987 typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG4                                                     */
69988   TIMER_OUTCFG1_OUTCFG4_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
69989   TIMER_OUTCFG1_OUTCFG4_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
69990   TIMER_OUTCFG1_OUTCFG4_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
69991   TIMER_OUTCFG1_OUTCFG4_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
69992   TIMER_OUTCFG1_OUTCFG4_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
69993   TIMER_OUTCFG1_OUTCFG4_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
69994   TIMER_OUTCFG1_OUTCFG4_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
69995   TIMER_OUTCFG1_OUTCFG4_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
69996   TIMER_OUTCFG1_OUTCFG4_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
69997   TIMER_OUTCFG1_OUTCFG4_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
69998   TIMER_OUTCFG1_OUTCFG4_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
69999   TIMER_OUTCFG1_OUTCFG4_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70000   TIMER_OUTCFG1_OUTCFG4_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70001   TIMER_OUTCFG1_OUTCFG4_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70002   TIMER_OUTCFG1_OUTCFG4_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70003   TIMER_OUTCFG1_OUTCFG4_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70004   TIMER_OUTCFG1_OUTCFG4_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70005   TIMER_OUTCFG1_OUTCFG4_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70006   TIMER_OUTCFG1_OUTCFG4_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70007   TIMER_OUTCFG1_OUTCFG4_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70008   TIMER_OUTCFG1_OUTCFG4_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70009   TIMER_OUTCFG1_OUTCFG4_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70010   TIMER_OUTCFG1_OUTCFG4_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70011   TIMER_OUTCFG1_OUTCFG4_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70012   TIMER_OUTCFG1_OUTCFG4_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70013   TIMER_OUTCFG1_OUTCFG4_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70014   TIMER_OUTCFG1_OUTCFG4_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70015   TIMER_OUTCFG1_OUTCFG4_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70016   TIMER_OUTCFG1_OUTCFG4_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70017   TIMER_OUTCFG1_OUTCFG4_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70018   TIMER_OUTCFG1_OUTCFG4_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70019   TIMER_OUTCFG1_OUTCFG4_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70020   TIMER_OUTCFG1_OUTCFG4_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70021   TIMER_OUTCFG1_OUTCFG4_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70022   TIMER_OUTCFG1_OUTCFG4_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70023   TIMER_OUTCFG1_OUTCFG4_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70024   TIMER_OUTCFG1_OUTCFG4_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70025   TIMER_OUTCFG1_OUTCFG4_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70026   TIMER_OUTCFG1_OUTCFG4_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70027   TIMER_OUTCFG1_OUTCFG4_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70028   TIMER_OUTCFG1_OUTCFG4_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
70029 } TIMER_OUTCFG1_OUTCFG4_Enum;
70030 
70031 /* ========================================================  OUTCFG2  ======================================================== */
70032 /* ============================================  TIMER OUTCFG2 OUTCFG11 [24..29]  ============================================ */
70033 typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG11                                                    */
70034   TIMER_OUTCFG2_OUTCFG11_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70035   TIMER_OUTCFG2_OUTCFG11_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70036   TIMER_OUTCFG2_OUTCFG11_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70037   TIMER_OUTCFG2_OUTCFG11_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70038   TIMER_OUTCFG2_OUTCFG11_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70039   TIMER_OUTCFG2_OUTCFG11_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70040   TIMER_OUTCFG2_OUTCFG11_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70041   TIMER_OUTCFG2_OUTCFG11_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70042   TIMER_OUTCFG2_OUTCFG11_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70043   TIMER_OUTCFG2_OUTCFG11_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70044   TIMER_OUTCFG2_OUTCFG11_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70045   TIMER_OUTCFG2_OUTCFG11_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70046   TIMER_OUTCFG2_OUTCFG11_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70047   TIMER_OUTCFG2_OUTCFG11_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70048   TIMER_OUTCFG2_OUTCFG11_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70049   TIMER_OUTCFG2_OUTCFG11_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70050   TIMER_OUTCFG2_OUTCFG11_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70051   TIMER_OUTCFG2_OUTCFG11_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70052   TIMER_OUTCFG2_OUTCFG11_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70053   TIMER_OUTCFG2_OUTCFG11_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70054   TIMER_OUTCFG2_OUTCFG11_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70055   TIMER_OUTCFG2_OUTCFG11_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70056   TIMER_OUTCFG2_OUTCFG11_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70057   TIMER_OUTCFG2_OUTCFG11_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70058   TIMER_OUTCFG2_OUTCFG11_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70059   TIMER_OUTCFG2_OUTCFG11_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70060   TIMER_OUTCFG2_OUTCFG11_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70061   TIMER_OUTCFG2_OUTCFG11_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70062   TIMER_OUTCFG2_OUTCFG11_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70063   TIMER_OUTCFG2_OUTCFG11_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70064   TIMER_OUTCFG2_OUTCFG11_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70065   TIMER_OUTCFG2_OUTCFG11_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70066   TIMER_OUTCFG2_OUTCFG11_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70067   TIMER_OUTCFG2_OUTCFG11_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70068   TIMER_OUTCFG2_OUTCFG11_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70069   TIMER_OUTCFG2_OUTCFG11_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70070   TIMER_OUTCFG2_OUTCFG11_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70071   TIMER_OUTCFG2_OUTCFG11_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70072   TIMER_OUTCFG2_OUTCFG11_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70073   TIMER_OUTCFG2_OUTCFG11_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70074   TIMER_OUTCFG2_OUTCFG11_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70075 } TIMER_OUTCFG2_OUTCFG11_Enum;
70076 
70077 /* ============================================  TIMER OUTCFG2 OUTCFG10 [16..21]  ============================================ */
70078 typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG10                                                    */
70079   TIMER_OUTCFG2_OUTCFG10_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70080   TIMER_OUTCFG2_OUTCFG10_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70081   TIMER_OUTCFG2_OUTCFG10_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70082   TIMER_OUTCFG2_OUTCFG10_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70083   TIMER_OUTCFG2_OUTCFG10_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70084   TIMER_OUTCFG2_OUTCFG10_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70085   TIMER_OUTCFG2_OUTCFG10_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70086   TIMER_OUTCFG2_OUTCFG10_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70087   TIMER_OUTCFG2_OUTCFG10_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70088   TIMER_OUTCFG2_OUTCFG10_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70089   TIMER_OUTCFG2_OUTCFG10_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70090   TIMER_OUTCFG2_OUTCFG10_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70091   TIMER_OUTCFG2_OUTCFG10_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70092   TIMER_OUTCFG2_OUTCFG10_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70093   TIMER_OUTCFG2_OUTCFG10_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70094   TIMER_OUTCFG2_OUTCFG10_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70095   TIMER_OUTCFG2_OUTCFG10_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70096   TIMER_OUTCFG2_OUTCFG10_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70097   TIMER_OUTCFG2_OUTCFG10_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70098   TIMER_OUTCFG2_OUTCFG10_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70099   TIMER_OUTCFG2_OUTCFG10_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70100   TIMER_OUTCFG2_OUTCFG10_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70101   TIMER_OUTCFG2_OUTCFG10_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70102   TIMER_OUTCFG2_OUTCFG10_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70103   TIMER_OUTCFG2_OUTCFG10_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70104   TIMER_OUTCFG2_OUTCFG10_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70105   TIMER_OUTCFG2_OUTCFG10_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70106   TIMER_OUTCFG2_OUTCFG10_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70107   TIMER_OUTCFG2_OUTCFG10_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70108   TIMER_OUTCFG2_OUTCFG10_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70109   TIMER_OUTCFG2_OUTCFG10_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70110   TIMER_OUTCFG2_OUTCFG10_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70111   TIMER_OUTCFG2_OUTCFG10_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70112   TIMER_OUTCFG2_OUTCFG10_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70113   TIMER_OUTCFG2_OUTCFG10_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70114   TIMER_OUTCFG2_OUTCFG10_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70115   TIMER_OUTCFG2_OUTCFG10_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70116   TIMER_OUTCFG2_OUTCFG10_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70117   TIMER_OUTCFG2_OUTCFG10_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70118   TIMER_OUTCFG2_OUTCFG10_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70119   TIMER_OUTCFG2_OUTCFG10_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70120 } TIMER_OUTCFG2_OUTCFG10_Enum;
70121 
70122 /* =============================================  TIMER OUTCFG2 OUTCFG9 [8..13]  ============================================= */
70123 typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG9                                                     */
70124   TIMER_OUTCFG2_OUTCFG9_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70125   TIMER_OUTCFG2_OUTCFG9_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70126   TIMER_OUTCFG2_OUTCFG9_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70127   TIMER_OUTCFG2_OUTCFG9_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70128   TIMER_OUTCFG2_OUTCFG9_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70129   TIMER_OUTCFG2_OUTCFG9_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70130   TIMER_OUTCFG2_OUTCFG9_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70131   TIMER_OUTCFG2_OUTCFG9_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70132   TIMER_OUTCFG2_OUTCFG9_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70133   TIMER_OUTCFG2_OUTCFG9_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70134   TIMER_OUTCFG2_OUTCFG9_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70135   TIMER_OUTCFG2_OUTCFG9_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70136   TIMER_OUTCFG2_OUTCFG9_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70137   TIMER_OUTCFG2_OUTCFG9_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70138   TIMER_OUTCFG2_OUTCFG9_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70139   TIMER_OUTCFG2_OUTCFG9_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70140   TIMER_OUTCFG2_OUTCFG9_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70141   TIMER_OUTCFG2_OUTCFG9_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70142   TIMER_OUTCFG2_OUTCFG9_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70143   TIMER_OUTCFG2_OUTCFG9_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70144   TIMER_OUTCFG2_OUTCFG9_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70145   TIMER_OUTCFG2_OUTCFG9_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70146   TIMER_OUTCFG2_OUTCFG9_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70147   TIMER_OUTCFG2_OUTCFG9_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70148   TIMER_OUTCFG2_OUTCFG9_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70149   TIMER_OUTCFG2_OUTCFG9_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70150   TIMER_OUTCFG2_OUTCFG9_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70151   TIMER_OUTCFG2_OUTCFG9_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70152   TIMER_OUTCFG2_OUTCFG9_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70153   TIMER_OUTCFG2_OUTCFG9_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70154   TIMER_OUTCFG2_OUTCFG9_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70155   TIMER_OUTCFG2_OUTCFG9_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70156   TIMER_OUTCFG2_OUTCFG9_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70157   TIMER_OUTCFG2_OUTCFG9_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70158   TIMER_OUTCFG2_OUTCFG9_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70159   TIMER_OUTCFG2_OUTCFG9_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70160   TIMER_OUTCFG2_OUTCFG9_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70161   TIMER_OUTCFG2_OUTCFG9_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70162   TIMER_OUTCFG2_OUTCFG9_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70163   TIMER_OUTCFG2_OUTCFG9_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70164   TIMER_OUTCFG2_OUTCFG9_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
70165 } TIMER_OUTCFG2_OUTCFG9_Enum;
70166 
70167 /* =============================================  TIMER OUTCFG2 OUTCFG8 [0..5]  ============================================== */
70168 typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG8                                                     */
70169   TIMER_OUTCFG2_OUTCFG8_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70170   TIMER_OUTCFG2_OUTCFG8_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70171   TIMER_OUTCFG2_OUTCFG8_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70172   TIMER_OUTCFG2_OUTCFG8_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70173   TIMER_OUTCFG2_OUTCFG8_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70174   TIMER_OUTCFG2_OUTCFG8_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70175   TIMER_OUTCFG2_OUTCFG8_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70176   TIMER_OUTCFG2_OUTCFG8_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70177   TIMER_OUTCFG2_OUTCFG8_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70178   TIMER_OUTCFG2_OUTCFG8_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70179   TIMER_OUTCFG2_OUTCFG8_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70180   TIMER_OUTCFG2_OUTCFG8_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70181   TIMER_OUTCFG2_OUTCFG8_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70182   TIMER_OUTCFG2_OUTCFG8_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70183   TIMER_OUTCFG2_OUTCFG8_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70184   TIMER_OUTCFG2_OUTCFG8_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70185   TIMER_OUTCFG2_OUTCFG8_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70186   TIMER_OUTCFG2_OUTCFG8_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70187   TIMER_OUTCFG2_OUTCFG8_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70188   TIMER_OUTCFG2_OUTCFG8_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70189   TIMER_OUTCFG2_OUTCFG8_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70190   TIMER_OUTCFG2_OUTCFG8_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70191   TIMER_OUTCFG2_OUTCFG8_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70192   TIMER_OUTCFG2_OUTCFG8_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70193   TIMER_OUTCFG2_OUTCFG8_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70194   TIMER_OUTCFG2_OUTCFG8_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70195   TIMER_OUTCFG2_OUTCFG8_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70196   TIMER_OUTCFG2_OUTCFG8_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70197   TIMER_OUTCFG2_OUTCFG8_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70198   TIMER_OUTCFG2_OUTCFG8_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70199   TIMER_OUTCFG2_OUTCFG8_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70200   TIMER_OUTCFG2_OUTCFG8_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70201   TIMER_OUTCFG2_OUTCFG8_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70202   TIMER_OUTCFG2_OUTCFG8_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70203   TIMER_OUTCFG2_OUTCFG8_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70204   TIMER_OUTCFG2_OUTCFG8_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70205   TIMER_OUTCFG2_OUTCFG8_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70206   TIMER_OUTCFG2_OUTCFG8_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70207   TIMER_OUTCFG2_OUTCFG8_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70208   TIMER_OUTCFG2_OUTCFG8_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70209   TIMER_OUTCFG2_OUTCFG8_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
70210 } TIMER_OUTCFG2_OUTCFG8_Enum;
70211 
70212 /* ========================================================  OUTCFG3  ======================================================== */
70213 /* ============================================  TIMER OUTCFG3 OUTCFG15 [24..29]  ============================================ */
70214 typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG15                                                    */
70215   TIMER_OUTCFG3_OUTCFG15_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70216   TIMER_OUTCFG3_OUTCFG15_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70217   TIMER_OUTCFG3_OUTCFG15_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70218   TIMER_OUTCFG3_OUTCFG15_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70219   TIMER_OUTCFG3_OUTCFG15_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70220   TIMER_OUTCFG3_OUTCFG15_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70221   TIMER_OUTCFG3_OUTCFG15_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70222   TIMER_OUTCFG3_OUTCFG15_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70223   TIMER_OUTCFG3_OUTCFG15_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70224   TIMER_OUTCFG3_OUTCFG15_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70225   TIMER_OUTCFG3_OUTCFG15_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70226   TIMER_OUTCFG3_OUTCFG15_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70227   TIMER_OUTCFG3_OUTCFG15_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70228   TIMER_OUTCFG3_OUTCFG15_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70229   TIMER_OUTCFG3_OUTCFG15_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70230   TIMER_OUTCFG3_OUTCFG15_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70231   TIMER_OUTCFG3_OUTCFG15_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70232   TIMER_OUTCFG3_OUTCFG15_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70233   TIMER_OUTCFG3_OUTCFG15_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70234   TIMER_OUTCFG3_OUTCFG15_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70235   TIMER_OUTCFG3_OUTCFG15_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70236   TIMER_OUTCFG3_OUTCFG15_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70237   TIMER_OUTCFG3_OUTCFG15_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70238   TIMER_OUTCFG3_OUTCFG15_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70239   TIMER_OUTCFG3_OUTCFG15_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70240   TIMER_OUTCFG3_OUTCFG15_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70241   TIMER_OUTCFG3_OUTCFG15_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70242   TIMER_OUTCFG3_OUTCFG15_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70243   TIMER_OUTCFG3_OUTCFG15_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70244   TIMER_OUTCFG3_OUTCFG15_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70245   TIMER_OUTCFG3_OUTCFG15_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70246   TIMER_OUTCFG3_OUTCFG15_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70247   TIMER_OUTCFG3_OUTCFG15_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70248   TIMER_OUTCFG3_OUTCFG15_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70249   TIMER_OUTCFG3_OUTCFG15_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70250   TIMER_OUTCFG3_OUTCFG15_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70251   TIMER_OUTCFG3_OUTCFG15_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70252   TIMER_OUTCFG3_OUTCFG15_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70253   TIMER_OUTCFG3_OUTCFG15_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70254   TIMER_OUTCFG3_OUTCFG15_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70255   TIMER_OUTCFG3_OUTCFG15_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70256 } TIMER_OUTCFG3_OUTCFG15_Enum;
70257 
70258 /* ============================================  TIMER OUTCFG3 OUTCFG14 [16..21]  ============================================ */
70259 typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG14                                                    */
70260   TIMER_OUTCFG3_OUTCFG14_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70261   TIMER_OUTCFG3_OUTCFG14_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70262   TIMER_OUTCFG3_OUTCFG14_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70263   TIMER_OUTCFG3_OUTCFG14_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70264   TIMER_OUTCFG3_OUTCFG14_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70265   TIMER_OUTCFG3_OUTCFG14_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70266   TIMER_OUTCFG3_OUTCFG14_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70267   TIMER_OUTCFG3_OUTCFG14_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70268   TIMER_OUTCFG3_OUTCFG14_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70269   TIMER_OUTCFG3_OUTCFG14_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70270   TIMER_OUTCFG3_OUTCFG14_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70271   TIMER_OUTCFG3_OUTCFG14_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70272   TIMER_OUTCFG3_OUTCFG14_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70273   TIMER_OUTCFG3_OUTCFG14_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70274   TIMER_OUTCFG3_OUTCFG14_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70275   TIMER_OUTCFG3_OUTCFG14_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70276   TIMER_OUTCFG3_OUTCFG14_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70277   TIMER_OUTCFG3_OUTCFG14_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70278   TIMER_OUTCFG3_OUTCFG14_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70279   TIMER_OUTCFG3_OUTCFG14_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70280   TIMER_OUTCFG3_OUTCFG14_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70281   TIMER_OUTCFG3_OUTCFG14_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70282   TIMER_OUTCFG3_OUTCFG14_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70283   TIMER_OUTCFG3_OUTCFG14_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70284   TIMER_OUTCFG3_OUTCFG14_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70285   TIMER_OUTCFG3_OUTCFG14_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70286   TIMER_OUTCFG3_OUTCFG14_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70287   TIMER_OUTCFG3_OUTCFG14_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70288   TIMER_OUTCFG3_OUTCFG14_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70289   TIMER_OUTCFG3_OUTCFG14_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70290   TIMER_OUTCFG3_OUTCFG14_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70291   TIMER_OUTCFG3_OUTCFG14_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70292   TIMER_OUTCFG3_OUTCFG14_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70293   TIMER_OUTCFG3_OUTCFG14_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70294   TIMER_OUTCFG3_OUTCFG14_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70295   TIMER_OUTCFG3_OUTCFG14_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70296   TIMER_OUTCFG3_OUTCFG14_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70297   TIMER_OUTCFG3_OUTCFG14_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70298   TIMER_OUTCFG3_OUTCFG14_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70299   TIMER_OUTCFG3_OUTCFG14_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70300   TIMER_OUTCFG3_OUTCFG14_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70301 } TIMER_OUTCFG3_OUTCFG14_Enum;
70302 
70303 /* ============================================  TIMER OUTCFG3 OUTCFG13 [8..13]  ============================================= */
70304 typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG13                                                    */
70305   TIMER_OUTCFG3_OUTCFG13_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70306   TIMER_OUTCFG3_OUTCFG13_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70307   TIMER_OUTCFG3_OUTCFG13_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70308   TIMER_OUTCFG3_OUTCFG13_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70309   TIMER_OUTCFG3_OUTCFG13_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70310   TIMER_OUTCFG3_OUTCFG13_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70311   TIMER_OUTCFG3_OUTCFG13_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70312   TIMER_OUTCFG3_OUTCFG13_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70313   TIMER_OUTCFG3_OUTCFG13_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70314   TIMER_OUTCFG3_OUTCFG13_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70315   TIMER_OUTCFG3_OUTCFG13_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70316   TIMER_OUTCFG3_OUTCFG13_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70317   TIMER_OUTCFG3_OUTCFG13_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70318   TIMER_OUTCFG3_OUTCFG13_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70319   TIMER_OUTCFG3_OUTCFG13_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70320   TIMER_OUTCFG3_OUTCFG13_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70321   TIMER_OUTCFG3_OUTCFG13_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70322   TIMER_OUTCFG3_OUTCFG13_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70323   TIMER_OUTCFG3_OUTCFG13_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70324   TIMER_OUTCFG3_OUTCFG13_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70325   TIMER_OUTCFG3_OUTCFG13_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70326   TIMER_OUTCFG3_OUTCFG13_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70327   TIMER_OUTCFG3_OUTCFG13_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70328   TIMER_OUTCFG3_OUTCFG13_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70329   TIMER_OUTCFG3_OUTCFG13_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70330   TIMER_OUTCFG3_OUTCFG13_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70331   TIMER_OUTCFG3_OUTCFG13_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70332   TIMER_OUTCFG3_OUTCFG13_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70333   TIMER_OUTCFG3_OUTCFG13_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70334   TIMER_OUTCFG3_OUTCFG13_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70335   TIMER_OUTCFG3_OUTCFG13_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70336   TIMER_OUTCFG3_OUTCFG13_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70337   TIMER_OUTCFG3_OUTCFG13_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70338   TIMER_OUTCFG3_OUTCFG13_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70339   TIMER_OUTCFG3_OUTCFG13_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70340   TIMER_OUTCFG3_OUTCFG13_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70341   TIMER_OUTCFG3_OUTCFG13_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70342   TIMER_OUTCFG3_OUTCFG13_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70343   TIMER_OUTCFG3_OUTCFG13_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70344   TIMER_OUTCFG3_OUTCFG13_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70345   TIMER_OUTCFG3_OUTCFG13_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70346 } TIMER_OUTCFG3_OUTCFG13_Enum;
70347 
70348 /* =============================================  TIMER OUTCFG3 OUTCFG12 [0..5]  ============================================= */
70349 typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG12                                                    */
70350   TIMER_OUTCFG3_OUTCFG12_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70351   TIMER_OUTCFG3_OUTCFG12_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70352   TIMER_OUTCFG3_OUTCFG12_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70353   TIMER_OUTCFG3_OUTCFG12_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70354   TIMER_OUTCFG3_OUTCFG12_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70355   TIMER_OUTCFG3_OUTCFG12_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70356   TIMER_OUTCFG3_OUTCFG12_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70357   TIMER_OUTCFG3_OUTCFG12_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70358   TIMER_OUTCFG3_OUTCFG12_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70359   TIMER_OUTCFG3_OUTCFG12_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70360   TIMER_OUTCFG3_OUTCFG12_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70361   TIMER_OUTCFG3_OUTCFG12_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70362   TIMER_OUTCFG3_OUTCFG12_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70363   TIMER_OUTCFG3_OUTCFG12_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70364   TIMER_OUTCFG3_OUTCFG12_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70365   TIMER_OUTCFG3_OUTCFG12_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70366   TIMER_OUTCFG3_OUTCFG12_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70367   TIMER_OUTCFG3_OUTCFG12_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70368   TIMER_OUTCFG3_OUTCFG12_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70369   TIMER_OUTCFG3_OUTCFG12_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70370   TIMER_OUTCFG3_OUTCFG12_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70371   TIMER_OUTCFG3_OUTCFG12_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70372   TIMER_OUTCFG3_OUTCFG12_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70373   TIMER_OUTCFG3_OUTCFG12_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70374   TIMER_OUTCFG3_OUTCFG12_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70375   TIMER_OUTCFG3_OUTCFG12_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70376   TIMER_OUTCFG3_OUTCFG12_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70377   TIMER_OUTCFG3_OUTCFG12_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70378   TIMER_OUTCFG3_OUTCFG12_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70379   TIMER_OUTCFG3_OUTCFG12_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70380   TIMER_OUTCFG3_OUTCFG12_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70381   TIMER_OUTCFG3_OUTCFG12_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70382   TIMER_OUTCFG3_OUTCFG12_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70383   TIMER_OUTCFG3_OUTCFG12_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70384   TIMER_OUTCFG3_OUTCFG12_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70385   TIMER_OUTCFG3_OUTCFG12_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70386   TIMER_OUTCFG3_OUTCFG12_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70387   TIMER_OUTCFG3_OUTCFG12_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70388   TIMER_OUTCFG3_OUTCFG12_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70389   TIMER_OUTCFG3_OUTCFG12_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70390   TIMER_OUTCFG3_OUTCFG12_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70391 } TIMER_OUTCFG3_OUTCFG12_Enum;
70392 
70393 /* ========================================================  OUTCFG4  ======================================================== */
70394 /* ============================================  TIMER OUTCFG4 OUTCFG19 [24..29]  ============================================ */
70395 typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG19                                                    */
70396   TIMER_OUTCFG4_OUTCFG19_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70397   TIMER_OUTCFG4_OUTCFG19_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70398   TIMER_OUTCFG4_OUTCFG19_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70399   TIMER_OUTCFG4_OUTCFG19_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70400   TIMER_OUTCFG4_OUTCFG19_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70401   TIMER_OUTCFG4_OUTCFG19_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70402   TIMER_OUTCFG4_OUTCFG19_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70403   TIMER_OUTCFG4_OUTCFG19_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70404   TIMER_OUTCFG4_OUTCFG19_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70405   TIMER_OUTCFG4_OUTCFG19_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70406   TIMER_OUTCFG4_OUTCFG19_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70407   TIMER_OUTCFG4_OUTCFG19_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70408   TIMER_OUTCFG4_OUTCFG19_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70409   TIMER_OUTCFG4_OUTCFG19_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70410   TIMER_OUTCFG4_OUTCFG19_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70411   TIMER_OUTCFG4_OUTCFG19_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70412   TIMER_OUTCFG4_OUTCFG19_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70413   TIMER_OUTCFG4_OUTCFG19_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70414   TIMER_OUTCFG4_OUTCFG19_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70415   TIMER_OUTCFG4_OUTCFG19_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70416   TIMER_OUTCFG4_OUTCFG19_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70417   TIMER_OUTCFG4_OUTCFG19_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70418   TIMER_OUTCFG4_OUTCFG19_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70419   TIMER_OUTCFG4_OUTCFG19_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70420   TIMER_OUTCFG4_OUTCFG19_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70421   TIMER_OUTCFG4_OUTCFG19_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70422   TIMER_OUTCFG4_OUTCFG19_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70423   TIMER_OUTCFG4_OUTCFG19_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70424   TIMER_OUTCFG4_OUTCFG19_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70425   TIMER_OUTCFG4_OUTCFG19_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70426   TIMER_OUTCFG4_OUTCFG19_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70427   TIMER_OUTCFG4_OUTCFG19_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70428   TIMER_OUTCFG4_OUTCFG19_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70429   TIMER_OUTCFG4_OUTCFG19_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70430   TIMER_OUTCFG4_OUTCFG19_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70431   TIMER_OUTCFG4_OUTCFG19_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70432   TIMER_OUTCFG4_OUTCFG19_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70433   TIMER_OUTCFG4_OUTCFG19_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70434   TIMER_OUTCFG4_OUTCFG19_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70435   TIMER_OUTCFG4_OUTCFG19_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70436   TIMER_OUTCFG4_OUTCFG19_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70437 } TIMER_OUTCFG4_OUTCFG19_Enum;
70438 
70439 /* ============================================  TIMER OUTCFG4 OUTCFG18 [16..21]  ============================================ */
70440 typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG18                                                    */
70441   TIMER_OUTCFG4_OUTCFG18_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70442   TIMER_OUTCFG4_OUTCFG18_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70443   TIMER_OUTCFG4_OUTCFG18_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70444   TIMER_OUTCFG4_OUTCFG18_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70445   TIMER_OUTCFG4_OUTCFG18_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70446   TIMER_OUTCFG4_OUTCFG18_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70447   TIMER_OUTCFG4_OUTCFG18_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70448   TIMER_OUTCFG4_OUTCFG18_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70449   TIMER_OUTCFG4_OUTCFG18_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70450   TIMER_OUTCFG4_OUTCFG18_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70451   TIMER_OUTCFG4_OUTCFG18_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70452   TIMER_OUTCFG4_OUTCFG18_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70453   TIMER_OUTCFG4_OUTCFG18_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70454   TIMER_OUTCFG4_OUTCFG18_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70455   TIMER_OUTCFG4_OUTCFG18_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70456   TIMER_OUTCFG4_OUTCFG18_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70457   TIMER_OUTCFG4_OUTCFG18_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70458   TIMER_OUTCFG4_OUTCFG18_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70459   TIMER_OUTCFG4_OUTCFG18_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70460   TIMER_OUTCFG4_OUTCFG18_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70461   TIMER_OUTCFG4_OUTCFG18_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70462   TIMER_OUTCFG4_OUTCFG18_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70463   TIMER_OUTCFG4_OUTCFG18_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70464   TIMER_OUTCFG4_OUTCFG18_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70465   TIMER_OUTCFG4_OUTCFG18_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70466   TIMER_OUTCFG4_OUTCFG18_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70467   TIMER_OUTCFG4_OUTCFG18_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70468   TIMER_OUTCFG4_OUTCFG18_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70469   TIMER_OUTCFG4_OUTCFG18_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70470   TIMER_OUTCFG4_OUTCFG18_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70471   TIMER_OUTCFG4_OUTCFG18_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70472   TIMER_OUTCFG4_OUTCFG18_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70473   TIMER_OUTCFG4_OUTCFG18_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70474   TIMER_OUTCFG4_OUTCFG18_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70475   TIMER_OUTCFG4_OUTCFG18_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70476   TIMER_OUTCFG4_OUTCFG18_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70477   TIMER_OUTCFG4_OUTCFG18_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70478   TIMER_OUTCFG4_OUTCFG18_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70479   TIMER_OUTCFG4_OUTCFG18_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70480   TIMER_OUTCFG4_OUTCFG18_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70481   TIMER_OUTCFG4_OUTCFG18_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70482 } TIMER_OUTCFG4_OUTCFG18_Enum;
70483 
70484 /* ============================================  TIMER OUTCFG4 OUTCFG17 [8..13]  ============================================= */
70485 typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG17                                                    */
70486   TIMER_OUTCFG4_OUTCFG17_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70487   TIMER_OUTCFG4_OUTCFG17_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70488   TIMER_OUTCFG4_OUTCFG17_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70489   TIMER_OUTCFG4_OUTCFG17_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70490   TIMER_OUTCFG4_OUTCFG17_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70491   TIMER_OUTCFG4_OUTCFG17_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70492   TIMER_OUTCFG4_OUTCFG17_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70493   TIMER_OUTCFG4_OUTCFG17_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70494   TIMER_OUTCFG4_OUTCFG17_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70495   TIMER_OUTCFG4_OUTCFG17_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70496   TIMER_OUTCFG4_OUTCFG17_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70497   TIMER_OUTCFG4_OUTCFG17_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70498   TIMER_OUTCFG4_OUTCFG17_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70499   TIMER_OUTCFG4_OUTCFG17_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70500   TIMER_OUTCFG4_OUTCFG17_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70501   TIMER_OUTCFG4_OUTCFG17_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70502   TIMER_OUTCFG4_OUTCFG17_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70503   TIMER_OUTCFG4_OUTCFG17_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70504   TIMER_OUTCFG4_OUTCFG17_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70505   TIMER_OUTCFG4_OUTCFG17_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70506   TIMER_OUTCFG4_OUTCFG17_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70507   TIMER_OUTCFG4_OUTCFG17_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70508   TIMER_OUTCFG4_OUTCFG17_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70509   TIMER_OUTCFG4_OUTCFG17_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70510   TIMER_OUTCFG4_OUTCFG17_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70511   TIMER_OUTCFG4_OUTCFG17_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70512   TIMER_OUTCFG4_OUTCFG17_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70513   TIMER_OUTCFG4_OUTCFG17_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70514   TIMER_OUTCFG4_OUTCFG17_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70515   TIMER_OUTCFG4_OUTCFG17_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70516   TIMER_OUTCFG4_OUTCFG17_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70517   TIMER_OUTCFG4_OUTCFG17_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70518   TIMER_OUTCFG4_OUTCFG17_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70519   TIMER_OUTCFG4_OUTCFG17_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70520   TIMER_OUTCFG4_OUTCFG17_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70521   TIMER_OUTCFG4_OUTCFG17_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70522   TIMER_OUTCFG4_OUTCFG17_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70523   TIMER_OUTCFG4_OUTCFG17_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70524   TIMER_OUTCFG4_OUTCFG17_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70525   TIMER_OUTCFG4_OUTCFG17_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70526   TIMER_OUTCFG4_OUTCFG17_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70527 } TIMER_OUTCFG4_OUTCFG17_Enum;
70528 
70529 /* =============================================  TIMER OUTCFG4 OUTCFG16 [0..5]  ============================================= */
70530 typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG16                                                    */
70531   TIMER_OUTCFG4_OUTCFG16_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70532   TIMER_OUTCFG4_OUTCFG16_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70533   TIMER_OUTCFG4_OUTCFG16_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70534   TIMER_OUTCFG4_OUTCFG16_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70535   TIMER_OUTCFG4_OUTCFG16_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70536   TIMER_OUTCFG4_OUTCFG16_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70537   TIMER_OUTCFG4_OUTCFG16_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70538   TIMER_OUTCFG4_OUTCFG16_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70539   TIMER_OUTCFG4_OUTCFG16_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70540   TIMER_OUTCFG4_OUTCFG16_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70541   TIMER_OUTCFG4_OUTCFG16_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70542   TIMER_OUTCFG4_OUTCFG16_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70543   TIMER_OUTCFG4_OUTCFG16_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70544   TIMER_OUTCFG4_OUTCFG16_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70545   TIMER_OUTCFG4_OUTCFG16_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70546   TIMER_OUTCFG4_OUTCFG16_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70547   TIMER_OUTCFG4_OUTCFG16_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70548   TIMER_OUTCFG4_OUTCFG16_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70549   TIMER_OUTCFG4_OUTCFG16_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70550   TIMER_OUTCFG4_OUTCFG16_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70551   TIMER_OUTCFG4_OUTCFG16_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70552   TIMER_OUTCFG4_OUTCFG16_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70553   TIMER_OUTCFG4_OUTCFG16_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70554   TIMER_OUTCFG4_OUTCFG16_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70555   TIMER_OUTCFG4_OUTCFG16_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70556   TIMER_OUTCFG4_OUTCFG16_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70557   TIMER_OUTCFG4_OUTCFG16_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70558   TIMER_OUTCFG4_OUTCFG16_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70559   TIMER_OUTCFG4_OUTCFG16_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70560   TIMER_OUTCFG4_OUTCFG16_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70561   TIMER_OUTCFG4_OUTCFG16_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70562   TIMER_OUTCFG4_OUTCFG16_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70563   TIMER_OUTCFG4_OUTCFG16_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70564   TIMER_OUTCFG4_OUTCFG16_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70565   TIMER_OUTCFG4_OUTCFG16_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70566   TIMER_OUTCFG4_OUTCFG16_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70567   TIMER_OUTCFG4_OUTCFG16_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70568   TIMER_OUTCFG4_OUTCFG16_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70569   TIMER_OUTCFG4_OUTCFG16_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70570   TIMER_OUTCFG4_OUTCFG16_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70571   TIMER_OUTCFG4_OUTCFG16_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70572 } TIMER_OUTCFG4_OUTCFG16_Enum;
70573 
70574 /* ========================================================  OUTCFG5  ======================================================== */
70575 /* ============================================  TIMER OUTCFG5 OUTCFG23 [24..29]  ============================================ */
70576 typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG23                                                    */
70577   TIMER_OUTCFG5_OUTCFG23_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70578   TIMER_OUTCFG5_OUTCFG23_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70579   TIMER_OUTCFG5_OUTCFG23_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70580   TIMER_OUTCFG5_OUTCFG23_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70581   TIMER_OUTCFG5_OUTCFG23_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70582   TIMER_OUTCFG5_OUTCFG23_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70583   TIMER_OUTCFG5_OUTCFG23_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70584   TIMER_OUTCFG5_OUTCFG23_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70585   TIMER_OUTCFG5_OUTCFG23_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70586   TIMER_OUTCFG5_OUTCFG23_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70587   TIMER_OUTCFG5_OUTCFG23_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70588   TIMER_OUTCFG5_OUTCFG23_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70589   TIMER_OUTCFG5_OUTCFG23_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70590   TIMER_OUTCFG5_OUTCFG23_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70591   TIMER_OUTCFG5_OUTCFG23_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70592   TIMER_OUTCFG5_OUTCFG23_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70593   TIMER_OUTCFG5_OUTCFG23_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70594   TIMER_OUTCFG5_OUTCFG23_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70595   TIMER_OUTCFG5_OUTCFG23_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70596   TIMER_OUTCFG5_OUTCFG23_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70597   TIMER_OUTCFG5_OUTCFG23_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70598   TIMER_OUTCFG5_OUTCFG23_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70599   TIMER_OUTCFG5_OUTCFG23_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70600   TIMER_OUTCFG5_OUTCFG23_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70601   TIMER_OUTCFG5_OUTCFG23_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70602   TIMER_OUTCFG5_OUTCFG23_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70603   TIMER_OUTCFG5_OUTCFG23_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70604   TIMER_OUTCFG5_OUTCFG23_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70605   TIMER_OUTCFG5_OUTCFG23_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70606   TIMER_OUTCFG5_OUTCFG23_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70607   TIMER_OUTCFG5_OUTCFG23_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70608   TIMER_OUTCFG5_OUTCFG23_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70609   TIMER_OUTCFG5_OUTCFG23_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70610   TIMER_OUTCFG5_OUTCFG23_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70611   TIMER_OUTCFG5_OUTCFG23_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70612   TIMER_OUTCFG5_OUTCFG23_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70613   TIMER_OUTCFG5_OUTCFG23_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70614   TIMER_OUTCFG5_OUTCFG23_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70615   TIMER_OUTCFG5_OUTCFG23_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70616   TIMER_OUTCFG5_OUTCFG23_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70617   TIMER_OUTCFG5_OUTCFG23_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70618 } TIMER_OUTCFG5_OUTCFG23_Enum;
70619 
70620 /* ============================================  TIMER OUTCFG5 OUTCFG22 [16..21]  ============================================ */
70621 typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG22                                                    */
70622   TIMER_OUTCFG5_OUTCFG22_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70623   TIMER_OUTCFG5_OUTCFG22_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70624   TIMER_OUTCFG5_OUTCFG22_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70625   TIMER_OUTCFG5_OUTCFG22_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70626   TIMER_OUTCFG5_OUTCFG22_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70627   TIMER_OUTCFG5_OUTCFG22_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70628   TIMER_OUTCFG5_OUTCFG22_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70629   TIMER_OUTCFG5_OUTCFG22_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70630   TIMER_OUTCFG5_OUTCFG22_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70631   TIMER_OUTCFG5_OUTCFG22_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70632   TIMER_OUTCFG5_OUTCFG22_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70633   TIMER_OUTCFG5_OUTCFG22_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70634   TIMER_OUTCFG5_OUTCFG22_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70635   TIMER_OUTCFG5_OUTCFG22_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70636   TIMER_OUTCFG5_OUTCFG22_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70637   TIMER_OUTCFG5_OUTCFG22_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70638   TIMER_OUTCFG5_OUTCFG22_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70639   TIMER_OUTCFG5_OUTCFG22_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70640   TIMER_OUTCFG5_OUTCFG22_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70641   TIMER_OUTCFG5_OUTCFG22_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70642   TIMER_OUTCFG5_OUTCFG22_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70643   TIMER_OUTCFG5_OUTCFG22_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70644   TIMER_OUTCFG5_OUTCFG22_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70645   TIMER_OUTCFG5_OUTCFG22_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70646   TIMER_OUTCFG5_OUTCFG22_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70647   TIMER_OUTCFG5_OUTCFG22_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70648   TIMER_OUTCFG5_OUTCFG22_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70649   TIMER_OUTCFG5_OUTCFG22_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70650   TIMER_OUTCFG5_OUTCFG22_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70651   TIMER_OUTCFG5_OUTCFG22_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70652   TIMER_OUTCFG5_OUTCFG22_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70653   TIMER_OUTCFG5_OUTCFG22_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70654   TIMER_OUTCFG5_OUTCFG22_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70655   TIMER_OUTCFG5_OUTCFG22_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70656   TIMER_OUTCFG5_OUTCFG22_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70657   TIMER_OUTCFG5_OUTCFG22_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70658   TIMER_OUTCFG5_OUTCFG22_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70659   TIMER_OUTCFG5_OUTCFG22_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70660   TIMER_OUTCFG5_OUTCFG22_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70661   TIMER_OUTCFG5_OUTCFG22_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70662   TIMER_OUTCFG5_OUTCFG22_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70663 } TIMER_OUTCFG5_OUTCFG22_Enum;
70664 
70665 /* ============================================  TIMER OUTCFG5 OUTCFG21 [8..13]  ============================================= */
70666 typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG21                                                    */
70667   TIMER_OUTCFG5_OUTCFG21_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70668   TIMER_OUTCFG5_OUTCFG21_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70669   TIMER_OUTCFG5_OUTCFG21_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70670   TIMER_OUTCFG5_OUTCFG21_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70671   TIMER_OUTCFG5_OUTCFG21_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70672   TIMER_OUTCFG5_OUTCFG21_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70673   TIMER_OUTCFG5_OUTCFG21_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70674   TIMER_OUTCFG5_OUTCFG21_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70675   TIMER_OUTCFG5_OUTCFG21_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70676   TIMER_OUTCFG5_OUTCFG21_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70677   TIMER_OUTCFG5_OUTCFG21_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70678   TIMER_OUTCFG5_OUTCFG21_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70679   TIMER_OUTCFG5_OUTCFG21_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70680   TIMER_OUTCFG5_OUTCFG21_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70681   TIMER_OUTCFG5_OUTCFG21_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70682   TIMER_OUTCFG5_OUTCFG21_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70683   TIMER_OUTCFG5_OUTCFG21_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70684   TIMER_OUTCFG5_OUTCFG21_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70685   TIMER_OUTCFG5_OUTCFG21_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70686   TIMER_OUTCFG5_OUTCFG21_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70687   TIMER_OUTCFG5_OUTCFG21_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70688   TIMER_OUTCFG5_OUTCFG21_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70689   TIMER_OUTCFG5_OUTCFG21_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70690   TIMER_OUTCFG5_OUTCFG21_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70691   TIMER_OUTCFG5_OUTCFG21_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70692   TIMER_OUTCFG5_OUTCFG21_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70693   TIMER_OUTCFG5_OUTCFG21_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70694   TIMER_OUTCFG5_OUTCFG21_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70695   TIMER_OUTCFG5_OUTCFG21_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70696   TIMER_OUTCFG5_OUTCFG21_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70697   TIMER_OUTCFG5_OUTCFG21_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70698   TIMER_OUTCFG5_OUTCFG21_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70699   TIMER_OUTCFG5_OUTCFG21_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70700   TIMER_OUTCFG5_OUTCFG21_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70701   TIMER_OUTCFG5_OUTCFG21_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70702   TIMER_OUTCFG5_OUTCFG21_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70703   TIMER_OUTCFG5_OUTCFG21_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70704   TIMER_OUTCFG5_OUTCFG21_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70705   TIMER_OUTCFG5_OUTCFG21_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70706   TIMER_OUTCFG5_OUTCFG21_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70707   TIMER_OUTCFG5_OUTCFG21_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70708 } TIMER_OUTCFG5_OUTCFG21_Enum;
70709 
70710 /* =============================================  TIMER OUTCFG5 OUTCFG20 [0..5]  ============================================= */
70711 typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG20                                                    */
70712   TIMER_OUTCFG5_OUTCFG20_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70713   TIMER_OUTCFG5_OUTCFG20_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70714   TIMER_OUTCFG5_OUTCFG20_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70715   TIMER_OUTCFG5_OUTCFG20_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70716   TIMER_OUTCFG5_OUTCFG20_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70717   TIMER_OUTCFG5_OUTCFG20_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70718   TIMER_OUTCFG5_OUTCFG20_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70719   TIMER_OUTCFG5_OUTCFG20_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70720   TIMER_OUTCFG5_OUTCFG20_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70721   TIMER_OUTCFG5_OUTCFG20_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70722   TIMER_OUTCFG5_OUTCFG20_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70723   TIMER_OUTCFG5_OUTCFG20_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70724   TIMER_OUTCFG5_OUTCFG20_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70725   TIMER_OUTCFG5_OUTCFG20_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70726   TIMER_OUTCFG5_OUTCFG20_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70727   TIMER_OUTCFG5_OUTCFG20_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70728   TIMER_OUTCFG5_OUTCFG20_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70729   TIMER_OUTCFG5_OUTCFG20_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70730   TIMER_OUTCFG5_OUTCFG20_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70731   TIMER_OUTCFG5_OUTCFG20_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70732   TIMER_OUTCFG5_OUTCFG20_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70733   TIMER_OUTCFG5_OUTCFG20_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70734   TIMER_OUTCFG5_OUTCFG20_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70735   TIMER_OUTCFG5_OUTCFG20_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70736   TIMER_OUTCFG5_OUTCFG20_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70737   TIMER_OUTCFG5_OUTCFG20_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70738   TIMER_OUTCFG5_OUTCFG20_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70739   TIMER_OUTCFG5_OUTCFG20_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70740   TIMER_OUTCFG5_OUTCFG20_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70741   TIMER_OUTCFG5_OUTCFG20_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70742   TIMER_OUTCFG5_OUTCFG20_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70743   TIMER_OUTCFG5_OUTCFG20_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70744   TIMER_OUTCFG5_OUTCFG20_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70745   TIMER_OUTCFG5_OUTCFG20_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70746   TIMER_OUTCFG5_OUTCFG20_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70747   TIMER_OUTCFG5_OUTCFG20_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70748   TIMER_OUTCFG5_OUTCFG20_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70749   TIMER_OUTCFG5_OUTCFG20_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70750   TIMER_OUTCFG5_OUTCFG20_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70751   TIMER_OUTCFG5_OUTCFG20_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70752   TIMER_OUTCFG5_OUTCFG20_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70753 } TIMER_OUTCFG5_OUTCFG20_Enum;
70754 
70755 /* ========================================================  OUTCFG6  ======================================================== */
70756 /* ============================================  TIMER OUTCFG6 OUTCFG27 [24..29]  ============================================ */
70757 typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG27                                                    */
70758   TIMER_OUTCFG6_OUTCFG27_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70759   TIMER_OUTCFG6_OUTCFG27_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70760   TIMER_OUTCFG6_OUTCFG27_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70761   TIMER_OUTCFG6_OUTCFG27_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70762   TIMER_OUTCFG6_OUTCFG27_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70763   TIMER_OUTCFG6_OUTCFG27_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70764   TIMER_OUTCFG6_OUTCFG27_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70765   TIMER_OUTCFG6_OUTCFG27_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70766   TIMER_OUTCFG6_OUTCFG27_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70767   TIMER_OUTCFG6_OUTCFG27_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70768   TIMER_OUTCFG6_OUTCFG27_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70769   TIMER_OUTCFG6_OUTCFG27_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70770   TIMER_OUTCFG6_OUTCFG27_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70771   TIMER_OUTCFG6_OUTCFG27_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70772   TIMER_OUTCFG6_OUTCFG27_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70773   TIMER_OUTCFG6_OUTCFG27_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70774   TIMER_OUTCFG6_OUTCFG27_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70775   TIMER_OUTCFG6_OUTCFG27_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70776   TIMER_OUTCFG6_OUTCFG27_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70777   TIMER_OUTCFG6_OUTCFG27_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70778   TIMER_OUTCFG6_OUTCFG27_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70779   TIMER_OUTCFG6_OUTCFG27_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70780   TIMER_OUTCFG6_OUTCFG27_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70781   TIMER_OUTCFG6_OUTCFG27_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70782   TIMER_OUTCFG6_OUTCFG27_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70783   TIMER_OUTCFG6_OUTCFG27_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70784   TIMER_OUTCFG6_OUTCFG27_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70785   TIMER_OUTCFG6_OUTCFG27_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70786   TIMER_OUTCFG6_OUTCFG27_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70787   TIMER_OUTCFG6_OUTCFG27_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70788   TIMER_OUTCFG6_OUTCFG27_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70789   TIMER_OUTCFG6_OUTCFG27_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70790   TIMER_OUTCFG6_OUTCFG27_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70791   TIMER_OUTCFG6_OUTCFG27_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70792   TIMER_OUTCFG6_OUTCFG27_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70793   TIMER_OUTCFG6_OUTCFG27_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70794   TIMER_OUTCFG6_OUTCFG27_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70795   TIMER_OUTCFG6_OUTCFG27_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70796   TIMER_OUTCFG6_OUTCFG27_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70797   TIMER_OUTCFG6_OUTCFG27_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70798   TIMER_OUTCFG6_OUTCFG27_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70799 } TIMER_OUTCFG6_OUTCFG27_Enum;
70800 
70801 /* ============================================  TIMER OUTCFG6 OUTCFG26 [16..21]  ============================================ */
70802 typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG26                                                    */
70803   TIMER_OUTCFG6_OUTCFG26_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70804   TIMER_OUTCFG6_OUTCFG26_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70805   TIMER_OUTCFG6_OUTCFG26_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70806   TIMER_OUTCFG6_OUTCFG26_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70807   TIMER_OUTCFG6_OUTCFG26_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70808   TIMER_OUTCFG6_OUTCFG26_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70809   TIMER_OUTCFG6_OUTCFG26_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70810   TIMER_OUTCFG6_OUTCFG26_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70811   TIMER_OUTCFG6_OUTCFG26_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70812   TIMER_OUTCFG6_OUTCFG26_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70813   TIMER_OUTCFG6_OUTCFG26_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70814   TIMER_OUTCFG6_OUTCFG26_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70815   TIMER_OUTCFG6_OUTCFG26_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70816   TIMER_OUTCFG6_OUTCFG26_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70817   TIMER_OUTCFG6_OUTCFG26_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70818   TIMER_OUTCFG6_OUTCFG26_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70819   TIMER_OUTCFG6_OUTCFG26_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70820   TIMER_OUTCFG6_OUTCFG26_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70821   TIMER_OUTCFG6_OUTCFG26_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70822   TIMER_OUTCFG6_OUTCFG26_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70823   TIMER_OUTCFG6_OUTCFG26_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70824   TIMER_OUTCFG6_OUTCFG26_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70825   TIMER_OUTCFG6_OUTCFG26_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70826   TIMER_OUTCFG6_OUTCFG26_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70827   TIMER_OUTCFG6_OUTCFG26_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70828   TIMER_OUTCFG6_OUTCFG26_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70829   TIMER_OUTCFG6_OUTCFG26_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70830   TIMER_OUTCFG6_OUTCFG26_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70831   TIMER_OUTCFG6_OUTCFG26_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70832   TIMER_OUTCFG6_OUTCFG26_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70833   TIMER_OUTCFG6_OUTCFG26_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70834   TIMER_OUTCFG6_OUTCFG26_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70835   TIMER_OUTCFG6_OUTCFG26_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70836   TIMER_OUTCFG6_OUTCFG26_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70837   TIMER_OUTCFG6_OUTCFG26_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70838   TIMER_OUTCFG6_OUTCFG26_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70839   TIMER_OUTCFG6_OUTCFG26_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70840   TIMER_OUTCFG6_OUTCFG26_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70841   TIMER_OUTCFG6_OUTCFG26_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70842   TIMER_OUTCFG6_OUTCFG26_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70843   TIMER_OUTCFG6_OUTCFG26_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70844 } TIMER_OUTCFG6_OUTCFG26_Enum;
70845 
70846 /* ============================================  TIMER OUTCFG6 OUTCFG25 [8..13]  ============================================= */
70847 typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG25                                                    */
70848   TIMER_OUTCFG6_OUTCFG25_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70849   TIMER_OUTCFG6_OUTCFG25_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70850   TIMER_OUTCFG6_OUTCFG25_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70851   TIMER_OUTCFG6_OUTCFG25_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70852   TIMER_OUTCFG6_OUTCFG25_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70853   TIMER_OUTCFG6_OUTCFG25_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70854   TIMER_OUTCFG6_OUTCFG25_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70855   TIMER_OUTCFG6_OUTCFG25_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70856   TIMER_OUTCFG6_OUTCFG25_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70857   TIMER_OUTCFG6_OUTCFG25_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70858   TIMER_OUTCFG6_OUTCFG25_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70859   TIMER_OUTCFG6_OUTCFG25_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70860   TIMER_OUTCFG6_OUTCFG25_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70861   TIMER_OUTCFG6_OUTCFG25_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70862   TIMER_OUTCFG6_OUTCFG25_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70863   TIMER_OUTCFG6_OUTCFG25_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70864   TIMER_OUTCFG6_OUTCFG25_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70865   TIMER_OUTCFG6_OUTCFG25_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70866   TIMER_OUTCFG6_OUTCFG25_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70867   TIMER_OUTCFG6_OUTCFG25_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70868   TIMER_OUTCFG6_OUTCFG25_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70869   TIMER_OUTCFG6_OUTCFG25_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70870   TIMER_OUTCFG6_OUTCFG25_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70871   TIMER_OUTCFG6_OUTCFG25_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70872   TIMER_OUTCFG6_OUTCFG25_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70873   TIMER_OUTCFG6_OUTCFG25_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70874   TIMER_OUTCFG6_OUTCFG25_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70875   TIMER_OUTCFG6_OUTCFG25_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70876   TIMER_OUTCFG6_OUTCFG25_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70877   TIMER_OUTCFG6_OUTCFG25_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70878   TIMER_OUTCFG6_OUTCFG25_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70879   TIMER_OUTCFG6_OUTCFG25_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70880   TIMER_OUTCFG6_OUTCFG25_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70881   TIMER_OUTCFG6_OUTCFG25_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70882   TIMER_OUTCFG6_OUTCFG25_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70883   TIMER_OUTCFG6_OUTCFG25_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70884   TIMER_OUTCFG6_OUTCFG25_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70885   TIMER_OUTCFG6_OUTCFG25_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70886   TIMER_OUTCFG6_OUTCFG25_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70887   TIMER_OUTCFG6_OUTCFG25_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70888   TIMER_OUTCFG6_OUTCFG25_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70889 } TIMER_OUTCFG6_OUTCFG25_Enum;
70890 
70891 /* =============================================  TIMER OUTCFG6 OUTCFG24 [0..5]  ============================================= */
70892 typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG24                                                    */
70893   TIMER_OUTCFG6_OUTCFG24_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70894   TIMER_OUTCFG6_OUTCFG24_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70895   TIMER_OUTCFG6_OUTCFG24_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70896   TIMER_OUTCFG6_OUTCFG24_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70897   TIMER_OUTCFG6_OUTCFG24_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70898   TIMER_OUTCFG6_OUTCFG24_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70899   TIMER_OUTCFG6_OUTCFG24_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70900   TIMER_OUTCFG6_OUTCFG24_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70901   TIMER_OUTCFG6_OUTCFG24_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70902   TIMER_OUTCFG6_OUTCFG24_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70903   TIMER_OUTCFG6_OUTCFG24_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70904   TIMER_OUTCFG6_OUTCFG24_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70905   TIMER_OUTCFG6_OUTCFG24_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70906   TIMER_OUTCFG6_OUTCFG24_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70907   TIMER_OUTCFG6_OUTCFG24_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70908   TIMER_OUTCFG6_OUTCFG24_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70909   TIMER_OUTCFG6_OUTCFG24_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70910   TIMER_OUTCFG6_OUTCFG24_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70911   TIMER_OUTCFG6_OUTCFG24_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70912   TIMER_OUTCFG6_OUTCFG24_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70913   TIMER_OUTCFG6_OUTCFG24_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70914   TIMER_OUTCFG6_OUTCFG24_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70915   TIMER_OUTCFG6_OUTCFG24_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70916   TIMER_OUTCFG6_OUTCFG24_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70917   TIMER_OUTCFG6_OUTCFG24_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70918   TIMER_OUTCFG6_OUTCFG24_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70919   TIMER_OUTCFG6_OUTCFG24_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70920   TIMER_OUTCFG6_OUTCFG24_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70921   TIMER_OUTCFG6_OUTCFG24_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70922   TIMER_OUTCFG6_OUTCFG24_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70923   TIMER_OUTCFG6_OUTCFG24_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70924   TIMER_OUTCFG6_OUTCFG24_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70925   TIMER_OUTCFG6_OUTCFG24_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70926   TIMER_OUTCFG6_OUTCFG24_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70927   TIMER_OUTCFG6_OUTCFG24_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70928   TIMER_OUTCFG6_OUTCFG24_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70929   TIMER_OUTCFG6_OUTCFG24_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70930   TIMER_OUTCFG6_OUTCFG24_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70931   TIMER_OUTCFG6_OUTCFG24_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70932   TIMER_OUTCFG6_OUTCFG24_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70933   TIMER_OUTCFG6_OUTCFG24_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70934 } TIMER_OUTCFG6_OUTCFG24_Enum;
70935 
70936 /* ========================================================  OUTCFG7  ======================================================== */
70937 /* ============================================  TIMER OUTCFG7 OUTCFG31 [24..29]  ============================================ */
70938 typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG31                                                    */
70939   TIMER_OUTCFG7_OUTCFG31_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70940   TIMER_OUTCFG7_OUTCFG31_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70941   TIMER_OUTCFG7_OUTCFG31_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70942   TIMER_OUTCFG7_OUTCFG31_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70943   TIMER_OUTCFG7_OUTCFG31_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70944   TIMER_OUTCFG7_OUTCFG31_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70945   TIMER_OUTCFG7_OUTCFG31_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70946   TIMER_OUTCFG7_OUTCFG31_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70947   TIMER_OUTCFG7_OUTCFG31_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70948   TIMER_OUTCFG7_OUTCFG31_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70949   TIMER_OUTCFG7_OUTCFG31_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70950   TIMER_OUTCFG7_OUTCFG31_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70951   TIMER_OUTCFG7_OUTCFG31_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70952   TIMER_OUTCFG7_OUTCFG31_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70953   TIMER_OUTCFG7_OUTCFG31_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70954   TIMER_OUTCFG7_OUTCFG31_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
70955   TIMER_OUTCFG7_OUTCFG31_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
70956   TIMER_OUTCFG7_OUTCFG31_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
70957   TIMER_OUTCFG7_OUTCFG31_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
70958   TIMER_OUTCFG7_OUTCFG31_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
70959   TIMER_OUTCFG7_OUTCFG31_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
70960   TIMER_OUTCFG7_OUTCFG31_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
70961   TIMER_OUTCFG7_OUTCFG31_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
70962   TIMER_OUTCFG7_OUTCFG31_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
70963   TIMER_OUTCFG7_OUTCFG31_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
70964   TIMER_OUTCFG7_OUTCFG31_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
70965   TIMER_OUTCFG7_OUTCFG31_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
70966   TIMER_OUTCFG7_OUTCFG31_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
70967   TIMER_OUTCFG7_OUTCFG31_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
70968   TIMER_OUTCFG7_OUTCFG31_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
70969   TIMER_OUTCFG7_OUTCFG31_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
70970   TIMER_OUTCFG7_OUTCFG31_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
70971   TIMER_OUTCFG7_OUTCFG31_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
70972   TIMER_OUTCFG7_OUTCFG31_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
70973   TIMER_OUTCFG7_OUTCFG31_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
70974   TIMER_OUTCFG7_OUTCFG31_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
70975   TIMER_OUTCFG7_OUTCFG31_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
70976   TIMER_OUTCFG7_OUTCFG31_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
70977   TIMER_OUTCFG7_OUTCFG31_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
70978   TIMER_OUTCFG7_OUTCFG31_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
70979   TIMER_OUTCFG7_OUTCFG31_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
70980 } TIMER_OUTCFG7_OUTCFG31_Enum;
70981 
70982 /* ============================================  TIMER OUTCFG7 OUTCFG30 [16..21]  ============================================ */
70983 typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG30                                                    */
70984   TIMER_OUTCFG7_OUTCFG30_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
70985   TIMER_OUTCFG7_OUTCFG30_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
70986   TIMER_OUTCFG7_OUTCFG30_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
70987   TIMER_OUTCFG7_OUTCFG30_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
70988   TIMER_OUTCFG7_OUTCFG30_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
70989   TIMER_OUTCFG7_OUTCFG30_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
70990   TIMER_OUTCFG7_OUTCFG30_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
70991   TIMER_OUTCFG7_OUTCFG30_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
70992   TIMER_OUTCFG7_OUTCFG30_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
70993   TIMER_OUTCFG7_OUTCFG30_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
70994   TIMER_OUTCFG7_OUTCFG30_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
70995   TIMER_OUTCFG7_OUTCFG30_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
70996   TIMER_OUTCFG7_OUTCFG30_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
70997   TIMER_OUTCFG7_OUTCFG30_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
70998   TIMER_OUTCFG7_OUTCFG30_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
70999   TIMER_OUTCFG7_OUTCFG30_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71000   TIMER_OUTCFG7_OUTCFG30_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71001   TIMER_OUTCFG7_OUTCFG30_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71002   TIMER_OUTCFG7_OUTCFG30_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71003   TIMER_OUTCFG7_OUTCFG30_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71004   TIMER_OUTCFG7_OUTCFG30_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71005   TIMER_OUTCFG7_OUTCFG30_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71006   TIMER_OUTCFG7_OUTCFG30_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71007   TIMER_OUTCFG7_OUTCFG30_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71008   TIMER_OUTCFG7_OUTCFG30_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71009   TIMER_OUTCFG7_OUTCFG30_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71010   TIMER_OUTCFG7_OUTCFG30_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71011   TIMER_OUTCFG7_OUTCFG30_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71012   TIMER_OUTCFG7_OUTCFG30_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71013   TIMER_OUTCFG7_OUTCFG30_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71014   TIMER_OUTCFG7_OUTCFG30_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71015   TIMER_OUTCFG7_OUTCFG30_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71016   TIMER_OUTCFG7_OUTCFG30_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71017   TIMER_OUTCFG7_OUTCFG30_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71018   TIMER_OUTCFG7_OUTCFG30_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71019   TIMER_OUTCFG7_OUTCFG30_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71020   TIMER_OUTCFG7_OUTCFG30_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71021   TIMER_OUTCFG7_OUTCFG30_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71022   TIMER_OUTCFG7_OUTCFG30_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71023   TIMER_OUTCFG7_OUTCFG30_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71024   TIMER_OUTCFG7_OUTCFG30_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71025 } TIMER_OUTCFG7_OUTCFG30_Enum;
71026 
71027 /* ============================================  TIMER OUTCFG7 OUTCFG29 [8..13]  ============================================= */
71028 typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG29                                                    */
71029   TIMER_OUTCFG7_OUTCFG29_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71030   TIMER_OUTCFG7_OUTCFG29_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71031   TIMER_OUTCFG7_OUTCFG29_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71032   TIMER_OUTCFG7_OUTCFG29_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71033   TIMER_OUTCFG7_OUTCFG29_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71034   TIMER_OUTCFG7_OUTCFG29_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71035   TIMER_OUTCFG7_OUTCFG29_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71036   TIMER_OUTCFG7_OUTCFG29_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71037   TIMER_OUTCFG7_OUTCFG29_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71038   TIMER_OUTCFG7_OUTCFG29_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71039   TIMER_OUTCFG7_OUTCFG29_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71040   TIMER_OUTCFG7_OUTCFG29_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71041   TIMER_OUTCFG7_OUTCFG29_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71042   TIMER_OUTCFG7_OUTCFG29_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71043   TIMER_OUTCFG7_OUTCFG29_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71044   TIMER_OUTCFG7_OUTCFG29_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71045   TIMER_OUTCFG7_OUTCFG29_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71046   TIMER_OUTCFG7_OUTCFG29_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71047   TIMER_OUTCFG7_OUTCFG29_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71048   TIMER_OUTCFG7_OUTCFG29_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71049   TIMER_OUTCFG7_OUTCFG29_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71050   TIMER_OUTCFG7_OUTCFG29_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71051   TIMER_OUTCFG7_OUTCFG29_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71052   TIMER_OUTCFG7_OUTCFG29_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71053   TIMER_OUTCFG7_OUTCFG29_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71054   TIMER_OUTCFG7_OUTCFG29_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71055   TIMER_OUTCFG7_OUTCFG29_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71056   TIMER_OUTCFG7_OUTCFG29_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71057   TIMER_OUTCFG7_OUTCFG29_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71058   TIMER_OUTCFG7_OUTCFG29_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71059   TIMER_OUTCFG7_OUTCFG29_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71060   TIMER_OUTCFG7_OUTCFG29_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71061   TIMER_OUTCFG7_OUTCFG29_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71062   TIMER_OUTCFG7_OUTCFG29_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71063   TIMER_OUTCFG7_OUTCFG29_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71064   TIMER_OUTCFG7_OUTCFG29_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71065   TIMER_OUTCFG7_OUTCFG29_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71066   TIMER_OUTCFG7_OUTCFG29_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71067   TIMER_OUTCFG7_OUTCFG29_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71068   TIMER_OUTCFG7_OUTCFG29_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71069   TIMER_OUTCFG7_OUTCFG29_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71070 } TIMER_OUTCFG7_OUTCFG29_Enum;
71071 
71072 /* =============================================  TIMER OUTCFG7 OUTCFG28 [0..5]  ============================================= */
71073 typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG28                                                    */
71074   TIMER_OUTCFG7_OUTCFG28_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71075   TIMER_OUTCFG7_OUTCFG28_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71076   TIMER_OUTCFG7_OUTCFG28_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71077   TIMER_OUTCFG7_OUTCFG28_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71078   TIMER_OUTCFG7_OUTCFG28_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71079   TIMER_OUTCFG7_OUTCFG28_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71080   TIMER_OUTCFG7_OUTCFG28_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71081   TIMER_OUTCFG7_OUTCFG28_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71082   TIMER_OUTCFG7_OUTCFG28_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71083   TIMER_OUTCFG7_OUTCFG28_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71084   TIMER_OUTCFG7_OUTCFG28_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71085   TIMER_OUTCFG7_OUTCFG28_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71086   TIMER_OUTCFG7_OUTCFG28_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71087   TIMER_OUTCFG7_OUTCFG28_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71088   TIMER_OUTCFG7_OUTCFG28_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71089   TIMER_OUTCFG7_OUTCFG28_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71090   TIMER_OUTCFG7_OUTCFG28_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71091   TIMER_OUTCFG7_OUTCFG28_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71092   TIMER_OUTCFG7_OUTCFG28_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71093   TIMER_OUTCFG7_OUTCFG28_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71094   TIMER_OUTCFG7_OUTCFG28_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71095   TIMER_OUTCFG7_OUTCFG28_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71096   TIMER_OUTCFG7_OUTCFG28_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71097   TIMER_OUTCFG7_OUTCFG28_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71098   TIMER_OUTCFG7_OUTCFG28_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71099   TIMER_OUTCFG7_OUTCFG28_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71100   TIMER_OUTCFG7_OUTCFG28_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71101   TIMER_OUTCFG7_OUTCFG28_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71102   TIMER_OUTCFG7_OUTCFG28_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71103   TIMER_OUTCFG7_OUTCFG28_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71104   TIMER_OUTCFG7_OUTCFG28_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71105   TIMER_OUTCFG7_OUTCFG28_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71106   TIMER_OUTCFG7_OUTCFG28_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71107   TIMER_OUTCFG7_OUTCFG28_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71108   TIMER_OUTCFG7_OUTCFG28_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71109   TIMER_OUTCFG7_OUTCFG28_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71110   TIMER_OUTCFG7_OUTCFG28_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71111   TIMER_OUTCFG7_OUTCFG28_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71112   TIMER_OUTCFG7_OUTCFG28_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71113   TIMER_OUTCFG7_OUTCFG28_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71114   TIMER_OUTCFG7_OUTCFG28_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71115 } TIMER_OUTCFG7_OUTCFG28_Enum;
71116 
71117 /* ========================================================  OUTCFG8  ======================================================== */
71118 /* ============================================  TIMER OUTCFG8 OUTCFG35 [24..29]  ============================================ */
71119 typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG35                                                    */
71120   TIMER_OUTCFG8_OUTCFG35_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71121   TIMER_OUTCFG8_OUTCFG35_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71122   TIMER_OUTCFG8_OUTCFG35_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71123   TIMER_OUTCFG8_OUTCFG35_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71124   TIMER_OUTCFG8_OUTCFG35_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71125   TIMER_OUTCFG8_OUTCFG35_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71126   TIMER_OUTCFG8_OUTCFG35_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71127   TIMER_OUTCFG8_OUTCFG35_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71128   TIMER_OUTCFG8_OUTCFG35_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71129   TIMER_OUTCFG8_OUTCFG35_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71130   TIMER_OUTCFG8_OUTCFG35_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71131   TIMER_OUTCFG8_OUTCFG35_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71132   TIMER_OUTCFG8_OUTCFG35_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71133   TIMER_OUTCFG8_OUTCFG35_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71134   TIMER_OUTCFG8_OUTCFG35_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71135   TIMER_OUTCFG8_OUTCFG35_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71136   TIMER_OUTCFG8_OUTCFG35_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71137   TIMER_OUTCFG8_OUTCFG35_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71138   TIMER_OUTCFG8_OUTCFG35_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71139   TIMER_OUTCFG8_OUTCFG35_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71140   TIMER_OUTCFG8_OUTCFG35_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71141   TIMER_OUTCFG8_OUTCFG35_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71142   TIMER_OUTCFG8_OUTCFG35_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71143   TIMER_OUTCFG8_OUTCFG35_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71144   TIMER_OUTCFG8_OUTCFG35_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71145   TIMER_OUTCFG8_OUTCFG35_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71146   TIMER_OUTCFG8_OUTCFG35_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71147   TIMER_OUTCFG8_OUTCFG35_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71148   TIMER_OUTCFG8_OUTCFG35_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71149   TIMER_OUTCFG8_OUTCFG35_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71150   TIMER_OUTCFG8_OUTCFG35_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71151   TIMER_OUTCFG8_OUTCFG35_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71152   TIMER_OUTCFG8_OUTCFG35_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71153   TIMER_OUTCFG8_OUTCFG35_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71154   TIMER_OUTCFG8_OUTCFG35_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71155   TIMER_OUTCFG8_OUTCFG35_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71156   TIMER_OUTCFG8_OUTCFG35_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71157   TIMER_OUTCFG8_OUTCFG35_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71158   TIMER_OUTCFG8_OUTCFG35_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71159   TIMER_OUTCFG8_OUTCFG35_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71160   TIMER_OUTCFG8_OUTCFG35_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71161 } TIMER_OUTCFG8_OUTCFG35_Enum;
71162 
71163 /* ============================================  TIMER OUTCFG8 OUTCFG34 [16..21]  ============================================ */
71164 typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG34                                                    */
71165   TIMER_OUTCFG8_OUTCFG34_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71166   TIMER_OUTCFG8_OUTCFG34_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71167   TIMER_OUTCFG8_OUTCFG34_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71168   TIMER_OUTCFG8_OUTCFG34_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71169   TIMER_OUTCFG8_OUTCFG34_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71170   TIMER_OUTCFG8_OUTCFG34_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71171   TIMER_OUTCFG8_OUTCFG34_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71172   TIMER_OUTCFG8_OUTCFG34_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71173   TIMER_OUTCFG8_OUTCFG34_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71174   TIMER_OUTCFG8_OUTCFG34_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71175   TIMER_OUTCFG8_OUTCFG34_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71176   TIMER_OUTCFG8_OUTCFG34_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71177   TIMER_OUTCFG8_OUTCFG34_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71178   TIMER_OUTCFG8_OUTCFG34_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71179   TIMER_OUTCFG8_OUTCFG34_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71180   TIMER_OUTCFG8_OUTCFG34_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71181   TIMER_OUTCFG8_OUTCFG34_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71182   TIMER_OUTCFG8_OUTCFG34_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71183   TIMER_OUTCFG8_OUTCFG34_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71184   TIMER_OUTCFG8_OUTCFG34_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71185   TIMER_OUTCFG8_OUTCFG34_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71186   TIMER_OUTCFG8_OUTCFG34_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71187   TIMER_OUTCFG8_OUTCFG34_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71188   TIMER_OUTCFG8_OUTCFG34_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71189   TIMER_OUTCFG8_OUTCFG34_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71190   TIMER_OUTCFG8_OUTCFG34_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71191   TIMER_OUTCFG8_OUTCFG34_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71192   TIMER_OUTCFG8_OUTCFG34_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71193   TIMER_OUTCFG8_OUTCFG34_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71194   TIMER_OUTCFG8_OUTCFG34_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71195   TIMER_OUTCFG8_OUTCFG34_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71196   TIMER_OUTCFG8_OUTCFG34_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71197   TIMER_OUTCFG8_OUTCFG34_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71198   TIMER_OUTCFG8_OUTCFG34_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71199   TIMER_OUTCFG8_OUTCFG34_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71200   TIMER_OUTCFG8_OUTCFG34_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71201   TIMER_OUTCFG8_OUTCFG34_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71202   TIMER_OUTCFG8_OUTCFG34_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71203   TIMER_OUTCFG8_OUTCFG34_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71204   TIMER_OUTCFG8_OUTCFG34_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71205   TIMER_OUTCFG8_OUTCFG34_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71206 } TIMER_OUTCFG8_OUTCFG34_Enum;
71207 
71208 /* ============================================  TIMER OUTCFG8 OUTCFG33 [8..13]  ============================================= */
71209 typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG33                                                    */
71210   TIMER_OUTCFG8_OUTCFG33_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71211   TIMER_OUTCFG8_OUTCFG33_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71212   TIMER_OUTCFG8_OUTCFG33_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71213   TIMER_OUTCFG8_OUTCFG33_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71214   TIMER_OUTCFG8_OUTCFG33_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71215   TIMER_OUTCFG8_OUTCFG33_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71216   TIMER_OUTCFG8_OUTCFG33_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71217   TIMER_OUTCFG8_OUTCFG33_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71218   TIMER_OUTCFG8_OUTCFG33_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71219   TIMER_OUTCFG8_OUTCFG33_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71220   TIMER_OUTCFG8_OUTCFG33_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71221   TIMER_OUTCFG8_OUTCFG33_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71222   TIMER_OUTCFG8_OUTCFG33_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71223   TIMER_OUTCFG8_OUTCFG33_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71224   TIMER_OUTCFG8_OUTCFG33_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71225   TIMER_OUTCFG8_OUTCFG33_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71226   TIMER_OUTCFG8_OUTCFG33_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71227   TIMER_OUTCFG8_OUTCFG33_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71228   TIMER_OUTCFG8_OUTCFG33_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71229   TIMER_OUTCFG8_OUTCFG33_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71230   TIMER_OUTCFG8_OUTCFG33_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71231   TIMER_OUTCFG8_OUTCFG33_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71232   TIMER_OUTCFG8_OUTCFG33_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71233   TIMER_OUTCFG8_OUTCFG33_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71234   TIMER_OUTCFG8_OUTCFG33_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71235   TIMER_OUTCFG8_OUTCFG33_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71236   TIMER_OUTCFG8_OUTCFG33_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71237   TIMER_OUTCFG8_OUTCFG33_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71238   TIMER_OUTCFG8_OUTCFG33_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71239   TIMER_OUTCFG8_OUTCFG33_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71240   TIMER_OUTCFG8_OUTCFG33_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71241   TIMER_OUTCFG8_OUTCFG33_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71242   TIMER_OUTCFG8_OUTCFG33_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71243   TIMER_OUTCFG8_OUTCFG33_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71244   TIMER_OUTCFG8_OUTCFG33_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71245   TIMER_OUTCFG8_OUTCFG33_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71246   TIMER_OUTCFG8_OUTCFG33_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71247   TIMER_OUTCFG8_OUTCFG33_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71248   TIMER_OUTCFG8_OUTCFG33_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71249   TIMER_OUTCFG8_OUTCFG33_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71250   TIMER_OUTCFG8_OUTCFG33_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71251 } TIMER_OUTCFG8_OUTCFG33_Enum;
71252 
71253 /* =============================================  TIMER OUTCFG8 OUTCFG32 [0..5]  ============================================= */
71254 typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG32                                                    */
71255   TIMER_OUTCFG8_OUTCFG32_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71256   TIMER_OUTCFG8_OUTCFG32_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71257   TIMER_OUTCFG8_OUTCFG32_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71258   TIMER_OUTCFG8_OUTCFG32_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71259   TIMER_OUTCFG8_OUTCFG32_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71260   TIMER_OUTCFG8_OUTCFG32_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71261   TIMER_OUTCFG8_OUTCFG32_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71262   TIMER_OUTCFG8_OUTCFG32_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71263   TIMER_OUTCFG8_OUTCFG32_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71264   TIMER_OUTCFG8_OUTCFG32_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71265   TIMER_OUTCFG8_OUTCFG32_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71266   TIMER_OUTCFG8_OUTCFG32_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71267   TIMER_OUTCFG8_OUTCFG32_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71268   TIMER_OUTCFG8_OUTCFG32_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71269   TIMER_OUTCFG8_OUTCFG32_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71270   TIMER_OUTCFG8_OUTCFG32_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71271   TIMER_OUTCFG8_OUTCFG32_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71272   TIMER_OUTCFG8_OUTCFG32_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71273   TIMER_OUTCFG8_OUTCFG32_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71274   TIMER_OUTCFG8_OUTCFG32_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71275   TIMER_OUTCFG8_OUTCFG32_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71276   TIMER_OUTCFG8_OUTCFG32_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71277   TIMER_OUTCFG8_OUTCFG32_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71278   TIMER_OUTCFG8_OUTCFG32_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71279   TIMER_OUTCFG8_OUTCFG32_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71280   TIMER_OUTCFG8_OUTCFG32_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71281   TIMER_OUTCFG8_OUTCFG32_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71282   TIMER_OUTCFG8_OUTCFG32_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71283   TIMER_OUTCFG8_OUTCFG32_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71284   TIMER_OUTCFG8_OUTCFG32_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71285   TIMER_OUTCFG8_OUTCFG32_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71286   TIMER_OUTCFG8_OUTCFG32_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71287   TIMER_OUTCFG8_OUTCFG32_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71288   TIMER_OUTCFG8_OUTCFG32_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71289   TIMER_OUTCFG8_OUTCFG32_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71290   TIMER_OUTCFG8_OUTCFG32_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71291   TIMER_OUTCFG8_OUTCFG32_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71292   TIMER_OUTCFG8_OUTCFG32_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71293   TIMER_OUTCFG8_OUTCFG32_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71294   TIMER_OUTCFG8_OUTCFG32_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71295   TIMER_OUTCFG8_OUTCFG32_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71296 } TIMER_OUTCFG8_OUTCFG32_Enum;
71297 
71298 /* ========================================================  OUTCFG9  ======================================================== */
71299 /* ============================================  TIMER OUTCFG9 OUTCFG39 [24..29]  ============================================ */
71300 typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG39                                                    */
71301   TIMER_OUTCFG9_OUTCFG39_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71302   TIMER_OUTCFG9_OUTCFG39_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71303   TIMER_OUTCFG9_OUTCFG39_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71304   TIMER_OUTCFG9_OUTCFG39_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71305   TIMER_OUTCFG9_OUTCFG39_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71306   TIMER_OUTCFG9_OUTCFG39_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71307   TIMER_OUTCFG9_OUTCFG39_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71308   TIMER_OUTCFG9_OUTCFG39_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71309   TIMER_OUTCFG9_OUTCFG39_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71310   TIMER_OUTCFG9_OUTCFG39_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71311   TIMER_OUTCFG9_OUTCFG39_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71312   TIMER_OUTCFG9_OUTCFG39_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71313   TIMER_OUTCFG9_OUTCFG39_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71314   TIMER_OUTCFG9_OUTCFG39_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71315   TIMER_OUTCFG9_OUTCFG39_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71316   TIMER_OUTCFG9_OUTCFG39_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71317   TIMER_OUTCFG9_OUTCFG39_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71318   TIMER_OUTCFG9_OUTCFG39_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71319   TIMER_OUTCFG9_OUTCFG39_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71320   TIMER_OUTCFG9_OUTCFG39_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71321   TIMER_OUTCFG9_OUTCFG39_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71322   TIMER_OUTCFG9_OUTCFG39_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71323   TIMER_OUTCFG9_OUTCFG39_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71324   TIMER_OUTCFG9_OUTCFG39_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71325   TIMER_OUTCFG9_OUTCFG39_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71326   TIMER_OUTCFG9_OUTCFG39_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71327   TIMER_OUTCFG9_OUTCFG39_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71328   TIMER_OUTCFG9_OUTCFG39_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71329   TIMER_OUTCFG9_OUTCFG39_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71330   TIMER_OUTCFG9_OUTCFG39_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71331   TIMER_OUTCFG9_OUTCFG39_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71332   TIMER_OUTCFG9_OUTCFG39_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71333   TIMER_OUTCFG9_OUTCFG39_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71334   TIMER_OUTCFG9_OUTCFG39_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71335   TIMER_OUTCFG9_OUTCFG39_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71336   TIMER_OUTCFG9_OUTCFG39_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71337   TIMER_OUTCFG9_OUTCFG39_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71338   TIMER_OUTCFG9_OUTCFG39_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71339   TIMER_OUTCFG9_OUTCFG39_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71340   TIMER_OUTCFG9_OUTCFG39_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71341   TIMER_OUTCFG9_OUTCFG39_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71342 } TIMER_OUTCFG9_OUTCFG39_Enum;
71343 
71344 /* ============================================  TIMER OUTCFG9 OUTCFG38 [16..21]  ============================================ */
71345 typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG38                                                    */
71346   TIMER_OUTCFG9_OUTCFG38_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71347   TIMER_OUTCFG9_OUTCFG38_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71348   TIMER_OUTCFG9_OUTCFG38_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71349   TIMER_OUTCFG9_OUTCFG38_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71350   TIMER_OUTCFG9_OUTCFG38_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71351   TIMER_OUTCFG9_OUTCFG38_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71352   TIMER_OUTCFG9_OUTCFG38_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71353   TIMER_OUTCFG9_OUTCFG38_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71354   TIMER_OUTCFG9_OUTCFG38_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71355   TIMER_OUTCFG9_OUTCFG38_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71356   TIMER_OUTCFG9_OUTCFG38_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71357   TIMER_OUTCFG9_OUTCFG38_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71358   TIMER_OUTCFG9_OUTCFG38_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71359   TIMER_OUTCFG9_OUTCFG38_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71360   TIMER_OUTCFG9_OUTCFG38_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71361   TIMER_OUTCFG9_OUTCFG38_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71362   TIMER_OUTCFG9_OUTCFG38_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71363   TIMER_OUTCFG9_OUTCFG38_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71364   TIMER_OUTCFG9_OUTCFG38_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71365   TIMER_OUTCFG9_OUTCFG38_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71366   TIMER_OUTCFG9_OUTCFG38_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71367   TIMER_OUTCFG9_OUTCFG38_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71368   TIMER_OUTCFG9_OUTCFG38_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71369   TIMER_OUTCFG9_OUTCFG38_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71370   TIMER_OUTCFG9_OUTCFG38_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71371   TIMER_OUTCFG9_OUTCFG38_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71372   TIMER_OUTCFG9_OUTCFG38_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71373   TIMER_OUTCFG9_OUTCFG38_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71374   TIMER_OUTCFG9_OUTCFG38_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71375   TIMER_OUTCFG9_OUTCFG38_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71376   TIMER_OUTCFG9_OUTCFG38_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71377   TIMER_OUTCFG9_OUTCFG38_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71378   TIMER_OUTCFG9_OUTCFG38_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71379   TIMER_OUTCFG9_OUTCFG38_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71380   TIMER_OUTCFG9_OUTCFG38_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71381   TIMER_OUTCFG9_OUTCFG38_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71382   TIMER_OUTCFG9_OUTCFG38_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71383   TIMER_OUTCFG9_OUTCFG38_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71384   TIMER_OUTCFG9_OUTCFG38_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71385   TIMER_OUTCFG9_OUTCFG38_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71386   TIMER_OUTCFG9_OUTCFG38_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71387 } TIMER_OUTCFG9_OUTCFG38_Enum;
71388 
71389 /* ============================================  TIMER OUTCFG9 OUTCFG37 [8..13]  ============================================= */
71390 typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG37                                                    */
71391   TIMER_OUTCFG9_OUTCFG37_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71392   TIMER_OUTCFG9_OUTCFG37_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71393   TIMER_OUTCFG9_OUTCFG37_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71394   TIMER_OUTCFG9_OUTCFG37_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71395   TIMER_OUTCFG9_OUTCFG37_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71396   TIMER_OUTCFG9_OUTCFG37_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71397   TIMER_OUTCFG9_OUTCFG37_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71398   TIMER_OUTCFG9_OUTCFG37_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71399   TIMER_OUTCFG9_OUTCFG37_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71400   TIMER_OUTCFG9_OUTCFG37_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71401   TIMER_OUTCFG9_OUTCFG37_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71402   TIMER_OUTCFG9_OUTCFG37_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71403   TIMER_OUTCFG9_OUTCFG37_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71404   TIMER_OUTCFG9_OUTCFG37_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71405   TIMER_OUTCFG9_OUTCFG37_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71406   TIMER_OUTCFG9_OUTCFG37_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71407   TIMER_OUTCFG9_OUTCFG37_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71408   TIMER_OUTCFG9_OUTCFG37_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71409   TIMER_OUTCFG9_OUTCFG37_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71410   TIMER_OUTCFG9_OUTCFG37_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71411   TIMER_OUTCFG9_OUTCFG37_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71412   TIMER_OUTCFG9_OUTCFG37_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71413   TIMER_OUTCFG9_OUTCFG37_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71414   TIMER_OUTCFG9_OUTCFG37_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71415   TIMER_OUTCFG9_OUTCFG37_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71416   TIMER_OUTCFG9_OUTCFG37_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71417   TIMER_OUTCFG9_OUTCFG37_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71418   TIMER_OUTCFG9_OUTCFG37_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71419   TIMER_OUTCFG9_OUTCFG37_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71420   TIMER_OUTCFG9_OUTCFG37_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71421   TIMER_OUTCFG9_OUTCFG37_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71422   TIMER_OUTCFG9_OUTCFG37_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71423   TIMER_OUTCFG9_OUTCFG37_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71424   TIMER_OUTCFG9_OUTCFG37_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71425   TIMER_OUTCFG9_OUTCFG37_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71426   TIMER_OUTCFG9_OUTCFG37_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71427   TIMER_OUTCFG9_OUTCFG37_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71428   TIMER_OUTCFG9_OUTCFG37_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71429   TIMER_OUTCFG9_OUTCFG37_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71430   TIMER_OUTCFG9_OUTCFG37_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71431   TIMER_OUTCFG9_OUTCFG37_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71432 } TIMER_OUTCFG9_OUTCFG37_Enum;
71433 
71434 /* =============================================  TIMER OUTCFG9 OUTCFG36 [0..5]  ============================================= */
71435 typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG36                                                    */
71436   TIMER_OUTCFG9_OUTCFG36_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71437   TIMER_OUTCFG9_OUTCFG36_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71438   TIMER_OUTCFG9_OUTCFG36_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71439   TIMER_OUTCFG9_OUTCFG36_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71440   TIMER_OUTCFG9_OUTCFG36_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71441   TIMER_OUTCFG9_OUTCFG36_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71442   TIMER_OUTCFG9_OUTCFG36_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71443   TIMER_OUTCFG9_OUTCFG36_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71444   TIMER_OUTCFG9_OUTCFG36_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71445   TIMER_OUTCFG9_OUTCFG36_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71446   TIMER_OUTCFG9_OUTCFG36_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71447   TIMER_OUTCFG9_OUTCFG36_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71448   TIMER_OUTCFG9_OUTCFG36_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71449   TIMER_OUTCFG9_OUTCFG36_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71450   TIMER_OUTCFG9_OUTCFG36_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71451   TIMER_OUTCFG9_OUTCFG36_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71452   TIMER_OUTCFG9_OUTCFG36_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71453   TIMER_OUTCFG9_OUTCFG36_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71454   TIMER_OUTCFG9_OUTCFG36_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71455   TIMER_OUTCFG9_OUTCFG36_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71456   TIMER_OUTCFG9_OUTCFG36_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71457   TIMER_OUTCFG9_OUTCFG36_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71458   TIMER_OUTCFG9_OUTCFG36_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71459   TIMER_OUTCFG9_OUTCFG36_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71460   TIMER_OUTCFG9_OUTCFG36_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71461   TIMER_OUTCFG9_OUTCFG36_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71462   TIMER_OUTCFG9_OUTCFG36_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71463   TIMER_OUTCFG9_OUTCFG36_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71464   TIMER_OUTCFG9_OUTCFG36_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71465   TIMER_OUTCFG9_OUTCFG36_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71466   TIMER_OUTCFG9_OUTCFG36_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71467   TIMER_OUTCFG9_OUTCFG36_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71468   TIMER_OUTCFG9_OUTCFG36_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71469   TIMER_OUTCFG9_OUTCFG36_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71470   TIMER_OUTCFG9_OUTCFG36_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71471   TIMER_OUTCFG9_OUTCFG36_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71472   TIMER_OUTCFG9_OUTCFG36_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71473   TIMER_OUTCFG9_OUTCFG36_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71474   TIMER_OUTCFG9_OUTCFG36_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71475   TIMER_OUTCFG9_OUTCFG36_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71476   TIMER_OUTCFG9_OUTCFG36_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
71477 } TIMER_OUTCFG9_OUTCFG36_Enum;
71478 
71479 /* =======================================================  OUTCFG10  ======================================================== */
71480 /* ===========================================  TIMER OUTCFG10 OUTCFG43 [24..29]  ============================================ */
71481 typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG43                                                   */
71482   TIMER_OUTCFG10_OUTCFG43_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71483   TIMER_OUTCFG10_OUTCFG43_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71484   TIMER_OUTCFG10_OUTCFG43_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71485   TIMER_OUTCFG10_OUTCFG43_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71486   TIMER_OUTCFG10_OUTCFG43_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71487   TIMER_OUTCFG10_OUTCFG43_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71488   TIMER_OUTCFG10_OUTCFG43_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71489   TIMER_OUTCFG10_OUTCFG43_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71490   TIMER_OUTCFG10_OUTCFG43_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71491   TIMER_OUTCFG10_OUTCFG43_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71492   TIMER_OUTCFG10_OUTCFG43_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71493   TIMER_OUTCFG10_OUTCFG43_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71494   TIMER_OUTCFG10_OUTCFG43_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71495   TIMER_OUTCFG10_OUTCFG43_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71496   TIMER_OUTCFG10_OUTCFG43_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71497   TIMER_OUTCFG10_OUTCFG43_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71498   TIMER_OUTCFG10_OUTCFG43_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71499   TIMER_OUTCFG10_OUTCFG43_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71500   TIMER_OUTCFG10_OUTCFG43_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71501   TIMER_OUTCFG10_OUTCFG43_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71502   TIMER_OUTCFG10_OUTCFG43_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71503   TIMER_OUTCFG10_OUTCFG43_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71504   TIMER_OUTCFG10_OUTCFG43_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71505   TIMER_OUTCFG10_OUTCFG43_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71506   TIMER_OUTCFG10_OUTCFG43_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71507   TIMER_OUTCFG10_OUTCFG43_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71508   TIMER_OUTCFG10_OUTCFG43_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71509   TIMER_OUTCFG10_OUTCFG43_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71510   TIMER_OUTCFG10_OUTCFG43_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71511   TIMER_OUTCFG10_OUTCFG43_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71512   TIMER_OUTCFG10_OUTCFG43_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71513   TIMER_OUTCFG10_OUTCFG43_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71514   TIMER_OUTCFG10_OUTCFG43_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71515   TIMER_OUTCFG10_OUTCFG43_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71516   TIMER_OUTCFG10_OUTCFG43_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71517   TIMER_OUTCFG10_OUTCFG43_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71518   TIMER_OUTCFG10_OUTCFG43_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71519   TIMER_OUTCFG10_OUTCFG43_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71520   TIMER_OUTCFG10_OUTCFG43_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71521   TIMER_OUTCFG10_OUTCFG43_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71522   TIMER_OUTCFG10_OUTCFG43_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71523 } TIMER_OUTCFG10_OUTCFG43_Enum;
71524 
71525 /* ===========================================  TIMER OUTCFG10 OUTCFG42 [16..21]  ============================================ */
71526 typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG42                                                   */
71527   TIMER_OUTCFG10_OUTCFG42_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71528   TIMER_OUTCFG10_OUTCFG42_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71529   TIMER_OUTCFG10_OUTCFG42_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71530   TIMER_OUTCFG10_OUTCFG42_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71531   TIMER_OUTCFG10_OUTCFG42_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71532   TIMER_OUTCFG10_OUTCFG42_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71533   TIMER_OUTCFG10_OUTCFG42_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71534   TIMER_OUTCFG10_OUTCFG42_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71535   TIMER_OUTCFG10_OUTCFG42_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71536   TIMER_OUTCFG10_OUTCFG42_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71537   TIMER_OUTCFG10_OUTCFG42_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71538   TIMER_OUTCFG10_OUTCFG42_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71539   TIMER_OUTCFG10_OUTCFG42_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71540   TIMER_OUTCFG10_OUTCFG42_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71541   TIMER_OUTCFG10_OUTCFG42_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71542   TIMER_OUTCFG10_OUTCFG42_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71543   TIMER_OUTCFG10_OUTCFG42_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71544   TIMER_OUTCFG10_OUTCFG42_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71545   TIMER_OUTCFG10_OUTCFG42_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71546   TIMER_OUTCFG10_OUTCFG42_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71547   TIMER_OUTCFG10_OUTCFG42_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71548   TIMER_OUTCFG10_OUTCFG42_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71549   TIMER_OUTCFG10_OUTCFG42_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71550   TIMER_OUTCFG10_OUTCFG42_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71551   TIMER_OUTCFG10_OUTCFG42_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71552   TIMER_OUTCFG10_OUTCFG42_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71553   TIMER_OUTCFG10_OUTCFG42_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71554   TIMER_OUTCFG10_OUTCFG42_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71555   TIMER_OUTCFG10_OUTCFG42_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71556   TIMER_OUTCFG10_OUTCFG42_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71557   TIMER_OUTCFG10_OUTCFG42_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71558   TIMER_OUTCFG10_OUTCFG42_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71559   TIMER_OUTCFG10_OUTCFG42_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71560   TIMER_OUTCFG10_OUTCFG42_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71561   TIMER_OUTCFG10_OUTCFG42_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71562   TIMER_OUTCFG10_OUTCFG42_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71563   TIMER_OUTCFG10_OUTCFG42_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71564   TIMER_OUTCFG10_OUTCFG42_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71565   TIMER_OUTCFG10_OUTCFG42_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71566   TIMER_OUTCFG10_OUTCFG42_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71567   TIMER_OUTCFG10_OUTCFG42_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71568 } TIMER_OUTCFG10_OUTCFG42_Enum;
71569 
71570 /* ============================================  TIMER OUTCFG10 OUTCFG41 [8..13]  ============================================ */
71571 typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG41                                                   */
71572   TIMER_OUTCFG10_OUTCFG41_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71573   TIMER_OUTCFG10_OUTCFG41_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71574   TIMER_OUTCFG10_OUTCFG41_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71575   TIMER_OUTCFG10_OUTCFG41_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71576   TIMER_OUTCFG10_OUTCFG41_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71577   TIMER_OUTCFG10_OUTCFG41_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71578   TIMER_OUTCFG10_OUTCFG41_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71579   TIMER_OUTCFG10_OUTCFG41_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71580   TIMER_OUTCFG10_OUTCFG41_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71581   TIMER_OUTCFG10_OUTCFG41_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71582   TIMER_OUTCFG10_OUTCFG41_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71583   TIMER_OUTCFG10_OUTCFG41_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71584   TIMER_OUTCFG10_OUTCFG41_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71585   TIMER_OUTCFG10_OUTCFG41_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71586   TIMER_OUTCFG10_OUTCFG41_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71587   TIMER_OUTCFG10_OUTCFG41_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71588   TIMER_OUTCFG10_OUTCFG41_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71589   TIMER_OUTCFG10_OUTCFG41_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71590   TIMER_OUTCFG10_OUTCFG41_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71591   TIMER_OUTCFG10_OUTCFG41_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71592   TIMER_OUTCFG10_OUTCFG41_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71593   TIMER_OUTCFG10_OUTCFG41_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71594   TIMER_OUTCFG10_OUTCFG41_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71595   TIMER_OUTCFG10_OUTCFG41_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71596   TIMER_OUTCFG10_OUTCFG41_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71597   TIMER_OUTCFG10_OUTCFG41_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71598   TIMER_OUTCFG10_OUTCFG41_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71599   TIMER_OUTCFG10_OUTCFG41_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71600   TIMER_OUTCFG10_OUTCFG41_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71601   TIMER_OUTCFG10_OUTCFG41_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71602   TIMER_OUTCFG10_OUTCFG41_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71603   TIMER_OUTCFG10_OUTCFG41_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71604   TIMER_OUTCFG10_OUTCFG41_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71605   TIMER_OUTCFG10_OUTCFG41_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71606   TIMER_OUTCFG10_OUTCFG41_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71607   TIMER_OUTCFG10_OUTCFG41_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71608   TIMER_OUTCFG10_OUTCFG41_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71609   TIMER_OUTCFG10_OUTCFG41_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71610   TIMER_OUTCFG10_OUTCFG41_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71611   TIMER_OUTCFG10_OUTCFG41_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71612   TIMER_OUTCFG10_OUTCFG41_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71613 } TIMER_OUTCFG10_OUTCFG41_Enum;
71614 
71615 /* ============================================  TIMER OUTCFG10 OUTCFG40 [0..5]  ============================================= */
71616 typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG40                                                   */
71617   TIMER_OUTCFG10_OUTCFG40_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71618   TIMER_OUTCFG10_OUTCFG40_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71619   TIMER_OUTCFG10_OUTCFG40_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71620   TIMER_OUTCFG10_OUTCFG40_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71621   TIMER_OUTCFG10_OUTCFG40_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71622   TIMER_OUTCFG10_OUTCFG40_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71623   TIMER_OUTCFG10_OUTCFG40_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71624   TIMER_OUTCFG10_OUTCFG40_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71625   TIMER_OUTCFG10_OUTCFG40_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71626   TIMER_OUTCFG10_OUTCFG40_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71627   TIMER_OUTCFG10_OUTCFG40_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71628   TIMER_OUTCFG10_OUTCFG40_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71629   TIMER_OUTCFG10_OUTCFG40_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71630   TIMER_OUTCFG10_OUTCFG40_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71631   TIMER_OUTCFG10_OUTCFG40_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71632   TIMER_OUTCFG10_OUTCFG40_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71633   TIMER_OUTCFG10_OUTCFG40_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71634   TIMER_OUTCFG10_OUTCFG40_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71635   TIMER_OUTCFG10_OUTCFG40_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71636   TIMER_OUTCFG10_OUTCFG40_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71637   TIMER_OUTCFG10_OUTCFG40_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71638   TIMER_OUTCFG10_OUTCFG40_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71639   TIMER_OUTCFG10_OUTCFG40_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71640   TIMER_OUTCFG10_OUTCFG40_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71641   TIMER_OUTCFG10_OUTCFG40_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71642   TIMER_OUTCFG10_OUTCFG40_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71643   TIMER_OUTCFG10_OUTCFG40_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71644   TIMER_OUTCFG10_OUTCFG40_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71645   TIMER_OUTCFG10_OUTCFG40_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71646   TIMER_OUTCFG10_OUTCFG40_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71647   TIMER_OUTCFG10_OUTCFG40_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71648   TIMER_OUTCFG10_OUTCFG40_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71649   TIMER_OUTCFG10_OUTCFG40_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71650   TIMER_OUTCFG10_OUTCFG40_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71651   TIMER_OUTCFG10_OUTCFG40_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71652   TIMER_OUTCFG10_OUTCFG40_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71653   TIMER_OUTCFG10_OUTCFG40_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71654   TIMER_OUTCFG10_OUTCFG40_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71655   TIMER_OUTCFG10_OUTCFG40_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71656   TIMER_OUTCFG10_OUTCFG40_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71657   TIMER_OUTCFG10_OUTCFG40_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71658 } TIMER_OUTCFG10_OUTCFG40_Enum;
71659 
71660 /* =======================================================  OUTCFG11  ======================================================== */
71661 /* ===========================================  TIMER OUTCFG11 OUTCFG47 [24..29]  ============================================ */
71662 typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG47                                                   */
71663   TIMER_OUTCFG11_OUTCFG47_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71664   TIMER_OUTCFG11_OUTCFG47_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71665   TIMER_OUTCFG11_OUTCFG47_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71666   TIMER_OUTCFG11_OUTCFG47_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71667   TIMER_OUTCFG11_OUTCFG47_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71668   TIMER_OUTCFG11_OUTCFG47_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71669   TIMER_OUTCFG11_OUTCFG47_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71670   TIMER_OUTCFG11_OUTCFG47_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71671   TIMER_OUTCFG11_OUTCFG47_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71672   TIMER_OUTCFG11_OUTCFG47_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71673   TIMER_OUTCFG11_OUTCFG47_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71674   TIMER_OUTCFG11_OUTCFG47_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71675   TIMER_OUTCFG11_OUTCFG47_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71676   TIMER_OUTCFG11_OUTCFG47_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71677   TIMER_OUTCFG11_OUTCFG47_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71678   TIMER_OUTCFG11_OUTCFG47_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71679   TIMER_OUTCFG11_OUTCFG47_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71680   TIMER_OUTCFG11_OUTCFG47_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71681   TIMER_OUTCFG11_OUTCFG47_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71682   TIMER_OUTCFG11_OUTCFG47_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71683   TIMER_OUTCFG11_OUTCFG47_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71684   TIMER_OUTCFG11_OUTCFG47_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71685   TIMER_OUTCFG11_OUTCFG47_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71686   TIMER_OUTCFG11_OUTCFG47_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71687   TIMER_OUTCFG11_OUTCFG47_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71688   TIMER_OUTCFG11_OUTCFG47_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71689   TIMER_OUTCFG11_OUTCFG47_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71690   TIMER_OUTCFG11_OUTCFG47_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71691   TIMER_OUTCFG11_OUTCFG47_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71692   TIMER_OUTCFG11_OUTCFG47_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71693   TIMER_OUTCFG11_OUTCFG47_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71694   TIMER_OUTCFG11_OUTCFG47_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71695   TIMER_OUTCFG11_OUTCFG47_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71696   TIMER_OUTCFG11_OUTCFG47_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71697   TIMER_OUTCFG11_OUTCFG47_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71698   TIMER_OUTCFG11_OUTCFG47_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71699   TIMER_OUTCFG11_OUTCFG47_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71700   TIMER_OUTCFG11_OUTCFG47_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71701   TIMER_OUTCFG11_OUTCFG47_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71702   TIMER_OUTCFG11_OUTCFG47_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71703   TIMER_OUTCFG11_OUTCFG47_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71704 } TIMER_OUTCFG11_OUTCFG47_Enum;
71705 
71706 /* ===========================================  TIMER OUTCFG11 OUTCFG46 [16..21]  ============================================ */
71707 typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG46                                                   */
71708   TIMER_OUTCFG11_OUTCFG46_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71709   TIMER_OUTCFG11_OUTCFG46_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71710   TIMER_OUTCFG11_OUTCFG46_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71711   TIMER_OUTCFG11_OUTCFG46_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71712   TIMER_OUTCFG11_OUTCFG46_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71713   TIMER_OUTCFG11_OUTCFG46_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71714   TIMER_OUTCFG11_OUTCFG46_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71715   TIMER_OUTCFG11_OUTCFG46_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71716   TIMER_OUTCFG11_OUTCFG46_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71717   TIMER_OUTCFG11_OUTCFG46_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71718   TIMER_OUTCFG11_OUTCFG46_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71719   TIMER_OUTCFG11_OUTCFG46_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71720   TIMER_OUTCFG11_OUTCFG46_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71721   TIMER_OUTCFG11_OUTCFG46_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71722   TIMER_OUTCFG11_OUTCFG46_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71723   TIMER_OUTCFG11_OUTCFG46_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71724   TIMER_OUTCFG11_OUTCFG46_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71725   TIMER_OUTCFG11_OUTCFG46_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71726   TIMER_OUTCFG11_OUTCFG46_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71727   TIMER_OUTCFG11_OUTCFG46_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71728   TIMER_OUTCFG11_OUTCFG46_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71729   TIMER_OUTCFG11_OUTCFG46_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71730   TIMER_OUTCFG11_OUTCFG46_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71731   TIMER_OUTCFG11_OUTCFG46_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71732   TIMER_OUTCFG11_OUTCFG46_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71733   TIMER_OUTCFG11_OUTCFG46_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71734   TIMER_OUTCFG11_OUTCFG46_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71735   TIMER_OUTCFG11_OUTCFG46_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71736   TIMER_OUTCFG11_OUTCFG46_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71737   TIMER_OUTCFG11_OUTCFG46_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71738   TIMER_OUTCFG11_OUTCFG46_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71739   TIMER_OUTCFG11_OUTCFG46_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71740   TIMER_OUTCFG11_OUTCFG46_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71741   TIMER_OUTCFG11_OUTCFG46_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71742   TIMER_OUTCFG11_OUTCFG46_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71743   TIMER_OUTCFG11_OUTCFG46_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71744   TIMER_OUTCFG11_OUTCFG46_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71745   TIMER_OUTCFG11_OUTCFG46_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71746   TIMER_OUTCFG11_OUTCFG46_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71747   TIMER_OUTCFG11_OUTCFG46_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71748   TIMER_OUTCFG11_OUTCFG46_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71749 } TIMER_OUTCFG11_OUTCFG46_Enum;
71750 
71751 /* ============================================  TIMER OUTCFG11 OUTCFG45 [8..13]  ============================================ */
71752 typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG45                                                   */
71753   TIMER_OUTCFG11_OUTCFG45_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71754   TIMER_OUTCFG11_OUTCFG45_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71755   TIMER_OUTCFG11_OUTCFG45_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71756   TIMER_OUTCFG11_OUTCFG45_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71757   TIMER_OUTCFG11_OUTCFG45_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71758   TIMER_OUTCFG11_OUTCFG45_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71759   TIMER_OUTCFG11_OUTCFG45_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71760   TIMER_OUTCFG11_OUTCFG45_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71761   TIMER_OUTCFG11_OUTCFG45_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71762   TIMER_OUTCFG11_OUTCFG45_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71763   TIMER_OUTCFG11_OUTCFG45_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71764   TIMER_OUTCFG11_OUTCFG45_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71765   TIMER_OUTCFG11_OUTCFG45_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71766   TIMER_OUTCFG11_OUTCFG45_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71767   TIMER_OUTCFG11_OUTCFG45_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71768   TIMER_OUTCFG11_OUTCFG45_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71769   TIMER_OUTCFG11_OUTCFG45_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71770   TIMER_OUTCFG11_OUTCFG45_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71771   TIMER_OUTCFG11_OUTCFG45_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71772   TIMER_OUTCFG11_OUTCFG45_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71773   TIMER_OUTCFG11_OUTCFG45_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71774   TIMER_OUTCFG11_OUTCFG45_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71775   TIMER_OUTCFG11_OUTCFG45_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71776   TIMER_OUTCFG11_OUTCFG45_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71777   TIMER_OUTCFG11_OUTCFG45_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71778   TIMER_OUTCFG11_OUTCFG45_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71779   TIMER_OUTCFG11_OUTCFG45_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71780   TIMER_OUTCFG11_OUTCFG45_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71781   TIMER_OUTCFG11_OUTCFG45_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71782   TIMER_OUTCFG11_OUTCFG45_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71783   TIMER_OUTCFG11_OUTCFG45_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71784   TIMER_OUTCFG11_OUTCFG45_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71785   TIMER_OUTCFG11_OUTCFG45_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71786   TIMER_OUTCFG11_OUTCFG45_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71787   TIMER_OUTCFG11_OUTCFG45_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71788   TIMER_OUTCFG11_OUTCFG45_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71789   TIMER_OUTCFG11_OUTCFG45_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71790   TIMER_OUTCFG11_OUTCFG45_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71791   TIMER_OUTCFG11_OUTCFG45_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71792   TIMER_OUTCFG11_OUTCFG45_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71793   TIMER_OUTCFG11_OUTCFG45_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71794 } TIMER_OUTCFG11_OUTCFG45_Enum;
71795 
71796 /* ============================================  TIMER OUTCFG11 OUTCFG44 [0..5]  ============================================= */
71797 typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG44                                                   */
71798   TIMER_OUTCFG11_OUTCFG44_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71799   TIMER_OUTCFG11_OUTCFG44_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71800   TIMER_OUTCFG11_OUTCFG44_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71801   TIMER_OUTCFG11_OUTCFG44_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71802   TIMER_OUTCFG11_OUTCFG44_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71803   TIMER_OUTCFG11_OUTCFG44_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71804   TIMER_OUTCFG11_OUTCFG44_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71805   TIMER_OUTCFG11_OUTCFG44_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71806   TIMER_OUTCFG11_OUTCFG44_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71807   TIMER_OUTCFG11_OUTCFG44_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71808   TIMER_OUTCFG11_OUTCFG44_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71809   TIMER_OUTCFG11_OUTCFG44_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71810   TIMER_OUTCFG11_OUTCFG44_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71811   TIMER_OUTCFG11_OUTCFG44_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71812   TIMER_OUTCFG11_OUTCFG44_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71813   TIMER_OUTCFG11_OUTCFG44_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71814   TIMER_OUTCFG11_OUTCFG44_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71815   TIMER_OUTCFG11_OUTCFG44_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71816   TIMER_OUTCFG11_OUTCFG44_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71817   TIMER_OUTCFG11_OUTCFG44_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71818   TIMER_OUTCFG11_OUTCFG44_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71819   TIMER_OUTCFG11_OUTCFG44_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71820   TIMER_OUTCFG11_OUTCFG44_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71821   TIMER_OUTCFG11_OUTCFG44_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71822   TIMER_OUTCFG11_OUTCFG44_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71823   TIMER_OUTCFG11_OUTCFG44_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71824   TIMER_OUTCFG11_OUTCFG44_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71825   TIMER_OUTCFG11_OUTCFG44_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71826   TIMER_OUTCFG11_OUTCFG44_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71827   TIMER_OUTCFG11_OUTCFG44_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71828   TIMER_OUTCFG11_OUTCFG44_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71829   TIMER_OUTCFG11_OUTCFG44_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71830   TIMER_OUTCFG11_OUTCFG44_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71831   TIMER_OUTCFG11_OUTCFG44_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71832   TIMER_OUTCFG11_OUTCFG44_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71833   TIMER_OUTCFG11_OUTCFG44_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71834   TIMER_OUTCFG11_OUTCFG44_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71835   TIMER_OUTCFG11_OUTCFG44_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71836   TIMER_OUTCFG11_OUTCFG44_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71837   TIMER_OUTCFG11_OUTCFG44_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71838   TIMER_OUTCFG11_OUTCFG44_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71839 } TIMER_OUTCFG11_OUTCFG44_Enum;
71840 
71841 /* =======================================================  OUTCFG12  ======================================================== */
71842 /* ===========================================  TIMER OUTCFG12 OUTCFG51 [24..29]  ============================================ */
71843 typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG51                                                   */
71844   TIMER_OUTCFG12_OUTCFG51_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71845   TIMER_OUTCFG12_OUTCFG51_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71846   TIMER_OUTCFG12_OUTCFG51_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71847   TIMER_OUTCFG12_OUTCFG51_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71848   TIMER_OUTCFG12_OUTCFG51_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71849   TIMER_OUTCFG12_OUTCFG51_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71850   TIMER_OUTCFG12_OUTCFG51_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71851   TIMER_OUTCFG12_OUTCFG51_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71852   TIMER_OUTCFG12_OUTCFG51_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71853   TIMER_OUTCFG12_OUTCFG51_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71854   TIMER_OUTCFG12_OUTCFG51_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71855   TIMER_OUTCFG12_OUTCFG51_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71856   TIMER_OUTCFG12_OUTCFG51_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71857   TIMER_OUTCFG12_OUTCFG51_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71858   TIMER_OUTCFG12_OUTCFG51_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71859   TIMER_OUTCFG12_OUTCFG51_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71860   TIMER_OUTCFG12_OUTCFG51_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71861   TIMER_OUTCFG12_OUTCFG51_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71862   TIMER_OUTCFG12_OUTCFG51_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71863   TIMER_OUTCFG12_OUTCFG51_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71864   TIMER_OUTCFG12_OUTCFG51_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71865   TIMER_OUTCFG12_OUTCFG51_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71866   TIMER_OUTCFG12_OUTCFG51_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71867   TIMER_OUTCFG12_OUTCFG51_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71868   TIMER_OUTCFG12_OUTCFG51_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71869   TIMER_OUTCFG12_OUTCFG51_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71870   TIMER_OUTCFG12_OUTCFG51_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71871   TIMER_OUTCFG12_OUTCFG51_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71872   TIMER_OUTCFG12_OUTCFG51_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71873   TIMER_OUTCFG12_OUTCFG51_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71874   TIMER_OUTCFG12_OUTCFG51_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71875   TIMER_OUTCFG12_OUTCFG51_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71876   TIMER_OUTCFG12_OUTCFG51_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71877   TIMER_OUTCFG12_OUTCFG51_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71878   TIMER_OUTCFG12_OUTCFG51_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71879   TIMER_OUTCFG12_OUTCFG51_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71880   TIMER_OUTCFG12_OUTCFG51_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71881   TIMER_OUTCFG12_OUTCFG51_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71882   TIMER_OUTCFG12_OUTCFG51_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71883   TIMER_OUTCFG12_OUTCFG51_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71884   TIMER_OUTCFG12_OUTCFG51_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71885 } TIMER_OUTCFG12_OUTCFG51_Enum;
71886 
71887 /* ===========================================  TIMER OUTCFG12 OUTCFG50 [16..21]  ============================================ */
71888 typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG50                                                   */
71889   TIMER_OUTCFG12_OUTCFG50_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71890   TIMER_OUTCFG12_OUTCFG50_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71891   TIMER_OUTCFG12_OUTCFG50_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71892   TIMER_OUTCFG12_OUTCFG50_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71893   TIMER_OUTCFG12_OUTCFG50_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71894   TIMER_OUTCFG12_OUTCFG50_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71895   TIMER_OUTCFG12_OUTCFG50_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71896   TIMER_OUTCFG12_OUTCFG50_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71897   TIMER_OUTCFG12_OUTCFG50_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71898   TIMER_OUTCFG12_OUTCFG50_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71899   TIMER_OUTCFG12_OUTCFG50_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71900   TIMER_OUTCFG12_OUTCFG50_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71901   TIMER_OUTCFG12_OUTCFG50_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71902   TIMER_OUTCFG12_OUTCFG50_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71903   TIMER_OUTCFG12_OUTCFG50_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71904   TIMER_OUTCFG12_OUTCFG50_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71905   TIMER_OUTCFG12_OUTCFG50_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71906   TIMER_OUTCFG12_OUTCFG50_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71907   TIMER_OUTCFG12_OUTCFG50_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71908   TIMER_OUTCFG12_OUTCFG50_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71909   TIMER_OUTCFG12_OUTCFG50_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71910   TIMER_OUTCFG12_OUTCFG50_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71911   TIMER_OUTCFG12_OUTCFG50_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71912   TIMER_OUTCFG12_OUTCFG50_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71913   TIMER_OUTCFG12_OUTCFG50_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71914   TIMER_OUTCFG12_OUTCFG50_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71915   TIMER_OUTCFG12_OUTCFG50_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71916   TIMER_OUTCFG12_OUTCFG50_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71917   TIMER_OUTCFG12_OUTCFG50_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71918   TIMER_OUTCFG12_OUTCFG50_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71919   TIMER_OUTCFG12_OUTCFG50_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71920   TIMER_OUTCFG12_OUTCFG50_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71921   TIMER_OUTCFG12_OUTCFG50_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71922   TIMER_OUTCFG12_OUTCFG50_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71923   TIMER_OUTCFG12_OUTCFG50_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71924   TIMER_OUTCFG12_OUTCFG50_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71925   TIMER_OUTCFG12_OUTCFG50_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71926   TIMER_OUTCFG12_OUTCFG50_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71927   TIMER_OUTCFG12_OUTCFG50_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71928   TIMER_OUTCFG12_OUTCFG50_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71929   TIMER_OUTCFG12_OUTCFG50_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71930 } TIMER_OUTCFG12_OUTCFG50_Enum;
71931 
71932 /* ============================================  TIMER OUTCFG12 OUTCFG49 [8..13]  ============================================ */
71933 typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG49                                                   */
71934   TIMER_OUTCFG12_OUTCFG49_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71935   TIMER_OUTCFG12_OUTCFG49_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71936   TIMER_OUTCFG12_OUTCFG49_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71937   TIMER_OUTCFG12_OUTCFG49_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71938   TIMER_OUTCFG12_OUTCFG49_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71939   TIMER_OUTCFG12_OUTCFG49_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71940   TIMER_OUTCFG12_OUTCFG49_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71941   TIMER_OUTCFG12_OUTCFG49_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71942   TIMER_OUTCFG12_OUTCFG49_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71943   TIMER_OUTCFG12_OUTCFG49_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71944   TIMER_OUTCFG12_OUTCFG49_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71945   TIMER_OUTCFG12_OUTCFG49_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71946   TIMER_OUTCFG12_OUTCFG49_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71947   TIMER_OUTCFG12_OUTCFG49_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71948   TIMER_OUTCFG12_OUTCFG49_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71949   TIMER_OUTCFG12_OUTCFG49_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71950   TIMER_OUTCFG12_OUTCFG49_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71951   TIMER_OUTCFG12_OUTCFG49_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71952   TIMER_OUTCFG12_OUTCFG49_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71953   TIMER_OUTCFG12_OUTCFG49_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71954   TIMER_OUTCFG12_OUTCFG49_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
71955   TIMER_OUTCFG12_OUTCFG49_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
71956   TIMER_OUTCFG12_OUTCFG49_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
71957   TIMER_OUTCFG12_OUTCFG49_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
71958   TIMER_OUTCFG12_OUTCFG49_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
71959   TIMER_OUTCFG12_OUTCFG49_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
71960   TIMER_OUTCFG12_OUTCFG49_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
71961   TIMER_OUTCFG12_OUTCFG49_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
71962   TIMER_OUTCFG12_OUTCFG49_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
71963   TIMER_OUTCFG12_OUTCFG49_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
71964   TIMER_OUTCFG12_OUTCFG49_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
71965   TIMER_OUTCFG12_OUTCFG49_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
71966   TIMER_OUTCFG12_OUTCFG49_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
71967   TIMER_OUTCFG12_OUTCFG49_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
71968   TIMER_OUTCFG12_OUTCFG49_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
71969   TIMER_OUTCFG12_OUTCFG49_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
71970   TIMER_OUTCFG12_OUTCFG49_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
71971   TIMER_OUTCFG12_OUTCFG49_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
71972   TIMER_OUTCFG12_OUTCFG49_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
71973   TIMER_OUTCFG12_OUTCFG49_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
71974   TIMER_OUTCFG12_OUTCFG49_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
71975 } TIMER_OUTCFG12_OUTCFG49_Enum;
71976 
71977 /* ============================================  TIMER OUTCFG12 OUTCFG48 [0..5]  ============================================= */
71978 typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG48                                                   */
71979   TIMER_OUTCFG12_OUTCFG48_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
71980   TIMER_OUTCFG12_OUTCFG48_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
71981   TIMER_OUTCFG12_OUTCFG48_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
71982   TIMER_OUTCFG12_OUTCFG48_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
71983   TIMER_OUTCFG12_OUTCFG48_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
71984   TIMER_OUTCFG12_OUTCFG48_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
71985   TIMER_OUTCFG12_OUTCFG48_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
71986   TIMER_OUTCFG12_OUTCFG48_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
71987   TIMER_OUTCFG12_OUTCFG48_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
71988   TIMER_OUTCFG12_OUTCFG48_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
71989   TIMER_OUTCFG12_OUTCFG48_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
71990   TIMER_OUTCFG12_OUTCFG48_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
71991   TIMER_OUTCFG12_OUTCFG48_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
71992   TIMER_OUTCFG12_OUTCFG48_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
71993   TIMER_OUTCFG12_OUTCFG48_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
71994   TIMER_OUTCFG12_OUTCFG48_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
71995   TIMER_OUTCFG12_OUTCFG48_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
71996   TIMER_OUTCFG12_OUTCFG48_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
71997   TIMER_OUTCFG12_OUTCFG48_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
71998   TIMER_OUTCFG12_OUTCFG48_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
71999   TIMER_OUTCFG12_OUTCFG48_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72000   TIMER_OUTCFG12_OUTCFG48_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72001   TIMER_OUTCFG12_OUTCFG48_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72002   TIMER_OUTCFG12_OUTCFG48_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72003   TIMER_OUTCFG12_OUTCFG48_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72004   TIMER_OUTCFG12_OUTCFG48_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72005   TIMER_OUTCFG12_OUTCFG48_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72006   TIMER_OUTCFG12_OUTCFG48_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72007   TIMER_OUTCFG12_OUTCFG48_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72008   TIMER_OUTCFG12_OUTCFG48_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72009   TIMER_OUTCFG12_OUTCFG48_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72010   TIMER_OUTCFG12_OUTCFG48_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72011   TIMER_OUTCFG12_OUTCFG48_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72012   TIMER_OUTCFG12_OUTCFG48_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72013   TIMER_OUTCFG12_OUTCFG48_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72014   TIMER_OUTCFG12_OUTCFG48_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72015   TIMER_OUTCFG12_OUTCFG48_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72016   TIMER_OUTCFG12_OUTCFG48_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72017   TIMER_OUTCFG12_OUTCFG48_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72018   TIMER_OUTCFG12_OUTCFG48_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72019   TIMER_OUTCFG12_OUTCFG48_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72020 } TIMER_OUTCFG12_OUTCFG48_Enum;
72021 
72022 /* =======================================================  OUTCFG13  ======================================================== */
72023 /* ===========================================  TIMER OUTCFG13 OUTCFG55 [24..29]  ============================================ */
72024 typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG55                                                   */
72025   TIMER_OUTCFG13_OUTCFG55_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72026   TIMER_OUTCFG13_OUTCFG55_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72027   TIMER_OUTCFG13_OUTCFG55_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72028   TIMER_OUTCFG13_OUTCFG55_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72029   TIMER_OUTCFG13_OUTCFG55_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72030   TIMER_OUTCFG13_OUTCFG55_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72031   TIMER_OUTCFG13_OUTCFG55_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72032   TIMER_OUTCFG13_OUTCFG55_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72033   TIMER_OUTCFG13_OUTCFG55_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72034   TIMER_OUTCFG13_OUTCFG55_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72035   TIMER_OUTCFG13_OUTCFG55_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72036   TIMER_OUTCFG13_OUTCFG55_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72037   TIMER_OUTCFG13_OUTCFG55_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72038   TIMER_OUTCFG13_OUTCFG55_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72039   TIMER_OUTCFG13_OUTCFG55_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72040   TIMER_OUTCFG13_OUTCFG55_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72041   TIMER_OUTCFG13_OUTCFG55_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72042   TIMER_OUTCFG13_OUTCFG55_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72043   TIMER_OUTCFG13_OUTCFG55_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72044   TIMER_OUTCFG13_OUTCFG55_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72045   TIMER_OUTCFG13_OUTCFG55_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72046   TIMER_OUTCFG13_OUTCFG55_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72047   TIMER_OUTCFG13_OUTCFG55_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72048   TIMER_OUTCFG13_OUTCFG55_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72049   TIMER_OUTCFG13_OUTCFG55_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72050   TIMER_OUTCFG13_OUTCFG55_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72051   TIMER_OUTCFG13_OUTCFG55_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72052   TIMER_OUTCFG13_OUTCFG55_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72053   TIMER_OUTCFG13_OUTCFG55_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72054   TIMER_OUTCFG13_OUTCFG55_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72055   TIMER_OUTCFG13_OUTCFG55_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72056   TIMER_OUTCFG13_OUTCFG55_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72057   TIMER_OUTCFG13_OUTCFG55_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72058   TIMER_OUTCFG13_OUTCFG55_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72059   TIMER_OUTCFG13_OUTCFG55_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72060   TIMER_OUTCFG13_OUTCFG55_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72061   TIMER_OUTCFG13_OUTCFG55_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72062   TIMER_OUTCFG13_OUTCFG55_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72063   TIMER_OUTCFG13_OUTCFG55_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72064   TIMER_OUTCFG13_OUTCFG55_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72065   TIMER_OUTCFG13_OUTCFG55_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72066 } TIMER_OUTCFG13_OUTCFG55_Enum;
72067 
72068 /* ===========================================  TIMER OUTCFG13 OUTCFG54 [16..21]  ============================================ */
72069 typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG54                                                   */
72070   TIMER_OUTCFG13_OUTCFG54_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72071   TIMER_OUTCFG13_OUTCFG54_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72072   TIMER_OUTCFG13_OUTCFG54_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72073   TIMER_OUTCFG13_OUTCFG54_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72074   TIMER_OUTCFG13_OUTCFG54_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72075   TIMER_OUTCFG13_OUTCFG54_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72076   TIMER_OUTCFG13_OUTCFG54_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72077   TIMER_OUTCFG13_OUTCFG54_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72078   TIMER_OUTCFG13_OUTCFG54_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72079   TIMER_OUTCFG13_OUTCFG54_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72080   TIMER_OUTCFG13_OUTCFG54_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72081   TIMER_OUTCFG13_OUTCFG54_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72082   TIMER_OUTCFG13_OUTCFG54_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72083   TIMER_OUTCFG13_OUTCFG54_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72084   TIMER_OUTCFG13_OUTCFG54_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72085   TIMER_OUTCFG13_OUTCFG54_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72086   TIMER_OUTCFG13_OUTCFG54_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72087   TIMER_OUTCFG13_OUTCFG54_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72088   TIMER_OUTCFG13_OUTCFG54_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72089   TIMER_OUTCFG13_OUTCFG54_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72090   TIMER_OUTCFG13_OUTCFG54_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72091   TIMER_OUTCFG13_OUTCFG54_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72092   TIMER_OUTCFG13_OUTCFG54_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72093   TIMER_OUTCFG13_OUTCFG54_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72094   TIMER_OUTCFG13_OUTCFG54_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72095   TIMER_OUTCFG13_OUTCFG54_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72096   TIMER_OUTCFG13_OUTCFG54_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72097   TIMER_OUTCFG13_OUTCFG54_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72098   TIMER_OUTCFG13_OUTCFG54_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72099   TIMER_OUTCFG13_OUTCFG54_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72100   TIMER_OUTCFG13_OUTCFG54_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72101   TIMER_OUTCFG13_OUTCFG54_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72102   TIMER_OUTCFG13_OUTCFG54_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72103   TIMER_OUTCFG13_OUTCFG54_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72104   TIMER_OUTCFG13_OUTCFG54_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72105   TIMER_OUTCFG13_OUTCFG54_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72106   TIMER_OUTCFG13_OUTCFG54_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72107   TIMER_OUTCFG13_OUTCFG54_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72108   TIMER_OUTCFG13_OUTCFG54_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72109   TIMER_OUTCFG13_OUTCFG54_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72110   TIMER_OUTCFG13_OUTCFG54_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72111 } TIMER_OUTCFG13_OUTCFG54_Enum;
72112 
72113 /* ============================================  TIMER OUTCFG13 OUTCFG53 [8..13]  ============================================ */
72114 typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG53                                                   */
72115   TIMER_OUTCFG13_OUTCFG53_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72116   TIMER_OUTCFG13_OUTCFG53_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72117   TIMER_OUTCFG13_OUTCFG53_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72118   TIMER_OUTCFG13_OUTCFG53_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72119   TIMER_OUTCFG13_OUTCFG53_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72120   TIMER_OUTCFG13_OUTCFG53_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72121   TIMER_OUTCFG13_OUTCFG53_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72122   TIMER_OUTCFG13_OUTCFG53_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72123   TIMER_OUTCFG13_OUTCFG53_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72124   TIMER_OUTCFG13_OUTCFG53_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72125   TIMER_OUTCFG13_OUTCFG53_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72126   TIMER_OUTCFG13_OUTCFG53_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72127   TIMER_OUTCFG13_OUTCFG53_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72128   TIMER_OUTCFG13_OUTCFG53_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72129   TIMER_OUTCFG13_OUTCFG53_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72130   TIMER_OUTCFG13_OUTCFG53_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72131   TIMER_OUTCFG13_OUTCFG53_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72132   TIMER_OUTCFG13_OUTCFG53_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72133   TIMER_OUTCFG13_OUTCFG53_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72134   TIMER_OUTCFG13_OUTCFG53_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72135   TIMER_OUTCFG13_OUTCFG53_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72136   TIMER_OUTCFG13_OUTCFG53_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72137   TIMER_OUTCFG13_OUTCFG53_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72138   TIMER_OUTCFG13_OUTCFG53_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72139   TIMER_OUTCFG13_OUTCFG53_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72140   TIMER_OUTCFG13_OUTCFG53_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72141   TIMER_OUTCFG13_OUTCFG53_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72142   TIMER_OUTCFG13_OUTCFG53_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72143   TIMER_OUTCFG13_OUTCFG53_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72144   TIMER_OUTCFG13_OUTCFG53_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72145   TIMER_OUTCFG13_OUTCFG53_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72146   TIMER_OUTCFG13_OUTCFG53_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72147   TIMER_OUTCFG13_OUTCFG53_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72148   TIMER_OUTCFG13_OUTCFG53_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72149   TIMER_OUTCFG13_OUTCFG53_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72150   TIMER_OUTCFG13_OUTCFG53_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72151   TIMER_OUTCFG13_OUTCFG53_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72152   TIMER_OUTCFG13_OUTCFG53_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72153   TIMER_OUTCFG13_OUTCFG53_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72154   TIMER_OUTCFG13_OUTCFG53_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72155   TIMER_OUTCFG13_OUTCFG53_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72156 } TIMER_OUTCFG13_OUTCFG53_Enum;
72157 
72158 /* ============================================  TIMER OUTCFG13 OUTCFG52 [0..5]  ============================================= */
72159 typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG52                                                   */
72160   TIMER_OUTCFG13_OUTCFG52_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72161   TIMER_OUTCFG13_OUTCFG52_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72162   TIMER_OUTCFG13_OUTCFG52_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72163   TIMER_OUTCFG13_OUTCFG52_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72164   TIMER_OUTCFG13_OUTCFG52_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72165   TIMER_OUTCFG13_OUTCFG52_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72166   TIMER_OUTCFG13_OUTCFG52_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72167   TIMER_OUTCFG13_OUTCFG52_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72168   TIMER_OUTCFG13_OUTCFG52_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72169   TIMER_OUTCFG13_OUTCFG52_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72170   TIMER_OUTCFG13_OUTCFG52_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72171   TIMER_OUTCFG13_OUTCFG52_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72172   TIMER_OUTCFG13_OUTCFG52_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72173   TIMER_OUTCFG13_OUTCFG52_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72174   TIMER_OUTCFG13_OUTCFG52_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72175   TIMER_OUTCFG13_OUTCFG52_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72176   TIMER_OUTCFG13_OUTCFG52_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72177   TIMER_OUTCFG13_OUTCFG52_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72178   TIMER_OUTCFG13_OUTCFG52_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72179   TIMER_OUTCFG13_OUTCFG52_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72180   TIMER_OUTCFG13_OUTCFG52_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72181   TIMER_OUTCFG13_OUTCFG52_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72182   TIMER_OUTCFG13_OUTCFG52_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72183   TIMER_OUTCFG13_OUTCFG52_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72184   TIMER_OUTCFG13_OUTCFG52_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72185   TIMER_OUTCFG13_OUTCFG52_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72186   TIMER_OUTCFG13_OUTCFG52_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72187   TIMER_OUTCFG13_OUTCFG52_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72188   TIMER_OUTCFG13_OUTCFG52_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72189   TIMER_OUTCFG13_OUTCFG52_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72190   TIMER_OUTCFG13_OUTCFG52_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72191   TIMER_OUTCFG13_OUTCFG52_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72192   TIMER_OUTCFG13_OUTCFG52_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72193   TIMER_OUTCFG13_OUTCFG52_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72194   TIMER_OUTCFG13_OUTCFG52_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72195   TIMER_OUTCFG13_OUTCFG52_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72196   TIMER_OUTCFG13_OUTCFG52_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72197   TIMER_OUTCFG13_OUTCFG52_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72198   TIMER_OUTCFG13_OUTCFG52_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72199   TIMER_OUTCFG13_OUTCFG52_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72200   TIMER_OUTCFG13_OUTCFG52_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72201 } TIMER_OUTCFG13_OUTCFG52_Enum;
72202 
72203 /* =======================================================  OUTCFG14  ======================================================== */
72204 /* ===========================================  TIMER OUTCFG14 OUTCFG59 [24..29]  ============================================ */
72205 typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG59                                                   */
72206   TIMER_OUTCFG14_OUTCFG59_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72207   TIMER_OUTCFG14_OUTCFG59_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72208   TIMER_OUTCFG14_OUTCFG59_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72209   TIMER_OUTCFG14_OUTCFG59_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72210   TIMER_OUTCFG14_OUTCFG59_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72211   TIMER_OUTCFG14_OUTCFG59_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72212   TIMER_OUTCFG14_OUTCFG59_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72213   TIMER_OUTCFG14_OUTCFG59_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72214   TIMER_OUTCFG14_OUTCFG59_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72215   TIMER_OUTCFG14_OUTCFG59_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72216   TIMER_OUTCFG14_OUTCFG59_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72217   TIMER_OUTCFG14_OUTCFG59_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72218   TIMER_OUTCFG14_OUTCFG59_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72219   TIMER_OUTCFG14_OUTCFG59_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72220   TIMER_OUTCFG14_OUTCFG59_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72221   TIMER_OUTCFG14_OUTCFG59_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72222   TIMER_OUTCFG14_OUTCFG59_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72223   TIMER_OUTCFG14_OUTCFG59_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72224   TIMER_OUTCFG14_OUTCFG59_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72225   TIMER_OUTCFG14_OUTCFG59_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72226   TIMER_OUTCFG14_OUTCFG59_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72227   TIMER_OUTCFG14_OUTCFG59_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72228   TIMER_OUTCFG14_OUTCFG59_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72229   TIMER_OUTCFG14_OUTCFG59_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72230   TIMER_OUTCFG14_OUTCFG59_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72231   TIMER_OUTCFG14_OUTCFG59_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72232   TIMER_OUTCFG14_OUTCFG59_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72233   TIMER_OUTCFG14_OUTCFG59_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72234   TIMER_OUTCFG14_OUTCFG59_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72235   TIMER_OUTCFG14_OUTCFG59_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72236   TIMER_OUTCFG14_OUTCFG59_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72237   TIMER_OUTCFG14_OUTCFG59_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72238   TIMER_OUTCFG14_OUTCFG59_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72239   TIMER_OUTCFG14_OUTCFG59_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72240   TIMER_OUTCFG14_OUTCFG59_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72241   TIMER_OUTCFG14_OUTCFG59_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72242   TIMER_OUTCFG14_OUTCFG59_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72243   TIMER_OUTCFG14_OUTCFG59_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72244   TIMER_OUTCFG14_OUTCFG59_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72245   TIMER_OUTCFG14_OUTCFG59_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72246   TIMER_OUTCFG14_OUTCFG59_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72247 } TIMER_OUTCFG14_OUTCFG59_Enum;
72248 
72249 /* ===========================================  TIMER OUTCFG14 OUTCFG58 [16..21]  ============================================ */
72250 typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG58                                                   */
72251   TIMER_OUTCFG14_OUTCFG58_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72252   TIMER_OUTCFG14_OUTCFG58_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72253   TIMER_OUTCFG14_OUTCFG58_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72254   TIMER_OUTCFG14_OUTCFG58_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72255   TIMER_OUTCFG14_OUTCFG58_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72256   TIMER_OUTCFG14_OUTCFG58_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72257   TIMER_OUTCFG14_OUTCFG58_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72258   TIMER_OUTCFG14_OUTCFG58_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72259   TIMER_OUTCFG14_OUTCFG58_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72260   TIMER_OUTCFG14_OUTCFG58_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72261   TIMER_OUTCFG14_OUTCFG58_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72262   TIMER_OUTCFG14_OUTCFG58_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72263   TIMER_OUTCFG14_OUTCFG58_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72264   TIMER_OUTCFG14_OUTCFG58_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72265   TIMER_OUTCFG14_OUTCFG58_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72266   TIMER_OUTCFG14_OUTCFG58_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72267   TIMER_OUTCFG14_OUTCFG58_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72268   TIMER_OUTCFG14_OUTCFG58_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72269   TIMER_OUTCFG14_OUTCFG58_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72270   TIMER_OUTCFG14_OUTCFG58_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72271   TIMER_OUTCFG14_OUTCFG58_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72272   TIMER_OUTCFG14_OUTCFG58_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72273   TIMER_OUTCFG14_OUTCFG58_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72274   TIMER_OUTCFG14_OUTCFG58_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72275   TIMER_OUTCFG14_OUTCFG58_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72276   TIMER_OUTCFG14_OUTCFG58_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72277   TIMER_OUTCFG14_OUTCFG58_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72278   TIMER_OUTCFG14_OUTCFG58_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72279   TIMER_OUTCFG14_OUTCFG58_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72280   TIMER_OUTCFG14_OUTCFG58_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72281   TIMER_OUTCFG14_OUTCFG58_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72282   TIMER_OUTCFG14_OUTCFG58_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72283   TIMER_OUTCFG14_OUTCFG58_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72284   TIMER_OUTCFG14_OUTCFG58_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72285   TIMER_OUTCFG14_OUTCFG58_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72286   TIMER_OUTCFG14_OUTCFG58_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72287   TIMER_OUTCFG14_OUTCFG58_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72288   TIMER_OUTCFG14_OUTCFG58_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72289   TIMER_OUTCFG14_OUTCFG58_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72290   TIMER_OUTCFG14_OUTCFG58_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72291   TIMER_OUTCFG14_OUTCFG58_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72292 } TIMER_OUTCFG14_OUTCFG58_Enum;
72293 
72294 /* ============================================  TIMER OUTCFG14 OUTCFG57 [8..13]  ============================================ */
72295 typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG57                                                   */
72296   TIMER_OUTCFG14_OUTCFG57_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72297   TIMER_OUTCFG14_OUTCFG57_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72298   TIMER_OUTCFG14_OUTCFG57_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72299   TIMER_OUTCFG14_OUTCFG57_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72300   TIMER_OUTCFG14_OUTCFG57_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72301   TIMER_OUTCFG14_OUTCFG57_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72302   TIMER_OUTCFG14_OUTCFG57_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72303   TIMER_OUTCFG14_OUTCFG57_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72304   TIMER_OUTCFG14_OUTCFG57_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72305   TIMER_OUTCFG14_OUTCFG57_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72306   TIMER_OUTCFG14_OUTCFG57_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72307   TIMER_OUTCFG14_OUTCFG57_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72308   TIMER_OUTCFG14_OUTCFG57_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72309   TIMER_OUTCFG14_OUTCFG57_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72310   TIMER_OUTCFG14_OUTCFG57_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72311   TIMER_OUTCFG14_OUTCFG57_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72312   TIMER_OUTCFG14_OUTCFG57_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72313   TIMER_OUTCFG14_OUTCFG57_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72314   TIMER_OUTCFG14_OUTCFG57_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72315   TIMER_OUTCFG14_OUTCFG57_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72316   TIMER_OUTCFG14_OUTCFG57_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72317   TIMER_OUTCFG14_OUTCFG57_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72318   TIMER_OUTCFG14_OUTCFG57_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72319   TIMER_OUTCFG14_OUTCFG57_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72320   TIMER_OUTCFG14_OUTCFG57_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72321   TIMER_OUTCFG14_OUTCFG57_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72322   TIMER_OUTCFG14_OUTCFG57_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72323   TIMER_OUTCFG14_OUTCFG57_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72324   TIMER_OUTCFG14_OUTCFG57_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72325   TIMER_OUTCFG14_OUTCFG57_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72326   TIMER_OUTCFG14_OUTCFG57_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72327   TIMER_OUTCFG14_OUTCFG57_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72328   TIMER_OUTCFG14_OUTCFG57_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72329   TIMER_OUTCFG14_OUTCFG57_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72330   TIMER_OUTCFG14_OUTCFG57_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72331   TIMER_OUTCFG14_OUTCFG57_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72332   TIMER_OUTCFG14_OUTCFG57_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72333   TIMER_OUTCFG14_OUTCFG57_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72334   TIMER_OUTCFG14_OUTCFG57_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72335   TIMER_OUTCFG14_OUTCFG57_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72336   TIMER_OUTCFG14_OUTCFG57_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72337 } TIMER_OUTCFG14_OUTCFG57_Enum;
72338 
72339 /* ============================================  TIMER OUTCFG14 OUTCFG56 [0..5]  ============================================= */
72340 typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG56                                                   */
72341   TIMER_OUTCFG14_OUTCFG56_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72342   TIMER_OUTCFG14_OUTCFG56_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72343   TIMER_OUTCFG14_OUTCFG56_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72344   TIMER_OUTCFG14_OUTCFG56_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72345   TIMER_OUTCFG14_OUTCFG56_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72346   TIMER_OUTCFG14_OUTCFG56_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72347   TIMER_OUTCFG14_OUTCFG56_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72348   TIMER_OUTCFG14_OUTCFG56_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72349   TIMER_OUTCFG14_OUTCFG56_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72350   TIMER_OUTCFG14_OUTCFG56_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72351   TIMER_OUTCFG14_OUTCFG56_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72352   TIMER_OUTCFG14_OUTCFG56_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72353   TIMER_OUTCFG14_OUTCFG56_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72354   TIMER_OUTCFG14_OUTCFG56_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72355   TIMER_OUTCFG14_OUTCFG56_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72356   TIMER_OUTCFG14_OUTCFG56_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72357   TIMER_OUTCFG14_OUTCFG56_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72358   TIMER_OUTCFG14_OUTCFG56_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72359   TIMER_OUTCFG14_OUTCFG56_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72360   TIMER_OUTCFG14_OUTCFG56_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72361   TIMER_OUTCFG14_OUTCFG56_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72362   TIMER_OUTCFG14_OUTCFG56_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72363   TIMER_OUTCFG14_OUTCFG56_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72364   TIMER_OUTCFG14_OUTCFG56_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72365   TIMER_OUTCFG14_OUTCFG56_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72366   TIMER_OUTCFG14_OUTCFG56_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72367   TIMER_OUTCFG14_OUTCFG56_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72368   TIMER_OUTCFG14_OUTCFG56_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72369   TIMER_OUTCFG14_OUTCFG56_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72370   TIMER_OUTCFG14_OUTCFG56_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72371   TIMER_OUTCFG14_OUTCFG56_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72372   TIMER_OUTCFG14_OUTCFG56_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72373   TIMER_OUTCFG14_OUTCFG56_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72374   TIMER_OUTCFG14_OUTCFG56_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72375   TIMER_OUTCFG14_OUTCFG56_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72376   TIMER_OUTCFG14_OUTCFG56_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72377   TIMER_OUTCFG14_OUTCFG56_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72378   TIMER_OUTCFG14_OUTCFG56_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72379   TIMER_OUTCFG14_OUTCFG56_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72380   TIMER_OUTCFG14_OUTCFG56_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72381   TIMER_OUTCFG14_OUTCFG56_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72382 } TIMER_OUTCFG14_OUTCFG56_Enum;
72383 
72384 /* =======================================================  OUTCFG15  ======================================================== */
72385 /* ===========================================  TIMER OUTCFG15 OUTCFG63 [24..29]  ============================================ */
72386 typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG63                                                   */
72387   TIMER_OUTCFG15_OUTCFG63_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72388   TIMER_OUTCFG15_OUTCFG63_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72389   TIMER_OUTCFG15_OUTCFG63_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72390   TIMER_OUTCFG15_OUTCFG63_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72391   TIMER_OUTCFG15_OUTCFG63_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72392   TIMER_OUTCFG15_OUTCFG63_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72393   TIMER_OUTCFG15_OUTCFG63_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72394   TIMER_OUTCFG15_OUTCFG63_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72395   TIMER_OUTCFG15_OUTCFG63_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72396   TIMER_OUTCFG15_OUTCFG63_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72397   TIMER_OUTCFG15_OUTCFG63_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72398   TIMER_OUTCFG15_OUTCFG63_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72399   TIMER_OUTCFG15_OUTCFG63_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72400   TIMER_OUTCFG15_OUTCFG63_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72401   TIMER_OUTCFG15_OUTCFG63_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72402   TIMER_OUTCFG15_OUTCFG63_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72403   TIMER_OUTCFG15_OUTCFG63_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72404   TIMER_OUTCFG15_OUTCFG63_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72405   TIMER_OUTCFG15_OUTCFG63_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72406   TIMER_OUTCFG15_OUTCFG63_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72407   TIMER_OUTCFG15_OUTCFG63_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72408   TIMER_OUTCFG15_OUTCFG63_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72409   TIMER_OUTCFG15_OUTCFG63_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72410   TIMER_OUTCFG15_OUTCFG63_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72411   TIMER_OUTCFG15_OUTCFG63_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72412   TIMER_OUTCFG15_OUTCFG63_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72413   TIMER_OUTCFG15_OUTCFG63_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72414   TIMER_OUTCFG15_OUTCFG63_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72415   TIMER_OUTCFG15_OUTCFG63_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72416   TIMER_OUTCFG15_OUTCFG63_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72417   TIMER_OUTCFG15_OUTCFG63_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72418   TIMER_OUTCFG15_OUTCFG63_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72419   TIMER_OUTCFG15_OUTCFG63_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72420   TIMER_OUTCFG15_OUTCFG63_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72421   TIMER_OUTCFG15_OUTCFG63_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72422   TIMER_OUTCFG15_OUTCFG63_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72423   TIMER_OUTCFG15_OUTCFG63_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72424   TIMER_OUTCFG15_OUTCFG63_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72425   TIMER_OUTCFG15_OUTCFG63_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72426   TIMER_OUTCFG15_OUTCFG63_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72427   TIMER_OUTCFG15_OUTCFG63_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72428 } TIMER_OUTCFG15_OUTCFG63_Enum;
72429 
72430 /* ===========================================  TIMER OUTCFG15 OUTCFG62 [16..21]  ============================================ */
72431 typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG62                                                   */
72432   TIMER_OUTCFG15_OUTCFG62_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72433   TIMER_OUTCFG15_OUTCFG62_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72434   TIMER_OUTCFG15_OUTCFG62_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72435   TIMER_OUTCFG15_OUTCFG62_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72436   TIMER_OUTCFG15_OUTCFG62_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72437   TIMER_OUTCFG15_OUTCFG62_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72438   TIMER_OUTCFG15_OUTCFG62_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72439   TIMER_OUTCFG15_OUTCFG62_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72440   TIMER_OUTCFG15_OUTCFG62_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72441   TIMER_OUTCFG15_OUTCFG62_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72442   TIMER_OUTCFG15_OUTCFG62_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72443   TIMER_OUTCFG15_OUTCFG62_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72444   TIMER_OUTCFG15_OUTCFG62_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72445   TIMER_OUTCFG15_OUTCFG62_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72446   TIMER_OUTCFG15_OUTCFG62_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72447   TIMER_OUTCFG15_OUTCFG62_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72448   TIMER_OUTCFG15_OUTCFG62_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72449   TIMER_OUTCFG15_OUTCFG62_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72450   TIMER_OUTCFG15_OUTCFG62_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72451   TIMER_OUTCFG15_OUTCFG62_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72452   TIMER_OUTCFG15_OUTCFG62_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72453   TIMER_OUTCFG15_OUTCFG62_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72454   TIMER_OUTCFG15_OUTCFG62_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72455   TIMER_OUTCFG15_OUTCFG62_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72456   TIMER_OUTCFG15_OUTCFG62_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72457   TIMER_OUTCFG15_OUTCFG62_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72458   TIMER_OUTCFG15_OUTCFG62_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72459   TIMER_OUTCFG15_OUTCFG62_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72460   TIMER_OUTCFG15_OUTCFG62_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72461   TIMER_OUTCFG15_OUTCFG62_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72462   TIMER_OUTCFG15_OUTCFG62_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72463   TIMER_OUTCFG15_OUTCFG62_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72464   TIMER_OUTCFG15_OUTCFG62_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72465   TIMER_OUTCFG15_OUTCFG62_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72466   TIMER_OUTCFG15_OUTCFG62_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72467   TIMER_OUTCFG15_OUTCFG62_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72468   TIMER_OUTCFG15_OUTCFG62_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72469   TIMER_OUTCFG15_OUTCFG62_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72470   TIMER_OUTCFG15_OUTCFG62_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72471   TIMER_OUTCFG15_OUTCFG62_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72472   TIMER_OUTCFG15_OUTCFG62_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72473 } TIMER_OUTCFG15_OUTCFG62_Enum;
72474 
72475 /* ============================================  TIMER OUTCFG15 OUTCFG61 [8..13]  ============================================ */
72476 typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG61                                                   */
72477   TIMER_OUTCFG15_OUTCFG61_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72478   TIMER_OUTCFG15_OUTCFG61_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72479   TIMER_OUTCFG15_OUTCFG61_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72480   TIMER_OUTCFG15_OUTCFG61_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72481   TIMER_OUTCFG15_OUTCFG61_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72482   TIMER_OUTCFG15_OUTCFG61_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72483   TIMER_OUTCFG15_OUTCFG61_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72484   TIMER_OUTCFG15_OUTCFG61_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72485   TIMER_OUTCFG15_OUTCFG61_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72486   TIMER_OUTCFG15_OUTCFG61_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72487   TIMER_OUTCFG15_OUTCFG61_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72488   TIMER_OUTCFG15_OUTCFG61_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72489   TIMER_OUTCFG15_OUTCFG61_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72490   TIMER_OUTCFG15_OUTCFG61_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72491   TIMER_OUTCFG15_OUTCFG61_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72492   TIMER_OUTCFG15_OUTCFG61_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72493   TIMER_OUTCFG15_OUTCFG61_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72494   TIMER_OUTCFG15_OUTCFG61_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72495   TIMER_OUTCFG15_OUTCFG61_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72496   TIMER_OUTCFG15_OUTCFG61_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72497   TIMER_OUTCFG15_OUTCFG61_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72498   TIMER_OUTCFG15_OUTCFG61_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72499   TIMER_OUTCFG15_OUTCFG61_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72500   TIMER_OUTCFG15_OUTCFG61_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72501   TIMER_OUTCFG15_OUTCFG61_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72502   TIMER_OUTCFG15_OUTCFG61_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72503   TIMER_OUTCFG15_OUTCFG61_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72504   TIMER_OUTCFG15_OUTCFG61_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72505   TIMER_OUTCFG15_OUTCFG61_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72506   TIMER_OUTCFG15_OUTCFG61_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72507   TIMER_OUTCFG15_OUTCFG61_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72508   TIMER_OUTCFG15_OUTCFG61_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72509   TIMER_OUTCFG15_OUTCFG61_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72510   TIMER_OUTCFG15_OUTCFG61_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72511   TIMER_OUTCFG15_OUTCFG61_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72512   TIMER_OUTCFG15_OUTCFG61_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72513   TIMER_OUTCFG15_OUTCFG61_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72514   TIMER_OUTCFG15_OUTCFG61_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72515   TIMER_OUTCFG15_OUTCFG61_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72516   TIMER_OUTCFG15_OUTCFG61_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72517   TIMER_OUTCFG15_OUTCFG61_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72518 } TIMER_OUTCFG15_OUTCFG61_Enum;
72519 
72520 /* ============================================  TIMER OUTCFG15 OUTCFG60 [0..5]  ============================================= */
72521 typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG60                                                   */
72522   TIMER_OUTCFG15_OUTCFG60_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72523   TIMER_OUTCFG15_OUTCFG60_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72524   TIMER_OUTCFG15_OUTCFG60_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72525   TIMER_OUTCFG15_OUTCFG60_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72526   TIMER_OUTCFG15_OUTCFG60_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72527   TIMER_OUTCFG15_OUTCFG60_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72528   TIMER_OUTCFG15_OUTCFG60_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72529   TIMER_OUTCFG15_OUTCFG60_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72530   TIMER_OUTCFG15_OUTCFG60_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72531   TIMER_OUTCFG15_OUTCFG60_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72532   TIMER_OUTCFG15_OUTCFG60_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72533   TIMER_OUTCFG15_OUTCFG60_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72534   TIMER_OUTCFG15_OUTCFG60_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72535   TIMER_OUTCFG15_OUTCFG60_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72536   TIMER_OUTCFG15_OUTCFG60_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72537   TIMER_OUTCFG15_OUTCFG60_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72538   TIMER_OUTCFG15_OUTCFG60_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72539   TIMER_OUTCFG15_OUTCFG60_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72540   TIMER_OUTCFG15_OUTCFG60_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72541   TIMER_OUTCFG15_OUTCFG60_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72542   TIMER_OUTCFG15_OUTCFG60_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72543   TIMER_OUTCFG15_OUTCFG60_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72544   TIMER_OUTCFG15_OUTCFG60_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72545   TIMER_OUTCFG15_OUTCFG60_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72546   TIMER_OUTCFG15_OUTCFG60_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72547   TIMER_OUTCFG15_OUTCFG60_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72548   TIMER_OUTCFG15_OUTCFG60_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72549   TIMER_OUTCFG15_OUTCFG60_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72550   TIMER_OUTCFG15_OUTCFG60_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72551   TIMER_OUTCFG15_OUTCFG60_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72552   TIMER_OUTCFG15_OUTCFG60_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72553   TIMER_OUTCFG15_OUTCFG60_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72554   TIMER_OUTCFG15_OUTCFG60_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72555   TIMER_OUTCFG15_OUTCFG60_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72556   TIMER_OUTCFG15_OUTCFG60_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72557   TIMER_OUTCFG15_OUTCFG60_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72558   TIMER_OUTCFG15_OUTCFG60_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72559   TIMER_OUTCFG15_OUTCFG60_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72560   TIMER_OUTCFG15_OUTCFG60_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72561   TIMER_OUTCFG15_OUTCFG60_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72562   TIMER_OUTCFG15_OUTCFG60_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72563 } TIMER_OUTCFG15_OUTCFG60_Enum;
72564 
72565 /* =======================================================  OUTCFG16  ======================================================== */
72566 /* ===========================================  TIMER OUTCFG16 OUTCFG67 [24..29]  ============================================ */
72567 typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG67                                                   */
72568   TIMER_OUTCFG16_OUTCFG67_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72569   TIMER_OUTCFG16_OUTCFG67_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72570   TIMER_OUTCFG16_OUTCFG67_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72571   TIMER_OUTCFG16_OUTCFG67_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72572   TIMER_OUTCFG16_OUTCFG67_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72573   TIMER_OUTCFG16_OUTCFG67_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72574   TIMER_OUTCFG16_OUTCFG67_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72575   TIMER_OUTCFG16_OUTCFG67_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72576   TIMER_OUTCFG16_OUTCFG67_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72577   TIMER_OUTCFG16_OUTCFG67_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72578   TIMER_OUTCFG16_OUTCFG67_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72579   TIMER_OUTCFG16_OUTCFG67_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72580   TIMER_OUTCFG16_OUTCFG67_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72581   TIMER_OUTCFG16_OUTCFG67_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72582   TIMER_OUTCFG16_OUTCFG67_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72583   TIMER_OUTCFG16_OUTCFG67_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72584   TIMER_OUTCFG16_OUTCFG67_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72585   TIMER_OUTCFG16_OUTCFG67_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72586   TIMER_OUTCFG16_OUTCFG67_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72587   TIMER_OUTCFG16_OUTCFG67_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72588   TIMER_OUTCFG16_OUTCFG67_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72589   TIMER_OUTCFG16_OUTCFG67_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72590   TIMER_OUTCFG16_OUTCFG67_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72591   TIMER_OUTCFG16_OUTCFG67_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72592   TIMER_OUTCFG16_OUTCFG67_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72593   TIMER_OUTCFG16_OUTCFG67_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72594   TIMER_OUTCFG16_OUTCFG67_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72595   TIMER_OUTCFG16_OUTCFG67_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72596   TIMER_OUTCFG16_OUTCFG67_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72597   TIMER_OUTCFG16_OUTCFG67_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72598   TIMER_OUTCFG16_OUTCFG67_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72599   TIMER_OUTCFG16_OUTCFG67_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72600   TIMER_OUTCFG16_OUTCFG67_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72601   TIMER_OUTCFG16_OUTCFG67_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72602   TIMER_OUTCFG16_OUTCFG67_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72603   TIMER_OUTCFG16_OUTCFG67_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72604   TIMER_OUTCFG16_OUTCFG67_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72605   TIMER_OUTCFG16_OUTCFG67_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72606   TIMER_OUTCFG16_OUTCFG67_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72607   TIMER_OUTCFG16_OUTCFG67_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72608   TIMER_OUTCFG16_OUTCFG67_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72609 } TIMER_OUTCFG16_OUTCFG67_Enum;
72610 
72611 /* ===========================================  TIMER OUTCFG16 OUTCFG66 [16..21]  ============================================ */
72612 typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG66                                                   */
72613   TIMER_OUTCFG16_OUTCFG66_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72614   TIMER_OUTCFG16_OUTCFG66_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72615   TIMER_OUTCFG16_OUTCFG66_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72616   TIMER_OUTCFG16_OUTCFG66_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72617   TIMER_OUTCFG16_OUTCFG66_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72618   TIMER_OUTCFG16_OUTCFG66_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72619   TIMER_OUTCFG16_OUTCFG66_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72620   TIMER_OUTCFG16_OUTCFG66_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72621   TIMER_OUTCFG16_OUTCFG66_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72622   TIMER_OUTCFG16_OUTCFG66_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72623   TIMER_OUTCFG16_OUTCFG66_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72624   TIMER_OUTCFG16_OUTCFG66_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72625   TIMER_OUTCFG16_OUTCFG66_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72626   TIMER_OUTCFG16_OUTCFG66_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72627   TIMER_OUTCFG16_OUTCFG66_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72628   TIMER_OUTCFG16_OUTCFG66_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72629   TIMER_OUTCFG16_OUTCFG66_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72630   TIMER_OUTCFG16_OUTCFG66_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72631   TIMER_OUTCFG16_OUTCFG66_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72632   TIMER_OUTCFG16_OUTCFG66_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72633   TIMER_OUTCFG16_OUTCFG66_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72634   TIMER_OUTCFG16_OUTCFG66_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72635   TIMER_OUTCFG16_OUTCFG66_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72636   TIMER_OUTCFG16_OUTCFG66_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72637   TIMER_OUTCFG16_OUTCFG66_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72638   TIMER_OUTCFG16_OUTCFG66_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72639   TIMER_OUTCFG16_OUTCFG66_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72640   TIMER_OUTCFG16_OUTCFG66_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72641   TIMER_OUTCFG16_OUTCFG66_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72642   TIMER_OUTCFG16_OUTCFG66_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72643   TIMER_OUTCFG16_OUTCFG66_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72644   TIMER_OUTCFG16_OUTCFG66_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72645   TIMER_OUTCFG16_OUTCFG66_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72646   TIMER_OUTCFG16_OUTCFG66_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72647   TIMER_OUTCFG16_OUTCFG66_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72648   TIMER_OUTCFG16_OUTCFG66_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72649   TIMER_OUTCFG16_OUTCFG66_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72650   TIMER_OUTCFG16_OUTCFG66_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72651   TIMER_OUTCFG16_OUTCFG66_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72652   TIMER_OUTCFG16_OUTCFG66_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72653   TIMER_OUTCFG16_OUTCFG66_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72654 } TIMER_OUTCFG16_OUTCFG66_Enum;
72655 
72656 /* ============================================  TIMER OUTCFG16 OUTCFG65 [8..13]  ============================================ */
72657 typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG65                                                   */
72658   TIMER_OUTCFG16_OUTCFG65_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72659   TIMER_OUTCFG16_OUTCFG65_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72660   TIMER_OUTCFG16_OUTCFG65_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72661   TIMER_OUTCFG16_OUTCFG65_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72662   TIMER_OUTCFG16_OUTCFG65_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72663   TIMER_OUTCFG16_OUTCFG65_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72664   TIMER_OUTCFG16_OUTCFG65_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72665   TIMER_OUTCFG16_OUTCFG65_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72666   TIMER_OUTCFG16_OUTCFG65_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72667   TIMER_OUTCFG16_OUTCFG65_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72668   TIMER_OUTCFG16_OUTCFG65_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72669   TIMER_OUTCFG16_OUTCFG65_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72670   TIMER_OUTCFG16_OUTCFG65_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72671   TIMER_OUTCFG16_OUTCFG65_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72672   TIMER_OUTCFG16_OUTCFG65_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72673   TIMER_OUTCFG16_OUTCFG65_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72674   TIMER_OUTCFG16_OUTCFG65_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72675   TIMER_OUTCFG16_OUTCFG65_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72676   TIMER_OUTCFG16_OUTCFG65_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72677   TIMER_OUTCFG16_OUTCFG65_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72678   TIMER_OUTCFG16_OUTCFG65_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72679   TIMER_OUTCFG16_OUTCFG65_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72680   TIMER_OUTCFG16_OUTCFG65_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72681   TIMER_OUTCFG16_OUTCFG65_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72682   TIMER_OUTCFG16_OUTCFG65_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72683   TIMER_OUTCFG16_OUTCFG65_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72684   TIMER_OUTCFG16_OUTCFG65_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72685   TIMER_OUTCFG16_OUTCFG65_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72686   TIMER_OUTCFG16_OUTCFG65_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72687   TIMER_OUTCFG16_OUTCFG65_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72688   TIMER_OUTCFG16_OUTCFG65_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72689   TIMER_OUTCFG16_OUTCFG65_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72690   TIMER_OUTCFG16_OUTCFG65_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72691   TIMER_OUTCFG16_OUTCFG65_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72692   TIMER_OUTCFG16_OUTCFG65_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72693   TIMER_OUTCFG16_OUTCFG65_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72694   TIMER_OUTCFG16_OUTCFG65_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72695   TIMER_OUTCFG16_OUTCFG65_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72696   TIMER_OUTCFG16_OUTCFG65_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72697   TIMER_OUTCFG16_OUTCFG65_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72698   TIMER_OUTCFG16_OUTCFG65_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72699 } TIMER_OUTCFG16_OUTCFG65_Enum;
72700 
72701 /* ============================================  TIMER OUTCFG16 OUTCFG64 [0..5]  ============================================= */
72702 typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG64                                                   */
72703   TIMER_OUTCFG16_OUTCFG64_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72704   TIMER_OUTCFG16_OUTCFG64_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72705   TIMER_OUTCFG16_OUTCFG64_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72706   TIMER_OUTCFG16_OUTCFG64_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72707   TIMER_OUTCFG16_OUTCFG64_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72708   TIMER_OUTCFG16_OUTCFG64_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72709   TIMER_OUTCFG16_OUTCFG64_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72710   TIMER_OUTCFG16_OUTCFG64_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72711   TIMER_OUTCFG16_OUTCFG64_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72712   TIMER_OUTCFG16_OUTCFG64_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72713   TIMER_OUTCFG16_OUTCFG64_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72714   TIMER_OUTCFG16_OUTCFG64_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72715   TIMER_OUTCFG16_OUTCFG64_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72716   TIMER_OUTCFG16_OUTCFG64_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72717   TIMER_OUTCFG16_OUTCFG64_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72718   TIMER_OUTCFG16_OUTCFG64_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72719   TIMER_OUTCFG16_OUTCFG64_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72720   TIMER_OUTCFG16_OUTCFG64_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72721   TIMER_OUTCFG16_OUTCFG64_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72722   TIMER_OUTCFG16_OUTCFG64_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72723   TIMER_OUTCFG16_OUTCFG64_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72724   TIMER_OUTCFG16_OUTCFG64_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72725   TIMER_OUTCFG16_OUTCFG64_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72726   TIMER_OUTCFG16_OUTCFG64_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72727   TIMER_OUTCFG16_OUTCFG64_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72728   TIMER_OUTCFG16_OUTCFG64_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72729   TIMER_OUTCFG16_OUTCFG64_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72730   TIMER_OUTCFG16_OUTCFG64_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72731   TIMER_OUTCFG16_OUTCFG64_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72732   TIMER_OUTCFG16_OUTCFG64_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72733   TIMER_OUTCFG16_OUTCFG64_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72734   TIMER_OUTCFG16_OUTCFG64_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72735   TIMER_OUTCFG16_OUTCFG64_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72736   TIMER_OUTCFG16_OUTCFG64_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72737   TIMER_OUTCFG16_OUTCFG64_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72738   TIMER_OUTCFG16_OUTCFG64_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72739   TIMER_OUTCFG16_OUTCFG64_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72740   TIMER_OUTCFG16_OUTCFG64_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72741   TIMER_OUTCFG16_OUTCFG64_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72742   TIMER_OUTCFG16_OUTCFG64_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72743   TIMER_OUTCFG16_OUTCFG64_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72744 } TIMER_OUTCFG16_OUTCFG64_Enum;
72745 
72746 /* =======================================================  OUTCFG17  ======================================================== */
72747 /* ===========================================  TIMER OUTCFG17 OUTCFG71 [24..29]  ============================================ */
72748 typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG71                                                   */
72749   TIMER_OUTCFG17_OUTCFG71_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72750   TIMER_OUTCFG17_OUTCFG71_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72751   TIMER_OUTCFG17_OUTCFG71_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72752   TIMER_OUTCFG17_OUTCFG71_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72753   TIMER_OUTCFG17_OUTCFG71_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72754   TIMER_OUTCFG17_OUTCFG71_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72755   TIMER_OUTCFG17_OUTCFG71_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72756   TIMER_OUTCFG17_OUTCFG71_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72757   TIMER_OUTCFG17_OUTCFG71_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72758   TIMER_OUTCFG17_OUTCFG71_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72759   TIMER_OUTCFG17_OUTCFG71_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72760   TIMER_OUTCFG17_OUTCFG71_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72761   TIMER_OUTCFG17_OUTCFG71_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72762   TIMER_OUTCFG17_OUTCFG71_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72763   TIMER_OUTCFG17_OUTCFG71_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72764   TIMER_OUTCFG17_OUTCFG71_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72765   TIMER_OUTCFG17_OUTCFG71_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72766   TIMER_OUTCFG17_OUTCFG71_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72767   TIMER_OUTCFG17_OUTCFG71_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72768   TIMER_OUTCFG17_OUTCFG71_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72769   TIMER_OUTCFG17_OUTCFG71_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72770   TIMER_OUTCFG17_OUTCFG71_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72771   TIMER_OUTCFG17_OUTCFG71_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72772   TIMER_OUTCFG17_OUTCFG71_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72773   TIMER_OUTCFG17_OUTCFG71_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72774   TIMER_OUTCFG17_OUTCFG71_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72775   TIMER_OUTCFG17_OUTCFG71_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72776   TIMER_OUTCFG17_OUTCFG71_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72777   TIMER_OUTCFG17_OUTCFG71_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72778   TIMER_OUTCFG17_OUTCFG71_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72779   TIMER_OUTCFG17_OUTCFG71_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72780   TIMER_OUTCFG17_OUTCFG71_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72781   TIMER_OUTCFG17_OUTCFG71_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72782   TIMER_OUTCFG17_OUTCFG71_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72783   TIMER_OUTCFG17_OUTCFG71_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72784   TIMER_OUTCFG17_OUTCFG71_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72785   TIMER_OUTCFG17_OUTCFG71_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72786   TIMER_OUTCFG17_OUTCFG71_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72787   TIMER_OUTCFG17_OUTCFG71_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72788   TIMER_OUTCFG17_OUTCFG71_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72789   TIMER_OUTCFG17_OUTCFG71_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72790 } TIMER_OUTCFG17_OUTCFG71_Enum;
72791 
72792 /* ===========================================  TIMER OUTCFG17 OUTCFG70 [16..21]  ============================================ */
72793 typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG70                                                   */
72794   TIMER_OUTCFG17_OUTCFG70_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72795   TIMER_OUTCFG17_OUTCFG70_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72796   TIMER_OUTCFG17_OUTCFG70_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72797   TIMER_OUTCFG17_OUTCFG70_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72798   TIMER_OUTCFG17_OUTCFG70_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72799   TIMER_OUTCFG17_OUTCFG70_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72800   TIMER_OUTCFG17_OUTCFG70_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72801   TIMER_OUTCFG17_OUTCFG70_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72802   TIMER_OUTCFG17_OUTCFG70_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72803   TIMER_OUTCFG17_OUTCFG70_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72804   TIMER_OUTCFG17_OUTCFG70_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72805   TIMER_OUTCFG17_OUTCFG70_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72806   TIMER_OUTCFG17_OUTCFG70_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72807   TIMER_OUTCFG17_OUTCFG70_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72808   TIMER_OUTCFG17_OUTCFG70_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72809   TIMER_OUTCFG17_OUTCFG70_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72810   TIMER_OUTCFG17_OUTCFG70_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72811   TIMER_OUTCFG17_OUTCFG70_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72812   TIMER_OUTCFG17_OUTCFG70_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72813   TIMER_OUTCFG17_OUTCFG70_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72814   TIMER_OUTCFG17_OUTCFG70_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72815   TIMER_OUTCFG17_OUTCFG70_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72816   TIMER_OUTCFG17_OUTCFG70_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72817   TIMER_OUTCFG17_OUTCFG70_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72818   TIMER_OUTCFG17_OUTCFG70_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72819   TIMER_OUTCFG17_OUTCFG70_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72820   TIMER_OUTCFG17_OUTCFG70_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72821   TIMER_OUTCFG17_OUTCFG70_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72822   TIMER_OUTCFG17_OUTCFG70_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72823   TIMER_OUTCFG17_OUTCFG70_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72824   TIMER_OUTCFG17_OUTCFG70_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72825   TIMER_OUTCFG17_OUTCFG70_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72826   TIMER_OUTCFG17_OUTCFG70_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72827   TIMER_OUTCFG17_OUTCFG70_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72828   TIMER_OUTCFG17_OUTCFG70_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72829   TIMER_OUTCFG17_OUTCFG70_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72830   TIMER_OUTCFG17_OUTCFG70_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72831   TIMER_OUTCFG17_OUTCFG70_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72832   TIMER_OUTCFG17_OUTCFG70_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72833   TIMER_OUTCFG17_OUTCFG70_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72834   TIMER_OUTCFG17_OUTCFG70_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72835 } TIMER_OUTCFG17_OUTCFG70_Enum;
72836 
72837 /* ============================================  TIMER OUTCFG17 OUTCFG69 [8..13]  ============================================ */
72838 typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG69                                                   */
72839   TIMER_OUTCFG17_OUTCFG69_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72840   TIMER_OUTCFG17_OUTCFG69_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72841   TIMER_OUTCFG17_OUTCFG69_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72842   TIMER_OUTCFG17_OUTCFG69_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72843   TIMER_OUTCFG17_OUTCFG69_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72844   TIMER_OUTCFG17_OUTCFG69_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72845   TIMER_OUTCFG17_OUTCFG69_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72846   TIMER_OUTCFG17_OUTCFG69_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72847   TIMER_OUTCFG17_OUTCFG69_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72848   TIMER_OUTCFG17_OUTCFG69_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72849   TIMER_OUTCFG17_OUTCFG69_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72850   TIMER_OUTCFG17_OUTCFG69_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72851   TIMER_OUTCFG17_OUTCFG69_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72852   TIMER_OUTCFG17_OUTCFG69_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72853   TIMER_OUTCFG17_OUTCFG69_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72854   TIMER_OUTCFG17_OUTCFG69_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72855   TIMER_OUTCFG17_OUTCFG69_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72856   TIMER_OUTCFG17_OUTCFG69_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72857   TIMER_OUTCFG17_OUTCFG69_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72858   TIMER_OUTCFG17_OUTCFG69_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72859   TIMER_OUTCFG17_OUTCFG69_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72860   TIMER_OUTCFG17_OUTCFG69_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72861   TIMER_OUTCFG17_OUTCFG69_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72862   TIMER_OUTCFG17_OUTCFG69_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72863   TIMER_OUTCFG17_OUTCFG69_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72864   TIMER_OUTCFG17_OUTCFG69_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72865   TIMER_OUTCFG17_OUTCFG69_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72866   TIMER_OUTCFG17_OUTCFG69_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72867   TIMER_OUTCFG17_OUTCFG69_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72868   TIMER_OUTCFG17_OUTCFG69_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72869   TIMER_OUTCFG17_OUTCFG69_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72870   TIMER_OUTCFG17_OUTCFG69_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72871   TIMER_OUTCFG17_OUTCFG69_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72872   TIMER_OUTCFG17_OUTCFG69_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72873   TIMER_OUTCFG17_OUTCFG69_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72874   TIMER_OUTCFG17_OUTCFG69_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72875   TIMER_OUTCFG17_OUTCFG69_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72876   TIMER_OUTCFG17_OUTCFG69_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72877   TIMER_OUTCFG17_OUTCFG69_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72878   TIMER_OUTCFG17_OUTCFG69_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72879   TIMER_OUTCFG17_OUTCFG69_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72880 } TIMER_OUTCFG17_OUTCFG69_Enum;
72881 
72882 /* ============================================  TIMER OUTCFG17 OUTCFG68 [0..5]  ============================================= */
72883 typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG68                                                   */
72884   TIMER_OUTCFG17_OUTCFG68_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72885   TIMER_OUTCFG17_OUTCFG68_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72886   TIMER_OUTCFG17_OUTCFG68_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72887   TIMER_OUTCFG17_OUTCFG68_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72888   TIMER_OUTCFG17_OUTCFG68_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72889   TIMER_OUTCFG17_OUTCFG68_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72890   TIMER_OUTCFG17_OUTCFG68_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72891   TIMER_OUTCFG17_OUTCFG68_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72892   TIMER_OUTCFG17_OUTCFG68_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72893   TIMER_OUTCFG17_OUTCFG68_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72894   TIMER_OUTCFG17_OUTCFG68_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72895   TIMER_OUTCFG17_OUTCFG68_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72896   TIMER_OUTCFG17_OUTCFG68_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72897   TIMER_OUTCFG17_OUTCFG68_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72898   TIMER_OUTCFG17_OUTCFG68_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72899   TIMER_OUTCFG17_OUTCFG68_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72900   TIMER_OUTCFG17_OUTCFG68_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72901   TIMER_OUTCFG17_OUTCFG68_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72902   TIMER_OUTCFG17_OUTCFG68_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72903   TIMER_OUTCFG17_OUTCFG68_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72904   TIMER_OUTCFG17_OUTCFG68_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72905   TIMER_OUTCFG17_OUTCFG68_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72906   TIMER_OUTCFG17_OUTCFG68_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72907   TIMER_OUTCFG17_OUTCFG68_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72908   TIMER_OUTCFG17_OUTCFG68_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72909   TIMER_OUTCFG17_OUTCFG68_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72910   TIMER_OUTCFG17_OUTCFG68_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72911   TIMER_OUTCFG17_OUTCFG68_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72912   TIMER_OUTCFG17_OUTCFG68_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72913   TIMER_OUTCFG17_OUTCFG68_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72914   TIMER_OUTCFG17_OUTCFG68_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72915   TIMER_OUTCFG17_OUTCFG68_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72916   TIMER_OUTCFG17_OUTCFG68_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72917   TIMER_OUTCFG17_OUTCFG68_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72918   TIMER_OUTCFG17_OUTCFG68_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72919   TIMER_OUTCFG17_OUTCFG68_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72920   TIMER_OUTCFG17_OUTCFG68_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72921   TIMER_OUTCFG17_OUTCFG68_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72922   TIMER_OUTCFG17_OUTCFG68_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72923   TIMER_OUTCFG17_OUTCFG68_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72924   TIMER_OUTCFG17_OUTCFG68_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72925 } TIMER_OUTCFG17_OUTCFG68_Enum;
72926 
72927 /* =======================================================  OUTCFG18  ======================================================== */
72928 /* ===========================================  TIMER OUTCFG18 OUTCFG75 [24..29]  ============================================ */
72929 typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG75                                                   */
72930   TIMER_OUTCFG18_OUTCFG75_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72931   TIMER_OUTCFG18_OUTCFG75_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72932   TIMER_OUTCFG18_OUTCFG75_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72933   TIMER_OUTCFG18_OUTCFG75_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72934   TIMER_OUTCFG18_OUTCFG75_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72935   TIMER_OUTCFG18_OUTCFG75_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72936   TIMER_OUTCFG18_OUTCFG75_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72937   TIMER_OUTCFG18_OUTCFG75_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72938   TIMER_OUTCFG18_OUTCFG75_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72939   TIMER_OUTCFG18_OUTCFG75_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72940   TIMER_OUTCFG18_OUTCFG75_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72941   TIMER_OUTCFG18_OUTCFG75_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72942   TIMER_OUTCFG18_OUTCFG75_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72943   TIMER_OUTCFG18_OUTCFG75_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72944   TIMER_OUTCFG18_OUTCFG75_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72945   TIMER_OUTCFG18_OUTCFG75_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72946   TIMER_OUTCFG18_OUTCFG75_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72947   TIMER_OUTCFG18_OUTCFG75_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72948   TIMER_OUTCFG18_OUTCFG75_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72949   TIMER_OUTCFG18_OUTCFG75_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72950   TIMER_OUTCFG18_OUTCFG75_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72951   TIMER_OUTCFG18_OUTCFG75_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72952   TIMER_OUTCFG18_OUTCFG75_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72953   TIMER_OUTCFG18_OUTCFG75_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72954   TIMER_OUTCFG18_OUTCFG75_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
72955   TIMER_OUTCFG18_OUTCFG75_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
72956   TIMER_OUTCFG18_OUTCFG75_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
72957   TIMER_OUTCFG18_OUTCFG75_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
72958   TIMER_OUTCFG18_OUTCFG75_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
72959   TIMER_OUTCFG18_OUTCFG75_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
72960   TIMER_OUTCFG18_OUTCFG75_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
72961   TIMER_OUTCFG18_OUTCFG75_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
72962   TIMER_OUTCFG18_OUTCFG75_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
72963   TIMER_OUTCFG18_OUTCFG75_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
72964   TIMER_OUTCFG18_OUTCFG75_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
72965   TIMER_OUTCFG18_OUTCFG75_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
72966   TIMER_OUTCFG18_OUTCFG75_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
72967   TIMER_OUTCFG18_OUTCFG75_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
72968   TIMER_OUTCFG18_OUTCFG75_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
72969   TIMER_OUTCFG18_OUTCFG75_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
72970   TIMER_OUTCFG18_OUTCFG75_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
72971 } TIMER_OUTCFG18_OUTCFG75_Enum;
72972 
72973 /* ===========================================  TIMER OUTCFG18 OUTCFG74 [16..21]  ============================================ */
72974 typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG74                                                   */
72975   TIMER_OUTCFG18_OUTCFG74_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
72976   TIMER_OUTCFG18_OUTCFG74_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
72977   TIMER_OUTCFG18_OUTCFG74_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
72978   TIMER_OUTCFG18_OUTCFG74_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
72979   TIMER_OUTCFG18_OUTCFG74_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
72980   TIMER_OUTCFG18_OUTCFG74_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
72981   TIMER_OUTCFG18_OUTCFG74_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
72982   TIMER_OUTCFG18_OUTCFG74_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
72983   TIMER_OUTCFG18_OUTCFG74_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
72984   TIMER_OUTCFG18_OUTCFG74_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
72985   TIMER_OUTCFG18_OUTCFG74_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
72986   TIMER_OUTCFG18_OUTCFG74_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
72987   TIMER_OUTCFG18_OUTCFG74_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
72988   TIMER_OUTCFG18_OUTCFG74_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
72989   TIMER_OUTCFG18_OUTCFG74_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
72990   TIMER_OUTCFG18_OUTCFG74_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
72991   TIMER_OUTCFG18_OUTCFG74_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
72992   TIMER_OUTCFG18_OUTCFG74_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
72993   TIMER_OUTCFG18_OUTCFG74_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
72994   TIMER_OUTCFG18_OUTCFG74_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
72995   TIMER_OUTCFG18_OUTCFG74_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
72996   TIMER_OUTCFG18_OUTCFG74_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
72997   TIMER_OUTCFG18_OUTCFG74_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
72998   TIMER_OUTCFG18_OUTCFG74_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
72999   TIMER_OUTCFG18_OUTCFG74_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73000   TIMER_OUTCFG18_OUTCFG74_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73001   TIMER_OUTCFG18_OUTCFG74_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73002   TIMER_OUTCFG18_OUTCFG74_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73003   TIMER_OUTCFG18_OUTCFG74_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73004   TIMER_OUTCFG18_OUTCFG74_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73005   TIMER_OUTCFG18_OUTCFG74_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73006   TIMER_OUTCFG18_OUTCFG74_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73007   TIMER_OUTCFG18_OUTCFG74_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73008   TIMER_OUTCFG18_OUTCFG74_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73009   TIMER_OUTCFG18_OUTCFG74_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73010   TIMER_OUTCFG18_OUTCFG74_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73011   TIMER_OUTCFG18_OUTCFG74_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73012   TIMER_OUTCFG18_OUTCFG74_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73013   TIMER_OUTCFG18_OUTCFG74_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73014   TIMER_OUTCFG18_OUTCFG74_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73015   TIMER_OUTCFG18_OUTCFG74_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73016 } TIMER_OUTCFG18_OUTCFG74_Enum;
73017 
73018 /* ============================================  TIMER OUTCFG18 OUTCFG73 [8..13]  ============================================ */
73019 typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG73                                                   */
73020   TIMER_OUTCFG18_OUTCFG73_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73021   TIMER_OUTCFG18_OUTCFG73_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73022   TIMER_OUTCFG18_OUTCFG73_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73023   TIMER_OUTCFG18_OUTCFG73_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73024   TIMER_OUTCFG18_OUTCFG73_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73025   TIMER_OUTCFG18_OUTCFG73_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73026   TIMER_OUTCFG18_OUTCFG73_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73027   TIMER_OUTCFG18_OUTCFG73_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73028   TIMER_OUTCFG18_OUTCFG73_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73029   TIMER_OUTCFG18_OUTCFG73_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73030   TIMER_OUTCFG18_OUTCFG73_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73031   TIMER_OUTCFG18_OUTCFG73_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73032   TIMER_OUTCFG18_OUTCFG73_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73033   TIMER_OUTCFG18_OUTCFG73_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73034   TIMER_OUTCFG18_OUTCFG73_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73035   TIMER_OUTCFG18_OUTCFG73_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73036   TIMER_OUTCFG18_OUTCFG73_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73037   TIMER_OUTCFG18_OUTCFG73_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73038   TIMER_OUTCFG18_OUTCFG73_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73039   TIMER_OUTCFG18_OUTCFG73_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73040   TIMER_OUTCFG18_OUTCFG73_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73041   TIMER_OUTCFG18_OUTCFG73_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73042   TIMER_OUTCFG18_OUTCFG73_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73043   TIMER_OUTCFG18_OUTCFG73_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73044   TIMER_OUTCFG18_OUTCFG73_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73045   TIMER_OUTCFG18_OUTCFG73_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73046   TIMER_OUTCFG18_OUTCFG73_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73047   TIMER_OUTCFG18_OUTCFG73_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73048   TIMER_OUTCFG18_OUTCFG73_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73049   TIMER_OUTCFG18_OUTCFG73_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73050   TIMER_OUTCFG18_OUTCFG73_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73051   TIMER_OUTCFG18_OUTCFG73_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73052   TIMER_OUTCFG18_OUTCFG73_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73053   TIMER_OUTCFG18_OUTCFG73_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73054   TIMER_OUTCFG18_OUTCFG73_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73055   TIMER_OUTCFG18_OUTCFG73_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73056   TIMER_OUTCFG18_OUTCFG73_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73057   TIMER_OUTCFG18_OUTCFG73_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73058   TIMER_OUTCFG18_OUTCFG73_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73059   TIMER_OUTCFG18_OUTCFG73_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73060   TIMER_OUTCFG18_OUTCFG73_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73061 } TIMER_OUTCFG18_OUTCFG73_Enum;
73062 
73063 /* ============================================  TIMER OUTCFG18 OUTCFG72 [0..5]  ============================================= */
73064 typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG72                                                   */
73065   TIMER_OUTCFG18_OUTCFG72_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73066   TIMER_OUTCFG18_OUTCFG72_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73067   TIMER_OUTCFG18_OUTCFG72_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73068   TIMER_OUTCFG18_OUTCFG72_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73069   TIMER_OUTCFG18_OUTCFG72_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73070   TIMER_OUTCFG18_OUTCFG72_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73071   TIMER_OUTCFG18_OUTCFG72_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73072   TIMER_OUTCFG18_OUTCFG72_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73073   TIMER_OUTCFG18_OUTCFG72_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73074   TIMER_OUTCFG18_OUTCFG72_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73075   TIMER_OUTCFG18_OUTCFG72_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73076   TIMER_OUTCFG18_OUTCFG72_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73077   TIMER_OUTCFG18_OUTCFG72_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73078   TIMER_OUTCFG18_OUTCFG72_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73079   TIMER_OUTCFG18_OUTCFG72_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73080   TIMER_OUTCFG18_OUTCFG72_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73081   TIMER_OUTCFG18_OUTCFG72_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73082   TIMER_OUTCFG18_OUTCFG72_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73083   TIMER_OUTCFG18_OUTCFG72_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73084   TIMER_OUTCFG18_OUTCFG72_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73085   TIMER_OUTCFG18_OUTCFG72_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73086   TIMER_OUTCFG18_OUTCFG72_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73087   TIMER_OUTCFG18_OUTCFG72_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73088   TIMER_OUTCFG18_OUTCFG72_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73089   TIMER_OUTCFG18_OUTCFG72_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73090   TIMER_OUTCFG18_OUTCFG72_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73091   TIMER_OUTCFG18_OUTCFG72_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73092   TIMER_OUTCFG18_OUTCFG72_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73093   TIMER_OUTCFG18_OUTCFG72_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73094   TIMER_OUTCFG18_OUTCFG72_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73095   TIMER_OUTCFG18_OUTCFG72_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73096   TIMER_OUTCFG18_OUTCFG72_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73097   TIMER_OUTCFG18_OUTCFG72_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73098   TIMER_OUTCFG18_OUTCFG72_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73099   TIMER_OUTCFG18_OUTCFG72_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73100   TIMER_OUTCFG18_OUTCFG72_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73101   TIMER_OUTCFG18_OUTCFG72_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73102   TIMER_OUTCFG18_OUTCFG72_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73103   TIMER_OUTCFG18_OUTCFG72_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73104   TIMER_OUTCFG18_OUTCFG72_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73105   TIMER_OUTCFG18_OUTCFG72_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73106 } TIMER_OUTCFG18_OUTCFG72_Enum;
73107 
73108 /* =======================================================  OUTCFG19  ======================================================== */
73109 /* ===========================================  TIMER OUTCFG19 OUTCFG79 [24..29]  ============================================ */
73110 typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG79                                                   */
73111   TIMER_OUTCFG19_OUTCFG79_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73112   TIMER_OUTCFG19_OUTCFG79_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73113   TIMER_OUTCFG19_OUTCFG79_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73114   TIMER_OUTCFG19_OUTCFG79_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73115   TIMER_OUTCFG19_OUTCFG79_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73116   TIMER_OUTCFG19_OUTCFG79_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73117   TIMER_OUTCFG19_OUTCFG79_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73118   TIMER_OUTCFG19_OUTCFG79_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73119   TIMER_OUTCFG19_OUTCFG79_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73120   TIMER_OUTCFG19_OUTCFG79_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73121   TIMER_OUTCFG19_OUTCFG79_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73122   TIMER_OUTCFG19_OUTCFG79_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73123   TIMER_OUTCFG19_OUTCFG79_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73124   TIMER_OUTCFG19_OUTCFG79_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73125   TIMER_OUTCFG19_OUTCFG79_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73126   TIMER_OUTCFG19_OUTCFG79_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73127   TIMER_OUTCFG19_OUTCFG79_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73128   TIMER_OUTCFG19_OUTCFG79_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73129   TIMER_OUTCFG19_OUTCFG79_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73130   TIMER_OUTCFG19_OUTCFG79_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73131   TIMER_OUTCFG19_OUTCFG79_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73132   TIMER_OUTCFG19_OUTCFG79_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73133   TIMER_OUTCFG19_OUTCFG79_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73134   TIMER_OUTCFG19_OUTCFG79_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73135   TIMER_OUTCFG19_OUTCFG79_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73136   TIMER_OUTCFG19_OUTCFG79_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73137   TIMER_OUTCFG19_OUTCFG79_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73138   TIMER_OUTCFG19_OUTCFG79_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73139   TIMER_OUTCFG19_OUTCFG79_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73140   TIMER_OUTCFG19_OUTCFG79_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73141   TIMER_OUTCFG19_OUTCFG79_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73142   TIMER_OUTCFG19_OUTCFG79_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73143   TIMER_OUTCFG19_OUTCFG79_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73144   TIMER_OUTCFG19_OUTCFG79_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73145   TIMER_OUTCFG19_OUTCFG79_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73146   TIMER_OUTCFG19_OUTCFG79_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73147   TIMER_OUTCFG19_OUTCFG79_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73148   TIMER_OUTCFG19_OUTCFG79_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73149   TIMER_OUTCFG19_OUTCFG79_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73150   TIMER_OUTCFG19_OUTCFG79_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73151   TIMER_OUTCFG19_OUTCFG79_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73152 } TIMER_OUTCFG19_OUTCFG79_Enum;
73153 
73154 /* ===========================================  TIMER OUTCFG19 OUTCFG78 [16..21]  ============================================ */
73155 typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG78                                                   */
73156   TIMER_OUTCFG19_OUTCFG78_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73157   TIMER_OUTCFG19_OUTCFG78_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73158   TIMER_OUTCFG19_OUTCFG78_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73159   TIMER_OUTCFG19_OUTCFG78_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73160   TIMER_OUTCFG19_OUTCFG78_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73161   TIMER_OUTCFG19_OUTCFG78_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73162   TIMER_OUTCFG19_OUTCFG78_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73163   TIMER_OUTCFG19_OUTCFG78_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73164   TIMER_OUTCFG19_OUTCFG78_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73165   TIMER_OUTCFG19_OUTCFG78_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73166   TIMER_OUTCFG19_OUTCFG78_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73167   TIMER_OUTCFG19_OUTCFG78_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73168   TIMER_OUTCFG19_OUTCFG78_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73169   TIMER_OUTCFG19_OUTCFG78_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73170   TIMER_OUTCFG19_OUTCFG78_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73171   TIMER_OUTCFG19_OUTCFG78_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73172   TIMER_OUTCFG19_OUTCFG78_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73173   TIMER_OUTCFG19_OUTCFG78_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73174   TIMER_OUTCFG19_OUTCFG78_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73175   TIMER_OUTCFG19_OUTCFG78_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73176   TIMER_OUTCFG19_OUTCFG78_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73177   TIMER_OUTCFG19_OUTCFG78_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73178   TIMER_OUTCFG19_OUTCFG78_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73179   TIMER_OUTCFG19_OUTCFG78_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73180   TIMER_OUTCFG19_OUTCFG78_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73181   TIMER_OUTCFG19_OUTCFG78_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73182   TIMER_OUTCFG19_OUTCFG78_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73183   TIMER_OUTCFG19_OUTCFG78_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73184   TIMER_OUTCFG19_OUTCFG78_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73185   TIMER_OUTCFG19_OUTCFG78_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73186   TIMER_OUTCFG19_OUTCFG78_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73187   TIMER_OUTCFG19_OUTCFG78_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73188   TIMER_OUTCFG19_OUTCFG78_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73189   TIMER_OUTCFG19_OUTCFG78_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73190   TIMER_OUTCFG19_OUTCFG78_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73191   TIMER_OUTCFG19_OUTCFG78_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73192   TIMER_OUTCFG19_OUTCFG78_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73193   TIMER_OUTCFG19_OUTCFG78_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73194   TIMER_OUTCFG19_OUTCFG78_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73195   TIMER_OUTCFG19_OUTCFG78_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73196   TIMER_OUTCFG19_OUTCFG78_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73197 } TIMER_OUTCFG19_OUTCFG78_Enum;
73198 
73199 /* ============================================  TIMER OUTCFG19 OUTCFG77 [8..13]  ============================================ */
73200 typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG77                                                   */
73201   TIMER_OUTCFG19_OUTCFG77_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73202   TIMER_OUTCFG19_OUTCFG77_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73203   TIMER_OUTCFG19_OUTCFG77_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73204   TIMER_OUTCFG19_OUTCFG77_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73205   TIMER_OUTCFG19_OUTCFG77_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73206   TIMER_OUTCFG19_OUTCFG77_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73207   TIMER_OUTCFG19_OUTCFG77_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73208   TIMER_OUTCFG19_OUTCFG77_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73209   TIMER_OUTCFG19_OUTCFG77_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73210   TIMER_OUTCFG19_OUTCFG77_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73211   TIMER_OUTCFG19_OUTCFG77_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73212   TIMER_OUTCFG19_OUTCFG77_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73213   TIMER_OUTCFG19_OUTCFG77_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73214   TIMER_OUTCFG19_OUTCFG77_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73215   TIMER_OUTCFG19_OUTCFG77_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73216   TIMER_OUTCFG19_OUTCFG77_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73217   TIMER_OUTCFG19_OUTCFG77_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73218   TIMER_OUTCFG19_OUTCFG77_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73219   TIMER_OUTCFG19_OUTCFG77_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73220   TIMER_OUTCFG19_OUTCFG77_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73221   TIMER_OUTCFG19_OUTCFG77_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73222   TIMER_OUTCFG19_OUTCFG77_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73223   TIMER_OUTCFG19_OUTCFG77_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73224   TIMER_OUTCFG19_OUTCFG77_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73225   TIMER_OUTCFG19_OUTCFG77_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73226   TIMER_OUTCFG19_OUTCFG77_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73227   TIMER_OUTCFG19_OUTCFG77_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73228   TIMER_OUTCFG19_OUTCFG77_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73229   TIMER_OUTCFG19_OUTCFG77_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73230   TIMER_OUTCFG19_OUTCFG77_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73231   TIMER_OUTCFG19_OUTCFG77_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73232   TIMER_OUTCFG19_OUTCFG77_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73233   TIMER_OUTCFG19_OUTCFG77_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73234   TIMER_OUTCFG19_OUTCFG77_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73235   TIMER_OUTCFG19_OUTCFG77_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73236   TIMER_OUTCFG19_OUTCFG77_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73237   TIMER_OUTCFG19_OUTCFG77_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73238   TIMER_OUTCFG19_OUTCFG77_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73239   TIMER_OUTCFG19_OUTCFG77_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73240   TIMER_OUTCFG19_OUTCFG77_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73241   TIMER_OUTCFG19_OUTCFG77_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73242 } TIMER_OUTCFG19_OUTCFG77_Enum;
73243 
73244 /* ============================================  TIMER OUTCFG19 OUTCFG76 [0..5]  ============================================= */
73245 typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG76                                                   */
73246   TIMER_OUTCFG19_OUTCFG76_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73247   TIMER_OUTCFG19_OUTCFG76_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73248   TIMER_OUTCFG19_OUTCFG76_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73249   TIMER_OUTCFG19_OUTCFG76_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73250   TIMER_OUTCFG19_OUTCFG76_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73251   TIMER_OUTCFG19_OUTCFG76_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73252   TIMER_OUTCFG19_OUTCFG76_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73253   TIMER_OUTCFG19_OUTCFG76_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73254   TIMER_OUTCFG19_OUTCFG76_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73255   TIMER_OUTCFG19_OUTCFG76_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73256   TIMER_OUTCFG19_OUTCFG76_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73257   TIMER_OUTCFG19_OUTCFG76_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73258   TIMER_OUTCFG19_OUTCFG76_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73259   TIMER_OUTCFG19_OUTCFG76_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73260   TIMER_OUTCFG19_OUTCFG76_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73261   TIMER_OUTCFG19_OUTCFG76_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73262   TIMER_OUTCFG19_OUTCFG76_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73263   TIMER_OUTCFG19_OUTCFG76_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73264   TIMER_OUTCFG19_OUTCFG76_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73265   TIMER_OUTCFG19_OUTCFG76_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73266   TIMER_OUTCFG19_OUTCFG76_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73267   TIMER_OUTCFG19_OUTCFG76_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73268   TIMER_OUTCFG19_OUTCFG76_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73269   TIMER_OUTCFG19_OUTCFG76_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73270   TIMER_OUTCFG19_OUTCFG76_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73271   TIMER_OUTCFG19_OUTCFG76_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73272   TIMER_OUTCFG19_OUTCFG76_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73273   TIMER_OUTCFG19_OUTCFG76_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73274   TIMER_OUTCFG19_OUTCFG76_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73275   TIMER_OUTCFG19_OUTCFG76_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73276   TIMER_OUTCFG19_OUTCFG76_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73277   TIMER_OUTCFG19_OUTCFG76_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73278   TIMER_OUTCFG19_OUTCFG76_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73279   TIMER_OUTCFG19_OUTCFG76_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73280   TIMER_OUTCFG19_OUTCFG76_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73281   TIMER_OUTCFG19_OUTCFG76_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73282   TIMER_OUTCFG19_OUTCFG76_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73283   TIMER_OUTCFG19_OUTCFG76_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73284   TIMER_OUTCFG19_OUTCFG76_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73285   TIMER_OUTCFG19_OUTCFG76_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73286   TIMER_OUTCFG19_OUTCFG76_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73287 } TIMER_OUTCFG19_OUTCFG76_Enum;
73288 
73289 /* =======================================================  OUTCFG20  ======================================================== */
73290 /* ===========================================  TIMER OUTCFG20 OUTCFG83 [24..29]  ============================================ */
73291 typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG83                                                   */
73292   TIMER_OUTCFG20_OUTCFG83_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73293   TIMER_OUTCFG20_OUTCFG83_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73294   TIMER_OUTCFG20_OUTCFG83_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73295   TIMER_OUTCFG20_OUTCFG83_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73296   TIMER_OUTCFG20_OUTCFG83_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73297   TIMER_OUTCFG20_OUTCFG83_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73298   TIMER_OUTCFG20_OUTCFG83_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73299   TIMER_OUTCFG20_OUTCFG83_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73300   TIMER_OUTCFG20_OUTCFG83_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73301   TIMER_OUTCFG20_OUTCFG83_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73302   TIMER_OUTCFG20_OUTCFG83_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73303   TIMER_OUTCFG20_OUTCFG83_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73304   TIMER_OUTCFG20_OUTCFG83_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73305   TIMER_OUTCFG20_OUTCFG83_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73306   TIMER_OUTCFG20_OUTCFG83_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73307   TIMER_OUTCFG20_OUTCFG83_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73308   TIMER_OUTCFG20_OUTCFG83_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73309   TIMER_OUTCFG20_OUTCFG83_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73310   TIMER_OUTCFG20_OUTCFG83_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73311   TIMER_OUTCFG20_OUTCFG83_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73312   TIMER_OUTCFG20_OUTCFG83_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73313   TIMER_OUTCFG20_OUTCFG83_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73314   TIMER_OUTCFG20_OUTCFG83_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73315   TIMER_OUTCFG20_OUTCFG83_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73316   TIMER_OUTCFG20_OUTCFG83_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73317   TIMER_OUTCFG20_OUTCFG83_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73318   TIMER_OUTCFG20_OUTCFG83_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73319   TIMER_OUTCFG20_OUTCFG83_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73320   TIMER_OUTCFG20_OUTCFG83_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73321   TIMER_OUTCFG20_OUTCFG83_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73322   TIMER_OUTCFG20_OUTCFG83_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73323   TIMER_OUTCFG20_OUTCFG83_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73324   TIMER_OUTCFG20_OUTCFG83_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73325   TIMER_OUTCFG20_OUTCFG83_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73326   TIMER_OUTCFG20_OUTCFG83_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73327   TIMER_OUTCFG20_OUTCFG83_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73328   TIMER_OUTCFG20_OUTCFG83_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73329   TIMER_OUTCFG20_OUTCFG83_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73330   TIMER_OUTCFG20_OUTCFG83_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73331   TIMER_OUTCFG20_OUTCFG83_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73332   TIMER_OUTCFG20_OUTCFG83_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73333 } TIMER_OUTCFG20_OUTCFG83_Enum;
73334 
73335 /* ===========================================  TIMER OUTCFG20 OUTCFG82 [16..21]  ============================================ */
73336 typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG82                                                   */
73337   TIMER_OUTCFG20_OUTCFG82_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73338   TIMER_OUTCFG20_OUTCFG82_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73339   TIMER_OUTCFG20_OUTCFG82_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73340   TIMER_OUTCFG20_OUTCFG82_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73341   TIMER_OUTCFG20_OUTCFG82_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73342   TIMER_OUTCFG20_OUTCFG82_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73343   TIMER_OUTCFG20_OUTCFG82_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73344   TIMER_OUTCFG20_OUTCFG82_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73345   TIMER_OUTCFG20_OUTCFG82_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73346   TIMER_OUTCFG20_OUTCFG82_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73347   TIMER_OUTCFG20_OUTCFG82_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73348   TIMER_OUTCFG20_OUTCFG82_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73349   TIMER_OUTCFG20_OUTCFG82_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73350   TIMER_OUTCFG20_OUTCFG82_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73351   TIMER_OUTCFG20_OUTCFG82_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73352   TIMER_OUTCFG20_OUTCFG82_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73353   TIMER_OUTCFG20_OUTCFG82_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73354   TIMER_OUTCFG20_OUTCFG82_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73355   TIMER_OUTCFG20_OUTCFG82_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73356   TIMER_OUTCFG20_OUTCFG82_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73357   TIMER_OUTCFG20_OUTCFG82_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73358   TIMER_OUTCFG20_OUTCFG82_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73359   TIMER_OUTCFG20_OUTCFG82_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73360   TIMER_OUTCFG20_OUTCFG82_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73361   TIMER_OUTCFG20_OUTCFG82_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73362   TIMER_OUTCFG20_OUTCFG82_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73363   TIMER_OUTCFG20_OUTCFG82_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73364   TIMER_OUTCFG20_OUTCFG82_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73365   TIMER_OUTCFG20_OUTCFG82_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73366   TIMER_OUTCFG20_OUTCFG82_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73367   TIMER_OUTCFG20_OUTCFG82_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73368   TIMER_OUTCFG20_OUTCFG82_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73369   TIMER_OUTCFG20_OUTCFG82_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73370   TIMER_OUTCFG20_OUTCFG82_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73371   TIMER_OUTCFG20_OUTCFG82_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73372   TIMER_OUTCFG20_OUTCFG82_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73373   TIMER_OUTCFG20_OUTCFG82_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73374   TIMER_OUTCFG20_OUTCFG82_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73375   TIMER_OUTCFG20_OUTCFG82_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73376   TIMER_OUTCFG20_OUTCFG82_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73377   TIMER_OUTCFG20_OUTCFG82_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73378 } TIMER_OUTCFG20_OUTCFG82_Enum;
73379 
73380 /* ============================================  TIMER OUTCFG20 OUTCFG81 [8..13]  ============================================ */
73381 typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG81                                                   */
73382   TIMER_OUTCFG20_OUTCFG81_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73383   TIMER_OUTCFG20_OUTCFG81_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73384   TIMER_OUTCFG20_OUTCFG81_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73385   TIMER_OUTCFG20_OUTCFG81_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73386   TIMER_OUTCFG20_OUTCFG81_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73387   TIMER_OUTCFG20_OUTCFG81_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73388   TIMER_OUTCFG20_OUTCFG81_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73389   TIMER_OUTCFG20_OUTCFG81_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73390   TIMER_OUTCFG20_OUTCFG81_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73391   TIMER_OUTCFG20_OUTCFG81_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73392   TIMER_OUTCFG20_OUTCFG81_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73393   TIMER_OUTCFG20_OUTCFG81_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73394   TIMER_OUTCFG20_OUTCFG81_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73395   TIMER_OUTCFG20_OUTCFG81_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73396   TIMER_OUTCFG20_OUTCFG81_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73397   TIMER_OUTCFG20_OUTCFG81_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73398   TIMER_OUTCFG20_OUTCFG81_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73399   TIMER_OUTCFG20_OUTCFG81_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73400   TIMER_OUTCFG20_OUTCFG81_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73401   TIMER_OUTCFG20_OUTCFG81_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73402   TIMER_OUTCFG20_OUTCFG81_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73403   TIMER_OUTCFG20_OUTCFG81_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73404   TIMER_OUTCFG20_OUTCFG81_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73405   TIMER_OUTCFG20_OUTCFG81_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73406   TIMER_OUTCFG20_OUTCFG81_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73407   TIMER_OUTCFG20_OUTCFG81_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73408   TIMER_OUTCFG20_OUTCFG81_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73409   TIMER_OUTCFG20_OUTCFG81_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73410   TIMER_OUTCFG20_OUTCFG81_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73411   TIMER_OUTCFG20_OUTCFG81_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73412   TIMER_OUTCFG20_OUTCFG81_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73413   TIMER_OUTCFG20_OUTCFG81_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73414   TIMER_OUTCFG20_OUTCFG81_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73415   TIMER_OUTCFG20_OUTCFG81_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73416   TIMER_OUTCFG20_OUTCFG81_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73417   TIMER_OUTCFG20_OUTCFG81_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73418   TIMER_OUTCFG20_OUTCFG81_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73419   TIMER_OUTCFG20_OUTCFG81_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73420   TIMER_OUTCFG20_OUTCFG81_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73421   TIMER_OUTCFG20_OUTCFG81_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73422   TIMER_OUTCFG20_OUTCFG81_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73423 } TIMER_OUTCFG20_OUTCFG81_Enum;
73424 
73425 /* ============================================  TIMER OUTCFG20 OUTCFG80 [0..5]  ============================================= */
73426 typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG80                                                   */
73427   TIMER_OUTCFG20_OUTCFG80_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73428   TIMER_OUTCFG20_OUTCFG80_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73429   TIMER_OUTCFG20_OUTCFG80_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73430   TIMER_OUTCFG20_OUTCFG80_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73431   TIMER_OUTCFG20_OUTCFG80_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73432   TIMER_OUTCFG20_OUTCFG80_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73433   TIMER_OUTCFG20_OUTCFG80_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73434   TIMER_OUTCFG20_OUTCFG80_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73435   TIMER_OUTCFG20_OUTCFG80_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73436   TIMER_OUTCFG20_OUTCFG80_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73437   TIMER_OUTCFG20_OUTCFG80_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73438   TIMER_OUTCFG20_OUTCFG80_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73439   TIMER_OUTCFG20_OUTCFG80_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73440   TIMER_OUTCFG20_OUTCFG80_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73441   TIMER_OUTCFG20_OUTCFG80_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73442   TIMER_OUTCFG20_OUTCFG80_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73443   TIMER_OUTCFG20_OUTCFG80_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73444   TIMER_OUTCFG20_OUTCFG80_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73445   TIMER_OUTCFG20_OUTCFG80_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73446   TIMER_OUTCFG20_OUTCFG80_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73447   TIMER_OUTCFG20_OUTCFG80_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73448   TIMER_OUTCFG20_OUTCFG80_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73449   TIMER_OUTCFG20_OUTCFG80_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73450   TIMER_OUTCFG20_OUTCFG80_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73451   TIMER_OUTCFG20_OUTCFG80_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73452   TIMER_OUTCFG20_OUTCFG80_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73453   TIMER_OUTCFG20_OUTCFG80_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73454   TIMER_OUTCFG20_OUTCFG80_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73455   TIMER_OUTCFG20_OUTCFG80_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73456   TIMER_OUTCFG20_OUTCFG80_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73457   TIMER_OUTCFG20_OUTCFG80_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73458   TIMER_OUTCFG20_OUTCFG80_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73459   TIMER_OUTCFG20_OUTCFG80_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73460   TIMER_OUTCFG20_OUTCFG80_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73461   TIMER_OUTCFG20_OUTCFG80_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73462   TIMER_OUTCFG20_OUTCFG80_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73463   TIMER_OUTCFG20_OUTCFG80_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73464   TIMER_OUTCFG20_OUTCFG80_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73465   TIMER_OUTCFG20_OUTCFG80_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73466   TIMER_OUTCFG20_OUTCFG80_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73467   TIMER_OUTCFG20_OUTCFG80_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73468 } TIMER_OUTCFG20_OUTCFG80_Enum;
73469 
73470 /* =======================================================  OUTCFG21  ======================================================== */
73471 /* ===========================================  TIMER OUTCFG21 OUTCFG87 [24..29]  ============================================ */
73472 typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG87                                                   */
73473   TIMER_OUTCFG21_OUTCFG87_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73474   TIMER_OUTCFG21_OUTCFG87_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73475   TIMER_OUTCFG21_OUTCFG87_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73476   TIMER_OUTCFG21_OUTCFG87_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73477   TIMER_OUTCFG21_OUTCFG87_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73478   TIMER_OUTCFG21_OUTCFG87_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73479   TIMER_OUTCFG21_OUTCFG87_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73480   TIMER_OUTCFG21_OUTCFG87_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73481   TIMER_OUTCFG21_OUTCFG87_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73482   TIMER_OUTCFG21_OUTCFG87_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73483   TIMER_OUTCFG21_OUTCFG87_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73484   TIMER_OUTCFG21_OUTCFG87_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73485   TIMER_OUTCFG21_OUTCFG87_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73486   TIMER_OUTCFG21_OUTCFG87_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73487   TIMER_OUTCFG21_OUTCFG87_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73488   TIMER_OUTCFG21_OUTCFG87_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73489   TIMER_OUTCFG21_OUTCFG87_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73490   TIMER_OUTCFG21_OUTCFG87_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73491   TIMER_OUTCFG21_OUTCFG87_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73492   TIMER_OUTCFG21_OUTCFG87_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73493   TIMER_OUTCFG21_OUTCFG87_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73494   TIMER_OUTCFG21_OUTCFG87_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73495   TIMER_OUTCFG21_OUTCFG87_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73496   TIMER_OUTCFG21_OUTCFG87_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73497   TIMER_OUTCFG21_OUTCFG87_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73498   TIMER_OUTCFG21_OUTCFG87_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73499   TIMER_OUTCFG21_OUTCFG87_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73500   TIMER_OUTCFG21_OUTCFG87_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73501   TIMER_OUTCFG21_OUTCFG87_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73502   TIMER_OUTCFG21_OUTCFG87_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73503   TIMER_OUTCFG21_OUTCFG87_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73504   TIMER_OUTCFG21_OUTCFG87_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73505   TIMER_OUTCFG21_OUTCFG87_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73506   TIMER_OUTCFG21_OUTCFG87_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73507   TIMER_OUTCFG21_OUTCFG87_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73508   TIMER_OUTCFG21_OUTCFG87_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73509   TIMER_OUTCFG21_OUTCFG87_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73510   TIMER_OUTCFG21_OUTCFG87_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73511   TIMER_OUTCFG21_OUTCFG87_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73512   TIMER_OUTCFG21_OUTCFG87_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73513   TIMER_OUTCFG21_OUTCFG87_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73514 } TIMER_OUTCFG21_OUTCFG87_Enum;
73515 
73516 /* ===========================================  TIMER OUTCFG21 OUTCFG86 [16..21]  ============================================ */
73517 typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG86                                                   */
73518   TIMER_OUTCFG21_OUTCFG86_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73519   TIMER_OUTCFG21_OUTCFG86_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73520   TIMER_OUTCFG21_OUTCFG86_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73521   TIMER_OUTCFG21_OUTCFG86_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73522   TIMER_OUTCFG21_OUTCFG86_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73523   TIMER_OUTCFG21_OUTCFG86_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73524   TIMER_OUTCFG21_OUTCFG86_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73525   TIMER_OUTCFG21_OUTCFG86_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73526   TIMER_OUTCFG21_OUTCFG86_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73527   TIMER_OUTCFG21_OUTCFG86_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73528   TIMER_OUTCFG21_OUTCFG86_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73529   TIMER_OUTCFG21_OUTCFG86_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73530   TIMER_OUTCFG21_OUTCFG86_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73531   TIMER_OUTCFG21_OUTCFG86_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73532   TIMER_OUTCFG21_OUTCFG86_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73533   TIMER_OUTCFG21_OUTCFG86_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73534   TIMER_OUTCFG21_OUTCFG86_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73535   TIMER_OUTCFG21_OUTCFG86_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73536   TIMER_OUTCFG21_OUTCFG86_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73537   TIMER_OUTCFG21_OUTCFG86_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73538   TIMER_OUTCFG21_OUTCFG86_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73539   TIMER_OUTCFG21_OUTCFG86_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73540   TIMER_OUTCFG21_OUTCFG86_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73541   TIMER_OUTCFG21_OUTCFG86_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73542   TIMER_OUTCFG21_OUTCFG86_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73543   TIMER_OUTCFG21_OUTCFG86_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73544   TIMER_OUTCFG21_OUTCFG86_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73545   TIMER_OUTCFG21_OUTCFG86_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73546   TIMER_OUTCFG21_OUTCFG86_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73547   TIMER_OUTCFG21_OUTCFG86_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73548   TIMER_OUTCFG21_OUTCFG86_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73549   TIMER_OUTCFG21_OUTCFG86_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73550   TIMER_OUTCFG21_OUTCFG86_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73551   TIMER_OUTCFG21_OUTCFG86_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73552   TIMER_OUTCFG21_OUTCFG86_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73553   TIMER_OUTCFG21_OUTCFG86_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73554   TIMER_OUTCFG21_OUTCFG86_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73555   TIMER_OUTCFG21_OUTCFG86_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73556   TIMER_OUTCFG21_OUTCFG86_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73557   TIMER_OUTCFG21_OUTCFG86_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73558   TIMER_OUTCFG21_OUTCFG86_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73559 } TIMER_OUTCFG21_OUTCFG86_Enum;
73560 
73561 /* ============================================  TIMER OUTCFG21 OUTCFG85 [8..13]  ============================================ */
73562 typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG85                                                   */
73563   TIMER_OUTCFG21_OUTCFG85_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73564   TIMER_OUTCFG21_OUTCFG85_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73565   TIMER_OUTCFG21_OUTCFG85_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73566   TIMER_OUTCFG21_OUTCFG85_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73567   TIMER_OUTCFG21_OUTCFG85_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73568   TIMER_OUTCFG21_OUTCFG85_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73569   TIMER_OUTCFG21_OUTCFG85_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73570   TIMER_OUTCFG21_OUTCFG85_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73571   TIMER_OUTCFG21_OUTCFG85_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73572   TIMER_OUTCFG21_OUTCFG85_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73573   TIMER_OUTCFG21_OUTCFG85_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73574   TIMER_OUTCFG21_OUTCFG85_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73575   TIMER_OUTCFG21_OUTCFG85_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73576   TIMER_OUTCFG21_OUTCFG85_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73577   TIMER_OUTCFG21_OUTCFG85_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73578   TIMER_OUTCFG21_OUTCFG85_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73579   TIMER_OUTCFG21_OUTCFG85_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73580   TIMER_OUTCFG21_OUTCFG85_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73581   TIMER_OUTCFG21_OUTCFG85_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73582   TIMER_OUTCFG21_OUTCFG85_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73583   TIMER_OUTCFG21_OUTCFG85_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73584   TIMER_OUTCFG21_OUTCFG85_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73585   TIMER_OUTCFG21_OUTCFG85_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73586   TIMER_OUTCFG21_OUTCFG85_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73587   TIMER_OUTCFG21_OUTCFG85_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73588   TIMER_OUTCFG21_OUTCFG85_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73589   TIMER_OUTCFG21_OUTCFG85_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73590   TIMER_OUTCFG21_OUTCFG85_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73591   TIMER_OUTCFG21_OUTCFG85_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73592   TIMER_OUTCFG21_OUTCFG85_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73593   TIMER_OUTCFG21_OUTCFG85_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73594   TIMER_OUTCFG21_OUTCFG85_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73595   TIMER_OUTCFG21_OUTCFG85_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73596   TIMER_OUTCFG21_OUTCFG85_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73597   TIMER_OUTCFG21_OUTCFG85_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73598   TIMER_OUTCFG21_OUTCFG85_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73599   TIMER_OUTCFG21_OUTCFG85_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73600   TIMER_OUTCFG21_OUTCFG85_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73601   TIMER_OUTCFG21_OUTCFG85_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73602   TIMER_OUTCFG21_OUTCFG85_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73603   TIMER_OUTCFG21_OUTCFG85_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73604 } TIMER_OUTCFG21_OUTCFG85_Enum;
73605 
73606 /* ============================================  TIMER OUTCFG21 OUTCFG84 [0..5]  ============================================= */
73607 typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG84                                                   */
73608   TIMER_OUTCFG21_OUTCFG84_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73609   TIMER_OUTCFG21_OUTCFG84_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73610   TIMER_OUTCFG21_OUTCFG84_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73611   TIMER_OUTCFG21_OUTCFG84_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73612   TIMER_OUTCFG21_OUTCFG84_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73613   TIMER_OUTCFG21_OUTCFG84_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73614   TIMER_OUTCFG21_OUTCFG84_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73615   TIMER_OUTCFG21_OUTCFG84_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73616   TIMER_OUTCFG21_OUTCFG84_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73617   TIMER_OUTCFG21_OUTCFG84_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73618   TIMER_OUTCFG21_OUTCFG84_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73619   TIMER_OUTCFG21_OUTCFG84_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73620   TIMER_OUTCFG21_OUTCFG84_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73621   TIMER_OUTCFG21_OUTCFG84_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73622   TIMER_OUTCFG21_OUTCFG84_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73623   TIMER_OUTCFG21_OUTCFG84_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73624   TIMER_OUTCFG21_OUTCFG84_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73625   TIMER_OUTCFG21_OUTCFG84_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73626   TIMER_OUTCFG21_OUTCFG84_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73627   TIMER_OUTCFG21_OUTCFG84_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73628   TIMER_OUTCFG21_OUTCFG84_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73629   TIMER_OUTCFG21_OUTCFG84_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73630   TIMER_OUTCFG21_OUTCFG84_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73631   TIMER_OUTCFG21_OUTCFG84_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73632   TIMER_OUTCFG21_OUTCFG84_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73633   TIMER_OUTCFG21_OUTCFG84_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73634   TIMER_OUTCFG21_OUTCFG84_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73635   TIMER_OUTCFG21_OUTCFG84_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73636   TIMER_OUTCFG21_OUTCFG84_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73637   TIMER_OUTCFG21_OUTCFG84_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73638   TIMER_OUTCFG21_OUTCFG84_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73639   TIMER_OUTCFG21_OUTCFG84_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73640   TIMER_OUTCFG21_OUTCFG84_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73641   TIMER_OUTCFG21_OUTCFG84_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73642   TIMER_OUTCFG21_OUTCFG84_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73643   TIMER_OUTCFG21_OUTCFG84_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73644   TIMER_OUTCFG21_OUTCFG84_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73645   TIMER_OUTCFG21_OUTCFG84_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73646   TIMER_OUTCFG21_OUTCFG84_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73647   TIMER_OUTCFG21_OUTCFG84_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73648   TIMER_OUTCFG21_OUTCFG84_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73649 } TIMER_OUTCFG21_OUTCFG84_Enum;
73650 
73651 /* =======================================================  OUTCFG22  ======================================================== */
73652 /* ===========================================  TIMER OUTCFG22 OUTCFG91 [24..29]  ============================================ */
73653 typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG91                                                   */
73654   TIMER_OUTCFG22_OUTCFG91_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73655   TIMER_OUTCFG22_OUTCFG91_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73656   TIMER_OUTCFG22_OUTCFG91_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73657   TIMER_OUTCFG22_OUTCFG91_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73658   TIMER_OUTCFG22_OUTCFG91_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73659   TIMER_OUTCFG22_OUTCFG91_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73660   TIMER_OUTCFG22_OUTCFG91_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73661   TIMER_OUTCFG22_OUTCFG91_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73662   TIMER_OUTCFG22_OUTCFG91_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73663   TIMER_OUTCFG22_OUTCFG91_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73664   TIMER_OUTCFG22_OUTCFG91_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73665   TIMER_OUTCFG22_OUTCFG91_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73666   TIMER_OUTCFG22_OUTCFG91_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73667   TIMER_OUTCFG22_OUTCFG91_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73668   TIMER_OUTCFG22_OUTCFG91_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73669   TIMER_OUTCFG22_OUTCFG91_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73670   TIMER_OUTCFG22_OUTCFG91_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73671   TIMER_OUTCFG22_OUTCFG91_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73672   TIMER_OUTCFG22_OUTCFG91_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73673   TIMER_OUTCFG22_OUTCFG91_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73674   TIMER_OUTCFG22_OUTCFG91_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73675   TIMER_OUTCFG22_OUTCFG91_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73676   TIMER_OUTCFG22_OUTCFG91_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73677   TIMER_OUTCFG22_OUTCFG91_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73678   TIMER_OUTCFG22_OUTCFG91_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73679   TIMER_OUTCFG22_OUTCFG91_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73680   TIMER_OUTCFG22_OUTCFG91_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73681   TIMER_OUTCFG22_OUTCFG91_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73682   TIMER_OUTCFG22_OUTCFG91_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73683   TIMER_OUTCFG22_OUTCFG91_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73684   TIMER_OUTCFG22_OUTCFG91_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73685   TIMER_OUTCFG22_OUTCFG91_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73686   TIMER_OUTCFG22_OUTCFG91_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73687   TIMER_OUTCFG22_OUTCFG91_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73688   TIMER_OUTCFG22_OUTCFG91_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73689   TIMER_OUTCFG22_OUTCFG91_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73690   TIMER_OUTCFG22_OUTCFG91_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73691   TIMER_OUTCFG22_OUTCFG91_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73692   TIMER_OUTCFG22_OUTCFG91_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73693   TIMER_OUTCFG22_OUTCFG91_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73694   TIMER_OUTCFG22_OUTCFG91_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73695 } TIMER_OUTCFG22_OUTCFG91_Enum;
73696 
73697 /* ===========================================  TIMER OUTCFG22 OUTCFG90 [16..21]  ============================================ */
73698 typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG90                                                   */
73699   TIMER_OUTCFG22_OUTCFG90_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73700   TIMER_OUTCFG22_OUTCFG90_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73701   TIMER_OUTCFG22_OUTCFG90_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73702   TIMER_OUTCFG22_OUTCFG90_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73703   TIMER_OUTCFG22_OUTCFG90_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73704   TIMER_OUTCFG22_OUTCFG90_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73705   TIMER_OUTCFG22_OUTCFG90_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73706   TIMER_OUTCFG22_OUTCFG90_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73707   TIMER_OUTCFG22_OUTCFG90_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73708   TIMER_OUTCFG22_OUTCFG90_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73709   TIMER_OUTCFG22_OUTCFG90_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73710   TIMER_OUTCFG22_OUTCFG90_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73711   TIMER_OUTCFG22_OUTCFG90_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73712   TIMER_OUTCFG22_OUTCFG90_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73713   TIMER_OUTCFG22_OUTCFG90_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73714   TIMER_OUTCFG22_OUTCFG90_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73715   TIMER_OUTCFG22_OUTCFG90_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73716   TIMER_OUTCFG22_OUTCFG90_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73717   TIMER_OUTCFG22_OUTCFG90_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73718   TIMER_OUTCFG22_OUTCFG90_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73719   TIMER_OUTCFG22_OUTCFG90_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73720   TIMER_OUTCFG22_OUTCFG90_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73721   TIMER_OUTCFG22_OUTCFG90_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73722   TIMER_OUTCFG22_OUTCFG90_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73723   TIMER_OUTCFG22_OUTCFG90_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73724   TIMER_OUTCFG22_OUTCFG90_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73725   TIMER_OUTCFG22_OUTCFG90_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73726   TIMER_OUTCFG22_OUTCFG90_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73727   TIMER_OUTCFG22_OUTCFG90_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73728   TIMER_OUTCFG22_OUTCFG90_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73729   TIMER_OUTCFG22_OUTCFG90_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73730   TIMER_OUTCFG22_OUTCFG90_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73731   TIMER_OUTCFG22_OUTCFG90_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73732   TIMER_OUTCFG22_OUTCFG90_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73733   TIMER_OUTCFG22_OUTCFG90_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73734   TIMER_OUTCFG22_OUTCFG90_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73735   TIMER_OUTCFG22_OUTCFG90_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73736   TIMER_OUTCFG22_OUTCFG90_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73737   TIMER_OUTCFG22_OUTCFG90_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73738   TIMER_OUTCFG22_OUTCFG90_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73739   TIMER_OUTCFG22_OUTCFG90_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73740 } TIMER_OUTCFG22_OUTCFG90_Enum;
73741 
73742 /* ============================================  TIMER OUTCFG22 OUTCFG89 [8..13]  ============================================ */
73743 typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG89                                                   */
73744   TIMER_OUTCFG22_OUTCFG89_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73745   TIMER_OUTCFG22_OUTCFG89_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73746   TIMER_OUTCFG22_OUTCFG89_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73747   TIMER_OUTCFG22_OUTCFG89_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73748   TIMER_OUTCFG22_OUTCFG89_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73749   TIMER_OUTCFG22_OUTCFG89_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73750   TIMER_OUTCFG22_OUTCFG89_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73751   TIMER_OUTCFG22_OUTCFG89_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73752   TIMER_OUTCFG22_OUTCFG89_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73753   TIMER_OUTCFG22_OUTCFG89_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73754   TIMER_OUTCFG22_OUTCFG89_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73755   TIMER_OUTCFG22_OUTCFG89_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73756   TIMER_OUTCFG22_OUTCFG89_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73757   TIMER_OUTCFG22_OUTCFG89_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73758   TIMER_OUTCFG22_OUTCFG89_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73759   TIMER_OUTCFG22_OUTCFG89_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73760   TIMER_OUTCFG22_OUTCFG89_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73761   TIMER_OUTCFG22_OUTCFG89_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73762   TIMER_OUTCFG22_OUTCFG89_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73763   TIMER_OUTCFG22_OUTCFG89_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73764   TIMER_OUTCFG22_OUTCFG89_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73765   TIMER_OUTCFG22_OUTCFG89_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73766   TIMER_OUTCFG22_OUTCFG89_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73767   TIMER_OUTCFG22_OUTCFG89_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73768   TIMER_OUTCFG22_OUTCFG89_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73769   TIMER_OUTCFG22_OUTCFG89_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73770   TIMER_OUTCFG22_OUTCFG89_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73771   TIMER_OUTCFG22_OUTCFG89_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73772   TIMER_OUTCFG22_OUTCFG89_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73773   TIMER_OUTCFG22_OUTCFG89_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73774   TIMER_OUTCFG22_OUTCFG89_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73775   TIMER_OUTCFG22_OUTCFG89_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73776   TIMER_OUTCFG22_OUTCFG89_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73777   TIMER_OUTCFG22_OUTCFG89_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73778   TIMER_OUTCFG22_OUTCFG89_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73779   TIMER_OUTCFG22_OUTCFG89_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73780   TIMER_OUTCFG22_OUTCFG89_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73781   TIMER_OUTCFG22_OUTCFG89_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73782   TIMER_OUTCFG22_OUTCFG89_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73783   TIMER_OUTCFG22_OUTCFG89_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73784   TIMER_OUTCFG22_OUTCFG89_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73785 } TIMER_OUTCFG22_OUTCFG89_Enum;
73786 
73787 /* ============================================  TIMER OUTCFG22 OUTCFG88 [0..5]  ============================================= */
73788 typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG88                                                   */
73789   TIMER_OUTCFG22_OUTCFG88_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73790   TIMER_OUTCFG22_OUTCFG88_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73791   TIMER_OUTCFG22_OUTCFG88_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73792   TIMER_OUTCFG22_OUTCFG88_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73793   TIMER_OUTCFG22_OUTCFG88_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73794   TIMER_OUTCFG22_OUTCFG88_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73795   TIMER_OUTCFG22_OUTCFG88_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73796   TIMER_OUTCFG22_OUTCFG88_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73797   TIMER_OUTCFG22_OUTCFG88_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73798   TIMER_OUTCFG22_OUTCFG88_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73799   TIMER_OUTCFG22_OUTCFG88_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73800   TIMER_OUTCFG22_OUTCFG88_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73801   TIMER_OUTCFG22_OUTCFG88_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73802   TIMER_OUTCFG22_OUTCFG88_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73803   TIMER_OUTCFG22_OUTCFG88_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73804   TIMER_OUTCFG22_OUTCFG88_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73805   TIMER_OUTCFG22_OUTCFG88_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73806   TIMER_OUTCFG22_OUTCFG88_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73807   TIMER_OUTCFG22_OUTCFG88_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73808   TIMER_OUTCFG22_OUTCFG88_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73809   TIMER_OUTCFG22_OUTCFG88_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73810   TIMER_OUTCFG22_OUTCFG88_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73811   TIMER_OUTCFG22_OUTCFG88_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73812   TIMER_OUTCFG22_OUTCFG88_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73813   TIMER_OUTCFG22_OUTCFG88_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73814   TIMER_OUTCFG22_OUTCFG88_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73815   TIMER_OUTCFG22_OUTCFG88_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73816   TIMER_OUTCFG22_OUTCFG88_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73817   TIMER_OUTCFG22_OUTCFG88_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73818   TIMER_OUTCFG22_OUTCFG88_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73819   TIMER_OUTCFG22_OUTCFG88_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73820   TIMER_OUTCFG22_OUTCFG88_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73821   TIMER_OUTCFG22_OUTCFG88_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73822   TIMER_OUTCFG22_OUTCFG88_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73823   TIMER_OUTCFG22_OUTCFG88_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73824   TIMER_OUTCFG22_OUTCFG88_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73825   TIMER_OUTCFG22_OUTCFG88_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73826   TIMER_OUTCFG22_OUTCFG88_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73827   TIMER_OUTCFG22_OUTCFG88_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73828   TIMER_OUTCFG22_OUTCFG88_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73829   TIMER_OUTCFG22_OUTCFG88_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73830 } TIMER_OUTCFG22_OUTCFG88_Enum;
73831 
73832 /* =======================================================  OUTCFG23  ======================================================== */
73833 /* ===========================================  TIMER OUTCFG23 OUTCFG95 [24..29]  ============================================ */
73834 typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG95                                                   */
73835   TIMER_OUTCFG23_OUTCFG95_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73836   TIMER_OUTCFG23_OUTCFG95_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73837   TIMER_OUTCFG23_OUTCFG95_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73838   TIMER_OUTCFG23_OUTCFG95_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73839   TIMER_OUTCFG23_OUTCFG95_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73840   TIMER_OUTCFG23_OUTCFG95_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73841   TIMER_OUTCFG23_OUTCFG95_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73842   TIMER_OUTCFG23_OUTCFG95_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73843   TIMER_OUTCFG23_OUTCFG95_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73844   TIMER_OUTCFG23_OUTCFG95_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73845   TIMER_OUTCFG23_OUTCFG95_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73846   TIMER_OUTCFG23_OUTCFG95_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73847   TIMER_OUTCFG23_OUTCFG95_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73848   TIMER_OUTCFG23_OUTCFG95_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73849   TIMER_OUTCFG23_OUTCFG95_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73850   TIMER_OUTCFG23_OUTCFG95_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73851   TIMER_OUTCFG23_OUTCFG95_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73852   TIMER_OUTCFG23_OUTCFG95_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73853   TIMER_OUTCFG23_OUTCFG95_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73854   TIMER_OUTCFG23_OUTCFG95_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73855   TIMER_OUTCFG23_OUTCFG95_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73856   TIMER_OUTCFG23_OUTCFG95_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73857   TIMER_OUTCFG23_OUTCFG95_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73858   TIMER_OUTCFG23_OUTCFG95_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73859   TIMER_OUTCFG23_OUTCFG95_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73860   TIMER_OUTCFG23_OUTCFG95_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73861   TIMER_OUTCFG23_OUTCFG95_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73862   TIMER_OUTCFG23_OUTCFG95_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73863   TIMER_OUTCFG23_OUTCFG95_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73864   TIMER_OUTCFG23_OUTCFG95_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73865   TIMER_OUTCFG23_OUTCFG95_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73866   TIMER_OUTCFG23_OUTCFG95_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73867   TIMER_OUTCFG23_OUTCFG95_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73868   TIMER_OUTCFG23_OUTCFG95_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73869   TIMER_OUTCFG23_OUTCFG95_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73870   TIMER_OUTCFG23_OUTCFG95_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73871   TIMER_OUTCFG23_OUTCFG95_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73872   TIMER_OUTCFG23_OUTCFG95_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73873   TIMER_OUTCFG23_OUTCFG95_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73874   TIMER_OUTCFG23_OUTCFG95_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73875   TIMER_OUTCFG23_OUTCFG95_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73876 } TIMER_OUTCFG23_OUTCFG95_Enum;
73877 
73878 /* ===========================================  TIMER OUTCFG23 OUTCFG94 [16..21]  ============================================ */
73879 typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG94                                                   */
73880   TIMER_OUTCFG23_OUTCFG94_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73881   TIMER_OUTCFG23_OUTCFG94_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73882   TIMER_OUTCFG23_OUTCFG94_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73883   TIMER_OUTCFG23_OUTCFG94_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73884   TIMER_OUTCFG23_OUTCFG94_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73885   TIMER_OUTCFG23_OUTCFG94_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73886   TIMER_OUTCFG23_OUTCFG94_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73887   TIMER_OUTCFG23_OUTCFG94_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73888   TIMER_OUTCFG23_OUTCFG94_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73889   TIMER_OUTCFG23_OUTCFG94_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73890   TIMER_OUTCFG23_OUTCFG94_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73891   TIMER_OUTCFG23_OUTCFG94_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73892   TIMER_OUTCFG23_OUTCFG94_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73893   TIMER_OUTCFG23_OUTCFG94_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73894   TIMER_OUTCFG23_OUTCFG94_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73895   TIMER_OUTCFG23_OUTCFG94_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73896   TIMER_OUTCFG23_OUTCFG94_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73897   TIMER_OUTCFG23_OUTCFG94_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73898   TIMER_OUTCFG23_OUTCFG94_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73899   TIMER_OUTCFG23_OUTCFG94_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73900   TIMER_OUTCFG23_OUTCFG94_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73901   TIMER_OUTCFG23_OUTCFG94_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73902   TIMER_OUTCFG23_OUTCFG94_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73903   TIMER_OUTCFG23_OUTCFG94_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73904   TIMER_OUTCFG23_OUTCFG94_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73905   TIMER_OUTCFG23_OUTCFG94_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73906   TIMER_OUTCFG23_OUTCFG94_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73907   TIMER_OUTCFG23_OUTCFG94_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73908   TIMER_OUTCFG23_OUTCFG94_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73909   TIMER_OUTCFG23_OUTCFG94_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73910   TIMER_OUTCFG23_OUTCFG94_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73911   TIMER_OUTCFG23_OUTCFG94_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73912   TIMER_OUTCFG23_OUTCFG94_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73913   TIMER_OUTCFG23_OUTCFG94_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73914   TIMER_OUTCFG23_OUTCFG94_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73915   TIMER_OUTCFG23_OUTCFG94_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73916   TIMER_OUTCFG23_OUTCFG94_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73917   TIMER_OUTCFG23_OUTCFG94_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73918   TIMER_OUTCFG23_OUTCFG94_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73919   TIMER_OUTCFG23_OUTCFG94_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73920   TIMER_OUTCFG23_OUTCFG94_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73921 } TIMER_OUTCFG23_OUTCFG94_Enum;
73922 
73923 /* ============================================  TIMER OUTCFG23 OUTCFG93 [8..13]  ============================================ */
73924 typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG93                                                   */
73925   TIMER_OUTCFG23_OUTCFG93_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73926   TIMER_OUTCFG23_OUTCFG93_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73927   TIMER_OUTCFG23_OUTCFG93_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73928   TIMER_OUTCFG23_OUTCFG93_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73929   TIMER_OUTCFG23_OUTCFG93_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73930   TIMER_OUTCFG23_OUTCFG93_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73931   TIMER_OUTCFG23_OUTCFG93_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73932   TIMER_OUTCFG23_OUTCFG93_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73933   TIMER_OUTCFG23_OUTCFG93_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73934   TIMER_OUTCFG23_OUTCFG93_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73935   TIMER_OUTCFG23_OUTCFG93_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73936   TIMER_OUTCFG23_OUTCFG93_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73937   TIMER_OUTCFG23_OUTCFG93_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73938   TIMER_OUTCFG23_OUTCFG93_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73939   TIMER_OUTCFG23_OUTCFG93_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73940   TIMER_OUTCFG23_OUTCFG93_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73941   TIMER_OUTCFG23_OUTCFG93_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73942   TIMER_OUTCFG23_OUTCFG93_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73943   TIMER_OUTCFG23_OUTCFG93_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73944   TIMER_OUTCFG23_OUTCFG93_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73945   TIMER_OUTCFG23_OUTCFG93_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73946   TIMER_OUTCFG23_OUTCFG93_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73947   TIMER_OUTCFG23_OUTCFG93_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73948   TIMER_OUTCFG23_OUTCFG93_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73949   TIMER_OUTCFG23_OUTCFG93_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73950   TIMER_OUTCFG23_OUTCFG93_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73951   TIMER_OUTCFG23_OUTCFG93_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73952   TIMER_OUTCFG23_OUTCFG93_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73953   TIMER_OUTCFG23_OUTCFG93_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73954   TIMER_OUTCFG23_OUTCFG93_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
73955   TIMER_OUTCFG23_OUTCFG93_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
73956   TIMER_OUTCFG23_OUTCFG93_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
73957   TIMER_OUTCFG23_OUTCFG93_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
73958   TIMER_OUTCFG23_OUTCFG93_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
73959   TIMER_OUTCFG23_OUTCFG93_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
73960   TIMER_OUTCFG23_OUTCFG93_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
73961   TIMER_OUTCFG23_OUTCFG93_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
73962   TIMER_OUTCFG23_OUTCFG93_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
73963   TIMER_OUTCFG23_OUTCFG93_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
73964   TIMER_OUTCFG23_OUTCFG93_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
73965   TIMER_OUTCFG23_OUTCFG93_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
73966 } TIMER_OUTCFG23_OUTCFG93_Enum;
73967 
73968 /* ============================================  TIMER OUTCFG23 OUTCFG92 [0..5]  ============================================= */
73969 typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG92                                                   */
73970   TIMER_OUTCFG23_OUTCFG92_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
73971   TIMER_OUTCFG23_OUTCFG92_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
73972   TIMER_OUTCFG23_OUTCFG92_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
73973   TIMER_OUTCFG23_OUTCFG92_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
73974   TIMER_OUTCFG23_OUTCFG92_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
73975   TIMER_OUTCFG23_OUTCFG92_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
73976   TIMER_OUTCFG23_OUTCFG92_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
73977   TIMER_OUTCFG23_OUTCFG92_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
73978   TIMER_OUTCFG23_OUTCFG92_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
73979   TIMER_OUTCFG23_OUTCFG92_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
73980   TIMER_OUTCFG23_OUTCFG92_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
73981   TIMER_OUTCFG23_OUTCFG92_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
73982   TIMER_OUTCFG23_OUTCFG92_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
73983   TIMER_OUTCFG23_OUTCFG92_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
73984   TIMER_OUTCFG23_OUTCFG92_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
73985   TIMER_OUTCFG23_OUTCFG92_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
73986   TIMER_OUTCFG23_OUTCFG92_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
73987   TIMER_OUTCFG23_OUTCFG92_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
73988   TIMER_OUTCFG23_OUTCFG92_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
73989   TIMER_OUTCFG23_OUTCFG92_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
73990   TIMER_OUTCFG23_OUTCFG92_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
73991   TIMER_OUTCFG23_OUTCFG92_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
73992   TIMER_OUTCFG23_OUTCFG92_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
73993   TIMER_OUTCFG23_OUTCFG92_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
73994   TIMER_OUTCFG23_OUTCFG92_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
73995   TIMER_OUTCFG23_OUTCFG92_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
73996   TIMER_OUTCFG23_OUTCFG92_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
73997   TIMER_OUTCFG23_OUTCFG92_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
73998   TIMER_OUTCFG23_OUTCFG92_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
73999   TIMER_OUTCFG23_OUTCFG92_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74000   TIMER_OUTCFG23_OUTCFG92_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74001   TIMER_OUTCFG23_OUTCFG92_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74002   TIMER_OUTCFG23_OUTCFG92_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74003   TIMER_OUTCFG23_OUTCFG92_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74004   TIMER_OUTCFG23_OUTCFG92_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74005   TIMER_OUTCFG23_OUTCFG92_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74006   TIMER_OUTCFG23_OUTCFG92_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74007   TIMER_OUTCFG23_OUTCFG92_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74008   TIMER_OUTCFG23_OUTCFG92_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74009   TIMER_OUTCFG23_OUTCFG92_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74010   TIMER_OUTCFG23_OUTCFG92_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
74011 } TIMER_OUTCFG23_OUTCFG92_Enum;
74012 
74013 /* =======================================================  OUTCFG24  ======================================================== */
74014 /* ===========================================  TIMER OUTCFG24 OUTCFG99 [24..29]  ============================================ */
74015 typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG99                                                   */
74016   TIMER_OUTCFG24_OUTCFG99_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74017   TIMER_OUTCFG24_OUTCFG99_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74018   TIMER_OUTCFG24_OUTCFG99_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74019   TIMER_OUTCFG24_OUTCFG99_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74020   TIMER_OUTCFG24_OUTCFG99_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74021   TIMER_OUTCFG24_OUTCFG99_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74022   TIMER_OUTCFG24_OUTCFG99_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74023   TIMER_OUTCFG24_OUTCFG99_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74024   TIMER_OUTCFG24_OUTCFG99_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74025   TIMER_OUTCFG24_OUTCFG99_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74026   TIMER_OUTCFG24_OUTCFG99_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74027   TIMER_OUTCFG24_OUTCFG99_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74028   TIMER_OUTCFG24_OUTCFG99_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74029   TIMER_OUTCFG24_OUTCFG99_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74030   TIMER_OUTCFG24_OUTCFG99_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74031   TIMER_OUTCFG24_OUTCFG99_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74032   TIMER_OUTCFG24_OUTCFG99_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74033   TIMER_OUTCFG24_OUTCFG99_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74034   TIMER_OUTCFG24_OUTCFG99_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74035   TIMER_OUTCFG24_OUTCFG99_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74036   TIMER_OUTCFG24_OUTCFG99_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74037   TIMER_OUTCFG24_OUTCFG99_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74038   TIMER_OUTCFG24_OUTCFG99_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74039   TIMER_OUTCFG24_OUTCFG99_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74040   TIMER_OUTCFG24_OUTCFG99_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74041   TIMER_OUTCFG24_OUTCFG99_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74042   TIMER_OUTCFG24_OUTCFG99_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74043   TIMER_OUTCFG24_OUTCFG99_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74044   TIMER_OUTCFG24_OUTCFG99_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74045   TIMER_OUTCFG24_OUTCFG99_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74046   TIMER_OUTCFG24_OUTCFG99_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74047   TIMER_OUTCFG24_OUTCFG99_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74048   TIMER_OUTCFG24_OUTCFG99_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74049   TIMER_OUTCFG24_OUTCFG99_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74050   TIMER_OUTCFG24_OUTCFG99_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74051   TIMER_OUTCFG24_OUTCFG99_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74052   TIMER_OUTCFG24_OUTCFG99_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74053   TIMER_OUTCFG24_OUTCFG99_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74054   TIMER_OUTCFG24_OUTCFG99_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74055   TIMER_OUTCFG24_OUTCFG99_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74056   TIMER_OUTCFG24_OUTCFG99_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
74057 } TIMER_OUTCFG24_OUTCFG99_Enum;
74058 
74059 /* ===========================================  TIMER OUTCFG24 OUTCFG98 [16..21]  ============================================ */
74060 typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG98                                                   */
74061   TIMER_OUTCFG24_OUTCFG98_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74062   TIMER_OUTCFG24_OUTCFG98_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74063   TIMER_OUTCFG24_OUTCFG98_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74064   TIMER_OUTCFG24_OUTCFG98_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74065   TIMER_OUTCFG24_OUTCFG98_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74066   TIMER_OUTCFG24_OUTCFG98_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74067   TIMER_OUTCFG24_OUTCFG98_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74068   TIMER_OUTCFG24_OUTCFG98_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74069   TIMER_OUTCFG24_OUTCFG98_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74070   TIMER_OUTCFG24_OUTCFG98_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74071   TIMER_OUTCFG24_OUTCFG98_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74072   TIMER_OUTCFG24_OUTCFG98_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74073   TIMER_OUTCFG24_OUTCFG98_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74074   TIMER_OUTCFG24_OUTCFG98_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74075   TIMER_OUTCFG24_OUTCFG98_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74076   TIMER_OUTCFG24_OUTCFG98_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74077   TIMER_OUTCFG24_OUTCFG98_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74078   TIMER_OUTCFG24_OUTCFG98_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74079   TIMER_OUTCFG24_OUTCFG98_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74080   TIMER_OUTCFG24_OUTCFG98_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74081   TIMER_OUTCFG24_OUTCFG98_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74082   TIMER_OUTCFG24_OUTCFG98_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74083   TIMER_OUTCFG24_OUTCFG98_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74084   TIMER_OUTCFG24_OUTCFG98_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74085   TIMER_OUTCFG24_OUTCFG98_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74086   TIMER_OUTCFG24_OUTCFG98_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74087   TIMER_OUTCFG24_OUTCFG98_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74088   TIMER_OUTCFG24_OUTCFG98_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74089   TIMER_OUTCFG24_OUTCFG98_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74090   TIMER_OUTCFG24_OUTCFG98_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74091   TIMER_OUTCFG24_OUTCFG98_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74092   TIMER_OUTCFG24_OUTCFG98_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74093   TIMER_OUTCFG24_OUTCFG98_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74094   TIMER_OUTCFG24_OUTCFG98_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74095   TIMER_OUTCFG24_OUTCFG98_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74096   TIMER_OUTCFG24_OUTCFG98_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74097   TIMER_OUTCFG24_OUTCFG98_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74098   TIMER_OUTCFG24_OUTCFG98_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74099   TIMER_OUTCFG24_OUTCFG98_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74100   TIMER_OUTCFG24_OUTCFG98_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74101   TIMER_OUTCFG24_OUTCFG98_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
74102 } TIMER_OUTCFG24_OUTCFG98_Enum;
74103 
74104 /* ============================================  TIMER OUTCFG24 OUTCFG97 [8..13]  ============================================ */
74105 typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG97                                                   */
74106   TIMER_OUTCFG24_OUTCFG97_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74107   TIMER_OUTCFG24_OUTCFG97_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74108   TIMER_OUTCFG24_OUTCFG97_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74109   TIMER_OUTCFG24_OUTCFG97_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74110   TIMER_OUTCFG24_OUTCFG97_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74111   TIMER_OUTCFG24_OUTCFG97_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74112   TIMER_OUTCFG24_OUTCFG97_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74113   TIMER_OUTCFG24_OUTCFG97_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74114   TIMER_OUTCFG24_OUTCFG97_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74115   TIMER_OUTCFG24_OUTCFG97_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74116   TIMER_OUTCFG24_OUTCFG97_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74117   TIMER_OUTCFG24_OUTCFG97_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74118   TIMER_OUTCFG24_OUTCFG97_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74119   TIMER_OUTCFG24_OUTCFG97_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74120   TIMER_OUTCFG24_OUTCFG97_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74121   TIMER_OUTCFG24_OUTCFG97_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74122   TIMER_OUTCFG24_OUTCFG97_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74123   TIMER_OUTCFG24_OUTCFG97_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74124   TIMER_OUTCFG24_OUTCFG97_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74125   TIMER_OUTCFG24_OUTCFG97_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74126   TIMER_OUTCFG24_OUTCFG97_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74127   TIMER_OUTCFG24_OUTCFG97_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74128   TIMER_OUTCFG24_OUTCFG97_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74129   TIMER_OUTCFG24_OUTCFG97_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74130   TIMER_OUTCFG24_OUTCFG97_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74131   TIMER_OUTCFG24_OUTCFG97_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74132   TIMER_OUTCFG24_OUTCFG97_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74133   TIMER_OUTCFG24_OUTCFG97_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74134   TIMER_OUTCFG24_OUTCFG97_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74135   TIMER_OUTCFG24_OUTCFG97_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74136   TIMER_OUTCFG24_OUTCFG97_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74137   TIMER_OUTCFG24_OUTCFG97_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74138   TIMER_OUTCFG24_OUTCFG97_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74139   TIMER_OUTCFG24_OUTCFG97_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74140   TIMER_OUTCFG24_OUTCFG97_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74141   TIMER_OUTCFG24_OUTCFG97_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74142   TIMER_OUTCFG24_OUTCFG97_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74143   TIMER_OUTCFG24_OUTCFG97_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74144   TIMER_OUTCFG24_OUTCFG97_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74145   TIMER_OUTCFG24_OUTCFG97_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74146   TIMER_OUTCFG24_OUTCFG97_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
74147 } TIMER_OUTCFG24_OUTCFG97_Enum;
74148 
74149 /* ============================================  TIMER OUTCFG24 OUTCFG96 [0..5]  ============================================= */
74150 typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG96                                                   */
74151   TIMER_OUTCFG24_OUTCFG96_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74152   TIMER_OUTCFG24_OUTCFG96_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74153   TIMER_OUTCFG24_OUTCFG96_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74154   TIMER_OUTCFG24_OUTCFG96_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74155   TIMER_OUTCFG24_OUTCFG96_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74156   TIMER_OUTCFG24_OUTCFG96_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74157   TIMER_OUTCFG24_OUTCFG96_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74158   TIMER_OUTCFG24_OUTCFG96_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74159   TIMER_OUTCFG24_OUTCFG96_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74160   TIMER_OUTCFG24_OUTCFG96_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74161   TIMER_OUTCFG24_OUTCFG96_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74162   TIMER_OUTCFG24_OUTCFG96_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74163   TIMER_OUTCFG24_OUTCFG96_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74164   TIMER_OUTCFG24_OUTCFG96_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74165   TIMER_OUTCFG24_OUTCFG96_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74166   TIMER_OUTCFG24_OUTCFG96_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74167   TIMER_OUTCFG24_OUTCFG96_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74168   TIMER_OUTCFG24_OUTCFG96_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74169   TIMER_OUTCFG24_OUTCFG96_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74170   TIMER_OUTCFG24_OUTCFG96_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74171   TIMER_OUTCFG24_OUTCFG96_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74172   TIMER_OUTCFG24_OUTCFG96_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74173   TIMER_OUTCFG24_OUTCFG96_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74174   TIMER_OUTCFG24_OUTCFG96_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74175   TIMER_OUTCFG24_OUTCFG96_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74176   TIMER_OUTCFG24_OUTCFG96_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74177   TIMER_OUTCFG24_OUTCFG96_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74178   TIMER_OUTCFG24_OUTCFG96_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74179   TIMER_OUTCFG24_OUTCFG96_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74180   TIMER_OUTCFG24_OUTCFG96_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74181   TIMER_OUTCFG24_OUTCFG96_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74182   TIMER_OUTCFG24_OUTCFG96_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74183   TIMER_OUTCFG24_OUTCFG96_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74184   TIMER_OUTCFG24_OUTCFG96_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74185   TIMER_OUTCFG24_OUTCFG96_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74186   TIMER_OUTCFG24_OUTCFG96_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74187   TIMER_OUTCFG24_OUTCFG96_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74188   TIMER_OUTCFG24_OUTCFG96_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74189   TIMER_OUTCFG24_OUTCFG96_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74190   TIMER_OUTCFG24_OUTCFG96_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74191   TIMER_OUTCFG24_OUTCFG96_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
74192 } TIMER_OUTCFG24_OUTCFG96_Enum;
74193 
74194 /* =======================================================  OUTCFG25  ======================================================== */
74195 /* ===========================================  TIMER OUTCFG25 OUTCFG103 [24..29]  =========================================== */
74196 typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG103                                                  */
74197   TIMER_OUTCFG25_OUTCFG103_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74198   TIMER_OUTCFG25_OUTCFG103_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74199   TIMER_OUTCFG25_OUTCFG103_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74200   TIMER_OUTCFG25_OUTCFG103_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74201   TIMER_OUTCFG25_OUTCFG103_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74202   TIMER_OUTCFG25_OUTCFG103_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74203   TIMER_OUTCFG25_OUTCFG103_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74204   TIMER_OUTCFG25_OUTCFG103_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74205   TIMER_OUTCFG25_OUTCFG103_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74206   TIMER_OUTCFG25_OUTCFG103_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74207   TIMER_OUTCFG25_OUTCFG103_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74208   TIMER_OUTCFG25_OUTCFG103_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74209   TIMER_OUTCFG25_OUTCFG103_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74210   TIMER_OUTCFG25_OUTCFG103_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74211   TIMER_OUTCFG25_OUTCFG103_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74212   TIMER_OUTCFG25_OUTCFG103_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74213   TIMER_OUTCFG25_OUTCFG103_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74214   TIMER_OUTCFG25_OUTCFG103_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74215   TIMER_OUTCFG25_OUTCFG103_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74216   TIMER_OUTCFG25_OUTCFG103_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74217   TIMER_OUTCFG25_OUTCFG103_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74218   TIMER_OUTCFG25_OUTCFG103_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74219   TIMER_OUTCFG25_OUTCFG103_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74220   TIMER_OUTCFG25_OUTCFG103_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74221   TIMER_OUTCFG25_OUTCFG103_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74222   TIMER_OUTCFG25_OUTCFG103_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74223   TIMER_OUTCFG25_OUTCFG103_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74224   TIMER_OUTCFG25_OUTCFG103_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74225   TIMER_OUTCFG25_OUTCFG103_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74226   TIMER_OUTCFG25_OUTCFG103_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74227   TIMER_OUTCFG25_OUTCFG103_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74228   TIMER_OUTCFG25_OUTCFG103_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74229   TIMER_OUTCFG25_OUTCFG103_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74230   TIMER_OUTCFG25_OUTCFG103_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74231   TIMER_OUTCFG25_OUTCFG103_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74232   TIMER_OUTCFG25_OUTCFG103_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74233   TIMER_OUTCFG25_OUTCFG103_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74234   TIMER_OUTCFG25_OUTCFG103_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74235   TIMER_OUTCFG25_OUTCFG103_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74236   TIMER_OUTCFG25_OUTCFG103_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74237   TIMER_OUTCFG25_OUTCFG103_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74238 } TIMER_OUTCFG25_OUTCFG103_Enum;
74239 
74240 /* ===========================================  TIMER OUTCFG25 OUTCFG102 [16..21]  =========================================== */
74241 typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG102                                                  */
74242   TIMER_OUTCFG25_OUTCFG102_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74243   TIMER_OUTCFG25_OUTCFG102_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74244   TIMER_OUTCFG25_OUTCFG102_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74245   TIMER_OUTCFG25_OUTCFG102_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74246   TIMER_OUTCFG25_OUTCFG102_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74247   TIMER_OUTCFG25_OUTCFG102_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74248   TIMER_OUTCFG25_OUTCFG102_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74249   TIMER_OUTCFG25_OUTCFG102_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74250   TIMER_OUTCFG25_OUTCFG102_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74251   TIMER_OUTCFG25_OUTCFG102_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74252   TIMER_OUTCFG25_OUTCFG102_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74253   TIMER_OUTCFG25_OUTCFG102_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74254   TIMER_OUTCFG25_OUTCFG102_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74255   TIMER_OUTCFG25_OUTCFG102_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74256   TIMER_OUTCFG25_OUTCFG102_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74257   TIMER_OUTCFG25_OUTCFG102_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74258   TIMER_OUTCFG25_OUTCFG102_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74259   TIMER_OUTCFG25_OUTCFG102_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74260   TIMER_OUTCFG25_OUTCFG102_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74261   TIMER_OUTCFG25_OUTCFG102_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74262   TIMER_OUTCFG25_OUTCFG102_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74263   TIMER_OUTCFG25_OUTCFG102_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74264   TIMER_OUTCFG25_OUTCFG102_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74265   TIMER_OUTCFG25_OUTCFG102_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74266   TIMER_OUTCFG25_OUTCFG102_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74267   TIMER_OUTCFG25_OUTCFG102_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74268   TIMER_OUTCFG25_OUTCFG102_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74269   TIMER_OUTCFG25_OUTCFG102_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74270   TIMER_OUTCFG25_OUTCFG102_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74271   TIMER_OUTCFG25_OUTCFG102_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74272   TIMER_OUTCFG25_OUTCFG102_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74273   TIMER_OUTCFG25_OUTCFG102_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74274   TIMER_OUTCFG25_OUTCFG102_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74275   TIMER_OUTCFG25_OUTCFG102_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74276   TIMER_OUTCFG25_OUTCFG102_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74277   TIMER_OUTCFG25_OUTCFG102_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74278   TIMER_OUTCFG25_OUTCFG102_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74279   TIMER_OUTCFG25_OUTCFG102_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74280   TIMER_OUTCFG25_OUTCFG102_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74281   TIMER_OUTCFG25_OUTCFG102_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74282   TIMER_OUTCFG25_OUTCFG102_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74283 } TIMER_OUTCFG25_OUTCFG102_Enum;
74284 
74285 /* ===========================================  TIMER OUTCFG25 OUTCFG101 [8..13]  ============================================ */
74286 typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG101                                                  */
74287   TIMER_OUTCFG25_OUTCFG101_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74288   TIMER_OUTCFG25_OUTCFG101_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74289   TIMER_OUTCFG25_OUTCFG101_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74290   TIMER_OUTCFG25_OUTCFG101_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74291   TIMER_OUTCFG25_OUTCFG101_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74292   TIMER_OUTCFG25_OUTCFG101_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74293   TIMER_OUTCFG25_OUTCFG101_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74294   TIMER_OUTCFG25_OUTCFG101_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74295   TIMER_OUTCFG25_OUTCFG101_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74296   TIMER_OUTCFG25_OUTCFG101_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74297   TIMER_OUTCFG25_OUTCFG101_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74298   TIMER_OUTCFG25_OUTCFG101_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74299   TIMER_OUTCFG25_OUTCFG101_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74300   TIMER_OUTCFG25_OUTCFG101_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74301   TIMER_OUTCFG25_OUTCFG101_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74302   TIMER_OUTCFG25_OUTCFG101_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74303   TIMER_OUTCFG25_OUTCFG101_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74304   TIMER_OUTCFG25_OUTCFG101_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74305   TIMER_OUTCFG25_OUTCFG101_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74306   TIMER_OUTCFG25_OUTCFG101_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74307   TIMER_OUTCFG25_OUTCFG101_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74308   TIMER_OUTCFG25_OUTCFG101_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74309   TIMER_OUTCFG25_OUTCFG101_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74310   TIMER_OUTCFG25_OUTCFG101_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74311   TIMER_OUTCFG25_OUTCFG101_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74312   TIMER_OUTCFG25_OUTCFG101_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74313   TIMER_OUTCFG25_OUTCFG101_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74314   TIMER_OUTCFG25_OUTCFG101_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74315   TIMER_OUTCFG25_OUTCFG101_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74316   TIMER_OUTCFG25_OUTCFG101_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74317   TIMER_OUTCFG25_OUTCFG101_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74318   TIMER_OUTCFG25_OUTCFG101_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74319   TIMER_OUTCFG25_OUTCFG101_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74320   TIMER_OUTCFG25_OUTCFG101_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74321   TIMER_OUTCFG25_OUTCFG101_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74322   TIMER_OUTCFG25_OUTCFG101_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74323   TIMER_OUTCFG25_OUTCFG101_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74324   TIMER_OUTCFG25_OUTCFG101_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74325   TIMER_OUTCFG25_OUTCFG101_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74326   TIMER_OUTCFG25_OUTCFG101_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74327   TIMER_OUTCFG25_OUTCFG101_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74328 } TIMER_OUTCFG25_OUTCFG101_Enum;
74329 
74330 /* ============================================  TIMER OUTCFG25 OUTCFG100 [0..5]  ============================================ */
74331 typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG100                                                  */
74332   TIMER_OUTCFG25_OUTCFG100_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74333   TIMER_OUTCFG25_OUTCFG100_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74334   TIMER_OUTCFG25_OUTCFG100_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74335   TIMER_OUTCFG25_OUTCFG100_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74336   TIMER_OUTCFG25_OUTCFG100_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74337   TIMER_OUTCFG25_OUTCFG100_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74338   TIMER_OUTCFG25_OUTCFG100_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74339   TIMER_OUTCFG25_OUTCFG100_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74340   TIMER_OUTCFG25_OUTCFG100_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74341   TIMER_OUTCFG25_OUTCFG100_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74342   TIMER_OUTCFG25_OUTCFG100_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74343   TIMER_OUTCFG25_OUTCFG100_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74344   TIMER_OUTCFG25_OUTCFG100_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74345   TIMER_OUTCFG25_OUTCFG100_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74346   TIMER_OUTCFG25_OUTCFG100_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74347   TIMER_OUTCFG25_OUTCFG100_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74348   TIMER_OUTCFG25_OUTCFG100_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74349   TIMER_OUTCFG25_OUTCFG100_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74350   TIMER_OUTCFG25_OUTCFG100_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74351   TIMER_OUTCFG25_OUTCFG100_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74352   TIMER_OUTCFG25_OUTCFG100_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74353   TIMER_OUTCFG25_OUTCFG100_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74354   TIMER_OUTCFG25_OUTCFG100_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74355   TIMER_OUTCFG25_OUTCFG100_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74356   TIMER_OUTCFG25_OUTCFG100_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74357   TIMER_OUTCFG25_OUTCFG100_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74358   TIMER_OUTCFG25_OUTCFG100_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74359   TIMER_OUTCFG25_OUTCFG100_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74360   TIMER_OUTCFG25_OUTCFG100_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74361   TIMER_OUTCFG25_OUTCFG100_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74362   TIMER_OUTCFG25_OUTCFG100_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74363   TIMER_OUTCFG25_OUTCFG100_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74364   TIMER_OUTCFG25_OUTCFG100_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74365   TIMER_OUTCFG25_OUTCFG100_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74366   TIMER_OUTCFG25_OUTCFG100_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74367   TIMER_OUTCFG25_OUTCFG100_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74368   TIMER_OUTCFG25_OUTCFG100_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74369   TIMER_OUTCFG25_OUTCFG100_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74370   TIMER_OUTCFG25_OUTCFG100_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74371   TIMER_OUTCFG25_OUTCFG100_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74372   TIMER_OUTCFG25_OUTCFG100_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74373 } TIMER_OUTCFG25_OUTCFG100_Enum;
74374 
74375 /* =======================================================  OUTCFG26  ======================================================== */
74376 /* ===========================================  TIMER OUTCFG26 OUTCFG107 [24..29]  =========================================== */
74377 typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG107                                                  */
74378   TIMER_OUTCFG26_OUTCFG107_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74379   TIMER_OUTCFG26_OUTCFG107_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74380   TIMER_OUTCFG26_OUTCFG107_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74381   TIMER_OUTCFG26_OUTCFG107_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74382   TIMER_OUTCFG26_OUTCFG107_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74383   TIMER_OUTCFG26_OUTCFG107_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74384   TIMER_OUTCFG26_OUTCFG107_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74385   TIMER_OUTCFG26_OUTCFG107_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74386   TIMER_OUTCFG26_OUTCFG107_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74387   TIMER_OUTCFG26_OUTCFG107_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74388   TIMER_OUTCFG26_OUTCFG107_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74389   TIMER_OUTCFG26_OUTCFG107_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74390   TIMER_OUTCFG26_OUTCFG107_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74391   TIMER_OUTCFG26_OUTCFG107_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74392   TIMER_OUTCFG26_OUTCFG107_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74393   TIMER_OUTCFG26_OUTCFG107_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74394   TIMER_OUTCFG26_OUTCFG107_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74395   TIMER_OUTCFG26_OUTCFG107_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74396   TIMER_OUTCFG26_OUTCFG107_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74397   TIMER_OUTCFG26_OUTCFG107_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74398   TIMER_OUTCFG26_OUTCFG107_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74399   TIMER_OUTCFG26_OUTCFG107_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74400   TIMER_OUTCFG26_OUTCFG107_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74401   TIMER_OUTCFG26_OUTCFG107_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74402   TIMER_OUTCFG26_OUTCFG107_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74403   TIMER_OUTCFG26_OUTCFG107_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74404   TIMER_OUTCFG26_OUTCFG107_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74405   TIMER_OUTCFG26_OUTCFG107_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74406   TIMER_OUTCFG26_OUTCFG107_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74407   TIMER_OUTCFG26_OUTCFG107_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74408   TIMER_OUTCFG26_OUTCFG107_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74409   TIMER_OUTCFG26_OUTCFG107_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74410   TIMER_OUTCFG26_OUTCFG107_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74411   TIMER_OUTCFG26_OUTCFG107_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74412   TIMER_OUTCFG26_OUTCFG107_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74413   TIMER_OUTCFG26_OUTCFG107_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74414   TIMER_OUTCFG26_OUTCFG107_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74415   TIMER_OUTCFG26_OUTCFG107_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74416   TIMER_OUTCFG26_OUTCFG107_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74417   TIMER_OUTCFG26_OUTCFG107_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74418   TIMER_OUTCFG26_OUTCFG107_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74419 } TIMER_OUTCFG26_OUTCFG107_Enum;
74420 
74421 /* ===========================================  TIMER OUTCFG26 OUTCFG106 [16..21]  =========================================== */
74422 typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG106                                                  */
74423   TIMER_OUTCFG26_OUTCFG106_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74424   TIMER_OUTCFG26_OUTCFG106_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74425   TIMER_OUTCFG26_OUTCFG106_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74426   TIMER_OUTCFG26_OUTCFG106_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74427   TIMER_OUTCFG26_OUTCFG106_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74428   TIMER_OUTCFG26_OUTCFG106_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74429   TIMER_OUTCFG26_OUTCFG106_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74430   TIMER_OUTCFG26_OUTCFG106_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74431   TIMER_OUTCFG26_OUTCFG106_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74432   TIMER_OUTCFG26_OUTCFG106_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74433   TIMER_OUTCFG26_OUTCFG106_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74434   TIMER_OUTCFG26_OUTCFG106_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74435   TIMER_OUTCFG26_OUTCFG106_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74436   TIMER_OUTCFG26_OUTCFG106_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74437   TIMER_OUTCFG26_OUTCFG106_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74438   TIMER_OUTCFG26_OUTCFG106_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74439   TIMER_OUTCFG26_OUTCFG106_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74440   TIMER_OUTCFG26_OUTCFG106_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74441   TIMER_OUTCFG26_OUTCFG106_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74442   TIMER_OUTCFG26_OUTCFG106_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74443   TIMER_OUTCFG26_OUTCFG106_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74444   TIMER_OUTCFG26_OUTCFG106_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74445   TIMER_OUTCFG26_OUTCFG106_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74446   TIMER_OUTCFG26_OUTCFG106_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74447   TIMER_OUTCFG26_OUTCFG106_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74448   TIMER_OUTCFG26_OUTCFG106_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74449   TIMER_OUTCFG26_OUTCFG106_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74450   TIMER_OUTCFG26_OUTCFG106_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74451   TIMER_OUTCFG26_OUTCFG106_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74452   TIMER_OUTCFG26_OUTCFG106_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74453   TIMER_OUTCFG26_OUTCFG106_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74454   TIMER_OUTCFG26_OUTCFG106_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74455   TIMER_OUTCFG26_OUTCFG106_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74456   TIMER_OUTCFG26_OUTCFG106_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74457   TIMER_OUTCFG26_OUTCFG106_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74458   TIMER_OUTCFG26_OUTCFG106_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74459   TIMER_OUTCFG26_OUTCFG106_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74460   TIMER_OUTCFG26_OUTCFG106_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74461   TIMER_OUTCFG26_OUTCFG106_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74462   TIMER_OUTCFG26_OUTCFG106_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74463   TIMER_OUTCFG26_OUTCFG106_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74464 } TIMER_OUTCFG26_OUTCFG106_Enum;
74465 
74466 /* ===========================================  TIMER OUTCFG26 OUTCFG105 [8..13]  ============================================ */
74467 typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG105                                                  */
74468   TIMER_OUTCFG26_OUTCFG105_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74469   TIMER_OUTCFG26_OUTCFG105_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74470   TIMER_OUTCFG26_OUTCFG105_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74471   TIMER_OUTCFG26_OUTCFG105_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74472   TIMER_OUTCFG26_OUTCFG105_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74473   TIMER_OUTCFG26_OUTCFG105_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74474   TIMER_OUTCFG26_OUTCFG105_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74475   TIMER_OUTCFG26_OUTCFG105_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74476   TIMER_OUTCFG26_OUTCFG105_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74477   TIMER_OUTCFG26_OUTCFG105_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74478   TIMER_OUTCFG26_OUTCFG105_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74479   TIMER_OUTCFG26_OUTCFG105_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74480   TIMER_OUTCFG26_OUTCFG105_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74481   TIMER_OUTCFG26_OUTCFG105_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74482   TIMER_OUTCFG26_OUTCFG105_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74483   TIMER_OUTCFG26_OUTCFG105_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74484   TIMER_OUTCFG26_OUTCFG105_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74485   TIMER_OUTCFG26_OUTCFG105_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74486   TIMER_OUTCFG26_OUTCFG105_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74487   TIMER_OUTCFG26_OUTCFG105_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74488   TIMER_OUTCFG26_OUTCFG105_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74489   TIMER_OUTCFG26_OUTCFG105_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74490   TIMER_OUTCFG26_OUTCFG105_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74491   TIMER_OUTCFG26_OUTCFG105_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74492   TIMER_OUTCFG26_OUTCFG105_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74493   TIMER_OUTCFG26_OUTCFG105_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74494   TIMER_OUTCFG26_OUTCFG105_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74495   TIMER_OUTCFG26_OUTCFG105_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74496   TIMER_OUTCFG26_OUTCFG105_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74497   TIMER_OUTCFG26_OUTCFG105_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74498   TIMER_OUTCFG26_OUTCFG105_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74499   TIMER_OUTCFG26_OUTCFG105_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74500   TIMER_OUTCFG26_OUTCFG105_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74501   TIMER_OUTCFG26_OUTCFG105_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74502   TIMER_OUTCFG26_OUTCFG105_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74503   TIMER_OUTCFG26_OUTCFG105_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74504   TIMER_OUTCFG26_OUTCFG105_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74505   TIMER_OUTCFG26_OUTCFG105_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74506   TIMER_OUTCFG26_OUTCFG105_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74507   TIMER_OUTCFG26_OUTCFG105_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74508   TIMER_OUTCFG26_OUTCFG105_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74509 } TIMER_OUTCFG26_OUTCFG105_Enum;
74510 
74511 /* ============================================  TIMER OUTCFG26 OUTCFG104 [0..5]  ============================================ */
74512 typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG104                                                  */
74513   TIMER_OUTCFG26_OUTCFG104_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74514   TIMER_OUTCFG26_OUTCFG104_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74515   TIMER_OUTCFG26_OUTCFG104_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74516   TIMER_OUTCFG26_OUTCFG104_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74517   TIMER_OUTCFG26_OUTCFG104_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74518   TIMER_OUTCFG26_OUTCFG104_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74519   TIMER_OUTCFG26_OUTCFG104_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74520   TIMER_OUTCFG26_OUTCFG104_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74521   TIMER_OUTCFG26_OUTCFG104_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74522   TIMER_OUTCFG26_OUTCFG104_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74523   TIMER_OUTCFG26_OUTCFG104_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74524   TIMER_OUTCFG26_OUTCFG104_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74525   TIMER_OUTCFG26_OUTCFG104_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74526   TIMER_OUTCFG26_OUTCFG104_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74527   TIMER_OUTCFG26_OUTCFG104_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74528   TIMER_OUTCFG26_OUTCFG104_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74529   TIMER_OUTCFG26_OUTCFG104_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74530   TIMER_OUTCFG26_OUTCFG104_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74531   TIMER_OUTCFG26_OUTCFG104_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74532   TIMER_OUTCFG26_OUTCFG104_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74533   TIMER_OUTCFG26_OUTCFG104_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74534   TIMER_OUTCFG26_OUTCFG104_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74535   TIMER_OUTCFG26_OUTCFG104_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74536   TIMER_OUTCFG26_OUTCFG104_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74537   TIMER_OUTCFG26_OUTCFG104_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74538   TIMER_OUTCFG26_OUTCFG104_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74539   TIMER_OUTCFG26_OUTCFG104_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74540   TIMER_OUTCFG26_OUTCFG104_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74541   TIMER_OUTCFG26_OUTCFG104_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74542   TIMER_OUTCFG26_OUTCFG104_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74543   TIMER_OUTCFG26_OUTCFG104_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74544   TIMER_OUTCFG26_OUTCFG104_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74545   TIMER_OUTCFG26_OUTCFG104_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74546   TIMER_OUTCFG26_OUTCFG104_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74547   TIMER_OUTCFG26_OUTCFG104_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74548   TIMER_OUTCFG26_OUTCFG104_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74549   TIMER_OUTCFG26_OUTCFG104_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74550   TIMER_OUTCFG26_OUTCFG104_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74551   TIMER_OUTCFG26_OUTCFG104_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74552   TIMER_OUTCFG26_OUTCFG104_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74553   TIMER_OUTCFG26_OUTCFG104_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74554 } TIMER_OUTCFG26_OUTCFG104_Enum;
74555 
74556 /* =======================================================  OUTCFG27  ======================================================== */
74557 /* ===========================================  TIMER OUTCFG27 OUTCFG111 [24..29]  =========================================== */
74558 typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG111                                                  */
74559   TIMER_OUTCFG27_OUTCFG111_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74560   TIMER_OUTCFG27_OUTCFG111_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74561   TIMER_OUTCFG27_OUTCFG111_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74562   TIMER_OUTCFG27_OUTCFG111_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74563   TIMER_OUTCFG27_OUTCFG111_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74564   TIMER_OUTCFG27_OUTCFG111_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74565   TIMER_OUTCFG27_OUTCFG111_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74566   TIMER_OUTCFG27_OUTCFG111_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74567   TIMER_OUTCFG27_OUTCFG111_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74568   TIMER_OUTCFG27_OUTCFG111_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74569   TIMER_OUTCFG27_OUTCFG111_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74570   TIMER_OUTCFG27_OUTCFG111_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74571   TIMER_OUTCFG27_OUTCFG111_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74572   TIMER_OUTCFG27_OUTCFG111_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74573   TIMER_OUTCFG27_OUTCFG111_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74574   TIMER_OUTCFG27_OUTCFG111_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74575   TIMER_OUTCFG27_OUTCFG111_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74576   TIMER_OUTCFG27_OUTCFG111_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74577   TIMER_OUTCFG27_OUTCFG111_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74578   TIMER_OUTCFG27_OUTCFG111_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74579   TIMER_OUTCFG27_OUTCFG111_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74580   TIMER_OUTCFG27_OUTCFG111_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74581   TIMER_OUTCFG27_OUTCFG111_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74582   TIMER_OUTCFG27_OUTCFG111_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74583   TIMER_OUTCFG27_OUTCFG111_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74584   TIMER_OUTCFG27_OUTCFG111_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74585   TIMER_OUTCFG27_OUTCFG111_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74586   TIMER_OUTCFG27_OUTCFG111_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74587   TIMER_OUTCFG27_OUTCFG111_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74588   TIMER_OUTCFG27_OUTCFG111_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74589   TIMER_OUTCFG27_OUTCFG111_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74590   TIMER_OUTCFG27_OUTCFG111_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74591   TIMER_OUTCFG27_OUTCFG111_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74592   TIMER_OUTCFG27_OUTCFG111_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74593   TIMER_OUTCFG27_OUTCFG111_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74594   TIMER_OUTCFG27_OUTCFG111_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74595   TIMER_OUTCFG27_OUTCFG111_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74596   TIMER_OUTCFG27_OUTCFG111_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74597   TIMER_OUTCFG27_OUTCFG111_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74598   TIMER_OUTCFG27_OUTCFG111_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74599   TIMER_OUTCFG27_OUTCFG111_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74600 } TIMER_OUTCFG27_OUTCFG111_Enum;
74601 
74602 /* ===========================================  TIMER OUTCFG27 OUTCFG110 [16..21]  =========================================== */
74603 typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG110                                                  */
74604   TIMER_OUTCFG27_OUTCFG110_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74605   TIMER_OUTCFG27_OUTCFG110_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74606   TIMER_OUTCFG27_OUTCFG110_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74607   TIMER_OUTCFG27_OUTCFG110_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74608   TIMER_OUTCFG27_OUTCFG110_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74609   TIMER_OUTCFG27_OUTCFG110_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74610   TIMER_OUTCFG27_OUTCFG110_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74611   TIMER_OUTCFG27_OUTCFG110_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74612   TIMER_OUTCFG27_OUTCFG110_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74613   TIMER_OUTCFG27_OUTCFG110_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74614   TIMER_OUTCFG27_OUTCFG110_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74615   TIMER_OUTCFG27_OUTCFG110_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74616   TIMER_OUTCFG27_OUTCFG110_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74617   TIMER_OUTCFG27_OUTCFG110_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74618   TIMER_OUTCFG27_OUTCFG110_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74619   TIMER_OUTCFG27_OUTCFG110_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74620   TIMER_OUTCFG27_OUTCFG110_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74621   TIMER_OUTCFG27_OUTCFG110_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74622   TIMER_OUTCFG27_OUTCFG110_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74623   TIMER_OUTCFG27_OUTCFG110_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74624   TIMER_OUTCFG27_OUTCFG110_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74625   TIMER_OUTCFG27_OUTCFG110_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74626   TIMER_OUTCFG27_OUTCFG110_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74627   TIMER_OUTCFG27_OUTCFG110_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74628   TIMER_OUTCFG27_OUTCFG110_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74629   TIMER_OUTCFG27_OUTCFG110_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74630   TIMER_OUTCFG27_OUTCFG110_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74631   TIMER_OUTCFG27_OUTCFG110_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74632   TIMER_OUTCFG27_OUTCFG110_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74633   TIMER_OUTCFG27_OUTCFG110_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74634   TIMER_OUTCFG27_OUTCFG110_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74635   TIMER_OUTCFG27_OUTCFG110_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74636   TIMER_OUTCFG27_OUTCFG110_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74637   TIMER_OUTCFG27_OUTCFG110_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74638   TIMER_OUTCFG27_OUTCFG110_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74639   TIMER_OUTCFG27_OUTCFG110_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74640   TIMER_OUTCFG27_OUTCFG110_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74641   TIMER_OUTCFG27_OUTCFG110_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74642   TIMER_OUTCFG27_OUTCFG110_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74643   TIMER_OUTCFG27_OUTCFG110_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74644   TIMER_OUTCFG27_OUTCFG110_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74645 } TIMER_OUTCFG27_OUTCFG110_Enum;
74646 
74647 /* ===========================================  TIMER OUTCFG27 OUTCFG109 [8..13]  ============================================ */
74648 typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG109                                                  */
74649   TIMER_OUTCFG27_OUTCFG109_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74650   TIMER_OUTCFG27_OUTCFG109_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74651   TIMER_OUTCFG27_OUTCFG109_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74652   TIMER_OUTCFG27_OUTCFG109_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74653   TIMER_OUTCFG27_OUTCFG109_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74654   TIMER_OUTCFG27_OUTCFG109_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74655   TIMER_OUTCFG27_OUTCFG109_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74656   TIMER_OUTCFG27_OUTCFG109_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74657   TIMER_OUTCFG27_OUTCFG109_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74658   TIMER_OUTCFG27_OUTCFG109_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74659   TIMER_OUTCFG27_OUTCFG109_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74660   TIMER_OUTCFG27_OUTCFG109_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74661   TIMER_OUTCFG27_OUTCFG109_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74662   TIMER_OUTCFG27_OUTCFG109_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74663   TIMER_OUTCFG27_OUTCFG109_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74664   TIMER_OUTCFG27_OUTCFG109_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74665   TIMER_OUTCFG27_OUTCFG109_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74666   TIMER_OUTCFG27_OUTCFG109_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74667   TIMER_OUTCFG27_OUTCFG109_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74668   TIMER_OUTCFG27_OUTCFG109_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74669   TIMER_OUTCFG27_OUTCFG109_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74670   TIMER_OUTCFG27_OUTCFG109_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74671   TIMER_OUTCFG27_OUTCFG109_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74672   TIMER_OUTCFG27_OUTCFG109_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74673   TIMER_OUTCFG27_OUTCFG109_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74674   TIMER_OUTCFG27_OUTCFG109_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74675   TIMER_OUTCFG27_OUTCFG109_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74676   TIMER_OUTCFG27_OUTCFG109_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74677   TIMER_OUTCFG27_OUTCFG109_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74678   TIMER_OUTCFG27_OUTCFG109_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74679   TIMER_OUTCFG27_OUTCFG109_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74680   TIMER_OUTCFG27_OUTCFG109_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74681   TIMER_OUTCFG27_OUTCFG109_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74682   TIMER_OUTCFG27_OUTCFG109_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74683   TIMER_OUTCFG27_OUTCFG109_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74684   TIMER_OUTCFG27_OUTCFG109_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74685   TIMER_OUTCFG27_OUTCFG109_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74686   TIMER_OUTCFG27_OUTCFG109_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74687   TIMER_OUTCFG27_OUTCFG109_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74688   TIMER_OUTCFG27_OUTCFG109_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74689   TIMER_OUTCFG27_OUTCFG109_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74690 } TIMER_OUTCFG27_OUTCFG109_Enum;
74691 
74692 /* ============================================  TIMER OUTCFG27 OUTCFG108 [0..5]  ============================================ */
74693 typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG108                                                  */
74694   TIMER_OUTCFG27_OUTCFG108_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74695   TIMER_OUTCFG27_OUTCFG108_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74696   TIMER_OUTCFG27_OUTCFG108_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74697   TIMER_OUTCFG27_OUTCFG108_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74698   TIMER_OUTCFG27_OUTCFG108_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74699   TIMER_OUTCFG27_OUTCFG108_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74700   TIMER_OUTCFG27_OUTCFG108_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74701   TIMER_OUTCFG27_OUTCFG108_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74702   TIMER_OUTCFG27_OUTCFG108_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74703   TIMER_OUTCFG27_OUTCFG108_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74704   TIMER_OUTCFG27_OUTCFG108_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74705   TIMER_OUTCFG27_OUTCFG108_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74706   TIMER_OUTCFG27_OUTCFG108_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74707   TIMER_OUTCFG27_OUTCFG108_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74708   TIMER_OUTCFG27_OUTCFG108_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74709   TIMER_OUTCFG27_OUTCFG108_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74710   TIMER_OUTCFG27_OUTCFG108_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74711   TIMER_OUTCFG27_OUTCFG108_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74712   TIMER_OUTCFG27_OUTCFG108_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74713   TIMER_OUTCFG27_OUTCFG108_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74714   TIMER_OUTCFG27_OUTCFG108_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74715   TIMER_OUTCFG27_OUTCFG108_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74716   TIMER_OUTCFG27_OUTCFG108_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74717   TIMER_OUTCFG27_OUTCFG108_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74718   TIMER_OUTCFG27_OUTCFG108_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74719   TIMER_OUTCFG27_OUTCFG108_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74720   TIMER_OUTCFG27_OUTCFG108_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74721   TIMER_OUTCFG27_OUTCFG108_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74722   TIMER_OUTCFG27_OUTCFG108_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74723   TIMER_OUTCFG27_OUTCFG108_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74724   TIMER_OUTCFG27_OUTCFG108_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74725   TIMER_OUTCFG27_OUTCFG108_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74726   TIMER_OUTCFG27_OUTCFG108_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74727   TIMER_OUTCFG27_OUTCFG108_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74728   TIMER_OUTCFG27_OUTCFG108_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74729   TIMER_OUTCFG27_OUTCFG108_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74730   TIMER_OUTCFG27_OUTCFG108_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74731   TIMER_OUTCFG27_OUTCFG108_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74732   TIMER_OUTCFG27_OUTCFG108_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74733   TIMER_OUTCFG27_OUTCFG108_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74734   TIMER_OUTCFG27_OUTCFG108_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74735 } TIMER_OUTCFG27_OUTCFG108_Enum;
74736 
74737 /* =======================================================  OUTCFG28  ======================================================== */
74738 /* ===========================================  TIMER OUTCFG28 OUTCFG115 [24..29]  =========================================== */
74739 typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG115                                                  */
74740   TIMER_OUTCFG28_OUTCFG115_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74741   TIMER_OUTCFG28_OUTCFG115_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74742   TIMER_OUTCFG28_OUTCFG115_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74743   TIMER_OUTCFG28_OUTCFG115_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74744   TIMER_OUTCFG28_OUTCFG115_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74745   TIMER_OUTCFG28_OUTCFG115_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74746   TIMER_OUTCFG28_OUTCFG115_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74747   TIMER_OUTCFG28_OUTCFG115_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74748   TIMER_OUTCFG28_OUTCFG115_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74749   TIMER_OUTCFG28_OUTCFG115_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74750   TIMER_OUTCFG28_OUTCFG115_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74751   TIMER_OUTCFG28_OUTCFG115_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74752   TIMER_OUTCFG28_OUTCFG115_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74753   TIMER_OUTCFG28_OUTCFG115_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74754   TIMER_OUTCFG28_OUTCFG115_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74755   TIMER_OUTCFG28_OUTCFG115_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74756   TIMER_OUTCFG28_OUTCFG115_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74757   TIMER_OUTCFG28_OUTCFG115_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74758   TIMER_OUTCFG28_OUTCFG115_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74759   TIMER_OUTCFG28_OUTCFG115_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74760   TIMER_OUTCFG28_OUTCFG115_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74761   TIMER_OUTCFG28_OUTCFG115_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74762   TIMER_OUTCFG28_OUTCFG115_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74763   TIMER_OUTCFG28_OUTCFG115_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74764   TIMER_OUTCFG28_OUTCFG115_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74765   TIMER_OUTCFG28_OUTCFG115_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74766   TIMER_OUTCFG28_OUTCFG115_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74767   TIMER_OUTCFG28_OUTCFG115_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74768   TIMER_OUTCFG28_OUTCFG115_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74769   TIMER_OUTCFG28_OUTCFG115_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74770   TIMER_OUTCFG28_OUTCFG115_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74771   TIMER_OUTCFG28_OUTCFG115_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74772   TIMER_OUTCFG28_OUTCFG115_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74773   TIMER_OUTCFG28_OUTCFG115_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74774   TIMER_OUTCFG28_OUTCFG115_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74775   TIMER_OUTCFG28_OUTCFG115_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74776   TIMER_OUTCFG28_OUTCFG115_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74777   TIMER_OUTCFG28_OUTCFG115_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74778   TIMER_OUTCFG28_OUTCFG115_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74779   TIMER_OUTCFG28_OUTCFG115_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74780   TIMER_OUTCFG28_OUTCFG115_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74781 } TIMER_OUTCFG28_OUTCFG115_Enum;
74782 
74783 /* ===========================================  TIMER OUTCFG28 OUTCFG114 [16..21]  =========================================== */
74784 typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG114                                                  */
74785   TIMER_OUTCFG28_OUTCFG114_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74786   TIMER_OUTCFG28_OUTCFG114_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74787   TIMER_OUTCFG28_OUTCFG114_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74788   TIMER_OUTCFG28_OUTCFG114_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74789   TIMER_OUTCFG28_OUTCFG114_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74790   TIMER_OUTCFG28_OUTCFG114_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74791   TIMER_OUTCFG28_OUTCFG114_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74792   TIMER_OUTCFG28_OUTCFG114_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74793   TIMER_OUTCFG28_OUTCFG114_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74794   TIMER_OUTCFG28_OUTCFG114_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74795   TIMER_OUTCFG28_OUTCFG114_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74796   TIMER_OUTCFG28_OUTCFG114_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74797   TIMER_OUTCFG28_OUTCFG114_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74798   TIMER_OUTCFG28_OUTCFG114_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74799   TIMER_OUTCFG28_OUTCFG114_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74800   TIMER_OUTCFG28_OUTCFG114_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74801   TIMER_OUTCFG28_OUTCFG114_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74802   TIMER_OUTCFG28_OUTCFG114_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74803   TIMER_OUTCFG28_OUTCFG114_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74804   TIMER_OUTCFG28_OUTCFG114_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74805   TIMER_OUTCFG28_OUTCFG114_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74806   TIMER_OUTCFG28_OUTCFG114_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74807   TIMER_OUTCFG28_OUTCFG114_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74808   TIMER_OUTCFG28_OUTCFG114_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74809   TIMER_OUTCFG28_OUTCFG114_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74810   TIMER_OUTCFG28_OUTCFG114_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74811   TIMER_OUTCFG28_OUTCFG114_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74812   TIMER_OUTCFG28_OUTCFG114_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74813   TIMER_OUTCFG28_OUTCFG114_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74814   TIMER_OUTCFG28_OUTCFG114_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74815   TIMER_OUTCFG28_OUTCFG114_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74816   TIMER_OUTCFG28_OUTCFG114_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74817   TIMER_OUTCFG28_OUTCFG114_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74818   TIMER_OUTCFG28_OUTCFG114_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74819   TIMER_OUTCFG28_OUTCFG114_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74820   TIMER_OUTCFG28_OUTCFG114_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74821   TIMER_OUTCFG28_OUTCFG114_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74822   TIMER_OUTCFG28_OUTCFG114_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74823   TIMER_OUTCFG28_OUTCFG114_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74824   TIMER_OUTCFG28_OUTCFG114_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74825   TIMER_OUTCFG28_OUTCFG114_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74826 } TIMER_OUTCFG28_OUTCFG114_Enum;
74827 
74828 /* ===========================================  TIMER OUTCFG28 OUTCFG113 [8..13]  ============================================ */
74829 typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG113                                                  */
74830   TIMER_OUTCFG28_OUTCFG113_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74831   TIMER_OUTCFG28_OUTCFG113_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74832   TIMER_OUTCFG28_OUTCFG113_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74833   TIMER_OUTCFG28_OUTCFG113_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74834   TIMER_OUTCFG28_OUTCFG113_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74835   TIMER_OUTCFG28_OUTCFG113_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74836   TIMER_OUTCFG28_OUTCFG113_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74837   TIMER_OUTCFG28_OUTCFG113_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74838   TIMER_OUTCFG28_OUTCFG113_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74839   TIMER_OUTCFG28_OUTCFG113_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74840   TIMER_OUTCFG28_OUTCFG113_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74841   TIMER_OUTCFG28_OUTCFG113_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74842   TIMER_OUTCFG28_OUTCFG113_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74843   TIMER_OUTCFG28_OUTCFG113_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74844   TIMER_OUTCFG28_OUTCFG113_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74845   TIMER_OUTCFG28_OUTCFG113_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74846   TIMER_OUTCFG28_OUTCFG113_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74847   TIMER_OUTCFG28_OUTCFG113_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74848   TIMER_OUTCFG28_OUTCFG113_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74849   TIMER_OUTCFG28_OUTCFG113_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74850   TIMER_OUTCFG28_OUTCFG113_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74851   TIMER_OUTCFG28_OUTCFG113_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74852   TIMER_OUTCFG28_OUTCFG113_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74853   TIMER_OUTCFG28_OUTCFG113_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74854   TIMER_OUTCFG28_OUTCFG113_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74855   TIMER_OUTCFG28_OUTCFG113_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74856   TIMER_OUTCFG28_OUTCFG113_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74857   TIMER_OUTCFG28_OUTCFG113_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74858   TIMER_OUTCFG28_OUTCFG113_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74859   TIMER_OUTCFG28_OUTCFG113_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74860   TIMER_OUTCFG28_OUTCFG113_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74861   TIMER_OUTCFG28_OUTCFG113_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74862   TIMER_OUTCFG28_OUTCFG113_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74863   TIMER_OUTCFG28_OUTCFG113_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74864   TIMER_OUTCFG28_OUTCFG113_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74865   TIMER_OUTCFG28_OUTCFG113_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74866   TIMER_OUTCFG28_OUTCFG113_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74867   TIMER_OUTCFG28_OUTCFG113_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74868   TIMER_OUTCFG28_OUTCFG113_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74869   TIMER_OUTCFG28_OUTCFG113_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74870   TIMER_OUTCFG28_OUTCFG113_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74871 } TIMER_OUTCFG28_OUTCFG113_Enum;
74872 
74873 /* ============================================  TIMER OUTCFG28 OUTCFG112 [0..5]  ============================================ */
74874 typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG112                                                  */
74875   TIMER_OUTCFG28_OUTCFG112_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74876   TIMER_OUTCFG28_OUTCFG112_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74877   TIMER_OUTCFG28_OUTCFG112_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74878   TIMER_OUTCFG28_OUTCFG112_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74879   TIMER_OUTCFG28_OUTCFG112_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74880   TIMER_OUTCFG28_OUTCFG112_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74881   TIMER_OUTCFG28_OUTCFG112_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74882   TIMER_OUTCFG28_OUTCFG112_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74883   TIMER_OUTCFG28_OUTCFG112_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74884   TIMER_OUTCFG28_OUTCFG112_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74885   TIMER_OUTCFG28_OUTCFG112_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74886   TIMER_OUTCFG28_OUTCFG112_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74887   TIMER_OUTCFG28_OUTCFG112_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74888   TIMER_OUTCFG28_OUTCFG112_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74889   TIMER_OUTCFG28_OUTCFG112_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74890   TIMER_OUTCFG28_OUTCFG112_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74891   TIMER_OUTCFG28_OUTCFG112_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74892   TIMER_OUTCFG28_OUTCFG112_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74893   TIMER_OUTCFG28_OUTCFG112_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74894   TIMER_OUTCFG28_OUTCFG112_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74895   TIMER_OUTCFG28_OUTCFG112_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74896   TIMER_OUTCFG28_OUTCFG112_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74897   TIMER_OUTCFG28_OUTCFG112_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74898   TIMER_OUTCFG28_OUTCFG112_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74899   TIMER_OUTCFG28_OUTCFG112_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74900   TIMER_OUTCFG28_OUTCFG112_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74901   TIMER_OUTCFG28_OUTCFG112_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74902   TIMER_OUTCFG28_OUTCFG112_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74903   TIMER_OUTCFG28_OUTCFG112_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74904   TIMER_OUTCFG28_OUTCFG112_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74905   TIMER_OUTCFG28_OUTCFG112_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74906   TIMER_OUTCFG28_OUTCFG112_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74907   TIMER_OUTCFG28_OUTCFG112_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74908   TIMER_OUTCFG28_OUTCFG112_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74909   TIMER_OUTCFG28_OUTCFG112_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74910   TIMER_OUTCFG28_OUTCFG112_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74911   TIMER_OUTCFG28_OUTCFG112_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74912   TIMER_OUTCFG28_OUTCFG112_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74913   TIMER_OUTCFG28_OUTCFG112_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74914   TIMER_OUTCFG28_OUTCFG112_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74915   TIMER_OUTCFG28_OUTCFG112_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74916 } TIMER_OUTCFG28_OUTCFG112_Enum;
74917 
74918 /* =======================================================  OUTCFG29  ======================================================== */
74919 /* ===========================================  TIMER OUTCFG29 OUTCFG119 [24..29]  =========================================== */
74920 typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG119                                                  */
74921   TIMER_OUTCFG29_OUTCFG119_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74922   TIMER_OUTCFG29_OUTCFG119_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74923   TIMER_OUTCFG29_OUTCFG119_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74924   TIMER_OUTCFG29_OUTCFG119_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74925   TIMER_OUTCFG29_OUTCFG119_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74926   TIMER_OUTCFG29_OUTCFG119_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74927   TIMER_OUTCFG29_OUTCFG119_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74928   TIMER_OUTCFG29_OUTCFG119_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74929   TIMER_OUTCFG29_OUTCFG119_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74930   TIMER_OUTCFG29_OUTCFG119_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74931   TIMER_OUTCFG29_OUTCFG119_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74932   TIMER_OUTCFG29_OUTCFG119_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74933   TIMER_OUTCFG29_OUTCFG119_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74934   TIMER_OUTCFG29_OUTCFG119_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74935   TIMER_OUTCFG29_OUTCFG119_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74936   TIMER_OUTCFG29_OUTCFG119_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74937   TIMER_OUTCFG29_OUTCFG119_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74938   TIMER_OUTCFG29_OUTCFG119_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74939   TIMER_OUTCFG29_OUTCFG119_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74940   TIMER_OUTCFG29_OUTCFG119_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74941   TIMER_OUTCFG29_OUTCFG119_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74942   TIMER_OUTCFG29_OUTCFG119_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74943   TIMER_OUTCFG29_OUTCFG119_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74944   TIMER_OUTCFG29_OUTCFG119_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74945   TIMER_OUTCFG29_OUTCFG119_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74946   TIMER_OUTCFG29_OUTCFG119_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74947   TIMER_OUTCFG29_OUTCFG119_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74948   TIMER_OUTCFG29_OUTCFG119_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74949   TIMER_OUTCFG29_OUTCFG119_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74950   TIMER_OUTCFG29_OUTCFG119_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74951   TIMER_OUTCFG29_OUTCFG119_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74952   TIMER_OUTCFG29_OUTCFG119_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74953   TIMER_OUTCFG29_OUTCFG119_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74954   TIMER_OUTCFG29_OUTCFG119_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
74955   TIMER_OUTCFG29_OUTCFG119_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
74956   TIMER_OUTCFG29_OUTCFG119_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
74957   TIMER_OUTCFG29_OUTCFG119_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
74958   TIMER_OUTCFG29_OUTCFG119_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
74959   TIMER_OUTCFG29_OUTCFG119_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
74960   TIMER_OUTCFG29_OUTCFG119_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
74961   TIMER_OUTCFG29_OUTCFG119_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
74962 } TIMER_OUTCFG29_OUTCFG119_Enum;
74963 
74964 /* ===========================================  TIMER OUTCFG29 OUTCFG118 [16..21]  =========================================== */
74965 typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG118                                                  */
74966   TIMER_OUTCFG29_OUTCFG118_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
74967   TIMER_OUTCFG29_OUTCFG118_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
74968   TIMER_OUTCFG29_OUTCFG118_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
74969   TIMER_OUTCFG29_OUTCFG118_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
74970   TIMER_OUTCFG29_OUTCFG118_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
74971   TIMER_OUTCFG29_OUTCFG118_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
74972   TIMER_OUTCFG29_OUTCFG118_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
74973   TIMER_OUTCFG29_OUTCFG118_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
74974   TIMER_OUTCFG29_OUTCFG118_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
74975   TIMER_OUTCFG29_OUTCFG118_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
74976   TIMER_OUTCFG29_OUTCFG118_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
74977   TIMER_OUTCFG29_OUTCFG118_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
74978   TIMER_OUTCFG29_OUTCFG118_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
74979   TIMER_OUTCFG29_OUTCFG118_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
74980   TIMER_OUTCFG29_OUTCFG118_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
74981   TIMER_OUTCFG29_OUTCFG118_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
74982   TIMER_OUTCFG29_OUTCFG118_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
74983   TIMER_OUTCFG29_OUTCFG118_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
74984   TIMER_OUTCFG29_OUTCFG118_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
74985   TIMER_OUTCFG29_OUTCFG118_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
74986   TIMER_OUTCFG29_OUTCFG118_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
74987   TIMER_OUTCFG29_OUTCFG118_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
74988   TIMER_OUTCFG29_OUTCFG118_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
74989   TIMER_OUTCFG29_OUTCFG118_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
74990   TIMER_OUTCFG29_OUTCFG118_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
74991   TIMER_OUTCFG29_OUTCFG118_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
74992   TIMER_OUTCFG29_OUTCFG118_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
74993   TIMER_OUTCFG29_OUTCFG118_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
74994   TIMER_OUTCFG29_OUTCFG118_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
74995   TIMER_OUTCFG29_OUTCFG118_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
74996   TIMER_OUTCFG29_OUTCFG118_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
74997   TIMER_OUTCFG29_OUTCFG118_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
74998   TIMER_OUTCFG29_OUTCFG118_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
74999   TIMER_OUTCFG29_OUTCFG118_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75000   TIMER_OUTCFG29_OUTCFG118_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75001   TIMER_OUTCFG29_OUTCFG118_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75002   TIMER_OUTCFG29_OUTCFG118_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75003   TIMER_OUTCFG29_OUTCFG118_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75004   TIMER_OUTCFG29_OUTCFG118_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75005   TIMER_OUTCFG29_OUTCFG118_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75006   TIMER_OUTCFG29_OUTCFG118_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75007 } TIMER_OUTCFG29_OUTCFG118_Enum;
75008 
75009 /* ===========================================  TIMER OUTCFG29 OUTCFG117 [8..13]  ============================================ */
75010 typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG117                                                  */
75011   TIMER_OUTCFG29_OUTCFG117_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75012   TIMER_OUTCFG29_OUTCFG117_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75013   TIMER_OUTCFG29_OUTCFG117_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75014   TIMER_OUTCFG29_OUTCFG117_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75015   TIMER_OUTCFG29_OUTCFG117_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75016   TIMER_OUTCFG29_OUTCFG117_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75017   TIMER_OUTCFG29_OUTCFG117_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75018   TIMER_OUTCFG29_OUTCFG117_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75019   TIMER_OUTCFG29_OUTCFG117_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75020   TIMER_OUTCFG29_OUTCFG117_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75021   TIMER_OUTCFG29_OUTCFG117_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75022   TIMER_OUTCFG29_OUTCFG117_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75023   TIMER_OUTCFG29_OUTCFG117_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75024   TIMER_OUTCFG29_OUTCFG117_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75025   TIMER_OUTCFG29_OUTCFG117_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75026   TIMER_OUTCFG29_OUTCFG117_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75027   TIMER_OUTCFG29_OUTCFG117_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75028   TIMER_OUTCFG29_OUTCFG117_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75029   TIMER_OUTCFG29_OUTCFG117_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75030   TIMER_OUTCFG29_OUTCFG117_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75031   TIMER_OUTCFG29_OUTCFG117_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75032   TIMER_OUTCFG29_OUTCFG117_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75033   TIMER_OUTCFG29_OUTCFG117_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75034   TIMER_OUTCFG29_OUTCFG117_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75035   TIMER_OUTCFG29_OUTCFG117_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75036   TIMER_OUTCFG29_OUTCFG117_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75037   TIMER_OUTCFG29_OUTCFG117_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75038   TIMER_OUTCFG29_OUTCFG117_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75039   TIMER_OUTCFG29_OUTCFG117_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75040   TIMER_OUTCFG29_OUTCFG117_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75041   TIMER_OUTCFG29_OUTCFG117_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75042   TIMER_OUTCFG29_OUTCFG117_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75043   TIMER_OUTCFG29_OUTCFG117_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75044   TIMER_OUTCFG29_OUTCFG117_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75045   TIMER_OUTCFG29_OUTCFG117_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75046   TIMER_OUTCFG29_OUTCFG117_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75047   TIMER_OUTCFG29_OUTCFG117_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75048   TIMER_OUTCFG29_OUTCFG117_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75049   TIMER_OUTCFG29_OUTCFG117_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75050   TIMER_OUTCFG29_OUTCFG117_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75051   TIMER_OUTCFG29_OUTCFG117_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75052 } TIMER_OUTCFG29_OUTCFG117_Enum;
75053 
75054 /* ============================================  TIMER OUTCFG29 OUTCFG116 [0..5]  ============================================ */
75055 typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG116                                                  */
75056   TIMER_OUTCFG29_OUTCFG116_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75057   TIMER_OUTCFG29_OUTCFG116_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75058   TIMER_OUTCFG29_OUTCFG116_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75059   TIMER_OUTCFG29_OUTCFG116_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75060   TIMER_OUTCFG29_OUTCFG116_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75061   TIMER_OUTCFG29_OUTCFG116_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75062   TIMER_OUTCFG29_OUTCFG116_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75063   TIMER_OUTCFG29_OUTCFG116_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75064   TIMER_OUTCFG29_OUTCFG116_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75065   TIMER_OUTCFG29_OUTCFG116_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75066   TIMER_OUTCFG29_OUTCFG116_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75067   TIMER_OUTCFG29_OUTCFG116_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75068   TIMER_OUTCFG29_OUTCFG116_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75069   TIMER_OUTCFG29_OUTCFG116_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75070   TIMER_OUTCFG29_OUTCFG116_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75071   TIMER_OUTCFG29_OUTCFG116_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75072   TIMER_OUTCFG29_OUTCFG116_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75073   TIMER_OUTCFG29_OUTCFG116_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75074   TIMER_OUTCFG29_OUTCFG116_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75075   TIMER_OUTCFG29_OUTCFG116_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75076   TIMER_OUTCFG29_OUTCFG116_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75077   TIMER_OUTCFG29_OUTCFG116_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75078   TIMER_OUTCFG29_OUTCFG116_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75079   TIMER_OUTCFG29_OUTCFG116_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75080   TIMER_OUTCFG29_OUTCFG116_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75081   TIMER_OUTCFG29_OUTCFG116_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75082   TIMER_OUTCFG29_OUTCFG116_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75083   TIMER_OUTCFG29_OUTCFG116_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75084   TIMER_OUTCFG29_OUTCFG116_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75085   TIMER_OUTCFG29_OUTCFG116_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75086   TIMER_OUTCFG29_OUTCFG116_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75087   TIMER_OUTCFG29_OUTCFG116_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75088   TIMER_OUTCFG29_OUTCFG116_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75089   TIMER_OUTCFG29_OUTCFG116_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75090   TIMER_OUTCFG29_OUTCFG116_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75091   TIMER_OUTCFG29_OUTCFG116_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75092   TIMER_OUTCFG29_OUTCFG116_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75093   TIMER_OUTCFG29_OUTCFG116_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75094   TIMER_OUTCFG29_OUTCFG116_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75095   TIMER_OUTCFG29_OUTCFG116_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75096   TIMER_OUTCFG29_OUTCFG116_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75097 } TIMER_OUTCFG29_OUTCFG116_Enum;
75098 
75099 /* =======================================================  OUTCFG30  ======================================================== */
75100 /* ===========================================  TIMER OUTCFG30 OUTCFG123 [24..29]  =========================================== */
75101 typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG123                                                  */
75102   TIMER_OUTCFG30_OUTCFG123_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75103   TIMER_OUTCFG30_OUTCFG123_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75104   TIMER_OUTCFG30_OUTCFG123_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75105   TIMER_OUTCFG30_OUTCFG123_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75106   TIMER_OUTCFG30_OUTCFG123_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75107   TIMER_OUTCFG30_OUTCFG123_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75108   TIMER_OUTCFG30_OUTCFG123_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75109   TIMER_OUTCFG30_OUTCFG123_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75110   TIMER_OUTCFG30_OUTCFG123_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75111   TIMER_OUTCFG30_OUTCFG123_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75112   TIMER_OUTCFG30_OUTCFG123_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75113   TIMER_OUTCFG30_OUTCFG123_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75114   TIMER_OUTCFG30_OUTCFG123_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75115   TIMER_OUTCFG30_OUTCFG123_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75116   TIMER_OUTCFG30_OUTCFG123_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75117   TIMER_OUTCFG30_OUTCFG123_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75118   TIMER_OUTCFG30_OUTCFG123_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75119   TIMER_OUTCFG30_OUTCFG123_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75120   TIMER_OUTCFG30_OUTCFG123_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75121   TIMER_OUTCFG30_OUTCFG123_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75122   TIMER_OUTCFG30_OUTCFG123_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75123   TIMER_OUTCFG30_OUTCFG123_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75124   TIMER_OUTCFG30_OUTCFG123_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75125   TIMER_OUTCFG30_OUTCFG123_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75126   TIMER_OUTCFG30_OUTCFG123_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75127   TIMER_OUTCFG30_OUTCFG123_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75128   TIMER_OUTCFG30_OUTCFG123_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75129   TIMER_OUTCFG30_OUTCFG123_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75130   TIMER_OUTCFG30_OUTCFG123_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75131   TIMER_OUTCFG30_OUTCFG123_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75132   TIMER_OUTCFG30_OUTCFG123_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75133   TIMER_OUTCFG30_OUTCFG123_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75134   TIMER_OUTCFG30_OUTCFG123_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75135   TIMER_OUTCFG30_OUTCFG123_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75136   TIMER_OUTCFG30_OUTCFG123_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75137   TIMER_OUTCFG30_OUTCFG123_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75138   TIMER_OUTCFG30_OUTCFG123_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75139   TIMER_OUTCFG30_OUTCFG123_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75140   TIMER_OUTCFG30_OUTCFG123_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75141   TIMER_OUTCFG30_OUTCFG123_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75142   TIMER_OUTCFG30_OUTCFG123_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75143 } TIMER_OUTCFG30_OUTCFG123_Enum;
75144 
75145 /* ===========================================  TIMER OUTCFG30 OUTCFG122 [16..21]  =========================================== */
75146 typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG122                                                  */
75147   TIMER_OUTCFG30_OUTCFG122_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75148   TIMER_OUTCFG30_OUTCFG122_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75149   TIMER_OUTCFG30_OUTCFG122_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75150   TIMER_OUTCFG30_OUTCFG122_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75151   TIMER_OUTCFG30_OUTCFG122_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75152   TIMER_OUTCFG30_OUTCFG122_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75153   TIMER_OUTCFG30_OUTCFG122_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75154   TIMER_OUTCFG30_OUTCFG122_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75155   TIMER_OUTCFG30_OUTCFG122_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75156   TIMER_OUTCFG30_OUTCFG122_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75157   TIMER_OUTCFG30_OUTCFG122_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75158   TIMER_OUTCFG30_OUTCFG122_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75159   TIMER_OUTCFG30_OUTCFG122_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75160   TIMER_OUTCFG30_OUTCFG122_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75161   TIMER_OUTCFG30_OUTCFG122_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75162   TIMER_OUTCFG30_OUTCFG122_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75163   TIMER_OUTCFG30_OUTCFG122_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75164   TIMER_OUTCFG30_OUTCFG122_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75165   TIMER_OUTCFG30_OUTCFG122_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75166   TIMER_OUTCFG30_OUTCFG122_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75167   TIMER_OUTCFG30_OUTCFG122_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75168   TIMER_OUTCFG30_OUTCFG122_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75169   TIMER_OUTCFG30_OUTCFG122_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75170   TIMER_OUTCFG30_OUTCFG122_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75171   TIMER_OUTCFG30_OUTCFG122_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75172   TIMER_OUTCFG30_OUTCFG122_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75173   TIMER_OUTCFG30_OUTCFG122_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75174   TIMER_OUTCFG30_OUTCFG122_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75175   TIMER_OUTCFG30_OUTCFG122_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75176   TIMER_OUTCFG30_OUTCFG122_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75177   TIMER_OUTCFG30_OUTCFG122_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75178   TIMER_OUTCFG30_OUTCFG122_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75179   TIMER_OUTCFG30_OUTCFG122_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75180   TIMER_OUTCFG30_OUTCFG122_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75181   TIMER_OUTCFG30_OUTCFG122_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75182   TIMER_OUTCFG30_OUTCFG122_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75183   TIMER_OUTCFG30_OUTCFG122_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75184   TIMER_OUTCFG30_OUTCFG122_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75185   TIMER_OUTCFG30_OUTCFG122_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75186   TIMER_OUTCFG30_OUTCFG122_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75187   TIMER_OUTCFG30_OUTCFG122_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75188 } TIMER_OUTCFG30_OUTCFG122_Enum;
75189 
75190 /* ===========================================  TIMER OUTCFG30 OUTCFG121 [8..13]  ============================================ */
75191 typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG121                                                  */
75192   TIMER_OUTCFG30_OUTCFG121_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75193   TIMER_OUTCFG30_OUTCFG121_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75194   TIMER_OUTCFG30_OUTCFG121_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75195   TIMER_OUTCFG30_OUTCFG121_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75196   TIMER_OUTCFG30_OUTCFG121_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75197   TIMER_OUTCFG30_OUTCFG121_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75198   TIMER_OUTCFG30_OUTCFG121_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75199   TIMER_OUTCFG30_OUTCFG121_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75200   TIMER_OUTCFG30_OUTCFG121_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75201   TIMER_OUTCFG30_OUTCFG121_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75202   TIMER_OUTCFG30_OUTCFG121_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75203   TIMER_OUTCFG30_OUTCFG121_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75204   TIMER_OUTCFG30_OUTCFG121_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75205   TIMER_OUTCFG30_OUTCFG121_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75206   TIMER_OUTCFG30_OUTCFG121_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75207   TIMER_OUTCFG30_OUTCFG121_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75208   TIMER_OUTCFG30_OUTCFG121_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75209   TIMER_OUTCFG30_OUTCFG121_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75210   TIMER_OUTCFG30_OUTCFG121_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75211   TIMER_OUTCFG30_OUTCFG121_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75212   TIMER_OUTCFG30_OUTCFG121_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75213   TIMER_OUTCFG30_OUTCFG121_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75214   TIMER_OUTCFG30_OUTCFG121_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75215   TIMER_OUTCFG30_OUTCFG121_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75216   TIMER_OUTCFG30_OUTCFG121_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75217   TIMER_OUTCFG30_OUTCFG121_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75218   TIMER_OUTCFG30_OUTCFG121_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75219   TIMER_OUTCFG30_OUTCFG121_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75220   TIMER_OUTCFG30_OUTCFG121_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75221   TIMER_OUTCFG30_OUTCFG121_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75222   TIMER_OUTCFG30_OUTCFG121_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75223   TIMER_OUTCFG30_OUTCFG121_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75224   TIMER_OUTCFG30_OUTCFG121_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75225   TIMER_OUTCFG30_OUTCFG121_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75226   TIMER_OUTCFG30_OUTCFG121_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75227   TIMER_OUTCFG30_OUTCFG121_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75228   TIMER_OUTCFG30_OUTCFG121_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75229   TIMER_OUTCFG30_OUTCFG121_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75230   TIMER_OUTCFG30_OUTCFG121_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75231   TIMER_OUTCFG30_OUTCFG121_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75232   TIMER_OUTCFG30_OUTCFG121_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75233 } TIMER_OUTCFG30_OUTCFG121_Enum;
75234 
75235 /* ============================================  TIMER OUTCFG30 OUTCFG120 [0..5]  ============================================ */
75236 typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG120                                                  */
75237   TIMER_OUTCFG30_OUTCFG120_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75238   TIMER_OUTCFG30_OUTCFG120_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75239   TIMER_OUTCFG30_OUTCFG120_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75240   TIMER_OUTCFG30_OUTCFG120_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75241   TIMER_OUTCFG30_OUTCFG120_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75242   TIMER_OUTCFG30_OUTCFG120_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75243   TIMER_OUTCFG30_OUTCFG120_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75244   TIMER_OUTCFG30_OUTCFG120_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75245   TIMER_OUTCFG30_OUTCFG120_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75246   TIMER_OUTCFG30_OUTCFG120_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75247   TIMER_OUTCFG30_OUTCFG120_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75248   TIMER_OUTCFG30_OUTCFG120_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75249   TIMER_OUTCFG30_OUTCFG120_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75250   TIMER_OUTCFG30_OUTCFG120_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75251   TIMER_OUTCFG30_OUTCFG120_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75252   TIMER_OUTCFG30_OUTCFG120_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75253   TIMER_OUTCFG30_OUTCFG120_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75254   TIMER_OUTCFG30_OUTCFG120_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75255   TIMER_OUTCFG30_OUTCFG120_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75256   TIMER_OUTCFG30_OUTCFG120_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75257   TIMER_OUTCFG30_OUTCFG120_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75258   TIMER_OUTCFG30_OUTCFG120_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75259   TIMER_OUTCFG30_OUTCFG120_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75260   TIMER_OUTCFG30_OUTCFG120_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75261   TIMER_OUTCFG30_OUTCFG120_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75262   TIMER_OUTCFG30_OUTCFG120_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75263   TIMER_OUTCFG30_OUTCFG120_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75264   TIMER_OUTCFG30_OUTCFG120_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75265   TIMER_OUTCFG30_OUTCFG120_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75266   TIMER_OUTCFG30_OUTCFG120_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75267   TIMER_OUTCFG30_OUTCFG120_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75268   TIMER_OUTCFG30_OUTCFG120_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75269   TIMER_OUTCFG30_OUTCFG120_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75270   TIMER_OUTCFG30_OUTCFG120_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75271   TIMER_OUTCFG30_OUTCFG120_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75272   TIMER_OUTCFG30_OUTCFG120_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75273   TIMER_OUTCFG30_OUTCFG120_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75274   TIMER_OUTCFG30_OUTCFG120_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75275   TIMER_OUTCFG30_OUTCFG120_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75276   TIMER_OUTCFG30_OUTCFG120_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75277   TIMER_OUTCFG30_OUTCFG120_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75278 } TIMER_OUTCFG30_OUTCFG120_Enum;
75279 
75280 /* =======================================================  OUTCFG31  ======================================================== */
75281 /* ===========================================  TIMER OUTCFG31 OUTCFG127 [24..29]  =========================================== */
75282 typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG127                                                  */
75283   TIMER_OUTCFG31_OUTCFG127_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75284   TIMER_OUTCFG31_OUTCFG127_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75285   TIMER_OUTCFG31_OUTCFG127_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75286   TIMER_OUTCFG31_OUTCFG127_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75287   TIMER_OUTCFG31_OUTCFG127_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75288   TIMER_OUTCFG31_OUTCFG127_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75289   TIMER_OUTCFG31_OUTCFG127_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75290   TIMER_OUTCFG31_OUTCFG127_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75291   TIMER_OUTCFG31_OUTCFG127_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75292   TIMER_OUTCFG31_OUTCFG127_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75293   TIMER_OUTCFG31_OUTCFG127_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75294   TIMER_OUTCFG31_OUTCFG127_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75295   TIMER_OUTCFG31_OUTCFG127_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75296   TIMER_OUTCFG31_OUTCFG127_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75297   TIMER_OUTCFG31_OUTCFG127_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75298   TIMER_OUTCFG31_OUTCFG127_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75299   TIMER_OUTCFG31_OUTCFG127_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75300   TIMER_OUTCFG31_OUTCFG127_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75301   TIMER_OUTCFG31_OUTCFG127_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75302   TIMER_OUTCFG31_OUTCFG127_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75303   TIMER_OUTCFG31_OUTCFG127_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75304   TIMER_OUTCFG31_OUTCFG127_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75305   TIMER_OUTCFG31_OUTCFG127_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75306   TIMER_OUTCFG31_OUTCFG127_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75307   TIMER_OUTCFG31_OUTCFG127_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75308   TIMER_OUTCFG31_OUTCFG127_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75309   TIMER_OUTCFG31_OUTCFG127_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75310   TIMER_OUTCFG31_OUTCFG127_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75311   TIMER_OUTCFG31_OUTCFG127_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75312   TIMER_OUTCFG31_OUTCFG127_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75313   TIMER_OUTCFG31_OUTCFG127_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75314   TIMER_OUTCFG31_OUTCFG127_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75315   TIMER_OUTCFG31_OUTCFG127_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75316   TIMER_OUTCFG31_OUTCFG127_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75317   TIMER_OUTCFG31_OUTCFG127_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75318   TIMER_OUTCFG31_OUTCFG127_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75319   TIMER_OUTCFG31_OUTCFG127_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75320   TIMER_OUTCFG31_OUTCFG127_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75321   TIMER_OUTCFG31_OUTCFG127_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75322   TIMER_OUTCFG31_OUTCFG127_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75323   TIMER_OUTCFG31_OUTCFG127_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75324 } TIMER_OUTCFG31_OUTCFG127_Enum;
75325 
75326 /* ===========================================  TIMER OUTCFG31 OUTCFG126 [16..21]  =========================================== */
75327 typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG126                                                  */
75328   TIMER_OUTCFG31_OUTCFG126_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75329   TIMER_OUTCFG31_OUTCFG126_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75330   TIMER_OUTCFG31_OUTCFG126_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75331   TIMER_OUTCFG31_OUTCFG126_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75332   TIMER_OUTCFG31_OUTCFG126_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75333   TIMER_OUTCFG31_OUTCFG126_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75334   TIMER_OUTCFG31_OUTCFG126_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75335   TIMER_OUTCFG31_OUTCFG126_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75336   TIMER_OUTCFG31_OUTCFG126_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75337   TIMER_OUTCFG31_OUTCFG126_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75338   TIMER_OUTCFG31_OUTCFG126_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75339   TIMER_OUTCFG31_OUTCFG126_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75340   TIMER_OUTCFG31_OUTCFG126_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75341   TIMER_OUTCFG31_OUTCFG126_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75342   TIMER_OUTCFG31_OUTCFG126_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75343   TIMER_OUTCFG31_OUTCFG126_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75344   TIMER_OUTCFG31_OUTCFG126_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75345   TIMER_OUTCFG31_OUTCFG126_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75346   TIMER_OUTCFG31_OUTCFG126_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75347   TIMER_OUTCFG31_OUTCFG126_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75348   TIMER_OUTCFG31_OUTCFG126_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75349   TIMER_OUTCFG31_OUTCFG126_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75350   TIMER_OUTCFG31_OUTCFG126_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75351   TIMER_OUTCFG31_OUTCFG126_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75352   TIMER_OUTCFG31_OUTCFG126_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75353   TIMER_OUTCFG31_OUTCFG126_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75354   TIMER_OUTCFG31_OUTCFG126_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75355   TIMER_OUTCFG31_OUTCFG126_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75356   TIMER_OUTCFG31_OUTCFG126_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75357   TIMER_OUTCFG31_OUTCFG126_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75358   TIMER_OUTCFG31_OUTCFG126_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75359   TIMER_OUTCFG31_OUTCFG126_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75360   TIMER_OUTCFG31_OUTCFG126_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75361   TIMER_OUTCFG31_OUTCFG126_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75362   TIMER_OUTCFG31_OUTCFG126_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75363   TIMER_OUTCFG31_OUTCFG126_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75364   TIMER_OUTCFG31_OUTCFG126_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75365   TIMER_OUTCFG31_OUTCFG126_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75366   TIMER_OUTCFG31_OUTCFG126_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75367   TIMER_OUTCFG31_OUTCFG126_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75368   TIMER_OUTCFG31_OUTCFG126_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75369 } TIMER_OUTCFG31_OUTCFG126_Enum;
75370 
75371 /* ===========================================  TIMER OUTCFG31 OUTCFG125 [8..13]  ============================================ */
75372 typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG125                                                  */
75373   TIMER_OUTCFG31_OUTCFG125_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75374   TIMER_OUTCFG31_OUTCFG125_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75375   TIMER_OUTCFG31_OUTCFG125_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75376   TIMER_OUTCFG31_OUTCFG125_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75377   TIMER_OUTCFG31_OUTCFG125_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75378   TIMER_OUTCFG31_OUTCFG125_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75379   TIMER_OUTCFG31_OUTCFG125_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75380   TIMER_OUTCFG31_OUTCFG125_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75381   TIMER_OUTCFG31_OUTCFG125_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75382   TIMER_OUTCFG31_OUTCFG125_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75383   TIMER_OUTCFG31_OUTCFG125_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75384   TIMER_OUTCFG31_OUTCFG125_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75385   TIMER_OUTCFG31_OUTCFG125_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75386   TIMER_OUTCFG31_OUTCFG125_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75387   TIMER_OUTCFG31_OUTCFG125_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75388   TIMER_OUTCFG31_OUTCFG125_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75389   TIMER_OUTCFG31_OUTCFG125_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75390   TIMER_OUTCFG31_OUTCFG125_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75391   TIMER_OUTCFG31_OUTCFG125_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75392   TIMER_OUTCFG31_OUTCFG125_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75393   TIMER_OUTCFG31_OUTCFG125_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75394   TIMER_OUTCFG31_OUTCFG125_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75395   TIMER_OUTCFG31_OUTCFG125_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75396   TIMER_OUTCFG31_OUTCFG125_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75397   TIMER_OUTCFG31_OUTCFG125_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75398   TIMER_OUTCFG31_OUTCFG125_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75399   TIMER_OUTCFG31_OUTCFG125_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75400   TIMER_OUTCFG31_OUTCFG125_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75401   TIMER_OUTCFG31_OUTCFG125_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75402   TIMER_OUTCFG31_OUTCFG125_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75403   TIMER_OUTCFG31_OUTCFG125_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75404   TIMER_OUTCFG31_OUTCFG125_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75405   TIMER_OUTCFG31_OUTCFG125_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75406   TIMER_OUTCFG31_OUTCFG125_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75407   TIMER_OUTCFG31_OUTCFG125_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75408   TIMER_OUTCFG31_OUTCFG125_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75409   TIMER_OUTCFG31_OUTCFG125_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75410   TIMER_OUTCFG31_OUTCFG125_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75411   TIMER_OUTCFG31_OUTCFG125_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75412   TIMER_OUTCFG31_OUTCFG125_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75413   TIMER_OUTCFG31_OUTCFG125_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75414 } TIMER_OUTCFG31_OUTCFG125_Enum;
75415 
75416 /* ============================================  TIMER OUTCFG31 OUTCFG124 [0..5]  ============================================ */
75417 typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG124                                                  */
75418   TIMER_OUTCFG31_OUTCFG124_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
75419   TIMER_OUTCFG31_OUTCFG124_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
75420   TIMER_OUTCFG31_OUTCFG124_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
75421   TIMER_OUTCFG31_OUTCFG124_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
75422   TIMER_OUTCFG31_OUTCFG124_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
75423   TIMER_OUTCFG31_OUTCFG124_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
75424   TIMER_OUTCFG31_OUTCFG124_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
75425   TIMER_OUTCFG31_OUTCFG124_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
75426   TIMER_OUTCFG31_OUTCFG124_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
75427   TIMER_OUTCFG31_OUTCFG124_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
75428   TIMER_OUTCFG31_OUTCFG124_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
75429   TIMER_OUTCFG31_OUTCFG124_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
75430   TIMER_OUTCFG31_OUTCFG124_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
75431   TIMER_OUTCFG31_OUTCFG124_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
75432   TIMER_OUTCFG31_OUTCFG124_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
75433   TIMER_OUTCFG31_OUTCFG124_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
75434   TIMER_OUTCFG31_OUTCFG124_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
75435   TIMER_OUTCFG31_OUTCFG124_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
75436   TIMER_OUTCFG31_OUTCFG124_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
75437   TIMER_OUTCFG31_OUTCFG124_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
75438   TIMER_OUTCFG31_OUTCFG124_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
75439   TIMER_OUTCFG31_OUTCFG124_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
75440   TIMER_OUTCFG31_OUTCFG124_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
75441   TIMER_OUTCFG31_OUTCFG124_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
75442   TIMER_OUTCFG31_OUTCFG124_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
75443   TIMER_OUTCFG31_OUTCFG124_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
75444   TIMER_OUTCFG31_OUTCFG124_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
75445   TIMER_OUTCFG31_OUTCFG124_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
75446   TIMER_OUTCFG31_OUTCFG124_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
75447   TIMER_OUTCFG31_OUTCFG124_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
75448   TIMER_OUTCFG31_OUTCFG124_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
75449   TIMER_OUTCFG31_OUTCFG124_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
75450   TIMER_OUTCFG31_OUTCFG124_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
75451   TIMER_OUTCFG31_OUTCFG124_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
75452   TIMER_OUTCFG31_OUTCFG124_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
75453   TIMER_OUTCFG31_OUTCFG124_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
75454   TIMER_OUTCFG31_OUTCFG124_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
75455   TIMER_OUTCFG31_OUTCFG124_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
75456   TIMER_OUTCFG31_OUTCFG124_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
75457   TIMER_OUTCFG31_OUTCFG124_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
75458   TIMER_OUTCFG31_OUTCFG124_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
75459 } TIMER_OUTCFG31_OUTCFG124_Enum;
75460 
75461 /* =========================================================  CTRL0  ========================================================= */
75462 /* ============================================  TIMER CTRL0 TMR0TMODE [16..17]  ============================================= */
75463 typedef enum {                                  /*!< TIMER_CTRL0_TMR0TMODE                                                     */
75464   TIMER_CTRL0_TMR0TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
75465   TIMER_CTRL0_TMR0TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
75466   TIMER_CTRL0_TMR0TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
75467   TIMER_CTRL0_TMR0TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
75468 } TIMER_CTRL0_TMR0TMODE_Enum;
75469 
75470 /* ==============================================  TIMER CTRL0 TMR0CLK [8..15]  ============================================== */
75471 typedef enum {                                  /*!< TIMER_CTRL0_TMR0CLK                                                       */
75472   TIMER_CTRL0_TMR0CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
75473   TIMER_CTRL0_TMR0CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
75474   TIMER_CTRL0_TMR0CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
75475   TIMER_CTRL0_TMR0CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
75476   TIMER_CTRL0_TMR0CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
75477   TIMER_CTRL0_TMR0CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
75478   TIMER_CTRL0_TMR0CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
75479   TIMER_CTRL0_TMR0CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
75480   TIMER_CTRL0_TMR0CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
75481   TIMER_CTRL0_TMR0CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
75482   TIMER_CTRL0_TMR0CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
75483   TIMER_CTRL0_TMR0CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
75484   TIMER_CTRL0_TMR0CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
75485   TIMER_CTRL0_TMR0CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
75486   TIMER_CTRL0_TMR0CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
75487   TIMER_CTRL0_TMR0CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
75488   TIMER_CTRL0_TMR0CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
75489   TIMER_CTRL0_TMR0CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
75490   TIMER_CTRL0_TMR0CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
75491   TIMER_CTRL0_TMR0CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
75492   TIMER_CTRL0_TMR0CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
75493   TIMER_CTRL0_TMR0CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
75494   TIMER_CTRL0_TMR0CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
75495   TIMER_CTRL0_TMR0CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
75496   TIMER_CTRL0_TMR0CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
75497   TIMER_CTRL0_TMR0CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
75498   TIMER_CTRL0_TMR0CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
75499   TIMER_CTRL0_TMR0CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
75500   TIMER_CTRL0_TMR0CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
75501   TIMER_CTRL0_TMR0CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
75502   TIMER_CTRL0_TMR0CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
75503   TIMER_CTRL0_TMR0CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
75504   TIMER_CTRL0_TMR0CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
75505   TIMER_CTRL0_TMR0CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
75506   TIMER_CTRL0_TMR0CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
75507   TIMER_CTRL0_TMR0CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
75508   TIMER_CTRL0_TMR0CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
75509   TIMER_CTRL0_TMR0CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
75510   TIMER_CTRL0_TMR0CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
75511   TIMER_CTRL0_TMR0CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
75512   TIMER_CTRL0_TMR0CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
75513   TIMER_CTRL0_TMR0CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
75514   TIMER_CTRL0_TMR0CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
75515   TIMER_CTRL0_TMR0CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
75516   TIMER_CTRL0_TMR0CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
75517   TIMER_CTRL0_TMR0CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
75518   TIMER_CTRL0_TMR0CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
75519   TIMER_CTRL0_TMR0CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
75520   TIMER_CTRL0_TMR0CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
75521   TIMER_CTRL0_TMR0CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
75522   TIMER_CTRL0_TMR0CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
75523   TIMER_CTRL0_TMR0CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
75524   TIMER_CTRL0_TMR0CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
75525   TIMER_CTRL0_TMR0CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
75526   TIMER_CTRL0_TMR0CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
75527   TIMER_CTRL0_TMR0CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
75528   TIMER_CTRL0_TMR0CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
75529   TIMER_CTRL0_TMR0CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
75530 } TIMER_CTRL0_TMR0CLK_Enum;
75531 
75532 /* ===============================================  TIMER CTRL0 TMR0FN [4..7]  =============================================== */
75533 typedef enum {                                  /*!< TIMER_CTRL0_TMR0FN                                                        */
75534   TIMER_CTRL0_TMR0FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
75535                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
75536                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
75537   TIMER_CTRL0_TMR0FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
75538                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
75539                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
75540                                                      for TMR_LMT iterations.                                                   */
75541   TIMER_CTRL0_TMR0FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
75542                                                      clock pulse. CMP1 dictates the low phase of the output
75543                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
75544   TIMER_CTRL0_TMR0FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
75545                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
75546                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
75547                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
75548                                                      Both OUT0 and OUT1 can be inverted individually applications
75549                                                      with POL0/POL1 = 0x1.                                                     */
75550   TIMER_CTRL0_TMR0FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
75551                                                      pattern repeats after reaching LMT.                                       */
75552 } TIMER_CTRL0_TMR0FN_Enum;
75553 
75554 /* ==============================================  TIMER CTRL0 TMR0POL1 [3..3]  ============================================== */
75555 typedef enum {                                  /*!< TIMER_CTRL0_TMR0POL1                                                      */
75556   TIMER_CTRL0_TMR0POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR0OUT1 pin is the same as the
75557                                                      timer output.                                                             */
75558   TIMER_CTRL0_TMR0POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR0OUT1 pin is the inverse of
75559                                                      the timer output.                                                         */
75560 } TIMER_CTRL0_TMR0POL1_Enum;
75561 
75562 /* ==============================================  TIMER CTRL0 TMR0POL0 [2..2]  ============================================== */
75563 typedef enum {                                  /*!< TIMER_CTRL0_TMR0POL0                                                      */
75564   TIMER_CTRL0_TMR0POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR0OUT0 pin is the same as the
75565                                                      timer output.                                                             */
75566   TIMER_CTRL0_TMR0POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR0OUT0 pin is the inverse of
75567                                                      the timer output.                                                         */
75568 } TIMER_CTRL0_TMR0POL0_Enum;
75569 
75570 /* ==============================================  TIMER CTRL0 TMR0CLR [1..1]  =============================================== */
75571 typedef enum {                                  /*!< TIMER_CTRL0_TMR0CLR                                                       */
75572   TIMER_CTRL0_TMR0CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
75573                                                      cleared to its reset state # (0 for count up counter, CMP0
75574                                                      for down counter)                                                         */
75575   TIMER_CTRL0_TMR0CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
75576 } TIMER_CTRL0_TMR0CLR_Enum;
75577 
75578 /* ===============================================  TIMER CTRL0 TMR0EN [0..0]  =============================================== */
75579 typedef enum {                                  /*!< TIMER_CTRL0_TMR0EN                                                        */
75580   TIMER_CTRL0_TMR0EN_DIS               = 0,     /*!< DIS : Counter/Timer 0 Disable.                                            */
75581   TIMER_CTRL0_TMR0EN_EN                = 1,     /*!< EN : Counter/Timer 0 Enable.                                              */
75582 } TIMER_CTRL0_TMR0EN_Enum;
75583 
75584 /* ========================================================  TIMER0  ========================================================= */
75585 /* =======================================================  TMR0CMP0  ======================================================== */
75586 /* =======================================================  TMR0CMP1  ======================================================== */
75587 /* =========================================================  MODE0  ========================================================= */
75588 /* ============================================  TIMER MODE0 TMR0TRIGSEL [8..15]  ============================================ */
75589 typedef enum {                                  /*!< TIMER_MODE0_TMR0TRIGSEL                                                   */
75590   TIMER_MODE0_TMR0TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
75591   TIMER_MODE0_TMR0TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
75592   TIMER_MODE0_TMR0TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
75593   TIMER_MODE0_TMR0TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
75594   TIMER_MODE0_TMR0TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
75595   TIMER_MODE0_TMR0TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
75596   TIMER_MODE0_TMR0TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
75597   TIMER_MODE0_TMR0TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
75598   TIMER_MODE0_TMR0TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
75599   TIMER_MODE0_TMR0TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
75600   TIMER_MODE0_TMR0TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
75601   TIMER_MODE0_TMR0TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
75602   TIMER_MODE0_TMR0TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
75603   TIMER_MODE0_TMR0TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
75604   TIMER_MODE0_TMR0TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
75605   TIMER_MODE0_TMR0TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
75606   TIMER_MODE0_TMR0TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
75607   TIMER_MODE0_TMR0TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
75608   TIMER_MODE0_TMR0TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
75609   TIMER_MODE0_TMR0TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
75610   TIMER_MODE0_TMR0TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
75611   TIMER_MODE0_TMR0TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
75612   TIMER_MODE0_TMR0TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
75613   TIMER_MODE0_TMR0TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
75614   TIMER_MODE0_TMR0TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
75615   TIMER_MODE0_TMR0TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
75616   TIMER_MODE0_TMR0TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
75617   TIMER_MODE0_TMR0TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
75618   TIMER_MODE0_TMR0TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
75619   TIMER_MODE0_TMR0TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
75620   TIMER_MODE0_TMR0TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
75621   TIMER_MODE0_TMR0TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
75622   TIMER_MODE0_TMR0TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
75623   TIMER_MODE0_TMR0TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
75624 } TIMER_MODE0_TMR0TRIGSEL_Enum;
75625 
75626 /* ======================================================  TMR0LMTVAL  ======================================================= */
75627 /* =========================================================  CTRL1  ========================================================= */
75628 /* ============================================  TIMER CTRL1 TMR1TMODE [16..17]  ============================================= */
75629 typedef enum {                                  /*!< TIMER_CTRL1_TMR1TMODE                                                     */
75630   TIMER_CTRL1_TMR1TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
75631   TIMER_CTRL1_TMR1TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
75632   TIMER_CTRL1_TMR1TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
75633   TIMER_CTRL1_TMR1TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
75634 } TIMER_CTRL1_TMR1TMODE_Enum;
75635 
75636 /* ==============================================  TIMER CTRL1 TMR1CLK [8..15]  ============================================== */
75637 typedef enum {                                  /*!< TIMER_CTRL1_TMR1CLK                                                       */
75638   TIMER_CTRL1_TMR1CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
75639   TIMER_CTRL1_TMR1CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
75640   TIMER_CTRL1_TMR1CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
75641   TIMER_CTRL1_TMR1CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
75642   TIMER_CTRL1_TMR1CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
75643   TIMER_CTRL1_TMR1CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
75644   TIMER_CTRL1_TMR1CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
75645   TIMER_CTRL1_TMR1CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
75646   TIMER_CTRL1_TMR1CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
75647   TIMER_CTRL1_TMR1CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
75648   TIMER_CTRL1_TMR1CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
75649   TIMER_CTRL1_TMR1CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
75650   TIMER_CTRL1_TMR1CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
75651   TIMER_CTRL1_TMR1CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
75652   TIMER_CTRL1_TMR1CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
75653   TIMER_CTRL1_TMR1CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
75654   TIMER_CTRL1_TMR1CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
75655   TIMER_CTRL1_TMR1CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
75656   TIMER_CTRL1_TMR1CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
75657   TIMER_CTRL1_TMR1CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
75658   TIMER_CTRL1_TMR1CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
75659   TIMER_CTRL1_TMR1CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
75660   TIMER_CTRL1_TMR1CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
75661   TIMER_CTRL1_TMR1CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
75662   TIMER_CTRL1_TMR1CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
75663   TIMER_CTRL1_TMR1CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
75664   TIMER_CTRL1_TMR1CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
75665   TIMER_CTRL1_TMR1CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
75666   TIMER_CTRL1_TMR1CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
75667   TIMER_CTRL1_TMR1CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
75668   TIMER_CTRL1_TMR1CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
75669   TIMER_CTRL1_TMR1CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
75670   TIMER_CTRL1_TMR1CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
75671   TIMER_CTRL1_TMR1CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
75672   TIMER_CTRL1_TMR1CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
75673   TIMER_CTRL1_TMR1CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
75674   TIMER_CTRL1_TMR1CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
75675   TIMER_CTRL1_TMR1CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
75676   TIMER_CTRL1_TMR1CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
75677   TIMER_CTRL1_TMR1CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
75678   TIMER_CTRL1_TMR1CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
75679   TIMER_CTRL1_TMR1CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
75680   TIMER_CTRL1_TMR1CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
75681   TIMER_CTRL1_TMR1CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
75682   TIMER_CTRL1_TMR1CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
75683   TIMER_CTRL1_TMR1CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
75684   TIMER_CTRL1_TMR1CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
75685   TIMER_CTRL1_TMR1CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
75686   TIMER_CTRL1_TMR1CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
75687   TIMER_CTRL1_TMR1CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
75688   TIMER_CTRL1_TMR1CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
75689   TIMER_CTRL1_TMR1CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
75690   TIMER_CTRL1_TMR1CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
75691   TIMER_CTRL1_TMR1CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
75692   TIMER_CTRL1_TMR1CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
75693   TIMER_CTRL1_TMR1CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
75694   TIMER_CTRL1_TMR1CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
75695   TIMER_CTRL1_TMR1CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
75696 } TIMER_CTRL1_TMR1CLK_Enum;
75697 
75698 /* ===============================================  TIMER CTRL1 TMR1FN [4..7]  =============================================== */
75699 typedef enum {                                  /*!< TIMER_CTRL1_TMR1FN                                                        */
75700   TIMER_CTRL1_TMR1FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
75701                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
75702                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
75703   TIMER_CTRL1_TMR1FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
75704                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
75705                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
75706                                                      for TMR_LMT iterations.                                                   */
75707   TIMER_CTRL1_TMR1FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
75708                                                      clock pulse. CMP1 dictates the low phase of the output
75709                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
75710   TIMER_CTRL1_TMR1FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
75711                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
75712                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
75713                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
75714                                                      Both OUT0 and OUT1 can be inverted individually applications
75715                                                      with POL0/POL1 = 0x1.                                                     */
75716   TIMER_CTRL1_TMR1FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
75717                                                      pattern repeats after reaching LMT.                                       */
75718 } TIMER_CTRL1_TMR1FN_Enum;
75719 
75720 /* ==============================================  TIMER CTRL1 TMR1POL1 [3..3]  ============================================== */
75721 typedef enum {                                  /*!< TIMER_CTRL1_TMR1POL1                                                      */
75722   TIMER_CTRL1_TMR1POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR1OUT1 pin is the same as the
75723                                                      timer output.                                                             */
75724   TIMER_CTRL1_TMR1POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR1OUT1 pin is the inverse of
75725                                                      the timer output.                                                         */
75726 } TIMER_CTRL1_TMR1POL1_Enum;
75727 
75728 /* ==============================================  TIMER CTRL1 TMR1POL0 [2..2]  ============================================== */
75729 typedef enum {                                  /*!< TIMER_CTRL1_TMR1POL0                                                      */
75730   TIMER_CTRL1_TMR1POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR1OUT0 pin is the same as the
75731                                                      timer output.                                                             */
75732   TIMER_CTRL1_TMR1POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR1OUT0 pin is the inverse of
75733                                                      the timer output.                                                         */
75734 } TIMER_CTRL1_TMR1POL0_Enum;
75735 
75736 /* ==============================================  TIMER CTRL1 TMR1CLR [1..1]  =============================================== */
75737 typedef enum {                                  /*!< TIMER_CTRL1_TMR1CLR                                                       */
75738   TIMER_CTRL1_TMR1CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
75739                                                      cleared to its reset state # (0 for count up counter, CMP0
75740                                                      for down counter)                                                         */
75741   TIMER_CTRL1_TMR1CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
75742 } TIMER_CTRL1_TMR1CLR_Enum;
75743 
75744 /* ===============================================  TIMER CTRL1 TMR1EN [0..0]  =============================================== */
75745 typedef enum {                                  /*!< TIMER_CTRL1_TMR1EN                                                        */
75746   TIMER_CTRL1_TMR1EN_DIS               = 0,     /*!< DIS : Counter/Timer 1 Disable.                                            */
75747   TIMER_CTRL1_TMR1EN_EN                = 1,     /*!< EN : Counter/Timer 1 Enable.                                              */
75748 } TIMER_CTRL1_TMR1EN_Enum;
75749 
75750 /* ========================================================  TIMER1  ========================================================= */
75751 /* =======================================================  TMR1CMP0  ======================================================== */
75752 /* =======================================================  TMR1CMP1  ======================================================== */
75753 /* =========================================================  MODE1  ========================================================= */
75754 /* ============================================  TIMER MODE1 TMR1TRIGSEL [8..15]  ============================================ */
75755 typedef enum {                                  /*!< TIMER_MODE1_TMR1TRIGSEL                                                   */
75756   TIMER_MODE1_TMR1TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
75757   TIMER_MODE1_TMR1TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
75758   TIMER_MODE1_TMR1TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
75759   TIMER_MODE1_TMR1TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
75760   TIMER_MODE1_TMR1TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
75761   TIMER_MODE1_TMR1TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
75762   TIMER_MODE1_TMR1TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
75763   TIMER_MODE1_TMR1TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
75764   TIMER_MODE1_TMR1TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
75765   TIMER_MODE1_TMR1TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
75766   TIMER_MODE1_TMR1TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
75767   TIMER_MODE1_TMR1TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
75768   TIMER_MODE1_TMR1TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
75769   TIMER_MODE1_TMR1TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
75770   TIMER_MODE1_TMR1TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
75771   TIMER_MODE1_TMR1TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
75772   TIMER_MODE1_TMR1TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
75773   TIMER_MODE1_TMR1TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
75774   TIMER_MODE1_TMR1TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
75775   TIMER_MODE1_TMR1TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
75776   TIMER_MODE1_TMR1TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
75777   TIMER_MODE1_TMR1TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
75778   TIMER_MODE1_TMR1TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
75779   TIMER_MODE1_TMR1TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
75780   TIMER_MODE1_TMR1TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
75781   TIMER_MODE1_TMR1TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
75782   TIMER_MODE1_TMR1TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
75783   TIMER_MODE1_TMR1TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
75784   TIMER_MODE1_TMR1TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
75785   TIMER_MODE1_TMR1TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
75786   TIMER_MODE1_TMR1TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
75787   TIMER_MODE1_TMR1TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
75788   TIMER_MODE1_TMR1TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
75789   TIMER_MODE1_TMR1TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
75790 } TIMER_MODE1_TMR1TRIGSEL_Enum;
75791 
75792 /* ======================================================  TMR1LMTVAL  ======================================================= */
75793 /* =========================================================  CTRL2  ========================================================= */
75794 /* ============================================  TIMER CTRL2 TMR2TMODE [16..17]  ============================================= */
75795 typedef enum {                                  /*!< TIMER_CTRL2_TMR2TMODE                                                     */
75796   TIMER_CTRL2_TMR2TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
75797   TIMER_CTRL2_TMR2TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
75798   TIMER_CTRL2_TMR2TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
75799   TIMER_CTRL2_TMR2TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
75800 } TIMER_CTRL2_TMR2TMODE_Enum;
75801 
75802 /* ==============================================  TIMER CTRL2 TMR2CLK [8..15]  ============================================== */
75803 typedef enum {                                  /*!< TIMER_CTRL2_TMR2CLK                                                       */
75804   TIMER_CTRL2_TMR2CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
75805   TIMER_CTRL2_TMR2CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
75806   TIMER_CTRL2_TMR2CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
75807   TIMER_CTRL2_TMR2CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
75808   TIMER_CTRL2_TMR2CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
75809   TIMER_CTRL2_TMR2CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
75810   TIMER_CTRL2_TMR2CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
75811   TIMER_CTRL2_TMR2CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
75812   TIMER_CTRL2_TMR2CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
75813   TIMER_CTRL2_TMR2CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
75814   TIMER_CTRL2_TMR2CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
75815   TIMER_CTRL2_TMR2CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
75816   TIMER_CTRL2_TMR2CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
75817   TIMER_CTRL2_TMR2CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
75818   TIMER_CTRL2_TMR2CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
75819   TIMER_CTRL2_TMR2CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
75820   TIMER_CTRL2_TMR2CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
75821   TIMER_CTRL2_TMR2CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
75822   TIMER_CTRL2_TMR2CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
75823   TIMER_CTRL2_TMR2CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
75824   TIMER_CTRL2_TMR2CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
75825   TIMER_CTRL2_TMR2CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
75826   TIMER_CTRL2_TMR2CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
75827   TIMER_CTRL2_TMR2CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
75828   TIMER_CTRL2_TMR2CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
75829   TIMER_CTRL2_TMR2CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
75830   TIMER_CTRL2_TMR2CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
75831   TIMER_CTRL2_TMR2CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
75832   TIMER_CTRL2_TMR2CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
75833   TIMER_CTRL2_TMR2CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
75834   TIMER_CTRL2_TMR2CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
75835   TIMER_CTRL2_TMR2CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
75836   TIMER_CTRL2_TMR2CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
75837   TIMER_CTRL2_TMR2CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
75838   TIMER_CTRL2_TMR2CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
75839   TIMER_CTRL2_TMR2CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
75840   TIMER_CTRL2_TMR2CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
75841   TIMER_CTRL2_TMR2CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
75842   TIMER_CTRL2_TMR2CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
75843   TIMER_CTRL2_TMR2CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
75844   TIMER_CTRL2_TMR2CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
75845   TIMER_CTRL2_TMR2CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
75846   TIMER_CTRL2_TMR2CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
75847   TIMER_CTRL2_TMR2CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
75848   TIMER_CTRL2_TMR2CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
75849   TIMER_CTRL2_TMR2CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
75850   TIMER_CTRL2_TMR2CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
75851   TIMER_CTRL2_TMR2CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
75852   TIMER_CTRL2_TMR2CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
75853   TIMER_CTRL2_TMR2CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
75854   TIMER_CTRL2_TMR2CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
75855   TIMER_CTRL2_TMR2CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
75856   TIMER_CTRL2_TMR2CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
75857   TIMER_CTRL2_TMR2CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
75858   TIMER_CTRL2_TMR2CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
75859   TIMER_CTRL2_TMR2CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
75860   TIMER_CTRL2_TMR2CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
75861   TIMER_CTRL2_TMR2CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
75862 } TIMER_CTRL2_TMR2CLK_Enum;
75863 
75864 /* ===============================================  TIMER CTRL2 TMR2FN [4..7]  =============================================== */
75865 typedef enum {                                  /*!< TIMER_CTRL2_TMR2FN                                                        */
75866   TIMER_CTRL2_TMR2FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
75867                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
75868                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
75869   TIMER_CTRL2_TMR2FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
75870                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
75871                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
75872                                                      for TMR_LMT iterations.                                                   */
75873   TIMER_CTRL2_TMR2FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
75874                                                      clock pulse. CMP1 dictates the low phase of the output
75875                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
75876   TIMER_CTRL2_TMR2FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
75877                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
75878                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
75879                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
75880                                                      Both OUT0 and OUT1 can be inverted individually applications
75881                                                      with POL0/POL1 = 0x1.                                                     */
75882   TIMER_CTRL2_TMR2FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
75883                                                      pattern repeats after reaching LMT.                                       */
75884 } TIMER_CTRL2_TMR2FN_Enum;
75885 
75886 /* ==============================================  TIMER CTRL2 TMR2POL1 [3..3]  ============================================== */
75887 typedef enum {                                  /*!< TIMER_CTRL2_TMR2POL1                                                      */
75888   TIMER_CTRL2_TMR2POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR2OUT1 pin is the same as the
75889                                                      timer output.                                                             */
75890   TIMER_CTRL2_TMR2POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR2OUT1 pin is the inverse of
75891                                                      the timer output.                                                         */
75892 } TIMER_CTRL2_TMR2POL1_Enum;
75893 
75894 /* ==============================================  TIMER CTRL2 TMR2POL0 [2..2]  ============================================== */
75895 typedef enum {                                  /*!< TIMER_CTRL2_TMR2POL0                                                      */
75896   TIMER_CTRL2_TMR2POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR2OUT0 pin is the same as the
75897                                                      timer output.                                                             */
75898   TIMER_CTRL2_TMR2POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR2OUT0 pin is the inverse of
75899                                                      the timer output.                                                         */
75900 } TIMER_CTRL2_TMR2POL0_Enum;
75901 
75902 /* ==============================================  TIMER CTRL2 TMR2CLR [1..1]  =============================================== */
75903 typedef enum {                                  /*!< TIMER_CTRL2_TMR2CLR                                                       */
75904   TIMER_CTRL2_TMR2CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
75905                                                      cleared to its reset state # (0 for count up counter, CMP0
75906                                                      for down counter)                                                         */
75907   TIMER_CTRL2_TMR2CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
75908 } TIMER_CTRL2_TMR2CLR_Enum;
75909 
75910 /* ===============================================  TIMER CTRL2 TMR2EN [0..0]  =============================================== */
75911 typedef enum {                                  /*!< TIMER_CTRL2_TMR2EN                                                        */
75912   TIMER_CTRL2_TMR2EN_DIS               = 0,     /*!< DIS : Counter/Timer 2 Disable.                                            */
75913   TIMER_CTRL2_TMR2EN_EN                = 1,     /*!< EN : Counter/Timer 2 Enable.                                              */
75914 } TIMER_CTRL2_TMR2EN_Enum;
75915 
75916 /* ========================================================  TIMER2  ========================================================= */
75917 /* =======================================================  TMR2CMP0  ======================================================== */
75918 /* =======================================================  TMR2CMP1  ======================================================== */
75919 /* =========================================================  MODE2  ========================================================= */
75920 /* ============================================  TIMER MODE2 TMR2TRIGSEL [8..15]  ============================================ */
75921 typedef enum {                                  /*!< TIMER_MODE2_TMR2TRIGSEL                                                   */
75922   TIMER_MODE2_TMR2TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
75923   TIMER_MODE2_TMR2TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
75924   TIMER_MODE2_TMR2TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
75925   TIMER_MODE2_TMR2TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
75926   TIMER_MODE2_TMR2TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
75927   TIMER_MODE2_TMR2TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
75928   TIMER_MODE2_TMR2TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
75929   TIMER_MODE2_TMR2TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
75930   TIMER_MODE2_TMR2TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
75931   TIMER_MODE2_TMR2TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
75932   TIMER_MODE2_TMR2TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
75933   TIMER_MODE2_TMR2TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
75934   TIMER_MODE2_TMR2TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
75935   TIMER_MODE2_TMR2TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
75936   TIMER_MODE2_TMR2TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
75937   TIMER_MODE2_TMR2TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
75938   TIMER_MODE2_TMR2TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
75939   TIMER_MODE2_TMR2TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
75940   TIMER_MODE2_TMR2TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
75941   TIMER_MODE2_TMR2TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
75942   TIMER_MODE2_TMR2TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
75943   TIMER_MODE2_TMR2TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
75944   TIMER_MODE2_TMR2TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
75945   TIMER_MODE2_TMR2TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
75946   TIMER_MODE2_TMR2TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
75947   TIMER_MODE2_TMR2TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
75948   TIMER_MODE2_TMR2TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
75949   TIMER_MODE2_TMR2TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
75950   TIMER_MODE2_TMR2TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
75951   TIMER_MODE2_TMR2TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
75952   TIMER_MODE2_TMR2TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
75953   TIMER_MODE2_TMR2TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
75954   TIMER_MODE2_TMR2TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
75955   TIMER_MODE2_TMR2TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
75956 } TIMER_MODE2_TMR2TRIGSEL_Enum;
75957 
75958 /* ======================================================  TMR2LMTVAL  ======================================================= */
75959 /* =========================================================  CTRL3  ========================================================= */
75960 /* ============================================  TIMER CTRL3 TMR3TMODE [16..17]  ============================================= */
75961 typedef enum {                                  /*!< TIMER_CTRL3_TMR3TMODE                                                     */
75962   TIMER_CTRL3_TMR3TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
75963   TIMER_CTRL3_TMR3TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
75964   TIMER_CTRL3_TMR3TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
75965   TIMER_CTRL3_TMR3TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
75966 } TIMER_CTRL3_TMR3TMODE_Enum;
75967 
75968 /* ==============================================  TIMER CTRL3 TMR3CLK [8..15]  ============================================== */
75969 typedef enum {                                  /*!< TIMER_CTRL3_TMR3CLK                                                       */
75970   TIMER_CTRL3_TMR3CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
75971   TIMER_CTRL3_TMR3CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
75972   TIMER_CTRL3_TMR3CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
75973   TIMER_CTRL3_TMR3CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
75974   TIMER_CTRL3_TMR3CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
75975   TIMER_CTRL3_TMR3CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
75976   TIMER_CTRL3_TMR3CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
75977   TIMER_CTRL3_TMR3CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
75978   TIMER_CTRL3_TMR3CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
75979   TIMER_CTRL3_TMR3CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
75980   TIMER_CTRL3_TMR3CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
75981   TIMER_CTRL3_TMR3CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
75982   TIMER_CTRL3_TMR3CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
75983   TIMER_CTRL3_TMR3CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
75984   TIMER_CTRL3_TMR3CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
75985   TIMER_CTRL3_TMR3CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
75986   TIMER_CTRL3_TMR3CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
75987   TIMER_CTRL3_TMR3CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
75988   TIMER_CTRL3_TMR3CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
75989   TIMER_CTRL3_TMR3CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
75990   TIMER_CTRL3_TMR3CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
75991   TIMER_CTRL3_TMR3CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
75992   TIMER_CTRL3_TMR3CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
75993   TIMER_CTRL3_TMR3CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
75994   TIMER_CTRL3_TMR3CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
75995   TIMER_CTRL3_TMR3CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
75996   TIMER_CTRL3_TMR3CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
75997   TIMER_CTRL3_TMR3CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
75998   TIMER_CTRL3_TMR3CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
75999   TIMER_CTRL3_TMR3CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76000   TIMER_CTRL3_TMR3CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76001   TIMER_CTRL3_TMR3CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76002   TIMER_CTRL3_TMR3CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76003   TIMER_CTRL3_TMR3CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76004   TIMER_CTRL3_TMR3CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76005   TIMER_CTRL3_TMR3CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76006   TIMER_CTRL3_TMR3CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76007   TIMER_CTRL3_TMR3CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76008   TIMER_CTRL3_TMR3CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76009   TIMER_CTRL3_TMR3CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76010   TIMER_CTRL3_TMR3CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76011   TIMER_CTRL3_TMR3CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76012   TIMER_CTRL3_TMR3CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76013   TIMER_CTRL3_TMR3CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76014   TIMER_CTRL3_TMR3CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76015   TIMER_CTRL3_TMR3CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76016   TIMER_CTRL3_TMR3CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76017   TIMER_CTRL3_TMR3CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76018   TIMER_CTRL3_TMR3CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76019   TIMER_CTRL3_TMR3CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76020   TIMER_CTRL3_TMR3CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76021   TIMER_CTRL3_TMR3CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76022   TIMER_CTRL3_TMR3CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76023   TIMER_CTRL3_TMR3CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76024   TIMER_CTRL3_TMR3CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76025   TIMER_CTRL3_TMR3CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76026   TIMER_CTRL3_TMR3CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76027   TIMER_CTRL3_TMR3CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76028 } TIMER_CTRL3_TMR3CLK_Enum;
76029 
76030 /* ===============================================  TIMER CTRL3 TMR3FN [4..7]  =============================================== */
76031 typedef enum {                                  /*!< TIMER_CTRL3_TMR3FN                                                        */
76032   TIMER_CTRL3_TMR3FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
76033                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
76034                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
76035   TIMER_CTRL3_TMR3FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
76036                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
76037                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
76038                                                      for TMR_LMT iterations.                                                   */
76039   TIMER_CTRL3_TMR3FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
76040                                                      clock pulse. CMP1 dictates the low phase of the output
76041                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
76042   TIMER_CTRL3_TMR3FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76043                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
76044                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
76045                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
76046                                                      Both OUT0 and OUT1 can be inverted individually applications
76047                                                      with POL0/POL1 = 0x1.                                                     */
76048   TIMER_CTRL3_TMR3FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76049                                                      pattern repeats after reaching LMT.                                       */
76050 } TIMER_CTRL3_TMR3FN_Enum;
76051 
76052 /* ==============================================  TIMER CTRL3 TMR3POL1 [3..3]  ============================================== */
76053 typedef enum {                                  /*!< TIMER_CTRL3_TMR3POL1                                                      */
76054   TIMER_CTRL3_TMR3POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR3OUT1 pin is the same as the
76055                                                      timer output.                                                             */
76056   TIMER_CTRL3_TMR3POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR3OUT1 pin is the inverse of
76057                                                      the timer output.                                                         */
76058 } TIMER_CTRL3_TMR3POL1_Enum;
76059 
76060 /* ==============================================  TIMER CTRL3 TMR3POL0 [2..2]  ============================================== */
76061 typedef enum {                                  /*!< TIMER_CTRL3_TMR3POL0                                                      */
76062   TIMER_CTRL3_TMR3POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR3OUT0 pin is the same as the
76063                                                      timer output.                                                             */
76064   TIMER_CTRL3_TMR3POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR3OUT0 pin is the inverse of
76065                                                      the timer output.                                                         */
76066 } TIMER_CTRL3_TMR3POL0_Enum;
76067 
76068 /* ==============================================  TIMER CTRL3 TMR3CLR [1..1]  =============================================== */
76069 typedef enum {                                  /*!< TIMER_CTRL3_TMR3CLR                                                       */
76070   TIMER_CTRL3_TMR3CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76071                                                      cleared to its reset state # (0 for count up counter, CMP0
76072                                                      for down counter)                                                         */
76073   TIMER_CTRL3_TMR3CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
76074 } TIMER_CTRL3_TMR3CLR_Enum;
76075 
76076 /* ===============================================  TIMER CTRL3 TMR3EN [0..0]  =============================================== */
76077 typedef enum {                                  /*!< TIMER_CTRL3_TMR3EN                                                        */
76078   TIMER_CTRL3_TMR3EN_DIS               = 0,     /*!< DIS : Counter/Timer 3 Disable.                                            */
76079   TIMER_CTRL3_TMR3EN_EN                = 1,     /*!< EN : Counter/Timer 3 Enable.                                              */
76080 } TIMER_CTRL3_TMR3EN_Enum;
76081 
76082 /* ========================================================  TIMER3  ========================================================= */
76083 /* =======================================================  TMR3CMP0  ======================================================== */
76084 /* =======================================================  TMR3CMP1  ======================================================== */
76085 /* =========================================================  MODE3  ========================================================= */
76086 /* ============================================  TIMER MODE3 TMR3TRIGSEL [8..15]  ============================================ */
76087 typedef enum {                                  /*!< TIMER_MODE3_TMR3TRIGSEL                                                   */
76088   TIMER_MODE3_TMR3TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76089   TIMER_MODE3_TMR3TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76090   TIMER_MODE3_TMR3TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76091   TIMER_MODE3_TMR3TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76092   TIMER_MODE3_TMR3TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76093   TIMER_MODE3_TMR3TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76094   TIMER_MODE3_TMR3TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76095   TIMER_MODE3_TMR3TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76096   TIMER_MODE3_TMR3TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76097   TIMER_MODE3_TMR3TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76098   TIMER_MODE3_TMR3TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76099   TIMER_MODE3_TMR3TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76100   TIMER_MODE3_TMR3TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76101   TIMER_MODE3_TMR3TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76102   TIMER_MODE3_TMR3TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76103   TIMER_MODE3_TMR3TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76104   TIMER_MODE3_TMR3TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76105   TIMER_MODE3_TMR3TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76106   TIMER_MODE3_TMR3TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76107   TIMER_MODE3_TMR3TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76108   TIMER_MODE3_TMR3TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76109   TIMER_MODE3_TMR3TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76110   TIMER_MODE3_TMR3TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76111   TIMER_MODE3_TMR3TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76112   TIMER_MODE3_TMR3TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76113   TIMER_MODE3_TMR3TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76114   TIMER_MODE3_TMR3TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76115   TIMER_MODE3_TMR3TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76116   TIMER_MODE3_TMR3TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76117   TIMER_MODE3_TMR3TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76118   TIMER_MODE3_TMR3TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76119   TIMER_MODE3_TMR3TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76120   TIMER_MODE3_TMR3TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76121   TIMER_MODE3_TMR3TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76122 } TIMER_MODE3_TMR3TRIGSEL_Enum;
76123 
76124 /* ======================================================  TMR3LMTVAL  ======================================================= */
76125 /* =========================================================  CTRL4  ========================================================= */
76126 /* ============================================  TIMER CTRL4 TMR4TMODE [16..17]  ============================================= */
76127 typedef enum {                                  /*!< TIMER_CTRL4_TMR4TMODE                                                     */
76128   TIMER_CTRL4_TMR4TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
76129   TIMER_CTRL4_TMR4TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76130   TIMER_CTRL4_TMR4TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76131   TIMER_CTRL4_TMR4TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76132 } TIMER_CTRL4_TMR4TMODE_Enum;
76133 
76134 /* ==============================================  TIMER CTRL4 TMR4CLK [8..15]  ============================================== */
76135 typedef enum {                                  /*!< TIMER_CTRL4_TMR4CLK                                                       */
76136   TIMER_CTRL4_TMR4CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
76137   TIMER_CTRL4_TMR4CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76138   TIMER_CTRL4_TMR4CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76139   TIMER_CTRL4_TMR4CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76140   TIMER_CTRL4_TMR4CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76141   TIMER_CTRL4_TMR4CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76142   TIMER_CTRL4_TMR4CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
76143   TIMER_CTRL4_TMR4CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76144   TIMER_CTRL4_TMR4CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76145   TIMER_CTRL4_TMR4CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76146   TIMER_CTRL4_TMR4CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76147   TIMER_CTRL4_TMR4CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76148   TIMER_CTRL4_TMR4CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76149   TIMER_CTRL4_TMR4CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76150   TIMER_CTRL4_TMR4CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76151   TIMER_CTRL4_TMR4CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76152   TIMER_CTRL4_TMR4CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76153   TIMER_CTRL4_TMR4CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76154   TIMER_CTRL4_TMR4CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76155   TIMER_CTRL4_TMR4CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76156   TIMER_CTRL4_TMR4CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76157   TIMER_CTRL4_TMR4CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76158   TIMER_CTRL4_TMR4CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76159   TIMER_CTRL4_TMR4CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76160   TIMER_CTRL4_TMR4CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76161   TIMER_CTRL4_TMR4CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76162   TIMER_CTRL4_TMR4CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76163   TIMER_CTRL4_TMR4CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76164   TIMER_CTRL4_TMR4CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76165   TIMER_CTRL4_TMR4CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76166   TIMER_CTRL4_TMR4CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76167   TIMER_CTRL4_TMR4CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76168   TIMER_CTRL4_TMR4CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76169   TIMER_CTRL4_TMR4CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76170   TIMER_CTRL4_TMR4CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76171   TIMER_CTRL4_TMR4CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76172   TIMER_CTRL4_TMR4CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76173   TIMER_CTRL4_TMR4CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76174   TIMER_CTRL4_TMR4CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76175   TIMER_CTRL4_TMR4CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76176   TIMER_CTRL4_TMR4CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76177   TIMER_CTRL4_TMR4CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76178   TIMER_CTRL4_TMR4CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76179   TIMER_CTRL4_TMR4CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76180   TIMER_CTRL4_TMR4CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76181   TIMER_CTRL4_TMR4CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76182   TIMER_CTRL4_TMR4CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76183   TIMER_CTRL4_TMR4CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76184   TIMER_CTRL4_TMR4CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76185   TIMER_CTRL4_TMR4CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76186   TIMER_CTRL4_TMR4CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76187   TIMER_CTRL4_TMR4CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76188   TIMER_CTRL4_TMR4CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76189   TIMER_CTRL4_TMR4CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76190   TIMER_CTRL4_TMR4CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76191   TIMER_CTRL4_TMR4CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76192   TIMER_CTRL4_TMR4CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76193   TIMER_CTRL4_TMR4CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76194 } TIMER_CTRL4_TMR4CLK_Enum;
76195 
76196 /* ===============================================  TIMER CTRL4 TMR4FN [4..7]  =============================================== */
76197 typedef enum {                                  /*!< TIMER_CTRL4_TMR4FN                                                        */
76198   TIMER_CTRL4_TMR4FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
76199                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
76200                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
76201   TIMER_CTRL4_TMR4FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
76202                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
76203                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
76204                                                      for TMR_LMT iterations.                                                   */
76205   TIMER_CTRL4_TMR4FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
76206                                                      clock pulse. CMP1 dictates the low phase of the output
76207                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
76208   TIMER_CTRL4_TMR4FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76209                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
76210                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
76211                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
76212                                                      Both OUT0 and OUT1 can be inverted individually applications
76213                                                      with POL0/POL1 = 0x1.                                                     */
76214   TIMER_CTRL4_TMR4FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76215                                                      pattern repeats after reaching LMT.                                       */
76216 } TIMER_CTRL4_TMR4FN_Enum;
76217 
76218 /* ==============================================  TIMER CTRL4 TMR4POL1 [3..3]  ============================================== */
76219 typedef enum {                                  /*!< TIMER_CTRL4_TMR4POL1                                                      */
76220   TIMER_CTRL4_TMR4POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR4OUT1 pin is the same as the
76221                                                      timer output.                                                             */
76222   TIMER_CTRL4_TMR4POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR4OUT1 pin is the inverse of
76223                                                      the timer output.                                                         */
76224 } TIMER_CTRL4_TMR4POL1_Enum;
76225 
76226 /* ==============================================  TIMER CTRL4 TMR4POL0 [2..2]  ============================================== */
76227 typedef enum {                                  /*!< TIMER_CTRL4_TMR4POL0                                                      */
76228   TIMER_CTRL4_TMR4POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR4OUT0 pin is the same as the
76229                                                      timer output.                                                             */
76230   TIMER_CTRL4_TMR4POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR4OUT0 pin is the inverse of
76231                                                      the timer output.                                                         */
76232 } TIMER_CTRL4_TMR4POL0_Enum;
76233 
76234 /* ==============================================  TIMER CTRL4 TMR4CLR [1..1]  =============================================== */
76235 typedef enum {                                  /*!< TIMER_CTRL4_TMR4CLR                                                       */
76236   TIMER_CTRL4_TMR4CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76237                                                      cleared to its reset state # (0 for count up counter, CMP0
76238                                                      for down counter)                                                         */
76239   TIMER_CTRL4_TMR4CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
76240 } TIMER_CTRL4_TMR4CLR_Enum;
76241 
76242 /* ===============================================  TIMER CTRL4 TMR4EN [0..0]  =============================================== */
76243 typedef enum {                                  /*!< TIMER_CTRL4_TMR4EN                                                        */
76244   TIMER_CTRL4_TMR4EN_DIS               = 0,     /*!< DIS : Counter/Timer 4 Disable.                                            */
76245   TIMER_CTRL4_TMR4EN_EN                = 1,     /*!< EN : Counter/Timer 4 Enable.                                              */
76246 } TIMER_CTRL4_TMR4EN_Enum;
76247 
76248 /* ========================================================  TIMER4  ========================================================= */
76249 /* =======================================================  TMR4CMP0  ======================================================== */
76250 /* =======================================================  TMR4CMP1  ======================================================== */
76251 /* =========================================================  MODE4  ========================================================= */
76252 /* ============================================  TIMER MODE4 TMR4TRIGSEL [8..15]  ============================================ */
76253 typedef enum {                                  /*!< TIMER_MODE4_TMR4TRIGSEL                                                   */
76254   TIMER_MODE4_TMR4TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76255   TIMER_MODE4_TMR4TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76256   TIMER_MODE4_TMR4TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76257   TIMER_MODE4_TMR4TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76258   TIMER_MODE4_TMR4TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76259   TIMER_MODE4_TMR4TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76260   TIMER_MODE4_TMR4TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76261   TIMER_MODE4_TMR4TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76262   TIMER_MODE4_TMR4TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76263   TIMER_MODE4_TMR4TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76264   TIMER_MODE4_TMR4TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76265   TIMER_MODE4_TMR4TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76266   TIMER_MODE4_TMR4TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76267   TIMER_MODE4_TMR4TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76268   TIMER_MODE4_TMR4TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76269   TIMER_MODE4_TMR4TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76270   TIMER_MODE4_TMR4TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76271   TIMER_MODE4_TMR4TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76272   TIMER_MODE4_TMR4TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76273   TIMER_MODE4_TMR4TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76274   TIMER_MODE4_TMR4TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76275   TIMER_MODE4_TMR4TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76276   TIMER_MODE4_TMR4TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76277   TIMER_MODE4_TMR4TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76278   TIMER_MODE4_TMR4TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76279   TIMER_MODE4_TMR4TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76280   TIMER_MODE4_TMR4TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76281   TIMER_MODE4_TMR4TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76282   TIMER_MODE4_TMR4TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76283   TIMER_MODE4_TMR4TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76284   TIMER_MODE4_TMR4TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76285   TIMER_MODE4_TMR4TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76286   TIMER_MODE4_TMR4TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76287   TIMER_MODE4_TMR4TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76288 } TIMER_MODE4_TMR4TRIGSEL_Enum;
76289 
76290 /* ======================================================  TMR4LMTVAL  ======================================================= */
76291 /* =========================================================  CTRL5  ========================================================= */
76292 /* ============================================  TIMER CTRL5 TMR5TMODE [16..17]  ============================================= */
76293 typedef enum {                                  /*!< TIMER_CTRL5_TMR5TMODE                                                     */
76294   TIMER_CTRL5_TMR5TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
76295   TIMER_CTRL5_TMR5TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76296   TIMER_CTRL5_TMR5TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76297   TIMER_CTRL5_TMR5TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76298 } TIMER_CTRL5_TMR5TMODE_Enum;
76299 
76300 /* ==============================================  TIMER CTRL5 TMR5CLK [8..15]  ============================================== */
76301 typedef enum {                                  /*!< TIMER_CTRL5_TMR5CLK                                                       */
76302   TIMER_CTRL5_TMR5CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
76303   TIMER_CTRL5_TMR5CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76304   TIMER_CTRL5_TMR5CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76305   TIMER_CTRL5_TMR5CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76306   TIMER_CTRL5_TMR5CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76307   TIMER_CTRL5_TMR5CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76308   TIMER_CTRL5_TMR5CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
76309   TIMER_CTRL5_TMR5CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76310   TIMER_CTRL5_TMR5CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76311   TIMER_CTRL5_TMR5CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76312   TIMER_CTRL5_TMR5CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76313   TIMER_CTRL5_TMR5CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76314   TIMER_CTRL5_TMR5CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76315   TIMER_CTRL5_TMR5CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76316   TIMER_CTRL5_TMR5CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76317   TIMER_CTRL5_TMR5CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76318   TIMER_CTRL5_TMR5CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76319   TIMER_CTRL5_TMR5CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76320   TIMER_CTRL5_TMR5CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76321   TIMER_CTRL5_TMR5CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76322   TIMER_CTRL5_TMR5CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76323   TIMER_CTRL5_TMR5CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76324   TIMER_CTRL5_TMR5CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76325   TIMER_CTRL5_TMR5CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76326   TIMER_CTRL5_TMR5CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76327   TIMER_CTRL5_TMR5CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76328   TIMER_CTRL5_TMR5CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76329   TIMER_CTRL5_TMR5CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76330   TIMER_CTRL5_TMR5CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76331   TIMER_CTRL5_TMR5CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76332   TIMER_CTRL5_TMR5CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76333   TIMER_CTRL5_TMR5CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76334   TIMER_CTRL5_TMR5CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76335   TIMER_CTRL5_TMR5CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76336   TIMER_CTRL5_TMR5CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76337   TIMER_CTRL5_TMR5CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76338   TIMER_CTRL5_TMR5CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76339   TIMER_CTRL5_TMR5CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76340   TIMER_CTRL5_TMR5CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76341   TIMER_CTRL5_TMR5CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76342   TIMER_CTRL5_TMR5CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76343   TIMER_CTRL5_TMR5CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76344   TIMER_CTRL5_TMR5CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76345   TIMER_CTRL5_TMR5CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76346   TIMER_CTRL5_TMR5CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76347   TIMER_CTRL5_TMR5CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76348   TIMER_CTRL5_TMR5CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76349   TIMER_CTRL5_TMR5CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76350   TIMER_CTRL5_TMR5CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76351   TIMER_CTRL5_TMR5CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76352   TIMER_CTRL5_TMR5CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76353   TIMER_CTRL5_TMR5CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76354   TIMER_CTRL5_TMR5CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76355   TIMER_CTRL5_TMR5CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76356   TIMER_CTRL5_TMR5CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76357   TIMER_CTRL5_TMR5CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76358   TIMER_CTRL5_TMR5CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76359   TIMER_CTRL5_TMR5CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76360 } TIMER_CTRL5_TMR5CLK_Enum;
76361 
76362 /* ===============================================  TIMER CTRL5 TMR5FN [4..7]  =============================================== */
76363 typedef enum {                                  /*!< TIMER_CTRL5_TMR5FN                                                        */
76364   TIMER_CTRL5_TMR5FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
76365                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
76366                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
76367   TIMER_CTRL5_TMR5FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
76368                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
76369                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
76370                                                      for TMR_LMT iterations.                                                   */
76371   TIMER_CTRL5_TMR5FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
76372                                                      clock pulse. CMP1 dictates the low phase of the output
76373                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
76374   TIMER_CTRL5_TMR5FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76375                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
76376                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
76377                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
76378                                                      Both OUT0 and OUT1 can be inverted individually applications
76379                                                      with POL0/POL1 = 0x1.                                                     */
76380   TIMER_CTRL5_TMR5FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76381                                                      pattern repeats after reaching LMT.                                       */
76382 } TIMER_CTRL5_TMR5FN_Enum;
76383 
76384 /* ==============================================  TIMER CTRL5 TMR5POL1 [3..3]  ============================================== */
76385 typedef enum {                                  /*!< TIMER_CTRL5_TMR5POL1                                                      */
76386   TIMER_CTRL5_TMR5POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR5OUT1 pin is the same as the
76387                                                      timer output.                                                             */
76388   TIMER_CTRL5_TMR5POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR5OUT1 pin is the inverse of
76389                                                      the timer output.                                                         */
76390 } TIMER_CTRL5_TMR5POL1_Enum;
76391 
76392 /* ==============================================  TIMER CTRL5 TMR5POL0 [2..2]  ============================================== */
76393 typedef enum {                                  /*!< TIMER_CTRL5_TMR5POL0                                                      */
76394   TIMER_CTRL5_TMR5POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR5OUT0 pin is the same as the
76395                                                      timer output.                                                             */
76396   TIMER_CTRL5_TMR5POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR5OUT0 pin is the inverse of
76397                                                      the timer output.                                                         */
76398 } TIMER_CTRL5_TMR5POL0_Enum;
76399 
76400 /* ==============================================  TIMER CTRL5 TMR5CLR [1..1]  =============================================== */
76401 typedef enum {                                  /*!< TIMER_CTRL5_TMR5CLR                                                       */
76402   TIMER_CTRL5_TMR5CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76403                                                      cleared to its reset state # (0 for count up counter, CMP0
76404                                                      for down counter)                                                         */
76405   TIMER_CTRL5_TMR5CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
76406 } TIMER_CTRL5_TMR5CLR_Enum;
76407 
76408 /* ===============================================  TIMER CTRL5 TMR5EN [0..0]  =============================================== */
76409 typedef enum {                                  /*!< TIMER_CTRL5_TMR5EN                                                        */
76410   TIMER_CTRL5_TMR5EN_DIS               = 0,     /*!< DIS : Counter/Timer 5 Disable.                                            */
76411   TIMER_CTRL5_TMR5EN_EN                = 1,     /*!< EN : Counter/Timer 5 Enable.                                              */
76412 } TIMER_CTRL5_TMR5EN_Enum;
76413 
76414 /* ========================================================  TIMER5  ========================================================= */
76415 /* =======================================================  TMR5CMP0  ======================================================== */
76416 /* =======================================================  TMR5CMP1  ======================================================== */
76417 /* =========================================================  MODE5  ========================================================= */
76418 /* ============================================  TIMER MODE5 TMR5TRIGSEL [8..15]  ============================================ */
76419 typedef enum {                                  /*!< TIMER_MODE5_TMR5TRIGSEL                                                   */
76420   TIMER_MODE5_TMR5TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76421   TIMER_MODE5_TMR5TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76422   TIMER_MODE5_TMR5TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76423   TIMER_MODE5_TMR5TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76424   TIMER_MODE5_TMR5TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76425   TIMER_MODE5_TMR5TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76426   TIMER_MODE5_TMR5TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76427   TIMER_MODE5_TMR5TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76428   TIMER_MODE5_TMR5TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76429   TIMER_MODE5_TMR5TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76430   TIMER_MODE5_TMR5TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76431   TIMER_MODE5_TMR5TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76432   TIMER_MODE5_TMR5TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76433   TIMER_MODE5_TMR5TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76434   TIMER_MODE5_TMR5TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76435   TIMER_MODE5_TMR5TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76436   TIMER_MODE5_TMR5TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76437   TIMER_MODE5_TMR5TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76438   TIMER_MODE5_TMR5TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76439   TIMER_MODE5_TMR5TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76440   TIMER_MODE5_TMR5TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76441   TIMER_MODE5_TMR5TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76442   TIMER_MODE5_TMR5TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76443   TIMER_MODE5_TMR5TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76444   TIMER_MODE5_TMR5TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76445   TIMER_MODE5_TMR5TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76446   TIMER_MODE5_TMR5TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76447   TIMER_MODE5_TMR5TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76448   TIMER_MODE5_TMR5TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76449   TIMER_MODE5_TMR5TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76450   TIMER_MODE5_TMR5TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76451   TIMER_MODE5_TMR5TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76452   TIMER_MODE5_TMR5TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76453   TIMER_MODE5_TMR5TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76454 } TIMER_MODE5_TMR5TRIGSEL_Enum;
76455 
76456 /* ======================================================  TMR5LMTVAL  ======================================================= */
76457 /* =========================================================  CTRL6  ========================================================= */
76458 /* ============================================  TIMER CTRL6 TMR6TMODE [16..17]  ============================================= */
76459 typedef enum {                                  /*!< TIMER_CTRL6_TMR6TMODE                                                     */
76460   TIMER_CTRL6_TMR6TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
76461   TIMER_CTRL6_TMR6TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76462   TIMER_CTRL6_TMR6TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76463   TIMER_CTRL6_TMR6TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76464 } TIMER_CTRL6_TMR6TMODE_Enum;
76465 
76466 /* ==============================================  TIMER CTRL6 TMR6CLK [8..15]  ============================================== */
76467 typedef enum {                                  /*!< TIMER_CTRL6_TMR6CLK                                                       */
76468   TIMER_CTRL6_TMR6CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
76469   TIMER_CTRL6_TMR6CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76470   TIMER_CTRL6_TMR6CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76471   TIMER_CTRL6_TMR6CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76472   TIMER_CTRL6_TMR6CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76473   TIMER_CTRL6_TMR6CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76474   TIMER_CTRL6_TMR6CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
76475   TIMER_CTRL6_TMR6CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76476   TIMER_CTRL6_TMR6CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76477   TIMER_CTRL6_TMR6CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76478   TIMER_CTRL6_TMR6CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76479   TIMER_CTRL6_TMR6CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76480   TIMER_CTRL6_TMR6CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76481   TIMER_CTRL6_TMR6CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76482   TIMER_CTRL6_TMR6CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76483   TIMER_CTRL6_TMR6CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76484   TIMER_CTRL6_TMR6CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76485   TIMER_CTRL6_TMR6CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76486   TIMER_CTRL6_TMR6CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76487   TIMER_CTRL6_TMR6CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76488   TIMER_CTRL6_TMR6CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76489   TIMER_CTRL6_TMR6CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76490   TIMER_CTRL6_TMR6CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76491   TIMER_CTRL6_TMR6CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76492   TIMER_CTRL6_TMR6CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76493   TIMER_CTRL6_TMR6CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76494   TIMER_CTRL6_TMR6CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76495   TIMER_CTRL6_TMR6CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76496   TIMER_CTRL6_TMR6CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76497   TIMER_CTRL6_TMR6CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76498   TIMER_CTRL6_TMR6CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76499   TIMER_CTRL6_TMR6CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76500   TIMER_CTRL6_TMR6CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76501   TIMER_CTRL6_TMR6CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76502   TIMER_CTRL6_TMR6CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76503   TIMER_CTRL6_TMR6CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76504   TIMER_CTRL6_TMR6CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76505   TIMER_CTRL6_TMR6CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76506   TIMER_CTRL6_TMR6CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76507   TIMER_CTRL6_TMR6CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76508   TIMER_CTRL6_TMR6CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76509   TIMER_CTRL6_TMR6CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76510   TIMER_CTRL6_TMR6CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76511   TIMER_CTRL6_TMR6CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76512   TIMER_CTRL6_TMR6CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76513   TIMER_CTRL6_TMR6CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76514   TIMER_CTRL6_TMR6CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76515   TIMER_CTRL6_TMR6CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76516   TIMER_CTRL6_TMR6CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76517   TIMER_CTRL6_TMR6CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76518   TIMER_CTRL6_TMR6CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76519   TIMER_CTRL6_TMR6CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76520   TIMER_CTRL6_TMR6CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76521   TIMER_CTRL6_TMR6CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76522   TIMER_CTRL6_TMR6CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76523   TIMER_CTRL6_TMR6CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76524   TIMER_CTRL6_TMR6CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76525   TIMER_CTRL6_TMR6CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76526 } TIMER_CTRL6_TMR6CLK_Enum;
76527 
76528 /* ===============================================  TIMER CTRL6 TMR6FN [4..7]  =============================================== */
76529 typedef enum {                                  /*!< TIMER_CTRL6_TMR6FN                                                        */
76530   TIMER_CTRL6_TMR6FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
76531                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
76532                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
76533   TIMER_CTRL6_TMR6FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
76534                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
76535                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
76536                                                      for TMR_LMT iterations.                                                   */
76537   TIMER_CTRL6_TMR6FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
76538                                                      clock pulse. CMP1 dictates the low phase of the output
76539                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
76540   TIMER_CTRL6_TMR6FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76541                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
76542                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
76543                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
76544                                                      Both OUT0 and OUT1 can be inverted individually applications
76545                                                      with POL0/POL1 = 0x1.                                                     */
76546   TIMER_CTRL6_TMR6FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76547                                                      pattern repeats after reaching LMT.                                       */
76548 } TIMER_CTRL6_TMR6FN_Enum;
76549 
76550 /* ==============================================  TIMER CTRL6 TMR6POL1 [3..3]  ============================================== */
76551 typedef enum {                                  /*!< TIMER_CTRL6_TMR6POL1                                                      */
76552   TIMER_CTRL6_TMR6POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR6OUT1 pin is the same as the
76553                                                      timer output.                                                             */
76554   TIMER_CTRL6_TMR6POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR6OUT1 pin is the inverse of
76555                                                      the timer output.                                                         */
76556 } TIMER_CTRL6_TMR6POL1_Enum;
76557 
76558 /* ==============================================  TIMER CTRL6 TMR6POL0 [2..2]  ============================================== */
76559 typedef enum {                                  /*!< TIMER_CTRL6_TMR6POL0                                                      */
76560   TIMER_CTRL6_TMR6POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR6OUT0 pin is the same as the
76561                                                      timer output.                                                             */
76562   TIMER_CTRL6_TMR6POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR6OUT0 pin is the inverse of
76563                                                      the timer output.                                                         */
76564 } TIMER_CTRL6_TMR6POL0_Enum;
76565 
76566 /* ==============================================  TIMER CTRL6 TMR6CLR [1..1]  =============================================== */
76567 typedef enum {                                  /*!< TIMER_CTRL6_TMR6CLR                                                       */
76568   TIMER_CTRL6_TMR6CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76569                                                      cleared to its reset state # (0 for count up counter, CMP0
76570                                                      for down counter)                                                         */
76571   TIMER_CTRL6_TMR6CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
76572 } TIMER_CTRL6_TMR6CLR_Enum;
76573 
76574 /* ===============================================  TIMER CTRL6 TMR6EN [0..0]  =============================================== */
76575 typedef enum {                                  /*!< TIMER_CTRL6_TMR6EN                                                        */
76576   TIMER_CTRL6_TMR6EN_DIS               = 0,     /*!< DIS : Counter/Timer 6 Disable.                                            */
76577   TIMER_CTRL6_TMR6EN_EN                = 1,     /*!< EN : Counter/Timer 6 Enable.                                              */
76578 } TIMER_CTRL6_TMR6EN_Enum;
76579 
76580 /* ========================================================  TIMER6  ========================================================= */
76581 /* =======================================================  TMR6CMP0  ======================================================== */
76582 /* =======================================================  TMR6CMP1  ======================================================== */
76583 /* =========================================================  MODE6  ========================================================= */
76584 /* ============================================  TIMER MODE6 TMR6TRIGSEL [8..15]  ============================================ */
76585 typedef enum {                                  /*!< TIMER_MODE6_TMR6TRIGSEL                                                   */
76586   TIMER_MODE6_TMR6TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76587   TIMER_MODE6_TMR6TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76588   TIMER_MODE6_TMR6TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76589   TIMER_MODE6_TMR6TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76590   TIMER_MODE6_TMR6TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76591   TIMER_MODE6_TMR6TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76592   TIMER_MODE6_TMR6TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76593   TIMER_MODE6_TMR6TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76594   TIMER_MODE6_TMR6TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76595   TIMER_MODE6_TMR6TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76596   TIMER_MODE6_TMR6TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76597   TIMER_MODE6_TMR6TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76598   TIMER_MODE6_TMR6TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76599   TIMER_MODE6_TMR6TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76600   TIMER_MODE6_TMR6TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76601   TIMER_MODE6_TMR6TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76602   TIMER_MODE6_TMR6TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76603   TIMER_MODE6_TMR6TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76604   TIMER_MODE6_TMR6TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76605   TIMER_MODE6_TMR6TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76606   TIMER_MODE6_TMR6TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76607   TIMER_MODE6_TMR6TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76608   TIMER_MODE6_TMR6TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76609   TIMER_MODE6_TMR6TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76610   TIMER_MODE6_TMR6TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76611   TIMER_MODE6_TMR6TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76612   TIMER_MODE6_TMR6TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76613   TIMER_MODE6_TMR6TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76614   TIMER_MODE6_TMR6TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76615   TIMER_MODE6_TMR6TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76616   TIMER_MODE6_TMR6TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76617   TIMER_MODE6_TMR6TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76618   TIMER_MODE6_TMR6TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76619   TIMER_MODE6_TMR6TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76620 } TIMER_MODE6_TMR6TRIGSEL_Enum;
76621 
76622 /* ======================================================  TMR6LMTVAL  ======================================================= */
76623 /* =========================================================  CTRL7  ========================================================= */
76624 /* ============================================  TIMER CTRL7 TMR7TMODE [16..17]  ============================================= */
76625 typedef enum {                                  /*!< TIMER_CTRL7_TMR7TMODE                                                     */
76626   TIMER_CTRL7_TMR7TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
76627   TIMER_CTRL7_TMR7TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76628   TIMER_CTRL7_TMR7TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76629   TIMER_CTRL7_TMR7TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76630 } TIMER_CTRL7_TMR7TMODE_Enum;
76631 
76632 /* ==============================================  TIMER CTRL7 TMR7CLK [8..15]  ============================================== */
76633 typedef enum {                                  /*!< TIMER_CTRL7_TMR7CLK                                                       */
76634   TIMER_CTRL7_TMR7CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
76635   TIMER_CTRL7_TMR7CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76636   TIMER_CTRL7_TMR7CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76637   TIMER_CTRL7_TMR7CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76638   TIMER_CTRL7_TMR7CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76639   TIMER_CTRL7_TMR7CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76640   TIMER_CTRL7_TMR7CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
76641   TIMER_CTRL7_TMR7CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76642   TIMER_CTRL7_TMR7CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76643   TIMER_CTRL7_TMR7CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76644   TIMER_CTRL7_TMR7CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76645   TIMER_CTRL7_TMR7CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76646   TIMER_CTRL7_TMR7CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76647   TIMER_CTRL7_TMR7CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76648   TIMER_CTRL7_TMR7CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76649   TIMER_CTRL7_TMR7CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76650   TIMER_CTRL7_TMR7CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76651   TIMER_CTRL7_TMR7CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76652   TIMER_CTRL7_TMR7CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76653   TIMER_CTRL7_TMR7CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76654   TIMER_CTRL7_TMR7CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76655   TIMER_CTRL7_TMR7CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76656   TIMER_CTRL7_TMR7CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76657   TIMER_CTRL7_TMR7CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76658   TIMER_CTRL7_TMR7CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76659   TIMER_CTRL7_TMR7CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76660   TIMER_CTRL7_TMR7CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76661   TIMER_CTRL7_TMR7CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76662   TIMER_CTRL7_TMR7CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76663   TIMER_CTRL7_TMR7CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76664   TIMER_CTRL7_TMR7CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76665   TIMER_CTRL7_TMR7CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76666   TIMER_CTRL7_TMR7CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76667   TIMER_CTRL7_TMR7CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76668   TIMER_CTRL7_TMR7CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76669   TIMER_CTRL7_TMR7CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76670   TIMER_CTRL7_TMR7CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76671   TIMER_CTRL7_TMR7CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76672   TIMER_CTRL7_TMR7CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76673   TIMER_CTRL7_TMR7CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76674   TIMER_CTRL7_TMR7CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76675   TIMER_CTRL7_TMR7CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76676   TIMER_CTRL7_TMR7CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76677   TIMER_CTRL7_TMR7CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76678   TIMER_CTRL7_TMR7CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76679   TIMER_CTRL7_TMR7CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76680   TIMER_CTRL7_TMR7CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76681   TIMER_CTRL7_TMR7CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76682   TIMER_CTRL7_TMR7CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76683   TIMER_CTRL7_TMR7CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76684   TIMER_CTRL7_TMR7CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76685   TIMER_CTRL7_TMR7CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76686   TIMER_CTRL7_TMR7CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76687   TIMER_CTRL7_TMR7CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76688   TIMER_CTRL7_TMR7CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76689   TIMER_CTRL7_TMR7CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76690   TIMER_CTRL7_TMR7CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76691   TIMER_CTRL7_TMR7CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76692 } TIMER_CTRL7_TMR7CLK_Enum;
76693 
76694 /* ===============================================  TIMER CTRL7 TMR7FN [4..7]  =============================================== */
76695 typedef enum {                                  /*!< TIMER_CTRL7_TMR7FN                                                        */
76696   TIMER_CTRL7_TMR7FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
76697                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
76698                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
76699   TIMER_CTRL7_TMR7FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
76700                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
76701                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
76702                                                      for TMR_LMT iterations.                                                   */
76703   TIMER_CTRL7_TMR7FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
76704                                                      clock pulse. CMP1 dictates the low phase of the output
76705                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
76706   TIMER_CTRL7_TMR7FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76707                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
76708                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
76709                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
76710                                                      Both OUT0 and OUT1 can be inverted individually applications
76711                                                      with POL0/POL1 = 0x1.                                                     */
76712   TIMER_CTRL7_TMR7FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76713                                                      pattern repeats after reaching LMT.                                       */
76714 } TIMER_CTRL7_TMR7FN_Enum;
76715 
76716 /* ==============================================  TIMER CTRL7 TMR7POL1 [3..3]  ============================================== */
76717 typedef enum {                                  /*!< TIMER_CTRL7_TMR7POL1                                                      */
76718   TIMER_CTRL7_TMR7POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR7OUT1 pin is the same as the
76719                                                      timer output.                                                             */
76720   TIMER_CTRL7_TMR7POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR7OUT1 pin is the inverse of
76721                                                      the timer output.                                                         */
76722 } TIMER_CTRL7_TMR7POL1_Enum;
76723 
76724 /* ==============================================  TIMER CTRL7 TMR7POL0 [2..2]  ============================================== */
76725 typedef enum {                                  /*!< TIMER_CTRL7_TMR7POL0                                                      */
76726   TIMER_CTRL7_TMR7POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR7OUT0 pin is the same as the
76727                                                      timer output.                                                             */
76728   TIMER_CTRL7_TMR7POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR7OUT0 pin is the inverse of
76729                                                      the timer output.                                                         */
76730 } TIMER_CTRL7_TMR7POL0_Enum;
76731 
76732 /* ==============================================  TIMER CTRL7 TMR7CLR [1..1]  =============================================== */
76733 typedef enum {                                  /*!< TIMER_CTRL7_TMR7CLR                                                       */
76734   TIMER_CTRL7_TMR7CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76735                                                      cleared to its reset state # (0 for count up counter, CMP0
76736                                                      for down counter)                                                         */
76737   TIMER_CTRL7_TMR7CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
76738 } TIMER_CTRL7_TMR7CLR_Enum;
76739 
76740 /* ===============================================  TIMER CTRL7 TMR7EN [0..0]  =============================================== */
76741 typedef enum {                                  /*!< TIMER_CTRL7_TMR7EN                                                        */
76742   TIMER_CTRL7_TMR7EN_DIS               = 0,     /*!< DIS : Counter/Timer 7 Disable.                                            */
76743   TIMER_CTRL7_TMR7EN_EN                = 1,     /*!< EN : Counter/Timer 7 Enable.                                              */
76744 } TIMER_CTRL7_TMR7EN_Enum;
76745 
76746 /* ========================================================  TIMER7  ========================================================= */
76747 /* =======================================================  TMR7CMP0  ======================================================== */
76748 /* =======================================================  TMR7CMP1  ======================================================== */
76749 /* =========================================================  MODE7  ========================================================= */
76750 /* ============================================  TIMER MODE7 TMR7TRIGSEL [8..15]  ============================================ */
76751 typedef enum {                                  /*!< TIMER_MODE7_TMR7TRIGSEL                                                   */
76752   TIMER_MODE7_TMR7TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76753   TIMER_MODE7_TMR7TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76754   TIMER_MODE7_TMR7TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76755   TIMER_MODE7_TMR7TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76756   TIMER_MODE7_TMR7TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76757   TIMER_MODE7_TMR7TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76758   TIMER_MODE7_TMR7TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76759   TIMER_MODE7_TMR7TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76760   TIMER_MODE7_TMR7TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76761   TIMER_MODE7_TMR7TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76762   TIMER_MODE7_TMR7TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76763   TIMER_MODE7_TMR7TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76764   TIMER_MODE7_TMR7TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76765   TIMER_MODE7_TMR7TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76766   TIMER_MODE7_TMR7TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76767   TIMER_MODE7_TMR7TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76768   TIMER_MODE7_TMR7TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76769   TIMER_MODE7_TMR7TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76770   TIMER_MODE7_TMR7TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76771   TIMER_MODE7_TMR7TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76772   TIMER_MODE7_TMR7TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76773   TIMER_MODE7_TMR7TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76774   TIMER_MODE7_TMR7TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76775   TIMER_MODE7_TMR7TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76776   TIMER_MODE7_TMR7TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76777   TIMER_MODE7_TMR7TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76778   TIMER_MODE7_TMR7TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76779   TIMER_MODE7_TMR7TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76780   TIMER_MODE7_TMR7TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76781   TIMER_MODE7_TMR7TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76782   TIMER_MODE7_TMR7TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76783   TIMER_MODE7_TMR7TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76784   TIMER_MODE7_TMR7TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76785   TIMER_MODE7_TMR7TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76786 } TIMER_MODE7_TMR7TRIGSEL_Enum;
76787 
76788 /* ======================================================  TMR7LMTVAL  ======================================================= */
76789 /* =========================================================  CTRL8  ========================================================= */
76790 /* ============================================  TIMER CTRL8 TMR8TMODE [16..17]  ============================================= */
76791 typedef enum {                                  /*!< TIMER_CTRL8_TMR8TMODE                                                     */
76792   TIMER_CTRL8_TMR8TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
76793   TIMER_CTRL8_TMR8TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76794   TIMER_CTRL8_TMR8TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76795   TIMER_CTRL8_TMR8TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76796 } TIMER_CTRL8_TMR8TMODE_Enum;
76797 
76798 /* ==============================================  TIMER CTRL8 TMR8CLK [8..15]  ============================================== */
76799 typedef enum {                                  /*!< TIMER_CTRL8_TMR8CLK                                                       */
76800   TIMER_CTRL8_TMR8CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
76801   TIMER_CTRL8_TMR8CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76802   TIMER_CTRL8_TMR8CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76803   TIMER_CTRL8_TMR8CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76804   TIMER_CTRL8_TMR8CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76805   TIMER_CTRL8_TMR8CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76806   TIMER_CTRL8_TMR8CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
76807   TIMER_CTRL8_TMR8CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76808   TIMER_CTRL8_TMR8CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76809   TIMER_CTRL8_TMR8CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76810   TIMER_CTRL8_TMR8CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76811   TIMER_CTRL8_TMR8CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76812   TIMER_CTRL8_TMR8CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76813   TIMER_CTRL8_TMR8CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76814   TIMER_CTRL8_TMR8CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76815   TIMER_CTRL8_TMR8CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76816   TIMER_CTRL8_TMR8CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76817   TIMER_CTRL8_TMR8CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76818   TIMER_CTRL8_TMR8CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76819   TIMER_CTRL8_TMR8CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76820   TIMER_CTRL8_TMR8CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76821   TIMER_CTRL8_TMR8CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76822   TIMER_CTRL8_TMR8CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76823   TIMER_CTRL8_TMR8CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76824   TIMER_CTRL8_TMR8CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76825   TIMER_CTRL8_TMR8CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76826   TIMER_CTRL8_TMR8CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76827   TIMER_CTRL8_TMR8CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76828   TIMER_CTRL8_TMR8CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76829   TIMER_CTRL8_TMR8CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76830   TIMER_CTRL8_TMR8CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76831   TIMER_CTRL8_TMR8CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76832   TIMER_CTRL8_TMR8CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76833   TIMER_CTRL8_TMR8CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
76834   TIMER_CTRL8_TMR8CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
76835   TIMER_CTRL8_TMR8CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
76836   TIMER_CTRL8_TMR8CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
76837   TIMER_CTRL8_TMR8CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
76838   TIMER_CTRL8_TMR8CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
76839   TIMER_CTRL8_TMR8CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
76840   TIMER_CTRL8_TMR8CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
76841   TIMER_CTRL8_TMR8CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
76842   TIMER_CTRL8_TMR8CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
76843   TIMER_CTRL8_TMR8CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
76844   TIMER_CTRL8_TMR8CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
76845   TIMER_CTRL8_TMR8CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
76846   TIMER_CTRL8_TMR8CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
76847   TIMER_CTRL8_TMR8CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
76848   TIMER_CTRL8_TMR8CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
76849   TIMER_CTRL8_TMR8CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
76850   TIMER_CTRL8_TMR8CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
76851   TIMER_CTRL8_TMR8CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
76852   TIMER_CTRL8_TMR8CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
76853   TIMER_CTRL8_TMR8CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
76854   TIMER_CTRL8_TMR8CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
76855   TIMER_CTRL8_TMR8CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
76856   TIMER_CTRL8_TMR8CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
76857   TIMER_CTRL8_TMR8CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
76858 } TIMER_CTRL8_TMR8CLK_Enum;
76859 
76860 /* ===============================================  TIMER CTRL8 TMR8FN [4..7]  =============================================== */
76861 typedef enum {                                  /*!< TIMER_CTRL8_TMR8FN                                                        */
76862   TIMER_CTRL8_TMR8FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
76863                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
76864                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
76865   TIMER_CTRL8_TMR8FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
76866                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
76867                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
76868                                                      for TMR_LMT iterations.                                                   */
76869   TIMER_CTRL8_TMR8FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
76870                                                      clock pulse. CMP1 dictates the low phase of the output
76871                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
76872   TIMER_CTRL8_TMR8FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
76873                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
76874                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
76875                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
76876                                                      Both OUT0 and OUT1 can be inverted individually applications
76877                                                      with POL0/POL1 = 0x1.                                                     */
76878   TIMER_CTRL8_TMR8FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
76879                                                      pattern repeats after reaching LMT.                                       */
76880 } TIMER_CTRL8_TMR8FN_Enum;
76881 
76882 /* ==============================================  TIMER CTRL8 TMR8POL1 [3..3]  ============================================== */
76883 typedef enum {                                  /*!< TIMER_CTRL8_TMR8POL1                                                      */
76884   TIMER_CTRL8_TMR8POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR8OUT1 pin is the same as the
76885                                                      timer output.                                                             */
76886   TIMER_CTRL8_TMR8POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR8OUT1 pin is the inverse of
76887                                                      the timer output.                                                         */
76888 } TIMER_CTRL8_TMR8POL1_Enum;
76889 
76890 /* ==============================================  TIMER CTRL8 TMR8POL0 [2..2]  ============================================== */
76891 typedef enum {                                  /*!< TIMER_CTRL8_TMR8POL0                                                      */
76892   TIMER_CTRL8_TMR8POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR8OUT0 pin is the same as the
76893                                                      timer output.                                                             */
76894   TIMER_CTRL8_TMR8POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR8OUT0 pin is the inverse of
76895                                                      the timer output.                                                         */
76896 } TIMER_CTRL8_TMR8POL0_Enum;
76897 
76898 /* ==============================================  TIMER CTRL8 TMR8CLR [1..1]  =============================================== */
76899 typedef enum {                                  /*!< TIMER_CTRL8_TMR8CLR                                                       */
76900   TIMER_CTRL8_TMR8CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
76901                                                      cleared to its reset state # (0 for count up counter, CMP0
76902                                                      for down counter)                                                         */
76903   TIMER_CTRL8_TMR8CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
76904 } TIMER_CTRL8_TMR8CLR_Enum;
76905 
76906 /* ===============================================  TIMER CTRL8 TMR8EN [0..0]  =============================================== */
76907 typedef enum {                                  /*!< TIMER_CTRL8_TMR8EN                                                        */
76908   TIMER_CTRL8_TMR8EN_DIS               = 0,     /*!< DIS : Counter/Timer 8 Disable.                                            */
76909   TIMER_CTRL8_TMR8EN_EN                = 1,     /*!< EN : Counter/Timer 8 Enable.                                              */
76910 } TIMER_CTRL8_TMR8EN_Enum;
76911 
76912 /* ========================================================  TIMER8  ========================================================= */
76913 /* =======================================================  TMR8CMP0  ======================================================== */
76914 /* =======================================================  TMR8CMP1  ======================================================== */
76915 /* =========================================================  MODE8  ========================================================= */
76916 /* ============================================  TIMER MODE8 TMR8TRIGSEL [8..15]  ============================================ */
76917 typedef enum {                                  /*!< TIMER_MODE8_TMR8TRIGSEL                                                   */
76918   TIMER_MODE8_TMR8TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
76919   TIMER_MODE8_TMR8TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
76920   TIMER_MODE8_TMR8TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
76921   TIMER_MODE8_TMR8TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
76922   TIMER_MODE8_TMR8TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
76923   TIMER_MODE8_TMR8TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
76924   TIMER_MODE8_TMR8TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
76925   TIMER_MODE8_TMR8TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
76926   TIMER_MODE8_TMR8TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
76927   TIMER_MODE8_TMR8TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
76928   TIMER_MODE8_TMR8TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
76929   TIMER_MODE8_TMR8TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
76930   TIMER_MODE8_TMR8TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
76931   TIMER_MODE8_TMR8TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
76932   TIMER_MODE8_TMR8TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
76933   TIMER_MODE8_TMR8TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
76934   TIMER_MODE8_TMR8TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
76935   TIMER_MODE8_TMR8TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
76936   TIMER_MODE8_TMR8TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
76937   TIMER_MODE8_TMR8TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
76938   TIMER_MODE8_TMR8TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
76939   TIMER_MODE8_TMR8TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
76940   TIMER_MODE8_TMR8TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
76941   TIMER_MODE8_TMR8TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
76942   TIMER_MODE8_TMR8TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
76943   TIMER_MODE8_TMR8TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
76944   TIMER_MODE8_TMR8TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
76945   TIMER_MODE8_TMR8TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
76946   TIMER_MODE8_TMR8TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
76947   TIMER_MODE8_TMR8TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
76948   TIMER_MODE8_TMR8TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
76949   TIMER_MODE8_TMR8TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
76950   TIMER_MODE8_TMR8TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
76951   TIMER_MODE8_TMR8TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
76952 } TIMER_MODE8_TMR8TRIGSEL_Enum;
76953 
76954 /* ======================================================  TMR8LMTVAL  ======================================================= */
76955 /* =========================================================  CTRL9  ========================================================= */
76956 /* ============================================  TIMER CTRL9 TMR9TMODE [16..17]  ============================================= */
76957 typedef enum {                                  /*!< TIMER_CTRL9_TMR9TMODE                                                     */
76958   TIMER_CTRL9_TMR9TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
76959   TIMER_CTRL9_TMR9TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
76960   TIMER_CTRL9_TMR9TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
76961   TIMER_CTRL9_TMR9TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
76962 } TIMER_CTRL9_TMR9TMODE_Enum;
76963 
76964 /* ==============================================  TIMER CTRL9 TMR9CLK [8..15]  ============================================== */
76965 typedef enum {                                  /*!< TIMER_CTRL9_TMR9CLK                                                       */
76966   TIMER_CTRL9_TMR9CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
76967   TIMER_CTRL9_TMR9CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
76968   TIMER_CTRL9_TMR9CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
76969   TIMER_CTRL9_TMR9CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
76970   TIMER_CTRL9_TMR9CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
76971   TIMER_CTRL9_TMR9CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
76972   TIMER_CTRL9_TMR9CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
76973   TIMER_CTRL9_TMR9CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
76974   TIMER_CTRL9_TMR9CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
76975   TIMER_CTRL9_TMR9CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
76976   TIMER_CTRL9_TMR9CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
76977   TIMER_CTRL9_TMR9CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
76978   TIMER_CTRL9_TMR9CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
76979   TIMER_CTRL9_TMR9CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
76980   TIMER_CTRL9_TMR9CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
76981   TIMER_CTRL9_TMR9CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
76982   TIMER_CTRL9_TMR9CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
76983   TIMER_CTRL9_TMR9CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
76984   TIMER_CTRL9_TMR9CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
76985   TIMER_CTRL9_TMR9CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
76986   TIMER_CTRL9_TMR9CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
76987   TIMER_CTRL9_TMR9CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
76988   TIMER_CTRL9_TMR9CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
76989   TIMER_CTRL9_TMR9CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
76990   TIMER_CTRL9_TMR9CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
76991   TIMER_CTRL9_TMR9CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
76992   TIMER_CTRL9_TMR9CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
76993   TIMER_CTRL9_TMR9CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
76994   TIMER_CTRL9_TMR9CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
76995   TIMER_CTRL9_TMR9CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
76996   TIMER_CTRL9_TMR9CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
76997   TIMER_CTRL9_TMR9CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
76998   TIMER_CTRL9_TMR9CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
76999   TIMER_CTRL9_TMR9CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
77000   TIMER_CTRL9_TMR9CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
77001   TIMER_CTRL9_TMR9CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
77002   TIMER_CTRL9_TMR9CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
77003   TIMER_CTRL9_TMR9CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
77004   TIMER_CTRL9_TMR9CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
77005   TIMER_CTRL9_TMR9CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
77006   TIMER_CTRL9_TMR9CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
77007   TIMER_CTRL9_TMR9CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
77008   TIMER_CTRL9_TMR9CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
77009   TIMER_CTRL9_TMR9CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
77010   TIMER_CTRL9_TMR9CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
77011   TIMER_CTRL9_TMR9CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
77012   TIMER_CTRL9_TMR9CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
77013   TIMER_CTRL9_TMR9CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
77014   TIMER_CTRL9_TMR9CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
77015   TIMER_CTRL9_TMR9CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
77016   TIMER_CTRL9_TMR9CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
77017   TIMER_CTRL9_TMR9CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
77018   TIMER_CTRL9_TMR9CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
77019   TIMER_CTRL9_TMR9CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
77020   TIMER_CTRL9_TMR9CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
77021   TIMER_CTRL9_TMR9CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
77022   TIMER_CTRL9_TMR9CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
77023   TIMER_CTRL9_TMR9CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
77024 } TIMER_CTRL9_TMR9CLK_Enum;
77025 
77026 /* ===============================================  TIMER CTRL9 TMR9FN [4..7]  =============================================== */
77027 typedef enum {                                  /*!< TIMER_CTRL9_TMR9FN                                                        */
77028   TIMER_CTRL9_TMR9FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
77029                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
77030                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
77031   TIMER_CTRL9_TMR9FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
77032                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
77033                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
77034                                                      for TMR_LMT iterations.                                                   */
77035   TIMER_CTRL9_TMR9FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
77036                                                      clock pulse. CMP1 dictates the low phase of the output
77037                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
77038   TIMER_CTRL9_TMR9FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
77039                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
77040                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
77041                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
77042                                                      Both OUT0 and OUT1 can be inverted individually applications
77043                                                      with POL0/POL1 = 0x1.                                                     */
77044   TIMER_CTRL9_TMR9FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
77045                                                      pattern repeats after reaching LMT.                                       */
77046 } TIMER_CTRL9_TMR9FN_Enum;
77047 
77048 /* ==============================================  TIMER CTRL9 TMR9POL1 [3..3]  ============================================== */
77049 typedef enum {                                  /*!< TIMER_CTRL9_TMR9POL1                                                      */
77050   TIMER_CTRL9_TMR9POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR9OUT1 pin is the same as the
77051                                                      timer output.                                                             */
77052   TIMER_CTRL9_TMR9POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR9OUT1 pin is the inverse of
77053                                                      the timer output.                                                         */
77054 } TIMER_CTRL9_TMR9POL1_Enum;
77055 
77056 /* ==============================================  TIMER CTRL9 TMR9POL0 [2..2]  ============================================== */
77057 typedef enum {                                  /*!< TIMER_CTRL9_TMR9POL0                                                      */
77058   TIMER_CTRL9_TMR9POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR9OUT0 pin is the same as the
77059                                                      timer output.                                                             */
77060   TIMER_CTRL9_TMR9POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR9OUT0 pin is the inverse of
77061                                                      the timer output.                                                         */
77062 } TIMER_CTRL9_TMR9POL0_Enum;
77063 
77064 /* ==============================================  TIMER CTRL9 TMR9CLR [1..1]  =============================================== */
77065 typedef enum {                                  /*!< TIMER_CTRL9_TMR9CLR                                                       */
77066   TIMER_CTRL9_TMR9CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
77067                                                      cleared to its reset state # (0 for count up counter, CMP0
77068                                                      for down counter)                                                         */
77069   TIMER_CTRL9_TMR9CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
77070 } TIMER_CTRL9_TMR9CLR_Enum;
77071 
77072 /* ===============================================  TIMER CTRL9 TMR9EN [0..0]  =============================================== */
77073 typedef enum {                                  /*!< TIMER_CTRL9_TMR9EN                                                        */
77074   TIMER_CTRL9_TMR9EN_DIS               = 0,     /*!< DIS : Counter/Timer 9 Disable.                                            */
77075   TIMER_CTRL9_TMR9EN_EN                = 1,     /*!< EN : Counter/Timer 9 Enable.                                              */
77076 } TIMER_CTRL9_TMR9EN_Enum;
77077 
77078 /* ========================================================  TIMER9  ========================================================= */
77079 /* =======================================================  TMR9CMP0  ======================================================== */
77080 /* =======================================================  TMR9CMP1  ======================================================== */
77081 /* =========================================================  MODE9  ========================================================= */
77082 /* ============================================  TIMER MODE9 TMR9TRIGSEL [8..15]  ============================================ */
77083 typedef enum {                                  /*!< TIMER_MODE9_TMR9TRIGSEL                                                   */
77084   TIMER_MODE9_TMR9TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
77085   TIMER_MODE9_TMR9TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
77086   TIMER_MODE9_TMR9TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
77087   TIMER_MODE9_TMR9TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
77088   TIMER_MODE9_TMR9TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
77089   TIMER_MODE9_TMR9TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
77090   TIMER_MODE9_TMR9TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
77091   TIMER_MODE9_TMR9TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
77092   TIMER_MODE9_TMR9TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
77093   TIMER_MODE9_TMR9TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
77094   TIMER_MODE9_TMR9TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
77095   TIMER_MODE9_TMR9TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
77096   TIMER_MODE9_TMR9TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
77097   TIMER_MODE9_TMR9TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
77098   TIMER_MODE9_TMR9TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
77099   TIMER_MODE9_TMR9TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
77100   TIMER_MODE9_TMR9TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
77101   TIMER_MODE9_TMR9TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
77102   TIMER_MODE9_TMR9TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
77103   TIMER_MODE9_TMR9TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
77104   TIMER_MODE9_TMR9TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
77105   TIMER_MODE9_TMR9TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
77106   TIMER_MODE9_TMR9TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
77107   TIMER_MODE9_TMR9TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
77108   TIMER_MODE9_TMR9TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
77109   TIMER_MODE9_TMR9TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
77110   TIMER_MODE9_TMR9TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
77111   TIMER_MODE9_TMR9TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
77112   TIMER_MODE9_TMR9TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
77113   TIMER_MODE9_TMR9TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
77114   TIMER_MODE9_TMR9TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
77115   TIMER_MODE9_TMR9TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
77116   TIMER_MODE9_TMR9TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
77117   TIMER_MODE9_TMR9TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
77118 } TIMER_MODE9_TMR9TRIGSEL_Enum;
77119 
77120 /* ======================================================  TMR9LMTVAL  ======================================================= */
77121 /* ========================================================  CTRL10  ========================================================= */
77122 /* ===========================================  TIMER CTRL10 TMR10TMODE [16..17]  ============================================ */
77123 typedef enum {                                  /*!< TIMER_CTRL10_TMR10TMODE                                                   */
77124   TIMER_CTRL10_TMR10TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
77125   TIMER_CTRL10_TMR10TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
77126   TIMER_CTRL10_TMR10TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
77127   TIMER_CTRL10_TMR10TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
77128 } TIMER_CTRL10_TMR10TMODE_Enum;
77129 
77130 /* =============================================  TIMER CTRL10 TMR10CLK [8..15]  ============================================= */
77131 typedef enum {                                  /*!< TIMER_CTRL10_TMR10CLK                                                     */
77132   TIMER_CTRL10_TMR10CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
77133   TIMER_CTRL10_TMR10CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
77134   TIMER_CTRL10_TMR10CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
77135   TIMER_CTRL10_TMR10CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
77136   TIMER_CTRL10_TMR10CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
77137   TIMER_CTRL10_TMR10CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
77138   TIMER_CTRL10_TMR10CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
77139   TIMER_CTRL10_TMR10CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
77140   TIMER_CTRL10_TMR10CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
77141   TIMER_CTRL10_TMR10CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
77142   TIMER_CTRL10_TMR10CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
77143   TIMER_CTRL10_TMR10CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
77144   TIMER_CTRL10_TMR10CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
77145   TIMER_CTRL10_TMR10CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
77146   TIMER_CTRL10_TMR10CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
77147   TIMER_CTRL10_TMR10CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
77148   TIMER_CTRL10_TMR10CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
77149   TIMER_CTRL10_TMR10CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
77150   TIMER_CTRL10_TMR10CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
77151   TIMER_CTRL10_TMR10CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
77152   TIMER_CTRL10_TMR10CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
77153   TIMER_CTRL10_TMR10CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
77154   TIMER_CTRL10_TMR10CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
77155   TIMER_CTRL10_TMR10CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
77156   TIMER_CTRL10_TMR10CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
77157   TIMER_CTRL10_TMR10CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
77158   TIMER_CTRL10_TMR10CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
77159   TIMER_CTRL10_TMR10CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
77160   TIMER_CTRL10_TMR10CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
77161   TIMER_CTRL10_TMR10CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
77162   TIMER_CTRL10_TMR10CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
77163   TIMER_CTRL10_TMR10CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
77164   TIMER_CTRL10_TMR10CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
77165   TIMER_CTRL10_TMR10CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
77166   TIMER_CTRL10_TMR10CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
77167   TIMER_CTRL10_TMR10CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
77168   TIMER_CTRL10_TMR10CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
77169   TIMER_CTRL10_TMR10CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
77170   TIMER_CTRL10_TMR10CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
77171   TIMER_CTRL10_TMR10CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
77172   TIMER_CTRL10_TMR10CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
77173   TIMER_CTRL10_TMR10CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
77174   TIMER_CTRL10_TMR10CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
77175   TIMER_CTRL10_TMR10CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
77176   TIMER_CTRL10_TMR10CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
77177   TIMER_CTRL10_TMR10CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
77178   TIMER_CTRL10_TMR10CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
77179   TIMER_CTRL10_TMR10CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
77180   TIMER_CTRL10_TMR10CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
77181   TIMER_CTRL10_TMR10CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
77182   TIMER_CTRL10_TMR10CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
77183   TIMER_CTRL10_TMR10CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
77184   TIMER_CTRL10_TMR10CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
77185   TIMER_CTRL10_TMR10CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
77186   TIMER_CTRL10_TMR10CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
77187   TIMER_CTRL10_TMR10CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
77188   TIMER_CTRL10_TMR10CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
77189   TIMER_CTRL10_TMR10CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
77190 } TIMER_CTRL10_TMR10CLK_Enum;
77191 
77192 /* ==============================================  TIMER CTRL10 TMR10FN [4..7]  ============================================== */
77193 typedef enum {                                  /*!< TIMER_CTRL10_TMR10FN                                                      */
77194   TIMER_CTRL10_TMR10FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
77195                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
77196                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
77197   TIMER_CTRL10_TMR10FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
77198                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
77199                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
77200                                                      for TMR_LMT iterations.                                                   */
77201   TIMER_CTRL10_TMR10FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
77202                                                      clock pulse. CMP1 dictates the low phase of the output
77203                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
77204   TIMER_CTRL10_TMR10FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
77205                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
77206                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
77207                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
77208                                                      Both OUT0 and OUT1 can be inverted individually applications
77209                                                      with POL0/POL1 = 0x1.                                                     */
77210   TIMER_CTRL10_TMR10FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
77211                                                      pattern repeats after reaching LMT.                                       */
77212 } TIMER_CTRL10_TMR10FN_Enum;
77213 
77214 /* =============================================  TIMER CTRL10 TMR10POL1 [3..3]  ============================================= */
77215 typedef enum {                                  /*!< TIMER_CTRL10_TMR10POL1                                                    */
77216   TIMER_CTRL10_TMR10POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR10OUT1 pin is the same as the
77217                                                      timer output.                                                             */
77218   TIMER_CTRL10_TMR10POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR10OUT1 pin is the inverse
77219                                                      of the timer output.                                                      */
77220 } TIMER_CTRL10_TMR10POL1_Enum;
77221 
77222 /* =============================================  TIMER CTRL10 TMR10POL0 [2..2]  ============================================= */
77223 typedef enum {                                  /*!< TIMER_CTRL10_TMR10POL0                                                    */
77224   TIMER_CTRL10_TMR10POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR10OUT0 pin is the same as the
77225                                                      timer output.                                                             */
77226   TIMER_CTRL10_TMR10POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR10OUT0 pin is the inverse
77227                                                      of the timer output.                                                      */
77228 } TIMER_CTRL10_TMR10POL0_Enum;
77229 
77230 /* =============================================  TIMER CTRL10 TMR10CLR [1..1]  ============================================== */
77231 typedef enum {                                  /*!< TIMER_CTRL10_TMR10CLR                                                     */
77232   TIMER_CTRL10_TMR10CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
77233                                                      cleared to its reset state # (0 for count up counter, CMP0
77234                                                      for down counter)                                                         */
77235   TIMER_CTRL10_TMR10CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
77236 } TIMER_CTRL10_TMR10CLR_Enum;
77237 
77238 /* ==============================================  TIMER CTRL10 TMR10EN [0..0]  ============================================== */
77239 typedef enum {                                  /*!< TIMER_CTRL10_TMR10EN                                                      */
77240   TIMER_CTRL10_TMR10EN_DIS             = 0,     /*!< DIS : Counter/Timer 10 Disable.                                           */
77241   TIMER_CTRL10_TMR10EN_EN              = 1,     /*!< EN : Counter/Timer 10 Enable.                                             */
77242 } TIMER_CTRL10_TMR10EN_Enum;
77243 
77244 /* ========================================================  TIMER10  ======================================================== */
77245 /* =======================================================  TMR10CMP0  ======================================================= */
77246 /* =======================================================  TMR10CMP1  ======================================================= */
77247 /* ========================================================  MODE10  ========================================================= */
77248 /* ===========================================  TIMER MODE10 TMR10TRIGSEL [8..15]  =========================================== */
77249 typedef enum {                                  /*!< TIMER_MODE10_TMR10TRIGSEL                                                 */
77250   TIMER_MODE10_TMR10TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
77251   TIMER_MODE10_TMR10TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
77252   TIMER_MODE10_TMR10TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
77253   TIMER_MODE10_TMR10TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
77254   TIMER_MODE10_TMR10TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
77255   TIMER_MODE10_TMR10TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
77256   TIMER_MODE10_TMR10TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
77257   TIMER_MODE10_TMR10TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
77258   TIMER_MODE10_TMR10TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
77259   TIMER_MODE10_TMR10TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
77260   TIMER_MODE10_TMR10TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
77261   TIMER_MODE10_TMR10TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
77262   TIMER_MODE10_TMR10TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
77263   TIMER_MODE10_TMR10TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
77264   TIMER_MODE10_TMR10TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
77265   TIMER_MODE10_TMR10TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
77266   TIMER_MODE10_TMR10TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
77267   TIMER_MODE10_TMR10TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
77268   TIMER_MODE10_TMR10TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
77269   TIMER_MODE10_TMR10TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
77270   TIMER_MODE10_TMR10TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
77271   TIMER_MODE10_TMR10TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
77272   TIMER_MODE10_TMR10TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
77273   TIMER_MODE10_TMR10TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
77274   TIMER_MODE10_TMR10TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
77275   TIMER_MODE10_TMR10TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
77276   TIMER_MODE10_TMR10TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
77277   TIMER_MODE10_TMR10TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
77278   TIMER_MODE10_TMR10TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
77279   TIMER_MODE10_TMR10TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
77280   TIMER_MODE10_TMR10TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
77281   TIMER_MODE10_TMR10TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
77282   TIMER_MODE10_TMR10TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
77283   TIMER_MODE10_TMR10TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
77284 } TIMER_MODE10_TMR10TRIGSEL_Enum;
77285 
77286 /* ======================================================  TMR10LMTVAL  ====================================================== */
77287 /* ========================================================  CTRL11  ========================================================= */
77288 /* ===========================================  TIMER CTRL11 TMR11TMODE [16..17]  ============================================ */
77289 typedef enum {                                  /*!< TIMER_CTRL11_TMR11TMODE                                                   */
77290   TIMER_CTRL11_TMR11TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
77291   TIMER_CTRL11_TMR11TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
77292   TIMER_CTRL11_TMR11TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
77293   TIMER_CTRL11_TMR11TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
77294 } TIMER_CTRL11_TMR11TMODE_Enum;
77295 
77296 /* =============================================  TIMER CTRL11 TMR11CLK [8..15]  ============================================= */
77297 typedef enum {                                  /*!< TIMER_CTRL11_TMR11CLK                                                     */
77298   TIMER_CTRL11_TMR11CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
77299   TIMER_CTRL11_TMR11CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
77300   TIMER_CTRL11_TMR11CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
77301   TIMER_CTRL11_TMR11CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
77302   TIMER_CTRL11_TMR11CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
77303   TIMER_CTRL11_TMR11CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
77304   TIMER_CTRL11_TMR11CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
77305   TIMER_CTRL11_TMR11CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
77306   TIMER_CTRL11_TMR11CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
77307   TIMER_CTRL11_TMR11CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
77308   TIMER_CTRL11_TMR11CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
77309   TIMER_CTRL11_TMR11CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
77310   TIMER_CTRL11_TMR11CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
77311   TIMER_CTRL11_TMR11CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
77312   TIMER_CTRL11_TMR11CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
77313   TIMER_CTRL11_TMR11CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
77314   TIMER_CTRL11_TMR11CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
77315   TIMER_CTRL11_TMR11CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
77316   TIMER_CTRL11_TMR11CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
77317   TIMER_CTRL11_TMR11CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
77318   TIMER_CTRL11_TMR11CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
77319   TIMER_CTRL11_TMR11CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
77320   TIMER_CTRL11_TMR11CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
77321   TIMER_CTRL11_TMR11CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
77322   TIMER_CTRL11_TMR11CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
77323   TIMER_CTRL11_TMR11CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
77324   TIMER_CTRL11_TMR11CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
77325   TIMER_CTRL11_TMR11CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
77326   TIMER_CTRL11_TMR11CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
77327   TIMER_CTRL11_TMR11CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
77328   TIMER_CTRL11_TMR11CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
77329   TIMER_CTRL11_TMR11CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
77330   TIMER_CTRL11_TMR11CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
77331   TIMER_CTRL11_TMR11CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
77332   TIMER_CTRL11_TMR11CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
77333   TIMER_CTRL11_TMR11CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
77334   TIMER_CTRL11_TMR11CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
77335   TIMER_CTRL11_TMR11CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
77336   TIMER_CTRL11_TMR11CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
77337   TIMER_CTRL11_TMR11CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
77338   TIMER_CTRL11_TMR11CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
77339   TIMER_CTRL11_TMR11CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
77340   TIMER_CTRL11_TMR11CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
77341   TIMER_CTRL11_TMR11CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
77342   TIMER_CTRL11_TMR11CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
77343   TIMER_CTRL11_TMR11CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
77344   TIMER_CTRL11_TMR11CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
77345   TIMER_CTRL11_TMR11CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
77346   TIMER_CTRL11_TMR11CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
77347   TIMER_CTRL11_TMR11CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
77348   TIMER_CTRL11_TMR11CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
77349   TIMER_CTRL11_TMR11CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
77350   TIMER_CTRL11_TMR11CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
77351   TIMER_CTRL11_TMR11CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
77352   TIMER_CTRL11_TMR11CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
77353   TIMER_CTRL11_TMR11CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
77354   TIMER_CTRL11_TMR11CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
77355   TIMER_CTRL11_TMR11CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
77356 } TIMER_CTRL11_TMR11CLK_Enum;
77357 
77358 /* ==============================================  TIMER CTRL11 TMR11FN [4..7]  ============================================== */
77359 typedef enum {                                  /*!< TIMER_CTRL11_TMR11FN                                                      */
77360   TIMER_CTRL11_TMR11FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
77361                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
77362                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
77363   TIMER_CTRL11_TMR11FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
77364                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
77365                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
77366                                                      for TMR_LMT iterations.                                                   */
77367   TIMER_CTRL11_TMR11FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
77368                                                      clock pulse. CMP1 dictates the low phase of the output
77369                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
77370   TIMER_CTRL11_TMR11FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
77371                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
77372                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
77373                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
77374                                                      Both OUT0 and OUT1 can be inverted individually applications
77375                                                      with POL0/POL1 = 0x1.                                                     */
77376   TIMER_CTRL11_TMR11FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
77377                                                      pattern repeats after reaching LMT.                                       */
77378 } TIMER_CTRL11_TMR11FN_Enum;
77379 
77380 /* =============================================  TIMER CTRL11 TMR11POL1 [3..3]  ============================================= */
77381 typedef enum {                                  /*!< TIMER_CTRL11_TMR11POL1                                                    */
77382   TIMER_CTRL11_TMR11POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR11OUT1 pin is the same as the
77383                                                      timer output.                                                             */
77384   TIMER_CTRL11_TMR11POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR11OUT1 pin is the inverse
77385                                                      of the timer output.                                                      */
77386 } TIMER_CTRL11_TMR11POL1_Enum;
77387 
77388 /* =============================================  TIMER CTRL11 TMR11POL0 [2..2]  ============================================= */
77389 typedef enum {                                  /*!< TIMER_CTRL11_TMR11POL0                                                    */
77390   TIMER_CTRL11_TMR11POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR11OUT0 pin is the same as the
77391                                                      timer output.                                                             */
77392   TIMER_CTRL11_TMR11POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR11OUT0 pin is the inverse
77393                                                      of the timer output.                                                      */
77394 } TIMER_CTRL11_TMR11POL0_Enum;
77395 
77396 /* =============================================  TIMER CTRL11 TMR11CLR [1..1]  ============================================== */
77397 typedef enum {                                  /*!< TIMER_CTRL11_TMR11CLR                                                     */
77398   TIMER_CTRL11_TMR11CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
77399                                                      cleared to its reset state # (0 for count up counter, CMP0
77400                                                      for down counter)                                                         */
77401   TIMER_CTRL11_TMR11CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
77402 } TIMER_CTRL11_TMR11CLR_Enum;
77403 
77404 /* ==============================================  TIMER CTRL11 TMR11EN [0..0]  ============================================== */
77405 typedef enum {                                  /*!< TIMER_CTRL11_TMR11EN                                                      */
77406   TIMER_CTRL11_TMR11EN_DIS             = 0,     /*!< DIS : Counter/Timer 11 Disable.                                           */
77407   TIMER_CTRL11_TMR11EN_EN              = 1,     /*!< EN : Counter/Timer 11 Enable.                                             */
77408 } TIMER_CTRL11_TMR11EN_Enum;
77409 
77410 /* ========================================================  TIMER11  ======================================================== */
77411 /* =======================================================  TMR11CMP0  ======================================================= */
77412 /* =======================================================  TMR11CMP1  ======================================================= */
77413 /* ========================================================  MODE11  ========================================================= */
77414 /* ===========================================  TIMER MODE11 TMR11TRIGSEL [8..15]  =========================================== */
77415 typedef enum {                                  /*!< TIMER_MODE11_TMR11TRIGSEL                                                 */
77416   TIMER_MODE11_TMR11TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
77417   TIMER_MODE11_TMR11TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
77418   TIMER_MODE11_TMR11TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
77419   TIMER_MODE11_TMR11TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
77420   TIMER_MODE11_TMR11TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
77421   TIMER_MODE11_TMR11TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
77422   TIMER_MODE11_TMR11TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
77423   TIMER_MODE11_TMR11TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
77424   TIMER_MODE11_TMR11TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
77425   TIMER_MODE11_TMR11TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
77426   TIMER_MODE11_TMR11TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
77427   TIMER_MODE11_TMR11TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
77428   TIMER_MODE11_TMR11TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
77429   TIMER_MODE11_TMR11TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
77430   TIMER_MODE11_TMR11TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
77431   TIMER_MODE11_TMR11TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
77432   TIMER_MODE11_TMR11TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
77433   TIMER_MODE11_TMR11TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
77434   TIMER_MODE11_TMR11TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
77435   TIMER_MODE11_TMR11TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
77436   TIMER_MODE11_TMR11TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
77437   TIMER_MODE11_TMR11TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
77438   TIMER_MODE11_TMR11TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
77439   TIMER_MODE11_TMR11TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
77440   TIMER_MODE11_TMR11TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
77441   TIMER_MODE11_TMR11TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
77442   TIMER_MODE11_TMR11TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
77443   TIMER_MODE11_TMR11TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
77444   TIMER_MODE11_TMR11TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
77445   TIMER_MODE11_TMR11TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
77446   TIMER_MODE11_TMR11TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
77447   TIMER_MODE11_TMR11TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
77448   TIMER_MODE11_TMR11TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
77449   TIMER_MODE11_TMR11TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
77450 } TIMER_MODE11_TMR11TRIGSEL_Enum;
77451 
77452 /* ======================================================  TMR11LMTVAL  ====================================================== */
77453 /* ========================================================  CTRL12  ========================================================= */
77454 /* ===========================================  TIMER CTRL12 TMR12TMODE [16..17]  ============================================ */
77455 typedef enum {                                  /*!< TIMER_CTRL12_TMR12TMODE                                                   */
77456   TIMER_CTRL12_TMR12TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
77457   TIMER_CTRL12_TMR12TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
77458   TIMER_CTRL12_TMR12TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
77459   TIMER_CTRL12_TMR12TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
77460 } TIMER_CTRL12_TMR12TMODE_Enum;
77461 
77462 /* =============================================  TIMER CTRL12 TMR12CLK [8..15]  ============================================= */
77463 typedef enum {                                  /*!< TIMER_CTRL12_TMR12CLK                                                     */
77464   TIMER_CTRL12_TMR12CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
77465   TIMER_CTRL12_TMR12CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
77466   TIMER_CTRL12_TMR12CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
77467   TIMER_CTRL12_TMR12CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
77468   TIMER_CTRL12_TMR12CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
77469   TIMER_CTRL12_TMR12CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
77470   TIMER_CTRL12_TMR12CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
77471   TIMER_CTRL12_TMR12CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
77472   TIMER_CTRL12_TMR12CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
77473   TIMER_CTRL12_TMR12CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
77474   TIMER_CTRL12_TMR12CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
77475   TIMER_CTRL12_TMR12CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
77476   TIMER_CTRL12_TMR12CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
77477   TIMER_CTRL12_TMR12CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
77478   TIMER_CTRL12_TMR12CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
77479   TIMER_CTRL12_TMR12CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
77480   TIMER_CTRL12_TMR12CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
77481   TIMER_CTRL12_TMR12CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
77482   TIMER_CTRL12_TMR12CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
77483   TIMER_CTRL12_TMR12CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
77484   TIMER_CTRL12_TMR12CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
77485   TIMER_CTRL12_TMR12CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
77486   TIMER_CTRL12_TMR12CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
77487   TIMER_CTRL12_TMR12CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
77488   TIMER_CTRL12_TMR12CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
77489   TIMER_CTRL12_TMR12CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
77490   TIMER_CTRL12_TMR12CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
77491   TIMER_CTRL12_TMR12CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
77492   TIMER_CTRL12_TMR12CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
77493   TIMER_CTRL12_TMR12CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
77494   TIMER_CTRL12_TMR12CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
77495   TIMER_CTRL12_TMR12CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
77496   TIMER_CTRL12_TMR12CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
77497   TIMER_CTRL12_TMR12CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
77498   TIMER_CTRL12_TMR12CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
77499   TIMER_CTRL12_TMR12CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
77500   TIMER_CTRL12_TMR12CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
77501   TIMER_CTRL12_TMR12CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
77502   TIMER_CTRL12_TMR12CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
77503   TIMER_CTRL12_TMR12CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
77504   TIMER_CTRL12_TMR12CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
77505   TIMER_CTRL12_TMR12CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
77506   TIMER_CTRL12_TMR12CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
77507   TIMER_CTRL12_TMR12CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
77508   TIMER_CTRL12_TMR12CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
77509   TIMER_CTRL12_TMR12CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
77510   TIMER_CTRL12_TMR12CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
77511   TIMER_CTRL12_TMR12CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
77512   TIMER_CTRL12_TMR12CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
77513   TIMER_CTRL12_TMR12CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
77514   TIMER_CTRL12_TMR12CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
77515   TIMER_CTRL12_TMR12CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
77516   TIMER_CTRL12_TMR12CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
77517   TIMER_CTRL12_TMR12CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
77518   TIMER_CTRL12_TMR12CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
77519   TIMER_CTRL12_TMR12CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
77520   TIMER_CTRL12_TMR12CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
77521   TIMER_CTRL12_TMR12CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
77522 } TIMER_CTRL12_TMR12CLK_Enum;
77523 
77524 /* ==============================================  TIMER CTRL12 TMR12FN [4..7]  ============================================== */
77525 typedef enum {                                  /*!< TIMER_CTRL12_TMR12FN                                                      */
77526   TIMER_CTRL12_TMR12FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
77527                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
77528                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
77529   TIMER_CTRL12_TMR12FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
77530                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
77531                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
77532                                                      for TMR_LMT iterations.                                                   */
77533   TIMER_CTRL12_TMR12FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
77534                                                      clock pulse. CMP1 dictates the low phase of the output
77535                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
77536   TIMER_CTRL12_TMR12FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
77537                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
77538                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
77539                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
77540                                                      Both OUT0 and OUT1 can be inverted individually applications
77541                                                      with POL0/POL1 = 0x1.                                                     */
77542   TIMER_CTRL12_TMR12FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
77543                                                      pattern repeats after reaching LMT.                                       */
77544 } TIMER_CTRL12_TMR12FN_Enum;
77545 
77546 /* =============================================  TIMER CTRL12 TMR12POL1 [3..3]  ============================================= */
77547 typedef enum {                                  /*!< TIMER_CTRL12_TMR12POL1                                                    */
77548   TIMER_CTRL12_TMR12POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR12OUT1 pin is the same as the
77549                                                      timer output.                                                             */
77550   TIMER_CTRL12_TMR12POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR12OUT1 pin is the inverse
77551                                                      of the timer output.                                                      */
77552 } TIMER_CTRL12_TMR12POL1_Enum;
77553 
77554 /* =============================================  TIMER CTRL12 TMR12POL0 [2..2]  ============================================= */
77555 typedef enum {                                  /*!< TIMER_CTRL12_TMR12POL0                                                    */
77556   TIMER_CTRL12_TMR12POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR12OUT0 pin is the same as the
77557                                                      timer output.                                                             */
77558   TIMER_CTRL12_TMR12POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR12OUT0 pin is the inverse
77559                                                      of the timer output.                                                      */
77560 } TIMER_CTRL12_TMR12POL0_Enum;
77561 
77562 /* =============================================  TIMER CTRL12 TMR12CLR [1..1]  ============================================== */
77563 typedef enum {                                  /*!< TIMER_CTRL12_TMR12CLR                                                     */
77564   TIMER_CTRL12_TMR12CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
77565                                                      cleared to its reset state # (0 for count up counter, CMP0
77566                                                      for down counter)                                                         */
77567   TIMER_CTRL12_TMR12CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
77568 } TIMER_CTRL12_TMR12CLR_Enum;
77569 
77570 /* ==============================================  TIMER CTRL12 TMR12EN [0..0]  ============================================== */
77571 typedef enum {                                  /*!< TIMER_CTRL12_TMR12EN                                                      */
77572   TIMER_CTRL12_TMR12EN_DIS             = 0,     /*!< DIS : Counter/Timer 12 Disable.                                           */
77573   TIMER_CTRL12_TMR12EN_EN              = 1,     /*!< EN : Counter/Timer 12 Enable.                                             */
77574 } TIMER_CTRL12_TMR12EN_Enum;
77575 
77576 /* ========================================================  TIMER12  ======================================================== */
77577 /* =======================================================  TMR12CMP0  ======================================================= */
77578 /* =======================================================  TMR12CMP1  ======================================================= */
77579 /* ========================================================  MODE12  ========================================================= */
77580 /* ===========================================  TIMER MODE12 TMR12TRIGSEL [8..15]  =========================================== */
77581 typedef enum {                                  /*!< TIMER_MODE12_TMR12TRIGSEL                                                 */
77582   TIMER_MODE12_TMR12TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
77583   TIMER_MODE12_TMR12TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
77584   TIMER_MODE12_TMR12TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
77585   TIMER_MODE12_TMR12TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
77586   TIMER_MODE12_TMR12TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
77587   TIMER_MODE12_TMR12TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
77588   TIMER_MODE12_TMR12TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
77589   TIMER_MODE12_TMR12TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
77590   TIMER_MODE12_TMR12TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
77591   TIMER_MODE12_TMR12TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
77592   TIMER_MODE12_TMR12TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
77593   TIMER_MODE12_TMR12TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
77594   TIMER_MODE12_TMR12TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
77595   TIMER_MODE12_TMR12TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
77596   TIMER_MODE12_TMR12TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
77597   TIMER_MODE12_TMR12TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
77598   TIMER_MODE12_TMR12TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
77599   TIMER_MODE12_TMR12TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
77600   TIMER_MODE12_TMR12TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
77601   TIMER_MODE12_TMR12TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
77602   TIMER_MODE12_TMR12TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
77603   TIMER_MODE12_TMR12TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
77604   TIMER_MODE12_TMR12TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
77605   TIMER_MODE12_TMR12TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
77606   TIMER_MODE12_TMR12TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
77607   TIMER_MODE12_TMR12TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
77608   TIMER_MODE12_TMR12TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
77609   TIMER_MODE12_TMR12TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
77610   TIMER_MODE12_TMR12TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
77611   TIMER_MODE12_TMR12TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
77612   TIMER_MODE12_TMR12TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
77613   TIMER_MODE12_TMR12TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
77614   TIMER_MODE12_TMR12TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
77615   TIMER_MODE12_TMR12TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
77616 } TIMER_MODE12_TMR12TRIGSEL_Enum;
77617 
77618 /* ======================================================  TMR12LMTVAL  ====================================================== */
77619 /* ========================================================  CTRL13  ========================================================= */
77620 /* ===========================================  TIMER CTRL13 TMR13TMODE [16..17]  ============================================ */
77621 typedef enum {                                  /*!< TIMER_CTRL13_TMR13TMODE                                                   */
77622   TIMER_CTRL13_TMR13TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
77623   TIMER_CTRL13_TMR13TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
77624   TIMER_CTRL13_TMR13TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
77625   TIMER_CTRL13_TMR13TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
77626 } TIMER_CTRL13_TMR13TMODE_Enum;
77627 
77628 /* =============================================  TIMER CTRL13 TMR13CLK [8..15]  ============================================= */
77629 typedef enum {                                  /*!< TIMER_CTRL13_TMR13CLK                                                     */
77630   TIMER_CTRL13_TMR13CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
77631   TIMER_CTRL13_TMR13CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
77632   TIMER_CTRL13_TMR13CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
77633   TIMER_CTRL13_TMR13CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
77634   TIMER_CTRL13_TMR13CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
77635   TIMER_CTRL13_TMR13CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
77636   TIMER_CTRL13_TMR13CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
77637   TIMER_CTRL13_TMR13CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
77638   TIMER_CTRL13_TMR13CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
77639   TIMER_CTRL13_TMR13CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
77640   TIMER_CTRL13_TMR13CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
77641   TIMER_CTRL13_TMR13CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
77642   TIMER_CTRL13_TMR13CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
77643   TIMER_CTRL13_TMR13CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
77644   TIMER_CTRL13_TMR13CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
77645   TIMER_CTRL13_TMR13CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
77646   TIMER_CTRL13_TMR13CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
77647   TIMER_CTRL13_TMR13CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
77648   TIMER_CTRL13_TMR13CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
77649   TIMER_CTRL13_TMR13CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
77650   TIMER_CTRL13_TMR13CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
77651   TIMER_CTRL13_TMR13CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
77652   TIMER_CTRL13_TMR13CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
77653   TIMER_CTRL13_TMR13CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
77654   TIMER_CTRL13_TMR13CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
77655   TIMER_CTRL13_TMR13CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
77656   TIMER_CTRL13_TMR13CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
77657   TIMER_CTRL13_TMR13CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
77658   TIMER_CTRL13_TMR13CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
77659   TIMER_CTRL13_TMR13CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
77660   TIMER_CTRL13_TMR13CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
77661   TIMER_CTRL13_TMR13CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
77662   TIMER_CTRL13_TMR13CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
77663   TIMER_CTRL13_TMR13CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
77664   TIMER_CTRL13_TMR13CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
77665   TIMER_CTRL13_TMR13CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
77666   TIMER_CTRL13_TMR13CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
77667   TIMER_CTRL13_TMR13CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
77668   TIMER_CTRL13_TMR13CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
77669   TIMER_CTRL13_TMR13CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
77670   TIMER_CTRL13_TMR13CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
77671   TIMER_CTRL13_TMR13CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
77672   TIMER_CTRL13_TMR13CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
77673   TIMER_CTRL13_TMR13CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
77674   TIMER_CTRL13_TMR13CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
77675   TIMER_CTRL13_TMR13CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
77676   TIMER_CTRL13_TMR13CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
77677   TIMER_CTRL13_TMR13CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
77678   TIMER_CTRL13_TMR13CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
77679   TIMER_CTRL13_TMR13CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
77680   TIMER_CTRL13_TMR13CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
77681   TIMER_CTRL13_TMR13CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
77682   TIMER_CTRL13_TMR13CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
77683   TIMER_CTRL13_TMR13CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
77684   TIMER_CTRL13_TMR13CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
77685   TIMER_CTRL13_TMR13CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
77686   TIMER_CTRL13_TMR13CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
77687   TIMER_CTRL13_TMR13CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
77688 } TIMER_CTRL13_TMR13CLK_Enum;
77689 
77690 /* ==============================================  TIMER CTRL13 TMR13FN [4..7]  ============================================== */
77691 typedef enum {                                  /*!< TIMER_CTRL13_TMR13FN                                                      */
77692   TIMER_CTRL13_TMR13FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
77693                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
77694                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
77695   TIMER_CTRL13_TMR13FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
77696                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
77697                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
77698                                                      for TMR_LMT iterations.                                                   */
77699   TIMER_CTRL13_TMR13FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
77700                                                      clock pulse. CMP1 dictates the low phase of the output
77701                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
77702   TIMER_CTRL13_TMR13FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
77703                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
77704                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
77705                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
77706                                                      Both OUT0 and OUT1 can be inverted individually applications
77707                                                      with POL0/POL1 = 0x1.                                                     */
77708   TIMER_CTRL13_TMR13FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
77709                                                      pattern repeats after reaching LMT.                                       */
77710 } TIMER_CTRL13_TMR13FN_Enum;
77711 
77712 /* =============================================  TIMER CTRL13 TMR13POL1 [3..3]  ============================================= */
77713 typedef enum {                                  /*!< TIMER_CTRL13_TMR13POL1                                                    */
77714   TIMER_CTRL13_TMR13POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR13OUT1 pin is the same as the
77715                                                      timer output.                                                             */
77716   TIMER_CTRL13_TMR13POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR13OUT1 pin is the inverse
77717                                                      of the timer output.                                                      */
77718 } TIMER_CTRL13_TMR13POL1_Enum;
77719 
77720 /* =============================================  TIMER CTRL13 TMR13POL0 [2..2]  ============================================= */
77721 typedef enum {                                  /*!< TIMER_CTRL13_TMR13POL0                                                    */
77722   TIMER_CTRL13_TMR13POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR13OUT0 pin is the same as the
77723                                                      timer output.                                                             */
77724   TIMER_CTRL13_TMR13POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR13OUT0 pin is the inverse
77725                                                      of the timer output.                                                      */
77726 } TIMER_CTRL13_TMR13POL0_Enum;
77727 
77728 /* =============================================  TIMER CTRL13 TMR13CLR [1..1]  ============================================== */
77729 typedef enum {                                  /*!< TIMER_CTRL13_TMR13CLR                                                     */
77730   TIMER_CTRL13_TMR13CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
77731                                                      cleared to its reset state # (0 for count up counter, CMP0
77732                                                      for down counter)                                                         */
77733   TIMER_CTRL13_TMR13CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
77734 } TIMER_CTRL13_TMR13CLR_Enum;
77735 
77736 /* ==============================================  TIMER CTRL13 TMR13EN [0..0]  ============================================== */
77737 typedef enum {                                  /*!< TIMER_CTRL13_TMR13EN                                                      */
77738   TIMER_CTRL13_TMR13EN_DIS             = 0,     /*!< DIS : Counter/Timer 13 Disable.                                           */
77739   TIMER_CTRL13_TMR13EN_EN              = 1,     /*!< EN : Counter/Timer 13 Enable.                                             */
77740 } TIMER_CTRL13_TMR13EN_Enum;
77741 
77742 /* ========================================================  TIMER13  ======================================================== */
77743 /* =======================================================  TMR13CMP0  ======================================================= */
77744 /* =======================================================  TMR13CMP1  ======================================================= */
77745 /* ========================================================  MODE13  ========================================================= */
77746 /* ===========================================  TIMER MODE13 TMR13TRIGSEL [8..15]  =========================================== */
77747 typedef enum {                                  /*!< TIMER_MODE13_TMR13TRIGSEL                                                 */
77748   TIMER_MODE13_TMR13TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
77749   TIMER_MODE13_TMR13TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
77750   TIMER_MODE13_TMR13TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
77751   TIMER_MODE13_TMR13TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
77752   TIMER_MODE13_TMR13TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
77753   TIMER_MODE13_TMR13TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
77754   TIMER_MODE13_TMR13TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
77755   TIMER_MODE13_TMR13TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
77756   TIMER_MODE13_TMR13TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
77757   TIMER_MODE13_TMR13TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
77758   TIMER_MODE13_TMR13TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
77759   TIMER_MODE13_TMR13TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
77760   TIMER_MODE13_TMR13TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
77761   TIMER_MODE13_TMR13TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
77762   TIMER_MODE13_TMR13TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
77763   TIMER_MODE13_TMR13TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
77764   TIMER_MODE13_TMR13TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
77765   TIMER_MODE13_TMR13TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
77766   TIMER_MODE13_TMR13TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
77767   TIMER_MODE13_TMR13TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
77768   TIMER_MODE13_TMR13TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
77769   TIMER_MODE13_TMR13TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
77770   TIMER_MODE13_TMR13TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
77771   TIMER_MODE13_TMR13TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
77772   TIMER_MODE13_TMR13TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
77773   TIMER_MODE13_TMR13TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
77774   TIMER_MODE13_TMR13TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
77775   TIMER_MODE13_TMR13TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
77776   TIMER_MODE13_TMR13TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
77777   TIMER_MODE13_TMR13TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
77778   TIMER_MODE13_TMR13TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
77779   TIMER_MODE13_TMR13TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
77780   TIMER_MODE13_TMR13TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
77781   TIMER_MODE13_TMR13TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
77782 } TIMER_MODE13_TMR13TRIGSEL_Enum;
77783 
77784 /* ======================================================  TMR13LMTVAL  ====================================================== */
77785 /* ========================================================  CTRL14  ========================================================= */
77786 /* ===========================================  TIMER CTRL14 TMR14TMODE [16..17]  ============================================ */
77787 typedef enum {                                  /*!< TIMER_CTRL14_TMR14TMODE                                                   */
77788   TIMER_CTRL14_TMR14TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
77789   TIMER_CTRL14_TMR14TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
77790   TIMER_CTRL14_TMR14TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
77791   TIMER_CTRL14_TMR14TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
77792 } TIMER_CTRL14_TMR14TMODE_Enum;
77793 
77794 /* =============================================  TIMER CTRL14 TMR14CLK [8..15]  ============================================= */
77795 typedef enum {                                  /*!< TIMER_CTRL14_TMR14CLK                                                     */
77796   TIMER_CTRL14_TMR14CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
77797   TIMER_CTRL14_TMR14CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
77798   TIMER_CTRL14_TMR14CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
77799   TIMER_CTRL14_TMR14CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
77800   TIMER_CTRL14_TMR14CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
77801   TIMER_CTRL14_TMR14CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
77802   TIMER_CTRL14_TMR14CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
77803   TIMER_CTRL14_TMR14CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
77804   TIMER_CTRL14_TMR14CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
77805   TIMER_CTRL14_TMR14CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
77806   TIMER_CTRL14_TMR14CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
77807   TIMER_CTRL14_TMR14CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
77808   TIMER_CTRL14_TMR14CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
77809   TIMER_CTRL14_TMR14CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
77810   TIMER_CTRL14_TMR14CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
77811   TIMER_CTRL14_TMR14CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
77812   TIMER_CTRL14_TMR14CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
77813   TIMER_CTRL14_TMR14CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
77814   TIMER_CTRL14_TMR14CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
77815   TIMER_CTRL14_TMR14CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
77816   TIMER_CTRL14_TMR14CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
77817   TIMER_CTRL14_TMR14CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
77818   TIMER_CTRL14_TMR14CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
77819   TIMER_CTRL14_TMR14CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
77820   TIMER_CTRL14_TMR14CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
77821   TIMER_CTRL14_TMR14CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
77822   TIMER_CTRL14_TMR14CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
77823   TIMER_CTRL14_TMR14CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
77824   TIMER_CTRL14_TMR14CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
77825   TIMER_CTRL14_TMR14CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
77826   TIMER_CTRL14_TMR14CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
77827   TIMER_CTRL14_TMR14CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
77828   TIMER_CTRL14_TMR14CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
77829   TIMER_CTRL14_TMR14CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
77830   TIMER_CTRL14_TMR14CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
77831   TIMER_CTRL14_TMR14CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
77832   TIMER_CTRL14_TMR14CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
77833   TIMER_CTRL14_TMR14CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
77834   TIMER_CTRL14_TMR14CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
77835   TIMER_CTRL14_TMR14CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
77836   TIMER_CTRL14_TMR14CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
77837   TIMER_CTRL14_TMR14CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
77838   TIMER_CTRL14_TMR14CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
77839   TIMER_CTRL14_TMR14CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
77840   TIMER_CTRL14_TMR14CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
77841   TIMER_CTRL14_TMR14CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
77842   TIMER_CTRL14_TMR14CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
77843   TIMER_CTRL14_TMR14CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
77844   TIMER_CTRL14_TMR14CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
77845   TIMER_CTRL14_TMR14CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
77846   TIMER_CTRL14_TMR14CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
77847   TIMER_CTRL14_TMR14CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
77848   TIMER_CTRL14_TMR14CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
77849   TIMER_CTRL14_TMR14CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
77850   TIMER_CTRL14_TMR14CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
77851   TIMER_CTRL14_TMR14CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
77852   TIMER_CTRL14_TMR14CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
77853   TIMER_CTRL14_TMR14CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
77854 } TIMER_CTRL14_TMR14CLK_Enum;
77855 
77856 /* ==============================================  TIMER CTRL14 TMR14FN [4..7]  ============================================== */
77857 typedef enum {                                  /*!< TIMER_CTRL14_TMR14FN                                                      */
77858   TIMER_CTRL14_TMR14FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
77859                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
77860                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
77861   TIMER_CTRL14_TMR14FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
77862                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
77863                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
77864                                                      for TMR_LMT iterations.                                                   */
77865   TIMER_CTRL14_TMR14FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
77866                                                      clock pulse. CMP1 dictates the low phase of the output
77867                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
77868   TIMER_CTRL14_TMR14FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
77869                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
77870                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
77871                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
77872                                                      Both OUT0 and OUT1 can be inverted individually applications
77873                                                      with POL0/POL1 = 0x1.                                                     */
77874   TIMER_CTRL14_TMR14FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
77875                                                      pattern repeats after reaching LMT.                                       */
77876 } TIMER_CTRL14_TMR14FN_Enum;
77877 
77878 /* =============================================  TIMER CTRL14 TMR14POL1 [3..3]  ============================================= */
77879 typedef enum {                                  /*!< TIMER_CTRL14_TMR14POL1                                                    */
77880   TIMER_CTRL14_TMR14POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR14OUT1 pin is the same as the
77881                                                      timer output.                                                             */
77882   TIMER_CTRL14_TMR14POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR14OUT1 pin is the inverse
77883                                                      of the timer output.                                                      */
77884 } TIMER_CTRL14_TMR14POL1_Enum;
77885 
77886 /* =============================================  TIMER CTRL14 TMR14POL0 [2..2]  ============================================= */
77887 typedef enum {                                  /*!< TIMER_CTRL14_TMR14POL0                                                    */
77888   TIMER_CTRL14_TMR14POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR14OUT0 pin is the same as the
77889                                                      timer output.                                                             */
77890   TIMER_CTRL14_TMR14POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR14OUT0 pin is the inverse
77891                                                      of the timer output.                                                      */
77892 } TIMER_CTRL14_TMR14POL0_Enum;
77893 
77894 /* =============================================  TIMER CTRL14 TMR14CLR [1..1]  ============================================== */
77895 typedef enum {                                  /*!< TIMER_CTRL14_TMR14CLR                                                     */
77896   TIMER_CTRL14_TMR14CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
77897                                                      cleared to its reset state # (0 for count up counter, CMP0
77898                                                      for down counter)                                                         */
77899   TIMER_CTRL14_TMR14CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
77900 } TIMER_CTRL14_TMR14CLR_Enum;
77901 
77902 /* ==============================================  TIMER CTRL14 TMR14EN [0..0]  ============================================== */
77903 typedef enum {                                  /*!< TIMER_CTRL14_TMR14EN                                                      */
77904   TIMER_CTRL14_TMR14EN_DIS             = 0,     /*!< DIS : Counter/Timer 14 Disable.                                           */
77905   TIMER_CTRL14_TMR14EN_EN              = 1,     /*!< EN : Counter/Timer 14 Enable.                                             */
77906 } TIMER_CTRL14_TMR14EN_Enum;
77907 
77908 /* ========================================================  TIMER14  ======================================================== */
77909 /* =======================================================  TMR14CMP0  ======================================================= */
77910 /* =======================================================  TMR14CMP1  ======================================================= */
77911 /* ========================================================  MODE14  ========================================================= */
77912 /* ===========================================  TIMER MODE14 TMR14TRIGSEL [8..15]  =========================================== */
77913 typedef enum {                                  /*!< TIMER_MODE14_TMR14TRIGSEL                                                 */
77914   TIMER_MODE14_TMR14TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
77915   TIMER_MODE14_TMR14TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
77916   TIMER_MODE14_TMR14TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
77917   TIMER_MODE14_TMR14TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
77918   TIMER_MODE14_TMR14TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
77919   TIMER_MODE14_TMR14TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
77920   TIMER_MODE14_TMR14TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
77921   TIMER_MODE14_TMR14TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
77922   TIMER_MODE14_TMR14TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
77923   TIMER_MODE14_TMR14TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
77924   TIMER_MODE14_TMR14TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
77925   TIMER_MODE14_TMR14TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
77926   TIMER_MODE14_TMR14TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
77927   TIMER_MODE14_TMR14TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
77928   TIMER_MODE14_TMR14TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
77929   TIMER_MODE14_TMR14TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
77930   TIMER_MODE14_TMR14TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
77931   TIMER_MODE14_TMR14TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
77932   TIMER_MODE14_TMR14TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
77933   TIMER_MODE14_TMR14TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
77934   TIMER_MODE14_TMR14TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
77935   TIMER_MODE14_TMR14TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
77936   TIMER_MODE14_TMR14TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
77937   TIMER_MODE14_TMR14TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
77938   TIMER_MODE14_TMR14TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
77939   TIMER_MODE14_TMR14TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
77940   TIMER_MODE14_TMR14TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
77941   TIMER_MODE14_TMR14TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
77942   TIMER_MODE14_TMR14TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
77943   TIMER_MODE14_TMR14TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
77944   TIMER_MODE14_TMR14TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
77945   TIMER_MODE14_TMR14TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
77946   TIMER_MODE14_TMR14TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
77947   TIMER_MODE14_TMR14TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
77948 } TIMER_MODE14_TMR14TRIGSEL_Enum;
77949 
77950 /* ======================================================  TMR14LMTVAL  ====================================================== */
77951 /* ========================================================  CTRL15  ========================================================= */
77952 /* ===========================================  TIMER CTRL15 TMR15TMODE [16..17]  ============================================ */
77953 typedef enum {                                  /*!< TIMER_CTRL15_TMR15TMODE                                                   */
77954   TIMER_CTRL15_TMR15TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
77955   TIMER_CTRL15_TMR15TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
77956   TIMER_CTRL15_TMR15TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
77957   TIMER_CTRL15_TMR15TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
77958 } TIMER_CTRL15_TMR15TMODE_Enum;
77959 
77960 /* =============================================  TIMER CTRL15 TMR15CLK [8..15]  ============================================= */
77961 typedef enum {                                  /*!< TIMER_CTRL15_TMR15CLK                                                     */
77962   TIMER_CTRL15_TMR15CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
77963   TIMER_CTRL15_TMR15CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
77964   TIMER_CTRL15_TMR15CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
77965   TIMER_CTRL15_TMR15CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
77966   TIMER_CTRL15_TMR15CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
77967   TIMER_CTRL15_TMR15CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
77968   TIMER_CTRL15_TMR15CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
77969   TIMER_CTRL15_TMR15CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
77970   TIMER_CTRL15_TMR15CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
77971   TIMER_CTRL15_TMR15CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
77972   TIMER_CTRL15_TMR15CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
77973   TIMER_CTRL15_TMR15CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
77974   TIMER_CTRL15_TMR15CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
77975   TIMER_CTRL15_TMR15CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
77976   TIMER_CTRL15_TMR15CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
77977   TIMER_CTRL15_TMR15CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
77978   TIMER_CTRL15_TMR15CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
77979   TIMER_CTRL15_TMR15CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
77980   TIMER_CTRL15_TMR15CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
77981   TIMER_CTRL15_TMR15CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
77982   TIMER_CTRL15_TMR15CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
77983   TIMER_CTRL15_TMR15CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
77984   TIMER_CTRL15_TMR15CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
77985   TIMER_CTRL15_TMR15CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
77986   TIMER_CTRL15_TMR15CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
77987   TIMER_CTRL15_TMR15CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
77988   TIMER_CTRL15_TMR15CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
77989   TIMER_CTRL15_TMR15CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
77990   TIMER_CTRL15_TMR15CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
77991   TIMER_CTRL15_TMR15CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
77992   TIMER_CTRL15_TMR15CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
77993   TIMER_CTRL15_TMR15CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
77994   TIMER_CTRL15_TMR15CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
77995   TIMER_CTRL15_TMR15CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
77996   TIMER_CTRL15_TMR15CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
77997   TIMER_CTRL15_TMR15CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
77998   TIMER_CTRL15_TMR15CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
77999   TIMER_CTRL15_TMR15CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
78000   TIMER_CTRL15_TMR15CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
78001   TIMER_CTRL15_TMR15CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
78002   TIMER_CTRL15_TMR15CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
78003   TIMER_CTRL15_TMR15CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
78004   TIMER_CTRL15_TMR15CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
78005   TIMER_CTRL15_TMR15CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
78006   TIMER_CTRL15_TMR15CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
78007   TIMER_CTRL15_TMR15CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
78008   TIMER_CTRL15_TMR15CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
78009   TIMER_CTRL15_TMR15CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
78010   TIMER_CTRL15_TMR15CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
78011   TIMER_CTRL15_TMR15CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
78012   TIMER_CTRL15_TMR15CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
78013   TIMER_CTRL15_TMR15CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
78014   TIMER_CTRL15_TMR15CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
78015   TIMER_CTRL15_TMR15CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
78016   TIMER_CTRL15_TMR15CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
78017   TIMER_CTRL15_TMR15CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
78018   TIMER_CTRL15_TMR15CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
78019   TIMER_CTRL15_TMR15CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
78020 } TIMER_CTRL15_TMR15CLK_Enum;
78021 
78022 /* ==============================================  TIMER CTRL15 TMR15FN [4..7]  ============================================== */
78023 typedef enum {                                  /*!< TIMER_CTRL15_TMR15FN                                                      */
78024   TIMER_CTRL15_TMR15FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
78025                                                      value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
78026                                                      to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
78027   TIMER_CTRL15_TMR15FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
78028                                                      CMP. OUT[0]/OUT[1] is pulsed for one source clock period
78029                                                      when TIMER matches CMP0/CMP1 respectively. Timer repeats
78030                                                      for TMR_LMT iterations.                                                   */
78031   TIMER_CTRL15_TMR15FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
78032                                                      clock pulse. CMP1 dictates the low phase of the output
78033                                                      and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
78034   TIMER_CTRL15_TMR15FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
78035                                                      LMT field specifies length of pattern. When LMT GT 32 OUT0
78036                                                      and OUT1 is the same 64-bit pattern consisting of concatenated
78037                                                      CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
78038                                                      Both OUT0 and OUT1 can be inverted individually applications
78039                                                      with POL0/POL1 = 0x1.                                                     */
78040   TIMER_CTRL15_TMR15FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
78041                                                      pattern repeats after reaching LMT.                                       */
78042 } TIMER_CTRL15_TMR15FN_Enum;
78043 
78044 /* =============================================  TIMER CTRL15 TMR15POL1 [3..3]  ============================================= */
78045 typedef enum {                                  /*!< TIMER_CTRL15_TMR15POL1                                                    */
78046   TIMER_CTRL15_TMR15POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR15OUT1 pin is the same as the
78047                                                      timer output.                                                             */
78048   TIMER_CTRL15_TMR15POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR15OUT1 pin is the inverse
78049                                                      of the timer output.                                                      */
78050 } TIMER_CTRL15_TMR15POL1_Enum;
78051 
78052 /* =============================================  TIMER CTRL15 TMR15POL0 [2..2]  ============================================= */
78053 typedef enum {                                  /*!< TIMER_CTRL15_TMR15POL0                                                    */
78054   TIMER_CTRL15_TMR15POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR15OUT0 pin is the same as the
78055                                                      timer output.                                                             */
78056   TIMER_CTRL15_TMR15POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR15OUT0 pin is the inverse
78057                                                      of the timer output.                                                      */
78058 } TIMER_CTRL15_TMR15POL0_Enum;
78059 
78060 /* =============================================  TIMER CTRL15 TMR15CLR [1..1]  ============================================== */
78061 typedef enum {                                  /*!< TIMER_CTRL15_TMR15CLR                                                     */
78062   TIMER_CTRL15_TMR15CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
78063                                                      cleared to its reset state # (0 for count up counter, CMP0
78064                                                      for down counter)                                                         */
78065   TIMER_CTRL15_TMR15CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
78066 } TIMER_CTRL15_TMR15CLR_Enum;
78067 
78068 /* ==============================================  TIMER CTRL15 TMR15EN [0..0]  ============================================== */
78069 typedef enum {                                  /*!< TIMER_CTRL15_TMR15EN                                                      */
78070   TIMER_CTRL15_TMR15EN_DIS             = 0,     /*!< DIS : Counter/Timer 15 Disable.                                           */
78071   TIMER_CTRL15_TMR15EN_EN              = 1,     /*!< EN : Counter/Timer 15 Enable.                                             */
78072 } TIMER_CTRL15_TMR15EN_Enum;
78073 
78074 /* ========================================================  TIMER15  ======================================================== */
78075 /* =======================================================  TMR15CMP0  ======================================================= */
78076 /* =======================================================  TMR15CMP1  ======================================================= */
78077 /* ========================================================  MODE15  ========================================================= */
78078 /* ===========================================  TIMER MODE15 TMR15TRIGSEL [8..15]  =========================================== */
78079 typedef enum {                                  /*!< TIMER_MODE15_TMR15TRIGSEL                                                 */
78080   TIMER_MODE15_TMR15TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
78081   TIMER_MODE15_TMR15TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
78082   TIMER_MODE15_TMR15TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
78083   TIMER_MODE15_TMR15TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
78084   TIMER_MODE15_TMR15TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
78085   TIMER_MODE15_TMR15TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
78086   TIMER_MODE15_TMR15TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
78087   TIMER_MODE15_TMR15TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
78088   TIMER_MODE15_TMR15TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
78089   TIMER_MODE15_TMR15TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
78090   TIMER_MODE15_TMR15TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
78091   TIMER_MODE15_TMR15TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
78092   TIMER_MODE15_TMR15TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
78093   TIMER_MODE15_TMR15TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
78094   TIMER_MODE15_TMR15TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
78095   TIMER_MODE15_TMR15TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
78096   TIMER_MODE15_TMR15TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
78097   TIMER_MODE15_TMR15TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
78098   TIMER_MODE15_TMR15TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
78099   TIMER_MODE15_TMR15TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
78100   TIMER_MODE15_TMR15TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
78101   TIMER_MODE15_TMR15TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
78102   TIMER_MODE15_TMR15TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
78103   TIMER_MODE15_TMR15TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
78104   TIMER_MODE15_TMR15TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
78105   TIMER_MODE15_TMR15TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
78106   TIMER_MODE15_TMR15TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
78107   TIMER_MODE15_TMR15TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
78108   TIMER_MODE15_TMR15TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
78109   TIMER_MODE15_TMR15TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
78110   TIMER_MODE15_TMR15TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
78111   TIMER_MODE15_TMR15TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
78112   TIMER_MODE15_TMR15TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
78113   TIMER_MODE15_TMR15TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
78114 } TIMER_MODE15_TMR15TRIGSEL_Enum;
78115 
78116 /* ======================================================  TMR15LMTVAL  ====================================================== */
78117 /* ======================================================  TIMERSPARES  ====================================================== */
78118 
78119 
78120 /* =========================================================================================================================== */
78121 /* ================                                           UART0                                           ================ */
78122 /* =========================================================================================================================== */
78123 
78124 /* ==========================================================  DR  =========================================================== */
78125 /* ===============================================  UART0 DR OEDATA [11..11]  ================================================ */
78126 typedef enum {                                  /*!< UART0_DR_OEDATA                                                           */
78127   UART0_DR_OEDATA_NOERR                = 0,     /*!< NOERR : No error on UART OEDATA, overrun error indicator.                 */
78128   UART0_DR_OEDATA_ERR                  = 1,     /*!< ERR : Error on UART OEDATA, overrun error indicator.                      */
78129 } UART0_DR_OEDATA_Enum;
78130 
78131 /* ===============================================  UART0 DR BEDATA [10..10]  ================================================ */
78132 typedef enum {                                  /*!< UART0_DR_BEDATA                                                           */
78133   UART0_DR_BEDATA_NOERR                = 0,     /*!< NOERR : No error on UART BEDATA, break error indicator.                   */
78134   UART0_DR_BEDATA_ERR                  = 1,     /*!< ERR : Error on UART BEDATA, break error indicator.                        */
78135 } UART0_DR_BEDATA_Enum;
78136 
78137 /* ================================================  UART0 DR PEDATA [9..9]  ================================================= */
78138 typedef enum {                                  /*!< UART0_DR_PEDATA                                                           */
78139   UART0_DR_PEDATA_NOERR                = 0,     /*!< NOERR : No error on UART PEDATA, parity error indicator.                  */
78140   UART0_DR_PEDATA_ERR                  = 1,     /*!< ERR : Error on UART PEDATA, parity error indicator.                       */
78141 } UART0_DR_PEDATA_Enum;
78142 
78143 /* ================================================  UART0 DR FEDATA [8..8]  ================================================= */
78144 typedef enum {                                  /*!< UART0_DR_FEDATA                                                           */
78145   UART0_DR_FEDATA_NOERR                = 0,     /*!< NOERR : No error on UART FEDATA, framing error indicator.                 */
78146   UART0_DR_FEDATA_ERR                  = 1,     /*!< ERR : Error on UART FEDATA, framing error indicator.                      */
78147 } UART0_DR_FEDATA_Enum;
78148 
78149 /* ==========================================================  RSR  ========================================================== */
78150 /* ================================================  UART0 RSR OESTAT [3..3]  ================================================ */
78151 typedef enum {                                  /*!< UART0_RSR_OESTAT                                                          */
78152   UART0_RSR_OESTAT_NOERR               = 0,     /*!< NOERR : No error on UART OESTAT, overrun error indicator.                 */
78153   UART0_RSR_OESTAT_ERR                 = 1,     /*!< ERR : Error on UART OESTAT, overrun error indicator.                      */
78154 } UART0_RSR_OESTAT_Enum;
78155 
78156 /* ================================================  UART0 RSR BESTAT [2..2]  ================================================ */
78157 typedef enum {                                  /*!< UART0_RSR_BESTAT                                                          */
78158   UART0_RSR_BESTAT_NOERR               = 0,     /*!< NOERR : No error on UART BESTAT, break error indicator.                   */
78159   UART0_RSR_BESTAT_ERR                 = 1,     /*!< ERR : Error on UART BESTAT, break error indicator.                        */
78160 } UART0_RSR_BESTAT_Enum;
78161 
78162 /* ================================================  UART0 RSR PESTAT [1..1]  ================================================ */
78163 typedef enum {                                  /*!< UART0_RSR_PESTAT                                                          */
78164   UART0_RSR_PESTAT_NOERR               = 0,     /*!< NOERR : No error on UART PESTAT, parity error indicator.                  */
78165   UART0_RSR_PESTAT_ERR                 = 1,     /*!< ERR : Error on UART PESTAT, parity error indicator.                       */
78166 } UART0_RSR_PESTAT_Enum;
78167 
78168 /* ================================================  UART0 RSR FESTAT [0..0]  ================================================ */
78169 typedef enum {                                  /*!< UART0_RSR_FESTAT                                                          */
78170   UART0_RSR_FESTAT_NOERR               = 0,     /*!< NOERR : No error on UART FESTAT, framing error indicator.                 */
78171   UART0_RSR_FESTAT_ERR                 = 1,     /*!< ERR : Error on UART FESTAT, framing error indicator.                      */
78172 } UART0_RSR_FESTAT_Enum;
78173 
78174 /* ==========================================================  FR  =========================================================== */
78175 /* =================================================  UART0 FR TXFE [7..7]  ================================================== */
78176 typedef enum {                                  /*!< UART0_FR_TXFE                                                             */
78177   UART0_FR_TXFE_XMTFIFO_EMPTY          = 1,     /*!< XMTFIFO_EMPTY : Transmit fifo is empty.                                   */
78178   UART0_FR_TXFE_XMTFIFO_NOTEMPTY       = 0,     /*!< XMTFIFO_NOTEMPTY : Transmit fifo is not empty.                            */
78179 } UART0_FR_TXFE_Enum;
78180 
78181 /* =================================================  UART0 FR RXFF [6..6]  ================================================== */
78182 typedef enum {                                  /*!< UART0_FR_RXFF                                                             */
78183   UART0_FR_RXFF_RCVFIFO_FULL           = 1,     /*!< RCVFIFO_FULL : Receive fifo is full.                                      */
78184   UART0_FR_RXFF_RCVFIFO_NOTFULL        = 0,     /*!< RCVFIFO_NOTFULL : Receive fifo is not full.                               */
78185 } UART0_FR_RXFF_Enum;
78186 
78187 /* =================================================  UART0 FR TXFF [5..5]  ================================================== */
78188 typedef enum {                                  /*!< UART0_FR_TXFF                                                             */
78189   UART0_FR_TXFF_XMTFIFO_FULL           = 1,     /*!< XMTFIFO_FULL : Transmit fifo is full.                                     */
78190   UART0_FR_TXFF_XMTFIFO_NOTFULL        = 0,     /*!< XMTFIFO_NOTFULL : Transmit fifo is not full.                              */
78191 } UART0_FR_TXFF_Enum;
78192 
78193 /* =================================================  UART0 FR RXFE [4..4]  ================================================== */
78194 typedef enum {                                  /*!< UART0_FR_RXFE                                                             */
78195   UART0_FR_RXFE_RCVFIFO_EMPTY          = 1,     /*!< RCVFIFO_EMPTY : Receive fifo is empty.                                    */
78196   UART0_FR_RXFE_RCVFIFO_NOTEMPTY       = 0,     /*!< RCVFIFO_NOTEMPTY : Receive fifo is not empty.                             */
78197 } UART0_FR_RXFE_Enum;
78198 
78199 /* =================================================  UART0 FR BUSY [3..3]  ================================================== */
78200 typedef enum {                                  /*!< UART0_FR_BUSY                                                             */
78201   UART0_FR_BUSY_BUSY                   = 1,     /*!< BUSY : UART busy indicator.                                               */
78202   UART0_FR_BUSY_NOTBUSY                = 0,     /*!< NOTBUSY : UART not busy.                                                  */
78203 } UART0_FR_BUSY_Enum;
78204 
78205 /* ==================================================  UART0 FR DCD [2..2]  ================================================== */
78206 typedef enum {                                  /*!< UART0_FR_DCD                                                              */
78207   UART0_FR_DCD_DETECTED                = 1,     /*!< DETECTED : Data carrier detect detected.                                  */
78208   UART0_FR_DCD_DEFAULT                 = 0,     /*!< DEFAULT : Data carrier detect not detected/default.                       */
78209 } UART0_FR_DCD_Enum;
78210 
78211 /* ==================================================  UART0 FR DSR [1..1]  ================================================== */
78212 typedef enum {                                  /*!< UART0_FR_DSR                                                              */
78213   UART0_FR_DSR_READY                   = 1,     /*!< READY : Data set ready.                                                   */
78214   UART0_FR_DSR_NOTREADY                = 0,     /*!< NOTREADY : Data set not ready/default.                                    */
78215 } UART0_FR_DSR_Enum;
78216 
78217 /* ==================================================  UART0 FR CTS [0..0]  ================================================== */
78218 typedef enum {                                  /*!< UART0_FR_CTS                                                              */
78219   UART0_FR_CTS_CLEARTOSEND             = 1,     /*!< CLEARTOSEND : Clear to send is indicated.                                 */
78220   UART0_FR_CTS_DEFAULT                 = 0,     /*!< DEFAULT : Clear to send default value.                                    */
78221 } UART0_FR_CTS_Enum;
78222 
78223 /* =========================================================  ILPR  ========================================================== */
78224 /* =========================================================  IBRD  ========================================================== */
78225 /* =========================================================  FBRD  ========================================================== */
78226 /* =========================================================  LCRH  ========================================================== */
78227 /* ==========================================================  CR  =========================================================== */
78228 /* ================================================  UART0 CR CLKSEL [4..6]  ================================================= */
78229 typedef enum {                                  /*!< UART0_CR_CLKSEL                                                           */
78230   UART0_CR_CLKSEL_NOCLK                = 0,     /*!< NOCLK : No UART clock. This is the low power default.                     */
78231   UART0_CR_CLKSEL_24MHZ                = 1,     /*!< 24MHZ : 24 MHz clock.                                                     */
78232   UART0_CR_CLKSEL_12MHZ                = 2,     /*!< 12MHZ : 12 MHz clock.                                                     */
78233   UART0_CR_CLKSEL_6MHZ                 = 3,     /*!< 6MHZ : 6 MHz clock.                                                       */
78234   UART0_CR_CLKSEL_3MHZ                 = 4,     /*!< 3MHZ : 3 MHz clock.                                                       */
78235   UART0_CR_CLKSEL_48MHZ                = 5,     /*!< 48MHZ : Reserved.                                                         */
78236 } UART0_CR_CLKSEL_Enum;
78237 
78238 /* =========================================================  IFLS  ========================================================== */
78239 /* ==========================================================  IER  ========================================================== */
78240 /* ==========================================================  IES  ========================================================== */
78241 /* ==========================================================  MIS  ========================================================== */
78242 /* ==========================================================  IEC  ========================================================== */
78243 
78244 
78245 /* =========================================================================================================================== */
78246 /* ================                                          USBPHY                                           ================ */
78247 /* =========================================================================================================================== */
78248 
78249 /* =========================================================  REG00  ========================================================= */
78250 /* =========================================================  REG04  ========================================================= */
78251 /* =========================================================  REG08  ========================================================= */
78252 /* =========================================================  REG0C  ========================================================= */
78253 /* =========================================================  REG10  ========================================================= */
78254 /* =========================================================  REG14  ========================================================= */
78255 /* =========================================================  REG18  ========================================================= */
78256 /* =========================================================  REG1C  ========================================================= */
78257 /* =========================================================  REG20  ========================================================= */
78258 /* =========================================================  REG24  ========================================================= */
78259 /* =========================================================  REG28  ========================================================= */
78260 /* =========================================================  REG2C  ========================================================= */
78261 /* =========================================================  REG30  ========================================================= */
78262 /* =========================================================  REG34  ========================================================= */
78263 /* =========================================================  REG38  ========================================================= */
78264 /* =========================================================  REG3C  ========================================================= */
78265 /* =========================================================  REG40  ========================================================= */
78266 /* =========================================================  REG44  ========================================================= */
78267 /* =========================================================  REG48  ========================================================= */
78268 /* =========================================================  REG4C  ========================================================= */
78269 /* =========================================================  REG50  ========================================================= */
78270 /* =========================================================  REG54  ========================================================= */
78271 /* =========================================================  REG58  ========================================================= */
78272 /* =========================================================  REG5C  ========================================================= */
78273 /* =========================================================  REG60  ========================================================= */
78274 /* =========================================================  REG64  ========================================================= */
78275 /* =========================================================  REG68  ========================================================= */
78276 /* =========================================================  REG6C  ========================================================= */
78277 /* =========================================================  REG70  ========================================================= */
78278 /* =========================================================  REG74  ========================================================= */
78279 /* =========================================================  REG78  ========================================================= */
78280 /* =========================================================  REG7C  ========================================================= */
78281 /* =========================================================  REG80  ========================================================= */
78282 /* =========================================================  REG84  ========================================================= */
78283 
78284 
78285 /* =========================================================================================================================== */
78286 /* ================                                            USB                                            ================ */
78287 /* =========================================================================================================================== */
78288 
78289 /* =========================================================  CFG0  ========================================================== */
78290 /* ============================================  USB CFG0 EP5InIntStat [21..21]  ============================================= */
78291 typedef enum {                                  /*!< USB_CFG0_EP5InIntStat                                                     */
78292   USB_CFG0_EP5InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78293   USB_CFG0_EP5InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
78294 } USB_CFG0_EP5InIntStat_Enum;
78295 
78296 /* ============================================  USB CFG0 EP4InIntStat [20..20]  ============================================= */
78297 typedef enum {                                  /*!< USB_CFG0_EP4InIntStat                                                     */
78298   USB_CFG0_EP4InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78299   USB_CFG0_EP4InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
78300 } USB_CFG0_EP4InIntStat_Enum;
78301 
78302 /* ============================================  USB CFG0 EP3InIntStat [19..19]  ============================================= */
78303 typedef enum {                                  /*!< USB_CFG0_EP3InIntStat                                                     */
78304   USB_CFG0_EP3InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78305   USB_CFG0_EP3InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
78306 } USB_CFG0_EP3InIntStat_Enum;
78307 
78308 /* ============================================  USB CFG0 EP2InIntStat [18..18]  ============================================= */
78309 typedef enum {                                  /*!< USB_CFG0_EP2InIntStat                                                     */
78310   USB_CFG0_EP2InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78311   USB_CFG0_EP2InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
78312 } USB_CFG0_EP2InIntStat_Enum;
78313 
78314 /* ============================================  USB CFG0 EP1InIntStat [17..17]  ============================================= */
78315 typedef enum {                                  /*!< USB_CFG0_EP1InIntStat                                                     */
78316   USB_CFG0_EP1InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78317   USB_CFG0_EP1InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
78318 } USB_CFG0_EP1InIntStat_Enum;
78319 
78320 /* ============================================  USB CFG0 EP0InIntStat [16..16]  ============================================= */
78321 typedef enum {                                  /*!< USB_CFG0_EP0InIntStat                                                     */
78322   USB_CFG0_EP0InIntStat_INACTIVE       = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78323   USB_CFG0_EP0InIntStat_ACTIVE         = 1,     /*!< ACTIVE : Interrupt active.                                                */
78324 } USB_CFG0_EP0InIntStat_Enum;
78325 
78326 /* ==============================================  USB CFG0 ISOUpdate [15..15]  ============================================== */
78327 typedef enum {                                  /*!< USB_CFG0_ISOUpdate                                                        */
78328   USB_CFG0_ISOUpdate_DONT_WAIT         = 0,     /*!< DONT_WAIT : Clear for USB Controller not to wait for SOF token
78329                                                      before sending packet.                                                    */
78330   USB_CFG0_ISOUpdate_WAIT              = 1,     /*!< WAIT : Set to have USB Controller wait for SOF token before
78331                                                      sending packet.                                                           */
78332 } USB_CFG0_ISOUpdate_Enum;
78333 
78334 /* =============================================  USB CFG0 AMSPECIFIC [14..14]  ============================================== */
78335 typedef enum {                                  /*!< USB_CFG0_AMSPECIFIC                                                       */
78336   USB_CFG0_AMSPECIFIC_NOT_CONNECTED    = 0,     /*!< NOT_CONNECTED : Clear to disable/disconnect USB lines.                    */
78337   USB_CFG0_AMSPECIFIC_CONNECTED        = 1,     /*!< CONNECTED : Set to enable USB lines.                                      */
78338 } USB_CFG0_AMSPECIFIC_Enum;
78339 
78340 /* ===============================================  USB CFG0 HSEnab [13..13]  ================================================ */
78341 typedef enum {                                  /*!< USB_CFG0_HSEnab                                                           */
78342   USB_CFG0_HSEnab_DIS_HS               = 0,     /*!< DIS_HS : Clear to disable High-speed mode (Full-speed mode only).         */
78343   USB_CFG0_HSEnab_EN_HS                = 1,     /*!< EN_HS : Set to enable High-speed mode.                                    */
78344 } USB_CFG0_HSEnab_Enum;
78345 
78346 /* ===============================================  USB CFG0 HSMode [12..12]  ================================================ */
78347 typedef enum {                                  /*!< USB_CFG0_HSMode                                                           */
78348   USB_CFG0_HSMode_FS_MODE              = 0,     /*!< FS_MODE : Indicates USB Controller is in Full-speed mode only.            */
78349   USB_CFG0_HSMode_HS_MODE              = 1,     /*!< HS_MODE : Indicates USB Controller is in High-speed mode.                 */
78350 } USB_CFG0_HSMode_Enum;
78351 
78352 /* ================================================  USB CFG0 Reset [11..11]  ================================================ */
78353 typedef enum {                                  /*!< USB_CFG0_Reset                                                            */
78354   USB_CFG0_Reset_NEG_RESET_COMPLETE    = 0,     /*!< NEG_RESET_COMPLETE : Indicates that HS negotiation has completed
78355                                                      successfully, or 2.1 ms of reset signaling has elapsed.                   */
78356   USB_CFG0_Reset_RESETTING             = 1,     /*!< RESETTING : Indicates that Reset signaling is detected and remains
78357                                                      high until the bus reverts to an idle state.                              */
78358 } USB_CFG0_Reset_Enum;
78359 
78360 /* ===============================================  USB CFG0 Resume [10..10]  ================================================ */
78361 typedef enum {                                  /*!< USB_CFG0_Resume                                                           */
78362   USB_CFG0_Resume_END_RESUME           = 0,     /*!< END_RESUME : Cleared automatically 10-15 ms after being manually
78363                                                      set.                                                                      */
78364   USB_CFG0_Resume_RESUME               = 1,     /*!< RESUME : Set to force USB Controller to generate Resume signal
78365                                                      on the USB to cause remote wake-up from Suspend mode.                     */
78366 } USB_CFG0_Resume_Enum;
78367 
78368 /* ================================================  USB CFG0 Suspen [9..9]  ================================================= */
78369 typedef enum {                                  /*!< USB_CFG0_Suspen                                                           */
78370   USB_CFG0_Suspen_RESUMED              = 0,     /*!< RESUMED : Indicates that Suspend Mode exited.                             */
78371   USB_CFG0_Suspen_SUSPENDED            = 1,     /*!< SUSPENDED : Indicates that Suspend Mode entered.                          */
78372 } USB_CFG0_Suspen_Enum;
78373 
78374 /* =================================================  USB CFG0 Enabl [8..8]  ================================================= */
78375 typedef enum {                                  /*!< USB_CFG0_Enabl                                                            */
78376   USB_CFG0_Enabl_DISABLE_SUSPENDM      = 0,     /*!< DISABLE_SUSPENDM : Clear to disable SUSPENDM signal - UTM does
78377                                                      not go into its low-power mode.                                           */
78378   USB_CFG0_Enabl_ENABLE_SUSPENDM       = 1,     /*!< ENABLE_SUSPENDM : Set to enable the SUSPENDM signal to put the
78379                                                      UTM (and any other HW which uses the SUSPENDM signal) into
78380                                                      Suspend mode.                                                             */
78381 } USB_CFG0_Enabl_Enum;
78382 
78383 /* ================================================  USB CFG0 Update [7..7]  ================================================= */
78384 typedef enum {                                  /*!< USB_CFG0_Update                                                           */
78385   USB_CFG0_Update_NEW_ADDR_SET         = 0,     /*!< NEW_ADDR_SET : Indicates that the new address has taken effect.           */
78386   USB_CFG0_Update_NEW_ADDR_WRITTEN     = 1,     /*!< NEW_ADDR_WRITTEN : Indicates that a new function address has
78387                                                      been written to the FuncAddr field.                                       */
78388 } USB_CFG0_Update_Enum;
78389 
78390 /* =========================================================  CFG1  ========================================================== */
78391 /* =============================================  USB CFG1 EP5InIntEn [21..21]  ============================================== */
78392 typedef enum {                                  /*!< USB_CFG1_EP5InIntEn                                                       */
78393   USB_CFG1_EP5InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
78394   USB_CFG1_EP5InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
78395 } USB_CFG1_EP5InIntEn_Enum;
78396 
78397 /* =============================================  USB CFG1 EP4InIntEn [20..20]  ============================================== */
78398 typedef enum {                                  /*!< USB_CFG1_EP4InIntEn                                                       */
78399   USB_CFG1_EP4InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
78400   USB_CFG1_EP4InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
78401 } USB_CFG1_EP4InIntEn_Enum;
78402 
78403 /* =============================================  USB CFG1 EP3InIntEn [19..19]  ============================================== */
78404 typedef enum {                                  /*!< USB_CFG1_EP3InIntEn                                                       */
78405   USB_CFG1_EP3InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
78406   USB_CFG1_EP3InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
78407 } USB_CFG1_EP3InIntEn_Enum;
78408 
78409 /* =============================================  USB CFG1 EP2InIntEn [18..18]  ============================================== */
78410 typedef enum {                                  /*!< USB_CFG1_EP2InIntEn                                                       */
78411   USB_CFG1_EP2InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
78412   USB_CFG1_EP2InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
78413 } USB_CFG1_EP2InIntEn_Enum;
78414 
78415 /* =============================================  USB CFG1 EP1InIntEn [17..17]  ============================================== */
78416 typedef enum {                                  /*!< USB_CFG1_EP1InIntEn                                                       */
78417   USB_CFG1_EP1InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
78418   USB_CFG1_EP1InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
78419 } USB_CFG1_EP1InIntEn_Enum;
78420 
78421 /* =============================================  USB CFG1 EP0InIntEn [16..16]  ============================================== */
78422 typedef enum {                                  /*!< USB_CFG1_EP0InIntEn                                                       */
78423   USB_CFG1_EP0InIntEn_DIS              = 0,     /*!< DIS : IN Endpoint interrupt disabled.                                     */
78424   USB_CFG1_EP0InIntEn_EN               = 1,     /*!< EN : IN Endpoint interrupt enabled.                                       */
78425 } USB_CFG1_EP0InIntEn_Enum;
78426 
78427 /* =============================================  USB CFG1 EP5OutIntStat [5..5]  ============================================= */
78428 typedef enum {                                  /*!< USB_CFG1_EP5OutIntStat                                                    */
78429   USB_CFG1_EP5OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78430   USB_CFG1_EP5OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
78431 } USB_CFG1_EP5OutIntStat_Enum;
78432 
78433 /* =============================================  USB CFG1 EP4OutIntStat [4..4]  ============================================= */
78434 typedef enum {                                  /*!< USB_CFG1_EP4OutIntStat                                                    */
78435   USB_CFG1_EP4OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78436   USB_CFG1_EP4OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
78437 } USB_CFG1_EP4OutIntStat_Enum;
78438 
78439 /* =============================================  USB CFG1 EP3OutIntStat [3..3]  ============================================= */
78440 typedef enum {                                  /*!< USB_CFG1_EP3OutIntStat                                                    */
78441   USB_CFG1_EP3OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78442   USB_CFG1_EP3OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
78443 } USB_CFG1_EP3OutIntStat_Enum;
78444 
78445 /* =============================================  USB CFG1 EP2OutIntStat [2..2]  ============================================= */
78446 typedef enum {                                  /*!< USB_CFG1_EP2OutIntStat                                                    */
78447   USB_CFG1_EP2OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78448   USB_CFG1_EP2OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
78449 } USB_CFG1_EP2OutIntStat_Enum;
78450 
78451 /* =============================================  USB CFG1 EP1OutIntStat [1..1]  ============================================= */
78452 typedef enum {                                  /*!< USB_CFG1_EP1OutIntStat                                                    */
78453   USB_CFG1_EP1OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78454   USB_CFG1_EP1OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
78455 } USB_CFG1_EP1OutIntStat_Enum;
78456 
78457 /* =============================================  USB CFG1 EP0OutIntStat [0..0]  ============================================= */
78458 typedef enum {                                  /*!< USB_CFG1_EP0OutIntStat                                                    */
78459   USB_CFG1_EP0OutIntStat_INACTIVE      = 0,     /*!< INACTIVE : Interrupt inactive.                                            */
78460   USB_CFG1_EP0OutIntStat_ACTIVE        = 1,     /*!< ACTIVE : Interrupt active.                                                */
78461 } USB_CFG1_EP0OutIntStat_Enum;
78462 
78463 /* =========================================================  CFG2  ========================================================== */
78464 /* ================================================  USB CFG2 SOFE [27..27]  ================================================= */
78465 typedef enum {                                  /*!< USB_CFG2_SOFE                                                             */
78466   USB_CFG2_SOFE_DIS                    = 0,     /*!< DIS : SOF interrupt disable.                                              */
78467   USB_CFG2_SOFE_EN                     = 1,     /*!< EN : SOF interrupt enable.                                                */
78468 } USB_CFG2_SOFE_Enum;
78469 
78470 /* ===============================================  USB CFG2 ResetE [26..26]  ================================================ */
78471 typedef enum {                                  /*!< USB_CFG2_ResetE                                                           */
78472   USB_CFG2_ResetE_DIS                  = 0,     /*!< DIS : Reset detect interrupt disable.                                     */
78473   USB_CFG2_ResetE_EN                   = 1,     /*!< EN : Reset detect interrupt enable.                                       */
78474 } USB_CFG2_ResetE_Enum;
78475 
78476 /* ===============================================  USB CFG2 ResumeE [25..25]  =============================================== */
78477 typedef enum {                                  /*!< USB_CFG2_ResumeE                                                          */
78478   USB_CFG2_ResumeE_DIS                 = 0,     /*!< DIS : Resume interrupt disable.                                           */
78479   USB_CFG2_ResumeE_EN                  = 1,     /*!< EN : Resume interrupt enable.                                             */
78480 } USB_CFG2_ResumeE_Enum;
78481 
78482 /* ==============================================  USB CFG2 SuspendE [24..24]  =============================================== */
78483 typedef enum {                                  /*!< USB_CFG2_SuspendE                                                         */
78484   USB_CFG2_SuspendE_DIS                = 0,     /*!< DIS : Suspend interrupt disable.                                          */
78485   USB_CFG2_SuspendE_EN                 = 1,     /*!< EN : Suspend interrupt enable.                                            */
78486 } USB_CFG2_SuspendE_Enum;
78487 
78488 /* =================================================  USB CFG2 SOF [19..19]  ================================================= */
78489 typedef enum {                                  /*!< USB_CFG2_SOF                                                              */
78490   USB_CFG2_SOF_SOF_INACTIVE            = 0,     /*!< SOF_INACTIVE : SOF interrupt inactive.                                    */
78491   USB_CFG2_SOF_SOF_ACTIVE              = 1,     /*!< SOF_ACTIVE : SOF interrupt active.                                        */
78492 } USB_CFG2_SOF_Enum;
78493 
78494 /* ================================================  USB CFG2 Reset [18..18]  ================================================ */
78495 typedef enum {                                  /*!< USB_CFG2_Reset                                                            */
78496   USB_CFG2_Reset_RESET_INACTIVE        = 0,     /*!< RESET_INACTIVE : Reset Detect interrupt inactive.                         */
78497   USB_CFG2_Reset_RESET_ACTIVE          = 1,     /*!< RESET_ACTIVE : Reset Detect interrupt active.                             */
78498 } USB_CFG2_Reset_Enum;
78499 
78500 /* ===============================================  USB CFG2 Resume [17..17]  ================================================ */
78501 typedef enum {                                  /*!< USB_CFG2_Resume                                                           */
78502   USB_CFG2_Resume_RESUME_INACTIVE      = 0,     /*!< RESUME_INACTIVE : Resume interrupt inactive.                              */
78503   USB_CFG2_Resume_RESUME_ACTIVE        = 1,     /*!< RESUME_ACTIVE : Resume interrupt active.                                  */
78504 } USB_CFG2_Resume_Enum;
78505 
78506 /* ===============================================  USB CFG2 Suspend [16..16]  =============================================== */
78507 typedef enum {                                  /*!< USB_CFG2_Suspend                                                          */
78508   USB_CFG2_Suspend_SUSPEND_INACTIVE    = 0,     /*!< SUSPEND_INACTIVE : Suspend interrupt inactive.                            */
78509   USB_CFG2_Suspend_SUSPEND_ACTIVE      = 1,     /*!< SUSPEND_ACTIVE : Suspend interrupt active.                                */
78510 } USB_CFG2_Suspend_Enum;
78511 
78512 /* ==============================================  USB CFG2 EP5OutIntEn [5..5]  ============================================== */
78513 typedef enum {                                  /*!< USB_CFG2_EP5OutIntEn                                                      */
78514   USB_CFG2_EP5OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
78515   USB_CFG2_EP5OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
78516 } USB_CFG2_EP5OutIntEn_Enum;
78517 
78518 /* ==============================================  USB CFG2 EP4OutIntEn [4..4]  ============================================== */
78519 typedef enum {                                  /*!< USB_CFG2_EP4OutIntEn                                                      */
78520   USB_CFG2_EP4OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
78521   USB_CFG2_EP4OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
78522 } USB_CFG2_EP4OutIntEn_Enum;
78523 
78524 /* ==============================================  USB CFG2 EP3OutIntEn [3..3]  ============================================== */
78525 typedef enum {                                  /*!< USB_CFG2_EP3OutIntEn                                                      */
78526   USB_CFG2_EP3OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
78527   USB_CFG2_EP3OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
78528 } USB_CFG2_EP3OutIntEn_Enum;
78529 
78530 /* ==============================================  USB CFG2 EP2OutIntEn [2..2]  ============================================== */
78531 typedef enum {                                  /*!< USB_CFG2_EP2OutIntEn                                                      */
78532   USB_CFG2_EP2OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
78533   USB_CFG2_EP2OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
78534 } USB_CFG2_EP2OutIntEn_Enum;
78535 
78536 /* ==============================================  USB CFG2 EP1OutIntEn [1..1]  ============================================== */
78537 typedef enum {                                  /*!< USB_CFG2_EP1OutIntEn                                                      */
78538   USB_CFG2_EP1OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
78539   USB_CFG2_EP1OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
78540 } USB_CFG2_EP1OutIntEn_Enum;
78541 
78542 /* ==============================================  USB CFG2 EP0OutIntEn [0..0]  ============================================== */
78543 typedef enum {                                  /*!< USB_CFG2_EP0OutIntEn                                                      */
78544   USB_CFG2_EP0OutIntEn_DIS             = 0,     /*!< DIS : Out Endpoint interrupt disabled.                                    */
78545   USB_CFG2_EP0OutIntEn_EN              = 1,     /*!< EN : Out Endpoint interrupt enabled.                                      */
78546 } USB_CFG2_EP0OutIntEn_Enum;
78547 
78548 /* =========================================================  CFG3  ========================================================== */
78549 /* ===============================================  USB CFG3 ForceFS [29..29]  =============================================== */
78550 typedef enum {                                  /*!< USB_CFG3_ForceFS                                                          */
78551   USB_CFG3_ForceFS_FS_NOT_FORCED       = 0,     /*!< FS_NOT_FORCED : Do not force FS mode upon USB reset.                      */
78552   USB_CFG3_ForceFS_FS_FORCED           = 1,     /*!< FS_FORCED : Force FS mode upon USB reset.                                 */
78553 } USB_CFG3_ForceFS_Enum;
78554 
78555 /* ===============================================  USB CFG3 ForceHS [28..28]  =============================================== */
78556 typedef enum {                                  /*!< USB_CFG3_ForceHS                                                          */
78557   USB_CFG3_ForceHS_HS_NOT_FORCED       = 0,     /*!< HS_NOT_FORCED : Do not force HS mode upon USB reset.                      */
78558   USB_CFG3_ForceHS_HS_FORCED           = 1,     /*!< HS_FORCED : Force HS mode upon USB reset.                                 */
78559 } USB_CFG3_ForceHS_Enum;
78560 
78561 /* =============================================  USB CFG3 TestPacket [27..27]  ============================================== */
78562 typedef enum {                                  /*!< USB_CFG3_TestPacket                                                       */
78563   USB_CFG3_TestPacket_STOP_TPTM        = 0,     /*!< STOP_TPTM : Terminates Test Packet Test Mode.                             */
78564   USB_CFG3_TestPacket_START_TPTM       = 1,     /*!< START_TPTM : Initiates Test Packet Test Mode.                             */
78565 } USB_CFG3_TestPacket_Enum;
78566 
78567 /* ================================================  USB CFG3 TestK [26..26]  ================================================ */
78568 typedef enum {                                  /*!< USB_CFG3_TestK                                                            */
78569   USB_CFG3_TestK_STOP_TESTK            = 0,     /*!< STOP_TESTK : Terminates Test_K Test Mode.                                 */
78570   USB_CFG3_TestK_START_TESTK           = 1,     /*!< START_TESTK : Initiates Test_K Test Mode.                                 */
78571 } USB_CFG3_TestK_Enum;
78572 
78573 /* ================================================  USB CFG3 TestJ [25..25]  ================================================ */
78574 typedef enum {                                  /*!< USB_CFG3_TestJ                                                            */
78575   USB_CFG3_TestJ_STOP_TESTJ            = 0,     /*!< STOP_TESTJ : Terminates Test_J Test Mode.                                 */
78576   USB_CFG3_TestJ_START_TESTJ           = 1,     /*!< START_TESTJ : Initiates Test_J Test Mode.                                 */
78577 } USB_CFG3_TestJ_Enum;
78578 
78579 /* =============================================  USB CFG3 TestSE0NAK [24..24]  ============================================== */
78580 typedef enum {                                  /*!< USB_CFG3_TestSE0NAK                                                       */
78581   USB_CFG3_TestSE0NAK_STOP_TESTSE0NAK  = 0,     /*!< STOP_TESTSE0NAK : Terminates Test_SE0_NAK Test Mode.                      */
78582   USB_CFG3_TestSE0NAK_START_TESTSE0NAK = 1,     /*!< START_TESTSE0NAK : Initiates Test_SE0_NAK Test Mode.                      */
78583 } USB_CFG3_TestSE0NAK_Enum;
78584 
78585 /* ==============================================  USB CFG3 ENDPOINT [16..19]  =============================================== */
78586 typedef enum {                                  /*!< USB_CFG3_ENDPOINT                                                         */
78587   USB_CFG3_ENDPOINT_ENDPOINT0          = 0,     /*!< ENDPOINT0 : Endpoint 0 selected.                                          */
78588   USB_CFG3_ENDPOINT_ENDPOINT1          = 1,     /*!< ENDPOINT1 : Endpoint 1 selected.                                          */
78589   USB_CFG3_ENDPOINT_ENDPOINT2          = 2,     /*!< ENDPOINT2 : Endpoint 2 selected.                                          */
78590   USB_CFG3_ENDPOINT_ENDPOINT3          = 3,     /*!< ENDPOINT3 : Endpoint 3 selected.                                          */
78591   USB_CFG3_ENDPOINT_ENDPOINT4          = 4,     /*!< ENDPOINT4 : Endpoint 4 selected.                                          */
78592   USB_CFG3_ENDPOINT_ENDPOINT5          = 5,     /*!< ENDPOINT5 : Endpoint 5 selected.                                          */
78593 } USB_CFG3_ENDPOINT_Enum;
78594 
78595 /* =========================================================  IDX0  ========================================================== */
78596 /* ===============================================  USB IDX0 AutoSet [31..31]  =============================================== */
78597 typedef enum {                                  /*!< USB_IDX0_AutoSet                                                          */
78598   USB_IDX0_AutoSet_NO_AUTOSET          = 0,     /*!< NO_AUTOSET : InPktRdy field is not automatically set when MAXPAYLOAD
78599                                                      data size is loaded into the IN FIFO.                                     */
78600   USB_IDX0_AutoSet_AUTOSET             = 1,     /*!< AUTOSET : Applicable InPktRdy field is automatically set when
78601                                                      MAXPAYLOAD data size is loaded into the IN FIFO. If a packet
78602                                                      of less than the maximum packet size is loaded, InPktRdy
78603                                                      will have to be set manually. Note: Should not be set for
78604                                                      high-bandwidth Isochronous endpoints.                                     */
78605 } USB_IDX0_AutoSet_Enum;
78606 
78607 /* =================================================  USB IDX0 ISO [30..30]  ================================================= */
78608 typedef enum {                                  /*!< USB_IDX0_ISO                                                              */
78609   USB_IDX0_ISO_BULK_INT                = 0,     /*!< BULK_INT : Clear to enable the IN endpoint for Bulk/Interrupt
78610                                                      transfers.                                                                */
78611   USB_IDX0_ISO_ISO                     = 1,     /*!< ISO : Set to enable the IN endpoint for Isochronous transfers.            */
78612 } USB_IDX0_ISO_Enum;
78613 
78614 /* ================================================  USB IDX0 Mode [29..29]  ================================================= */
78615 typedef enum {                                  /*!< USB_IDX0_Mode                                                             */
78616   USB_IDX0_Mode_OUT                    = 0,     /*!< OUT : Clear to enable the OUT direction for endpoint.                     */
78617   USB_IDX0_Mode_IN                     = 1,     /*!< IN : Set to enable the IN direction for endpoint.                         */
78618 } USB_IDX0_Mode_Enum;
78619 
78620 /* =============================================  USB IDX0 FrcDataTog [27..27]  ============================================== */
78621 typedef enum {                                  /*!< USB_IDX0_FrcDataTog                                                       */
78622   USB_IDX0_FrcDataTog_NO_FORCE_TOGGLE  = 0,     /*!< NO_FORCE_TOGGLE : Keep cleared to not force data toggle.                  */
78623   USB_IDX0_FrcDataTog_FORCE_TOGGLE     = 1,     /*!< FORCE_TOGGLE : Set to force the endpoint's IN data toggle to
78624                                                      switch after each data packet is sent.                                    */
78625 } USB_IDX0_FrcDataTog_Enum;
78626 
78627 /* =============================================  USB IDX0 DPktBufDis [25..25]  ============================================== */
78628 typedef enum {                                  /*!< USB_IDX0_DPktBufDis                                                       */
78629   USB_IDX0_DPktBufDis_EN_DPB           = 0,     /*!< EN_DPB : Clear to allow Double Packet Buffering.                          */
78630   USB_IDX0_DPktBufDis_DIS_DPB          = 1,     /*!< DIS_DPB : Set to disable Double Packet Buffering regardless
78631                                                      of the End Point FIFO size and MAXPAYLOAD size relationship.              */
78632 } USB_IDX0_DPktBufDis_Enum;
78633 
78634 /* =======================================  USB IDX0 IncompTxServiceSetupEnd [23..23]  ======================================= */
78635 typedef enum {                                  /*!< USB_IDX0_IncompTxServiceSetupEnd                                          */
78636   USB_IDX0_IncompTxServiceSetupEnd_NO_PACKET_SPLIT = 0,/*!< NO_PACKET_SPLIT : Packet has NOT been split into multiple packets
78637                                                      for transmission.                                                         */
78638   USB_IDX0_IncompTxServiceSetupEnd_PACKET_SPLIT = 1,/*!< PACKET_SPLIT : A large packet has been split into 2 or 3 packets
78639                                                      for transmission but insufficient IN tokens have been received
78640                                                      to send all the parts.If CFG3_ENDPOINT = 0x0, this bit
78641                                                      serves as the ServiceSetupEnd field.                                      */
78642 } USB_IDX0_IncompTxServiceSetupEnd_Enum;
78643 
78644 /* =========================================================  IDX1  ========================================================== */
78645 /* ==============================================  USB IDX1 AutoClear [31..31]  ============================================== */
78646 typedef enum {                                  /*!< USB_IDX1_AutoClear                                                        */
78647   USB_IDX1_AutoClear_NO_AUTOCLR        = 0,     /*!< NO_AUTOCLR : OutPktRdy field will not be automatically cleared
78648                                                      when a packet of MAXPAYLOAD data size is unloaded from
78649                                                      the OUT FIFO.                                                             */
78650   USB_IDX1_AutoClear_AUTOCLR           = 1,     /*!< AUTOCLR : OutPktRdy field will be automatically cleared when
78651                                                      a packet of MAXPAYLOAD data size is unloaded from the OUT
78652                                                      FIFO. When packets of less than the maximum packet size
78653                                                      are unloaded, OutPktRdy must be cleared manually. Note:
78654                                                      Should not be set for high bandwidth Isochronous endpoints.               */
78655 } USB_IDX1_AutoClear_Enum;
78656 
78657 /* =================================================  USB IDX1 ISO [30..30]  ================================================= */
78658 typedef enum {                                  /*!< USB_IDX1_ISO                                                              */
78659   USB_IDX1_ISO_BULK_INT                = 0,     /*!< BULK_INT : Clear to enable the OUT endpoint for Bulk/Interrupt
78660                                                      transfers.                                                                */
78661   USB_IDX1_ISO_ISO                     = 1,     /*!< ISO : Set to enable the OUT endpoint for Isochronous transfers.           */
78662 } USB_IDX1_ISO_Enum;
78663 
78664 /* =============================================  USB IDX1 DPktBufDis [25..25]  ============================================== */
78665 typedef enum {                                  /*!< USB_IDX1_DPktBufDis                                                       */
78666   USB_IDX1_DPktBufDis_EN_DPB           = 0,     /*!< EN_DPB : Clear to allow Double Packet Buffering.                          */
78667   USB_IDX1_DPktBufDis_DIS_DPB          = 1,     /*!< DIS_DPB : Set to disable Double Packet Buffering regardless
78668                                                      of the End Point FIFO size and MAXPAYLOAD size relationship.              */
78669 } USB_IDX1_DPktBufDis_Enum;
78670 
78671 /* =========================================================  IDX2  ========================================================== */
78672 /* ========================================================  FIFOADD  ======================================================== */
78673 /* =========================================================  FIFO0  ========================================================= */
78674 /* =========================================================  FIFO1  ========================================================= */
78675 /* =========================================================  FIFO2  ========================================================= */
78676 /* =========================================================  FIFO3  ========================================================= */
78677 /* =========================================================  FIFO4  ========================================================= */
78678 /* =========================================================  FIFO5  ========================================================= */
78679 /* ========================================================  HWVERS  ========================================================= */
78680 /* =========================================================  INFO  ========================================================== */
78681 /* =======================================================  TIMEOUT1  ======================================================== */
78682 /* =======================================================  TIMEOUT2  ======================================================== */
78683 /* ========================================================  CLKCTRL  ======================================================== */
78684 /* ===========================================  USB CLKCTRL PHYREFCLKSEL [24..25]  =========================================== */
78685 typedef enum {                                  /*!< USB_CLKCTRL_PHYREFCLKSEL                                                  */
78686   USB_CLKCTRL_PHYREFCLKSEL_HFRC48      = 0,     /*!< HFRC48 : 48 MHz HFRC-based reference clock for Full-Speed Mode            */
78687   USB_CLKCTRL_PHYREFCLKSEL_HFRC248     = 1,     /*!< HFRC248 : 48 MHz HFRC2-based reference clock for High-Speed
78688                                                      Mode                                                                      */
78689   USB_CLKCTRL_PHYREFCLKSEL_HFRC24      = 2,     /*!< HFRC24 : 24 MHz HFRC-based reference clock for Full-Speed Mode            */
78690 } USB_CLKCTRL_PHYREFCLKSEL_Enum;
78691 
78692 /* =======================================================  SRAMCTRL  ======================================================== */
78693 /* ===============================================  USB SRAMCTRL RAWLM [7..8]  =============================================== */
78694 typedef enum {                                  /*!< USB_SRAMCTRL_RAWLM                                                        */
78695   USB_SRAMCTRL_RAWLM_INCDLY            = 3,     /*!< INCDLY : Increased margin adjustment, increased delay for enabling
78696                                                      write assist.                                                             */
78697   USB_SRAMCTRL_RAWLM_MBINCDLY          = 2,     /*!< MBINCDLY : Minimum boost level with increased delay for enabling
78698                                                      write assist.                                                             */
78699   USB_SRAMCTRL_RAWLM_IMNB              = 1,     /*!< IMNB : Increased margin adjustment with more negative boost.              */
78700   USB_SRAMCTRL_RAWLM_MMNB              = 0,     /*!< MMNB : Minimum margin adjustment with lowest negative boost
78701                                                      level.                                                                    */
78702 } USB_SRAMCTRL_RAWLM_Enum;
78703 
78704 /* ===================================================  UTMISTICKYSTATUS  ==================================================== */
78705 /* =======================================  USB UTMISTICKYSTATUS obsportstciky [0..1]  ======================================= */
78706 typedef enum {                                  /*!< USB_UTMISTICKYSTATUS_obsportstciky                                        */
78707   USB_UTMISTICKYSTATUS_obsportstciky_OBS3 = 3,  /*!< OBS3 : bit 1:HS BIST results, bit 0:FS BIST results                       */
78708   USB_UTMISTICKYSTATUS_obsportstciky_OBS2 = 2,  /*!< OBS2 : bit 1: ODT calibration state, bit 0: Current calibration
78709                                                      state                                                                     */
78710   USB_UTMISTICKYSTATUS_obsportstciky_OBS1 = 1,  /*!< OBS1 : bit 1: Rx squelch signal, bit 0: Rx datap                          */
78711   USB_UTMISTICKYSTATUS_obsportstciky_OBS0 = 0,  /*!< OBS0 : bit 1: PLL lock signal, bit 0: Host Disconnect                     */
78712 } USB_UTMISTICKYSTATUS_obsportstciky_Enum;
78713 
78714 /* ======================================================  OBSCLRSTAT  ======================================================= */
78715 /* =====================================================  DPDMPULLDOWN  ====================================================== */
78716 /* ======================================================  BCDETSTATUS  ====================================================== */
78717 /* ======================================================  BCDETCRTL1  ======================================================= */
78718 /* ===========================================  USB BCDETCRTL1 USBDCOMPREF [8..9]  =========================================== */
78719 typedef enum {                                  /*!< USB_BCDETCRTL1_USBDCOMPREF                                                */
78720   USB_BCDETCRTL1_USBDCOMPREF_1P25V     = 3,     /*!< 1P25V : 1.25V                                                             */
78721   USB_BCDETCRTL1_USBDCOMPREF_2P35      = 2,     /*!< 2P35 : 2.35V                                                              */
78722   USB_BCDETCRTL1_USBDCOMPREF_3P10V     = 1,     /*!< 3P10V : 3.10V                                                             */
78723   USB_BCDETCRTL1_USBDCOMPREF_1P65      = 0,     /*!< 1P65 : 1.65V (VCCIO/2)                                                    */
78724 } USB_BCDETCRTL1_USBDCOMPREF_Enum;
78725 
78726 /* ======================================================  BCDETCRTL2  ======================================================= */
78727 
78728 
78729 /* =========================================================================================================================== */
78730 /* ================                                           VCOMP                                           ================ */
78731 /* =========================================================================================================================== */
78732 
78733 /* ==========================================================  CFG  ========================================================== */
78734 /* ===============================================  VCOMP CFG LVLSEL [16..19]  =============================================== */
78735 typedef enum {                                  /*!< VCOMP_CFG_LVLSEL                                                          */
78736   VCOMP_CFG_LVLSEL_0P58V               = 0,     /*!< 0P58V : Set Reference input to 0.58 Volts.                                */
78737   VCOMP_CFG_LVLSEL_0P77V               = 1,     /*!< 0P77V : Set Reference input to 0.77 Volts.                                */
78738   VCOMP_CFG_LVLSEL_0P97V               = 2,     /*!< 0P97V : Set Reference input to 0.97 Volts.                                */
78739   VCOMP_CFG_LVLSEL_1P16V               = 3,     /*!< 1P16V : Set Reference input to 1.16 Volts.                                */
78740   VCOMP_CFG_LVLSEL_1P35V               = 4,     /*!< 1P35V : Set Reference input to 1.35 Volts.                                */
78741   VCOMP_CFG_LVLSEL_1P55V               = 5,     /*!< 1P55V : Set Reference input to 1.55 Volts.                                */
78742   VCOMP_CFG_LVLSEL_1P74V               = 6,     /*!< 1P74V : Set Reference input to 1.74 Volts.                                */
78743   VCOMP_CFG_LVLSEL_1P93V               = 7,     /*!< 1P93V : Set Reference input to 1.93 Volts.                                */
78744   VCOMP_CFG_LVLSEL_2P13V               = 8,     /*!< 2P13V : Set Reference input to 2.13 Volts.                                */
78745   VCOMP_CFG_LVLSEL_2P32V               = 9,     /*!< 2P32V : Set Reference input to 2.32 Volts.                                */
78746   VCOMP_CFG_LVLSEL_2P51V               = 10,    /*!< 2P51V : Set Reference input to 2.51 Volts.                                */
78747   VCOMP_CFG_LVLSEL_2P71V               = 11,    /*!< 2P71V : Set Reference input to 2.71 Volts.                                */
78748   VCOMP_CFG_LVLSEL_2P90V               = 12,    /*!< 2P90V : Set Reference input to 2.90 Volts.                                */
78749   VCOMP_CFG_LVLSEL_3P09V               = 13,    /*!< 3P09V : Set Reference input to 3.09 Volts.                                */
78750   VCOMP_CFG_LVLSEL_3P29V               = 14,    /*!< 3P29V : Set Reference input to 3.29 Volts.                                */
78751   VCOMP_CFG_LVLSEL_3P48V               = 15,    /*!< 3P48V : Set Reference input to 3.48 Volts.                                */
78752 } VCOMP_CFG_LVLSEL_Enum;
78753 
78754 /* =================================================  VCOMP CFG NSEL [8..9]  ================================================= */
78755 typedef enum {                                  /*!< VCOMP_CFG_NSEL                                                            */
78756   VCOMP_CFG_NSEL_VREFEXT1              = 0,     /*!< VREFEXT1 : Use external reference 1 for reference input.                  */
78757   VCOMP_CFG_NSEL_VREFEXT2              = 1,     /*!< VREFEXT2 : Use external reference 2 for reference input.                  */
78758   VCOMP_CFG_NSEL_VREFEXT3              = 2,     /*!< VREFEXT3 : Use external reference 3 for reference input.                  */
78759   VCOMP_CFG_NSEL_DAC                   = 3,     /*!< DAC : Use DAC output selected by LVLSEL for reference input.              */
78760 } VCOMP_CFG_NSEL_Enum;
78761 
78762 /* =================================================  VCOMP CFG PSEL [0..1]  ================================================= */
78763 typedef enum {                                  /*!< VCOMP_CFG_PSEL                                                            */
78764   VCOMP_CFG_PSEL_VDDADJ                = 0,     /*!< VDDADJ : Use VDDADJ for the positive input.                               */
78765   VCOMP_CFG_PSEL_VTEMP                 = 1,     /*!< VTEMP : Use the temperature sensor output for the positive input.
78766                                                      Note: If this channel is selected for PSEL, the bandap
78767                                                      circuit required for temperature comparisons will automatically
78768                                                      turn on. The bandgap circuit requires 11us to stabalize.                  */
78769   VCOMP_CFG_PSEL_VEXT1                 = 2,     /*!< VEXT1 : Use external voltage 0 for positive input.                        */
78770   VCOMP_CFG_PSEL_VEXT2                 = 3,     /*!< VEXT2 : Use external voltage 1 for positive input.                        */
78771 } VCOMP_CFG_PSEL_Enum;
78772 
78773 /* =========================================================  STAT  ========================================================== */
78774 /* ===============================================  VCOMP STAT PWDSTAT [1..1]  =============================================== */
78775 typedef enum {                                  /*!< VCOMP_STAT_PWDSTAT                                                        */
78776   VCOMP_STAT_PWDSTAT_POWERED_DOWN      = 1,     /*!< POWERED_DOWN : The voltage comparator is powered down.                    */
78777   VCOMP_STAT_PWDSTAT_POWERED_UP        = 0,     /*!< POWERED_UP : The voltage comparator is powered up.                        */
78778 } VCOMP_STAT_PWDSTAT_Enum;
78779 
78780 /* ===============================================  VCOMP STAT CMPOUT [0..0]  ================================================ */
78781 typedef enum {                                  /*!< VCOMP_STAT_CMPOUT                                                         */
78782   VCOMP_STAT_CMPOUT_VOUT_LOW           = 0,     /*!< VOUT_LOW : The negative input of the comparator is greater than
78783                                                      the positive input.                                                       */
78784   VCOMP_STAT_CMPOUT_VOUT_HIGH          = 1,     /*!< VOUT_HIGH : The positive input of the comparator is greater
78785                                                      than the negative input.                                                  */
78786 } VCOMP_STAT_CMPOUT_Enum;
78787 
78788 /* ========================================================  PWDKEY  ========================================================= */
78789 /* ==============================================  VCOMP PWDKEY PWDKEY [0..31]  ============================================== */
78790 typedef enum {                                  /*!< VCOMP_PWDKEY_PWDKEY                                                       */
78791   VCOMP_PWDKEY_PWDKEY_Key              = 55,    /*!< Key : Key value to unlock the register.                                   */
78792 } VCOMP_PWDKEY_PWDKEY_Enum;
78793 
78794 /* =========================================================  INTEN  ========================================================= */
78795 /* ========================================================  INTSTAT  ======================================================== */
78796 /* ========================================================  INTCLR  ========================================================= */
78797 /* ========================================================  INTSET  ========================================================= */
78798 
78799 
78800 /* =========================================================================================================================== */
78801 /* ================                                            WDT                                            ================ */
78802 /* =========================================================================================================================== */
78803 
78804 /* ==========================================================  CFG  ========================================================== */
78805 /* ================================================  WDT CFG CLKSEL [24..26]  ================================================ */
78806 typedef enum {                                  /*!< WDT_CFG_CLKSEL                                                            */
78807   WDT_CFG_CLKSEL_OFF                   = 0,     /*!< OFF : Low Power Mode. This setting disables the watch dog timer.          */
78808   WDT_CFG_CLKSEL_128HZ                 = 1,     /*!< 128HZ : 128 Hz LFRC clock.                                                */
78809   WDT_CFG_CLKSEL_16HZ                  = 2,     /*!< 16HZ : 16 Hz LFRC clock.                                                  */
78810   WDT_CFG_CLKSEL_1HZ                   = 3,     /*!< 1HZ : 1 Hz LFRC clock.                                                    */
78811   WDT_CFG_CLKSEL_1_16HZ                = 4,     /*!< 1_16HZ : 1/16th Hz LFRC clock.                                            */
78812 } WDT_CFG_CLKSEL_Enum;
78813 
78814 /* =========================================================  RSTRT  ========================================================= */
78815 /* ================================================  WDT RSTRT RSTRT [0..7]  ================================================= */
78816 typedef enum {                                  /*!< WDT_RSTRT_RSTRT                                                           */
78817   WDT_RSTRT_RSTRT_KEYVALUE             = 178,   /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
78818                                                      the WDT. This is a write only register.                                   */
78819   WDT_RSTRT_RSTRT_DEFAULT              = 0,     /*!< DEFAULT : Default/Reset value. This is a write only register.             */
78820 } WDT_RSTRT_RSTRT_Enum;
78821 
78822 /* =========================================================  LOCK  ========================================================== */
78823 /* =================================================  WDT LOCK LOCK [0..7]  ================================================== */
78824 typedef enum {                                  /*!< WDT_LOCK_LOCK                                                             */
78825   WDT_LOCK_LOCK_KEYVALUE               = 58,    /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
78826                                                      the WDT.                                                                  */
78827   WDT_LOCK_LOCK_DEFAULT                = 0,     /*!< DEFAULT : Default/Reset value.                                            */
78828 } WDT_LOCK_LOCK_Enum;
78829 
78830 /* =========================================================  COUNT  ========================================================= */
78831 /* ========================================================  DSP0CFG  ======================================================== */
78832 /* =======================================================  DSP0RSTRT  ======================================================= */
78833 /* ============================================  WDT DSP0RSTRT DSP0RSTART [0..7]  ============================================ */
78834 typedef enum {                                  /*!< WDT_DSP0RSTRT_DSP0RSTART                                                  */
78835   WDT_DSP0RSTRT_DSP0RSTART_KEYVALUE    = 105,   /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
78836                                                      the WDT. This is a write only register.                                   */
78837   WDT_DSP0RSTRT_DSP0RSTART_DEFAULT     = 0,     /*!< DEFAULT : Reset value                                                     */
78838 } WDT_DSP0RSTRT_DSP0RSTART_Enum;
78839 
78840 /* =======================================================  DSP0TLOCK  ======================================================= */
78841 /* =============================================  WDT DSP0TLOCK DSP0LOCK [0..7]  ============================================= */
78842 typedef enum {                                  /*!< WDT_DSP0TLOCK_DSP0LOCK                                                    */
78843   WDT_DSP0TLOCK_DSP0LOCK_KEYVALUE      = 167,   /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
78844                                                      the WDT.                                                                  */
78845   WDT_DSP0TLOCK_DSP0LOCK_DEFAULT       = 0,     /*!< DEFAULT : Reset Value.                                                    */
78846 } WDT_DSP0TLOCK_DSP0LOCK_Enum;
78847 
78848 /* =======================================================  DSP0COUNT  ======================================================= */
78849 /* ========================================================  DSP1CFG  ======================================================== */
78850 /* =======================================================  DSP1RSTRT  ======================================================= */
78851 /* ============================================  WDT DSP1RSTRT DSP1RSTART [0..7]  ============================================ */
78852 typedef enum {                                  /*!< WDT_DSP1RSTRT_DSP1RSTART                                                  */
78853   WDT_DSP1RSTRT_DSP1RSTART_KEYVALUE    = 210,   /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
78854                                                      the WDT. This is a write only register.                                   */
78855   WDT_DSP1RSTRT_DSP1RSTART_DEFAULT     = 0,     /*!< DEFAULT : Reset value                                                     */
78856 } WDT_DSP1RSTRT_DSP1RSTART_Enum;
78857 
78858 /* =======================================================  DSP1TLOCK  ======================================================= */
78859 /* =============================================  WDT DSP1TLOCK DSP1LOCK [0..7]  ============================================= */
78860 typedef enum {                                  /*!< WDT_DSP1TLOCK_DSP1LOCK                                                    */
78861   WDT_DSP1TLOCK_DSP1LOCK_KEYVALUE      = 78,    /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
78862                                                      the WDT.                                                                  */
78863   WDT_DSP1TLOCK_DSP1LOCK_DEFAULT       = 0,     /*!< DEFAULT : Reset Value.                                                    */
78864 } WDT_DSP1TLOCK_DSP1LOCK_Enum;
78865 
78866 /* =======================================================  DSP1COUNT  ======================================================= */
78867 /* =======================================================  WDTIEREN  ======================================================== */
78868 /* ======================================================  WDTIERSTAT  ======================================================= */
78869 /* =======================================================  WDTIERCLR  ======================================================= */
78870 /* =======================================================  WDTIERSET  ======================================================= */
78871 /* =======================================================  DSP0IEREN  ======================================================= */
78872 /* ======================================================  DSP0IERSTAT  ====================================================== */
78873 /* ======================================================  DSP0IERCLR  ======================================================= */
78874 /* ======================================================  DSP0IERSET  ======================================================= */
78875 /* =======================================================  DSP1IEREN  ======================================================= */
78876 /* ======================================================  DSP1IERSTAT  ====================================================== */
78877 /* ======================================================  DSP1IERCLR  ======================================================= */
78878 /* ======================================================  DSP1IERSET  ======================================================= */
78879 
78880 /** @} */ /* End of group EnumValue_peripherals */
78881 
78882 
78883 #ifdef __cplusplus
78884 }
78885 #endif
78886 
78887 #endif /* APOLLO4P_H */
78888 
78889 
78890 /** @} */ /* End of group apollo4p */
78891 
78892 /** @} */ /* End of group Ambiq Micro */
78893