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Searched refs:DSP0MBINTSTAT (Results 1 – 2 of 2) sorted by relevance

/hal_ambiq-3.5.0/CMSIS/AmbiqMicro/Include/
Dapollo4b_generic.h7058 …__IOM uint32_t DSP0MBINTSTAT; /*!< (@ 0x000000A8) DSP 0 Mailbox Interrupt Status … member
7061 …__IOM uint32_t DSP0MBINTSTAT : 32; /*!< [31..0] DSP 0 CPU Mailbox interrupt … member
Dapollo4p.h7176 …__IOM uint32_t DSP0MBINTSTAT; /*!< (@ 0x000000A8) DSP 0 Mailbox Interrupt Status … member
7179 …__IOM uint32_t DSP0MBINTSTAT : 32; /*!< [31..0] DSP 0 CPU Mailbox interrupt … member