Home
last modified time | relevance | path

Searched refs:DEV0DDR_b (Results 1 – 3 of 3) sorted by relevance

/hal_ambiq-3.5.0/mcu/apollo4p/hal/mcu/
Dam_hal_mspi.c1521 MSPIn(ui32Module)->DEV0DDR_b.EMULATEDDR0 = pConfig->bEmulateDDR ? 1 : 0; in am_hal_mspi_device_configure()
1998 MSPIn(ui32Module)->DEV0DDR_b.EMULATEDDR0 = 0; in am_hal_mspi_control()
2005 MSPIn(ui32Module)->DEV0DDR_b.EMULATEDDR0 = 1; in am_hal_mspi_control()
2018 MSPIn(ui32Module)->DEV0DDR_b.ENABLEDQS0 = pDQS->bDQSEnable; in am_hal_mspi_control()
2019 MSPIn(ui32Module)->DEV0DDR_b.DQSSYNCNEG0 = pDQS->bDQSSyncNeg; in am_hal_mspi_control()
2020 MSPIn(ui32Module)->DEV0DDR_b.ENABLEFINEDELAY0 = pDQS->bEnableFineDelay; in am_hal_mspi_control()
2021 MSPIn(ui32Module)->DEV0DDR_b.TXDQSDELAY0 = pDQS->ui8TxDQSDelay; in am_hal_mspi_control()
2022 MSPIn(ui32Module)->DEV0DDR_b.RXDQSDELAY0 = pDQS->ui8RxDQSDelay; in am_hal_mspi_control()
2023 MSPIn(ui32Module)->DEV0DDR_b.RXDQSDELAYNEG0 = pDQS->ui8RxDQSDelayNeg; in am_hal_mspi_control()
2024 MSPIn(ui32Module)->DEV0DDR_b.RXDQSDELAYNEGEN0 = pDQS->bRxDQSDelayNegEN; in am_hal_mspi_control()
[all …]
/hal_ambiq-3.5.0/CMSIS/AmbiqMicro/Include/
Dapollo4b_generic.h19320 } DEV0DDR_b; member
Dapollo4p.h19494 } DEV0DDR_b; member