1 //***************************************************************************** 2 // 3 // am_mcu_apollo4p_info1.h 4 // 5 //***************************************************************************** 6 7 //***************************************************************************** 8 // 9 // Copyright (c) 2023, Ambiq Micro, Inc. 10 // All rights reserved. 11 // 12 // Redistribution and use in source and binary forms, with or without 13 // modification, are permitted provided that the following conditions are met: 14 // 15 // 1. Redistributions of source code must retain the above copyright notice, 16 // this list of conditions and the following disclaimer. 17 // 18 // 2. Redistributions in binary form must reproduce the above copyright 19 // notice, this list of conditions and the following disclaimer in the 20 // documentation and/or other materials provided with the distribution. 21 // 22 // 3. Neither the name of the copyright holder nor the names of its 23 // contributors may be used to endorse or promote products derived from this 24 // software without specific prior written permission. 25 // 26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 30 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 // POSSIBILITY OF SUCH DAMAGE. 37 // 38 // This is part of revision release_sdk_4_4_0-3c5977e664 of the AmbiqSuite Development Package. 39 // 40 //***************************************************************************** 41 42 #ifndef AM_REG_INFO1_H 43 #define AM_REG_INFO1_H 44 45 #define AM_REG_INFO1_BASEADDR 0x42002000 46 #define AM_REG_INFO1n(n) 0x42002000 47 48 #define AM_REG_INFO1_SBL_VERSION_0_O 0x00001200 49 #define AM_REG_INFO1_SBL_VERSION_0_ADDR 0x42003200 50 #define AM_REG_INFO1_SBL_VERSION_1_O 0x00001204 51 #define AM_REG_INFO1_SBL_VERSION_1_ADDR 0x42003204 52 #define AM_REG_INFO1_SBR_VERSION_0_O 0x00001208 53 #define AM_REG_INFO1_SBR_VERSION_0_ADDR 0x42003208 54 #define AM_REG_INFO1_MAINPTR_O 0x00001210 55 #define AM_REG_INFO1_MAINPTR_ADDR 0x42003210 56 #define AM_REG_INFO1_RESETSTATUS_O 0x00001214 57 #define AM_REG_INFO1_RESETSTATUS_ADDR 0x42003214 58 #define AM_REG_INFO1_SBLOTA_O 0x00001218 59 #define AM_REG_INFO1_SBLOTA_ADDR 0x42003218 60 #define AM_REG_INFO1_SOCID0_O 0x00001220 61 #define AM_REG_INFO1_SOCID0_ADDR 0x42003220 62 #define AM_REG_INFO1_SOCID1_O 0x00001224 63 #define AM_REG_INFO1_SOCID1_ADDR 0x42003224 64 #define AM_REG_INFO1_SOCID2_O 0x00001228 65 #define AM_REG_INFO1_SOCID2_ADDR 0x42003228 66 #define AM_REG_INFO1_SOCID3_O 0x0000122c 67 #define AM_REG_INFO1_SOCID3_ADDR 0x4200322c 68 #define AM_REG_INFO1_SOCID4_O 0x00001230 69 #define AM_REG_INFO1_SOCID4_ADDR 0x42003230 70 #define AM_REG_INFO1_SOCID5_O 0x00001234 71 #define AM_REG_INFO1_SOCID5_ADDR 0x42003234 72 #define AM_REG_INFO1_SOCID6_O 0x00001238 73 #define AM_REG_INFO1_SOCID6_ADDR 0x42003238 74 #define AM_REG_INFO1_SOCID7_O 0x0000123c 75 #define AM_REG_INFO1_SOCID7_ADDR 0x4200323c 76 #define AM_REG_INFO1_PATCH_TRACKER0_O 0x00001240 77 #define AM_REG_INFO1_PATCH_TRACKER0_ADDR 0x42003240 78 #define AM_REG_INFO1_PATCH_TRACKER1_O 0x00001244 79 #define AM_REG_INFO1_PATCH_TRACKER1_ADDR 0x42003244 80 #define AM_REG_INFO1_PATCH_TRACKER2_O 0x00001248 81 #define AM_REG_INFO1_PATCH_TRACKER2_ADDR 0x42003248 82 #define AM_REG_INFO1_PATCH_TRACKER3_O 0x0000124c 83 #define AM_REG_INFO1_PATCH_TRACKER3_ADDR 0x4200324c 84 #define AM_REG_INFO1_SBR_SDCERT_ADDR_O 0x00001250 85 #define AM_REG_INFO1_SBR_SDCERT_ADDR_ADDR 0x42003250 86 #define AM_REG_INFO1_SBR_IPT_ADDR_O 0x00001258 87 #define AM_REG_INFO1_SBR_IPT_ADDR_ADDR 0x42003258 88 #define AM_REG_INFO1_SBR_OPT_ADDR_O 0x0000125c 89 #define AM_REG_INFO1_SBR_OPT_ADDR_ADDR 0x4200325c 90 #define AM_REG_INFO1_TEMP_CAL_ATE_O 0x00001300 91 #define AM_REG_INFO1_TEMP_CAL_ATE_ADDR 0x42003300 92 #define AM_REG_INFO1_TEMP_CAL_MEASURED_O 0x00001304 93 #define AM_REG_INFO1_TEMP_CAL_MEASURED_ADDR 0x42003304 94 #define AM_REG_INFO1_TEMP_CAL_ADC_OFFSET_O 0x00001308 95 #define AM_REG_INFO1_TEMP_CAL_ADC_OFFSET_ADDR 0x42003308 96 #define AM_REG_INFO1_CHIPSUBREV_O 0x0000130c 97 #define AM_REG_INFO1_CHIPSUBREV_ADDR 0x4200330c 98 #define AM_REG_INFO1_TRIM_REV_O 0x00001310 99 #define AM_REG_INFO1_TRIM_REV_ADDR 0x42003310 100 #define AM_REG_INFO1_FT1_GDR1_O 0x00001314 101 #define AM_REG_INFO1_FT1_GDR1_ADDR 0x42003314 102 #define AM_REG_INFO1_FT2_GDR1_O 0x00001318 103 #define AM_REG_INFO1_FT2_GDR1_ADDR 0x42003318 104 #define AM_REG_INFO1_LVT_TRIMCODE_O 0x0000131c 105 #define AM_REG_INFO1_LVT_TRIMCODE_ADDR 0x4200331c 106 #define AM_REG_INFO1_EHVT_TRIMCODE_O 0x00001320 107 #define AM_REG_INFO1_EHVT_TRIMCODE_ADDR 0x42003320 108 #define AM_REG_INFO1_AUDADC_BINNING_O 0x00001324 109 #define AM_REG_INFO1_AUDADC_BINNING_ADDR 0x42003324 110 #define AM_REG_INFO1_ADC_GAIN_ERR_O 0x00001328 111 #define AM_REG_INFO1_ADC_GAIN_ERR_ADDR 0x42003328 112 #define AM_REG_INFO1_ADC_OFFSET_ERR_O 0x0000132c 113 #define AM_REG_INFO1_ADC_OFFSET_ERR_ADDR 0x4200332c 114 #define AM_REG_INFO1_AUDADC_A0_LG_OFFSET_O 0x00001340 115 #define AM_REG_INFO1_AUDADC_A0_LG_OFFSET_ADDR 0x42003340 116 #define AM_REG_INFO1_AUDADC_A0_HG_SLOPE_O 0x00001344 117 #define AM_REG_INFO1_AUDADC_A0_HG_SLOPE_ADDR 0x42003344 118 #define AM_REG_INFO1_AUDADC_A0_HG_INTERCEPT_O 0x00001348 119 #define AM_REG_INFO1_AUDADC_A0_HG_INTERCEPT_ADDR 0x42003348 120 #define AM_REG_INFO1_AUDADC_A1_LG_OFFSET_O 0x0000134c 121 #define AM_REG_INFO1_AUDADC_A1_LG_OFFSET_ADDR 0x4200334c 122 #define AM_REG_INFO1_AUDADC_A1_HG_SLOPE_O 0x00001350 123 #define AM_REG_INFO1_AUDADC_A1_HG_SLOPE_ADDR 0x42003350 124 #define AM_REG_INFO1_AUDADC_A1_HG_INTERCEPT_O 0x00001354 125 #define AM_REG_INFO1_AUDADC_A1_HG_INTERCEPT_ADDR 0x42003354 126 #define AM_REG_INFO1_AUDADC_B0_LG_OFFSET_O 0x00001358 127 #define AM_REG_INFO1_AUDADC_B0_LG_OFFSET_ADDR 0x42003358 128 #define AM_REG_INFO1_AUDADC_B0_HG_SLOPE_O 0x0000135c 129 #define AM_REG_INFO1_AUDADC_B0_HG_SLOPE_ADDR 0x4200335c 130 #define AM_REG_INFO1_AUDADC_B0_HG_INTERCEPT_O 0x00001360 131 #define AM_REG_INFO1_AUDADC_B0_HG_INTERCEPT_ADDR 0x42003360 132 #define AM_REG_INFO1_AUDADC_B1_LG_OFFSET_O 0x00001364 133 #define AM_REG_INFO1_AUDADC_B1_LG_OFFSET_ADDR 0x42003364 134 #define AM_REG_INFO1_AUDADC_B1_HG_SLOPE_O 0x00001368 135 #define AM_REG_INFO1_AUDADC_B1_HG_SLOPE_ADDR 0x42003368 136 #define AM_REG_INFO1_AUDADC_B1_HG_INTERCEPT_O 0x0000136c 137 #define AM_REG_INFO1_AUDADC_B1_HG_INTERCEPT_ADDR 0x4200336c 138 139 // SBL_VERSION_0 - Contains the SBL Version number encoding. 140 #define AM_REG_INFO1_SBL_VERSION_0_VERSION_S 0 141 #define AM_REG_INFO1_SBL_VERSION_0_VERSION_M 0xFFFFFFFF 142 #define AM_REG_INFO1_SBL_VERSION_0_VERSION(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 143 #define AM_REG_INFO1_SBL_VERSION_0_VERSION_Pos 0 144 #define AM_REG_INFO1_SBL_VERSION_0_VERSION_Msk 0xFFFFFFFF 145 146 // SBL_VERSION_1 - Contains the SBL date code encoding. 147 #define AM_REG_INFO1_SBL_VERSION_1_DATECODE_S 0 148 #define AM_REG_INFO1_SBL_VERSION_1_DATECODE_M 0xFFFFFFFF 149 #define AM_REG_INFO1_SBL_VERSION_1_DATECODE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 150 #define AM_REG_INFO1_SBL_VERSION_1_DATECODE_Pos 0 151 #define AM_REG_INFO1_SBL_VERSION_1_DATECODE_Msk 0xFFFFFFFF 152 153 // SBR_VERSION_0 - Contains the SBR version number and date code. 154 #define AM_REG_INFO1_SBR_VERSION_0_VERSION_S 0 155 #define AM_REG_INFO1_SBR_VERSION_0_VERSION_M 0xFFFFFFFF 156 #define AM_REG_INFO1_SBR_VERSION_0_VERSION(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 157 #define AM_REG_INFO1_SBR_VERSION_0_VERSION_Pos 0 158 #define AM_REG_INFO1_SBR_VERSION_0_VERSION_Msk 0xFFFFFFFF 159 160 // MAINPTR - The location of the vector table of the main program. This value is read-only. 161 #define AM_REG_INFO1_MAINPTR_ADDRESS_S 0 162 #define AM_REG_INFO1_MAINPTR_ADDRESS_M 0xFFFFFFFF 163 #define AM_REG_INFO1_MAINPTR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 164 #define AM_REG_INFO1_MAINPTR_ADDRESS_Pos 0 165 #define AM_REG_INFO1_MAINPTR_ADDRESS_Msk 0xFFFFFFFF 166 167 // RESETSTATUS - The actual hardware reset status is maintained at this location by the Secure Boot Loader. This value is read only. 168 #define AM_REG_INFO1_RESETSTATUS_STATUS_S 0 169 #define AM_REG_INFO1_RESETSTATUS_STATUS_M 0xFFFFFFFF 170 #define AM_REG_INFO1_RESETSTATUS_STATUS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 171 #define AM_REG_INFO1_RESETSTATUS_STATUS_Pos 0 172 #define AM_REG_INFO1_RESETSTATUS_STATUS_Msk 0xFFFFFFFF 173 174 // SBLOTA - This is the address of the slot to be used by the Secure Boot Loader for staging an upgrade. 175 #define AM_REG_INFO1_SBLOTA_ADDRESS_S 0 176 #define AM_REG_INFO1_SBLOTA_ADDRESS_M 0xFFFFFFFF 177 #define AM_REG_INFO1_SBLOTA_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 178 #define AM_REG_INFO1_SBLOTA_ADDRESS_Pos 0 179 #define AM_REG_INFO1_SBLOTA_ADDRESS_Msk 0xFFFFFFFF 180 181 // SOCID0 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates. 182 #define AM_REG_INFO1_SOCID0_ID_S 0 183 #define AM_REG_INFO1_SOCID0_ID_M 0xFFFFFFFF 184 #define AM_REG_INFO1_SOCID0_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 185 #define AM_REG_INFO1_SOCID0_ID_Pos 0 186 #define AM_REG_INFO1_SOCID0_ID_Msk 0xFFFFFFFF 187 188 // SOCID1 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates. 189 #define AM_REG_INFO1_SOCID1_ID_S 0 190 #define AM_REG_INFO1_SOCID1_ID_M 0xFFFFFFFF 191 #define AM_REG_INFO1_SOCID1_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 192 #define AM_REG_INFO1_SOCID1_ID_Pos 0 193 #define AM_REG_INFO1_SOCID1_ID_Msk 0xFFFFFFFF 194 195 // SOCID2 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates. 196 #define AM_REG_INFO1_SOCID2_ID_S 0 197 #define AM_REG_INFO1_SOCID2_ID_M 0xFFFFFFFF 198 #define AM_REG_INFO1_SOCID2_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 199 #define AM_REG_INFO1_SOCID2_ID_Pos 0 200 #define AM_REG_INFO1_SOCID2_ID_Msk 0xFFFFFFFF 201 202 // SOCID3 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates. 203 #define AM_REG_INFO1_SOCID3_ID_S 0 204 #define AM_REG_INFO1_SOCID3_ID_M 0xFFFFFFFF 205 #define AM_REG_INFO1_SOCID3_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 206 #define AM_REG_INFO1_SOCID3_ID_Pos 0 207 #define AM_REG_INFO1_SOCID3_ID_Msk 0xFFFFFFFF 208 209 // SOCID4 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates. 210 #define AM_REG_INFO1_SOCID4_ID_S 0 211 #define AM_REG_INFO1_SOCID4_ID_M 0xFFFFFFFF 212 #define AM_REG_INFO1_SOCID4_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 213 #define AM_REG_INFO1_SOCID4_ID_Pos 0 214 #define AM_REG_INFO1_SOCID4_ID_Msk 0xFFFFFFFF 215 216 // SOCID5 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates. 217 #define AM_REG_INFO1_SOCID5_ID_S 0 218 #define AM_REG_INFO1_SOCID5_ID_M 0xFFFFFFFF 219 #define AM_REG_INFO1_SOCID5_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 220 #define AM_REG_INFO1_SOCID5_ID_Pos 0 221 #define AM_REG_INFO1_SOCID5_ID_Msk 0xFFFFFFFF 222 223 // SOCID6 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates. 224 #define AM_REG_INFO1_SOCID6_ID_S 0 225 #define AM_REG_INFO1_SOCID6_ID_M 0xFFFFFFFF 226 #define AM_REG_INFO1_SOCID6_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 227 #define AM_REG_INFO1_SOCID6_ID_Pos 0 228 #define AM_REG_INFO1_SOCID6_ID_Msk 0xFFFFFFFF 229 230 // SOCID7 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates. 231 #define AM_REG_INFO1_SOCID7_ID_S 0 232 #define AM_REG_INFO1_SOCID7_ID_M 0xFFFFFFFF 233 #define AM_REG_INFO1_SOCID7_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 234 #define AM_REG_INFO1_SOCID7_ID_Pos 0 235 #define AM_REG_INFO1_SOCID7_ID_Msk 0xFFFFFFFF 236 237 // PATCH_TRACKER0 - Apollo4 SBL patch tracking [31:0] 238 #define AM_REG_INFO1_PATCH_TRACKER0_RSVD0_S 0 239 #define AM_REG_INFO1_PATCH_TRACKER0_RSVD0_M 0xFFFFFFFF 240 #define AM_REG_INFO1_PATCH_TRACKER0_RSVD0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 241 #define AM_REG_INFO1_PATCH_TRACKER0_RSVD0_Pos 0 242 #define AM_REG_INFO1_PATCH_TRACKER0_RSVD0_Msk 0xFFFFFFFF 243 244 // PATCH_TRACKER1 - Apollo4 SBL patch tracking [63:32] 245 #define AM_REG_INFO1_PATCH_TRACKER1_RSVD1_S 0 246 #define AM_REG_INFO1_PATCH_TRACKER1_RSVD1_M 0xFFFFFFFF 247 #define AM_REG_INFO1_PATCH_TRACKER1_RSVD1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 248 #define AM_REG_INFO1_PATCH_TRACKER1_RSVD1_Pos 0 249 #define AM_REG_INFO1_PATCH_TRACKER1_RSVD1_Msk 0xFFFFFFFF 250 251 // PATCH_TRACKER2 - Apollo4 SBL patch tracking [95:64] 252 #define AM_REG_INFO1_PATCH_TRACKER2_RSVD2_S 0 253 #define AM_REG_INFO1_PATCH_TRACKER2_RSVD2_M 0xFFFFFFFF 254 #define AM_REG_INFO1_PATCH_TRACKER2_RSVD2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 255 #define AM_REG_INFO1_PATCH_TRACKER2_RSVD2_Pos 0 256 #define AM_REG_INFO1_PATCH_TRACKER2_RSVD2_Msk 0xFFFFFFFF 257 258 // PATCH_TRACKER3 - Apollo4 SBL patch tracking [127:96] 259 #define AM_REG_INFO1_PATCH_TRACKER3_RSVD3_S 0 260 #define AM_REG_INFO1_PATCH_TRACKER3_RSVD3_M 0xFFFFFFFF 261 #define AM_REG_INFO1_PATCH_TRACKER3_RSVD3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 262 #define AM_REG_INFO1_PATCH_TRACKER3_RSVD3_Pos 0 263 #define AM_REG_INFO1_PATCH_TRACKER3_RSVD3_Msk 0xFFFFFFFF 264 265 // SBR_SDCERT_ADDR - A pointer to the SD certificate. 266 #define AM_REG_INFO1_SBR_SDCERT_ADDR_ICV_S 0 267 #define AM_REG_INFO1_SBR_SDCERT_ADDR_ICV_M 0xFFFFFFFF 268 #define AM_REG_INFO1_SBR_SDCERT_ADDR_ICV(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 269 #define AM_REG_INFO1_SBR_SDCERT_ADDR_ICV_Pos 0 270 #define AM_REG_INFO1_SBR_SDCERT_ADDR_ICV_Msk 0xFFFFFFFF 271 272 // SBR_IPT_ADDR - A pointer to the SBR IPT. 273 #define AM_REG_INFO1_SBR_IPT_ADDR_ADDRESS_S 0 274 #define AM_REG_INFO1_SBR_IPT_ADDR_ADDRESS_M 0xFFFFFFFF 275 #define AM_REG_INFO1_SBR_IPT_ADDR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 276 #define AM_REG_INFO1_SBR_IPT_ADDR_ADDRESS_Pos 0 277 #define AM_REG_INFO1_SBR_IPT_ADDR_ADDRESS_Msk 0xFFFFFFFF 278 279 // SBR_OPT_ADDR - A pointer to the SBR OPT. 280 #define AM_REG_INFO1_SBR_OPT_ADDR_ADDRESS_S 0 281 #define AM_REG_INFO1_SBR_OPT_ADDR_ADDRESS_M 0xFFFFFFFF 282 #define AM_REG_INFO1_SBR_OPT_ADDR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 283 #define AM_REG_INFO1_SBR_OPT_ADDR_ADDRESS_Pos 0 284 #define AM_REG_INFO1_SBR_OPT_ADDR_ADDRESS_Msk 0xFFFFFFFF 285 286 // TEMP_CAL_ATE - The temperature measured on the ATE test head when the part's temperature sensor was calibrated. 287 #define AM_REG_INFO1_TEMP_CAL_ATE_TEMPERATURE_S 0 288 #define AM_REG_INFO1_TEMP_CAL_ATE_TEMPERATURE_M 0xFFFFFFFF 289 #define AM_REG_INFO1_TEMP_CAL_ATE_TEMPERATURE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 290 #define AM_REG_INFO1_TEMP_CAL_ATE_TEMPERATURE_Pos 0 291 #define AM_REG_INFO1_TEMP_CAL_ATE_TEMPERATURE_Msk 0xFFFFFFFF 292 293 // TEMP_CAL_MEASURED - The voltage measured on the analog test mux output when the part's temperature sensor was calibrated. 294 #define AM_REG_INFO1_TEMP_CAL_MEASURED_VOLTS_S 0 295 #define AM_REG_INFO1_TEMP_CAL_MEASURED_VOLTS_M 0xFFFFFFFF 296 #define AM_REG_INFO1_TEMP_CAL_MEASURED_VOLTS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 297 #define AM_REG_INFO1_TEMP_CAL_MEASURED_VOLTS_Pos 0 298 #define AM_REG_INFO1_TEMP_CAL_MEASURED_VOLTS_Msk 0xFFFFFFFF 299 300 // TEMP_CAL_ADC_OFFSET - The offset voltage measured on for the ADC when the part's temperature sensor was calibrated. 301 #define AM_REG_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS_S 0 302 #define AM_REG_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS_M 0xFFFFFFFF 303 #define AM_REG_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 304 #define AM_REG_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS_Pos 0 305 #define AM_REG_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS_Msk 0xFFFFFFFF 306 307 // CHIPSUBREV - 308 #define AM_REG_INFO1_CHIPSUBREV_VOLTS_S 0 309 #define AM_REG_INFO1_CHIPSUBREV_VOLTS_M 0xFFFFFFFF 310 #define AM_REG_INFO1_CHIPSUBREV_VOLTS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 311 #define AM_REG_INFO1_CHIPSUBREV_VOLTS_Pos 0 312 #define AM_REG_INFO1_CHIPSUBREV_VOLTS_Msk 0xFFFFFFFF 313 314 // TRIM_REV - Contains the trim revision number. 315 #define AM_REG_INFO1_TRIM_REV_REVNUM_S 0 316 #define AM_REG_INFO1_TRIM_REV_REVNUM_M 0xFFFFFFFF 317 #define AM_REG_INFO1_TRIM_REV_REVNUM(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 318 #define AM_REG_INFO1_TRIM_REV_REVNUM_Pos 0 319 #define AM_REG_INFO1_TRIM_REV_REVNUM_Msk 0xFFFFFFFF 320 321 // FT1_GDR1 - Copy of FT1 GDR1 322 #define AM_REG_INFO1_FT1_GDR1_FTVAL_S 0 323 #define AM_REG_INFO1_FT1_GDR1_FTVAL_M 0xFFFFFFFF 324 #define AM_REG_INFO1_FT1_GDR1_FTVAL(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 325 #define AM_REG_INFO1_FT1_GDR1_FTVAL_Pos 0 326 #define AM_REG_INFO1_FT1_GDR1_FTVAL_Msk 0xFFFFFFFF 327 328 // FT2_GDR1 - Copy of FT2 GDR1 329 #define AM_REG_INFO1_FT2_GDR1_FTVAL_S 0 330 #define AM_REG_INFO1_FT2_GDR1_FTVAL_M 0xFFFFFFFF 331 #define AM_REG_INFO1_FT2_GDR1_FTVAL(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 332 #define AM_REG_INFO1_FT2_GDR1_FTVAL_Pos 0 333 #define AM_REG_INFO1_FT2_GDR1_FTVAL_Msk 0xFFFFFFFF 334 335 // LVT_TRIMCODE - LVT trim code value. 336 #define AM_REG_INFO1_LVT_TRIMCODE_TRIMCODE_S 0 337 #define AM_REG_INFO1_LVT_TRIMCODE_TRIMCODE_M 0xFFFFFFFF 338 #define AM_REG_INFO1_LVT_TRIMCODE_TRIMCODE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 339 #define AM_REG_INFO1_LVT_TRIMCODE_TRIMCODE_Pos 0 340 #define AM_REG_INFO1_LVT_TRIMCODE_TRIMCODE_Msk 0xFFFFFFFF 341 342 // EHVT_TRIMCODE - EHVT trim code value. 343 #define AM_REG_INFO1_EHVT_TRIMCODE_TRIMCODE_S 0 344 #define AM_REG_INFO1_EHVT_TRIMCODE_TRIMCODE_M 0xFFFFFFFF 345 #define AM_REG_INFO1_EHVT_TRIMCODE_TRIMCODE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 346 #define AM_REG_INFO1_EHVT_TRIMCODE_TRIMCODE_Pos 0 347 #define AM_REG_INFO1_EHVT_TRIMCODE_TRIMCODE_Msk 0xFFFFFFFF 348 349 // AUDADC_BINNING - Audio ADC binning value 350 #define AM_REG_INFO1_AUDADC_BINNING_STATUS_S 0 351 #define AM_REG_INFO1_AUDADC_BINNING_STATUS_M 0xFFFFFFFF 352 #define AM_REG_INFO1_AUDADC_BINNING_STATUS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 353 #define AM_REG_INFO1_AUDADC_BINNING_STATUS_Pos 0 354 #define AM_REG_INFO1_AUDADC_BINNING_STATUS_Msk 0xFFFFFFFF 355 356 // ADC_GAIN_ERR - This float value is the ADC gain error used for correcting the error from ADC measurement. 357 #define AM_REG_INFO1_ADC_GAIN_ERR_ERROR_S 0 358 #define AM_REG_INFO1_ADC_GAIN_ERR_ERROR_M 0xFFFFFFFF 359 #define AM_REG_INFO1_ADC_GAIN_ERR_ERROR(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 360 #define AM_REG_INFO1_ADC_GAIN_ERR_ERROR_Pos 0 361 #define AM_REG_INFO1_ADC_GAIN_ERR_ERROR_Msk 0xFFFFFFFF 362 363 // ADC_OFFSET_ERR - This float value is the ADC offset (volts). 364 #define AM_REG_INFO1_ADC_OFFSET_ERR_OFFSET_S 0 365 #define AM_REG_INFO1_ADC_OFFSET_ERR_OFFSET_M 0xFFFFFFFF 366 #define AM_REG_INFO1_ADC_OFFSET_ERR_OFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 367 #define AM_REG_INFO1_ADC_OFFSET_ERR_OFFSET_Pos 0 368 #define AM_REG_INFO1_ADC_OFFSET_ERR_OFFSET_Msk 0xFFFFFFFF 369 370 // AUDADC_A0_LG_OFFSET - This is the float value for low gain offset (less than 12dB). A0 maps to Slot 0 371 #define AM_REG_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET_S 0 372 #define AM_REG_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET_M 0xFFFFFFFF 373 #define AM_REG_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 374 #define AM_REG_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET_Pos 0 375 #define AM_REG_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET_Msk 0xFFFFFFFF 376 377 // AUDADC_A0_HG_SLOPE - This is the float value for high gain slope (more than 12dB). A0 maps to Slot 0 378 #define AM_REG_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE_S 0 379 #define AM_REG_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE_M 0xFFFFFFFF 380 #define AM_REG_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 381 #define AM_REG_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE_Pos 0 382 #define AM_REG_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE_Msk 0xFFFFFFFF 383 384 // AUDADC_A0_HG_INTERCEPT - This is the float value for high gain intercept (more than 12dB). A0 maps to Slot 0 385 #define AM_REG_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT_S 0 386 #define AM_REG_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT_M 0xFFFFFFFF 387 #define AM_REG_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 388 #define AM_REG_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT_Pos 0 389 #define AM_REG_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT_Msk 0xFFFFFFFF 390 391 // AUDADC_A1_LG_OFFSET - This is the float value for low gain offset (less than 12dB). A1 maps to Slot 1 392 #define AM_REG_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET_S 0 393 #define AM_REG_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET_M 0xFFFFFFFF 394 #define AM_REG_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 395 #define AM_REG_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET_Pos 0 396 #define AM_REG_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET_Msk 0xFFFFFFFF 397 398 // AUDADC_A1_HG_SLOPE - This is the float value for high gain slope (more than 12dB). A1 maps to Slot 1 399 #define AM_REG_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE_S 0 400 #define AM_REG_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE_M 0xFFFFFFFF 401 #define AM_REG_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 402 #define AM_REG_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE_Pos 0 403 #define AM_REG_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE_Msk 0xFFFFFFFF 404 405 // AUDADC_A1_HG_INTERCEPT - This is the float value for high gain intercept (more than 12dB). A1 maps to Slot 1 406 #define AM_REG_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT_S 0 407 #define AM_REG_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT_M 0xFFFFFFFF 408 #define AM_REG_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 409 #define AM_REG_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT_Pos 0 410 #define AM_REG_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT_Msk 0xFFFFFFFF 411 412 // AUDADC_B0_LG_OFFSET - This is the float value for low gain offset (less than 12dB). B0 maps to Slot 2 413 #define AM_REG_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET_S 0 414 #define AM_REG_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET_M 0xFFFFFFFF 415 #define AM_REG_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 416 #define AM_REG_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET_Pos 0 417 #define AM_REG_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET_Msk 0xFFFFFFFF 418 419 // AUDADC_B0_HG_SLOPE - This is the float value for high gain slope (more than 12dB). B0 maps to Slot 2 420 #define AM_REG_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE_S 0 421 #define AM_REG_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE_M 0xFFFFFFFF 422 #define AM_REG_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 423 #define AM_REG_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE_Pos 0 424 #define AM_REG_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE_Msk 0xFFFFFFFF 425 426 // AUDADC_B0_HG_INTERCEPT - This is the float value for high gain intercept (more than 12dB). B0 maps to Slot 2 427 #define AM_REG_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT_S 0 428 #define AM_REG_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT_M 0xFFFFFFFF 429 #define AM_REG_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 430 #define AM_REG_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT_Pos 0 431 #define AM_REG_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT_Msk 0xFFFFFFFF 432 433 // AUDADC_B1_LG_OFFSET - This is the float value for low gain offset (less than 12dB). B1 maps to Slot 3 434 #define AM_REG_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET_S 0 435 #define AM_REG_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET_M 0xFFFFFFFF 436 #define AM_REG_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 437 #define AM_REG_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET_Pos 0 438 #define AM_REG_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET_Msk 0xFFFFFFFF 439 440 // AUDADC_B1_HG_SLOPE - This is the float value for high gain slope (more than 12dB). B1 maps to Slot 3 441 #define AM_REG_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE_S 0 442 #define AM_REG_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE_M 0xFFFFFFFF 443 #define AM_REG_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 444 #define AM_REG_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE_Pos 0 445 #define AM_REG_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE_Msk 0xFFFFFFFF 446 447 // AUDADC_B1_HG_INTERCEPT - This is the float value for high gain intercept (more than 12dB). B1 maps to Slot 3 448 #define AM_REG_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT_S 0 449 #define AM_REG_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT_M 0xFFFFFFFF 450 #define AM_REG_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 451 #define AM_REG_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT_Pos 0 452 #define AM_REG_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT_Msk 0xFFFFFFFF 453 454 #endif 455
