1 //***************************************************************************** 2 // 3 //! @file am_hal_pwrctrl.h 4 //! 5 //! @brief Functions for enabling and disabling power domains. 6 //! 7 //! @addtogroup pwrctrl4_4p PWRCTRL - Power Control 8 //! @ingroup apollo4p_hal 9 //! @{ 10 11 //***************************************************************************** 12 13 //***************************************************************************** 14 // 15 // Copyright (c) 2023, Ambiq Micro, Inc. 16 // All rights reserved. 17 // 18 // Redistribution and use in source and binary forms, with or without 19 // modification, are permitted provided that the following conditions are met: 20 // 21 // 1. Redistributions of source code must retain the above copyright notice, 22 // this list of conditions and the following disclaimer. 23 // 24 // 2. Redistributions in binary form must reproduce the above copyright 25 // notice, this list of conditions and the following disclaimer in the 26 // documentation and/or other materials provided with the distribution. 27 // 28 // 3. Neither the name of the copyright holder nor the names of its 29 // contributors may be used to endorse or promote products derived from this 30 // software without specific prior written permission. 31 // 32 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 36 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 37 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 38 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 39 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 40 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 41 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 42 // POSSIBILITY OF SUCH DAMAGE. 43 // 44 // This is part of revision release_sdk_4_4_0-3c5977e664 of the AmbiqSuite Development Package. 45 // 46 //***************************************************************************** 47 48 #ifndef AM_HAL_PWRCTRL_H 49 #define AM_HAL_PWRCTRL_H 50 51 #ifdef __cplusplus 52 extern "C" 53 { 54 #endif 55 56 //***************************************************************************** 57 // 58 //! @name Delays (in uS) required for VDDF/VDDC trim enhancements. 59 //! @{ 60 // 61 //***************************************************************************** 62 #define AM_HAL_PWRCTRL_VDDF_BOOST_DELAY 20 63 #define AM_HAL_PWRCTRL_MEMLDO_BOOST_DELAY 20 64 #define AM_HAL_PWRCTRL_VDDC_BOOST_DELAY 20 65 #define AM_HAL_PWRCTRL_GOTOLDO_DELAY 20 66 //! @} 67 68 //***************************************************************************** 69 // 70 //! Option to optimize VDDF active and MEM LDO active when Crypto is not active. 71 //! AM_HAL_PWRCTL_OPTIMIZE_ACTIVE_TRIMS_CRYPTO 72 //! 0 = No trim optimizations depending on Crypto state. 73 //! 1 = Reduce voltage when Crypto is not active. 74 // Default: 1 75 // 76 //***************************************************************************** 77 #define AM_HAL_PWRCTL_OPTIMIZE_ACTIVE_TRIMS_CRYPTO 1 78 79 //***************************************************************************** 80 // 81 //! Option for coreldo and memldo to operate in parallel with simobuck 82 //! AM_HAL_PWRCTL_SET_CORELDO_MEMLDO_IN_PARALLEL 83 //! 0 = Do not turn on LDOs in parallel with simobuck. 84 //! 1 = Turn on LDOs in parallel with simobuck and set their voltage levels 85 //! ~35mV lower than minimum buck voltages. 86 //! Default: 1 87 //! NOTE: FOR Apollo4P - this must be 1 88 // 89 //***************************************************************************** 90 #define AM_HAL_PWRCTL_SET_CORELDO_MEMLDO_IN_PARALLEL 1 91 92 #if (AM_HAL_PWRCTL_SET_CORELDO_MEMLDO_IN_PARALLEL == 0) 93 #error Apollo4p requires AM_HAL_PWRCTL_SET_CORELDO_MEMLDO_IN_PARALLEL. 94 #endif 95 96 97 //***************************************************************************** 98 // 99 //! Option to assist VDDC by activating LDOs when disabling SIMOBUCK. 100 //! AM_HAL_PWRCTRL_LDOS_FOR_VDDC 101 //! 0 = Do not assist VDDC. 102 //! 1 = Activate LDOs in parallel when disabling SIMOBUCK. 103 //! Default: 1 104 // 105 //***************************************************************************** 106 #define AM_HAL_PWRCTRL_LDOS_FOR_VDDC 1 107 #if ( (AM_HAL_PWRCTL_SET_CORELDO_MEMLDO_IN_PARALLEL == 0) && (AM_HAL_PWRCTRL_LDOS_FOR_VDDC != 0) ) 108 #warning AM_HAL_PWRCTRL_LDOS_FOR_VDDC requires AM_HAL_PWRCTL_SET_CORELDO_MEMLDO_IN_PARALLEL. 109 #endif 110 111 //***************************************************************************** 112 // 113 //! Option for shorting VDDF to VDDS 114 //! AM_HAL_PWRCTL_SHORT_VDDF_TO_VDDS 115 //! 0 = Leave inactive. 116 //! 1 = Set trims to short. 117 //! Default: 1 118 // 119 //***************************************************************************** 120 #define AM_HAL_PWRCTL_SHORT_VDDF_TO_VDDS 1 121 122 // 123 //! Check for invalid option combinations 124 // 125 #if ( (AM_HAL_PWRCTL_SET_CORELDO_MEMLDO_IN_PARALLEL != 0) && (AM_HAL_PWRCTL_SHORT_VDDF_TO_VDDS == 0) ) 126 #error AM_HAL_PWRCTL_SET_CORELDO_MEMLDO_IN_PARALLEL must include AM_HAL_PWRCTL_SHORT_VDDF_TO_VDDS. 127 #endif 128 129 //***************************************************************************** 130 // 131 //! Option to connect MCU core to VDDC_LV for increased power efficiency. Ambiq 132 //! recommends this option be enabled for all new applications 133 // 134 // 135 //! Default: 1 for RevC 136 //***************************************************************************** 137 #define AM_HAL_PWRCTRL_CORE_PWR_OPTIMAL_EFFICIENCY 1 138 139 //***************************************************************************** 140 // 141 //! Option for the TempCo power minimum power. 142 // 143 //***************************************************************************** 144 #define AM_HAL_TEMPCO_LP 1 145 #if AM_HAL_TEMPCO_LP 146 #define AM_HAL_TEMPCO_DELAYUS 30 147 148 // 149 //! Define the recommended number of ADC samples required for accurate 150 //! temperature measurement. This number of samples must be passed along 151 //! to the HAL function, am_hal_pwrctrl_tempco_sample_handler(). 152 // 153 #define AM_HAL_TEMPCO_NUMSAMPLES 5 154 #endif // AM_HAL_TEMPCO_LP 155 156 //***************************************************************************** 157 // 158 //! Option for using the 70C workarounds 159 //! AM_HAL_PWRCTRL_70C_WA 160 //! 0 = Leave inactive. 161 //! 1 = enable 2 workarounds 162 //! AM_HAL_PWRCTL_HPLP_WA 163 //! AM_HAL_PWRCTL_SHORT_VDDC_TO_VDDCLV 164 //! Default: 0 165 // 166 //***************************************************************************** 167 #define AM_HAL_PWRCTRL_70C_WA 0 168 169 //***************************************************************************** 170 // 171 //! AM_HAL_PWRCTL_HPLP_WA workaround implementation uses a TIMER interrupt 172 //! AM_HAL_WRITE_WAIT_TIMER (TIMER13) defined in am_hal_global.h. The interrupt 173 //! is configured as the highest priority (0) interrupt to prevent unintentional 174 //! break out due to other interrupts. 175 //! 176 //! @note In order for this to work reliably, it is required that all the other 177 //! interrupts in the system are set at a lower priority, reserving the highest 178 //! priority interrupt exclusively for AmbiqSuite workaround. 179 // 180 //***************************************************************************** 181 #if (AM_HAL_PWRCTRL_70C_WA == 1) 182 #define AM_HAL_PWRCTL_HPLP_WA 183 #endif 184 185 #ifdef AM_HAL_PWRCTL_HPLP_WA 186 #define AM_HAL_PWRCTL_HPLP_DELAY 10 187 #endif 188 189 //***************************************************************************** 190 // 191 //! Option for shorting VDDC to VDDC_LV During normal operation 192 //! 193 //! @note During normal operation in active and deep-sleep, VDDC_LV is 194 //! disconnected from VDDC. While the VDDC_LV rail is disconnected from 195 //! VDDC, the VDDC_LV capacitor slowly discharges due to leakage. 196 //! A deeply discharged VDDC_LV capacitor can cause a large drop in VDDC 197 //! voltage when VDDC_LV and VDDC are shorted together. When the device 198 //! switches from SIMOBUCK to LDO mode, VDDC_LV and VDDC are shorted. 199 //! 200 //! AM_HAL_PWRCTL_SHORT_VDDC_TO_VDDCLV 201 //! Set trims to short. Uses extra power in Deepsleep. 202 //! Default: undefined 203 // 204 //***************************************************************************** 205 #if (AM_HAL_PWRCTRL_70C_WA == 1) 206 #define AM_HAL_PWRCTL_SHORT_VDDC_TO_VDDCLV 207 #endif 208 209 //***************************************************************************** 210 // 211 //! Due to the nature of these two macros, they cannot be defined together 212 //! - AM_HAL_PWRCTL_SHORT_VDDC_TO_VDDCLV shorts VDDC and VDDC_LV 213 //! - AM_HAL_PWRCTRL_CORE_PWR_OPTIMAL_EFFICIENCY turns on VDDC_LV for 214 //! power savings 215 // 216 //***************************************************************************** 217 #ifdef AM_HAL_PWRCTL_SHORT_VDDC_TO_VDDCLV 218 #if (AM_HAL_PWRCTRL_CORE_PWR_OPTIMAL_EFFICIENCY == 1) 219 #undef AM_HAL_PWRCTRL_CORE_PWR_OPTIMAL_EFFICIENCY 220 #endif 221 #endif 222 223 //***************************************************************************** 224 // 225 //! @name Performace mode enums. 226 //! @{ 227 // 228 //***************************************************************************** 229 // 230 //! Peripheral MCU Mode power enum. 231 // 232 typedef enum 233 { 234 AM_HAL_PWRCTRL_MCU_MODE_LOW_POWER = PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_LP, // 96 MHz 235 AM_HAL_PWRCTRL_MCU_MODE_HIGH_PERFORMANCE = PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_HP, // 192 MHz 236 } am_hal_pwrctrl_mcu_mode_e; 237 238 // 239 //! Peripheral DSP Mode power enum. 240 // 241 typedef enum 242 { 243 AM_HAL_PWRCTRL_DSP_MODE_ULTRA_LOW_POWER, // 48 MHz 244 AM_HAL_PWRCTRL_DSP_MODE_LOW_POWER, // 192 MHz 245 AM_HAL_PWRCTRL_DSP_MODE_HIGH_PERFORMANCE, // 384 MHz 246 } am_hal_pwrctrl_dsp_mode_e; 247 // 248 //! @} 249 // 250 251 //***************************************************************************** 252 // 253 //! Peripheral power enum. 254 // 255 //***************************************************************************** 256 typedef enum 257 { 258 AM_HAL_PWRCTRL_PERIPH_IOS, 259 AM_HAL_PWRCTRL_PERIPH_IOM0, 260 AM_HAL_PWRCTRL_PERIPH_IOM1, 261 AM_HAL_PWRCTRL_PERIPH_IOM2, 262 AM_HAL_PWRCTRL_PERIPH_IOM3, 263 AM_HAL_PWRCTRL_PERIPH_IOM4, 264 AM_HAL_PWRCTRL_PERIPH_IOM5, 265 AM_HAL_PWRCTRL_PERIPH_IOM6, 266 AM_HAL_PWRCTRL_PERIPH_IOM7, 267 AM_HAL_PWRCTRL_PERIPH_UART0, 268 AM_HAL_PWRCTRL_PERIPH_UART1, 269 AM_HAL_PWRCTRL_PERIPH_UART2, 270 AM_HAL_PWRCTRL_PERIPH_UART3, 271 AM_HAL_PWRCTRL_PERIPH_ADC, 272 AM_HAL_PWRCTRL_PERIPH_MSPI0, 273 AM_HAL_PWRCTRL_PERIPH_MSPI1, 274 AM_HAL_PWRCTRL_PERIPH_MSPI2, 275 AM_HAL_PWRCTRL_PERIPH_GFX, 276 AM_HAL_PWRCTRL_PERIPH_DISP, 277 AM_HAL_PWRCTRL_PERIPH_DISPPHY, 278 AM_HAL_PWRCTRL_PERIPH_CRYPTO, 279 AM_HAL_PWRCTRL_PERIPH_SDIO, 280 AM_HAL_PWRCTRL_PERIPH_USB, 281 AM_HAL_PWRCTRL_PERIPH_USBPHY, 282 AM_HAL_PWRCTRL_PERIPH_DEBUG, 283 AM_HAL_PWRCTRL_PERIPH_AUDREC, 284 AM_HAL_PWRCTRL_PERIPH_AUDPB, 285 AM_HAL_PWRCTRL_PERIPH_PDM0, 286 AM_HAL_PWRCTRL_PERIPH_PDM1, 287 AM_HAL_PWRCTRL_PERIPH_PDM2, 288 AM_HAL_PWRCTRL_PERIPH_PDM3, 289 AM_HAL_PWRCTRL_PERIPH_I2S0, 290 AM_HAL_PWRCTRL_PERIPH_I2S1, 291 AM_HAL_PWRCTRL_PERIPH_AUDADC, 292 AM_HAL_PWRCTRL_PERIPH_MAX 293 } am_hal_pwrctrl_periph_e; 294 295 //***************************************************************************** 296 // 297 // MCU memory control settings. 298 // 299 //***************************************************************************** 300 301 // 302 //! Cache enable settings. 303 // 304 typedef enum 305 { 306 AM_HAL_PWRCTRL_CACHE_NONE, 307 AM_HAL_PWRCTRL_CACHEB0_ONLY, 308 AM_HAL_PWRCTRL_CACHE_ALL, 309 } am_hal_pwrctrl_cache_select_e; 310 311 // 312 //! DTCM enable settings. 313 // 314 typedef enum 315 { 316 AM_HAL_PWRCTRL_DTCM_NONE = PWRCTRL_MEMPWREN_PWRENDTCM_NONE, 317 AM_HAL_PWRCTRL_DTCM_8K = PWRCTRL_MEMPWREN_PWRENDTCM_TCM8K, 318 AM_HAL_PWRCTRL_DTCM_128K = PWRCTRL_MEMPWREN_PWRENDTCM_TCM128K, 319 AM_HAL_PWRCTRL_DTCM_384K = PWRCTRL_MEMPWREN_PWRENDTCM_TCM384K, 320 } am_hal_pwrctrl_dtcm_select_e; 321 322 // 323 //! MCU memory configuration structure. 324 // 325 typedef struct 326 { 327 // 328 //! Cache configuration. 329 // 330 am_hal_pwrctrl_cache_select_e eCacheCfg; 331 bool bRetainCache; 332 333 // 334 //! DTCM configuration 335 // 336 am_hal_pwrctrl_dtcm_select_e eDTCMCfg; 337 am_hal_pwrctrl_dtcm_select_e eRetainDTCM; 338 339 // 340 //! NVM configuration. 341 // 342 bool bEnableNVM0; 343 bool bRetainNVM0; 344 } am_hal_pwrctrl_mcu_memory_config_t; 345 346 // 347 //! Miscellaneous power controls. 348 // 349 typedef enum 350 { 351 AM_HAL_PWRCTRL_CONTROL_SIMOBUCK_INIT, // Enable the SIMOBUCK 352 AM_HAL_PWRCTRL_CONTROL_CRYPTO_POWERDOWN, // Power down Crypto 353 AM_HAL_PWRCTRL_CONTROL_XTAL_PWDN_DEEPSLEEP, // Allow the crystal to power down during deepsleep 354 AM_HAL_PWRCTRL_CONTROL_DIS_PERIPHS_ALL, // Power down all peripherals 355 #if AM_HAL_TEMPCO_LP 356 AM_HAL_PWRCTRL_CONTROL_TEMPCO_GETMEASTEMP, // TempCo, return the measured temperature 357 #endif // AM_HAL_TEMPCO_LP 358 } am_hal_pwrctrl_control_e; 359 360 361 // 362 //! DSP memory config settings. 363 // 364 typedef struct 365 { 366 bool bEnableICache; 367 bool bRetainCache; 368 bool bEnableRAM; 369 bool bActiveRAM; 370 bool bRetainRAM; 371 } am_hal_pwrctrl_dsp_memory_config_t; 372 373 //***************************************************************************** 374 // 375 //! Shared memory control settings. 376 // 377 //***************************************************************************** 378 typedef enum 379 { 380 AM_HAL_PWRCTRL_SRAM_NONE = PWRCTRL_SSRAMPWREN_PWRENSSRAM_NONE, // No SSRAM 381 AM_HAL_PWRCTRL_SRAM_1M_GRP0 = PWRCTRL_SSRAMPWREN_PWRENSSRAM_GROUP0, // Lower 1M 382 AM_HAL_PWRCTRL_SRAM_1M_GRP1 = PWRCTRL_SSRAMPWREN_PWRENSSRAM_GROUP1, // Upper 1M 383 AM_HAL_PWRCTRL_SRAM_ALL = PWRCTRL_SSRAMPWREN_PWRENSSRAM_ALL, // All shared SRAM (2M) 384 // Legacy naming 385 AM_HAL_PWRCTRL_SRAM_1M = AM_HAL_PWRCTRL_SRAM_1M_GRP0, 386 AM_HAL_PWRCTRL_SRAM_2M = AM_HAL_PWRCTRL_SRAM_ALL 387 } am_hal_pwrctrl_sram_select_e; 388 389 //***************************************************************************** 390 // 391 //! Shared memory config settings. 392 // 393 //***************************************************************************** 394 typedef struct 395 { 396 // 397 //! Shared SRAM (SSRAM) banks to enable. 398 //! AM_HAL_PWRCTRL_SRAM_NONE = No SSRAM enabled. 399 //! AM_HAL_PWRCTRL_SRAM_1M_GRP0 = Lower 1M enabled, upper 1M disabled. 400 //! AM_HAL_PWRCTRL_SRAM_1M_GRP1 = Upper 1M enabled, lower 1M disabled. 401 //! AM_HAL_PWRCTRL_SRAM_ALL = ALL SSRAM enabled. 402 //! These bits are written to SSRAMPWREN.PWRENSSRAM. 403 // 404 am_hal_pwrctrl_sram_select_e eSRAMCfg; 405 406 // 407 //! For each of the eActiveWithXxx settings (which apply to each master). 408 //! AM_HAL_PWRCTRL_SRAM_NONE = Allow SSRAM to go to retention during deep sleep. 409 //! AM_HAL_PWRCTRL_SRAM_1M_GRP0 = Lower 1M forced on, upper 1M allowed to retention in deep sleep. 410 //! AM_HAL_PWRCTRL_SRAM_1M_GRP1 = Upper 1M forced on, lower 1M allowed to retention in deep sleep. 411 //! AM_HAL_PWRCTRL_SRAM_ALL = SSRAM forced on even in deep sleep. 412 // 413 //! Activate SSRAM when the MCU is active. 414 //! These bits are written to SSRAMRETCFG.SSRAMACTMCU. 415 // 416 am_hal_pwrctrl_sram_select_e eActiveWithMCU; 417 418 // 419 //! Activate SSRAM when the Graphics is active. 420 //! These bits are written to SSRAMRETCFG.SSRAMACTGFX. 421 // 422 am_hal_pwrctrl_sram_select_e eActiveWithGFX; 423 424 // 425 //! Activate SSRAM when the DISPLAY is active. 426 //! These bits are written to SSRAMRETCFG.SSRAMACTDISP. 427 // 428 am_hal_pwrctrl_sram_select_e eActiveWithDISP; 429 430 // 431 //! Activate SSRAM when either of the DSPs are active. 432 //! These bits are written to SSRAMRETCFG.SSRAMACTDSP. 433 // 434 am_hal_pwrctrl_sram_select_e eActiveWithDSP; 435 436 // 437 //! Retain SSRAM in deep sleep. 438 //! For SSRAM retention: 439 //! AM_HAL_PWRCTRL_SRAM_NONE = Power down all SSRAM in deepsleep (no retention). 440 //! AM_HAL_PWRCTRL_SRAM_1M_GRP0 = Retain lower 1M, power down upper 1M in deepsleep. 441 //! AM_HAL_PWRCTRL_SRAM_1M_GRP1 = Retain upper 1M, power down lower 1M in deepsleep. 442 //! AM_HAL_PWRCTRL_SRAM_ALL = Retain all SSRAM in deepsleep. 443 //! The HAL writes the INVERSE of these bits to SSRAMRETCFG.SSRAMPWDSLP in order to 444 //! provide the desired action. 445 // 446 am_hal_pwrctrl_sram_select_e eSRAMRetain; 447 448 } am_hal_pwrctrl_sram_memcfg_t; 449 450 //***************************************************************************** 451 // 452 //! System power status structure 453 // 454 //***************************************************************************** 455 typedef struct 456 { 457 // 458 //! DEVPWRSTATUS - Device Power ON Status 459 // 460 uint32_t ui32Device; 461 462 // 463 //! AUDSSPWRSTATUS - Audio Subsystem ON Status 464 // 465 uint32_t ui32AudioSS; 466 467 // 468 //! MEMPWRSTATUS - MCU Memory Power ON Status 469 // 470 uint32_t ui32Memory; 471 472 // 473 //! SYSPWRSTATUS - Power ON Status for MCU and DSP0/1 Cores 474 // 475 uint32_t ui32System; 476 477 // 478 //! SSRAMPWRST - Shared SRAM Power ON Status 479 // 480 uint32_t ui32SSRAM; 481 482 // 483 //! AUDSSPWRSTATUS - Audio Subsystem Power ON Status 484 // 485 uint32_t ui32Audio; 486 487 // 488 //! DSP0MEMPWRST - DSP0 Memories Power ON Status 489 // 490 uint32_t ui32DSP0MemStatus; 491 492 // 493 //! DSP1MEMPWRST - DSP1 Memories Power ON Status 494 // 495 uint32_t ui32DSP1MemStatus; 496 497 // 498 //! VRSTATUS - Voltage Regulators status 499 // 500 uint32_t ui32VRStatus; 501 502 // 503 //! ADCSTATUS - Power Status Register for ADC Block 504 // 505 uint32_t ui32ADC; 506 507 // 508 //! AUDADCSTATUS - Power Status Register for audio ADC Block 509 // 510 uint32_t ui32AudioADC; 511 } am_hal_pwrctrl_status_t; 512 513 //***************************************************************************** 514 // 515 //! @name Default configurations 516 //! @{ 517 // 518 //***************************************************************************** 519 extern const am_hal_pwrctrl_mcu_memory_config_t g_DefaultMcuMemCfg; 520 extern const am_hal_pwrctrl_sram_memcfg_t g_DefaultSRAMCfg; 521 extern const am_hal_pwrctrl_dsp_memory_config_t g_DefaultDSPMemCfg; 522 //! @} 523 524 // **************************************************************************** 525 // 526 //! @brief Return the current MCU performance mode. 527 //! 528 //! @param peCurrentPowerMode is a ptr to a variable to save the current status. 529 //! 530 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors. 531 // 532 // **************************************************************************** 533 extern uint32_t am_hal_pwrctrl_mcu_mode_status(am_hal_pwrctrl_mcu_mode_e *peCurrentPowerMode); 534 535 //***************************************************************************** 536 // 537 //! @brief Change the MCU performance mode. 538 //! 539 //! @param ePowerMode is the performance mode for the MCU 540 //! 541 //! Select the power mode for the MCU. 542 //! 543 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors. 544 // 545 //***************************************************************************** 546 extern uint32_t am_hal_pwrctrl_mcu_mode_select(am_hal_pwrctrl_mcu_mode_e ePowerMode); 547 548 //***************************************************************************** 549 // 550 //! @brief Configure the power settings for the MCU memory. 551 //! 552 //! @param psConfig is a structure describing the desired memory configuration. 553 //! 554 //! Use this function to enable, disable, or change the sleep configuration of 555 //! MCU memory. 556 //! 557 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 558 // 559 //***************************************************************************** 560 extern uint32_t am_hal_pwrctrl_mcu_memory_config(am_hal_pwrctrl_mcu_memory_config_t *psConfig); 561 562 //***************************************************************************** 563 // 564 //! @brief Read the power settings for the MCU memory. 565 //! 566 //! @param psConfig is a structure describing the desired memory configuration. 567 //! 568 //! Use this function to check the current settings for the MCU memories. 569 //! 570 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 571 // 572 //***************************************************************************** 573 extern uint32_t am_hal_pwrctrl_mcu_memory_config_get(am_hal_pwrctrl_mcu_memory_config_t *psConfig); 574 575 //***************************************************************************** 576 // 577 //! @brief Configure the power settings for the Shared RAM. 578 //! 579 //! @param psConfig is a structure describing the desired memory configuration. 580 //! 581 //! Use this function to enable, disable, or change the sleep configuration of 582 //! MCU memory. 583 //! 584 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 585 // 586 //***************************************************************************** 587 extern uint32_t am_hal_pwrctrl_sram_config(am_hal_pwrctrl_sram_memcfg_t *psConfig); 588 589 //***************************************************************************** 590 // 591 //! @brief Get the power settings for the Shared RAM. 592 //! 593 //! @param psConfig is a structure describing the desired memory configuration. 594 //! 595 //! Use this function to check the current settings for the MCU memories. 596 //! 597 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 598 // 599 //***************************************************************************** 600 extern uint32_t am_hal_pwrctrl_sram_config_get(am_hal_pwrctrl_sram_memcfg_t *psConfig); 601 602 //***************************************************************************** 603 // 604 //! @brief Change the DSP performance mode. 605 //! 606 //! @param eDSP is the instance of the DSP 0 or 1. 607 //! @param ePowerMode is the performance mode for the DSP 608 //! 609 //! Select the power mode for the DSP. 610 //! 611 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 612 // 613 //***************************************************************************** 614 extern uint32_t am_hal_pwrctrl_dsp_mode_select(am_hal_dsp_select_e eDSP, 615 am_hal_pwrctrl_dsp_mode_e ePowerMode); 616 617 //***************************************************************************** 618 // 619 //! @brief Configure the power and memory settings for the DSP. 620 //! 621 //! @param eDSP is the instance of the DSP 0 or 1. 622 //! @param psConfig is a structure containing settings for the DSP 623 //! 624 //! Use this function to configure the DSP. See the documentation for the 625 //! configuration structure for more information on the available settings. 626 //! 627 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 628 // 629 //***************************************************************************** 630 extern uint32_t am_hal_pwrctrl_dsp_memory_config(am_hal_dsp_select_e eDSP, 631 am_hal_pwrctrl_dsp_memory_config_t *psConfig); 632 633 //***************************************************************************** 634 // 635 //! @brief Get the current power and memory settings for the DSP. 636 //! 637 //! @param eDSP is the instance of the DSP 0 or 1. 638 //! @param psConfig is a returns the current settings for the DSP 639 //! 640 //! Use this function to check the current configuration of the DSP. This will 641 //! populate a configuration structure with exactly the same format required by 642 //! the configuration function. 643 //! 644 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 645 // 646 //***************************************************************************** 647 extern uint32_t am_hal_pwrctrl_dsp_memory_config_get(am_hal_dsp_select_e eDSP, 648 am_hal_pwrctrl_dsp_memory_config_t *psConfig); 649 650 //***************************************************************************** 651 // 652 //! @brief Enable power to a peripheral. 653 //! 654 //! @param ePeripheral - The peripheral to enable. 655 //! 656 //! This function enables power to the peripheral and waits for a 657 //! confirmation from the hardware. 658 //! 659 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 660 // 661 //***************************************************************************** 662 extern uint32_t am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral); 663 664 //***************************************************************************** 665 // 666 //! @brief Disable power to a peripheral. 667 //! 668 //! @param ePeripheral - The peripheral to disable. 669 //! 670 //! This function disables power to the peripheral and waits for a 671 //! confirmation from the hardware. 672 //! 673 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 674 // 675 //***************************************************************************** 676 extern uint32_t am_hal_pwrctrl_periph_disable(am_hal_pwrctrl_periph_e ePeripheral); 677 678 //***************************************************************************** 679 // 680 //! @brief Determine whether a peripheral is currently enabled. 681 //! 682 //! @param ePeripheral - The peripheral to enable. 683 //! @param bEnabled - Pointer to a ui32 that will return as 1 or 0. 684 //! 685 //! This function determines to the caller whether a given peripheral is 686 //! currently enabled or disabled. 687 //! 688 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 689 // 690 //***************************************************************************** 691 extern uint32_t am_hal_pwrctrl_periph_enabled(am_hal_pwrctrl_periph_e ePeripheral, 692 bool *bEnabled); 693 694 //***************************************************************************** 695 // 696 //! @brief Get the current powercontrol status registers. 697 //! 698 //! @param psStatus returns a structure containing power status information. 699 //! 700 //! This function can be used to determine the current status of a wide variety 701 //! of system components. 702 //! 703 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 704 // 705 //***************************************************************************** 706 extern uint32_t am_hal_pwrctrl_status_get(am_hal_pwrctrl_status_t *psStatus); 707 708 //***************************************************************************** 709 // 710 //! @brief Initialize system for low power configuration. 711 //! 712 //! This function implements various low power initialization and optimizations. 713 //! - See also am_hal_pwrctrl_control() for other power saving techniques. 714 //! 715 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 716 // 717 //***************************************************************************** 718 extern uint32_t am_hal_pwrctrl_low_power_init(void); 719 720 //***************************************************************************** 721 // 722 //! @brief Miscellaneous power saving controls 723 //! 724 //! @param eControl - Power saving type, one of the following: 725 //! AM_HAL_PWRCTRL_CONTROL_SIMOBUCK_INIT - Enable the SIMOBUCK 726 //! AM_HAL_PWRCTRL_CONTROL_XTAL_PWDN_DEEPSLEEP - Allow the crystal to power 727 //! down during deepsleep 728 //! 729 //! @param pArgs - Pointer to arguments for Control Switch Case 730 //! 731 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 732 // 733 //***************************************************************************** 734 extern uint32_t am_hal_pwrctrl_control(am_hal_pwrctrl_control_e eControl, void *pArgs); 735 736 //***************************************************************************** 737 // 738 //! @brief Restore original Power settings 739 //! 740 //! This function restores default power trims reverting relative 741 //! changes done as part of low_power_init and SIMOBUCK init. 742 //! User needs to make sure device is running in Low Power mode before calling 743 //! this function. 744 //! 745 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 746 // 747 //***************************************************************************** 748 extern uint32_t am_hal_pwrctrl_settings_restore(void); 749 750 #if AM_HAL_TEMPCO_LP 751 //***************************************************************************** 752 // 753 //! @brief Initialize the TempCo workaround. 754 //! 755 //! @param pADCHandle - Pointer to ADC Handle 756 //! @param ui32ADCslot - ADc Slot to initialize 757 //! 758 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 759 // 760 //***************************************************************************** 761 extern uint32_t am_hal_pwrctrl_tempco_init(void *pADCHandle, 762 uint32_t ui32ADCslot); 763 764 // **************************************************************************** 765 // 766 //! @brief This function to be called from the ADC or timer ISR. 767 //! 768 //! @param ui32NumSamples - Number of sSamples to process 769 //! @param sSamples - Array of ADC Samples 770 //! 771 //! @return AM_HAL_STATUS_SUCCESS or applicable PWRCTRL errors 772 // 773 // **************************************************************************** 774 extern uint32_t am_hal_pwrctrl_tempco_sample_handler(uint32_t ui32NumSamples, 775 am_hal_adc_sample_t sSamples[]); 776 #endif // AM_HAL_TEMPCO_LP 777 778 #ifdef __cplusplus 779 } 780 #endif 781 782 #endif // AM_HAL_PWRCTRL_H 783 784 //***************************************************************************** 785 // 786 // End Doxygen group. 787 //! @} 788 // 789 //***************************************************************************** 790 791
