1 #ifndef __NIOS2_H__ 2 #define __NIOS2_H__ 3 4 /****************************************************************************** 5 * * 6 * License Agreement * 7 * * 8 * Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * 9 * All rights reserved. * 10 * * 11 * Permission is hereby granted, free of charge, to any person obtaining a * 12 * copy of this software and associated documentation files (the "Software"), * 13 * to deal in the Software without restriction, including without limitation * 14 * the rights to use, copy, modify, merge, publish, distribute, sublicense, * 15 * and/or sell copies of the Software, and to permit persons to whom the * 16 * Software is furnished to do so, subject to the following conditions: * 17 * * 18 * The above copyright notice and this permission notice shall be included in * 19 * all copies or substantial portions of the Software. * 20 * * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * 24 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * 26 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * 27 * DEALINGS IN THE SOFTWARE. * 28 * * 29 * * 30 ******************************************************************************/ 31 32 /* 33 * This header provides processor specific macros for accessing the Nios2 34 * control registers. 35 */ 36 37 #ifdef __cplusplus 38 extern "C" 39 { 40 #endif /* __cplusplus */ 41 42 /* 43 * Number of available IRQs in internal interrupt controller. 44 */ 45 #define NIOS2_NIRQ 32 46 47 /* 48 * Macros for accessing select Nios II general-purpose registers. 49 */ 50 51 /* ET (Exception Temporary) register */ 52 #define NIOS2_READ_ET(et) \ 53 do { __asm ("mov %0, et" : "=r" (et) ); } while (0) 54 55 #define NIOS2_WRITE_ET(et) \ 56 do { __asm volatile ("mov et, %z0" : : "rM" (et)); } while (0) 57 58 /* SP (Stack Pointer) register */ 59 #define NIOS2_READ_SP(sp) \ 60 do { __asm ("mov %0, sp" : "=r" (sp) ); } while (0) 61 62 /* 63 * Macros for useful processor instructions. 64 */ 65 #define NIOS2_BREAK() \ 66 do { __asm volatile ("break"); } while (0) 67 68 #define NIOS2_REPORT_STACK_OVERFLOW() \ 69 do { __asm volatile("break 3"); } while (0) 70 71 /* 72 * Macros for accessing Nios II control registers. 73 */ 74 #define NIOS2_READ_STATUS(dest) \ 75 do { dest = __builtin_rdctl(0); } while (0) 76 77 #define NIOS2_WRITE_STATUS(src) \ 78 do { __builtin_wrctl(0, src); } while (0) 79 80 #define NIOS2_READ_ESTATUS(dest) \ 81 do { dest = __builtin_rdctl(1); } while (0) 82 83 #define NIOS2_READ_BSTATUS(dest) \ 84 do { dest = __builtin_rdctl(2); } while (0) 85 86 #define NIOS2_READ_IENABLE(dest) \ 87 do { dest = __builtin_rdctl(3); } while (0) 88 89 #define NIOS2_WRITE_IENABLE(src) \ 90 do { __builtin_wrctl(3, src); } while (0) 91 92 #define NIOS2_READ_IPENDING(dest) \ 93 do { dest = __builtin_rdctl(4); } while (0) 94 95 #define NIOS2_READ_CPUID(dest) \ 96 do { dest = __builtin_rdctl(5); } while (0) 97 98 #define NIOS2_READ_EXCEPTION(dest) \ 99 do { dest = __builtin_rdctl(7); } while (0) 100 101 #define NIOS2_READ_PTEADDR(dest) \ 102 do { dest = __builtin_rdctl(8); } while (0) 103 104 #define NIOS2_WRITE_PTEADDR(src) \ 105 do { __builtin_wrctl(8, src); } while (0) 106 107 #define NIOS2_READ_TLBACC(dest) \ 108 do { dest = __builtin_rdctl(9); } while (0) 109 110 #define NIOS2_WRITE_TLBACC(src) \ 111 do { __builtin_wrctl(9, src); } while (0) 112 113 #define NIOS2_READ_TLBMISC(dest) \ 114 do { dest = __builtin_rdctl(10); } while (0) 115 116 #define NIOS2_WRITE_TLBMISC(src) \ 117 do { __builtin_wrctl(10, src); } while (0) 118 119 #define NIOS2_READ_ECCINJ(dest) \ 120 do { dest = __builtin_rdctl(11); } while (0) 121 122 #define NIOS2_WRITE_ECCINJ(src) \ 123 do { __builtin_wrctl(11, src); } while (0) 124 125 #define NIOS2_READ_BADADDR(dest) \ 126 do { dest = __builtin_rdctl(12); } while (0) 127 128 #define NIOS2_WRITE_CONFIG(src) \ 129 do { __builtin_wrctl(13, src); } while (0) 130 131 #define NIOS2_READ_CONFIG(dest) \ 132 do { dest = __builtin_rdctl(13); } while (0) 133 134 #define NIOS2_WRITE_MPUBASE(src) \ 135 do { __builtin_wrctl(14, src); } while (0) 136 137 #define NIOS2_READ_MPUBASE(dest) \ 138 do { dest = __builtin_rdctl(14); } while (0) 139 140 #define NIOS2_WRITE_MPUACC(src) \ 141 do { __builtin_wrctl(15, src); } while (0) 142 143 #define NIOS2_READ_MPUACC(dest) \ 144 do { dest = __builtin_rdctl(15); } while (0) 145 146 /* 147 * Nios II control registers that are always present 148 */ 149 #define NIOS2_STATUS status 150 #define NIOS2_ESTATUS estatus 151 #define NIOS2_BSTATUS bstatus 152 #define NIOS2_IENABLE ienable 153 #define NIOS2_IPENDING ipending 154 #define NIOS2_CPUID cpuid 155 156 /* 157 * Bit masks & offsets for Nios II control registers. 158 * The presence and size of a field is sometimes dependent on the Nios II 159 * configuration. Bit masks for every possible field and the maximum size of 160 * that field are defined. 161 * 162 * All bit-masks are expressed relative to the position 163 * of the data with a register. To read data that is LSB- 164 * aligned, the register read data should be masked, then 165 * right-shifted by the designated "OFST" macro value. The 166 * opposite should be used for register writes when starting 167 * with LSB-aligned data. 168 */ 169 170 /* STATUS, ESTATUS, BSTATUS, and SSTATUS registers */ 171 #define NIOS2_STATUS_PIE_MSK (0x00000001) 172 #define NIOS2_STATUS_PIE_OFST (0) 173 #define NIOS2_STATUS_U_MSK (0x00000002) 174 #define NIOS2_STATUS_U_OFST (1) 175 #define NIOS2_STATUS_EH_MSK (0x00000004) 176 #define NIOS2_STATUS_EH_OFST (2) 177 #define NIOS2_STATUS_IH_MSK (0x00000008) 178 #define NIOS2_STATUS_IH_OFST (3) 179 #define NIOS2_STATUS_IL_MSK (0x000003f0) 180 #define NIOS2_STATUS_IL_OFST (4) 181 #define NIOS2_STATUS_CRS_MSK (0x0000fc00) 182 #define NIOS2_STATUS_CRS_OFST (10) 183 #define NIOS2_STATUS_PRS_MSK (0x003f0000) 184 #define NIOS2_STATUS_PRS_OFST (16) 185 #define NIOS2_STATUS_NMI_MSK (0x00400000) 186 #define NIOS2_STATUS_NMI_OFST (22) 187 #define NIOS2_STATUS_RSIE_MSK (0x00800000) 188 #define NIOS2_STATUS_RSIE_OFST (23) 189 #define NIOS2_STATUS_SRS_MSK (0x80000000) 190 #define NIOS2_STATUS_SRS_OFST (31) 191 192 /* EXCEPTION register */ 193 #define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c) 194 #define NIOS2_EXCEPTION_REG_CAUSE_OFST (2) 195 #define NIOS2_EXCEPTION_REG_ECCFTL_MASK (0x80000000) 196 #define NIOS2_EXCEPTION_REG_ECCFTL_OFST (31) 197 198 /* PTEADDR (Page Table Entry Address) register */ 199 #define NIOS2_PTEADDR_REG_VPN_OFST 2 200 #define NIOS2_PTEADDR_REG_VPN_MASK 0x3ffffc 201 #define NIOS2_PTEADDR_REG_PTBASE_OFST 22 202 #define NIOS2_PTEADDR_REG_PTBASE_MASK 0xffc00000 203 204 /* TLBACC (TLB Access) register */ 205 #define NIOS2_TLBACC_REG_PFN_OFST 0 206 #define NIOS2_TLBACC_REG_PFN_MASK 0xfffff 207 #define NIOS2_TLBACC_REG_G_OFST 20 208 #define NIOS2_TLBACC_REG_G_MASK 0x100000 209 #define NIOS2_TLBACC_REG_X_OFST 21 210 #define NIOS2_TLBACC_REG_X_MASK 0x200000 211 #define NIOS2_TLBACC_REG_W_OFST 22 212 #define NIOS2_TLBACC_REG_W_MASK 0x400000 213 #define NIOS2_TLBACC_REG_R_OFST 23 214 #define NIOS2_TLBACC_REG_R_MASK 0x800000 215 #define NIOS2_TLBACC_REG_C_OFST 24 216 #define NIOS2_TLBACC_REG_C_MASK 0x1000000 217 #define NIOS2_TLBACC_REG_IG_OFST 25 218 #define NIOS2_TLBACC_REG_IG_MASK 0xfe000000 219 220 /* TLBMISC (TLB Miscellaneous) register */ 221 #define NIOS2_TLBMISC_REG_D_OFST 0 222 #define NIOS2_TLBMISC_REG_D_MASK 0x1 223 #define NIOS2_TLBMISC_REG_PERM_OFST 1 224 #define NIOS2_TLBMISC_REG_PERM_MASK 0x2 225 #define NIOS2_TLBMISC_REG_BAD_OFST 2 226 #define NIOS2_TLBMISC_REG_BAD_MASK 0x4 227 #define NIOS2_TLBMISC_REG_DBL_OFST 3 228 #define NIOS2_TLBMISC_REG_DBL_MASK 0x8 229 #define NIOS2_TLBMISC_REG_PID_OFST 4 230 #define NIOS2_TLBMISC_REG_PID_MASK 0x3fff0 231 #define NIOS2_TLBMISC_REG_WE_OFST 18 232 #define NIOS2_TLBMISC_REG_WE_MASK 0x40000 233 #define NIOS2_TLBMISC_REG_RD_OFST 19 234 #define NIOS2_TLBMISC_REG_RD_MASK 0x80000 235 #define NIOS2_TLBMISC_REG_WAY_OFST 20 236 #define NIOS2_TLBMISC_REG_WAY_MASK 0xf00000 237 #define NIOS2_TLBMISC_REG_EE_OFST 24 238 #define NIOS2_TLBMISC_REG_EE_MASK 0x1000000 239 240 /* ECCINJ (ECC Inject) register */ 241 #define NIOS2_ECCINJ_REG_RF_OFST 0 242 #define NIOS2_ECCINJ_REG_RF_MASK 0x3 243 #define NIOS2_ECCINJ_REG_ICTAG_OFST 2 244 #define NIOS2_ECCINJ_REG_ICTAG_MASK 0xc 245 #define NIOS2_ECCINJ_REG_ICDAT_OFST 4 246 #define NIOS2_ECCINJ_REG_ICDAT_MASK 0x30 247 #define NIOS2_ECCINJ_REG_DCTAG_OFST 6 248 #define NIOS2_ECCINJ_REG_DCTAG_MASK 0xc0 249 #define NIOS2_ECCINJ_REG_DCDAT_OFST 8 250 #define NIOS2_ECCINJ_REG_DCDAT_MASK 0x300 251 #define NIOS2_ECCINJ_REG_TLB_OFST 10 252 #define NIOS2_ECCINJ_REG_TLB_MASK 0xc00 253 #define NIOS2_ECCINJ_REG_DTCM0_OFST 12 254 #define NIOS2_ECCINJ_REG_DTCM0_MASK 0x3000 255 #define NIOS2_ECCINJ_REG_DTCM1_OFST 14 256 #define NIOS2_ECCINJ_REG_DTCM1_MASK 0xc000 257 #define NIOS2_ECCINJ_REG_DTCM2_OFST 16 258 #define NIOS2_ECCINJ_REG_DTCM2_MASK 0x30000 259 #define NIOS2_ECCINJ_REG_DTCM3_OFST 18 260 #define NIOS2_ECCINJ_REG_DTCM3_MASK 0xc0000 261 262 /* CONFIG register */ 263 #define NIOS2_CONFIG_REG_PE_MASK (0x00000001) 264 #define NIOS2_CONFIG_REG_PE_OFST (0) 265 #define NIOS2_CONFIG_REG_ANI_MASK (0x00000002) 266 #define NIOS2_CONFIG_REG_ANI_OFST (1) 267 #define NIOS2_CONFIG_REG_ECCEN_MASK (0x00000004) 268 #define NIOS2_CONFIG_REG_ECCEN_OFST (2) 269 #define NIOS2_CONFIG_REG_ECCEXC_MASK (0x00000008) 270 #define NIOS2_CONFIG_REG_ECCEXC_OFST (3) 271 272 /* MPUBASE (MPU Base Address) Register */ 273 #define NIOS2_MPUBASE_D_MASK (0x00000001) 274 #define NIOS2_MPUBASE_D_OFST (0) 275 #define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) 276 #define NIOS2_MPUBASE_INDEX_OFST (1) 277 #define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0) 278 #define NIOS2_MPUBASE_BASE_ADDR_OFST (6) 279 280 /* MPUACC (MPU Access) Register */ 281 #define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) 282 #define NIOS2_MPUACC_LIMIT_OFST (6) 283 #define NIOS2_MPUACC_MASK_MASK (0xffffffc0) 284 #define NIOS2_MPUACC_MASK_OFST (6) 285 #define NIOS2_MPUACC_C_MASK (0x00000020) 286 #define NIOS2_MPUACC_C_OFST (5) 287 #define NIOS2_MPUACC_PERM_MASK (0x0000001c) 288 #define NIOS2_MPUACC_PERM_OFST (2) 289 #define NIOS2_MPUACC_RD_MASK (0x00000002) 290 #define NIOS2_MPUACC_RD_OFST (1) 291 #define NIOS2_MPUACC_WR_MASK (0x00000001) 292 #define NIOS2_MPUACC_WR_OFST (0) 293 294 #ifdef __cplusplus 295 } 296 #endif /* __cplusplus */ 297 298 #endif /* __NIOS2_H__ */ 299
