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Searched refs:ctrl (Results 1 – 25 of 291) sorted by relevance

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/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/QDEC/
Dqdec_reva.c45 qdec->ctrl &= ~MXC_F_QDEC_REVA_CTRL_EN; in MXC_QDEC_RevA_Init()
48 qdec->ctrl |= ((req->mode << MXC_F_QDEC_REVA_CTRL_MODE_POS) & MXC_F_QDEC_REVA_CTRL_MODE); in MXC_QDEC_RevA_Init()
52 qdec->ctrl |= MXC_F_QDEC_REVA_CTRL_SWAP; in MXC_QDEC_RevA_Init()
54 qdec->ctrl &= ~MXC_F_QDEC_REVA_CTRL_SWAP; in MXC_QDEC_RevA_Init()
58 qdec->ctrl |= ((req->sticky << MXC_F_QDEC_REVA_CTRL_STICKY_POS) & MXC_F_QDEC_REVA_CTRL_STICKY); in MXC_QDEC_RevA_Init()
60 qdec->ctrl |= ((req->clkdiv << MXC_F_QDEC_REVA_CTRL_PSC_POS) & MXC_F_QDEC_REVA_CTRL_PSC); in MXC_QDEC_RevA_Init()
66 qdec->ctrl &= ~(MXC_F_QDEC_REVA_CTRL_RST_MAXCNT | MXC_F_QDEC_REVA_CTRL_RST_INDEX); in MXC_QDEC_RevA_Init()
70 qdec->ctrl |= MXC_F_QDEC_REVA_CTRL_RST_MAXCNT; in MXC_QDEC_RevA_Init()
78 qdec->ctrl |= MXC_F_QDEC_REVA_CTRL_RST_INDEX; in MXC_QDEC_RevA_Init()
107 qdec->ctrl |= MXC_F_QDEC_REVA_CTRL_EN; in MXC_QDEC_RevA_Init()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/WDT/
Dwdt_reva.c33 MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVA_CTRL_INT_PERIOD, period); in MXC_WDT_RevA_SetIntPeriod()
38 MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVA_CTRL_RST_PERIOD, in MXC_WDT_RevA_SetResetPeriod()
45 wdt->ctrl |= MXC_F_WDT_REVA_CTRL_WDT_EN; in MXC_WDT_RevA_Enable()
50 wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_WDT_EN); in MXC_WDT_RevA_Disable()
56 wdt->ctrl |= MXC_F_WDT_REVA_CTRL_INT_EN; in MXC_WDT_RevA_EnableInt()
58 wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_INT_EN); in MXC_WDT_RevA_EnableInt()
65 wdt->ctrl |= MXC_F_WDT_REVA_CTRL_RST_EN; in MXC_WDT_RevA_EnableReset()
67 wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_RST_EN); in MXC_WDT_RevA_EnableReset()
79 return !!(wdt->ctrl & MXC_F_WDT_REVA_CTRL_RST_FLAG); in MXC_WDT_RevA_GetResetFlag()
84 wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_RST_FLAG); in MXC_WDT_RevA_ClearResetFlag()
[all …]
Dwdt_revb.c40 wdt->ctrl |= MXC_F_WDT_REVB_CTRL_WIN_EN; in MXC_WDT_RevB_Init()
42 wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_WIN_EN); in MXC_WDT_RevB_Init()
50 MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_INT_LATE_VAL, cfg->upperIntPeriod); in MXC_WDT_RevB_SetIntPeriod()
53 MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_INT_EARLY_VAL, in MXC_WDT_RevB_SetIntPeriod()
60 MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_RST_LATE_VAL, in MXC_WDT_RevB_SetResetPeriod()
64 MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVB_CTRL_RST_EARLY_VAL, in MXC_WDT_RevB_SetResetPeriod()
73 wdt->ctrl |= MXC_F_WDT_REVB_CTRL_EN; // Direct write chips in MXC_WDT_RevB_Enable()
80 wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_EN); // Direct write chips in MXC_WDT_RevB_Disable()
86 wdt->ctrl |= MXC_F_WDT_REVB_CTRL_WDT_INT_EN; in MXC_WDT_RevB_EnableInt()
88 wdt->ctrl &= ~(MXC_F_WDT_REVB_CTRL_WDT_INT_EN); in MXC_WDT_RevB_EnableInt()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/RTC/
Drtc_reva.c63 rtc->ctrl |= mask; in MXC_RTC_RevA_EnableInt()
86 rtc->ctrl &= ~mask; in MXC_RTC_RevA_DisableInt()
127 rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers in MXC_RTC_RevA_Start()
132 rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1 in MXC_RTC_RevA_Start()
136 rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... in MXC_RTC_RevA_Start()
147 rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers in MXC_RTC_RevA_Stop()
152 rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0 in MXC_RTC_RevA_Stop()
156 rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... in MXC_RTC_RevA_Stop()
167 rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes in MXC_RTC_RevA_Init()
171 rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register in MXC_RTC_RevA_Init()
[all …]
Drtc_me11.c109 MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SSEC register in MXC_RTC_GetSubSecond()
110 while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} in MXC_RTC_GetSubSecond()
117 MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SEC register in MXC_RTC_GetSecond()
118 while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} in MXC_RTC_GetSecond()
125 MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SSEC register in MXC_RTC_GetSubSeconds()
126 while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} in MXC_RTC_GetSubSeconds()
133 MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SEC register in MXC_RTC_GetSeconds()
134 while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} in MXC_RTC_GetSeconds()
Drtc_me16.c105 MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SSEC register in MXC_RTC_GetSubSeconds()
106 while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} in MXC_RTC_GetSubSeconds()
113 MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SEC register in MXC_RTC_GetSeconds()
114 while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} in MXC_RTC_GetSeconds()
Drtc_me55.c66 MXC_MCR->ctrl |= MXC_F_MCR_CLKCTRL_ERTCO_EN; in MXC_RTC_Init()
113 MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SSEC register in MXC_RTC_GetSubSeconds()
114 while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} in MXC_RTC_GetSubSeconds()
121 MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SEC register in MXC_RTC_GetSeconds()
122 while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} in MXC_RTC_GetSeconds()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/CAMERAIF/
Dcameraif_reva.c46 cameraif->ctrl &= ~(MXC_F_CAMERAIF_REVA_CTRL_DATA_WIDTH); in MXC_PCIF_RevA_SetDatawidth()
47 cameraif->ctrl |= (datawith << MXC_F_CAMERAIF_REVA_CTRL_DATA_WIDTH_POS); in MXC_PCIF_RevA_SetDatawidth()
53 cameraif->ctrl &= ~(MXC_F_CAMERAIF_REVA_CTRL_DS_TIMING_EN); in MXC_PCIF_RevA_SetTimingSel()
54 cameraif->ctrl |= (timingsel << MXC_F_CAMERAIF_REVA_CTRL_DS_TIMING_EN_POS); in MXC_PCIF_RevA_SetTimingSel()
59 cameraif->ctrl &= ~(MXC_F_CAMERAIF_REVA_CTRL_FIFO_THRSH); in MXC_PCIF_RevA_SetThreshold()
60 cameraif->ctrl |= ((fifo_thrsh << MXC_F_CAMERAIF_REVA_CTRL_FIFO_THRSH_POS) & in MXC_PCIF_RevA_SetThreshold()
76 cameraif->ctrl &= ~(MXC_F_CAMERAIF_REVA_CTRL_READ_MODE); in MXC_PCIF_RevA_Start()
77 cameraif->ctrl |= (readmode & MXC_F_CAMERAIF_REVA_CTRL_READ_MODE); in MXC_PCIF_RevA_Start()
82 cameraif->ctrl &= ~(MXC_F_CAMERAIF_REVA_CTRL_READ_MODE); in MXC_PCIF_RevA_Stop()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/ADC/
Dadc_reva.c62 adc->ctrl |= MXC_F_ADC_REVA_CTRL_PWR; in MXC_ADC_RevA_Init()
64 adc->ctrl |= MXC_F_ADC_REVA_CTRL_REFBUF_PWR; in MXC_ADC_RevA_Init()
87 adc->ctrl &= ~MXC_F_ADC_REVA_CTRL_PWR; in MXC_ADC_RevA_Shutdown()
89 adc->ctrl &= ~MXC_F_ADC_REVA_CTRL_REFBUF_PWR; in MXC_ADC_RevA_Shutdown()
91 adc->ctrl &= ~MXC_F_ADC_REVA_CTRL_CLK_EN; in MXC_ADC_RevA_Shutdown()
140 adc->ctrl |= MXC_F_ADC_REVA_CTRL_CLK_EN; in MXC_ADC_RevA_SetConversionSpeed()
153 adc->ctrl |= MXC_F_ADC_REVA_CTRL_DATA_ALIGN; in MXC_ADC_RevA_SetDataAlignment()
155 adc->ctrl &= ~MXC_F_ADC_REVA_CTRL_DATA_ALIGN; in MXC_ADC_RevA_SetDataAlignment()
162 adc->ctrl &= ~(MXC_S_ADC_REVA_CTRL_ADC_DIVSEL_DIV4); in MXC_ADC_RevA_SetExtScale()
166 adc->ctrl |= MXC_F_ADC_REVA_CTRL_REF_SCALE; in MXC_ADC_RevA_SetExtScale()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/HTMR/
Dhtmr_reva.c36 #define ASYNC_MODE (MXC_F_HTMR_REVA_CTRL_ACRE & htmr->ctrl)
54 htmr->ctrl = MXC_F_HTMR_REVA_CTRL_WE; // Allow Writes in MXC_HTMR_RevA_Init()
60 htmr->ctrl = HTMR_CTRL_RESET_DEFAULT; // Start with a Clean Register in MXC_HTMR_RevA_Init()
66 htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_WE; // Set Write Enable, allow writing to reg. in MXC_HTMR_RevA_Init()
87 htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_ACRE; in MXC_HTMR_RevA_Init()
90 htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_WE; // Prevent Writing... in MXC_HTMR_RevA_Init()
105 htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_WE; // Allow writing to registers in MXC_HTMR_RevA_Start()
112 htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_HTEN; // setting RTCE = 1 in MXC_HTMR_RevA_Start()
118 htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_WE; // Prevent Writing... in MXC_HTMR_RevA_Start()
133 htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_WE; // Allow writing to registers in MXC_HTMR_RevA_Stop()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/EMCC/
Demcc_reva.c53 emcc->ctrl |= MXC_F_EMCC_REVA_CTRL_EN; in MXC_EMCC_RevA_Enable()
58 emcc->ctrl &= ~MXC_F_EMCC_REVA_CTRL_EN; in MXC_EMCC_RevA_Disable()
63 emcc->ctrl |= MXC_F_EMCC_REVA_CTRL_WRITE_ALLOC; in MXC_EMCC_RevA_WriteAllocateEnable()
68 emcc->ctrl &= ~MXC_F_EMCC_REVA_CTRL_WRITE_ALLOC; in MXC_EMCC_RevA_WriteAllocateDisable()
73 emcc->ctrl |= MXC_F_EMCC_REVA_CTRL_CWFST_DIS; in MXC_EMCC_RevA_CriticalWordFirstEnable()
78 emcc->ctrl &= ~MXC_F_EMCC_REVA_CTRL_CWFST_DIS; in MXC_EMCC_RevA_CriticalWordFirstDisable()
83 return (emcc->ctrl & MXC_F_EMCC_REVA_CTRL_RDY) >> MXC_F_EMCC_REVA_CTRL_RDY_POS; in MXC_EMCC_RevA_Ready()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/CRC/
Dcrc_reva.c43 crc->ctrl = 0x00; in MXC_CRC_RevA_Init()
50 crc->ctrl &= ~MXC_F_CRC_REVA_CTRL_EN; in MXC_CRC_RevA_Shutdown()
72 MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_MSB, bitOrder << MXC_F_CRC_REVA_CTRL_MSB_POS); in MXC_CRC_RevA_SetDirection()
77 return !!(crc->ctrl & MXC_F_CRC_REVA_CTRL_MSB); in MXC_CRC_RevA_GetDirection()
82 MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_IN, in MXC_CRC_RevA_SwapDataIn()
88 MXC_SETFIELD(crc->ctrl, MXC_F_CRC_REVA_CTRL_BYTE_SWAP_OUT, in MXC_CRC_RevA_SwapDataOut()
128 crc->ctrl |= MXC_F_CRC_REVA_CTRL_EN; in MXC_CRC_RevA_Compute()
134 while (crc->ctrl & MXC_F_CRC_REVA_CTRL_BUSY) {} in MXC_CRC_RevA_Compute()
181 MXC_CRC->ctrl |= MXC_F_CRC_CTRL_DMA_EN; in MXC_CRC_RevA_ComputeAsync()
182 MXC_CRC->ctrl |= MXC_F_CRC_CTRL_EN; in MXC_CRC_RevA_ComputeAsync()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/TRNG/
Dtrng_reva.c53 trng->ctrl |= MXC_F_TRNG_REVA_CTRL_RNG_IE; in MXC_TRNG_RevA_EnableInt()
58 trng->ctrl &= ~MXC_F_TRNG_REVA_CTRL_RNG_IE; in MXC_TRNG_RevA_DisableInt()
73 trng->ctrl &= ~MXC_F_TRNG_REVA_CTRL_RNG_IE; in MXC_TRNG_RevA_Handler()
76 trng->ctrl |= MXC_S_TRNG_REVA_CTRL_RNG_ISC_CLEAR; in MXC_TRNG_RevA_Handler()
105 while (!(trng->ctrl & MXC_S_TRNG_REVA_CTRL_RNG_IS_READY)) {} in MXC_TRNG_RevA_RandomInt()
146 trng->ctrl |= MXC_F_TRNG_REVA_CTRL_RNG_IE; in MXC_TRNG_RevA_RandomAsync()
152 trng->ctrl |= MXC_F_TRNG_REVA_CTRL_AESKG; in MXC_TRNG_RevA_GenerateKey()
154 while (trng->ctrl & MXC_F_TRNG_REVA_CTRL_AESKG) {} in MXC_TRNG_RevA_GenerateKey()
Dtrng_revb.c52 trng->ctrl |= MXC_F_TRNG_REVB_CTRL_RND_IE; in MXC_TRNG_RevB_EnableInt()
57 trng->ctrl &= ~MXC_F_TRNG_REVB_CTRL_RND_IE; in MXC_TRNG_RevB_DisableInt()
72 trng->ctrl &= ~MXC_F_TRNG_REVB_CTRL_RND_IE; in MXC_TRNG_RevB_Handler()
138 trng->ctrl |= MXC_F_TRNG_REVB_CTRL_RND_IE; in MXC_TRNG_RevB_RandomAsync()
144 trng->ctrl |= MXC_F_TRNG_REVB_CTRL_AESKG_USR; in MXC_TRNG_RevB_GenerateKey()
153 if (trng->ctrl & MXC_F_TRNG_REVB_CTRL_ODHT) { in MXC_TRNG_RevB_HealthTest()
154 trng->ctrl &= ~MXC_F_TRNG_REVB_CTRL_ODHT; in MXC_TRNG_RevB_HealthTest()
159 trng->ctrl |= MXC_F_TRNG_REVB_CTRL_ODHT; in MXC_TRNG_RevB_HealthTest()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/FLC/
Dflc_reva.c58 return (flc->ctrl & in MXC_busy_flc()
84 flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_UNLOCK) | MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED; in MXC_prepare_flc()
127 flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | in MXC_FLC_RevA_MassErase()
131 flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME; in MXC_FLC_RevA_MassErase()
137 flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; in MXC_FLC_RevA_MassErase()
163 flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | in MXC_FLC_RevA_PageErase()
167 flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE; in MXC_FLC_RevA_PageErase()
173 flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; in MXC_FLC_RevA_PageErase()
214 flc->ctrl |= MXC_F_FLC_REVA_CTRL_WDTH; in MXC_FLC_RevA_Write32()
219 flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR; in MXC_FLC_RevA_Write32()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/CLCD/
Dclcd_reva.c40 clcd->ctrl = 0; in MXC_CLCD_RevA_Init()
63 clcd->ctrl = 0; in MXC_CLCD_RevA_Shutdown()
90 clcd->ctrl |= cfg->bpp; in MXC_CLCD_RevA_ConfigPanel()
101 clcd->ctrl |= MXC_S_CLCD_REVA_CTRL_LCDEN_ENABLE | (8 << MXC_F_CLCD_REVA_CTRL_DISPTYPE_POS) | in MXC_CLCD_RevA_Enable()
110 clcd->ctrl &= (~MXC_S_CLCD_REVA_CTRL_LCDEN_ENABLE); in MXC_CLCD_RevA_Disable()
118 clcd->ctrl &= (~MXC_S_CLCD_REVA_CTRL_LCDEN_ENABLE); in MXC_CLCD_RevA_SetFrameAddr()
120 clcd->ctrl |= (MXC_S_CLCD_REVA_CTRL_LCDEN_ENABLE); in MXC_CLCD_RevA_SetFrameAddr()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/ICC/
Dicc_reva.c38 return (icc->ctrl & MXC_F_ICC_REVA_CTRL_RDY); in MXC_ICC_Ready()
65 icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN; in MXC_ICC_RevA_Enable()
71 icc->ctrl |= MXC_F_ICC_REVA_CTRL_EN; in MXC_ICC_RevA_Enable()
78 icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN; in MXC_ICC_RevA_Disable()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/SFCC/
Dsfcc_reva.c36 return (sfcc->ctrl & MXC_F_SFCC_REVA_CTRL_RDY); in MXC_SFCC_Ready()
63 sfcc->ctrl &= ~MXC_F_SFCC_REVA_CTRL_EN; in MXC_SFCC_RevA_Enable()
69 sfcc->ctrl |= MXC_F_SFCC_REVA_CTRL_EN; in MXC_SFCC_RevA_Enable()
76 sfcc->ctrl &= ~MXC_F_SFCC_REVA_CTRL_EN; in MXC_SFCC_RevA_Disable()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/WUT/
Dwut_reva.c41 wut->ctrl = 0; in MXC_WUT_RevA_Init()
47 wut->ctrl |= pres; in MXC_WUT_RevA_Init()
60 wut->ctrl = 0; in MXC_WUT_RevA_Shutdown()
66 wut->ctrl |= MXC_F_WUT_REVA_CTRL_TEN; in MXC_WUT_RevA_Enable()
72 wut->ctrl &= ~(MXC_F_WUT_REVA_CTRL_TEN); in MXC_WUT_RevA_Disable()
79 uint32_t wut_ctrl = wut->ctrl; in MXC_WUT_RevA_Config()
80 wut->ctrl |= (wut_ctrl & ~(MXC_F_WUT_REVA_CTRL_TMODE | MXC_F_WUT_REVA_CTRL_TPOL)) | in MXC_WUT_RevA_Config()
138 uint32_t wut_ctrl = wut->ctrl; in MXC_WUT_RevA_GetTicks()
184 uint32_t wut_ctrl = wut->ctrl; in MXC_WUT_RevA_GetTime()
263 tmp += (waitMs * (timerClock / (0x1 << ((wut->ctrl & MXC_F_WUT_REVA_CTRL_PRES) >> in MXC_WUT_RevA_Delay_MS()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/TPU/
Dtpu_reva.c70 tpu->ctrl |= MXC_F_TPU_REVA_CTRL_DMA_DONE | MXC_F_TPU_REVA_CTRL_GLS_DONE | in MXC_TPU_RevA_Clear_Done_Flags()
81 tpu->ctrl = MXC_F_TPU_REVA_CTRL_RST; in MXC_TPU_RevA_Reset()
86 tpu->ctrl |= MXC_F_TPU_REVA_CTRL_FLAG_MODE; in MXC_TPU_RevA_Reset()
102 tpu->ctrl |= MXC_S_TPU_REVA_CTRL_RDSRC_DMAORAPB; in MXC_TPU_RevA_CRC_Config()
139 while (!(tpu->ctrl & MXC_F_TPU_REVA_CTRL_DMA_DONE)) {} in MXC_TPU_RevA_CRC()
142 while (!(tpu->ctrl & MXC_F_TPU_REVA_CTRL_GLS_DONE)) {} in MXC_TPU_RevA_CRC()
145 tpu->ctrl |= MXC_F_TPU_REVA_CTRL_GLS_DONE; in MXC_TPU_RevA_CRC()
159 tpu->ctrl |= MXC_F_TPU_REVA_CTRL_DMADNE_MSK; in MXC_TPU_RevA_Ham_Config()
162 tpu->ctrl |= MXC_S_TPU_REVA_CTRL_RDSRC_DMAORAPB; in MXC_TPU_RevA_Ham_Config()
202 while (!(tpu->ctrl & MXC_F_TPU_REVA_CTRL_GLS_DONE)) {} in MXC_TPU_RevA_Ham()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/SPIMSS/
Dspimss_reva.c80 spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start) in MXC_SPIMSS_RevA_Init()
90 spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_CLKPOL)) | in MXC_SPIMSS_RevA_Init()
93 spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_PHASE)) | in MXC_SPIMSS_RevA_Init()
107 spi->ctrl = 0; // Interrupts, SPI transaction all turned off in MXC_SPIMSS_RevA_Shutdown()
139 spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Make sure the Initiation in MXC_SPIMSS_RevA_TransSetup()
164 spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master. in MXC_SPIMSS_RevA_TransSetup()
167 spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave. in MXC_SPIMSS_RevA_TransSetup()
206 if ((spi->ctrl & MXC_F_SPIMSS_REVA_CTRL_MMEN) >> MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) { in MXC_SPIMSS_RevA_Handler()
215 spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE); in MXC_SPIMSS_RevA_Handler()
231 spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI in MXC_SPIMSS_RevA_MasterTrans()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/I2C/
Di2c_reva.c81 i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; in MXC_I2C_RevA_Init()
93 i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE; in MXC_I2C_RevA_Init()
144 i2c->ctrl = 0; in MXC_I2C_RevA_Shutdown()
211 i2c->ctrl |= MXC_F_I2C_REVA_CTRL_HS_EN; in MXC_I2C_RevA_SetFrequency()
246 if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_HS_EN) { in MXC_I2C_RevA_GetFrequency()
279 i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; in MXC_I2C_RevA_SetClockStretching()
281 i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; in MXC_I2C_RevA_SetClockStretching()
293 return !((i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); in MXC_I2C_RevA_GetClockStretching()
336 MXC_SETFIELD(dma->ch[txChannel].ctrl, MXC_F_DMA_REVA_CTRL_SRCWD, in MXC_I2C_RevA_DMA_Init()
338 MXC_SETFIELD(dma->ch[txChannel].ctrl, MXC_F_DMA_REVA_CTRL_DSTWD, in MXC_I2C_RevA_DMA_Init()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/UART/
Duart_reva.c91 uart->ctrl |= MXC_F_UART_REVA_CTRL_ENABLE; in MXC_UART_RevA_Init()
124 if (uart->ctrl & MXC_F_UART_REVA_CTRL_CLKSEL) { in MXC_UART_RevA_SetFrequency()
205 if (uart->ctrl & MXC_F_UART_REVA_CTRL_CLKSEL) { in MXC_UART_RevA_GetFrequency()
241 MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_CHAR_SIZE, dataSize); in MXC_UART_RevA_SetDataSize()
250 MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, in MXC_UART_RevA_SetStopBits()
255 MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, in MXC_UART_RevA_SetStopBits()
271 MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, in MXC_UART_RevA_SetParity()
277 MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, in MXC_UART_RevA_SetParity()
279 MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_EVEN); in MXC_UART_RevA_SetParity()
280 MXC_SETFIELD(uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); in MXC_UART_RevA_SetParity()
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/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/LP/
Dlp_me14.c260 MXC_MCR->ctrl |= MXC_F_MCR_CTRL_USBSWEN_N; in MXC_LP_USBSWLPDisable()
265 MXC_MCR->ctrl &= ~MXC_F_MCR_CTRL_USBSWEN_N; in MXC_LP_USBSWLPEnable()
394 MXC_MCR->ctrl &= ~MXC_F_MCR_CTRL_USBSWEN_N; in MXC_LP_EnableUSBWakeup()
400 MXC_MCR->ctrl |= MXC_F_MCR_CTRL_USBSWEN_N; in MXC_LP_DisableUSBWakeup()
625 MXC_MCR->ctrl |= MXC_F_MCR_CTRL_VDDCSWEN; in MXC_LP_EnterDeepSleepMode()
641 MXC_MCR->ctrl = (MXC_MCR->ctrl & ~(MXC_F_MCR_CTRL_VDDCSW)) | (0x2 << MXC_F_MCR_CTRL_VDDCSW_POS); in MXC_LP_EnterDeepSleepMode()
662 MXC_MCR->ctrl = (MXC_MCR->ctrl & ~(MXC_F_MCR_CTRL_VDDCSW)) | in MXC_LP_EnterDeepSleepMode()
670 if ((MXC_MCR->ctrl & MXC_F_MCR_CTRL_VDDCSW) == (1 << MXC_F_MCR_CTRL_VDDCSW_POS)) { in MXC_LP_EnterDeepSleepMode()
702 MXC_MCR->ctrl |= MXC_F_MCR_CTRL_VDDCSWEN; in MXC_LP_EnterBackupMode()
712 MXC_MCR->ctrl = (MXC_MCR->ctrl & ~(MXC_F_MCR_CTRL_VDDCSW)) | (0x2 << MXC_F_MCR_CTRL_VDDCSW_POS); in MXC_LP_EnterBackupMode()
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/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/AES/
Daes_revb.c64 aes->ctrl = 0x00; in MXC_AES_RevB_Init()
68 aes->ctrl |= MXC_F_AES_REVB_CTRL_EN; in MXC_AES_RevB_Init()
80 aes->ctrl = 0x00; in MXC_AES_RevB_Shutdown()
97 aes->ctrl |= key; in MXC_AES_RevB_SetKeySize()
102 return (aes->ctrl & MXC_F_AES_REVB_CTRL_KEY_SIZE); in MXC_AES_RevB_GetKeySize()
108 aes->ctrl |= MXC_F_AES_REVB_CTRL_INPUT_FLUSH; in MXC_AES_RevB_FlushInputFIFO()
114 aes->ctrl |= MXC_F_AES_REVB_CTRL_OUTPUT_FLUSH; in MXC_AES_RevB_FlushOutputFIFO()
120 aes->ctrl |= MXC_F_AES_REVB_CTRL_START; in MXC_AES_RevB_Start()
172 MXC_SETFIELD(aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, in MXC_AES_RevB_Generic()
348 MXC_SETFIELD(aes->ctrl, MXC_F_AES_REVB_CTRL_TYPE, in MXC_AES_RevB_GenericAsync()
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