1 /** 2 * @file spi_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spi_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPI_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPI_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spi 67 * @defgroup spi_registers SPI_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 69 * @details SPI peripheral. 70 */ 71 72 /** 73 * @ingroup spi_registers 74 * Structure type to access the SPI Registers. 75 */ 76 typedef struct { 77 union { 78 __IO uint32_t fifo32; /**< <tt>\b 0x00:</tt> SPI FIFO32 Register */ 79 __IO uint16_t fifo16[2]; /**< <tt>\b 0x00:</tt> SPI FIFO16 Register */ 80 __IO uint8_t fifo8[4]; /**< <tt>\b 0x00:</tt> SPI FIFO8 Register */ 81 }; 82 __IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */ 83 __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */ 84 __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */ 85 __IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI SS_TIME Register */ 86 __IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI CLK_CFG Register */ 87 __R uint32_t rsv_0x18; 88 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */ 89 __IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI INT_FL Register */ 90 __IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI INT_EN Register */ 91 __IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPI WAKE_FL Register */ 92 __IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPI WAKE_EN Register */ 93 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI STAT Register */ 94 } mxc_spi_regs_t; 95 96 /* Register offsets for module SPI */ 97 /** 98 * @ingroup spi_registers 99 * @defgroup SPI_Register_Offsets Register Offsets 100 * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 105 #define MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_SPI_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_SPI_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */ 112 #define MXC_R_SPI_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */ 113 #define MXC_R_SPI_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */ 114 #define MXC_R_SPI_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */ 115 #define MXC_R_SPI_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */ 116 #define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */ 117 /**@} end of group spi_registers */ 118 119 /** 120 * @ingroup spi_registers 121 * @defgroup SPI_FIFO32 SPI_FIFO32 122 * @brief Register for reading and writing the FIFO. 123 * @{ 124 */ 125 #define MXC_F_SPI_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */ 126 #define MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */ 127 128 /**@} end of group SPI_FIFO32_Register */ 129 130 /** 131 * @ingroup spi_registers 132 * @defgroup SPI_FIFO16 SPI_FIFO16 133 * @brief Register for reading and writing the FIFO. 134 * @{ 135 */ 136 #define MXC_F_SPI_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */ 137 #define MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */ 138 139 /**@} end of group SPI_FIFO16_Register */ 140 141 /** 142 * @ingroup spi_registers 143 * @defgroup SPI_FIFO8 SPI_FIFO8 144 * @brief Register for reading and writing the FIFO. 145 * @{ 146 */ 147 #define MXC_F_SPI_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */ 148 #define MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */ 149 150 /**@} end of group SPI_FIFO8_Register */ 151 152 /** 153 * @ingroup spi_registers 154 * @defgroup SPI_CTRL0 SPI_CTRL0 155 * @brief Register for controlling SPI peripheral. 156 * @{ 157 */ 158 #define MXC_F_SPI_CTRL0_SPI_EN_POS 0 /**< CTRL0_SPI_EN Position */ 159 #define MXC_F_SPI_CTRL0_SPI_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SPI_EN_POS)) /**< CTRL0_SPI_EN Mask */ 160 #define MXC_V_SPI_CTRL0_SPI_EN_DIS ((uint32_t)0x0UL) /**< CTRL0_SPI_EN_DIS Value */ 161 #define MXC_S_SPI_CTRL0_SPI_EN_DIS (MXC_V_SPI_CTRL0_SPI_EN_DIS << MXC_F_SPI_CTRL0_SPI_EN_POS) /**< CTRL0_SPI_EN_DIS Setting */ 162 #define MXC_V_SPI_CTRL0_SPI_EN_EN ((uint32_t)0x1UL) /**< CTRL0_SPI_EN_EN Value */ 163 #define MXC_S_SPI_CTRL0_SPI_EN_EN (MXC_V_SPI_CTRL0_SPI_EN_EN << MXC_F_SPI_CTRL0_SPI_EN_POS) /**< CTRL0_SPI_EN_EN Setting */ 164 165 #define MXC_F_SPI_CTRL0_MM_EN_POS 1 /**< CTRL0_MM_EN Position */ 166 #define MXC_F_SPI_CTRL0_MM_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MM_EN_POS)) /**< CTRL0_MM_EN Mask */ 167 #define MXC_V_SPI_CTRL0_MM_EN_DIS ((uint32_t)0x0UL) /**< CTRL0_MM_EN_DIS Value */ 168 #define MXC_S_SPI_CTRL0_MM_EN_DIS (MXC_V_SPI_CTRL0_MM_EN_DIS << MXC_F_SPI_CTRL0_MM_EN_POS) /**< CTRL0_MM_EN_DIS Setting */ 169 #define MXC_V_SPI_CTRL0_MM_EN_EN ((uint32_t)0x1UL) /**< CTRL0_MM_EN_EN Value */ 170 #define MXC_S_SPI_CTRL0_MM_EN_EN (MXC_V_SPI_CTRL0_MM_EN_EN << MXC_F_SPI_CTRL0_MM_EN_POS) /**< CTRL0_MM_EN_EN Setting */ 171 172 #define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ 173 #define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ 174 #define MXC_V_SPI_CTRL0_SS_IO_OUTPUT ((uint32_t)0x0UL) /**< CTRL0_SS_IO_OUTPUT Value */ 175 #define MXC_S_SPI_CTRL0_SS_IO_OUTPUT (MXC_V_SPI_CTRL0_SS_IO_OUTPUT << MXC_F_SPI_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_OUTPUT Setting */ 176 #define MXC_V_SPI_CTRL0_SS_IO_INPUT ((uint32_t)0x1UL) /**< CTRL0_SS_IO_INPUT Value */ 177 #define MXC_S_SPI_CTRL0_SS_IO_INPUT (MXC_V_SPI_CTRL0_SS_IO_INPUT << MXC_F_SPI_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_INPUT Setting */ 178 179 #define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ 180 #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ 181 #define MXC_V_SPI_CTRL0_START_START ((uint32_t)0x1UL) /**< CTRL0_START_START Value */ 182 #define MXC_S_SPI_CTRL0_START_START (MXC_V_SPI_CTRL0_START_START << MXC_F_SPI_CTRL0_START_POS) /**< CTRL0_START_START Setting */ 183 184 #define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ 185 #define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ 186 #define MXC_V_SPI_CTRL0_SS_CTRL_DEASSERT ((uint32_t)0x0UL) /**< CTRL0_SS_CTRL_DEASSERT Value */ 187 #define MXC_S_SPI_CTRL0_SS_CTRL_DEASSERT (MXC_V_SPI_CTRL0_SS_CTRL_DEASSERT << MXC_F_SPI_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_DEASSERT Setting */ 188 #define MXC_V_SPI_CTRL0_SS_CTRL_ASSERT ((uint32_t)0x1UL) /**< CTRL0_SS_CTRL_ASSERT Value */ 189 #define MXC_S_SPI_CTRL0_SS_CTRL_ASSERT (MXC_V_SPI_CTRL0_SS_CTRL_ASSERT << MXC_F_SPI_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_ASSERT Setting */ 190 191 #define MXC_F_SPI_CTRL0_SS_SEL_POS 16 /**< CTRL0_SS_SEL Position */ 192 #define MXC_F_SPI_CTRL0_SS_SEL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_SEL_POS)) /**< CTRL0_SS_SEL Mask */ 193 #define MXC_V_SPI_CTRL0_SS_SEL_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SEL_SS0 Value */ 194 #define MXC_S_SPI_CTRL0_SS_SEL_SS0 (MXC_V_SPI_CTRL0_SS_SEL_SS0 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS0 Setting */ 195 #define MXC_V_SPI_CTRL0_SS_SEL_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SEL_SS1 Value */ 196 #define MXC_S_SPI_CTRL0_SS_SEL_SS1 (MXC_V_SPI_CTRL0_SS_SEL_SS1 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS1 Setting */ 197 #define MXC_V_SPI_CTRL0_SS_SEL_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SEL_SS2 Value */ 198 #define MXC_S_SPI_CTRL0_SS_SEL_SS2 (MXC_V_SPI_CTRL0_SS_SEL_SS2 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS2 Setting */ 199 #define MXC_V_SPI_CTRL0_SS_SEL_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SEL_SS3 Value */ 200 #define MXC_S_SPI_CTRL0_SS_SEL_SS3 (MXC_V_SPI_CTRL0_SS_SEL_SS3 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS3 Setting */ 201 202 /**@} end of group SPI_CTRL0_Register */ 203 204 /** 205 * @ingroup spi_registers 206 * @defgroup SPI_CTRL1 SPI_CTRL1 207 * @brief Register for controlling SPI peripheral. 208 * @{ 209 */ 210 #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ 211 #define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ 212 213 #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ 214 #define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ 215 216 /**@} end of group SPI_CTRL1_Register */ 217 218 /** 219 * @ingroup spi_registers 220 * @defgroup SPI_CTRL2 SPI_CTRL2 221 * @brief Register for controlling SPI peripheral. 222 * @{ 223 */ 224 #define MXC_F_SPI_CTRL2_CLK_PHA_POS 0 /**< CTRL2_CLK_PHA Position */ 225 #define MXC_F_SPI_CTRL2_CLK_PHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS)) /**< CTRL2_CLK_PHA Mask */ 226 #define MXC_V_SPI_CTRL2_CLK_PHA_RISINGEDGE ((uint32_t)0x0UL) /**< CTRL2_CLK_PHA_RISINGEDGE Value */ 227 #define MXC_S_SPI_CTRL2_CLK_PHA_RISINGEDGE (MXC_V_SPI_CTRL2_CLK_PHA_RISINGEDGE << MXC_F_SPI_CTRL2_CLK_PHA_POS) /**< CTRL2_CLK_PHA_RISINGEDGE Setting */ 228 #define MXC_V_SPI_CTRL2_CLK_PHA_FALLINGEDGE ((uint32_t)0x1UL) /**< CTRL2_CLK_PHA_FALLINGEDGE Value */ 229 #define MXC_S_SPI_CTRL2_CLK_PHA_FALLINGEDGE (MXC_V_SPI_CTRL2_CLK_PHA_FALLINGEDGE << MXC_F_SPI_CTRL2_CLK_PHA_POS) /**< CTRL2_CLK_PHA_FALLINGEDGE Setting */ 230 231 #define MXC_F_SPI_CTRL2_CLK_POL_POS 1 /**< CTRL2_CLK_POL Position */ 232 #define MXC_F_SPI_CTRL2_CLK_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS)) /**< CTRL2_CLK_POL Mask */ 233 #define MXC_V_SPI_CTRL2_CLK_POL_NORMAL ((uint32_t)0x0UL) /**< CTRL2_CLK_POL_NORMAL Value */ 234 #define MXC_S_SPI_CTRL2_CLK_POL_NORMAL (MXC_V_SPI_CTRL2_CLK_POL_NORMAL << MXC_F_SPI_CTRL2_CLK_POL_POS) /**< CTRL2_CLK_POL_NORMAL Setting */ 235 #define MXC_V_SPI_CTRL2_CLK_POL_INVERTED ((uint32_t)0x1UL) /**< CTRL2_CLK_POL_INVERTED Value */ 236 #define MXC_S_SPI_CTRL2_CLK_POL_INVERTED (MXC_V_SPI_CTRL2_CLK_POL_INVERTED << MXC_F_SPI_CTRL2_CLK_POL_POS) /**< CTRL2_CLK_POL_INVERTED Setting */ 237 238 #define MXC_F_SPI_CTRL2_NUM_BITS_POS 8 /**< CTRL2_NUM_BITS Position */ 239 #define MXC_F_SPI_CTRL2_NUM_BITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS)) /**< CTRL2_NUM_BITS Mask */ 240 #define MXC_V_SPI_CTRL2_NUM_BITS_16BITS ((uint32_t)0x0UL) /**< CTRL2_NUM_BITS_16BITS Value */ 241 #define MXC_S_SPI_CTRL2_NUM_BITS_16BITS (MXC_V_SPI_CTRL2_NUM_BITS_16BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_16BITS Setting */ 242 #define MXC_V_SPI_CTRL2_NUM_BITS_1BITS ((uint32_t)0x1UL) /**< CTRL2_NUM_BITS_1BITS Value */ 243 #define MXC_S_SPI_CTRL2_NUM_BITS_1BITS (MXC_V_SPI_CTRL2_NUM_BITS_1BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_1BITS Setting */ 244 #define MXC_V_SPI_CTRL2_NUM_BITS_2BITS ((uint32_t)0x2UL) /**< CTRL2_NUM_BITS_2BITS Value */ 245 #define MXC_S_SPI_CTRL2_NUM_BITS_2BITS (MXC_V_SPI_CTRL2_NUM_BITS_2BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_2BITS Setting */ 246 #define MXC_V_SPI_CTRL2_NUM_BITS_3BITS ((uint32_t)0x3UL) /**< CTRL2_NUM_BITS_3BITS Value */ 247 #define MXC_S_SPI_CTRL2_NUM_BITS_3BITS (MXC_V_SPI_CTRL2_NUM_BITS_3BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_3BITS Setting */ 248 #define MXC_V_SPI_CTRL2_NUM_BITS_4BITS ((uint32_t)0x4UL) /**< CTRL2_NUM_BITS_4BITS Value */ 249 #define MXC_S_SPI_CTRL2_NUM_BITS_4BITS (MXC_V_SPI_CTRL2_NUM_BITS_4BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_4BITS Setting */ 250 #define MXC_V_SPI_CTRL2_NUM_BITS_5BITS ((uint32_t)0x5UL) /**< CTRL2_NUM_BITS_5BITS Value */ 251 #define MXC_S_SPI_CTRL2_NUM_BITS_5BITS (MXC_V_SPI_CTRL2_NUM_BITS_5BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_5BITS Setting */ 252 #define MXC_V_SPI_CTRL2_NUM_BITS_6BITS ((uint32_t)0x6UL) /**< CTRL2_NUM_BITS_6BITS Value */ 253 #define MXC_S_SPI_CTRL2_NUM_BITS_6BITS (MXC_V_SPI_CTRL2_NUM_BITS_6BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_6BITS Setting */ 254 #define MXC_V_SPI_CTRL2_NUM_BITS_7BITS ((uint32_t)0x7UL) /**< CTRL2_NUM_BITS_7BITS Value */ 255 #define MXC_S_SPI_CTRL2_NUM_BITS_7BITS (MXC_V_SPI_CTRL2_NUM_BITS_7BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_7BITS Setting */ 256 #define MXC_V_SPI_CTRL2_NUM_BITS_8BITS ((uint32_t)0x8UL) /**< CTRL2_NUM_BITS_8BITS Value */ 257 #define MXC_S_SPI_CTRL2_NUM_BITS_8BITS (MXC_V_SPI_CTRL2_NUM_BITS_8BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_8BITS Setting */ 258 #define MXC_V_SPI_CTRL2_NUM_BITS_9BITS ((uint32_t)0x9UL) /**< CTRL2_NUM_BITS_9BITS Value */ 259 #define MXC_S_SPI_CTRL2_NUM_BITS_9BITS (MXC_V_SPI_CTRL2_NUM_BITS_9BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_9BITS Setting */ 260 #define MXC_V_SPI_CTRL2_NUM_BITS_10BITS ((uint32_t)0xAUL) /**< CTRL2_NUM_BITS_10BITS Value */ 261 #define MXC_S_SPI_CTRL2_NUM_BITS_10BITS (MXC_V_SPI_CTRL2_NUM_BITS_10BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_10BITS Setting */ 262 #define MXC_V_SPI_CTRL2_NUM_BITS_11BITS ((uint32_t)0xBUL) /**< CTRL2_NUM_BITS_11BITS Value */ 263 #define MXC_S_SPI_CTRL2_NUM_BITS_11BITS (MXC_V_SPI_CTRL2_NUM_BITS_11BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_11BITS Setting */ 264 #define MXC_V_SPI_CTRL2_NUM_BITS_12BITS ((uint32_t)0xCUL) /**< CTRL2_NUM_BITS_12BITS Value */ 265 #define MXC_S_SPI_CTRL2_NUM_BITS_12BITS (MXC_V_SPI_CTRL2_NUM_BITS_12BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_12BITS Setting */ 266 #define MXC_V_SPI_CTRL2_NUM_BITS_13BITS ((uint32_t)0xDUL) /**< CTRL2_NUM_BITS_13BITS Value */ 267 #define MXC_S_SPI_CTRL2_NUM_BITS_13BITS (MXC_V_SPI_CTRL2_NUM_BITS_13BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_13BITS Setting */ 268 #define MXC_V_SPI_CTRL2_NUM_BITS_14BITS ((uint32_t)0xEUL) /**< CTRL2_NUM_BITS_14BITS Value */ 269 #define MXC_S_SPI_CTRL2_NUM_BITS_14BITS (MXC_V_SPI_CTRL2_NUM_BITS_14BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_14BITS Setting */ 270 #define MXC_V_SPI_CTRL2_NUM_BITS_15BITS ((uint32_t)0xFUL) /**< CTRL2_NUM_BITS_15BITS Value */ 271 #define MXC_S_SPI_CTRL2_NUM_BITS_15BITS (MXC_V_SPI_CTRL2_NUM_BITS_15BITS << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_15BITS Setting */ 272 273 #define MXC_F_SPI_CTRL2_BUS_WIDTH_POS 12 /**< CTRL2_BUS_WIDTH Position */ 274 #define MXC_F_SPI_CTRL2_BUS_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_BUS_WIDTH_POS)) /**< CTRL2_BUS_WIDTH Mask */ 275 #define MXC_V_SPI_CTRL2_BUS_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_BUS_WIDTH_MONO Value */ 276 #define MXC_S_SPI_CTRL2_BUS_WIDTH_MONO (MXC_V_SPI_CTRL2_BUS_WIDTH_MONO << MXC_F_SPI_CTRL2_BUS_WIDTH_POS) /**< CTRL2_BUS_WIDTH_MONO Setting */ 277 #define MXC_V_SPI_CTRL2_BUS_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_BUS_WIDTH_DUAL Value */ 278 #define MXC_S_SPI_CTRL2_BUS_WIDTH_DUAL (MXC_V_SPI_CTRL2_BUS_WIDTH_DUAL << MXC_F_SPI_CTRL2_BUS_WIDTH_POS) /**< CTRL2_BUS_WIDTH_DUAL Setting */ 279 #define MXC_V_SPI_CTRL2_BUS_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_BUS_WIDTH_QUAD Value */ 280 #define MXC_S_SPI_CTRL2_BUS_WIDTH_QUAD (MXC_V_SPI_CTRL2_BUS_WIDTH_QUAD << MXC_F_SPI_CTRL2_BUS_WIDTH_POS) /**< CTRL2_BUS_WIDTH_QUAD Setting */ 281 282 #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ 283 #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ 284 #define MXC_V_SPI_CTRL2_THREE_WIRE_4WIRE ((uint32_t)0x0UL) /**< CTRL2_THREE_WIRE_4WIRE Value */ 285 #define MXC_S_SPI_CTRL2_THREE_WIRE_4WIRE (MXC_V_SPI_CTRL2_THREE_WIRE_4WIRE << MXC_F_SPI_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_4WIRE Setting */ 286 #define MXC_V_SPI_CTRL2_THREE_WIRE_3WIRE ((uint32_t)0x1UL) /**< CTRL2_THREE_WIRE_3WIRE Value */ 287 #define MXC_S_SPI_CTRL2_THREE_WIRE_3WIRE (MXC_V_SPI_CTRL2_THREE_WIRE_3WIRE << MXC_F_SPI_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_3WIRE Setting */ 288 289 #define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ 290 #define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ 291 #define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ 292 #define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ 293 #define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ 294 #define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ 295 #define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ 296 #define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ 297 #define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ 298 #define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ 299 300 /**@} end of group SPI_CTRL2_Register */ 301 302 /** 303 * @ingroup spi_registers 304 * @defgroup SPI_SS_TIME SPI_SS_TIME 305 * @brief Register for controlling SPI peripheral/Slave Select Timing. 306 * @{ 307 */ 308 #define MXC_F_SPI_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */ 309 #define MXC_F_SPI_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */ 310 #define MXC_V_SPI_SS_TIME_SSACT1_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT1_256 Value */ 311 #define MXC_S_SPI_SS_TIME_SSACT1_256 (MXC_V_SPI_SS_TIME_SSACT1_256 << MXC_F_SPI_SS_TIME_SSACT1_POS) /**< SS_TIME_SSACT1_256 Setting */ 312 313 #define MXC_F_SPI_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */ 314 #define MXC_F_SPI_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */ 315 #define MXC_V_SPI_SS_TIME_SSACT2_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT2_256 Value */ 316 #define MXC_S_SPI_SS_TIME_SSACT2_256 (MXC_V_SPI_SS_TIME_SSACT2_256 << MXC_F_SPI_SS_TIME_SSACT2_POS) /**< SS_TIME_SSACT2_256 Setting */ 317 318 #define MXC_F_SPI_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */ 319 #define MXC_F_SPI_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */ 320 #define MXC_V_SPI_SS_TIME_SSINACT_256 ((uint32_t)0x0UL) /**< SS_TIME_SSINACT_256 Value */ 321 #define MXC_S_SPI_SS_TIME_SSINACT_256 (MXC_V_SPI_SS_TIME_SSINACT_256 << MXC_F_SPI_SS_TIME_SSINACT_POS) /**< SS_TIME_SSINACT_256 Setting */ 322 323 /**@} end of group SPI_SS_TIME_Register */ 324 325 /** 326 * @ingroup spi_registers 327 * @defgroup SPI_CLK_CFG SPI_CLK_CFG 328 * @brief Register for controlling SPI clock rate. 329 * @{ 330 */ 331 #define MXC_F_SPI_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */ 332 #define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */ 333 334 #define MXC_F_SPI_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */ 335 #define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */ 336 337 #define MXC_F_SPI_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */ 338 #define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */ 339 #define MXC_V_SPI_CLK_CFG_SCALE_DIV1 ((uint32_t)0x0UL) /**< CLK_CFG_SCALE_DIV1 Value */ 340 #define MXC_S_SPI_CLK_CFG_SCALE_DIV1 (MXC_V_SPI_CLK_CFG_SCALE_DIV1 << MXC_F_SPI_CLK_CFG_SCALE_POS) /**< CLK_CFG_SCALE_DIV1 Setting */ 341 #define MXC_V_SPI_CLK_CFG_SCALE_DIV2 ((uint32_t)0x1UL) /**< CLK_CFG_SCALE_DIV2 Value */ 342 #define MXC_S_SPI_CLK_CFG_SCALE_DIV2 (MXC_V_SPI_CLK_CFG_SCALE_DIV2 << MXC_F_SPI_CLK_CFG_SCALE_POS) /**< CLK_CFG_SCALE_DIV2 Setting */ 343 #define MXC_V_SPI_CLK_CFG_SCALE_DIV4 ((uint32_t)0x2UL) /**< CLK_CFG_SCALE_DIV4 Value */ 344 #define MXC_S_SPI_CLK_CFG_SCALE_DIV4 (MXC_V_SPI_CLK_CFG_SCALE_DIV4 << MXC_F_SPI_CLK_CFG_SCALE_POS) /**< CLK_CFG_SCALE_DIV4 Setting */ 345 #define MXC_V_SPI_CLK_CFG_SCALE_DIV8 ((uint32_t)0x3UL) /**< CLK_CFG_SCALE_DIV8 Value */ 346 #define MXC_S_SPI_CLK_CFG_SCALE_DIV8 (MXC_V_SPI_CLK_CFG_SCALE_DIV8 << MXC_F_SPI_CLK_CFG_SCALE_POS) /**< CLK_CFG_SCALE_DIV8 Setting */ 347 #define MXC_V_SPI_CLK_CFG_SCALE_DIV16 ((uint32_t)0x4UL) /**< CLK_CFG_SCALE_DIV16 Value */ 348 #define MXC_S_SPI_CLK_CFG_SCALE_DIV16 (MXC_V_SPI_CLK_CFG_SCALE_DIV16 << MXC_F_SPI_CLK_CFG_SCALE_POS) /**< CLK_CFG_SCALE_DIV16 Setting */ 349 #define MXC_V_SPI_CLK_CFG_SCALE_DIV32 ((uint32_t)0x5UL) /**< CLK_CFG_SCALE_DIV32 Value */ 350 #define MXC_S_SPI_CLK_CFG_SCALE_DIV32 (MXC_V_SPI_CLK_CFG_SCALE_DIV32 << MXC_F_SPI_CLK_CFG_SCALE_POS) /**< CLK_CFG_SCALE_DIV32 Setting */ 351 #define MXC_V_SPI_CLK_CFG_SCALE_DIV64 ((uint32_t)0x6UL) /**< CLK_CFG_SCALE_DIV64 Value */ 352 #define MXC_S_SPI_CLK_CFG_SCALE_DIV64 (MXC_V_SPI_CLK_CFG_SCALE_DIV64 << MXC_F_SPI_CLK_CFG_SCALE_POS) /**< CLK_CFG_SCALE_DIV64 Setting */ 353 #define MXC_V_SPI_CLK_CFG_SCALE_DIV128 ((uint32_t)0x7UL) /**< CLK_CFG_SCALE_DIV128 Value */ 354 #define MXC_S_SPI_CLK_CFG_SCALE_DIV128 (MXC_V_SPI_CLK_CFG_SCALE_DIV128 << MXC_F_SPI_CLK_CFG_SCALE_POS) /**< CLK_CFG_SCALE_DIV128 Setting */ 355 #define MXC_V_SPI_CLK_CFG_SCALE_DIV256 ((uint32_t)0x8UL) /**< CLK_CFG_SCALE_DIV256 Value */ 356 #define MXC_S_SPI_CLK_CFG_SCALE_DIV256 (MXC_V_SPI_CLK_CFG_SCALE_DIV256 << MXC_F_SPI_CLK_CFG_SCALE_POS) /**< CLK_CFG_SCALE_DIV256 Setting */ 357 358 /**@} end of group SPI_CLK_CFG_Register */ 359 360 /** 361 * @ingroup spi_registers 362 * @defgroup SPI_DMA SPI_DMA 363 * @brief Register for controlling DMA. 364 * @{ 365 */ 366 #define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ 367 #define MXC_F_SPI_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ 368 369 #define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 370 #define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 371 #define MXC_V_SPI_DMA_TX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_FIFO_EN_DIS Value */ 372 #define MXC_S_SPI_DMA_TX_FIFO_EN_DIS (MXC_V_SPI_DMA_TX_FIFO_EN_DIS << MXC_F_SPI_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_DIS Setting */ 373 #define MXC_V_SPI_DMA_TX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_FIFO_EN_EN Value */ 374 #define MXC_S_SPI_DMA_TX_FIFO_EN_EN (MXC_V_SPI_DMA_TX_FIFO_EN_EN << MXC_F_SPI_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_EN Setting */ 375 376 #define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ 377 #define MXC_F_SPI_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ 378 #define MXC_V_SPI_DMA_TX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_CLEAR Value */ 379 #define MXC_S_SPI_DMA_TX_FIFO_CLEAR_CLEAR (MXC_V_SPI_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_CLEAR Setting */ 380 381 #define MXC_F_SPI_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 382 #define MXC_F_SPI_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 383 384 #define MXC_F_SPI_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 385 #define MXC_F_SPI_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 386 #define MXC_V_SPI_DMA_TX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DIS Value */ 387 #define MXC_S_SPI_DMA_TX_DMA_EN_DIS (MXC_V_SPI_DMA_TX_DMA_EN_DIS << MXC_F_SPI_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DIS Setting */ 388 #define MXC_V_SPI_DMA_TX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_EN Value */ 389 #define MXC_S_SPI_DMA_TX_DMA_EN_EN (MXC_V_SPI_DMA_TX_DMA_EN_EN << MXC_F_SPI_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_EN Setting */ 390 391 #define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ 392 #define MXC_F_SPI_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ 393 394 #define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 395 #define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 396 #define MXC_V_SPI_DMA_RX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_FIFO_EN_DIS Value */ 397 #define MXC_S_SPI_DMA_RX_FIFO_EN_DIS (MXC_V_SPI_DMA_RX_FIFO_EN_DIS << MXC_F_SPI_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_DIS Setting */ 398 #define MXC_V_SPI_DMA_RX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_FIFO_EN_EN Value */ 399 #define MXC_S_SPI_DMA_RX_FIFO_EN_EN (MXC_V_SPI_DMA_RX_FIFO_EN_EN << MXC_F_SPI_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_EN Setting */ 400 401 #define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ 402 #define MXC_F_SPI_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ 403 #define MXC_V_SPI_DMA_RX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_CLEAR Value */ 404 #define MXC_S_SPI_DMA_RX_FIFO_CLEAR_CLEAR (MXC_V_SPI_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_CLEAR Setting */ 405 406 #define MXC_F_SPI_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 407 #define MXC_F_SPI_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 408 409 #define MXC_F_SPI_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 410 #define MXC_F_SPI_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 411 #define MXC_V_SPI_DMA_RX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DIS Value */ 412 #define MXC_S_SPI_DMA_RX_DMA_EN_DIS (MXC_V_SPI_DMA_RX_DMA_EN_DIS << MXC_F_SPI_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DIS Setting */ 413 #define MXC_V_SPI_DMA_RX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_EN Value */ 414 #define MXC_S_SPI_DMA_RX_DMA_EN_EN (MXC_V_SPI_DMA_RX_DMA_EN_EN << MXC_F_SPI_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_EN Setting */ 415 416 /**@} end of group SPI_DMA_Register */ 417 418 /** 419 * @ingroup spi_registers 420 * @defgroup SPI_INT_FL SPI_INT_FL 421 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 422 * clear. 423 * @{ 424 */ 425 #define MXC_F_SPI_INT_FL_TX_LEVEL_POS 0 /**< INT_FL_TX_LEVEL Position */ 426 #define MXC_F_SPI_INT_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_LEVEL_POS)) /**< INT_FL_TX_LEVEL Mask */ 427 #define MXC_V_SPI_INT_FL_TX_LEVEL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_LEVEL_CLEAR Value */ 428 #define MXC_S_SPI_INT_FL_TX_LEVEL_CLEAR (MXC_V_SPI_INT_FL_TX_LEVEL_CLEAR << MXC_F_SPI_INT_FL_TX_LEVEL_POS) /**< INT_FL_TX_LEVEL_CLEAR Setting */ 429 430 #define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ 431 #define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ 432 #define MXC_V_SPI_INT_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_EMPTY_CLEAR Value */ 433 #define MXC_S_SPI_INT_FL_TX_EMPTY_CLEAR (MXC_V_SPI_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPI_INT_FL_TX_EMPTY_POS) /**< INT_FL_TX_EMPTY_CLEAR Setting */ 434 435 #define MXC_F_SPI_INT_FL_RX_LEVEL_POS 2 /**< INT_FL_RX_LEVEL Position */ 436 #define MXC_F_SPI_INT_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_LEVEL_POS)) /**< INT_FL_RX_LEVEL Mask */ 437 #define MXC_V_SPI_INT_FL_RX_LEVEL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_LEVEL_CLEAR Value */ 438 #define MXC_S_SPI_INT_FL_RX_LEVEL_CLEAR (MXC_V_SPI_INT_FL_RX_LEVEL_CLEAR << MXC_F_SPI_INT_FL_RX_LEVEL_POS) /**< INT_FL_RX_LEVEL_CLEAR Setting */ 439 440 #define MXC_F_SPI_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ 441 #define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ 442 #define MXC_V_SPI_INT_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_FULL_CLEAR Value */ 443 #define MXC_S_SPI_INT_FL_RX_FULL_CLEAR (MXC_V_SPI_INT_FL_RX_FULL_CLEAR << MXC_F_SPI_INT_FL_RX_FULL_POS) /**< INT_FL_RX_FULL_CLEAR Setting */ 444 445 #define MXC_F_SPI_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ 446 #define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ 447 #define MXC_V_SPI_INT_FL_SSA_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSA_CLEAR Value */ 448 #define MXC_S_SPI_INT_FL_SSA_CLEAR (MXC_V_SPI_INT_FL_SSA_CLEAR << MXC_F_SPI_INT_FL_SSA_POS) /**< INT_FL_SSA_CLEAR Setting */ 449 450 #define MXC_F_SPI_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ 451 #define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ 452 #define MXC_V_SPI_INT_FL_SSD_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSD_CLEAR Value */ 453 #define MXC_S_SPI_INT_FL_SSD_CLEAR (MXC_V_SPI_INT_FL_SSD_CLEAR << MXC_F_SPI_INT_FL_SSD_POS) /**< INT_FL_SSD_CLEAR Setting */ 454 455 #define MXC_F_SPI_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */ 456 #define MXC_F_SPI_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */ 457 #define MXC_V_SPI_INT_FL_FAULT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_FAULT_CLEAR Value */ 458 #define MXC_S_SPI_INT_FL_FAULT_CLEAR (MXC_V_SPI_INT_FL_FAULT_CLEAR << MXC_F_SPI_INT_FL_FAULT_POS) /**< INT_FL_FAULT_CLEAR Setting */ 459 460 #define MXC_F_SPI_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ 461 #define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ 462 #define MXC_V_SPI_INT_FL_ABORT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_ABORT_CLEAR Value */ 463 #define MXC_S_SPI_INT_FL_ABORT_CLEAR (MXC_V_SPI_INT_FL_ABORT_CLEAR << MXC_F_SPI_INT_FL_ABORT_POS) /**< INT_FL_ABORT_CLEAR Setting */ 464 465 #define MXC_F_SPI_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ 466 #define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ 467 #define MXC_V_SPI_INT_FL_M_DONE_CLEAR ((uint32_t)0x1UL) /**< INT_FL_M_DONE_CLEAR Value */ 468 #define MXC_S_SPI_INT_FL_M_DONE_CLEAR (MXC_V_SPI_INT_FL_M_DONE_CLEAR << MXC_F_SPI_INT_FL_M_DONE_POS) /**< INT_FL_M_DONE_CLEAR Setting */ 469 470 #define MXC_F_SPI_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ 471 #define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ 472 #define MXC_V_SPI_INT_FL_TX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_OVR_CLEAR Value */ 473 #define MXC_S_SPI_INT_FL_TX_OVR_CLEAR (MXC_V_SPI_INT_FL_TX_OVR_CLEAR << MXC_F_SPI_INT_FL_TX_OVR_POS) /**< INT_FL_TX_OVR_CLEAR Setting */ 474 475 #define MXC_F_SPI_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ 476 #define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ 477 #define MXC_V_SPI_INT_FL_TX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_UND_CLEAR Value */ 478 #define MXC_S_SPI_INT_FL_TX_UND_CLEAR (MXC_V_SPI_INT_FL_TX_UND_CLEAR << MXC_F_SPI_INT_FL_TX_UND_POS) /**< INT_FL_TX_UND_CLEAR Setting */ 479 480 #define MXC_F_SPI_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ 481 #define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ 482 #define MXC_V_SPI_INT_FL_RX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_OVR_CLEAR Value */ 483 #define MXC_S_SPI_INT_FL_RX_OVR_CLEAR (MXC_V_SPI_INT_FL_RX_OVR_CLEAR << MXC_F_SPI_INT_FL_RX_OVR_POS) /**< INT_FL_RX_OVR_CLEAR Setting */ 484 485 #define MXC_F_SPI_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ 486 #define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ 487 #define MXC_V_SPI_INT_FL_RX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_UND_CLEAR Value */ 488 #define MXC_S_SPI_INT_FL_RX_UND_CLEAR (MXC_V_SPI_INT_FL_RX_UND_CLEAR << MXC_F_SPI_INT_FL_RX_UND_POS) /**< INT_FL_RX_UND_CLEAR Setting */ 489 490 /**@} end of group SPI_INT_FL_Register */ 491 492 /** 493 * @ingroup spi_registers 494 * @defgroup SPI_INT_EN SPI_INT_EN 495 * @brief Register for enabling interrupts. 496 * @{ 497 */ 498 #define MXC_F_SPI_INT_EN_TX_LEVEL_POS 0 /**< INT_EN_TX_LEVEL Position */ 499 #define MXC_F_SPI_INT_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_LEVEL_POS)) /**< INT_EN_TX_LEVEL Mask */ 500 #define MXC_V_SPI_INT_EN_TX_LEVEL_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_LEVEL_DIS Value */ 501 #define MXC_S_SPI_INT_EN_TX_LEVEL_DIS (MXC_V_SPI_INT_EN_TX_LEVEL_DIS << MXC_F_SPI_INT_EN_TX_LEVEL_POS) /**< INT_EN_TX_LEVEL_DIS Setting */ 502 #define MXC_V_SPI_INT_EN_TX_LEVEL_EN ((uint32_t)0x1UL) /**< INT_EN_TX_LEVEL_EN Value */ 503 #define MXC_S_SPI_INT_EN_TX_LEVEL_EN (MXC_V_SPI_INT_EN_TX_LEVEL_EN << MXC_F_SPI_INT_EN_TX_LEVEL_POS) /**< INT_EN_TX_LEVEL_EN Setting */ 504 505 #define MXC_F_SPI_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ 506 #define MXC_F_SPI_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ 507 #define MXC_V_SPI_INT_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_EMPTY_DIS Value */ 508 #define MXC_S_SPI_INT_EN_TX_EMPTY_DIS (MXC_V_SPI_INT_EN_TX_EMPTY_DIS << MXC_F_SPI_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_DIS Setting */ 509 #define MXC_V_SPI_INT_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< INT_EN_TX_EMPTY_EN Value */ 510 #define MXC_S_SPI_INT_EN_TX_EMPTY_EN (MXC_V_SPI_INT_EN_TX_EMPTY_EN << MXC_F_SPI_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_EN Setting */ 511 512 #define MXC_F_SPI_INT_EN_RX_LEVEL_POS 2 /**< INT_EN_RX_LEVEL Position */ 513 #define MXC_F_SPI_INT_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_LEVEL_POS)) /**< INT_EN_RX_LEVEL Mask */ 514 #define MXC_V_SPI_INT_EN_RX_LEVEL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_LEVEL_DIS Value */ 515 #define MXC_S_SPI_INT_EN_RX_LEVEL_DIS (MXC_V_SPI_INT_EN_RX_LEVEL_DIS << MXC_F_SPI_INT_EN_RX_LEVEL_POS) /**< INT_EN_RX_LEVEL_DIS Setting */ 516 #define MXC_V_SPI_INT_EN_RX_LEVEL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_LEVEL_EN Value */ 517 #define MXC_S_SPI_INT_EN_RX_LEVEL_EN (MXC_V_SPI_INT_EN_RX_LEVEL_EN << MXC_F_SPI_INT_EN_RX_LEVEL_POS) /**< INT_EN_RX_LEVEL_EN Setting */ 518 519 #define MXC_F_SPI_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ 520 #define MXC_F_SPI_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ 521 #define MXC_V_SPI_INT_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_FULL_DIS Value */ 522 #define MXC_S_SPI_INT_EN_RX_FULL_DIS (MXC_V_SPI_INT_EN_RX_FULL_DIS << MXC_F_SPI_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_DIS Setting */ 523 #define MXC_V_SPI_INT_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_FULL_EN Value */ 524 #define MXC_S_SPI_INT_EN_RX_FULL_EN (MXC_V_SPI_INT_EN_RX_FULL_EN << MXC_F_SPI_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_EN Setting */ 525 526 #define MXC_F_SPI_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ 527 #define MXC_F_SPI_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ 528 #define MXC_V_SPI_INT_EN_SSA_DIS ((uint32_t)0x0UL) /**< INT_EN_SSA_DIS Value */ 529 #define MXC_S_SPI_INT_EN_SSA_DIS (MXC_V_SPI_INT_EN_SSA_DIS << MXC_F_SPI_INT_EN_SSA_POS) /**< INT_EN_SSA_DIS Setting */ 530 #define MXC_V_SPI_INT_EN_SSA_EN ((uint32_t)0x1UL) /**< INT_EN_SSA_EN Value */ 531 #define MXC_S_SPI_INT_EN_SSA_EN (MXC_V_SPI_INT_EN_SSA_EN << MXC_F_SPI_INT_EN_SSA_POS) /**< INT_EN_SSA_EN Setting */ 532 533 #define MXC_F_SPI_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ 534 #define MXC_F_SPI_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ 535 #define MXC_V_SPI_INT_EN_SSD_DIS ((uint32_t)0x0UL) /**< INT_EN_SSD_DIS Value */ 536 #define MXC_S_SPI_INT_EN_SSD_DIS (MXC_V_SPI_INT_EN_SSD_DIS << MXC_F_SPI_INT_EN_SSD_POS) /**< INT_EN_SSD_DIS Setting */ 537 #define MXC_V_SPI_INT_EN_SSD_EN ((uint32_t)0x1UL) /**< INT_EN_SSD_EN Value */ 538 #define MXC_S_SPI_INT_EN_SSD_EN (MXC_V_SPI_INT_EN_SSD_EN << MXC_F_SPI_INT_EN_SSD_POS) /**< INT_EN_SSD_EN Setting */ 539 540 #define MXC_F_SPI_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ 541 #define MXC_F_SPI_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ 542 #define MXC_V_SPI_INT_EN_FAULT_DIS ((uint32_t)0x0UL) /**< INT_EN_FAULT_DIS Value */ 543 #define MXC_S_SPI_INT_EN_FAULT_DIS (MXC_V_SPI_INT_EN_FAULT_DIS << MXC_F_SPI_INT_EN_FAULT_POS) /**< INT_EN_FAULT_DIS Setting */ 544 #define MXC_V_SPI_INT_EN_FAULT_EN ((uint32_t)0x1UL) /**< INT_EN_FAULT_EN Value */ 545 #define MXC_S_SPI_INT_EN_FAULT_EN (MXC_V_SPI_INT_EN_FAULT_EN << MXC_F_SPI_INT_EN_FAULT_POS) /**< INT_EN_FAULT_EN Setting */ 546 547 #define MXC_F_SPI_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ 548 #define MXC_F_SPI_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ 549 #define MXC_V_SPI_INT_EN_ABORT_DIS ((uint32_t)0x0UL) /**< INT_EN_ABORT_DIS Value */ 550 #define MXC_S_SPI_INT_EN_ABORT_DIS (MXC_V_SPI_INT_EN_ABORT_DIS << MXC_F_SPI_INT_EN_ABORT_POS) /**< INT_EN_ABORT_DIS Setting */ 551 #define MXC_V_SPI_INT_EN_ABORT_EN ((uint32_t)0x1UL) /**< INT_EN_ABORT_EN Value */ 552 #define MXC_S_SPI_INT_EN_ABORT_EN (MXC_V_SPI_INT_EN_ABORT_EN << MXC_F_SPI_INT_EN_ABORT_POS) /**< INT_EN_ABORT_EN Setting */ 553 554 #define MXC_F_SPI_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ 555 #define MXC_F_SPI_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ 556 #define MXC_V_SPI_INT_EN_M_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN_M_DONE_DIS Value */ 557 #define MXC_S_SPI_INT_EN_M_DONE_DIS (MXC_V_SPI_INT_EN_M_DONE_DIS << MXC_F_SPI_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_DIS Setting */ 558 #define MXC_V_SPI_INT_EN_M_DONE_EN ((uint32_t)0x1UL) /**< INT_EN_M_DONE_EN Value */ 559 #define MXC_S_SPI_INT_EN_M_DONE_EN (MXC_V_SPI_INT_EN_M_DONE_EN << MXC_F_SPI_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_EN Setting */ 560 561 #define MXC_F_SPI_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ 562 #define MXC_F_SPI_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ 563 #define MXC_V_SPI_INT_EN_TX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_OVR_DIS Value */ 564 #define MXC_S_SPI_INT_EN_TX_OVR_DIS (MXC_V_SPI_INT_EN_TX_OVR_DIS << MXC_F_SPI_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_DIS Setting */ 565 #define MXC_V_SPI_INT_EN_TX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_TX_OVR_EN Value */ 566 #define MXC_S_SPI_INT_EN_TX_OVR_EN (MXC_V_SPI_INT_EN_TX_OVR_EN << MXC_F_SPI_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_EN Setting */ 567 568 #define MXC_F_SPI_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ 569 #define MXC_F_SPI_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ 570 #define MXC_V_SPI_INT_EN_TX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_UND_DIS Value */ 571 #define MXC_S_SPI_INT_EN_TX_UND_DIS (MXC_V_SPI_INT_EN_TX_UND_DIS << MXC_F_SPI_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_DIS Setting */ 572 #define MXC_V_SPI_INT_EN_TX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_TX_UND_EN Value */ 573 #define MXC_S_SPI_INT_EN_TX_UND_EN (MXC_V_SPI_INT_EN_TX_UND_EN << MXC_F_SPI_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_EN Setting */ 574 575 #define MXC_F_SPI_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ 576 #define MXC_F_SPI_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ 577 #define MXC_V_SPI_INT_EN_RX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_OVR_DIS Value */ 578 #define MXC_S_SPI_INT_EN_RX_OVR_DIS (MXC_V_SPI_INT_EN_RX_OVR_DIS << MXC_F_SPI_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_DIS Setting */ 579 #define MXC_V_SPI_INT_EN_RX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_RX_OVR_EN Value */ 580 #define MXC_S_SPI_INT_EN_RX_OVR_EN (MXC_V_SPI_INT_EN_RX_OVR_EN << MXC_F_SPI_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_EN Setting */ 581 582 #define MXC_F_SPI_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ 583 #define MXC_F_SPI_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ 584 #define MXC_V_SPI_INT_EN_RX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_UND_DIS Value */ 585 #define MXC_S_SPI_INT_EN_RX_UND_DIS (MXC_V_SPI_INT_EN_RX_UND_DIS << MXC_F_SPI_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_DIS Setting */ 586 #define MXC_V_SPI_INT_EN_RX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_RX_UND_EN Value */ 587 #define MXC_S_SPI_INT_EN_RX_UND_EN (MXC_V_SPI_INT_EN_RX_UND_EN << MXC_F_SPI_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_EN Setting */ 588 589 /**@} end of group SPI_INT_EN_Register */ 590 591 /** 592 * @ingroup spi_registers 593 * @defgroup SPI_WAKE_FL SPI_WAKE_FL 594 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 595 * @{ 596 */ 597 #define MXC_F_SPI_WAKE_FL_TX_LEVEL_POS 0 /**< WAKE_FL_TX_LEVEL Position */ 598 #define MXC_F_SPI_WAKE_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS)) /**< WAKE_FL_TX_LEVEL Mask */ 599 #define MXC_V_SPI_WAKE_FL_TX_LEVEL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_LEVEL_CLEAR Value */ 600 #define MXC_S_SPI_WAKE_FL_TX_LEVEL_CLEAR (MXC_V_SPI_WAKE_FL_TX_LEVEL_CLEAR << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS) /**< WAKE_FL_TX_LEVEL_CLEAR Setting */ 601 602 #define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ 603 #define MXC_F_SPI_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ 604 #define MXC_V_SPI_WAKE_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_EMPTY_CLEAR Value */ 605 #define MXC_S_SPI_WAKE_FL_TX_EMPTY_CLEAR (MXC_V_SPI_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS) /**< WAKE_FL_TX_EMPTY_CLEAR Setting */ 606 607 #define MXC_F_SPI_WAKE_FL_RX_LEVEL_POS 2 /**< WAKE_FL_RX_LEVEL Position */ 608 #define MXC_F_SPI_WAKE_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS)) /**< WAKE_FL_RX_LEVEL Mask */ 609 #define MXC_V_SPI_WAKE_FL_RX_LEVEL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_LEVEL_CLEAR Value */ 610 #define MXC_S_SPI_WAKE_FL_RX_LEVEL_CLEAR (MXC_V_SPI_WAKE_FL_RX_LEVEL_CLEAR << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS) /**< WAKE_FL_RX_LEVEL_CLEAR Setting */ 611 612 #define MXC_F_SPI_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ 613 #define MXC_F_SPI_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ 614 #define MXC_V_SPI_WAKE_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_FULL_CLEAR Value */ 615 #define MXC_S_SPI_WAKE_FL_RX_FULL_CLEAR (MXC_V_SPI_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPI_WAKE_FL_RX_FULL_POS) /**< WAKE_FL_RX_FULL_CLEAR Setting */ 616 617 /**@} end of group SPI_WAKE_FL_Register */ 618 619 /** 620 * @ingroup spi_registers 621 * @defgroup SPI_WAKE_EN SPI_WAKE_EN 622 * @brief Register for wake up enable. 623 * @{ 624 */ 625 #define MXC_F_SPI_WAKE_EN_TX_LEVEL_POS 0 /**< WAKE_EN_TX_LEVEL Position */ 626 #define MXC_F_SPI_WAKE_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)) /**< WAKE_EN_TX_LEVEL Mask */ 627 #define MXC_V_SPI_WAKE_EN_TX_LEVEL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_LEVEL_DIS Value */ 628 #define MXC_S_SPI_WAKE_EN_TX_LEVEL_DIS (MXC_V_SPI_WAKE_EN_TX_LEVEL_DIS << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS) /**< WAKE_EN_TX_LEVEL_DIS Setting */ 629 #define MXC_V_SPI_WAKE_EN_TX_LEVEL_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_LEVEL_EN Value */ 630 #define MXC_S_SPI_WAKE_EN_TX_LEVEL_EN (MXC_V_SPI_WAKE_EN_TX_LEVEL_EN << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS) /**< WAKE_EN_TX_LEVEL_EN Setting */ 631 632 #define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ 633 #define MXC_F_SPI_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ 634 #define MXC_V_SPI_WAKE_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_EMPTY_DIS Value */ 635 #define MXC_S_SPI_WAKE_EN_TX_EMPTY_DIS (MXC_V_SPI_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_DIS Setting */ 636 #define MXC_V_SPI_WAKE_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_EMPTY_EN Value */ 637 #define MXC_S_SPI_WAKE_EN_TX_EMPTY_EN (MXC_V_SPI_WAKE_EN_TX_EMPTY_EN << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_EN Setting */ 638 639 #define MXC_F_SPI_WAKE_EN_RX_LEVEL_POS 2 /**< WAKE_EN_RX_LEVEL Position */ 640 #define MXC_F_SPI_WAKE_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)) /**< WAKE_EN_RX_LEVEL Mask */ 641 #define MXC_V_SPI_WAKE_EN_RX_LEVEL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_LEVEL_DIS Value */ 642 #define MXC_S_SPI_WAKE_EN_RX_LEVEL_DIS (MXC_V_SPI_WAKE_EN_RX_LEVEL_DIS << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS) /**< WAKE_EN_RX_LEVEL_DIS Setting */ 643 #define MXC_V_SPI_WAKE_EN_RX_LEVEL_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_LEVEL_EN Value */ 644 #define MXC_S_SPI_WAKE_EN_RX_LEVEL_EN (MXC_V_SPI_WAKE_EN_RX_LEVEL_EN << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS) /**< WAKE_EN_RX_LEVEL_EN Setting */ 645 646 #define MXC_F_SPI_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ 647 #define MXC_F_SPI_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ 648 #define MXC_V_SPI_WAKE_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_FULL_DIS Value */ 649 #define MXC_S_SPI_WAKE_EN_RX_FULL_DIS (MXC_V_SPI_WAKE_EN_RX_FULL_DIS << MXC_F_SPI_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_DIS Setting */ 650 #define MXC_V_SPI_WAKE_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_FULL_EN Value */ 651 #define MXC_S_SPI_WAKE_EN_RX_FULL_EN (MXC_V_SPI_WAKE_EN_RX_FULL_EN << MXC_F_SPI_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_EN Setting */ 652 653 /**@} end of group SPI_WAKE_EN_Register */ 654 655 /** 656 * @ingroup spi_registers 657 * @defgroup SPI_STAT SPI_STAT 658 * @brief SPI Status register. 659 * @{ 660 */ 661 #define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 662 #define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 663 #define MXC_V_SPI_STAT_BUSY_NOTACTIVE ((uint32_t)0x0UL) /**< STAT_BUSY_NOTACTIVE Value */ 664 #define MXC_S_SPI_STAT_BUSY_NOTACTIVE (MXC_V_SPI_STAT_BUSY_NOTACTIVE << MXC_F_SPI_STAT_BUSY_POS) /**< STAT_BUSY_NOTACTIVE Setting */ 665 #define MXC_V_SPI_STAT_BUSY_ACTIVE ((uint32_t)0x1UL) /**< STAT_BUSY_ACTIVE Value */ 666 #define MXC_S_SPI_STAT_BUSY_ACTIVE (MXC_V_SPI_STAT_BUSY_ACTIVE << MXC_F_SPI_STAT_BUSY_POS) /**< STAT_BUSY_ACTIVE Setting */ 667 668 /**@} end of group SPI_STAT_Register */ 669 670 #ifdef __cplusplus 671 } 672 #endif 673 674 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_SPI_REGS_H_ 675
