1 /** 2 * @file adc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup adc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_ADC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_ADC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup adc 67 * @defgroup adc_registers ADC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 69 * @details 10-bit Analog to Digital Converter 70 */ 71 72 /** 73 * @ingroup adc_registers 74 * Structure type to access the ADC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> ADC CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x0004:</tt> ADC STATUS Register */ 79 __IO uint32_t data; /**< <tt>\b 0x0008:</tt> ADC DATA Register */ 80 __IO uint32_t intr; /**< <tt>\b 0x000C:</tt> ADC INTR Register */ 81 __IO uint32_t limit[4]; /**< <tt>\b 0x0010:</tt> ADC LIMIT Register */ 82 } mxc_adc_regs_t; 83 84 /* Register offsets for module ADC */ 85 /** 86 * @ingroup adc_registers 87 * @defgroup ADC_Register_Offsets Register Offsets 88 * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_ADC_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_ADC_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_ADC_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_ADC_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_ADC_LIMIT ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt> 0x0010</tt> */ 96 /**@} end of group adc_registers */ 97 98 /** 99 * @ingroup adc_registers 100 * @defgroup ADC_CTRL ADC_CTRL 101 * @brief ADC Control 102 * @{ 103 */ 104 #define MXC_F_ADC_CTRL_START_POS 0 /**< CTRL_START Position */ 105 #define MXC_F_ADC_CTRL_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_START_POS)) /**< CTRL_START Mask */ 106 #define MXC_V_ADC_CTRL_START_INACTIVE ((uint32_t)0x0UL) /**< CTRL_START_INACTIVE Value */ 107 #define MXC_S_ADC_CTRL_START_INACTIVE (MXC_V_ADC_CTRL_START_INACTIVE << MXC_F_ADC_CTRL_START_POS) /**< CTRL_START_INACTIVE Setting */ 108 #define MXC_V_ADC_CTRL_START_START ((uint32_t)0x1UL) /**< CTRL_START_START Value */ 109 #define MXC_S_ADC_CTRL_START_START (MXC_V_ADC_CTRL_START_START << MXC_F_ADC_CTRL_START_POS) /**< CTRL_START_START Setting */ 110 111 #define MXC_F_ADC_CTRL_PWR_POS 1 /**< CTRL_PWR Position */ 112 #define MXC_F_ADC_CTRL_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_PWR_POS)) /**< CTRL_PWR Mask */ 113 #define MXC_V_ADC_CTRL_PWR_ADC_OFF ((uint32_t)0x0UL) /**< CTRL_PWR_ADC_OFF Value */ 114 #define MXC_S_ADC_CTRL_PWR_ADC_OFF (MXC_V_ADC_CTRL_PWR_ADC_OFF << MXC_F_ADC_CTRL_PWR_POS) /**< CTRL_PWR_ADC_OFF Setting */ 115 #define MXC_V_ADC_CTRL_PWR_ADC_ON ((uint32_t)0x1UL) /**< CTRL_PWR_ADC_ON Value */ 116 #define MXC_S_ADC_CTRL_PWR_ADC_ON (MXC_V_ADC_CTRL_PWR_ADC_ON << MXC_F_ADC_CTRL_PWR_POS) /**< CTRL_PWR_ADC_ON Setting */ 117 118 #define MXC_F_ADC_CTRL_REFBUF_PWR_POS 3 /**< CTRL_REFBUF_PWR Position */ 119 #define MXC_F_ADC_CTRL_REFBUF_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REFBUF_PWR_POS)) /**< CTRL_REFBUF_PWR Mask */ 120 #define MXC_V_ADC_CTRL_REFBUF_PWR_REFBUF_OFF ((uint32_t)0x0UL) /**< CTRL_REFBUF_PWR_REFBUF_OFF Value */ 121 #define MXC_S_ADC_CTRL_REFBUF_PWR_REFBUF_OFF (MXC_V_ADC_CTRL_REFBUF_PWR_REFBUF_OFF << MXC_F_ADC_CTRL_REFBUF_PWR_POS) /**< CTRL_REFBUF_PWR_REFBUF_OFF Setting */ 122 #define MXC_V_ADC_CTRL_REFBUF_PWR_REFBUF_ON ((uint32_t)0x1UL) /**< CTRL_REFBUF_PWR_REFBUF_ON Value */ 123 #define MXC_S_ADC_CTRL_REFBUF_PWR_REFBUF_ON (MXC_V_ADC_CTRL_REFBUF_PWR_REFBUF_ON << MXC_F_ADC_CTRL_REFBUF_PWR_POS) /**< CTRL_REFBUF_PWR_REFBUF_ON Setting */ 124 125 #define MXC_F_ADC_CTRL_REF_SEL_POS 4 /**< CTRL_REF_SEL Position */ 126 #define MXC_F_ADC_CTRL_REF_SEL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */ 127 #define MXC_V_ADC_CTRL_REF_SEL_BANDGAP ((uint32_t)0x0UL) /**< CTRL_REF_SEL_BANDGAP Value */ 128 #define MXC_S_ADC_CTRL_REF_SEL_BANDGAP (MXC_V_ADC_CTRL_REF_SEL_BANDGAP << MXC_F_ADC_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_BANDGAP Setting */ 129 #define MXC_V_ADC_CTRL_REF_SEL_VDD_DIV2 ((uint32_t)0x1UL) /**< CTRL_REF_SEL_VDD_DIV2 Value */ 130 #define MXC_S_ADC_CTRL_REF_SEL_VDD_DIV2 (MXC_V_ADC_CTRL_REF_SEL_VDD_DIV2 << MXC_F_ADC_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_VDD_DIV2 Setting */ 131 132 #define MXC_F_ADC_CTRL_REF_SCALE_POS 8 /**< CTRL_REF_SCALE Position */ 133 #define MXC_F_ADC_CTRL_REF_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SCALE_POS)) /**< CTRL_REF_SCALE Mask */ 134 #define MXC_V_ADC_CTRL_REF_SCALE_DIV1 ((uint32_t)0x0UL) /**< CTRL_REF_SCALE_DIV1 Value */ 135 #define MXC_S_ADC_CTRL_REF_SCALE_DIV1 (MXC_V_ADC_CTRL_REF_SCALE_DIV1 << MXC_F_ADC_CTRL_REF_SCALE_POS) /**< CTRL_REF_SCALE_DIV1 Setting */ 136 #define MXC_V_ADC_CTRL_REF_SCALE_DIV2 ((uint32_t)0x1UL) /**< CTRL_REF_SCALE_DIV2 Value */ 137 #define MXC_S_ADC_CTRL_REF_SCALE_DIV2 (MXC_V_ADC_CTRL_REF_SCALE_DIV2 << MXC_F_ADC_CTRL_REF_SCALE_POS) /**< CTRL_REF_SCALE_DIV2 Setting */ 138 139 #define MXC_F_ADC_CTRL_INPUT_SCALE_POS 9 /**< CTRL_INPUT_SCALE Position */ 140 #define MXC_F_ADC_CTRL_INPUT_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_INPUT_SCALE_POS)) /**< CTRL_INPUT_SCALE Mask */ 141 #define MXC_V_ADC_CTRL_INPUT_SCALE_DIV1 ((uint32_t)0x0UL) /**< CTRL_INPUT_SCALE_DIV1 Value */ 142 #define MXC_S_ADC_CTRL_INPUT_SCALE_DIV1 (MXC_V_ADC_CTRL_INPUT_SCALE_DIV1 << MXC_F_ADC_CTRL_INPUT_SCALE_POS) /**< CTRL_INPUT_SCALE_DIV1 Setting */ 143 #define MXC_V_ADC_CTRL_INPUT_SCALE_DIV2 ((uint32_t)0x1UL) /**< CTRL_INPUT_SCALE_DIV2 Value */ 144 #define MXC_S_ADC_CTRL_INPUT_SCALE_DIV2 (MXC_V_ADC_CTRL_INPUT_SCALE_DIV2 << MXC_F_ADC_CTRL_INPUT_SCALE_POS) /**< CTRL_INPUT_SCALE_DIV2 Setting */ 145 146 #define MXC_F_ADC_CTRL_CLK_EN_POS 11 /**< CTRL_CLK_EN Position */ 147 #define MXC_F_ADC_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CLK_EN_POS)) /**< CTRL_CLK_EN Mask */ 148 #define MXC_V_ADC_CTRL_CLK_EN_DIS ((uint32_t)0x0UL) /**< CTRL_CLK_EN_DIS Value */ 149 #define MXC_S_ADC_CTRL_CLK_EN_DIS (MXC_V_ADC_CTRL_CLK_EN_DIS << MXC_F_ADC_CTRL_CLK_EN_POS) /**< CTRL_CLK_EN_DIS Setting */ 150 #define MXC_V_ADC_CTRL_CLK_EN_EN ((uint32_t)0x1UL) /**< CTRL_CLK_EN_EN Value */ 151 #define MXC_S_ADC_CTRL_CLK_EN_EN (MXC_V_ADC_CTRL_CLK_EN_EN << MXC_F_ADC_CTRL_CLK_EN_POS) /**< CTRL_CLK_EN_EN Setting */ 152 153 #define MXC_F_ADC_CTRL_CH_SEL_POS 12 /**< CTRL_CH_SEL Position */ 154 #define MXC_F_ADC_CTRL_CH_SEL ((uint32_t)(0xFUL << MXC_F_ADC_CTRL_CH_SEL_POS)) /**< CTRL_CH_SEL Mask */ 155 #define MXC_V_ADC_CTRL_CH_SEL_AIN0 ((uint32_t)0x0UL) /**< CTRL_CH_SEL_AIN0 Value */ 156 #define MXC_S_ADC_CTRL_CH_SEL_AIN0 (MXC_V_ADC_CTRL_CH_SEL_AIN0 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN0 Setting */ 157 #define MXC_V_ADC_CTRL_CH_SEL_AIN1 ((uint32_t)0x1UL) /**< CTRL_CH_SEL_AIN1 Value */ 158 #define MXC_S_ADC_CTRL_CH_SEL_AIN1 (MXC_V_ADC_CTRL_CH_SEL_AIN1 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN1 Setting */ 159 #define MXC_V_ADC_CTRL_CH_SEL_AIN2 ((uint32_t)0x2UL) /**< CTRL_CH_SEL_AIN2 Value */ 160 #define MXC_S_ADC_CTRL_CH_SEL_AIN2 (MXC_V_ADC_CTRL_CH_SEL_AIN2 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN2 Setting */ 161 #define MXC_V_ADC_CTRL_CH_SEL_AIN3 ((uint32_t)0x3UL) /**< CTRL_CH_SEL_AIN3 Value */ 162 #define MXC_S_ADC_CTRL_CH_SEL_AIN3 (MXC_V_ADC_CTRL_CH_SEL_AIN3 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN3 Setting */ 163 #define MXC_V_ADC_CTRL_CH_SEL_AIN0_DIV5 ((uint32_t)0x4UL) /**< CTRL_CH_SEL_AIN0_DIV5 Value */ 164 #define MXC_S_ADC_CTRL_CH_SEL_AIN0_DIV5 (MXC_V_ADC_CTRL_CH_SEL_AIN0_DIV5 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN0_DIV5 Setting */ 165 #define MXC_V_ADC_CTRL_CH_SEL_AIN1_DIV5 ((uint32_t)0x5UL) /**< CTRL_CH_SEL_AIN1_DIV5 Value */ 166 #define MXC_S_ADC_CTRL_CH_SEL_AIN1_DIV5 (MXC_V_ADC_CTRL_CH_SEL_AIN1_DIV5 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN1_DIV5 Setting */ 167 #define MXC_V_ADC_CTRL_CH_SEL_VDDB_DIV4 ((uint32_t)0x6UL) /**< CTRL_CH_SEL_VDDB_DIV4 Value */ 168 #define MXC_S_ADC_CTRL_CH_SEL_VDDB_DIV4 (MXC_V_ADC_CTRL_CH_SEL_VDDB_DIV4 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDB_DIV4 Setting */ 169 #define MXC_V_ADC_CTRL_CH_SEL_VDDA ((uint32_t)0x7UL) /**< CTRL_CH_SEL_VDDA Value */ 170 #define MXC_S_ADC_CTRL_CH_SEL_VDDA (MXC_V_ADC_CTRL_CH_SEL_VDDA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDA Setting */ 171 #define MXC_V_ADC_CTRL_CH_SEL_VCORE ((uint32_t)0x8UL) /**< CTRL_CH_SEL_VCORE Value */ 172 #define MXC_S_ADC_CTRL_CH_SEL_VCORE (MXC_V_ADC_CTRL_CH_SEL_VCORE << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCORE Setting */ 173 #define MXC_V_ADC_CTRL_CH_SEL_VRTC_DIV2 ((uint32_t)0x9UL) /**< CTRL_CH_SEL_VRTC_DIV2 Value */ 174 #define MXC_S_ADC_CTRL_CH_SEL_VRTC_DIV2 (MXC_V_ADC_CTRL_CH_SEL_VRTC_DIV2 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VRTC_DIV2 Setting */ 175 #define MXC_V_ADC_CTRL_CH_SEL_RSV_0XA ((uint32_t)0xAUL) /**< CTRL_CH_SEL_RSV_0XA Value */ 176 #define MXC_S_ADC_CTRL_CH_SEL_RSV_0XA (MXC_V_ADC_CTRL_CH_SEL_RSV_0XA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_RSV_0XA Setting */ 177 #define MXC_V_ADC_CTRL_CH_SEL_VDDIO_DIV4 ((uint32_t)0xBUL) /**< CTRL_CH_SEL_VDDIO_DIV4 Value */ 178 #define MXC_S_ADC_CTRL_CH_SEL_VDDIO_DIV4 (MXC_V_ADC_CTRL_CH_SEL_VDDIO_DIV4 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIO_DIV4 Setting */ 179 #define MXC_V_ADC_CTRL_CH_SEL_VDDIOH_DIV4 ((uint32_t)0xCUL) /**< CTRL_CH_SEL_VDDIOH_DIV4 Value */ 180 #define MXC_S_ADC_CTRL_CH_SEL_VDDIOH_DIV4 (MXC_V_ADC_CTRL_CH_SEL_VDDIOH_DIV4 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIOH_DIV4 Setting */ 181 182 #define MXC_F_ADC_CTRL_DATA_ALIGN_POS 17 /**< CTRL_DATA_ALIGN Position */ 183 #define MXC_F_ADC_CTRL_DATA_ALIGN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_DATA_ALIGN_POS)) /**< CTRL_DATA_ALIGN Mask */ 184 #define MXC_V_ADC_CTRL_DATA_ALIGN_LSB_JUSTIFIED ((uint32_t)0x0UL) /**< CTRL_DATA_ALIGN_LSB_JUSTIFIED Value */ 185 #define MXC_S_ADC_CTRL_DATA_ALIGN_LSB_JUSTIFIED (MXC_V_ADC_CTRL_DATA_ALIGN_LSB_JUSTIFIED << MXC_F_ADC_CTRL_DATA_ALIGN_POS) /**< CTRL_DATA_ALIGN_LSB_JUSTIFIED Setting */ 186 #define MXC_V_ADC_CTRL_DATA_ALIGN_MSB_JUSTIFIED ((uint32_t)0x1UL) /**< CTRL_DATA_ALIGN_MSB_JUSTIFIED Value */ 187 #define MXC_S_ADC_CTRL_DATA_ALIGN_MSB_JUSTIFIED (MXC_V_ADC_CTRL_DATA_ALIGN_MSB_JUSTIFIED << MXC_F_ADC_CTRL_DATA_ALIGN_POS) /**< CTRL_DATA_ALIGN_MSB_JUSTIFIED Setting */ 188 189 /**@} end of group ADC_CTRL_Register */ 190 191 /** 192 * @ingroup adc_registers 193 * @defgroup ADC_STATUS ADC_STATUS 194 * @brief ADC Status 195 * @{ 196 */ 197 #define MXC_F_ADC_STATUS_ACTIVE_POS 0 /**< STATUS_ACTIVE Position */ 198 #define MXC_F_ADC_STATUS_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_ACTIVE_POS)) /**< STATUS_ACTIVE Mask */ 199 #define MXC_V_ADC_STATUS_ACTIVE_IDLE ((uint32_t)0x0UL) /**< STATUS_ACTIVE_IDLE Value */ 200 #define MXC_S_ADC_STATUS_ACTIVE_IDLE (MXC_V_ADC_STATUS_ACTIVE_IDLE << MXC_F_ADC_STATUS_ACTIVE_POS) /**< STATUS_ACTIVE_IDLE Setting */ 201 #define MXC_V_ADC_STATUS_ACTIVE_ACTIVE ((uint32_t)0x1UL) /**< STATUS_ACTIVE_ACTIVE Value */ 202 #define MXC_S_ADC_STATUS_ACTIVE_ACTIVE (MXC_V_ADC_STATUS_ACTIVE_ACTIVE << MXC_F_ADC_STATUS_ACTIVE_POS) /**< STATUS_ACTIVE_ACTIVE Setting */ 203 204 #define MXC_F_ADC_STATUS_PWR_UP_ACTIVE_POS 2 /**< STATUS_PWR_UP_ACTIVE Position */ 205 #define MXC_F_ADC_STATUS_PWR_UP_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_PWR_UP_ACTIVE_POS)) /**< STATUS_PWR_UP_ACTIVE Mask */ 206 #define MXC_V_ADC_STATUS_PWR_UP_ACTIVE_NO_DELAY ((uint32_t)0x0UL) /**< STATUS_PWR_UP_ACTIVE_NO_DELAY Value */ 207 #define MXC_S_ADC_STATUS_PWR_UP_ACTIVE_NO_DELAY (MXC_V_ADC_STATUS_PWR_UP_ACTIVE_NO_DELAY << MXC_F_ADC_STATUS_PWR_UP_ACTIVE_POS) /**< STATUS_PWR_UP_ACTIVE_NO_DELAY Setting */ 208 #define MXC_V_ADC_STATUS_PWR_UP_ACTIVE_DELAY_ACTIVE ((uint32_t)0x1UL) /**< STATUS_PWR_UP_ACTIVE_DELAY_ACTIVE Value */ 209 #define MXC_S_ADC_STATUS_PWR_UP_ACTIVE_DELAY_ACTIVE (MXC_V_ADC_STATUS_PWR_UP_ACTIVE_DELAY_ACTIVE << MXC_F_ADC_STATUS_PWR_UP_ACTIVE_POS) /**< STATUS_PWR_UP_ACTIVE_DELAY_ACTIVE Setting */ 210 211 #define MXC_F_ADC_STATUS_OVERFLOW_POS 3 /**< STATUS_OVERFLOW Position */ 212 #define MXC_F_ADC_STATUS_OVERFLOW ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_OVERFLOW_POS)) /**< STATUS_OVERFLOW Mask */ 213 #define MXC_V_ADC_STATUS_OVERFLOW_UNDERFLOW ((uint32_t)0x0UL) /**< STATUS_OVERFLOW_UNDERFLOW Value */ 214 #define MXC_S_ADC_STATUS_OVERFLOW_UNDERFLOW (MXC_V_ADC_STATUS_OVERFLOW_UNDERFLOW << MXC_F_ADC_STATUS_OVERFLOW_POS) /**< STATUS_OVERFLOW_UNDERFLOW Setting */ 215 #define MXC_V_ADC_STATUS_OVERFLOW_OVERFLOW ((uint32_t)0x1UL) /**< STATUS_OVERFLOW_OVERFLOW Value */ 216 #define MXC_S_ADC_STATUS_OVERFLOW_OVERFLOW (MXC_V_ADC_STATUS_OVERFLOW_OVERFLOW << MXC_F_ADC_STATUS_OVERFLOW_POS) /**< STATUS_OVERFLOW_OVERFLOW Setting */ 217 218 /**@} end of group ADC_STATUS_Register */ 219 220 /** 221 * @ingroup adc_registers 222 * @defgroup ADC_DATA ADC_DATA 223 * @brief ADC Output Data 224 * @{ 225 */ 226 #define MXC_F_ADC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 227 #define MXC_F_ADC_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 228 229 /**@} end of group ADC_DATA_Register */ 230 231 /** 232 * @ingroup adc_registers 233 * @defgroup ADC_INTR ADC_INTR 234 * @brief ADC Interrupt Control Register 235 * @{ 236 */ 237 #define MXC_F_ADC_INTR_DONE_IE_POS 0 /**< INTR_DONE_IE Position */ 238 #define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ 239 #define MXC_V_ADC_INTR_DONE_IE_DIS ((uint32_t)0x0UL) /**< INTR_DONE_IE_DIS Value */ 240 #define MXC_S_ADC_INTR_DONE_IE_DIS (MXC_V_ADC_INTR_DONE_IE_DIS << MXC_F_ADC_INTR_DONE_IE_POS) /**< INTR_DONE_IE_DIS Setting */ 241 #define MXC_V_ADC_INTR_DONE_IE_EN ((uint32_t)0x1UL) /**< INTR_DONE_IE_EN Value */ 242 #define MXC_S_ADC_INTR_DONE_IE_EN (MXC_V_ADC_INTR_DONE_IE_EN << MXC_F_ADC_INTR_DONE_IE_POS) /**< INTR_DONE_IE_EN Setting */ 243 244 #define MXC_F_ADC_INTR_REF_READY_IE_POS 1 /**< INTR_REF_READY_IE Position */ 245 #define MXC_F_ADC_INTR_REF_READY_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IE_POS)) /**< INTR_REF_READY_IE Mask */ 246 #define MXC_V_ADC_INTR_REF_READY_IE_DIS ((uint32_t)0x0UL) /**< INTR_REF_READY_IE_DIS Value */ 247 #define MXC_S_ADC_INTR_REF_READY_IE_DIS (MXC_V_ADC_INTR_REF_READY_IE_DIS << MXC_F_ADC_INTR_REF_READY_IE_POS) /**< INTR_REF_READY_IE_DIS Setting */ 248 #define MXC_V_ADC_INTR_REF_READY_IE_EN ((uint32_t)0x1UL) /**< INTR_REF_READY_IE_EN Value */ 249 #define MXC_S_ADC_INTR_REF_READY_IE_EN (MXC_V_ADC_INTR_REF_READY_IE_EN << MXC_F_ADC_INTR_REF_READY_IE_POS) /**< INTR_REF_READY_IE_EN Setting */ 250 251 #define MXC_F_ADC_INTR_HI_LIMIT_IE_POS 2 /**< INTR_HI_LIMIT_IE Position */ 252 #define MXC_F_ADC_INTR_HI_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IE_POS)) /**< INTR_HI_LIMIT_IE Mask */ 253 #define MXC_V_ADC_INTR_HI_LIMIT_IE_DIS ((uint32_t)0x0UL) /**< INTR_HI_LIMIT_IE_DIS Value */ 254 #define MXC_S_ADC_INTR_HI_LIMIT_IE_DIS (MXC_V_ADC_INTR_HI_LIMIT_IE_DIS << MXC_F_ADC_INTR_HI_LIMIT_IE_POS) /**< INTR_HI_LIMIT_IE_DIS Setting */ 255 #define MXC_V_ADC_INTR_HI_LIMIT_IE_EN ((uint32_t)0x1UL) /**< INTR_HI_LIMIT_IE_EN Value */ 256 #define MXC_S_ADC_INTR_HI_LIMIT_IE_EN (MXC_V_ADC_INTR_HI_LIMIT_IE_EN << MXC_F_ADC_INTR_HI_LIMIT_IE_POS) /**< INTR_HI_LIMIT_IE_EN Setting */ 257 258 #define MXC_F_ADC_INTR_LO_LIMIT_IE_POS 3 /**< INTR_LO_LIMIT_IE Position */ 259 #define MXC_F_ADC_INTR_LO_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IE_POS)) /**< INTR_LO_LIMIT_IE Mask */ 260 #define MXC_V_ADC_INTR_LO_LIMIT_IE_DIS ((uint32_t)0x0UL) /**< INTR_LO_LIMIT_IE_DIS Value */ 261 #define MXC_S_ADC_INTR_LO_LIMIT_IE_DIS (MXC_V_ADC_INTR_LO_LIMIT_IE_DIS << MXC_F_ADC_INTR_LO_LIMIT_IE_POS) /**< INTR_LO_LIMIT_IE_DIS Setting */ 262 #define MXC_V_ADC_INTR_LO_LIMIT_IE_EN ((uint32_t)0x1UL) /**< INTR_LO_LIMIT_IE_EN Value */ 263 #define MXC_S_ADC_INTR_LO_LIMIT_IE_EN (MXC_V_ADC_INTR_LO_LIMIT_IE_EN << MXC_F_ADC_INTR_LO_LIMIT_IE_POS) /**< INTR_LO_LIMIT_IE_EN Setting */ 264 265 #define MXC_F_ADC_INTR_OVERFLOW_IE_POS 4 /**< INTR_OVERFLOW_IE Position */ 266 #define MXC_F_ADC_INTR_OVERFLOW_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IE_POS)) /**< INTR_OVERFLOW_IE Mask */ 267 #define MXC_V_ADC_INTR_OVERFLOW_IE_DIS ((uint32_t)0x0UL) /**< INTR_OVERFLOW_IE_DIS Value */ 268 #define MXC_S_ADC_INTR_OVERFLOW_IE_DIS (MXC_V_ADC_INTR_OVERFLOW_IE_DIS << MXC_F_ADC_INTR_OVERFLOW_IE_POS) /**< INTR_OVERFLOW_IE_DIS Setting */ 269 #define MXC_V_ADC_INTR_OVERFLOW_IE_EN ((uint32_t)0x1UL) /**< INTR_OVERFLOW_IE_EN Value */ 270 #define MXC_S_ADC_INTR_OVERFLOW_IE_EN (MXC_V_ADC_INTR_OVERFLOW_IE_EN << MXC_F_ADC_INTR_OVERFLOW_IE_POS) /**< INTR_OVERFLOW_IE_EN Setting */ 271 272 #define MXC_F_ADC_INTR_DONE_IF_POS 16 /**< INTR_DONE_IF Position */ 273 #define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IF_POS)) /**< INTR_DONE_IF Mask */ 274 #define MXC_V_ADC_INTR_DONE_IF_INACTIVE ((uint32_t)0x0UL) /**< INTR_DONE_IF_INACTIVE Value */ 275 #define MXC_S_ADC_INTR_DONE_IF_INACTIVE (MXC_V_ADC_INTR_DONE_IF_INACTIVE << MXC_F_ADC_INTR_DONE_IF_POS) /**< INTR_DONE_IF_INACTIVE Setting */ 276 #define MXC_V_ADC_INTR_DONE_IF_ACTIVE ((uint32_t)0x1UL) /**< INTR_DONE_IF_ACTIVE Value */ 277 #define MXC_S_ADC_INTR_DONE_IF_ACTIVE (MXC_V_ADC_INTR_DONE_IF_ACTIVE << MXC_F_ADC_INTR_DONE_IF_POS) /**< INTR_DONE_IF_ACTIVE Setting */ 278 279 #define MXC_F_ADC_INTR_REF_READY_IF_POS 17 /**< INTR_REF_READY_IF Position */ 280 #define MXC_F_ADC_INTR_REF_READY_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IF_POS)) /**< INTR_REF_READY_IF Mask */ 281 #define MXC_V_ADC_INTR_REF_READY_IF_INACTIVE ((uint32_t)0x0UL) /**< INTR_REF_READY_IF_INACTIVE Value */ 282 #define MXC_S_ADC_INTR_REF_READY_IF_INACTIVE (MXC_V_ADC_INTR_REF_READY_IF_INACTIVE << MXC_F_ADC_INTR_REF_READY_IF_POS) /**< INTR_REF_READY_IF_INACTIVE Setting */ 283 #define MXC_V_ADC_INTR_REF_READY_IF_ACTIVE ((uint32_t)0x1UL) /**< INTR_REF_READY_IF_ACTIVE Value */ 284 #define MXC_S_ADC_INTR_REF_READY_IF_ACTIVE (MXC_V_ADC_INTR_REF_READY_IF_ACTIVE << MXC_F_ADC_INTR_REF_READY_IF_POS) /**< INTR_REF_READY_IF_ACTIVE Setting */ 285 286 #define MXC_F_ADC_INTR_HI_LIMIT_IF_POS 18 /**< INTR_HI_LIMIT_IF Position */ 287 #define MXC_F_ADC_INTR_HI_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IF_POS)) /**< INTR_HI_LIMIT_IF Mask */ 288 #define MXC_V_ADC_INTR_HI_LIMIT_IF_INACTIVE ((uint32_t)0x0UL) /**< INTR_HI_LIMIT_IF_INACTIVE Value */ 289 #define MXC_S_ADC_INTR_HI_LIMIT_IF_INACTIVE (MXC_V_ADC_INTR_HI_LIMIT_IF_INACTIVE << MXC_F_ADC_INTR_HI_LIMIT_IF_POS) /**< INTR_HI_LIMIT_IF_INACTIVE Setting */ 290 #define MXC_V_ADC_INTR_HI_LIMIT_IF_ACTIVE ((uint32_t)0x1UL) /**< INTR_HI_LIMIT_IF_ACTIVE Value */ 291 #define MXC_S_ADC_INTR_HI_LIMIT_IF_ACTIVE (MXC_V_ADC_INTR_HI_LIMIT_IF_ACTIVE << MXC_F_ADC_INTR_HI_LIMIT_IF_POS) /**< INTR_HI_LIMIT_IF_ACTIVE Setting */ 292 293 #define MXC_F_ADC_INTR_LO_LIMIT_IF_POS 19 /**< INTR_LO_LIMIT_IF Position */ 294 #define MXC_F_ADC_INTR_LO_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IF_POS)) /**< INTR_LO_LIMIT_IF Mask */ 295 #define MXC_V_ADC_INTR_LO_LIMIT_IF_INACTIVE ((uint32_t)0x0UL) /**< INTR_LO_LIMIT_IF_INACTIVE Value */ 296 #define MXC_S_ADC_INTR_LO_LIMIT_IF_INACTIVE (MXC_V_ADC_INTR_LO_LIMIT_IF_INACTIVE << MXC_F_ADC_INTR_LO_LIMIT_IF_POS) /**< INTR_LO_LIMIT_IF_INACTIVE Setting */ 297 #define MXC_V_ADC_INTR_LO_LIMIT_IF_ACTIVE ((uint32_t)0x1UL) /**< INTR_LO_LIMIT_IF_ACTIVE Value */ 298 #define MXC_S_ADC_INTR_LO_LIMIT_IF_ACTIVE (MXC_V_ADC_INTR_LO_LIMIT_IF_ACTIVE << MXC_F_ADC_INTR_LO_LIMIT_IF_POS) /**< INTR_LO_LIMIT_IF_ACTIVE Setting */ 299 300 #define MXC_F_ADC_INTR_OVERFLOW_IF_POS 20 /**< INTR_OVERFLOW_IF Position */ 301 #define MXC_F_ADC_INTR_OVERFLOW_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IF_POS)) /**< INTR_OVERFLOW_IF Mask */ 302 #define MXC_V_ADC_INTR_OVERFLOW_IF_INACTIVE ((uint32_t)0x0UL) /**< INTR_OVERFLOW_IF_INACTIVE Value */ 303 #define MXC_S_ADC_INTR_OVERFLOW_IF_INACTIVE (MXC_V_ADC_INTR_OVERFLOW_IF_INACTIVE << MXC_F_ADC_INTR_OVERFLOW_IF_POS) /**< INTR_OVERFLOW_IF_INACTIVE Setting */ 304 #define MXC_V_ADC_INTR_OVERFLOW_IF_ACTIVE ((uint32_t)0x1UL) /**< INTR_OVERFLOW_IF_ACTIVE Value */ 305 #define MXC_S_ADC_INTR_OVERFLOW_IF_ACTIVE (MXC_V_ADC_INTR_OVERFLOW_IF_ACTIVE << MXC_F_ADC_INTR_OVERFLOW_IF_POS) /**< INTR_OVERFLOW_IF_ACTIVE Setting */ 306 307 #define MXC_F_ADC_INTR_PENDING_POS 22 /**< INTR_PENDING Position */ 308 #define MXC_F_ADC_INTR_PENDING ((uint32_t)(0x1UL << MXC_F_ADC_INTR_PENDING_POS)) /**< INTR_PENDING Mask */ 309 #define MXC_V_ADC_INTR_PENDING_NO_INT ((uint32_t)0x0UL) /**< INTR_PENDING_NO_INT Value */ 310 #define MXC_S_ADC_INTR_PENDING_NO_INT (MXC_V_ADC_INTR_PENDING_NO_INT << MXC_F_ADC_INTR_PENDING_POS) /**< INTR_PENDING_NO_INT Setting */ 311 #define MXC_V_ADC_INTR_PENDING_INT_PENDING ((uint32_t)0x1UL) /**< INTR_PENDING_INT_PENDING Value */ 312 #define MXC_S_ADC_INTR_PENDING_INT_PENDING (MXC_V_ADC_INTR_PENDING_INT_PENDING << MXC_F_ADC_INTR_PENDING_POS) /**< INTR_PENDING_INT_PENDING Setting */ 313 314 /**@} end of group ADC_INTR_Register */ 315 316 /** 317 * @ingroup adc_registers 318 * @defgroup ADC_LIMIT ADC_LIMIT 319 * @brief ADC Limit 320 * @{ 321 */ 322 #define MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS 0 /**< LIMIT_CH_LO_LIMIT Position */ 323 #define MXC_F_ADC_LIMIT_CH_LO_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS)) /**< LIMIT_CH_LO_LIMIT Mask */ 324 325 #define MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS 12 /**< LIMIT_CH_HI_LIMIT Position */ 326 #define MXC_F_ADC_LIMIT_CH_HI_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS)) /**< LIMIT_CH_HI_LIMIT Mask */ 327 328 #define MXC_F_ADC_LIMIT_CH_SEL_POS 24 /**< LIMIT_CH_SEL Position */ 329 #define MXC_F_ADC_LIMIT_CH_SEL ((uint32_t)(0xFUL << MXC_F_ADC_LIMIT_CH_SEL_POS)) /**< LIMIT_CH_SEL Mask */ 330 #define MXC_V_ADC_LIMIT_CH_SEL_AIN0 ((uint32_t)0x0UL) /**< LIMIT_CH_SEL_AIN0 Value */ 331 #define MXC_S_ADC_LIMIT_CH_SEL_AIN0 (MXC_V_ADC_LIMIT_CH_SEL_AIN0 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN0 Setting */ 332 #define MXC_V_ADC_LIMIT_CH_SEL_AIN1 ((uint32_t)0x1UL) /**< LIMIT_CH_SEL_AIN1 Value */ 333 #define MXC_S_ADC_LIMIT_CH_SEL_AIN1 (MXC_V_ADC_LIMIT_CH_SEL_AIN1 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN1 Setting */ 334 #define MXC_V_ADC_LIMIT_CH_SEL_AIN2 ((uint32_t)0x2UL) /**< LIMIT_CH_SEL_AIN2 Value */ 335 #define MXC_S_ADC_LIMIT_CH_SEL_AIN2 (MXC_V_ADC_LIMIT_CH_SEL_AIN2 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN2 Setting */ 336 #define MXC_V_ADC_LIMIT_CH_SEL_AIN3 ((uint32_t)0x3UL) /**< LIMIT_CH_SEL_AIN3 Value */ 337 #define MXC_S_ADC_LIMIT_CH_SEL_AIN3 (MXC_V_ADC_LIMIT_CH_SEL_AIN3 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN3 Setting */ 338 #define MXC_V_ADC_LIMIT_CH_SEL_AIN4 ((uint32_t)0x4UL) /**< LIMIT_CH_SEL_AIN4 Value */ 339 #define MXC_S_ADC_LIMIT_CH_SEL_AIN4 (MXC_V_ADC_LIMIT_CH_SEL_AIN4 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN4 Setting */ 340 #define MXC_V_ADC_LIMIT_CH_SEL_AIN5 ((uint32_t)0x5UL) /**< LIMIT_CH_SEL_AIN5 Value */ 341 #define MXC_S_ADC_LIMIT_CH_SEL_AIN5 (MXC_V_ADC_LIMIT_CH_SEL_AIN5 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN5 Setting */ 342 #define MXC_V_ADC_LIMIT_CH_SEL_AIN6 ((uint32_t)0x6UL) /**< LIMIT_CH_SEL_AIN6 Value */ 343 #define MXC_S_ADC_LIMIT_CH_SEL_AIN6 (MXC_V_ADC_LIMIT_CH_SEL_AIN6 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN6 Setting */ 344 #define MXC_V_ADC_LIMIT_CH_SEL_AIN7 ((uint32_t)0x7UL) /**< LIMIT_CH_SEL_AIN7 Value */ 345 #define MXC_S_ADC_LIMIT_CH_SEL_AIN7 (MXC_V_ADC_LIMIT_CH_SEL_AIN7 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN7 Setting */ 346 #define MXC_V_ADC_LIMIT_CH_SEL_AIN8 ((uint32_t)0x8UL) /**< LIMIT_CH_SEL_AIN8 Value */ 347 #define MXC_S_ADC_LIMIT_CH_SEL_AIN8 (MXC_V_ADC_LIMIT_CH_SEL_AIN8 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN8 Setting */ 348 #define MXC_V_ADC_LIMIT_CH_SEL_AIN9 ((uint32_t)0x9UL) /**< LIMIT_CH_SEL_AIN9 Value */ 349 #define MXC_S_ADC_LIMIT_CH_SEL_AIN9 (MXC_V_ADC_LIMIT_CH_SEL_AIN9 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN9 Setting */ 350 #define MXC_V_ADC_LIMIT_CH_SEL_AIN10 ((uint32_t)0xAUL) /**< LIMIT_CH_SEL_AIN10 Value */ 351 #define MXC_S_ADC_LIMIT_CH_SEL_AIN10 (MXC_V_ADC_LIMIT_CH_SEL_AIN10 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN10 Setting */ 352 #define MXC_V_ADC_LIMIT_CH_SEL_AIN11 ((uint32_t)0xBUL) /**< LIMIT_CH_SEL_AIN11 Value */ 353 #define MXC_S_ADC_LIMIT_CH_SEL_AIN11 (MXC_V_ADC_LIMIT_CH_SEL_AIN11 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN11 Setting */ 354 #define MXC_V_ADC_LIMIT_CH_SEL_AIN12 ((uint32_t)0xCUL) /**< LIMIT_CH_SEL_AIN12 Value */ 355 #define MXC_S_ADC_LIMIT_CH_SEL_AIN12 (MXC_V_ADC_LIMIT_CH_SEL_AIN12 << MXC_F_ADC_LIMIT_CH_SEL_POS) /**< LIMIT_CH_SEL_AIN12 Setting */ 356 357 #define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS 28 /**< LIMIT_CH_LO_LIMIT_EN Position */ 358 #define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS)) /**< LIMIT_CH_LO_LIMIT_EN Mask */ 359 #define MXC_V_ADC_LIMIT_CH_LO_LIMIT_EN_DIS ((uint32_t)0x0UL) /**< LIMIT_CH_LO_LIMIT_EN_DIS Value */ 360 #define MXC_S_ADC_LIMIT_CH_LO_LIMIT_EN_DIS (MXC_V_ADC_LIMIT_CH_LO_LIMIT_EN_DIS << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS) /**< LIMIT_CH_LO_LIMIT_EN_DIS Setting */ 361 #define MXC_V_ADC_LIMIT_CH_LO_LIMIT_EN_EN ((uint32_t)0x1UL) /**< LIMIT_CH_LO_LIMIT_EN_EN Value */ 362 #define MXC_S_ADC_LIMIT_CH_LO_LIMIT_EN_EN (MXC_V_ADC_LIMIT_CH_LO_LIMIT_EN_EN << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS) /**< LIMIT_CH_LO_LIMIT_EN_EN Setting */ 363 364 #define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS 29 /**< LIMIT_CH_HI_LIMIT_EN Position */ 365 #define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS)) /**< LIMIT_CH_HI_LIMIT_EN Mask */ 366 #define MXC_V_ADC_LIMIT_CH_HI_LIMIT_EN_DIS ((uint32_t)0x0UL) /**< LIMIT_CH_HI_LIMIT_EN_DIS Value */ 367 #define MXC_S_ADC_LIMIT_CH_HI_LIMIT_EN_DIS (MXC_V_ADC_LIMIT_CH_HI_LIMIT_EN_DIS << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS) /**< LIMIT_CH_HI_LIMIT_EN_DIS Setting */ 368 #define MXC_V_ADC_LIMIT_CH_HI_LIMIT_EN_EN ((uint32_t)0x1UL) /**< LIMIT_CH_HI_LIMIT_EN_EN Value */ 369 #define MXC_S_ADC_LIMIT_CH_HI_LIMIT_EN_EN (MXC_V_ADC_LIMIT_CH_HI_LIMIT_EN_EN << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS) /**< LIMIT_CH_HI_LIMIT_EN_EN Setting */ 370 371 /**@} end of group ADC_LIMIT_Register */ 372 373 #ifdef __cplusplus 374 } 375 #endif 376 377 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_ADC_REGS_H_ 378
