1 /** 2 * @file uart_revc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the UART_REVC Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _UART_REVC_REGS_H_ 27 #define _UART_REVC_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup uart_revc 65 * @defgroup uart_revc_registers UART_REVC_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the UART_REVC Peripheral Module. 67 * @details UART 68 */ 69 70 /** 71 * @ingroup uart_revc_registers 72 * Structure type to access the UART_REVC Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> UART_REVC CTRL Register */ 76 __I uint32_t status; /**< <tt>\b 0x04:</tt> UART_REVC STATUS Register */ 77 __IO uint32_t int_en; /**< <tt>\b 0x08:</tt> UART_REVC INT_EN Register */ 78 __IO uint32_t int_fl; /**< <tt>\b 0x0C:</tt> UART_REVC INT_FL Register */ 79 __IO uint32_t baud0; /**< <tt>\b 0x10:</tt> UART_REVC BAUD0 Register */ 80 __IO uint32_t baud1; /**< <tt>\b 0x14:</tt> UART_REVC BAUD1 Register */ 81 __R uint32_t rsv_0x18; 82 __IO uint32_t pin; /**< <tt>\b 0x1C:</tt> UART_REVC PIN Register */ 83 __IO uint32_t fifo; /**< <tt>\b 0x20:</tt> UART_REVC FIFO Register */ 84 __R uint32_t rsv_0x24_0x2f[3]; 85 __IO uint32_t dma; /**< <tt>\b 0x30:</tt> UART_REVC DMA Register */ 86 } mxc_uart_revc_regs_t; 87 88 /* Register offsets for module UART_REVC */ 89 /** 90 * @ingroup uart_revc_registers 91 * @defgroup UART_REVC_Register_Offsets Register Offsets 92 * @brief UART_REVC Peripheral Register Offsets from the UART_REVC Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_UART_REVC_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART_REVC Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_UART_REVC_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART_REVC Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_UART_REVC_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART_REVC Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_UART_REVC_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART_REVC Base Address: <tt> 0x000C</tt> */ 99 #define MXC_R_UART_REVC_BAUD0 ((uint32_t)0x00000010UL) /**< Offset from UART_REVC Base Address: <tt> 0x0010</tt> */ 100 #define MXC_R_UART_REVC_BAUD1 ((uint32_t)0x00000014UL) /**< Offset from UART_REVC Base Address: <tt> 0x0014</tt> */ 101 #define MXC_R_UART_REVC_PIN ((uint32_t)0x0000001CUL) /**< Offset from UART_REVC Base Address: <tt> 0x001C</tt> */ 102 #define MXC_R_UART_REVC_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART_REVC Base Address: <tt> 0x0020</tt> */ 103 #define MXC_R_UART_REVC_DMA ((uint32_t)0x00000030UL) /**< Offset from UART_REVC Base Address: <tt> 0x0030</tt> */ 104 /**@} end of group uart_revc_registers */ 105 106 /** 107 * @ingroup uart_revc_registers 108 * @defgroup UART_REVC_CTRL UART_REVC_CTRL 109 * @brief Control Register. 110 * @{ 111 */ 112 #define MXC_F_UART_REVC_CTRL_RXTHD_POS 0 /**< CTRL_RXTHD Position */ 113 #define MXC_F_UART_REVC_CTRL_RXTHD ((uint32_t)(0xFUL << MXC_F_UART_REVC_CTRL_RXTHD_POS)) /**< CTRL_RXTHD Mask */ 114 115 #define MXC_F_UART_REVC_CTRL_PARITY_EN_POS 4 /**< CTRL_PARITY_EN Position */ 116 #define MXC_F_UART_REVC_CTRL_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_REVC_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */ 117 118 #define MXC_F_UART_REVC_CTRL_PARITY_POS 5 /**< CTRL_PARITY Position */ 119 #define MXC_F_UART_REVC_CTRL_PARITY ((uint32_t)(0x1UL << MXC_F_UART_REVC_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */ 120 121 #define MXC_F_UART_REVC_CTRL_PARMD_POS 6 /**< CTRL_PARMD Position */ 122 #define MXC_F_UART_REVC_CTRL_PARMD ((uint32_t)(0x1UL << MXC_F_UART_REVC_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */ 123 124 #define MXC_F_UART_REVC_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ 125 #define MXC_F_UART_REVC_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVC_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ 126 127 #define MXC_F_UART_REVC_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ 128 #define MXC_F_UART_REVC_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVC_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ 129 130 #define MXC_F_UART_REVC_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ 131 #define MXC_F_UART_REVC_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_REVC_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ 132 #define MXC_V_UART_REVC_CTRL_CHAR_SIZE_5 ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */ 133 #define MXC_S_UART_REVC_CTRL_CHAR_SIZE_5 (MXC_V_UART_REVC_CTRL_CHAR_SIZE_5 << MXC_F_UART_REVC_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */ 134 #define MXC_V_UART_REVC_CTRL_CHAR_SIZE_6 ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */ 135 #define MXC_S_UART_REVC_CTRL_CHAR_SIZE_6 (MXC_V_UART_REVC_CTRL_CHAR_SIZE_6 << MXC_F_UART_REVC_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */ 136 #define MXC_V_UART_REVC_CTRL_CHAR_SIZE_7 ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */ 137 #define MXC_S_UART_REVC_CTRL_CHAR_SIZE_7 (MXC_V_UART_REVC_CTRL_CHAR_SIZE_7 << MXC_F_UART_REVC_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */ 138 #define MXC_V_UART_REVC_CTRL_CHAR_SIZE_8 ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */ 139 #define MXC_S_UART_REVC_CTRL_CHAR_SIZE_8 (MXC_V_UART_REVC_CTRL_CHAR_SIZE_8 << MXC_F_UART_REVC_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */ 140 141 #define MXC_F_UART_REVC_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ 142 #define MXC_F_UART_REVC_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_REVC_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ 143 144 #define MXC_F_UART_REVC_CTRL_FLOW_CTRL_POS 13 /**< CTRL_FLOW_CTRL Position */ 145 #define MXC_F_UART_REVC_CTRL_FLOW_CTRL ((uint32_t)(0x1UL << MXC_F_UART_REVC_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */ 146 147 /**@} end of group UART_REVC_CTRL_Register */ 148 149 /** 150 * @ingroup uart_revc_registers 151 * @defgroup UART_REVC_STATUS UART_REVC_STATUS 152 * @brief Status Register. 153 * @{ 154 */ 155 #define MXC_F_UART_REVC_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ 156 #define MXC_F_UART_REVC_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVC_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ 157 158 #define MXC_F_UART_REVC_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ 159 #define MXC_F_UART_REVC_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVC_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ 160 161 #define MXC_F_UART_REVC_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */ 162 #define MXC_F_UART_REVC_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVC_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ 163 164 #define MXC_F_UART_REVC_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ 165 #define MXC_F_UART_REVC_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVC_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 166 167 #define MXC_F_UART_REVC_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */ 168 #define MXC_F_UART_REVC_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVC_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ 169 170 #define MXC_F_UART_REVC_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ 171 #define MXC_F_UART_REVC_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVC_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 172 173 #define MXC_F_UART_REVC_STATUS_RX_FIFO_CNT_POS 8 /**< STATUS_RX_FIFO_CNT Position */ 174 #define MXC_F_UART_REVC_STATUS_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_UART_REVC_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT Mask */ 175 176 #define MXC_F_UART_REVC_STATUS_TX_FIFO_CNT_POS 12 /**< STATUS_TX_FIFO_CNT Position */ 177 #define MXC_F_UART_REVC_STATUS_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_UART_REVC_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT Mask */ 178 179 /**@} end of group UART_REVC_STATUS_Register */ 180 181 /** 182 * @ingroup uart_revc_registers 183 * @defgroup UART_REVC_INT_EN UART_REVC_INT_EN 184 * @brief Interrupt Enable Register. 185 * @{ 186 */ 187 #define MXC_F_UART_REVC_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ 188 #define MXC_F_UART_REVC_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ 189 190 #define MXC_F_UART_REVC_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ 191 #define MXC_F_UART_REVC_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ 192 193 #define MXC_F_UART_REVC_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ 194 #define MXC_F_UART_REVC_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ 195 196 #define MXC_F_UART_REVC_INT_EN_RX_FIFO_THRESH_POS 4 /**< INT_EN_RX_FIFO_THRESH Position */ 197 #define MXC_F_UART_REVC_INT_EN_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_EN_RX_FIFO_THRESH_POS)) /**< INT_EN_RX_FIFO_THRESH Mask */ 198 199 #define MXC_F_UART_REVC_INT_EN_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */ 200 #define MXC_F_UART_REVC_INT_EN_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_EN_TX_FIFO_ALMOST_EMPTY Mask */ 201 202 #define MXC_F_UART_REVC_INT_EN_TX_FIFO_HALF_EMPTY_POS 6 /**< INT_EN_TX_FIFO_HALF_EMPTY Position */ 203 #define MXC_F_UART_REVC_INT_EN_TX_FIFO_HALF_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_EN_TX_FIFO_HALF_EMPTY_POS)) /**< INT_EN_TX_FIFO_HALF_EMPTY Mask */ 204 205 /**@} end of group UART_REVC_INT_EN_Register */ 206 207 /** 208 * @ingroup uart_revc_registers 209 * @defgroup UART_REVC_INT_FL UART_REVC_INT_FL 210 * @brief Interrupt Status Flags. 211 * @{ 212 */ 213 #define MXC_F_UART_REVC_INT_FL_RX_FRAME_ERROR_POS 0 /**< INT_FL_RX_FRAME_ERROR Position */ 214 #define MXC_F_UART_REVC_INT_FL_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_FL_RX_FRAME_ERROR_POS)) /**< INT_FL_RX_FRAME_ERROR Mask */ 215 216 #define MXC_F_UART_REVC_INT_FL_RX_PARITY_ERROR_POS 1 /**< INT_FL_RX_PARITY_ERROR Position */ 217 #define MXC_F_UART_REVC_INT_FL_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_FL_RX_PARITY_ERROR_POS)) /**< INT_FL_RX_PARITY_ERROR Mask */ 218 219 #define MXC_F_UART_REVC_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */ 220 #define MXC_F_UART_REVC_INT_FL_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN Mask */ 221 222 #define MXC_F_UART_REVC_INT_FL_RX_FIFO_THRESH_POS 4 /**< INT_FL_RX_FIFO_THRESH Position */ 223 #define MXC_F_UART_REVC_INT_FL_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_FL_RX_FIFO_THRESH_POS)) /**< INT_FL_RX_FIFO_THRESH Mask */ 224 225 #define MXC_F_UART_REVC_INT_FL_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */ 226 #define MXC_F_UART_REVC_INT_FL_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_FL_TX_FIFO_ALMOST_EMPTY Mask */ 227 228 #define MXC_F_UART_REVC_INT_FL_TX_FIFO_HALF_EMPTY_POS 6 /**< INT_FL_TX_FIFO_HALF_EMPTY Position */ 229 #define MXC_F_UART_REVC_INT_FL_TX_FIFO_HALF_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVC_INT_FL_TX_FIFO_HALF_EMPTY_POS)) /**< INT_FL_TX_FIFO_HALF_EMPTY Mask */ 230 231 /**@} end of group UART_REVC_INT_FL_Register */ 232 233 /** 234 * @ingroup uart_revc_registers 235 * @defgroup UART_REVC_BAUD0 UART_REVC_BAUD0 236 * @brief Baud rate register. Integer portion. 237 * @{ 238 */ 239 #define MXC_F_UART_REVC_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ 240 #define MXC_F_UART_REVC_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_REVC_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ 241 242 /**@} end of group UART_REVC_BAUD0_Register */ 243 244 /** 245 * @ingroup uart_revc_registers 246 * @defgroup UART_REVC_BAUD1 UART_REVC_BAUD1 247 * @brief Baud rate register. Decimal Setting. 248 * @{ 249 */ 250 #define MXC_F_UART_REVC_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ 251 #define MXC_F_UART_REVC_BAUD1_DBAUD ((uint32_t)(0x7FUL << MXC_F_UART_REVC_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ 252 253 /**@} end of group UART_REVC_BAUD1_Register */ 254 255 /** 256 * @ingroup uart_revc_registers 257 * @defgroup UART_REVC_PIN UART_REVC_PIN 258 * @brief UART Pin Control Register. 259 * @{ 260 */ 261 #define MXC_F_UART_REVC_PIN_CTS_POS 0 /**< PIN_CTS Position */ 262 #define MXC_F_UART_REVC_PIN_CTS ((uint32_t)(0x1UL << MXC_F_UART_REVC_PIN_CTS_POS)) /**< PIN_CTS Mask */ 263 264 #define MXC_F_UART_REVC_PIN_RTS_POS 1 /**< PIN_RTS Position */ 265 #define MXC_F_UART_REVC_PIN_RTS ((uint32_t)(0x1UL << MXC_F_UART_REVC_PIN_RTS_POS)) /**< PIN_RTS Mask */ 266 267 /**@} end of group UART_REVC_PIN_Register */ 268 269 /** 270 * @ingroup uart_revc_registers 271 * @defgroup UART_REVC_FIFO UART_REVC_FIFO 272 * @brief FIFO Data buffer. 273 * @{ 274 */ 275 #define MXC_F_UART_REVC_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ 276 #define MXC_F_UART_REVC_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_REVC_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ 277 278 #define MXC_F_UART_REVC_FIFO_PARITY_POS 8 /**< FIFO_PARITY Position */ 279 #define MXC_F_UART_REVC_FIFO_PARITY ((uint32_t)(0x1UL << MXC_F_UART_REVC_FIFO_PARITY_POS)) /**< FIFO_PARITY Mask */ 280 281 /**@} end of group UART_REVC_FIFO_Register */ 282 283 /** 284 * @ingroup uart_revc_registers 285 * @defgroup UART_REVC_DMA UART_REVC_DMA 286 * @brief DMA Configuration. 287 * @{ 288 */ 289 #define MXC_F_UART_REVC_DMA_TXDMA_LEVEL_POS 0 /**< DMA_TXDMA_LEVEL Position */ 290 #define MXC_F_UART_REVC_DMA_TXDMA_LEVEL ((uint32_t)(0xFUL << MXC_F_UART_REVC_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */ 291 292 #define MXC_F_UART_REVC_DMA_TXDMA_EN_POS 4 /**< DMA_TXDMA_EN Position */ 293 #define MXC_F_UART_REVC_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_REVC_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */ 294 295 #define MXC_F_UART_REVC_DMA_RXDMA_LEVEL_POS 5 /**< DMA_RXDMA_LEVEL Position */ 296 #define MXC_F_UART_REVC_DMA_RXDMA_LEVEL ((uint32_t)(0xFUL << MXC_F_UART_REVC_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL Mask */ 297 298 #define MXC_F_UART_REVC_DMA_RXDMA_EN_POS 9 /**< DMA_RXDMA_EN Position */ 299 #define MXC_F_UART_REVC_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_REVC_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ 300 301 /**@} end of group UART_REVC_DMA_Register */ 302 303 #ifdef __cplusplus 304 } 305 #endif 306 307 #endif /* _UART_REVC_REGS_H_ */ 308
