1 /** 2 * @file uart_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup uart_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_UART_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_UART_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup uart 67 * @defgroup uart_registers UART_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 69 * @details UART 70 */ 71 72 /** 73 * @ingroup uart_registers 74 * Structure type to access the UART Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> UART CTRL Register */ 78 __I uint32_t stat; /**< <tt>\b 0x04:</tt> UART STAT Register */ 79 __IO uint32_t int_en; /**< <tt>\b 0x08:</tt> UART INT_EN Register */ 80 __IO uint32_t int_stat; /**< <tt>\b 0x0C:</tt> UART INT_STAT Register */ 81 __IO uint32_t baud0; /**< <tt>\b 0x10:</tt> UART BAUD0 Register */ 82 __IO uint32_t baud1; /**< <tt>\b 0x14:</tt> UART BAUD1 Register */ 83 __R uint32_t rsv_0x18_0x1f[2]; 84 __IO uint32_t data; /**< <tt>\b 0x20:</tt> UART DATA Register */ 85 __R uint32_t rsv_0x24_0x2f[3]; 86 __IO uint32_t dma; /**< <tt>\b 0x30:</tt> UART DMA Register */ 87 } mxc_uart_regs_t; 88 89 /* Register offsets for module UART */ 90 /** 91 * @ingroup uart_registers 92 * @defgroup UART_Register_Offsets Register Offsets 93 * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_UART_STAT ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */ 98 #define MXC_R_UART_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */ 99 #define MXC_R_UART_INT_STAT ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */ 100 #define MXC_R_UART_BAUD0 ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */ 101 #define MXC_R_UART_BAUD1 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */ 102 #define MXC_R_UART_DATA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */ 103 #define MXC_R_UART_DMA ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: <tt> 0x0030</tt> */ 104 /**@} end of group uart_registers */ 105 106 /** 107 * @ingroup uart_registers 108 * @defgroup UART_CTRL UART_CTRL 109 * @brief Control Register. 110 * @{ 111 */ 112 #define MXC_F_UART_CTRL_RXTHD_POS 0 /**< CTRL_RXTHD Position */ 113 #define MXC_F_UART_CTRL_RXTHD ((uint32_t)(0xFUL << MXC_F_UART_CTRL_RXTHD_POS)) /**< CTRL_RXTHD Mask */ 114 115 #define MXC_F_UART_CTRL_PAREN_POS 4 /**< CTRL_PAREN Position */ 116 #define MXC_F_UART_CTRL_PAREN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAREN_POS)) /**< CTRL_PAREN Mask */ 117 118 #define MXC_F_UART_CTRL_PAREO_POS 5 /**< CTRL_PAREO Position */ 119 #define MXC_F_UART_CTRL_PAREO ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAREO_POS)) /**< CTRL_PAREO Mask */ 120 121 #define MXC_F_UART_CTRL_PARMD_POS 6 /**< CTRL_PARMD Position */ 122 #define MXC_F_UART_CTRL_PARMD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */ 123 124 #define MXC_F_UART_CTRL_TXFLUSH_POS 8 /**< CTRL_TXFLUSH Position */ 125 #define MXC_F_UART_CTRL_TXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TXFLUSH_POS)) /**< CTRL_TXFLUSH Mask */ 126 127 #define MXC_F_UART_CTRL_RXFLUSH_POS 9 /**< CTRL_RXFLUSH Position */ 128 #define MXC_F_UART_CTRL_RXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RXFLUSH_POS)) /**< CTRL_RXFLUSH Mask */ 129 130 #define MXC_F_UART_CTRL_SIZE_POS 10 /**< CTRL_SIZE Position */ 131 #define MXC_F_UART_CTRL_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_SIZE_POS)) /**< CTRL_SIZE Mask */ 132 #define MXC_V_UART_CTRL_SIZE_5 ((uint32_t)0x0UL) /**< CTRL_SIZE_5 Value */ 133 #define MXC_S_UART_CTRL_SIZE_5 (MXC_V_UART_CTRL_SIZE_5 << MXC_F_UART_CTRL_SIZE_POS) /**< CTRL_SIZE_5 Setting */ 134 #define MXC_V_UART_CTRL_SIZE_6 ((uint32_t)0x1UL) /**< CTRL_SIZE_6 Value */ 135 #define MXC_S_UART_CTRL_SIZE_6 (MXC_V_UART_CTRL_SIZE_6 << MXC_F_UART_CTRL_SIZE_POS) /**< CTRL_SIZE_6 Setting */ 136 #define MXC_V_UART_CTRL_SIZE_7 ((uint32_t)0x2UL) /**< CTRL_SIZE_7 Value */ 137 #define MXC_S_UART_CTRL_SIZE_7 (MXC_V_UART_CTRL_SIZE_7 << MXC_F_UART_CTRL_SIZE_POS) /**< CTRL_SIZE_7 Setting */ 138 #define MXC_V_UART_CTRL_SIZE_8 ((uint32_t)0x3UL) /**< CTRL_SIZE_8 Value */ 139 #define MXC_S_UART_CTRL_SIZE_8 (MXC_V_UART_CTRL_SIZE_8 << MXC_F_UART_CTRL_SIZE_POS) /**< CTRL_SIZE_8 Setting */ 140 141 #define MXC_F_UART_CTRL_STOP_POS 12 /**< CTRL_STOP Position */ 142 #define MXC_F_UART_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOP_POS)) /**< CTRL_STOP Mask */ 143 144 /**@} end of group UART_CTRL_Register */ 145 146 /** 147 * @ingroup uart_registers 148 * @defgroup UART_STAT UART_STAT 149 * @brief Status Register. 150 * @{ 151 */ 152 #define MXC_F_UART_STAT_TXBUSY_POS 0 /**< STAT_TXBUSY Position */ 153 #define MXC_F_UART_STAT_TXBUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TXBUSY_POS)) /**< STAT_TXBUSY Mask */ 154 155 #define MXC_F_UART_STAT_RXBUSY_POS 1 /**< STAT_RXBUSY Position */ 156 #define MXC_F_UART_STAT_RXBUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RXBUSY_POS)) /**< STAT_RXBUSY Mask */ 157 158 #define MXC_F_UART_STAT_RXEMPTY_POS 4 /**< STAT_RXEMPTY Position */ 159 #define MXC_F_UART_STAT_RXEMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RXEMPTY_POS)) /**< STAT_RXEMPTY Mask */ 160 161 #define MXC_F_UART_STAT_RXFULL_POS 5 /**< STAT_RXFULL Position */ 162 #define MXC_F_UART_STAT_RXFULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_RXFULL_POS)) /**< STAT_RXFULL Mask */ 163 164 #define MXC_F_UART_STAT_TXEMPTY_POS 6 /**< STAT_TXEMPTY Position */ 165 #define MXC_F_UART_STAT_TXEMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TXEMPTY_POS)) /**< STAT_TXEMPTY Mask */ 166 167 #define MXC_F_UART_STAT_TXFULL_POS 7 /**< STAT_TXFULL Position */ 168 #define MXC_F_UART_STAT_TXFULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_TXFULL_POS)) /**< STAT_TXFULL Mask */ 169 170 #define MXC_F_UART_STAT_RXELT_POS 8 /**< STAT_RXELT Position */ 171 #define MXC_F_UART_STAT_RXELT ((uint32_t)(0xFUL << MXC_F_UART_STAT_RXELT_POS)) /**< STAT_RXELT Mask */ 172 173 #define MXC_F_UART_STAT_TXELT_POS 12 /**< STAT_TXELT Position */ 174 #define MXC_F_UART_STAT_TXELT ((uint32_t)(0xFUL << MXC_F_UART_STAT_TXELT_POS)) /**< STAT_TXELT Mask */ 175 176 /**@} end of group UART_STAT_Register */ 177 178 /** 179 * @ingroup uart_registers 180 * @defgroup UART_INT_EN UART_INT_EN 181 * @brief Interrupt Enable Register. 182 * @{ 183 */ 184 #define MXC_F_UART_INT_EN_FRAMIE_POS 0 /**< INT_EN_FRAMIE Position */ 185 #define MXC_F_UART_INT_EN_FRAMIE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_FRAMIE_POS)) /**< INT_EN_FRAMIE Mask */ 186 187 #define MXC_F_UART_INT_EN_PARITYIE_POS 1 /**< INT_EN_PARITYIE Position */ 188 #define MXC_F_UART_INT_EN_PARITYIE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_PARITYIE_POS)) /**< INT_EN_PARITYIE Mask */ 189 190 #define MXC_F_UART_INT_EN_OVERIE_POS 3 /**< INT_EN_OVERIE Position */ 191 #define MXC_F_UART_INT_EN_OVERIE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_OVERIE_POS)) /**< INT_EN_OVERIE Mask */ 192 193 #define MXC_F_UART_INT_EN_FFRXIE_POS 4 /**< INT_EN_FFRXIE Position */ 194 #define MXC_F_UART_INT_EN_FFRXIE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_FFRXIE_POS)) /**< INT_EN_FFRXIE Mask */ 195 196 #define MXC_F_UART_INT_EN_FFTXOIE_POS 5 /**< INT_EN_FFTXOIE Position */ 197 #define MXC_F_UART_INT_EN_FFTXOIE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_FFTXOIE_POS)) /**< INT_EN_FFTXOIE Mask */ 198 199 #define MXC_F_UART_INT_EN_FFTXHIE_POS 6 /**< INT_EN_FFTXHIE Position */ 200 #define MXC_F_UART_INT_EN_FFTXHIE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_FFTXHIE_POS)) /**< INT_EN_FFTXHIE Mask */ 201 202 /**@} end of group UART_INT_EN_Register */ 203 204 /** 205 * @ingroup uart_registers 206 * @defgroup UART_INT_STAT UART_INT_STAT 207 * @brief Interrupt Status Flags. 208 * @{ 209 */ 210 #define MXC_F_UART_INT_STAT_FRAMIS_POS 0 /**< INT_STAT_FRAMIS Position */ 211 #define MXC_F_UART_INT_STAT_FRAMIS ((uint32_t)(0x1UL << MXC_F_UART_INT_STAT_FRAMIS_POS)) /**< INT_STAT_FRAMIS Mask */ 212 213 #define MXC_F_UART_INT_STAT_PARITYIS_POS 1 /**< INT_STAT_PARITYIS Position */ 214 #define MXC_F_UART_INT_STAT_PARITYIS ((uint32_t)(0x1UL << MXC_F_UART_INT_STAT_PARITYIS_POS)) /**< INT_STAT_PARITYIS Mask */ 215 216 #define MXC_F_UART_INT_STAT_OVERIS_POS 3 /**< INT_STAT_OVERIS Position */ 217 #define MXC_F_UART_INT_STAT_OVERIS ((uint32_t)(0x1UL << MXC_F_UART_INT_STAT_OVERIS_POS)) /**< INT_STAT_OVERIS Mask */ 218 219 #define MXC_F_UART_INT_STAT_FFRXIS_POS 4 /**< INT_STAT_FFRXIS Position */ 220 #define MXC_F_UART_INT_STAT_FFRXIS ((uint32_t)(0x1UL << MXC_F_UART_INT_STAT_FFRXIS_POS)) /**< INT_STAT_FFRXIS Mask */ 221 222 #define MXC_F_UART_INT_STAT_FFTXOIS_POS 5 /**< INT_STAT_FFTXOIS Position */ 223 #define MXC_F_UART_INT_STAT_FFTXOIS ((uint32_t)(0x1UL << MXC_F_UART_INT_STAT_FFTXOIS_POS)) /**< INT_STAT_FFTXOIS Mask */ 224 225 #define MXC_F_UART_INT_STAT_FFTXHIS_POS 6 /**< INT_STAT_FFTXHIS Position */ 226 #define MXC_F_UART_INT_STAT_FFTXHIS ((uint32_t)(0x1UL << MXC_F_UART_INT_STAT_FFTXHIS_POS)) /**< INT_STAT_FFTXHIS Mask */ 227 228 /**@} end of group UART_INT_STAT_Register */ 229 230 /** 231 * @ingroup uart_registers 232 * @defgroup UART_BAUD0 UART_BAUD0 233 * @brief Baud rate register. Integer portion. 234 * @{ 235 */ 236 #define MXC_F_UART_BAUD0_IDIV_POS 0 /**< BAUD0_IDIV Position */ 237 #define MXC_F_UART_BAUD0_IDIV ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IDIV_POS)) /**< BAUD0_IDIV Mask */ 238 239 /**@} end of group UART_BAUD0_Register */ 240 241 /** 242 * @ingroup uart_registers 243 * @defgroup UART_BAUD1 UART_BAUD1 244 * @brief Baud rate register. Decimal Setting. 245 * @{ 246 */ 247 #define MXC_F_UART_BAUD1_DDIV_POS 0 /**< BAUD1_DDIV Position */ 248 #define MXC_F_UART_BAUD1_DDIV ((uint32_t)(0x7FUL << MXC_F_UART_BAUD1_DDIV_POS)) /**< BAUD1_DDIV Mask */ 249 250 /**@} end of group UART_BAUD1_Register */ 251 252 /** 253 * @ingroup uart_registers 254 * @defgroup UART_DATA UART_DATA 255 * @brief FIFO Data buffer. 256 * @{ 257 */ 258 #define MXC_F_UART_DATA_DATA_POS 0 /**< DATA_DATA Position */ 259 #define MXC_F_UART_DATA_DATA ((uint32_t)(0xFFUL << MXC_F_UART_DATA_DATA_POS)) /**< DATA_DATA Mask */ 260 261 #define MXC_F_UART_DATA_PARITY_POS 8 /**< DATA_PARITY Position */ 262 #define MXC_F_UART_DATA_PARITY ((uint32_t)(0x1UL << MXC_F_UART_DATA_PARITY_POS)) /**< DATA_PARITY Mask */ 263 264 /**@} end of group UART_DATA_Register */ 265 266 /** 267 * @ingroup uart_registers 268 * @defgroup UART_DMA UART_DMA 269 * @brief DMA Configuration. 270 * @{ 271 */ 272 #define MXC_F_UART_DMA_TXCNT_POS 0 /**< DMA_TXCNT Position */ 273 #define MXC_F_UART_DMA_TXCNT ((uint32_t)(0xFUL << MXC_F_UART_DMA_TXCNT_POS)) /**< DMA_TXCNT Mask */ 274 275 #define MXC_F_UART_DMA_TXEN_POS 4 /**< DMA_TXEN Position */ 276 #define MXC_F_UART_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXEN_POS)) /**< DMA_TXEN Mask */ 277 278 #define MXC_F_UART_DMA_RXCNT_POS 5 /**< DMA_RXCNT Position */ 279 #define MXC_F_UART_DMA_RXCNT ((uint32_t)(0xFUL << MXC_F_UART_DMA_RXCNT_POS)) /**< DMA_RXCNT Mask */ 280 281 #define MXC_F_UART_DMA_RXEN_POS 9 /**< DMA_RXEN Position */ 282 #define MXC_F_UART_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXEN_POS)) /**< DMA_RXEN Mask */ 283 284 /**@} end of group UART_DMA_Register */ 285 286 #ifdef __cplusplus 287 } 288 #endif 289 290 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_UART_REGS_H_ 291
