1 /** 2 * @file rtc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _RTC_REVA_REGS_H_ 27 #define _RTC_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup rtc 65 * @defgroup rtc_registers RTC_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 67 * @details Real Time Clock and Alarm. 68 */ 69 70 /** 71 * @ingroup rtc_registers 72 * Structure type to access the RTC Registers. 73 */ 74 typedef struct { 75 __IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */ 76 __IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */ 77 __IO uint32_t toda; /**< <tt>\b 0x08:</tt> RTC TODA Register */ 78 __IO uint32_t sseca; /**< <tt>\b 0x0C:</tt> RTC SSECA Register */ 79 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */ 80 __IO uint32_t trim; /**< <tt>\b 0x14:</tt> RTC TRIM Register */ 81 __IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */ 82 } mxc_rtc_reva_regs_t; 83 84 /* Register offsets for module RTC */ 85 /** 86 * @ingroup rtc_registers 87 * @defgroup RTC_Register_Offsets Register Offsets 88 * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_RTC_REVA_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_RTC_REVA_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_RTC_REVA_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_RTC_REVA_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_RTC_REVA_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */ 96 #define MXC_R_RTC_REVA_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */ 97 #define MXC_R_RTC_REVA_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */ 98 /**@} end of group rtc_registers */ 99 100 /** 101 * @ingroup rtc_registers 102 * @defgroup RTC_SEC RTC_SEC 103 * @brief RTC Second Counter. This register contains the 32-bit second counter. 104 * @{ 105 */ 106 #define MXC_F_RTC_REVA_SEC_SEC_POS 0 /**< SEC_SEC Position */ 107 #define MXC_F_RTC_REVA_SEC_SEC ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_SEC_SEC_POS)) /**< SEC_SEC Mask */ 108 109 /**@} end of group RTC_SEC_Register */ 110 111 /** 112 * @ingroup rtc_registers 113 * @defgroup RTC_SSEC RTC_SSEC 114 * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented 115 * when this register rolls over from 0xFF to 0x00. 116 * @{ 117 */ 118 #define MXC_F_RTC_REVA_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */ 119 #define MXC_F_RTC_REVA_SSEC_SSEC ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */ 120 121 /**@} end of group RTC_SSEC_Register */ 122 123 /** 124 * @ingroup rtc_registers 125 * @defgroup RTC_TODA RTC_TODA 126 * @brief Time-of-day Alarm. 127 * @{ 128 */ 129 #define MXC_F_RTC_REVA_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */ 130 #define MXC_F_RTC_REVA_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */ 131 132 /**@} end of group RTC_TODA_Register */ 133 134 /** 135 * @ingroup rtc_registers 136 * @defgroup RTC_SSECA RTC_SSECA 137 * @brief RTC sub-second alarm. This register contains the reload value for the sub- 138 * second alarm. 139 * @{ 140 */ 141 #define MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */ 142 #define MXC_F_RTC_REVA_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */ 143 144 /**@} end of group RTC_SSECA_Register */ 145 146 /** 147 * @ingroup rtc_registers 148 * @defgroup RTC_CTRL RTC_CTRL 149 * @brief RTC Control Register. 150 * @{ 151 */ 152 #define MXC_F_RTC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ 153 #define MXC_F_RTC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ 154 155 #define MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE_POS 1 /**< CTRL_TOD_ALARM_IE Position */ 156 #define MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */ 157 158 #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE_POS 2 /**< CTRL_SSEC_ALARM_IE Position */ 159 #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */ 160 161 #define MXC_F_RTC_REVA_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ 162 #define MXC_F_RTC_REVA_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 163 164 #define MXC_F_RTC_REVA_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ 165 #define MXC_F_RTC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 166 167 #define MXC_F_RTC_REVA_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */ 168 #define MXC_F_RTC_REVA_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */ 169 170 #define MXC_F_RTC_REVA_CTRL_TOD_ALARM_POS 6 /**< CTRL_TOD_ALARM Position */ 171 #define MXC_F_RTC_REVA_CTRL_TOD_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */ 172 173 #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_POS 7 /**< CTRL_SSEC_ALARM Position */ 174 #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */ 175 176 #define MXC_F_RTC_REVA_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */ 177 #define MXC_F_RTC_REVA_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */ 178 179 #define MXC_F_RTC_REVA_CTRL_SQW_SEL_POS 9 /**< CTRL_SQW_SEL Position */ 180 #define MXC_F_RTC_REVA_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */ 181 #define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */ 182 #define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */ 183 #define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */ 184 #define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */ 185 #define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */ 186 #define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */ 187 #define MXC_V_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_SQW_SEL_CLKDIV8 Value */ 188 #define MXC_S_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 (MXC_V_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_CLKDIV8 Setting */ 189 190 #define MXC_F_RTC_REVA_CTRL_RD_EN_POS 14 /**< CTRL_RD_EN Position */ 191 #define MXC_F_RTC_REVA_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */ 192 193 #define MXC_F_RTC_REVA_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */ 194 #define MXC_F_RTC_REVA_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */ 195 196 /**@} end of group RTC_CTRL_Register */ 197 198 /** 199 * @ingroup rtc_registers 200 * @defgroup RTC_TRIM RTC_TRIM 201 * @brief RTC Trim Register. 202 * @{ 203 */ 204 #define MXC_F_RTC_REVA_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ 205 #define MXC_F_RTC_REVA_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ 206 207 #define MXC_F_RTC_REVA_TRIM_VRTC_TMR_POS 8 /**< TRIM_VRTC_TMR Position */ 208 #define MXC_F_RTC_REVA_TRIM_VRTC_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_REVA_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */ 209 210 /**@} end of group RTC_TRIM_Register */ 211 212 /** 213 * @ingroup rtc_registers 214 * @defgroup RTC_OSCCTRL RTC_OSCCTRL 215 * @brief RTC Oscillator Control Register. 216 * @{ 217 */ 218 #define MXC_F_RTC_REVA_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ 219 #define MXC_F_RTC_REVA_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_REVA_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ 220 221 #define MXC_F_RTC_REVA_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */ 222 #define MXC_F_RTC_REVA_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_RTC_REVA_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */ 223 224 /**@} end of group RTC_OSCCTRL_Register */ 225 226 #ifdef __cplusplus 227 } 228 #endif 229 230 #endif /* _RTC_REVA_REGS_H_ */ 231
