1 /** 2 * @file owm_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the OWM_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_OWM_OWM_REVA_REGS_H_ 27 #define LIBRARIES_PERIPHDRIVERS_SOURCE_OWM_OWM_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup owm_reva 65 * @defgroup owm_reva_registers OWM_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the OWM_REVA Peripheral Module. 67 * @details 1-Wire Master Interface. 68 */ 69 70 /** 71 * @ingroup owm_reva_registers 72 * Structure type to access the OWM_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t cfg; /**< <tt>\b 0x0000:</tt> OWM_REVA CFG Register */ 76 __IO uint32_t clk_div_1us; /**< <tt>\b 0x0004:</tt> OWM_REVA CLK_DIV_1US Register */ 77 __IO uint32_t ctrl_stat; /**< <tt>\b 0x0008:</tt> OWM_REVA CTRL_STAT Register */ 78 __IO uint32_t data; /**< <tt>\b 0x000C:</tt> OWM_REVA DATA Register */ 79 __IO uint32_t intfl; /**< <tt>\b 0x0010:</tt> OWM_REVA INTFL Register */ 80 __IO uint32_t inten; /**< <tt>\b 0x0014:</tt> OWM_REVA INTEN Register */ 81 } mxc_owm_reva_regs_t; 82 83 /* Register offsets for module OWM_REVA */ 84 /** 85 * @ingroup owm_reva_registers 86 * @defgroup OWM_REVA_Register_Offsets Register Offsets 87 * @brief OWM_REVA Peripheral Register Offsets from the OWM_REVA Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_OWM_REVA_CFG ((uint32_t)0x00000000UL) /**< Offset from OWM_REVA Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_OWM_REVA_CLK_DIV_1US ((uint32_t)0x00000004UL) /**< Offset from OWM_REVA Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_OWM_REVA_CTRL_STAT ((uint32_t)0x00000008UL) /**< Offset from OWM_REVA Base Address: <tt> 0x0008</tt> */ 93 #define MXC_R_OWM_REVA_DATA ((uint32_t)0x0000000CUL) /**< Offset from OWM_REVA Base Address: <tt> 0x000C</tt> */ 94 #define MXC_R_OWM_REVA_INTFL ((uint32_t)0x00000010UL) /**< Offset from OWM_REVA Base Address: <tt> 0x0010</tt> */ 95 #define MXC_R_OWM_REVA_INTEN ((uint32_t)0x00000014UL) /**< Offset from OWM_REVA Base Address: <tt> 0x0014</tt> */ 96 /**@} end of group owm_reva_registers */ 97 98 /** 99 * @ingroup owm_reva_registers 100 * @defgroup OWM_REVA_CFG OWM_REVA_CFG 101 * @brief 1-Wire Master Configuration. 102 * @{ 103 */ 104 #define MXC_F_OWM_REVA_CFG_LONG_LINE_MODE_POS 0 /**< CFG_LONG_LINE_MODE Position */ 105 #define MXC_F_OWM_REVA_CFG_LONG_LINE_MODE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CFG_LONG_LINE_MODE_POS)) /**< CFG_LONG_LINE_MODE Mask */ 106 107 #define MXC_F_OWM_REVA_CFG_FORCE_PRES_DET_POS 1 /**< CFG_FORCE_PRES_DET Position */ 108 #define MXC_F_OWM_REVA_CFG_FORCE_PRES_DET ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CFG_FORCE_PRES_DET_POS)) /**< CFG_FORCE_PRES_DET Mask */ 109 110 #define MXC_F_OWM_REVA_CFG_BIT_BANG_EN_POS 2 /**< CFG_BIT_BANG_EN Position */ 111 #define MXC_F_OWM_REVA_CFG_BIT_BANG_EN ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CFG_BIT_BANG_EN_POS)) /**< CFG_BIT_BANG_EN Mask */ 112 113 #define MXC_F_OWM_REVA_CFG_EXT_PULLUP_MODE_POS 3 /**< CFG_EXT_PULLUP_MODE Position */ 114 #define MXC_F_OWM_REVA_CFG_EXT_PULLUP_MODE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CFG_EXT_PULLUP_MODE_POS)) /**< CFG_EXT_PULLUP_MODE Mask */ 115 116 #define MXC_F_OWM_REVA_CFG_EXT_PULLUP_ENABLE_POS 4 /**< CFG_EXT_PULLUP_ENABLE Position */ 117 #define MXC_F_OWM_REVA_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CFG_EXT_PULLUP_ENABLE_POS)) /**< CFG_EXT_PULLUP_ENABLE Mask */ 118 119 #define MXC_F_OWM_REVA_CFG_SINGLE_BIT_MODE_POS 5 /**< CFG_SINGLE_BIT_MODE Position */ 120 #define MXC_F_OWM_REVA_CFG_SINGLE_BIT_MODE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CFG_SINGLE_BIT_MODE_POS)) /**< CFG_SINGLE_BIT_MODE Mask */ 121 122 #define MXC_F_OWM_REVA_CFG_OVERDRIVE_POS 6 /**< CFG_OVERDRIVE Position */ 123 #define MXC_F_OWM_REVA_CFG_OVERDRIVE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CFG_OVERDRIVE_POS)) /**< CFG_OVERDRIVE Mask */ 124 125 #define MXC_F_OWM_REVA_CFG_INT_PULLUP_ENABLE_POS 7 /**< CFG_INT_PULLUP_ENABLE Position */ 126 #define MXC_F_OWM_REVA_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CFG_INT_PULLUP_ENABLE_POS)) /**< CFG_INT_PULLUP_ENABLE Mask */ 127 128 /**@} end of group OWM_REVA_CFG_Register */ 129 130 /** 131 * @ingroup owm_reva_registers 132 * @defgroup OWM_REVA_CLK_DIV_1US OWM_REVA_CLK_DIV_1US 133 * @brief 1-Wire Master Clock Divisor. 134 * @{ 135 */ 136 #define MXC_F_OWM_REVA_CLK_DIV_1US_DIVISOR_POS 0 /**< CLK_DIV_1US_DIVISOR Position */ 137 #define MXC_F_OWM_REVA_CLK_DIV_1US_DIVISOR ((uint32_t)(0xFFUL << MXC_F_OWM_REVA_CLK_DIV_1US_DIVISOR_POS)) /**< CLK_DIV_1US_DIVISOR Mask */ 138 139 /**@} end of group OWM_REVA_CLK_DIV_1US_Register */ 140 141 /** 142 * @ingroup owm_reva_registers 143 * @defgroup OWM_REVA_CTRL_STAT OWM_REVA_CTRL_STAT 144 * @brief 1-Wire Master Control/Status. 145 * @{ 146 */ 147 #define MXC_F_OWM_REVA_CTRL_STAT_START_OW_RESET_POS 0 /**< CTRL_STAT_START_OW_RESET Position */ 148 #define MXC_F_OWM_REVA_CTRL_STAT_START_OW_RESET ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CTRL_STAT_START_OW_RESET_POS)) /**< CTRL_STAT_START_OW_RESET Mask */ 149 150 #define MXC_F_OWM_REVA_CTRL_STAT_SRA_MODE_POS 1 /**< CTRL_STAT_SRA_MODE Position */ 151 #define MXC_F_OWM_REVA_CTRL_STAT_SRA_MODE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CTRL_STAT_SRA_MODE_POS)) /**< CTRL_STAT_SRA_MODE Mask */ 152 153 #define MXC_F_OWM_REVA_CTRL_STAT_BIT_BANG_OE_POS 2 /**< CTRL_STAT_BIT_BANG_OE Position */ 154 #define MXC_F_OWM_REVA_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CTRL_STAT_BIT_BANG_OE_POS)) /**< CTRL_STAT_BIT_BANG_OE Mask */ 155 156 #define MXC_F_OWM_REVA_CTRL_STAT_OW_INPUT_POS 3 /**< CTRL_STAT_OW_INPUT Position */ 157 #define MXC_F_OWM_REVA_CTRL_STAT_OW_INPUT ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CTRL_STAT_OW_INPUT_POS)) /**< CTRL_STAT_OW_INPUT Mask */ 158 159 #define MXC_F_OWM_REVA_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< CTRL_STAT_OD_SPEC_MODE Position */ 160 #define MXC_F_OWM_REVA_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CTRL_STAT_OD_SPEC_MODE_POS)) /**< CTRL_STAT_OD_SPEC_MODE Mask */ 161 162 #define MXC_F_OWM_REVA_CTRL_STAT_PRESENCE_DETECT_POS 5 /**< CTRL_STAT_PRESENCE_DETECT Position */ 163 #define MXC_F_OWM_REVA_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x1UL << MXC_F_OWM_REVA_CTRL_STAT_PRESENCE_DETECT_POS)) /**< CTRL_STAT_PRESENCE_DETECT Mask */ 164 165 /**@} end of group OWM_REVA_CTRL_STAT_Register */ 166 167 /** 168 * @ingroup owm_reva_registers 169 * @defgroup OWM_REVA_DATA OWM_REVA_DATA 170 * @brief 1-Wire Master Data Buffer. 171 * @{ 172 */ 173 #define MXC_F_OWM_REVA_DATA_TX_RX_POS 0 /**< DATA_TX_RX Position */ 174 #define MXC_F_OWM_REVA_DATA_TX_RX ((uint32_t)(0xFFUL << MXC_F_OWM_REVA_DATA_TX_RX_POS)) /**< DATA_TX_RX Mask */ 175 176 /**@} end of group OWM_REVA_DATA_Register */ 177 178 /** 179 * @ingroup owm_reva_registers 180 * @defgroup OWM_REVA_INTFL OWM_REVA_INTFL 181 * @brief 1-Wire Master Interrupt Flags. 182 * @{ 183 */ 184 #define MXC_F_OWM_REVA_INTFL_OW_RESET_DONE_POS 0 /**< INTFL_OW_RESET_DONE Position */ 185 #define MXC_F_OWM_REVA_INTFL_OW_RESET_DONE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTFL_OW_RESET_DONE_POS)) /**< INTFL_OW_RESET_DONE Mask */ 186 187 #define MXC_F_OWM_REVA_INTFL_TX_DATA_EMPTY_POS 1 /**< INTFL_TX_DATA_EMPTY Position */ 188 #define MXC_F_OWM_REVA_INTFL_TX_DATA_EMPTY ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTFL_TX_DATA_EMPTY_POS)) /**< INTFL_TX_DATA_EMPTY Mask */ 189 190 #define MXC_F_OWM_REVA_INTFL_RX_DATA_READY_POS 2 /**< INTFL_RX_DATA_READY Position */ 191 #define MXC_F_OWM_REVA_INTFL_RX_DATA_READY ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTFL_RX_DATA_READY_POS)) /**< INTFL_RX_DATA_READY Mask */ 192 193 #define MXC_F_OWM_REVA_INTFL_LINE_SHORT_POS 3 /**< INTFL_LINE_SHORT Position */ 194 #define MXC_F_OWM_REVA_INTFL_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTFL_LINE_SHORT_POS)) /**< INTFL_LINE_SHORT Mask */ 195 196 #define MXC_F_OWM_REVA_INTFL_LINE_LOW_POS 4 /**< INTFL_LINE_LOW Position */ 197 #define MXC_F_OWM_REVA_INTFL_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTFL_LINE_LOW_POS)) /**< INTFL_LINE_LOW Mask */ 198 199 /**@} end of group OWM_REVA_INTFL_Register */ 200 201 /** 202 * @ingroup owm_reva_registers 203 * @defgroup OWM_REVA_INTEN OWM_REVA_INTEN 204 * @brief 1-Wire Master Interrupt Enables. 205 * @{ 206 */ 207 #define MXC_F_OWM_REVA_INTEN_OW_RESET_DONE_POS 0 /**< INTEN_OW_RESET_DONE Position */ 208 #define MXC_F_OWM_REVA_INTEN_OW_RESET_DONE ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTEN_OW_RESET_DONE_POS)) /**< INTEN_OW_RESET_DONE Mask */ 209 210 #define MXC_F_OWM_REVA_INTEN_TX_DATA_EMPTY_POS 1 /**< INTEN_TX_DATA_EMPTY Position */ 211 #define MXC_F_OWM_REVA_INTEN_TX_DATA_EMPTY ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTEN_TX_DATA_EMPTY_POS)) /**< INTEN_TX_DATA_EMPTY Mask */ 212 213 #define MXC_F_OWM_REVA_INTEN_RX_DATA_READY_POS 2 /**< INTEN_RX_DATA_READY Position */ 214 #define MXC_F_OWM_REVA_INTEN_RX_DATA_READY ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTEN_RX_DATA_READY_POS)) /**< INTEN_RX_DATA_READY Mask */ 215 216 #define MXC_F_OWM_REVA_INTEN_LINE_SHORT_POS 3 /**< INTEN_LINE_SHORT Position */ 217 #define MXC_F_OWM_REVA_INTEN_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTEN_LINE_SHORT_POS)) /**< INTEN_LINE_SHORT Mask */ 218 219 #define MXC_F_OWM_REVA_INTEN_LINE_LOW_POS 4 /**< INTEN_LINE_LOW Position */ 220 #define MXC_F_OWM_REVA_INTEN_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_REVA_INTEN_LINE_LOW_POS)) /**< INTEN_LINE_LOW Mask */ 221 222 /**@} end of group OWM_REVA_INTEN_Register */ 223 224 #ifdef __cplusplus 225 } 226 #endif 227 228 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_OWM_OWM_REVA_REGS_H_ 229 230
