Searched refs:__SCB_DCACHE_LINE_SIZE (Results 1 – 2 of 2) sorted by relevance
43 #ifndef __SCB_DCACHE_LINE_SIZE44 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro188 __ALIGNED(__SCB_DCACHE_LINE_SIZE) in SCB_DisableDCache()360 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()367 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()368 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()390 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()397 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()398 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()420 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()[all …]
3152 #define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). S… macro3434 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_InvalidateDCache_by_Addr()3441 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()3442 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()3464 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanDCache_by_Addr()3471 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()3472 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()3494 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); in SCB_CleanInvalidateDCache_by_Addr()3501 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()3502 op_size -= __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
