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Searched refs:__RAM_SIZE (Results 1 – 24 of 24) sorted by relevance

/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/
DARMCA5_ac6.sct25 +__RAM_SIZE
34 +__RAM_SIZE
42 +__RAM_SIZE
49 +__RAM_SIZE
55 +__RAM_SIZE
60 +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
Dmem_ARMCA5.h72 #define __RAM_SIZE 0x00200000 macro
Dmmu_ARMCA5.c172 …MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sec… in MMU_CreateTranslationTable()
DARMCA5_gcc.ld6 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA5_clang.ld49 RAM0 (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/
DARMCA9_ac6.sct25 +__RAM_SIZE
34 +__RAM_SIZE
42 +__RAM_SIZE
49 +__RAM_SIZE
55 +__RAM_SIZE
60 +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
DARMCA9.sct37 +__RAM_SIZE
46 +__RAM_SIZE
54 +__RAM_SIZE
61 +__RAM_SIZE
67 +__RAM_SIZE
72 +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
Dmem_ARMCA9.h72 #define __RAM_SIZE 0x00200000 macro
Dmmu_ARMCA9.c172 …MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sec… in MMU_CreateTranslationTable()
DARMCA9_gcc.ld6 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA9.ld7 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA9_clang.ld49 RAM0 (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/
DARMCA7_ac6.sct25 +__RAM_SIZE
34 +__RAM_SIZE
42 +__RAM_SIZE
49 +__RAM_SIZE
55 +__RAM_SIZE
60 +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
DARMCA7.sct37 +__RAM_SIZE
46 +__RAM_SIZE
54 +__RAM_SIZE
61 +__RAM_SIZE
67 +__RAM_SIZE
72 +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
Dmem_ARMCA7.h72 #define __RAM_SIZE 0x00200000 macro
Dmmu_ARMCA7.c172 …MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sec… in MMU_CreateTranslationTable()
DARMCA7.ld7 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA7_gcc.ld6 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA7_clang.ld49 RAM0 (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/Core/Template/Device_A/Config/
DDevice_ac6.sct35 +__RAM_SIZE
44 +__RAM_SIZE
52 +__RAM_SIZE
59 +__RAM_SIZE
65 +__RAM_SIZE
70 +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
Dmem_Device.h65 #define __RAM_SIZE 0x00200000 macro
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/
DARMCM3_gcc.ld45 __RAM_SIZE = 0x00020000; symbol
63 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/Core/Template/Device_M/Config/
DDevice_gcc.ld45 __RAM_SIZE = 0x00020000; symbol
69 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/Documentation/Doxygen/Core/src/
Dcore_linker_sct.md33 #define __RAM_SIZE 0x00040000