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Searched refs:__RAM_BASE (Results 1 – 24 of 24) sorted by relevance

/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/
DARMCA5_ac6.sct12 RW_DATA __RAM_BASE __RW_DATA_SIZE
15 ZI_DATA (__RAM_BASE+
19 ARM_LIB_HEAP (__RAM_BASE
24 ARM_LIB_STACK (__RAM_BASE
33 UND_STACK (__RAM_BASE
41 ABT_STACK (__RAM_BASE
48 SVC_STACK (__RAM_BASE
54 IRQ_STACK (__RAM_BASE
59 FIQ_STACK (__RAM_BASE
Dmem_ARMCA5.h71 #define __RAM_BASE 0x80200000 macro
Dmmu_ARMCA5.c172 …MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sec… in MMU_CreateTranslationTable()
DARMCA5_gcc.ld6 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA5_clang.ld49 RAM0 (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/
DARMCA9_ac6.sct12 RW_DATA __RAM_BASE __RW_DATA_SIZE
15 ZI_DATA (__RAM_BASE+
19 ARM_LIB_HEAP (__RAM_BASE
24 ARM_LIB_STACK (__RAM_BASE
33 UND_STACK (__RAM_BASE
41 ABT_STACK (__RAM_BASE
48 SVC_STACK (__RAM_BASE
54 IRQ_STACK (__RAM_BASE
59 FIQ_STACK (__RAM_BASE
DARMCA9.sct24 RW_DATA __RAM_BASE __RW_DATA_SIZE
27 ZI_DATA (__RAM_BASE+
31 ARM_LIB_HEAP (__RAM_BASE
36 ARM_LIB_STACK (__RAM_BASE
45 UND_STACK (__RAM_BASE
53 ABT_STACK (__RAM_BASE
60 SVC_STACK (__RAM_BASE
66 IRQ_STACK (__RAM_BASE
71 FIQ_STACK (__RAM_BASE
Dmem_ARMCA9.h71 #define __RAM_BASE 0x80200000 macro
Dmmu_ARMCA9.c172 …MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sec… in MMU_CreateTranslationTable()
DARMCA9_gcc.ld6 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA9.ld7 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA9_clang.ld49 RAM0 (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/
DARMCA7_ac6.sct12 RW_DATA __RAM_BASE __RW_DATA_SIZE
15 ZI_DATA (__RAM_BASE+
19 ARM_LIB_HEAP (__RAM_BASE
24 ARM_LIB_STACK (__RAM_BASE
33 UND_STACK (__RAM_BASE
41 ABT_STACK (__RAM_BASE
48 SVC_STACK (__RAM_BASE
54 IRQ_STACK (__RAM_BASE
59 FIQ_STACK (__RAM_BASE
DARMCA7.sct24 RW_DATA __RAM_BASE __RW_DATA_SIZE
27 ZI_DATA (__RAM_BASE+
31 ARM_LIB_HEAP (__RAM_BASE
36 ARM_LIB_STACK (__RAM_BASE
45 UND_STACK (__RAM_BASE
53 ABT_STACK (__RAM_BASE
60 SVC_STACK (__RAM_BASE
66 IRQ_STACK (__RAM_BASE
71 FIQ_STACK (__RAM_BASE
Dmem_ARMCA7.h71 #define __RAM_BASE 0x80200000 macro
Dmmu_ARMCA7.c172 …MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sec… in MMU_CreateTranslationTable()
DARMCA7.ld7 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA7_gcc.ld6 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCA7_clang.ld49 RAM0 (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/Core/Template/Device_A/Config/
DDevice_ac6.sct22 RW_DATA __RAM_BASE __RW_DATA_SIZE
25 ZI_DATA (__RAM_BASE+
29 ARM_LIB_HEAP (__RAM_BASE
34 ARM_LIB_STACK (__RAM_BASE
43 UND_STACK (__RAM_BASE
51 ABT_STACK (__RAM_BASE
58 SVC_STACK (__RAM_BASE
64 IRQ_STACK (__RAM_BASE
69 FIQ_STACK (__RAM_BASE
Dmem_Device.h64 #define __RAM_BASE 0x80200000 macro
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/
DARMCM3_gcc.ld44 __RAM_BASE = 0x20000000; symbol
63 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/Core/Template/Device_M/Config/
DDevice_gcc.ld44 __RAM_BASE = 0x20000000; symbol
69 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis_6-latest/CMSIS/Documentation/Doxygen/Core/src/
Dcore_linker_sct.md32 #define __RAM_BASE 0x20000000