| /cmsis-latest/CMSIS/Core_A/Include/ |
| D | cmsis_cp15.h | 49 __set_CP(15, 0, actlr, 1, 0, 1); in __set_ACTLR()
67 __set_CP(15, 0, cpacr, 1, 0, 2); in __set_CPACR()
85 __set_CP(15, 0, dfsr, 5, 0, 0); in __set_DFSR()
103 __set_CP(15, 0, ifsr, 5, 0, 1); in __set_IFSR()
147 __set_CP(15, 0, ttbr0, 2, 0, 0); in __set_TTBR0()
171 __set_CP(15, 0, dacr, 3, 0, 0); in __set_DACR()
182 __set_CP(15, 0, sctlr, 1, 0, 0); in __set_SCTLR()
200 __set_CP(15, 0, actrl, 1, 0, 1); in __set_ACTRL()
247 __set_CP(15, 0, vbar, 12, 0, 0); in __set_VBAR()
271 __set_CP(15, 0, mvbar, 12, 0, 1); in __set_MVBAR()
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| D | cmsis_iccarm.h | 267 #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ macro
456 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ macro
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| D | cmsis_armclang.h | 538 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn… macro
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| D | cmsis_armcc.h | 474 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":… macro
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| D | cmsis_gcc.h | 839 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn… macro
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| /cmsis-latest/CMSIS/Core_R/Include/ |
| D | cmsis_cp15.h | 50 __set_CP(15, 0, actlr, 1, 0, 1); in __set_ACTLR()
68 __set_CP(15, 0, cpacr, 1, 0, 2); in __set_CPACR()
86 __set_CP(15, 0, dfsr, 5, 0, 0); in __set_DFSR()
104 __set_CP(15, 0, ifsr, 5, 0, 1); in __set_IFSR()
140 __set_CP(15, 0, sctlr, 1, 0, 0); in __set_SCTLR()
158 __set_CP(15, 0, actrl, 1, 0, 1); in __set_ACTRL()
205 __set_CP(15, 0, vbar, 12, 0, 0); in __set_VBAR()
220 __set_CP(15, 0, value, 14, 0, 0); in __set_CNTFRQ()
244 __set_CP(15, 0, value, 14, 2, 0); in __set_CNTP_TVAL()
305 __set_CP(15, 0, value, 14, 2, 1); in __set_CNTP_CTL()
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| D | cmsis_gcc.h | 833 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn… macro
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