Searched refs:__SCB_ICACHE_LINE_SIZE (Results 1 – 2 of 2) sorted by relevance
49 #ifndef __SCB_ICACHE_LINE_SIZE50 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). … macro119 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()127 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
3072 #define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). S… macro3140 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()3147 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()3148 op_size -= __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
