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Searched refs:SCB_CPUID_REVISION_Pos (Results 1 – 17 of 17) sorted by relevance

/cmsis-latest/CMSIS/Core/Include/
Dcore_cm0.h367 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm1.h367 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_sc000.h380 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm0plus.h385 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm3.h417 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_sc300.h419 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm4.h483 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm23.h413 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_armv8mbl.h413 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm7.h528 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm35p.h567 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm33.h567 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_armv8mml.h567 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_starmc1.h580 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_armv81mml.h575 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm85.h594 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm55.h577 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro