Searched refs:CSSELR (Results 1 – 9 of 9) sorted by relevance
150 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()188 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()226 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()261 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()296 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
535 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member3171 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()3209 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()3247 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()3282 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()3317 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
485 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
528 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
535 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
554 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
537 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
