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/cmsis-dsp-latest/Scripts/
DgenMVETwiddleCoefs.py150 def reorderTwiddle(theType,conjugate,f,h,n): argument
236 print(condition % ("F32",n, "F32",n << 1),file=h)
238 printHUInt32Array(h,"rearranged_twiddle_tab_stride1_arr_%d_f32" % n,list(tab1Offset))
241 printHUInt32Array(h,"rearranged_twiddle_tab_stride2_arr_%d_f32" % n,list(tab2Offset))
244 printHUInt32Array(h,"rearranged_twiddle_tab_stride3_arr_%d_f32" % n,list(tab3Offset))
247 printHFloat32Array(h,"rearranged_twiddle_stride1_%d_f32" % n,list(tab1))
250 printHFloat32Array(h,"rearranged_twiddle_stride2_%d_f32" % n,list(tab2))
253 printHFloat32Array(h,"rearranged_twiddle_stride3_%d_f32" % n,list(tab3))
255 print("#endif\n",file=h)
260 print(condition % ("F16",n, "F16",n << 1),file=h)
[all …]
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM23/
DARMCM23_ac6.sct13 ; <h> Flash Configuration
16 ; </h>
22 ; <h> RAM Configuration
25 ; </h>
31 ; <h> Stack / Heap Configuration
34 ; </h>
40 ; <h> CMSE Veneer Configuration
42 ; </h>
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM33/
DARMCM33_ac6.sct13 ; <h> Flash Configuration
16 ; </h>
22 ; <h> RAM Configuration
25 ; </h>
31 ; <h> Stack / Heap Configuration
34 ; </h>
40 ; <h> CMSE Veneer Configuration
42 ; </h>
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM33_DSP_FP/
DARMCM33_ac6.sct13 ; <h> Flash Configuration
16 ; </h>
22 ; <h> RAM Configuration
25 ; </h>
31 ; <h> Stack / Heap Configuration
34 ; </h>
40 ; <h> CMSE Veneer Configuration
42 ; </h>
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM35P_DSP_FP/
DARMCM35P_ac6.sct13 ; <h> Flash Configuration
16 ; </h>
22 ; <h> RAM Configuration
25 ; </h>
31 ; <h> Stack / Heap Configuration
34 ; </h>
40 ; <h> CMSE Veneer Configuration
42 ; </h>
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM55/
DARMCM55_ac6.sct13 ; <h> Flash Configuration
16 ; </h>
22 ; <h> RAM Configuration
25 ; </h>
31 ; <h> Stack / Heap Configuration
34 ; </h>
40 ; <h> CMSE Veneer Configuration
42 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/
DARMCM7_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/
DARMCM0_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/
DARMCM3_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/
DARMCM3_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/
DARMCM7_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/
DARMCM4_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/
DARMCM0_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/
DARMCM3_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/
DARMCM4_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/
DARMCM4_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/
DARMCM7_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/
DARMCM4_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/
DARMCM0_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/
DARMCM3_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/
DARMCM7_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/
DARMCM4_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/
DARMCM7_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/cmsis_build/RTE/Device/ARMCM7_DP/
DARMCM7_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>
/cmsis-dsp-latest/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/
DARMCM4_ac6.sct9 ; <h> Flash Configuration
12 ; </h>
18 ; <h> RAM Configuration
21 ; </h>
27 ; <h> Stack / Heap Configuration
30 ; </h>

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