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Searched refs:__TTB_BASE (Results 1 – 9 of 9) sorted by relevance

/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA5/
Dmmu_ARMCA5.c106 #define TTB_BASE ((uint32_t*)__TTB_BASE)
114 #define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Addres…
115 #define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1…
116 #define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2…
117 #define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchroni…
224 __set_TTBR0(__TTB_BASE | 0x48); in MMU_CreateTranslationTable()
Dmem_ARMCA5.h97 #define __TTB_BASE 0x80500000 macro
DARMCA5.sct75 TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA7/
Dmmu_ARMCA7.c106 #define TTB_BASE ((uint32_t*)__TTB_BASE)
114 #define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Addres…
115 #define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1…
116 #define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2…
117 #define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchroni…
224 __set_TTBR0(__TTB_BASE | 0x48); in MMU_CreateTranslationTable()
Dmem_ARMCA7.h97 #define __TTB_BASE 0x80500000 macro
DARMCA7.sct75 TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA9/
Dmmu_ARMCA9.c106 #define TTB_BASE ((uint32_t*)__TTB_BASE)
114 #define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Addres…
115 #define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1…
116 #define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2…
117 #define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchroni…
224 __set_TTBR0(__TTB_BASE | 0x48); in MMU_CreateTranslationTable()
Dmem_ARMCA9.h97 #define __TTB_BASE 0x80500000 macro
DARMCA9.sct75 TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU