Home
last modified time | relevance | path

Searched refs:DDR4_BLK3_BASE_S (Results 1 – 4 of 4) sorted by relevance

/cmsis-dsp-latest/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/
Dplatform_base_address.h178 #define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ macro
241 #define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S)
242 #define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
243 #define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
/cmsis-dsp-latest/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/
Dplatform_base_address.h192 #define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ macro
255 #define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S)
256 #define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
257 #define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/
Dplatform_base_address.h182 #define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ macro
245 #define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S)
246 #define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
247 #define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/SSE-310-MPS3/
Dplatform_base_address.h178 #define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ macro
241 #define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S)
242 #define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
243 #define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)