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Searched refs:CPU0_PWRCTRL_BASE_NS (Results 1 – 4 of 4) sorted by relevance

/cmsis-dsp-latest/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/
Dplatform_base_address.h39 #define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base ad… macro
/cmsis-dsp-latest/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/
Dplatform_base_address.h38 #define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base ad… macro
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/
Dplatform_base_address.h38 #define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base ad… macro
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/SSE-310-MPS3/
Dplatform_base_address.h39 #define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base ad… macro