1 /******************************************************************************
2 * @file arm_math_memory.h
3 * @brief Public header file for CMSIS DSP Library
4 * @version V1.10.0
5 * @date 08 July 2021
6 * Target Processor: Cortex-M and Cortex-A cores
7 ******************************************************************************/
8 /*
9 * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
10 *
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26 #ifndef _ARM_MATH_MEMORY_H_
27
28 #define _ARM_MATH_MEMORY_H_
29
30 #include "arm_math_types.h"
31
32
33 #ifdef __cplusplus
34 extern "C"
35 {
36 #endif
37
38 /**
39 @brief definition to read/write two 16 bit values.
40 @deprecated
41 */
42 #if defined ( __CC_ARM )
43 #define __SIMD32_TYPE int32_t __packed
44 #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
45 #define __SIMD32_TYPE int32_t
46 #elif defined ( __GNUC__ )
47 #define __SIMD32_TYPE int32_t
48 #elif defined ( __ICCARM__ )
49 #define __SIMD32_TYPE int32_t __packed
50 #elif defined ( __TI_ARM__ )
51 #define __SIMD32_TYPE int32_t
52 #elif defined ( __CSMC__ )
53 #define __SIMD32_TYPE int32_t
54 #elif defined ( __TASKING__ )
55 #define __SIMD32_TYPE __un(aligned) int32_t
56 #elif defined(_MSC_VER )
57 #define __SIMD32_TYPE int32_t
58 #else
59 #error Unknown compiler
60 #endif
61
62 #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
63 #define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
64 #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
65 #define __SIMD64(addr) (*( int64_t **) & (addr))
66
67
68 /* SIMD replacement */
69
70
71 /**
72 @brief Read 2 Q15 from Q15 pointer.
73 @param[in] pQ15 points to input value
74 @return Q31 value
75 */
read_q15x2(q15_t const * pQ15)76 __STATIC_FORCEINLINE q31_t read_q15x2 (
77 q15_t const * pQ15)
78 {
79 q31_t val;
80
81 #ifdef __ARM_FEATURE_UNALIGNED
82 memcpy (&val, pQ15, 4);
83 #else
84 val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
85 #endif
86
87 return (val);
88 }
89
90 /**
91 @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
92 @param[in] pQ15 points to input value
93 @return Q31 value
94 */
95 #define read_q15x2_ia(pQ15) read_q15x2((*(pQ15) += 2) - 2)
96
97 /**
98 @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
99 @param[in] pQ15 points to input value
100 @return Q31 value
101 */
102 #define read_q15x2_da(pQ15) read_q15x2((*(pQ15) -= 2) + 2)
103
104 /**
105 @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
106 @param[in] pQ15 points to input value
107 @param[in] value Q31 value
108 */
write_q15x2_ia(q15_t ** pQ15,q31_t value)109 __STATIC_FORCEINLINE void write_q15x2_ia (
110 q15_t ** pQ15,
111 q31_t value)
112 {
113 q31_t val = value;
114 #ifdef __ARM_FEATURE_UNALIGNED
115 memcpy (*pQ15, &val, 4);
116 #else
117 (*pQ15)[0] = (q15_t)(val & 0x0FFFF);
118 (*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF);
119 #endif
120
121 *pQ15 += 2;
122 }
123
124 /**
125 @brief Write 2 Q15 to Q15 pointer.
126 @param[in] pQ15 points to input value
127 @param[in] value Q31 value
128 */
write_q15x2(q15_t * pQ15,q31_t value)129 __STATIC_FORCEINLINE void write_q15x2 (
130 q15_t * pQ15,
131 q31_t value)
132 {
133 q31_t val = value;
134
135 #ifdef __ARM_FEATURE_UNALIGNED
136 memcpy (pQ15, &val, 4);
137 #else
138 pQ15[0] = (q15_t)(val & 0x0FFFF);
139 pQ15[1] = (q15_t)(val >> 16);
140 #endif
141 }
142
143
144 /**
145 @brief Read 4 Q7 from Q7 pointer
146 @param[in] pQ7 points to input value
147 @return Q31 value
148 */
read_q7x4(q7_t const * pQ7)149 __STATIC_FORCEINLINE q31_t read_q7x4 (
150 q7_t const * pQ7)
151 {
152 q31_t val;
153
154 #ifdef __ARM_FEATURE_UNALIGNED
155 memcpy (&val, pQ7, 4);
156 #else
157 val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF);
158 #endif
159 return (val);
160 }
161
162 /**
163 @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
164 @param[in] pQ7 points to input value
165 @return Q31 value
166 */
167 #define read_q7x4_ia(pQ7) read_q7x4((*(pQ7) += 4) - 4)
168
169 /**
170 @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
171 @param[in] pQ7 points to input value
172 @return Q31 value
173 */
174 #define read_q7x4_da(pQ7) read_q7x4((*(pQ7) -= 4) + 4)
175
176 /**
177 @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
178 @param[in] pQ7 points to input value
179 @param[in] value Q31 value
180 */
write_q7x4_ia(q7_t ** pQ7,q31_t value)181 __STATIC_FORCEINLINE void write_q7x4_ia (
182 q7_t ** pQ7,
183 q31_t value)
184 {
185 q31_t val = value;
186 #ifdef __ARM_FEATURE_UNALIGNED
187 memcpy (*pQ7, &val, 4);
188 #else
189 (*pQ7)[0] = (q7_t)(val & 0x0FF);
190 (*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF);
191 (*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF);
192 (*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF);
193
194 #endif
195 *pQ7 += 4;
196 }
197
198
199 #ifdef __cplusplus
200 }
201 #endif
202
203 #endif /*ifndef _ARM_MATH_MEMORY_H_ */
204
