| /Zephyr-latest/scripts/west_commands/runners/ |
| D | mdb.py | 46 return mdb_runner.cores - 1 - id
84 if mdb_runner.cores == 1:
87 elif 1 < mdb_runner.cores <= 12:
89 for i in range(mdb_runner.cores):
114 def __init__(self, cfg, cores=1, nsim_args=''): argument
117 self.cores = int(cores)
149 cores=args.cores,
159 def __init__(self, cfg, cores=1, jtag='digilent', dig_device=''): argument
162 self.cores = int(cores)
197 cores=args.cores,
|
| D | nrfjprog.py | 72 cores = {'Application': 'CP_APPLICATION',
75 core_opt = ['--coprocessor', cores[op['core']]] \
|
| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | Kconfig.soc | 20 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
27 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
35 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
42 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
50 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
58 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
66 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
|
| /Zephyr-latest/boards/snps/hsdk/ |
| D | board.cmake | 5 board_runner_args(openocd "--config=${CMAKE_CURRENT_LIST_DIR}/support/openocd-2-cores.cfg")
8 board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}")
|
| /Zephyr-latest/doc/kernel/data_structures/ |
| D | mpsc_lockfree.rst | 8 at `1024cores <https://www.1024cores.net/home/lock-free-algorithms/queues/intrusive-mpsc-node-based…
|
| /Zephyr-latest/boards/pimoroni/pico_plus2/ |
| D | pico_plus2_rp2350b_m33.dts | 19 /* there's nothing specific to the Cortex-M33 cores vs the (not yet
20 * implemented) Hazard3 cores.
|
| D | pico_plus2_rp2350b_m33_defconfig | 1 # This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores
|
| /Zephyr-latest/boards/raspberrypi/rpi_pico2/ |
| D | rpi_pico2_rp2350a_m33.dts | 19 /* there's nothing specific to the Cortex-M33 cores vs the (not yet
20 * implemented) Hazard3 cores.
|
| D | rpi_pico2_rp2350a_m33_defconfig | 1 # This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores
|
| /Zephyr-latest/boards/snps/nsim/arc_classic/ |
| D | board.cmake | 17 board_runner_args(mdb-nsim "--cores=${CONFIG_MP_MAX_NUM_CPUS}" "--nsim_args=${MDB_ARGS}")
18 board_runner_args(mdb-hw "--cores=${CONFIG_MP_MAX_NUM_CPUS}")
|
| /Zephyr-latest/samples/arch/smp/pi/ |
| D | README.rst | 9 demonstrates the benefit of multiple execution units (CPU cores)
14 can see that using more cores takes almost linearly less time
46 All 16 threads executed by 4 cores in 28 msec
|
| /Zephyr-latest/doc/services/llext/ |
| D | index.rst | 25 available only on RISC-V, ARM, ARM64, ARC (experimental) and Xtensa cores.
26 Harvard architecture cores that separate code and data paths and have no
|
| /Zephyr-latest/boards/renesas/rcar_spider_s4/doc/ |
| D | rcar_spider_a55.rst | 12 The software package supports the real-time cores with various drivers and basic software
19 * eight 1.2GHz Arm Cortex-A55 cores, 2 cores x 4 clusters;
21 * two 400MHz G4MH cores (hardware Lock step is supported);
|
| /Zephyr-latest/doc/kernel/object_cores/ |
| D | index.rst | 6 Object cores are a kernel debugging tool that can be used to both identify and
18 cores to form a singly linked list. Each object core also links to the their
20 linking together all the object cores of that type. Object types are also
24 Object cores have been integrated into following kernel objects:
44 Object cores provide a uniform means to retrieve that information via object
76 initialized for use with object cores and object core statistics.
120 automatically have their object cores initialized when the object is
139 Two routines exist for walking the list of object cores linked to an object
|
| /Zephyr-latest/arch/arm64/ |
| D | Kconfig | 23 A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
25 option must be selected when such cores are connected to an interrupt
|
| /Zephyr-latest/boards/snps/hsdk4xd/ |
| D | board.cmake | 4 board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}")
|
| /Zephyr-latest/boards/intel/rpl/doc/ |
| D | index.rst | 10 architecture, utilizing P-cores for performance and E-Cores for efficiency.
21 For more information about Raptor Lake Processor lines, P-cores, and E-cores
|
| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.vim | 14 and aggregating the interrupt sources for ARM Cortex-R5 processor cores.
|
| /Zephyr-latest/boards/nxp/s32z2xxdc2/ |
| D | s32z2xxdc2_s32z270_rtu1.dts | 12 model = "NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores";
|
| D | s32z2xxdc2_s32z270_rtu0.dts | 12 model = "NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores";
|
| /Zephyr-latest/samples/subsys/ipc/openamp/ |
| D | sysbuild.cmake | 13 # This is required because some primary cores need information from the
|
| /Zephyr-latest/samples/drivers/ipm/ipm_mcux/ |
| D | sysbuild.cmake | 13 # This is required because some primary cores need information from the
|
| /Zephyr-latest/samples/arch/smp/pktqueue/ |
| D | README.rst | 51 can see that using more cores takes almost linearly less time
78 Simulating IP header validation on multiple cores.
79 Each of 2 parallel queues is processed by 3 threads on 2 cores and contain 5000 packet headers.
|
| /Zephyr-latest/boards/renesas/rcar_salvator_xs/doc/ |
| D | index.rst | 15 * two 1.5-GHz ARM Cortex-A57 MPCore cores;
16 * four 1.3-GHz ARM Cortex-A53 MPCore cores,
|
| /Zephyr-latest/soc/intel/intel_adsp/cavs/ |
| D | Kconfig.defconfig.cavs_v25 | 10 # Hardware has four cores, limited to two pending test fixes
|
