1 /**************************************************************************//** 2 * @file irq_ctrl.h 3 * @brief Interrupt Controller API header file 4 * @version V1.1.0 5 * @date 03. March 2020 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2017-2020 ARM Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef IRQ_CTRL_H_ 32 #define IRQ_CTRL_H_ 33 34 #include <stdint.h> 35 36 #ifndef IRQHANDLER_T 37 #define IRQHANDLER_T 38 /// Interrupt handler data type 39 typedef void (*IRQHandler_t) (void); 40 #endif 41 42 #ifndef IRQN_ID_T 43 #define IRQN_ID_T 44 /// Interrupt ID number data type 45 typedef int32_t IRQn_ID_t; 46 #endif 47 48 /* Interrupt mode bit-masks */ 49 #define IRQ_MODE_TRIG_Pos (0U) 50 #define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) 51 #define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt 52 #define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt 53 #define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt 54 #define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt 55 #define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt 56 #define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt 57 #define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt 58 59 #define IRQ_MODE_TYPE_Pos (3U) 60 #define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) 61 #define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line 62 #define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line 63 64 #define IRQ_MODE_DOMAIN_Pos (4U) 65 #define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) 66 #define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain 67 #define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain 68 69 #define IRQ_MODE_CPU_Pos (5U) 70 #define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) 71 #define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs 72 #define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 73 #define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 74 #define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 75 #define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 76 #define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 77 #define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 78 #define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 79 #define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 80 81 // Encoding in some early GIC implementations 82 #define IRQ_MODE_MODEL_Pos (13U) 83 #define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos) 84 #define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the N-N model 85 #define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the 1-N model 86 87 #define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error 88 89 /* Interrupt priority bit-masks */ 90 #define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask 91 #define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error 92 93 /// Initialize interrupt controller. 94 /// \return 0 on success, -1 on error. 95 int32_t IRQ_Initialize (void); 96 97 /// Register interrupt handler. 98 /// \param[in] irqn interrupt ID number 99 /// \param[in] handler interrupt handler function address 100 /// \return 0 on success, -1 on error. 101 int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); 102 103 /// Get the registered interrupt handler. 104 /// \param[in] irqn interrupt ID number 105 /// \return registered interrupt handler function address. 106 IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); 107 108 /// Enable interrupt. 109 /// \param[in] irqn interrupt ID number 110 /// \return 0 on success, -1 on error. 111 int32_t IRQ_Enable (IRQn_ID_t irqn); 112 113 /// Disable interrupt. 114 /// \param[in] irqn interrupt ID number 115 /// \return 0 on success, -1 on error. 116 int32_t IRQ_Disable (IRQn_ID_t irqn); 117 118 /// Get interrupt enable state. 119 /// \param[in] irqn interrupt ID number 120 /// \return 0 - interrupt is disabled, 1 - interrupt is enabled. 121 uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); 122 123 /// Configure interrupt request mode. 124 /// \param[in] irqn interrupt ID number 125 /// \param[in] mode mode configuration 126 /// \return 0 on success, -1 on error. 127 int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); 128 129 /// Get interrupt mode configuration. 130 /// \param[in] irqn interrupt ID number 131 /// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. 132 uint32_t IRQ_GetMode (IRQn_ID_t irqn); 133 134 /// Get ID number of current interrupt request (IRQ). 135 /// \return interrupt ID number. 136 IRQn_ID_t IRQ_GetActiveIRQ (void); 137 138 /// Get ID number of current fast interrupt request (FIQ). 139 /// \return interrupt ID number. 140 IRQn_ID_t IRQ_GetActiveFIQ (void); 141 142 /// Signal end of interrupt processing. 143 /// \param[in] irqn interrupt ID number 144 /// \return 0 on success, -1 on error. 145 int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); 146 147 /// Set interrupt pending flag. 148 /// \param[in] irqn interrupt ID number 149 /// \return 0 on success, -1 on error. 150 int32_t IRQ_SetPending (IRQn_ID_t irqn); 151 152 /// Get interrupt pending flag. 153 /// \param[in] irqn interrupt ID number 154 /// \return 0 - interrupt is not pending, 1 - interrupt is pending. 155 uint32_t IRQ_GetPending (IRQn_ID_t irqn); 156 157 /// Clear interrupt pending flag. 158 /// \param[in] irqn interrupt ID number 159 /// \return 0 on success, -1 on error. 160 int32_t IRQ_ClearPending (IRQn_ID_t irqn); 161 162 /// Set interrupt priority value. 163 /// \param[in] irqn interrupt ID number 164 /// \param[in] priority interrupt priority value 165 /// \return 0 on success, -1 on error. 166 int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); 167 168 /// Get interrupt priority. 169 /// \param[in] irqn interrupt ID number 170 /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. 171 uint32_t IRQ_GetPriority (IRQn_ID_t irqn); 172 173 /// Set priority masking threshold. 174 /// \param[in] priority priority masking threshold value 175 /// \return 0 on success, -1 on error. 176 int32_t IRQ_SetPriorityMask (uint32_t priority); 177 178 /// Get priority masking threshold 179 /// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. 180 uint32_t IRQ_GetPriorityMask (void); 181 182 /// Set priority grouping field split point 183 /// \param[in] bits number of MSB bits included in the group priority field comparison 184 /// \return 0 on success, -1 on error. 185 int32_t IRQ_SetPriorityGroupBits (uint32_t bits); 186 187 /// Get priority grouping field split point 188 /// \return current number of MSB bits included in the group priority field comparison with 189 /// optional IRQ_PRIORITY_ERROR bit set. 190 uint32_t IRQ_GetPriorityGroupBits (void); 191 192 #endif // IRQ_CTRL_H_ 193
