Searched refs:w0 (Results 1 – 4 of 4) sorted by relevance
12 register unsigned long w0 __asm__ ("w0") = instr; in semihost_exec()17 : "=r" (ret) : "r" (w0), "r" (x1) : "memory"); in semihost_exec()
48 ldr w0, =(SCTLR_EL3_RES1 | SCTLR_I_BIT | SCTLR_SA_BIT)
339 rx_desc_list->buf[0].w0 = GMAC_RXW0_WRAP; in priority_queue_init_as_idle()342 tx_desc_list->buf[0].w0 = 0U; in priority_queue_init_as_idle()501 rx_desc_list->buf[i].w0 = (uint32_t)rx_buf_addr & GMAC_RXW0_ADDR; in rx_descriptors_init()506 rx_desc_list->buf[rx_desc_list->len - 1U].w0 |= GMAC_RXW0_WRAP; in rx_descriptors_init()522 tx_desc_list->buf[i].w0 = 0U; in tx_descriptors_init()823 queue->rx_desc_list.buf[i].w0 &= ~GMAC_RXW0_OWNERSHIP; in rx_error_handler()1240 while ((rx_desc->w0 & GMAC_RXW0_OWNERSHIP) in frame_get()1272 while ((rx_desc->w0 & GMAC_RXW0_OWNERSHIP) in frame_get()1276 (uint8_t *)(rx_desc->w0 & GMAC_RXW0_ADDR); in frame_get()1320 rx_desc->w0 = ((uint32_t)frag->data & GMAC_RXW0_ADDR) | wrap; in frame_get()[all …]
220 uint32_t w0; member
