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Searched refs:sw (Results 1 – 25 of 58) sorted by relevance

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/Zephyr-latest/soc/openisa/rv32m1/
Dsoc_irq.S36 sw t1, 0x00(t0)
55 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
56 sw t1, __soc_esf_t_lpend0_OFFSET(a0)
57 sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
61 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
62 sw t1, __soc_esf_t_lpend1_OFFSET(a0)
63 sw t2, __soc_esf_t_lpcount1_OFFSET(a0)
Dwdog.S49 sw t2, WDOG_CNT_OFFSET(t1)
55 sw t2, WDOG_CS_OFFSET(t1)
59 sw t2, WDOG_TOVAL_OFFSET(t1)
/Zephyr-latest/snippets/bt-ll-sw-split/
DREADME.rst1 .. _snippet-bt-ll-sw-split:
3 Zephyr Bluetooth LE Controller (bt-ll-sw-split)
11 west build -S bt-ll-sw-split [...]
/Zephyr-latest/soc/andestech/ae350/
Dsoc_irq.S28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
31 sw t1, __soc_esf_t_ucode_OFFSET(a0)
/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dsoc_irq.S32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
35 sw t1, __soc_esf_t_ucode_OFFSET(a0)
Dstart.S51 sw t0, 0(t2)
62 sw t0, 0(t2)
74 sw t0, 0(t2)
/Zephyr-latest/modules/lvgl/
DCMakeLists.txt89 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend.c
90 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_al88.c
91 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_argb8888.c
92 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_i1.c
93 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_l8.c
94 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_rgb565.c
95 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_rgb888.c
96 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_arc.c
97 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_border.c
98 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_box_shadow.c
[all …]
/Zephyr-latest/arch/riscv/core/
Duserspace.S29 sw a5, 0(a2) # Init error value to 0
50 sw a4, 0(a2)
Dasm_macros.inc21 /* register-wide load/store based on lw/sw (XLEN = 32) */
28 sw \rs, \mem
Dreset.S72 sw t2, 0x00(t0)
/Zephyr-latest/drivers/clock_control/
Dclock_control_numaker_scc.c110 #define LOG_OSC_SW(osc, sw) \ argument
111 if (sw == NUMAKER_SCC_CLKSW_ENABLE) { \
113 } else if (sw == NUMAKER_SCC_CLKSW_DISABLE) { \
/Zephyr-latest/arch/xtensa/include/
Dxtensa_mmu_priv.h67 #define XTENSA_MMU_PTE(paddr, ring, sw, attr) \ argument
70 (((sw) << XTENSA_MMU_PTE_SW_SHIFT) & XTENSA_MMU_PTE_SW_MASK) | \
82 #define XTENSA_MMU_PTE_SW_SET(pte, sw) \ argument
83 (((pte) & ~XTENSA_MMU_PTE_SW_MASK) | (sw << XTENSA_MMU_PTE_SW_SHIFT))
/Zephyr-latest/dts/common/nordic/
Dnrf_common.dtsi38 sw_pwm: sw-pwm {
39 compatible = "nordic,nrf-sw-pwm";
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_context.S14 sw t0, __soc_esf_t_minttresh_OFFSET(a0)
/Zephyr-latest/soc/espressif/esp32c2/
Dsoc_irq.S15 sw ra, 0x00(sp)
/Zephyr-latest/soc/espressif/esp32c3/
Dsoc_irq.S15 sw ra, 0x00(sp)
/Zephyr-latest/boards/st/nucleo_wb05kz/
Dboard.cmake3 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw")
/Zephyr-latest/boards/st/nucleo_wb09ke/
Dboard.cmake3 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw")
/Zephyr-latest/samples/boards/nordic/mesh/onoff-app/src/
Dmain.c268 static struct switch_data sw; variable
433 k_timer_start(&sw.button_timer, K_SECONDS(1), K_NO_WAIT); in button_pressed()
443 sw.sw_num = pin_to_sw(pin_pos); in button_pressed()
459 k_work_submit(&sw.button_work); in button_cnt_timer()
586 k_work_init(&sw.button_work, button_pressed_worker); in main()
589 k_timer_init(&sw.button_timer, button_cnt_timer, NULL); in main()
/Zephyr-latest/soc/espressif/esp32c6/
Dsoc_irq.S21 sw ra, 0x00(sp)
/Zephyr-latest/arch/mips/core/
Dreset.S41 sw t2, 0(t0)
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.S38 sw ra, 0(sp)
/Zephyr-latest/include/zephyr/arch/mips/
Darch.h26 #define OP_STOREREG sw
/Zephyr-latest/soc/neorv32/
Dreset.S56 1: sw x0, 0(x8)
/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr_heap/boards/
Dqemu_cortex_m3.overlay3 #include <zephyr/dt-bindings/memory-attr/memory-attr-sw.h>

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