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/Zephyr-latest/arch/arm/core/cortex_m/
Dpm_s2ram.S26 #define CPU_CTX_SR_OFFSET(sr_name) \ argument
27 ___cpu_context_t_ ## sr_name ## _OFFSET
33 #define SAVE_SPECIAL_REG(sr_name, cpu_ctx_reg, tmp_reg) \ argument
34 mrs tmp_reg, sr_name; \
35 str tmp_reg, [cpu_ctx_reg, # CPU_CTX_SR_OFFSET(sr_name)];
37 #define RESTORE_SPECIAL_REG(sr_name, cpu_ctx_reg, tmp_reg) \ argument
38 ldr tmp_reg, [cpu_ctx_reg, # CPU_CTX_SR_OFFSET(sr_name)]; \
39 msr sr_name, tmp_reg;