Searched refs:simulation (Results 1 – 25 of 44) sorted by relevance
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| /Zephyr-latest/scripts/tests/twister/ |
| D | test_quarantine.py | 235 simulation, argument
266 simulator_name=simulation
273 simulator_name=simulation
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| /Zephyr-latest/boards/native/nrf_bsim/doc/ |
| D | nrf52_bsim.rst | 116 option indicates you want to run it detached from a BabbleSim simulation. This
120 When you want to run a simulation with radio activity you need to run also the
121 BableSim 2G4 (2.4GHz) physical layer simulation (phy).
154 And then run them together with BabbleSim's 2G4 physical layer simulation:
164 this simulation; the ``-D`` option tells the Phy how many devices will be run
165 in this simulation; the ``-d`` option tells each device which is its device
166 number in the simulation; and the ``-sim_length`` option specifies the length
167 of the simulation in microseconds.
200 breakpoint will pause the whole simulation.
213 If for some reason you want to limit the speed of the simulation to real
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| /Zephyr-latest/soc/snps/nsim/arc_classic/hs/ |
| D | Kconfig.defconfig.hs6x_smp | 18 # SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
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| D | Kconfig.defconfig.hs_smp | 22 # SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
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| /Zephyr-latest/boards/arm/fvp_baser_aemv8r/doc/ |
| D | aarch32.rst | 21 To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM
101 .. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-e…
104 .. [3] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/docs
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| D | aarch64.rst | 26 To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM
111 .. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-e…
114 .. [3] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/docs
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| /Zephyr-latest/doc/develop/test/ |
| D | bsim.rst | 18 When there is radio activity, this Linux executable will connect to the BabbleSim Phy simulation
36 necessary to connect them to a physical layer simulation. Thanks to this, these target boards can
43 When there is radio activity, BabbleSim tests require at the very least a physical layer simulation
183 - Scripts will spawn the processes for every simulated device and the physical layer simulation.
185 - Each test must have a unique simulation id, to enable running different tests in parallel.
190 off, and powering up after as a new simulation) should use separate simulation ids for each
191 simulation segment, ensuring that the radio activity of each segment can be inspected a
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| D | twister.rst | 153 simulation:
158 simulation:
165 By default, tests will be executed using the first entry in the simulation array. Another
166 simulation can be selected with ``--simulation <simulation_name>``.
170 The simulation name must match one of the element of ``SUPPORTED_EMU_PLATFORMS``.
226 power-efficient but slow CPU or simulation platform which can perform instruction accurate
227 simulation but does it slowly.
378 hardware. Currently architectures/platforms/simulation are supported:
392 - simulation:qemu:CONFIG_MPU=y
537 in the Renode simulation framework.
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| /Zephyr-latest/boards/native/doc/ |
| D | bsim_boards_design.rst | 25 :ref:`nRF54l15<nrf54l15bsim>` simulation boards, including how to use them,
51 integration testing of embedded code on workstation/simulation.
88 As such can provide better integration coverage than simulation in some cases,
92 They otherwise serve a very similar purpose to simulation integration tests.
98 - Using bsim boards with the BabbleSim Physical layer simulation allows
158 simulation specific ones.
167 - The SOC ``inf_clock`` layer provides an adaptation to the native simulator CPU "simulation"
168 and the handling of control between the "CPU simulation" (Zephyr threads) and the
231 In general simulation time will pass much faster than real time,
232 and the simulation results will not be affected in any way by the
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| /Zephyr-latest/soc/altr/zephyr_nios2f/cpu/ |
| D | ghrd_10m50da.qpf | 7 # (including device programming or simulation files), and any
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| /Zephyr-latest/scripts/pylib/twister/twisterlib/ |
| D | platform.py | 79 self.simulation: str = "na"
144 self.simulation = default_sim.name
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| D | testinstance.py | 267 simulation = options.sim_name
269 simulator = self.platform.simulator_by_name(simulation)
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| /Zephyr-latest/boards/lowrisc/opentitan_earlgrey/doc/ |
| D | index.rst | 33 the Earl Grey chip simulated in Verilator, a cycle-accurate HDL simulation tool.
69 in simulated flash. The OpenTitan test ROM will then run in simulation, read
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| /Zephyr-latest/boards/qemu/xtensa/doc/ |
| D | index.rst | 7 configuration provides support for the Xtensa simulation environment.
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| /Zephyr-latest/boards/renode/cortex_r8_virtual/doc/ |
| D | index.rst | 28 Your software will run in simulation and you don't need to "flash" the board in a traditional way,
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| /Zephyr-latest/boards/arm/mps3/doc/ |
| D | index.rst | 27 The FVPs have been selected for simulation since they provide access to the
28 Ethos-U55 NPU, which is unavailable in QEMU or other simulation platforms.
114 To run the Fixed Virtual Platform simulation tool you must download "FVP model
171 To run the Fixed Virtual Platform simulation tool you must download "FVP model
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| /Zephyr-latest/drivers/flash/ |
| D | Kconfig.simulator | 53 bool "Hardware timing simulation"
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| /Zephyr-latest/samples/userspace/shared_mem/ |
| D | README.rst | 56 performs a simulation of the enigma machine to produce cypher text(CT).
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| /Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/doc/ |
| D | index.rst | 124 3. https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms
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| /Zephyr-latest/boards/native/nrf_bsim/ |
| D | Kconfig | 11 NRF52 simulation model
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| /Zephyr-latest/boards/snps/nsim/arc_classic/doc/ |
| D | index.rst | 7 simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The
46 simulation anyway).
74 To run single-core Zephyr RTOS applications in simulation on this board,
77 To run multi-core Zephyr RTOS applications in simulation on this board,
139 You can run applications built for ``nsim`` board not only on nSIM simulation itself, but also on
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| /Zephyr-latest/drivers/eeprom/ |
| D | Kconfig | 114 bool "Hardware timing simulation"
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| /Zephyr-latest/doc/contribute/ |
| D | index.rst | 83 Similarly, external tooling used during compilation, code analysis, testing or simulation, can be
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| /Zephyr-latest/boards/gaisler/generic_leon3/doc/ |
| D | index.rst | 81 Running in simulation
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| /Zephyr-latest/boards/snps/nsim/arc_v/doc/ |
| D | index.rst | 7 simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The
33 To run single-core Zephyr RTOS applications in simulation on this board,
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