Searched refs:s7 (Results 1 – 15 of 15) sorted by relevance
| /Zephyr-latest/include/zephyr/arch/mips/ |
| D | thread.h | 41 unsigned long s7; /* saved register */ member
|
| /Zephyr-latest/arch/mips/include/mips/ |
| D | regdef.h | 49 #define s7 $23 macro
|
| /Zephyr-latest/include/zephyr/arch/riscv/ |
| D | thread.h | 41 unsigned long s7; /* saved register */ member
|
| /Zephyr-latest/arch/mips/core/offsets/ |
| D | offsets.c | 23 GEN_OFFSET_SYM(_callee_saved_t, s7);
|
| /Zephyr-latest/boards/sifive/hifive_unmatched/doc/ |
| D | index.rst | 24 :board: hifive_unmatched/fu740/s7
|
| /Zephyr-latest/arch/riscv/core/ |
| D | switch.S | 26 RV_I( op s7, _thread_offset_to_s7(reg) );\
|
| D | fatal.c | 133 LOG_ERR(" s1: " PR_REG " s7: " PR_REG, csf->s1, csf->s7); in z_riscv_fatal_error_csf()
|
| D | isr.S | 54 RV_I( sr s7, ___callee_saved_t_s7_OFFSET(sp) );\
|
| /Zephyr-latest/arch/mips/core/ |
| D | isr.S | 30 op s7, THREAD_O(s7)(reg) ;\
|
| /Zephyr-latest/samples/subsys/fs/fs_sample/ |
| D | README.rst | 76 Ext2 sample can be built for ``hifive_unmatched/fu740/s7`` or ``bl5340_dvk/nrf5340/cpuapp``. Because
82 :board: hifive_unmatched/fu740/s7 hifive_unmatched/fu740/u74
|
| /Zephyr-latest/arch/riscv/core/offsets/ |
| D | offsets.c | 41 GEN_OFFSET_SYM(_callee_saved_t, s7);
|
| /Zephyr-latest/dts/riscv/sifive/ |
| D | riscv64-fu740.dtsi | 35 compatible = "sifive,s7", "riscv";
|
| /Zephyr-latest/dts/riscv/starfive/ |
| D | jh7110-visionfive-v2.dtsi | 23 compatible = "sifive,s7", "riscv";
|
| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.2.rst | 1144 * :dtcompatible:`sifive,s7` (formerly ``riscv,sifive-s7``)
|
| D | release-notes-3.1.rst | 891 and :dtcompatible:`riscv,sifive-s7` CPU bindings
|
