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Searched refs:regions (Results 1 – 25 of 179) sorted by relevance

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/Zephyr-latest/drivers/pcie/host/
Dpcie_ecam.c42 } regions[PCIE_REGION_MAX]; member
89 data->regions[PCIE_REGION_IO].bus_start = cfg->ranges[i].pcie_bus_addr; in pcie_ecam_init()
90 data->regions[PCIE_REGION_IO].phys_start = cfg->ranges[i].host_map_addr; in pcie_ecam_init()
91 data->regions[PCIE_REGION_IO].size = cfg->ranges[i].map_length; in pcie_ecam_init()
93 if (data->regions[PCIE_REGION_IO].bus_start < 0x1000) { in pcie_ecam_init()
94 data->regions[PCIE_REGION_IO].allocation_offset = 0x1000; in pcie_ecam_init()
98 data->regions[PCIE_REGION_MEM].bus_start = cfg->ranges[i].pcie_bus_addr; in pcie_ecam_init()
99 data->regions[PCIE_REGION_MEM].phys_start = cfg->ranges[i].host_map_addr; in pcie_ecam_init()
100 data->regions[PCIE_REGION_MEM].size = cfg->ranges[i].map_length; in pcie_ecam_init()
102 if (data->regions[PCIE_REGION_MEM].bus_start < 0x1000) { in pcie_ecam_init()
[all …]
/Zephyr-latest/tests/drivers/mm/sys_mm_drv_api/src/
Dmain.c11 const struct sys_mm_drv_region *regions, *region; in ZTEST() local
13 regions = sys_mm_drv_query_memory_regions(); in ZTEST()
14 zassert_not_null(regions, NULL); in ZTEST()
16 SYS_MM_DRV_MEMORY_REGION_FOREACH(regions, region) in ZTEST()
21 sys_mm_drv_query_memory_regions_free(regions); in ZTEST()
/Zephyr-latest/arch/arm/core/mpu/
Darm_mpu_v8_internal.h508 regions[], uint8_t regions_num, uint8_t start_reg_index,
520 regions[], uint8_t regions_num, uint8_t start_reg_index, in mpu_configure_regions_and_partition()
527 if (regions[i].size == 0U) { in mpu_configure_regions_and_partition()
533 (!mpu_partition_is_valid(&regions[i]))) { in mpu_configure_regions_and_partition()
542 get_region_index(regions[i].start, regions[i].size); in mpu_configure_regions_and_partition()
557 uint32_t reg_last = regions[i].start + regions[i].size - 1; in mpu_configure_regions_and_partition()
559 if ((regions[i].start == u_reg_base) && in mpu_configure_regions_and_partition()
567 mpu_configure_region(u_reg_index, &regions[i]); in mpu_configure_regions_and_partition()
568 } else if (regions[i].start == u_reg_base) { in mpu_configure_regions_and_partition()
574 regions[i].start + regions[i].size); in mpu_configure_regions_and_partition()
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/Zephyr-latest/tests/boards/nrf/dmm/src/
Dmain.c44 struct dmm_test_region regions[DMM_TEST_REGION_COUNT]; member
65 memcpy(fixture.regions, dmm_test_regions, sizeof(dmm_test_regions)); in test_setup()
157 dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value, in ZTEST_USER_F()
165 dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value, in ZTEST_USER_F()
173 dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value, in ZTEST_USER_F()
181 dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value, in ZTEST_USER_F()
189 dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value, in ZTEST_USER_F()
197 dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value, in ZTEST_USER_F()
205 dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value, in ZTEST_USER_F()
213 dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value, in ZTEST_USER_F()
/Zephyr-latest/tests/drivers/coredump/coredump_api/boards/
Dqemu_riscv32.overlay13 memory-regions = <0x85000000 0x4>,
22 memory-regions = <0x86000000 0xC>;
29 memory-regions = <0x0 0x4>;
/Zephyr-latest/tests/drivers/uart/uart_errors/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay6 memory-regions = <&cpuapp_dma_region>;
10 memory-regions = <&cpuapp_dma_region>;
Dnrf54h20dk_nrf54h20_common.dtsi50 memory-regions = <&cpuapp_dma_region>;
59 memory-regions = <&cpuapp_dma_region>;
/Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay9 memory-regions = <&cpuapp_dma_region>;
13 memory-regions = <&cpuapp_dma_region>;
Dnrf54h20dk_nrf54h20_cpurad.overlay9 memory-regions = <&cpurad_dma_region>;
13 memory-regions = <&cpurad_dma_region>;
/Zephyr-latest/tests/drivers/spi/spi_error_cases/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay10 memory-regions = <&cpuapp_dma_region>;
14 memory-regions = <&cpuapp_dma_region>;
Dnrf54h20dk_nrf54h20_cpurad.overlay10 memory-regions = <&cpurad_dma_region>;
14 memory-regions = <&cpurad_dma_region>;
/Zephyr-latest/tests/drivers/uart/uart_async_api/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay6 memory-regions = <&cpuapp_dma_region>;
11 memory-regions = <&dma_fast_region>;
Dnrf54h20dk_nrf54h20_cpurad.overlay6 memory-regions = <&cpurad_dma_region>;
/Zephyr-latest/subsys/mem_mgmt/
Dmem_attr_heap.c108 const struct mem_attr_region_t *regions; in mem_attr_heap_pool_init() local
118 num_regions = mem_attr_get_regions(&regions); in mem_attr_heap_pool_init()
123 sw_attr = DT_MEM_SW_ATTR_GET(regions[idx].dt_attr); in mem_attr_heap_pool_init()
130 if (ma_heap_add(&regions[idx], sw_attr)) { in mem_attr_heap_pool_init()
DKconfig8 Enable a small library to manage the memory regions defined in the DT
10 time an array of the memory regions defined in the DT that can be
19 allocate memory from DeviceTree defined memory regions.
/Zephyr-latest/include/zephyr/drivers/mm/
Dsystem_mm.h424 #define SYS_MM_DRV_MEMORY_REGION_FOREACH(regions, iter) \ argument
425 for (iter = regions; iter->size; iter++)
450 void sys_mm_drv_query_memory_regions_free(const struct sys_mm_drv_region *regions);
/Zephyr-latest/doc/services/mem_mgmt/
Dindex.rst6 It is possible in the devicetree to mark the memory regions with attributes by
36 regions out of devicetree defined memory regions, for example:
52 The conventional and recommended way to deal and manage with memory regions
55 list of memory regions and their attributes are compiled in a user-accessible
57 and act on regions and attributes (see next section for more details).
113 For example we can define several memory regions with different attributes and
115 allocate memory from those regions:
144 The user can then dynamically carve memory out of those regions using the
163 When several regions are marked with the same attributes, the memory is allocated:
165 1. From the regions where the ``zephyr,memory-attr`` property has the requested
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/Zephyr-latest/tests/boards/nrf/dmm/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay47 memory-regions = <&cpuapp_dma_region>;
61 memory-regions = <&dma_fast_region>;
/Zephyr-latest/tests/drivers/uart/uart_elementary/boards/
Dnrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay28 memory-regions = <&cpuapp_dma_region>;
58 memory-regions = <&cpuapp_dma_region>;
/Zephyr-latest/doc/hardware/peripherals/
Dcoredump.rst11 any dump. And the driver exposes an API to add/remove dump memory regions at runtime.
12 A COREDUMP_TYPE_CALLBACK device requires exactly one entry in the memory-regions
/Zephyr-latest/tests/boards/nrf/i2c/i2c_slave/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay49 memory-regions = <&cpuapp_dma_region>;
62 memory-regions = <&cpuapp_dma_region>;
/Zephyr-latest/doc/kernel/usermode/
Dmpu_stack_objects.rst16 requirements for MPU regions. This is discussed in the memory placement
24 The MPU provides a fixed number of regions. Each region contains information
44 or even interactions between overlapping regions.
53 Some ARM MPUs use start and end addresses to define MPU regions and both the
59 logically OR regions to determine enforcement policy.
/Zephyr-latest/tests/drivers/uart/uart_mix_fifo_poll/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay6 memory-regions = <&cpuapp_dma_region>;
Dnrf54h20dk_nrf54h20_cpurad.overlay6 memory-regions = <&cpurad_dma_region>;
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dnrf54h20dk_nrf54h20_cpurad.overlay9 memory-regions = <&cpurad_dma_region>;

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