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Searched refs:reg_val (Results 1 – 25 of 89) sorted by relevance

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/Zephyr-latest/drivers/serial/
Duart_rcar.c141 uint8_t reg_val; in uart_rcar_set_baudrate() local
144 reg_val = data->clk_rate / (2 * (HSSRR_SRCYC_DEF_VAL + 1) * baud_rate) - 1; in uart_rcar_set_baudrate()
146 reg_val = ((data->clk_rate + 16 * baud_rate) / (32 * baud_rate) - 1); in uart_rcar_set_baudrate()
148 uart_rcar_write_8(dev, SCBRR, reg_val); in uart_rcar_set_baudrate()
154 uint16_t reg_val; in uart_rcar_poll_in() local
167 reg_val = uart_rcar_read_16(dev, SCFSR); in uart_rcar_poll_in()
168 reg_val &= ~SCFSR_RDF; in uart_rcar_poll_in()
169 uart_rcar_write_16(dev, SCFSR, reg_val); in uart_rcar_poll_in()
180 uint16_t reg_val; in uart_rcar_poll_out() local
189 reg_val = uart_rcar_read_16(dev, SCFSR); in uart_rcar_poll_out()
[all …]
Duart_renesas_ra.c217 uint8_t reg_val; in uart_ra_set_baudrate() local
219 reg_val = uart_ra_read_8(dev, SEMR); in uart_ra_set_baudrate()
220 reg_val |= (REG_MASK(SEMR_BGDM) | REG_MASK(SEMR_ABCS)); in uart_ra_set_baudrate()
221 reg_val &= ~(REG_MASK(SEMR_BRME) | REG_MASK(SEMR_ABCSE)); in uart_ra_set_baudrate()
222 uart_ra_write_8(dev, SEMR, reg_val); in uart_ra_set_baudrate()
224 reg_val = (data->clk_rate / (8 * data->current_config.baudrate)) - 1; in uart_ra_set_baudrate()
225 uart_ra_write_8(dev, BRR, reg_val); in uart_ra_set_baudrate()
256 uint8_t reg_val; in uart_ra_poll_out() local
265 reg_val = uart_ra_read_8(dev, SCR); in uart_ra_poll_out()
266 uart_ra_write_8(dev, SCR, reg_val & ~REG_MASK(SCR_TIE)); in uart_ra_poll_out()
[all …]
Duart_xlnx_ps.c182 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart() local
184 reg_val &= (~XUARTPS_CR_EN_DIS_MASK); in xlnx_ps_disable_uart()
186 reg_val |= XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS; in xlnx_ps_disable_uart()
187 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart()
206 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart() local
208 reg_val &= (~XUARTPS_CR_EN_DIS_MASK); in xlnx_ps_enable_uart()
210 reg_val |= XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN; in xlnx_ps_enable_uart()
211 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart()
285 uint32_t reg_val; in uart_xlnx_ps_init() local
304 reg_val = sys_read32(reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_init()
[all …]
/Zephyr-latest/drivers/timer/
Dxlnx_psttc_timer.c151 uint32_t reg_val; in sys_clock_driver_init() local
174 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
175 reg_val |= XTTCPS_CNT_CNTRL_RST_MASK; in sys_clock_driver_init()
176 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
179 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
180 reg_val |= XTTCPS_CNT_CNTRL_MATCH_MASK; in sys_clock_driver_init()
181 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
184 reg_val = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? in sys_clock_driver_init()
186 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET); in sys_clock_driver_init()
193 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_IER_OFFSET); in sys_clock_driver_init()
[all …]
Drcar_cmt_timer.c64 uint32_t reg_val; in cmt_isr() local
67 reg_val = sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET); in cmt_isr()
68 reg_val &= ~CSR_MATCH_FLAG; in cmt_isr()
69 sys_write32(reg_val, TIMER_BASE_ADDR + CMCSR0_OFFSET); in cmt_isr()
95 uint32_t reg_val; in sys_clock_driver_init() local
112 reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()
113 reg_val &= ~START_BIT; in sys_clock_driver_init()
114 sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()
116 reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR1_OFFSET); in sys_clock_driver_init()
117 reg_val &= ~START_BIT; in sys_clock_driver_init()
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_xlnx_gem.c98 uint32_t reg_val; in DT_INST_FOREACH_STATUS_OKAY() local
201 reg_val = sys_read32(dev_conf->base_addr + in DT_INST_FOREACH_STATUS_OKAY()
203 reg_val |= ETH_XLNX_GEM_NWCTRL_MDEN_BIT; in DT_INST_FOREACH_STATUS_OKAY()
204 sys_write32(reg_val, dev_conf->base_addr + in DT_INST_FOREACH_STATUS_OKAY()
273 uint32_t reg_val; in eth_xlnx_gem_isr() local
276 reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET); in eth_xlnx_gem_isr()
282 if (reg_val & ETH_XLNX_GEM_IXR_ERRORS_MASK) { in eth_xlnx_gem_isr()
284 dev->name, reg_val); in eth_xlnx_gem_isr()
296 if ((reg_val & ETH_XLNX_GEM_IXR_TX_COMPLETE_BIT) != 0) { in eth_xlnx_gem_isr()
307 if ((reg_val & ETH_XLNX_GEM_IXR_FRAME_RX_BIT) != 0) { in eth_xlnx_gem_isr()
[all …]
Deth_dwmac.c461 uint32_t reg_val; in dwmac_set_mac_addr() local
463 reg_val = (addr[5] << 8) | addr[4]; in dwmac_set_mac_addr()
464 REG_WRITE(MAC_ADDRESS_HIGH(n), reg_val | MAC_ADDRESS_HIGH_AE); in dwmac_set_mac_addr()
465 reg_val = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; in dwmac_set_mac_addr()
466 REG_WRITE(MAC_ADDRESS_LOW(n), reg_val); in dwmac_set_mac_addr()
474 uint32_t reg_val; in dwmac_set_config() local
477 (void) reg_val; /* silence the "unused variable" warning */ in dwmac_set_config()
489 reg_val = REG_READ(MAC_PKT_FILTER); in dwmac_set_config()
491 !(reg_val & MAC_PKT_FILTER_PR)) { in dwmac_set_config()
493 reg_val | MAC_PKT_FILTER_PR); in dwmac_set_config()
[all …]
Dphy_xlnx_gem.c40 uint32_t reg_val; in phy_xlnx_gem_mdio_read() local
56 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_read()
57 } while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10); in phy_xlnx_gem_mdio_read()
68 reg_val = ETH_XLNX_GEM_PHY_MAINT_CONST_BITS; in phy_xlnx_gem_mdio_read()
70 reg_val |= ETH_XLNX_GEM_PHY_MAINT_READ_OP_BIT; in phy_xlnx_gem_mdio_read()
72 reg_val |= (((uint32_t)phy_addr & ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_MASK) << in phy_xlnx_gem_mdio_read()
75 reg_val |= (((uint32_t)reg_addr & ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_MASK) << in phy_xlnx_gem_mdio_read()
78 sys_write32(reg_val, base_addr + ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET); in phy_xlnx_gem_mdio_read()
89 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_read()
90 } while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10); in phy_xlnx_gem_mdio_read()
[all …]
Deth_dwmac_stm32h7x.c50 uint32_t reg_addr, reg_val; in dwmac_bus_init() local
76 reg_val = sys_read32(reg_addr); in dwmac_bus_init()
77 sys_write32(reg_val | BIT(1), reg_addr); in dwmac_bus_init()
81 reg_val = sys_read32(reg_addr); in dwmac_bus_init()
82 sys_write32(reg_val | 0x03800000, reg_addr); in dwmac_bus_init()
/Zephyr-latest/drivers/charger/
Dsbs_charger.c71 uint16_t reg_val; in sbs_charger_charge_enable() local
74 reg_val = SBS_CHARGER_MODE_INHIBIT_CHARGE; in sbs_charger_charge_enable()
76 reg_val = 0; in sbs_charger_charge_enable()
80 SBS_CHARGER_MODE_INHIBIT_CHARGE, reg_val); in sbs_charger_charge_enable()
86 uint16_t reg_val; in sbs_charger_get_prop() local
91 ret = sbs_cmd_reg_read(dev, SBS_CHARGER_REG_STATUS, &reg_val); in sbs_charger_get_prop()
96 if (reg_val & SBS_CHARGER_STATUS_AC_PRESENT) { in sbs_charger_get_prop()
104 ret = sbs_cmd_reg_read(dev, SBS_CHARGER_REG_STATUS, &reg_val); in sbs_charger_get_prop()
109 if (reg_val & SBS_CHARGER_STATUS_BATTERY_PRESENT) { in sbs_charger_get_prop()
117 ret = sbs_cmd_reg_read(dev, SBS_CHARGER_REG_STATUS, &reg_val); in sbs_charger_get_prop()
[all …]
/Zephyr-latest/drivers/pwm/
Dpwm_rcar.c78 uint32_t reg_val = pwm_rcar_read(config, offs); in pwm_rcar_write_bit() local
81 reg_val |= bits; in pwm_rcar_write_bit()
83 reg_val &= ~(bits); in pwm_rcar_write_bit()
86 pwm_rcar_write(config, offs, reg_val); in pwm_rcar_write_bit()
92 uint32_t reg_val, power, diviser; in pwm_rcar_update_clk() local
127 reg_val = pwm_rcar_read(config, RCAR_PWM_CR(channel)); in pwm_rcar_update_clk()
128 reg_val &= ~RCAR_PWM_DIVISER_MASK; in pwm_rcar_update_clk()
129 reg_val |= (power << RCAR_PWM_DIVISER_SHIFT); in pwm_rcar_update_clk()
130 pwm_rcar_write(config, RCAR_PWM_CR(channel), reg_val); in pwm_rcar_update_clk()
139 uint32_t reg_val; in pwm_rcar_set_cycles() local
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/Zephyr-latest/soc/atmel/sam/common/
Dsoc_pmc.h83 uint32_t reg_val; in soc_pmc_mck_set_prescaler() local
87 reg_val = PMC_MCKR_PRES_CLK_1; in soc_pmc_mck_set_prescaler()
90 reg_val = PMC_MCKR_PRES_CLK_2; in soc_pmc_mck_set_prescaler()
93 reg_val = PMC_MCKR_PRES_CLK_4; in soc_pmc_mck_set_prescaler()
96 reg_val = PMC_MCKR_PRES_CLK_8; in soc_pmc_mck_set_prescaler()
99 reg_val = PMC_MCKR_PRES_CLK_16; in soc_pmc_mck_set_prescaler()
102 reg_val = PMC_MCKR_PRES_CLK_32; in soc_pmc_mck_set_prescaler()
105 reg_val = PMC_MCKR_PRES_CLK_64; in soc_pmc_mck_set_prescaler()
108 reg_val = PMC_MCKR_PRES_CLK_3; in soc_pmc_mck_set_prescaler()
112 reg_val = PMC_MCKR_PRES_CLK_1; in soc_pmc_mck_set_prescaler()
[all …]
/Zephyr-latest/drivers/pinctrl/renesas/smartbond/
Dpinctrl_smartbond.c28 uint32_t reg_val; in pinctrl_configure_pin() local
36 reg_val = pin->func << GPIO_P0_00_MODE_REG_PID_Pos; in pinctrl_configure_pin()
38 reg_val |= 0x01 << GPIO_P0_00_MODE_REG_PUPD_Pos; in pinctrl_configure_pin()
40 reg_val |= 0x02 << GPIO_P0_00_MODE_REG_PUPD_Pos; in pinctrl_configure_pin()
42 reg_val |= 0x03 << GPIO_P0_00_MODE_REG_PUPD_Pos; in pinctrl_configure_pin()
45 *reg = reg_val; in pinctrl_configure_pin()
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_gd32_afio.c121 uint32_t port, pin_bit, reg_val; in configure_pin() local
144 reg_val = *reg; in configure_pin()
145 reg_val &= ~GPIO_MODE_MASK(pin_num); in configure_pin()
158 reg_val |= GPIO_MODE_SET(pin_num, new_mode); in configure_pin()
163 reg_val |= GPIO_MODE_SET(pin_num, GPIO_MODE_INP_FLOAT); in configure_pin()
165 reg_val |= GPIO_MODE_SET(pin_num, GPIO_MODE_INP_PUPD); in configure_pin()
175 *reg = reg_val; in configure_pin()
186 uint32_t reg_val; in configure_remap() local
202 reg_val = *reg; in configure_remap()
203 reg_val &= ~(GD32_REMAP_MSK_GET(remap) << pos); in configure_remap()
[all …]
/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac.c161 uint32_t reg_val = DMA_SYSBUS_MODE_RD_OSR_LMT_SET(dma_cfg->rd_osr_lmt) | in dwxgmac_dma_init() local
174 sys_write32(reg_val, reg_addr); in dwxgmac_dma_init()
179 reg_val = DMA_TX_EDMA_CONTROL_TDPS_SET(dma_cfg->edma_tdps); in dwxgmac_dma_init()
181 sys_write32(reg_val, reg_addr); in dwxgmac_dma_init()
186 reg_val = DMA_RX_EDMA_CONTROL_RDPS_SET(dma_cfg->edma_rdps); in dwxgmac_dma_init()
188 sys_write32(reg_val, reg_addr); in dwxgmac_dma_init()
202 uint32_t reg_val; in dwxgmac_dma_chnl_init() local
216 reg_val = DMA_CHx_CONTROL_SPH_SET(dma_chnl_cfg->sph) | in dwxgmac_dma_chnl_init()
219 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
227 reg_val = DMA_CHx_TX_CONTROL_TXPBL_SET(dma_chnl_cfg->txpbl) | in dwxgmac_dma_chnl_init()
[all …]
/Zephyr-latest/arch/arm/core/cortex_a_r/
Dprep_c.c44 uint32_t reg_val = 0; in z_arm_floating_point_init() local
59 reg_val = __get_CPACR(); in z_arm_floating_point_init()
61 reg_val |= (CPACR_CP10(CPACR_FA) | CPACR_CP11(CPACR_FA)); in z_arm_floating_point_init()
62 __set_CPACR(reg_val); in z_arm_floating_point_init()
/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c31 uint8_t reg_val; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
126 uint8_t reg_val = mdio_clock_divider[i].reg_val; in mdio_xmc4xxx_set_clock_divider() local
133 FIELD_PREP(ETH_GMII_ADDRESS_CR_Msk, reg_val); in mdio_xmc4xxx_set_clock_divider()
/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c167 static uint32_t r8a779f0_get_div_helper(uint32_t reg_val, uint32_t module) in r8a779f0_get_div_helper() argument
174 reg_val >>= R8A779F0_CLK_SDSRC_DIV_SHIFT; in r8a779f0_get_div_helper()
175 reg_val &= R8A779F0_CLK_SDSRC_DIV_MASK; in r8a779f0_get_div_helper()
177 if (reg_val < 3) { in r8a779f0_get_div_helper()
179 return reg_val + 4; in r8a779f0_get_div_helper()
182 LOG_WRN("SDSRC clock has an incorrect divider value: %u", reg_val); in r8a779f0_get_div_helper()
185 reg_val >>= R8A779F0_CLK_SD0H_DIV_SHIFT; in r8a779f0_get_div_helper()
186 reg_val &= R8A779F0_CLK_SD0H_DIV_MASK; in r8a779f0_get_div_helper()
188 if (reg_val < 5) { in r8a779f0_get_div_helper()
189 return (1 << reg_val); in r8a779f0_get_div_helper()
[all …]
/Zephyr-latest/arch/arm/core/
Dgdbstub.c101 uint32_t reg_val; in arch_gdb_init() local
103 __asm__ volatile("mrc p14, 0, %0, c0, c2, 2" : "=r"(reg_val)::); in arch_gdb_init()
104 reg_val |= DBGDSCR_MONITOR_MODE_EN; in arch_gdb_init()
105 __asm__ volatile("mcr p14, 0, %0, c0, c2, 2" ::"r"(reg_val) :); in arch_gdb_init()
119 uint32_t reg_val = ctx.registers[PC]; in arch_gdb_step() local
121 reg_val &= ~(0x3); in arch_gdb_step()
122 __asm__ volatile("mcr p14, 0, %0, c0, c0, 4" ::"r"(reg_val) :); in arch_gdb_step()
124 reg_val = 0; in arch_gdb_step()
126 reg_val |= (DBGDBCR_MEANING_ADDR_MISMATCH & DBGDBCR_MEANING_MASK) << DBGDBCR_MEANING_SHIFT; in arch_gdb_step()
128 reg_val |= (0xF & DBGDBCR_BYTE_ADDR_MASK) << DBGDBCR_BYTE_ADDR_SHIFT; in arch_gdb_step()
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/Zephyr-latest/include/zephyr/dt-bindings/adc/
Dstm32_adc.h37 #define STM32_ADC(real_val, reg_val, mask, shift, reg) \ argument
41 (((reg_val) & STM32_ADC_REG_VAL_MASK) << STM32_ADC_REG_VAL_SHIFT) | \
63 #define STM32_ADC_RES(resolution, reg_val) \ argument
64 STM32_ADC(resolution, reg_val, STM32_ADC_RES_MASK, STM32_ADC_RES_SHIFT, \
/Zephyr-latest/drivers/sensor/bosch/bmi08x/
Dbmi08x.c55 return range_map[i].reg_val; in bmi08x_range_to_reg_val()
62 int32_t bmi08x_reg_val_to_range(uint8_t reg_val, const struct bmi08x_range *range_map, in bmi08x_reg_val_to_range() argument
68 if (reg_val == range_map[i].reg_val) { in bmi08x_reg_val_to_range()
/Zephyr-latest/drivers/spi/
Dspi_it8xxx2.c108 uint8_t reg_val; in spi_it8xxx2_set_freq() local
129 reg_val = sys_read8(cfg->base + SPI01_CTRL1); in spi_it8xxx2_set_freq()
130 reg_val = (reg_val & (~SSCK_FREQ_MASK)) | (i << 2); in spi_it8xxx2_set_freq()
131 sys_write8(reg_val, cfg->base + SPI01_CTRL1); in spi_it8xxx2_set_freq()
147 uint8_t reg_val; in spi_it8xxx2_configure() local
171 reg_val = sys_read8(cfg->base + SPI01_CTRL1); in spi_it8xxx2_configure()
173 reg_val |= CLOCK_POLARTY; in spi_it8xxx2_configure()
175 reg_val &= ~CLOCK_POLARTY; in spi_it8xxx2_configure()
177 sys_write8(reg_val, cfg->base + SPI01_CTRL1); in spi_it8xxx2_configure()
194 reg_val = sys_read8(cfg->base + SPI0C_INT_STS); in spi_it8xxx2_configure()
[all …]
/Zephyr-latest/drivers/regulator/
Dregulator_da1469x.c194 uint32_t reg_val; in regulator_da1469x_enable() local
197 reg_val = CRG_TOP->POWER_CTRL_REG & ~(config->desc->enable_mask); in regulator_da1469x_enable()
198 reg_val |= config->power_bits & config->desc->enable_mask; in regulator_da1469x_enable()
199 CRG_TOP->POWER_CTRL_REG |= reg_val; in regulator_da1469x_enable()
203 reg_val = *config->desc->dcdc_register & in regulator_da1469x_enable()
206 reg_val |= config->dcdc_bits; in regulator_da1469x_enable()
207 *config->desc->dcdc_register_shadow = reg_val; in regulator_da1469x_enable()
208 *config->desc->dcdc_register = reg_val; in regulator_da1469x_enable()
230 uint32_t reg_val; in regulator_da1469x_disable() local
237 reg_val = *config->desc->dcdc_register & in regulator_da1469x_disable()
[all …]
/Zephyr-latest/drivers/sensor/bosch/bma4xx/
Dbma4xx.c24 static int bma4xx_offset_to_reg_val(const struct sensor_value *val, uint8_t *reg_val) in bma4xx_offset_to_reg_val() argument
32 *reg_val = ug / BMA4XX_OFFSET_MICROG_PER_BIT; in bma4xx_offset_to_reg_val()
44 uint8_t reg_val[3]; in bma4xx_attr_set_offset() local
52 rc = bma4xx_offset_to_reg_val(val, &reg_val[0]); in bma4xx_attr_set_offset()
56 return bma4xx->hw_ops->write_reg(dev, reg_addr, reg_val[0]); in bma4xx_attr_set_offset()
61 rc = bma4xx_offset_to_reg_val(&val[i], &reg_val[i]); in bma4xx_attr_set_offset()
66 return bma4xx->hw_ops->write_data(dev, reg_addr, (uint8_t *)reg_val, in bma4xx_attr_set_offset()
67 sizeof(reg_val)); in bma4xx_attr_set_offset()
92 static int bma4xx_odr_to_reg(uint32_t microhertz, uint8_t *reg_val) in bma4xx_odr_to_reg() argument
101 *reg_val = i; in bma4xx_odr_to_reg()
[all …]
/Zephyr-latest/drivers/ethernet/phy/
Dphy_realtek_rtl8211f.c117 uint32_t reg_val; in phy_rt_rtl8211f_reset() local
156 ret = phy_rt_rtl8211f_read(dev, MII_BMCR, &reg_val); in phy_rt_rtl8211f_reset()
161 } while (reg_val & MII_BMCR_RESET); in phy_rt_rtl8211f_reset()
168 ret = phy_rt_rtl8211f_read(dev, MII_PHYID1R, &reg_val); in phy_rt_rtl8211f_reset()
173 } while (reg_val != REALTEK_OUI_MSB); in phy_rt_rtl8211f_reset()
405 uint32_t reg_val; in phy_rt_rtl8211f_clear_interrupt() local
416 ret = phy_rt_rtl8211f_read(dev, PHY_RT_RTL8211F_INSR_REG, &reg_val); in phy_rt_rtl8211f_clear_interrupt()
484 uint32_t reg_val; in phy_rt_rtl8211f_init() local
521 ret = phy_rt_rtl8211f_read(dev, PHY_RT_RTL8211F_MIICR1_REG, &reg_val); in phy_rt_rtl8211f_init()
527 reg_val |= PHY_RT_RTL8211F_MIICR1_TXDLY_MASK; in phy_rt_rtl8211f_init()
[all …]

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