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Searched refs:reg2 (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/arch/arm/core/cortex_a_r/
Dmacro_priv.inc26 * clobbers: reg0, reg1, reg2, reg3
28 .macro get_cpu_logic_id reg0, reg1, reg2, reg3
32 1: ldr \reg2, [\reg3, \reg1, lsl #2]
33 cmp \reg2, \reg0
/Zephyr-latest/arch/arc/include/
Dswap_macros.h313 .macro _check_and_inc_int_nest_counter, reg1, reg2
320 ld MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET]
324 ld MACRO_ARG(reg2), [MACRO_ARG(reg1), _kernel_offset_to_nested]
326 add MACRO_ARG(reg2), MACRO_ARG(reg2), 1
328 st MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET]
330 st MACRO_ARG(reg2), [MACRO_ARG(reg1), _kernel_offset_to_nested]
332 cmp MACRO_ARG(reg2), 1
339 .macro _dec_int_nest_counter, reg1, reg2
346 ld MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET]
350 ld MACRO_ARG(reg2), [MACRO_ARG(reg1), _kernel_offset_to_nested]
[all …]
/Zephyr-latest/tests/drivers/regulator/api/src/
Dmain.c18 static const struct device *const reg2 = DEVICE_DT_GET(DT_NODELABEL(reg2)); variable
119 config = reg2->config; in ZTEST()
142 zassert_true(regulator_common_is_init_enabled(reg2)); in ZTEST()
162 zassert_equal(regulator_disable(reg2), 0); in ZTEST()
163 zassert_equal(regulator_fake_disable_fake.arg0_val, reg2); in ZTEST()
167 zassert_equal(regulator_enable(reg2), 0); in ZTEST()
168 zassert_equal(regulator_fake_enable_fake.arg0_val, reg2); in ZTEST()
806 zassert_true(device_is_ready(reg2)); in setup()
814 zassert_true(regulator_is_enabled(reg2)); in setup()
/Zephyr-latest/tests/drivers/regulator/api/
Dapp.overlay16 reg2: REG2 {
/Zephyr-latest/drivers/clock_control/
Dclock_control_litex.c53 m.clkout[5].reg2 = CLKOUT5_REG2; in litex_clk_regs_addr_init()
57 m.clkout[i].reg2 = addr; in litex_clk_regs_addr_init()
367 ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg2, &frac); in litex_clk_get_clkout_divider()
413 uint8_t reg2) in litex_clk_print_clkout_regs() argument
422 litex_clk_check_DO(reg_name, reg2, &clkout_reg2); in litex_clk_print_clkout_regs()
433 drp_addr.clkout[i].reg2); in litex_clk_print_all_regs()
562 drp_addr.clkout[clkout_nr].reg2); in litex_clk_set_clock()
855 ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg2, &clkout_reg2); in litex_clk_get_duty_cycle()
1117 ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg2, &r2); in litex_clk_get_phase_data()
Dclock_control_litex.h221 uint8_t reg2; member