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/Zephyr-latest/boards/renesas/rcar_salvator_x/support/
Dopenocd.cfg20 cti create $_CHIPNAME.r7.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr $CR7_CTIBASE
21 target create $_CHIPNAME.r7 cortex_r4 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase $CR7_DBGBASE -defer-ex…
23 $_CHIPNAME.r7 configure -rtos auto
59 $_CHIPNAME.r7 arp_examine
60 catch { $_CHIPNAME.r7 arp_halt }
66 targets $_CHIPNAME.r7
69 $_CHIPNAME.r7 configure -event reset-end {
86 $_CHIPNAME.r7 configure -event gdb-attach {
/Zephyr-latest/soc/renesas/rcar/rcar_gen3/
DCMakeLists.txt6 zephyr_sources(r7/soc.c)
7 zephyr_include_directories(r7)
/Zephyr-latest/arch/arm/core/cortex_m/
Dswap_helper.S87 stmea r0!, {r4-r7}
93 mov r7, ip
95 stmea r0!, {r3-r7}
138 ldr r7, =_SCS_ICSR
158 str r6, [r7, #0]
245 ldmia r0!, {r3-r7}
251 mov ip, r7
254 ldmia r0!, {r4-r7}
Dcoredump.c30 uint32_t r7; member
82 arch_blk.r.r7 = esf->extra_info.callee->v4; in arch_coredump_info_dump()
Dpm_s2ram.S55 push {r4-r7}; \
84 pop {r4-r7}
Dfault_s.S95 push {r4-r7}
/Zephyr-latest/arch/arm/core/cortex_a_r/
Dreset.S101 mov r7, #0
235 mov r7, #0
236 strb r7, [r4, r2]
241 strb r7, [r4, r2]
272 ldr r7, [r0, #BOOT_PARAM_ABT_SP_OFFSET]
284 ldr r7, =(z_arm_abort_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)
304 mov sp, r7
/Zephyr-latest/include/zephyr/arch/nios2/
Dexception.h25 uint32_t r7; /* register args */ member
/Zephyr-latest/samples/subsys/llext/shell_loader/
DREADME.rst104 0: b580 push {r7, lr}
105 2: af00 add r7, sp, #0
117 1e: 46bd mov sp, r7
118 20: bc80 pop {r7}
/Zephyr-latest/arch/arc/include/
Dkernel_arch_data.h62 uintptr_t r7; member
83 uintptr_t r7;
Dswap_macros.h194 STR r7, sp, ___isf_t_r7_OFFSET
255 LDR r7, sp, ___isf_t_r7_OFFSET
/Zephyr-latest/arch/arc/core/
Dfatal.c31 " r7: 0x%" PRIxPTR "", esf->r4, esf->r5, esf->r6, esf->r7); in dump_arc_esf()
Duserspace.S23 mov_s r7, 0
207 mov r7, sp
/Zephyr-latest/arch/nios2/core/offsets/
Doffsets.c54 GEN_OFFSET_STRUCT(arch_esf, r7);
/Zephyr-latest/arch/nios2/core/
Dexception.S48 stw r7, __struct_arch_esf_r7_OFFSET(sp)
211 ldw r7, __struct_arch_esf_r7_OFFSET(sp)
Dfatal.c30 esf->r5, esf->r6, esf->r7, esf->r8); in z_nios2_fatal_error()
Dswap.S161 ldw r7, 12(sp)
/Zephyr-latest/arch/arc/core/secureshield/
Darc_secure.S17 mov r7, 0
/Zephyr-latest/arch/arc/core/offsets/
Doffsets.c56 GEN_OFFSET_SYM(_isf_t, r7);
/Zephyr-latest/samples/subsys/dap/
DREADME.rst49 lr: 0x00009cdd r7: 0x00000000 (0)
/Zephyr-latest/boards/renesas/rcar_h3ulcb/doc/
Drcar_h3ulcb_r7.rst208 Applications for the ``rcar_h3ulcb/r8a77951/r7`` board configuration can be built in the usual way …
212 :board: rcar_h3ulcb/r8a77951/r7
231 :board: rcar_h3ulcb/r8a77951/r7
/Zephyr-latest/dts/arm/renesas/rcar/gen3/
Drcar_gen3_cr7.dtsi22 compatible = "arm,cortex-r7";
/Zephyr-latest/cmake/
Dgcc-m-cpu.cmake63 set(GCC_M_CPU cortex-r7)