Searched refs:port_base (Results 1 – 5 of 5) sorted by relevance
| /Zephyr-latest/drivers/gpio/ |
| D | gpio_cc32xx.c | 51 unsigned long port_base; member
73 unsigned long port_base = gpio_config->port_base; in gpio_cc32xx_config() local
90 MAP_GPIODirModeSet(port_base, (1 << pin), GPIO_DIR_MODE_OUT); in gpio_cc32xx_config()
97 MAP_GPIODirModeSet(port_base, (1 << pin), GPIO_DIR_MODE_IN); in gpio_cc32xx_config()
107 unsigned long port_base = gpio_config->port_base; in gpio_cc32xx_port_get_raw() local
110 *value = MAP_GPIOPinRead(port_base, pin_packed); in gpio_cc32xx_port_get_raw()
120 unsigned long port_base = gpio_config->port_base; in gpio_cc32xx_port_set_masked_raw() local
122 MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)value); in gpio_cc32xx_port_set_masked_raw()
131 unsigned long port_base = gpio_config->port_base; in gpio_cc32xx_port_set_bits_raw() local
133 MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)mask); in gpio_cc32xx_port_set_bits_raw()
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| D | gpio_rv32m1.c | 26 PORT_Type *port_base; member
81 PORT_Type *port_base = config->port_base; in gpio_rv32m1_configure() local
86 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_rv32m1_configure()
158 port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr; in gpio_rv32m1_configure()
224 PORT_Type *port_base = config->port_base; in gpio_rv32m1_pin_interrupt_configure() local
227 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_rv32m1_pin_interrupt_configure()
239 port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr; in gpio_rv32m1_pin_interrupt_configure()
262 int_status = config->port_base->ISFR; in gpio_rv32m1_port_isr()
265 config->port_base->ISFR = int_status; in gpio_rv32m1_port_isr()
315 .port_base = (PORT_Type *) INST_DT_PORT_ADDR(n), \
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| D | gpio_mcux.c | 30 PORT_Type *port_base; member
119 PORT_Type *port_base = config->port_base; in gpio_mcux_port_configure() local
124 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_mcux_port_configure()
201 port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr; in gpio_mcux_port_configure()
346 PORT_Type *port_base = config->port_base; in gpio_mcux_pin_interrupt_configure() local
349 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_mcux_pin_interrupt_configure()
372 port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr; in gpio_mcux_pin_interrupt_configure()
399 int_status = config->port_base->ISFR; in gpio_mcux_port_isr()
402 config->port_base->ISFR = int_status; in gpio_mcux_port_isr()
503 .port_base = (PORT_Type *)GPIO_PORT_BASE_ADDR(n), \
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| D | gpio_davinci.c | 31 ((struct gpio_davinci_regs *)DEVICE_MMIO_NAMED_GET(dev, port_base))
51 DEVICE_MMIO_NAMED_RAM(port_base);
60 DEVICE_MMIO_NAMED_ROM(port_base);
158 DEVICE_MMIO_NAMED_MAP(dev, port_base, K_MEM_CACHE_NONE); in gpio_davinci_init()
187 DEVICE_MMIO_NAMED_ROM_INIT(port_base, DT_DRV_INST(n)), \
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| D | gpio_nxp_s32.c | 35 #define PORT_READ(p) sys_read32(config->port_base + SIUL2_MSCR(p))
36 #define PORT_WRITE(p, v) sys_write32((v), config->port_base + SIUL2_MSCR(p))
57 mem_addr_t port_base; member
578 .port_base = DT_INST_REG_ADDR_BY_NAME(n, mscr), \
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