1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_KBC_H 8 #define _MEC_KBC_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* ---- EM8042 Keyboard Controller (KBC) ---- */ 14 15 /* EC_KBC_STS and KBC_STS_RD bit definitions */ 16 #define MCHP_KBC_STS_OBF_POS 0u 17 #define MCHP_KBC_STS_OBF BIT(MCHP_KBC_STS_OBF_POS) 18 #define MCHP_KBC_STS_IBF_POS 1u 19 #define MCHP_KBC_STS_IBF BIT(MCHP_KBC_STS_IBF_POS) 20 #define MCHP_KBC_STS_UD0_POS 2u 21 #define MCHP_KBC_STS_UD0 BIT(MCHP_KBC_STS_UD0_POS) 22 #define MCHP_KBC_STS_CD_POS 3u 23 #define MCHP_KBC_STS_CD BIT(MCHP_KBC_STS_CD_POS) 24 #define MCHP_KBC_STS_UD1_POS 4u 25 #define MCHP_KBC_STS_UD1 BIT(MCHP_KBC_STS_UD1_POS) 26 #define MCHP_KBC_STS_AUXOBF_POS 5u 27 #define MCHP_KBC_STS_AUXOBF BIT(MCHP_KBC_STS_AUXOBF_POS) 28 #define MCHP_KBC_STS_UD2_POS 6u 29 #define MCHP_KBC_STS_UD2_MASK0 0x03u 30 #define MCHP_KBC_STS_UD2_MASK 0xc0u 31 #define MCHP_KBC_STS_UD2_0_POS 6u 32 #define MCHP_KBC_STS_UD2_0 BIT(6) 33 #define MCHP_KBC_STS_UD2_1 BIT(7) 34 35 /* KBC_CTRL bit definitions */ 36 #define MCHP_KBC_CTRL_UD3_POS 0u 37 #define MCHP_KBC_CTRL_UD3 BIT(MCHP_KBC_CTRL_UD3_POS) 38 #define MCHP_KBC_CTRL_SAEN_POS 1u 39 #define MCHP_KBC_CTRL_SAEN BIT(MCHP_KBC_CTRL_SAEN_POS) 40 #define MCHP_KBC_CTRL_PCOBFEN_POS 2u 41 #define MCHP_KBC_CTRL_PCOBFEN BIT(MCHP_KBC_CTRL_PCOBFEN_POS) 42 #define MCHP_KBC_CTRL_UD4_POS 3u 43 #define MCHP_KBC_CTRL_UD4_MASK0 0x03u 44 #define MCHP_KBC_CTRL_UD4_MASK 0x18u 45 #define MCHP_KBC_CTRL_OBFEN_POS 5u 46 #define MCHP_KBC_CTRL_OBFEN BIT(MCHP_KBC_CTRL_OBFEN_POS) 47 #define MCHP_KBC_CTRL_UD5_POS 6u 48 #define MCHP_KBC_CTRL_UD5 BIT(MCHP_KBC_CTRL_UD5_POS) 49 #define MCHP_KBC_CTRL_AUXH_POS 7u 50 #define MCHP_KBC_CTRL_AUXH BIT(MCHP_KBC_CTRL_AUXH_POS) 51 52 /* PCOBF register bit definitions */ 53 #define MCHP_KBC_PCOBF_EN_POS 0u 54 #define MCHP_KBC_PCOBF_EN BIT(MCHP_KBC_PCOBF_EN_POS) 55 56 /* KBC_PORT92_EN register bit definitions */ 57 #define MCHP_KBC_PORT92_EN_POS 0u 58 #define MCHP_KBC_PORT92_EN BIT(MCHP_KBC_PORT92_EN_POS) 59 60 /* HOST Port 92h emulation registers */ 61 #define MCHP_PORT92_HOST_MASK GENMASK(1, 0) 62 #define MCHP_PORT92_HOST_ALT_CPU_RST_POS 0 63 #define MCHP_PORT92_HOST_ALT_CPU_RST BIT(0) 64 #define MCHP_PORT92_HOST_ALT_GA20_POS 1 65 #define MCHP_PORT92_HOST_ALT_GA20 BIT(1) 66 67 /* GATEA20_CTRL */ 68 #define MCHP_PORT92_GA20_CTRL_MASK BIT(0) 69 #define MCHP_PORT92_GA20_CTRL_VAL_POS 0 70 #define MCHP_PORT92_GA20_CTRL_VAL_HI BIT(0) 71 72 /* 73 * SETGA20L - writes of any data to this register causes 74 * GATEA20 latch to be set. 75 */ 76 #define MCHP_PORT92_SETGA20L_MASK BIT(0) 77 #define MCHP_PORT92_SETGA20L_SET_POS 0 78 #define MCHP_PORT92_SETGA20L_SET BIT(0) 79 80 /* 81 * RSTGA20L - writes of any data to this register causes 82 * the GATEA20 latch to be reset 83 */ 84 #define MCHP_PORT92_RSTGA20L_MASK BIT(0) 85 #define MCHP_PORT92_RSTGA20L_SET_POS 0 86 #define MCHP_PORT92_RSTGA20L_RST BIT(0) 87 88 /* ACTV */ 89 #define MCHP_PORT92_ACTV_MASK BIT(0) 90 #define MCHP_PORT92_ACTV_ENABLE BIT(0) 91 92 /** @brief 8042 Emulated Keyboard controller. Size = 820(0x334) */ 93 struct kbc_regs { 94 volatile uint32_t HOST_AUX_DATA; 95 volatile uint32_t KBC_STS_RD; 96 uint8_t RSVD1[0x100 - 0x08]; 97 volatile uint32_t EC_DATA; 98 volatile uint32_t EC_KBC_STS; 99 volatile uint32_t KBC_CTRL; 100 volatile uint32_t EC_AUX_DATA; 101 uint32_t RSVD2[1]; 102 volatile uint32_t PCOBF; 103 uint8_t RSVD3[0x0330 - 0x0118]; 104 volatile uint32_t KBC_PORT92_EN; 105 }; 106 107 /** @brief Fast Port92h Registers (PORT92) */ 108 struct port92_regs { 109 volatile uint32_t HOST_P92; 110 uint8_t RSVD1[0x100u - 0x04u]; 111 volatile uint32_t GATEA20_CTRL; 112 uint32_t RSVD2[1]; 113 volatile uint32_t SETGA20L; 114 volatile uint32_t RSTGA20L; 115 uint8_t RSVD3[0x0330ul - 0x0110ul]; 116 volatile uint32_t ACTV; 117 }; 118 119 #endif /* #ifndef _MEC_KBC_H */ 120
