Searched refs:pipeline (Results 1 – 8 of 8) sorted by relevance
| /Zephyr-latest/scripts/pylib/twister/twisterlib/ |
| D | runner.py | 937 def _add_to_pipeline(self, pipeline, op: str, additionals: dict=None): argument
943 pipeline.put(task)
951 def process(self, pipeline, done, message, lock, results): argument
983 self._add_to_pipeline(pipeline, next_op)
1016 self._add_to_pipeline(pipeline, next_op)
1065 self._add_to_pipeline(pipeline, next_op)
1096 self._add_to_pipeline(pipeline, next_op)
1123 self._add_to_pipeline(pipeline, next_op, additionals)
1152 self._add_to_pipeline(pipeline, next_op, additionals)
1764 self.pipeline = None
[all …]
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| /Zephyr-latest/subsys/logging/frontends/ |
| D | Kconfig | 65 in the buffer and flushed to the STMESP once the pipeline is ready.
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| /Zephyr-latest/doc/hardware/arch/ |
| D | arc-support-status.rst | 92 .. [#f6] currently only ARC VPX scalar port is supported. The support of VPX vector pipeline, VCCM,
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| /Zephyr-latest/doc/connectivity/networking/ |
| D | net-stack-architecture.rst | 96 act as a way to separate the data processing pipeline (bottom-half) as
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| /Zephyr-latest/boards/heltec/heltec_wireless_stick_lite_v3/doc/ |
| D | index.rst | 13 … MCU-based SoC (dual-core Xtensa® 32-bit LX7 microprocessor, five stage pipeline rack Structure, m…
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| /Zephyr-latest/boards/toradex/verdin_imx8mp/doc/ |
| D | index.rst | 44 processors. The microcontroller employs an efficient in-order super-scalar pipeline, allowing
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-4.0.rst | 892 * Removed an init order circular dependency for the camera pipeline on NXP RT10xx platforms
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| D | release-notes-2.7.rst | 1881 * :github:`30245` - Bluetooth: controller: event scheduling pipeline preemption by short schedule
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