/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/ |
D | lib_helpers.h | 17 #define read_sysreg32(op1, CRn, CRm, op2) \ argument 21 #CRm ", " #op2 : "=r" (val) :: "memory"); \ 25 #define write_sysreg32(val, op1, CRn, CRm, op2) \ argument 28 #CRm ", " #op2 :: "r" (val) : "memory"); \ 45 #define MAKE_REG_HELPER(reg, op1, CRn, CRm, op2) \ argument 48 return read_sysreg32(op1, CRn, CRm, op2); \ 52 write_sysreg32(val, op1, CRn, CRm, op2); \
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/Zephyr-latest/include/zephyr/arch/arc/asm-compat/ |
D | asm-macro-32-bit-mwdt.h | 91 .macro CMPR, op1, op2 92 cmp op1, op2
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D | asm-macro-64-bit-mwdt.h | 91 .macro CMPR, op1, op2 92 cmpl op1, op2
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D | asm-macro-32-bit-gnu.h | 99 .macro CMPR op1, op2 100 cmp \op1, \op2
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D | asm-macro-64-bit-gnu.h | 111 .macro CMPR op1, op2 112 cmpl \op1, \op2
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/Zephyr-latest/soc/microchip/mec/mec15xx/ |
D | soc_espi_saf_v1.h | 132 #define MCHP_SAF_OPCODE_REG_VAL(op0, op1, op2, op3) \ argument 134 (((uint32_t)(op2)&0xffU) << 16) | (((uint32_t)(op3)&0xffU) << 24))
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/Zephyr-latest/soc/microchip/mec/mec172x/ |
D | soc_espi_saf_v2.h | 156 #define MCHP_SAF_OPCODE_REG_VAL(op0, op1, op2, op3) \ argument 158 (((uint32_t)(op2)&0xffU) << 16) | (((uint32_t)(op3)&0xffU) << 24))
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/Zephyr-latest/tests/lib/cmsis_dsp/matrix/src/ |
D | binary_q7.c | 115 op2, arm_mat_mult_q7, OP2_MULT,
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D | unary_q15.c | 108 op2, arm_mat_add_q15, OP2_ADD, 111 op2, arm_mat_sub_q15, OP2_SUB,
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D | unary_q31.c | 108 op2, arm_mat_add_q31, OP2_ADD, 111 op2, arm_mat_sub_q31, OP2_SUB,
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D | binary_f32.c | 113 op2, arm_mat_mult_f32, OP2_MULT,
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D | binary_f64.c | 113 op2, arm_mat_mult_f64, OP2_MULT,
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D | binary_q31.c | 111 op2, arm_mat_mult_q31, OP2_MULT,
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D | binary_f16.c | 113 op2, arm_mat_mult_f16, OP2_MULT,
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D | binary_q15.c | 119 op2, arm_mat_mult_q15, OP2_MULT,
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D | unary_f16.c | 125 op2, arm_mat_add_f16, OP2_ADD, 128 op2, arm_mat_sub_f16, OP2_SUB,
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D | unary_f32.c | 121 op2, arm_mat_add_f32, OP2_ADD, 124 op2, arm_mat_sub_f32, OP2_SUB,
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D | unary_f64.c | 109 op2, arm_mat_sub_f64, OP2_SUB,
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