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/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dmchp-xec-ecia.h19 #define MCHP_XEC_ECIA(g, gb, na, nd) \ argument
21 (((nd) & 0xff) << 24))
/Zephyr-latest/tests/drivers/console/line_splitting/
Dline_splitting.robot11 Write Line To Uart \rabc\nd\n waitForEcho=false
13 Write Line To Uart \rabc\nd\n waitForEcho=false
/Zephyr-latest/tests/cmake/zephyr_get/
DCMakeLists.txt146 IMAGE zephyr_get_2nd "sysbuild.2nd"
160 IMAGE zephyr_get_2nd "sysbuild.2nd"
180 IMAGE zephyr_get_2nd "sysbuild.2nd"
231 IMAGE zephyr_get_2nd "sysbuild.2nd"
244 IMAGE zephyr_get_2nd "sysbuild.2nd;sysbuild.main"
257 IMAGE zephyr_get_2nd "sysbuild.2nd;sysbuild.main;cmake cache;environment;local"
266 IMAGE zephyr_get_2nd "sysbuild.2nd;cmake cache;environment"
278 IMAGE zephyr_get_2nd "sysbuild.2nd;sysbuild.main;environment"
375 IMAGE zephyr_get_2nd "sysbuild.2nd"
382 IMAGE zephyr_get_2nd "sysbuild.2nd"
[all …]
Dsysbuild.cmake6 foreach(suffix "2nd" "3rd")
/Zephyr-latest/arch/arc/core/
Dreset.S95 bz.nd done_icache_invalidate
108 bz.nd done_dcache_invalidate
/Zephyr-latest/cmake/sca/sparse/
Dsparse.template8 # argument to be passed to sparse is 2nd argument after `--`.
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.dw18 Designware Interrupt Controller can be used as a 2nd level interrupt
DKconfig.multilevel50 where storage for 2nd level interrupt ISRs begins. This is
/Zephyr-latest/samples/subsys/smf/smf_calculator/
DREADME.rst14 Fig 2.18 of *Practical UML Statecharts in C/C++* 2nd Edition by Miro Samek.
99 *Practical UML Statecharts in C/C++* 2nd Edition by Miro Samek
/Zephyr-latest/samples/drivers/espi/
DREADME.rst48 2nd phase completed
/Zephyr-latest/boards/phytec/phyboard_polis/
Dphyboard_polis_mimx8mm6_m4.dts107 /* UART of the M4 Core (2nd tty on Debug USB connector) */
/Zephyr-latest/soc/espressif/common/
DKconfig22 The Simple Boot is a booting method that doesn't need a 2nd stage bootloader.
DKconfig.esptool75 # The 1st and 2nd bootloader doesn't support opi mode,
/Zephyr-latest/samples/subsys/smf/hsm_psicc2/
DREADME.rst32 Practical UML Statecharts in C/C++, 2nd Edition, by Miro Samek (PSiCC2). Ebook available from
/Zephyr-latest/drivers/serial/
DKconfig.native_posix70 The 2nd UART will not be affected by this option.
/Zephyr-latest/boards/waveshare/esp32s3_touch_lcd_1_28/doc/
Dindex.rst112 The board could be loaded using the single binary image, without 2nd stage bootloader.
/Zephyr-latest/boards/01space/esp32c3_042_oled/doc/
Dindex.rst97 The board can be loaded using a single binary image, without 2nd stage bootloader.
/Zephyr-latest/boards/franzininho/esp32s2_franzininho/doc/
Dindex.rst53 The board could be loaded using the single binary image, without 2nd stage bootloader.
/Zephyr-latest/boards/seeed/xiao_esp32c3/doc/
Dindex.rst77 The board could be loaded using the single binary image, without 2nd stage bootloader.
/Zephyr-latest/boards/m5stack/stamp_c3/doc/
Dindex.rst59 The board could be loaded using the single binary image, without 2nd stage bootloader.
/Zephyr-latest/boards/lilygo/ttgo_t7v1_5/doc/
Dindex.rst72 The board could be loaded using the single binary image, without 2nd stage bootloader.
/Zephyr-latest/boards/hardkernel/odroid_go/doc/
Dindex.rst95 The board could be loaded using the single binary image, without 2nd stage bootloader.
/Zephyr-latest/boards/lilygo/ttgo_t8s3/doc/
Dindex.rst93 The board could be loaded using the single binary image, without 2nd stage bootloader.
/Zephyr-latest/boards/lilygo/ttgo_t8c3/doc/
Dindex.rst80 The board could be loaded using the single binary image, without 2nd stage bootloader.
/Zephyr-latest/boards/seeed/xiao_esp32c6/doc/
Dindex.rst87 The board could be loaded using the single binary image, without 2nd stage bootloader.

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