| /Zephyr-latest/drivers/adc/ |
| D | adc_common.c | 13 uint8_t mul; in adc_gain_invert() member
17 [ADC_GAIN_1_6] = {.mul = 6, .div = 1}, in adc_gain_invert()
18 [ADC_GAIN_1_5] = {.mul = 5, .div = 1}, in adc_gain_invert()
19 [ADC_GAIN_1_4] = {.mul = 4, .div = 1}, in adc_gain_invert()
20 [ADC_GAIN_1_3] = {.mul = 3, .div = 1}, in adc_gain_invert()
21 [ADC_GAIN_2_5] = {.mul = 5, .div = 2}, in adc_gain_invert()
22 [ADC_GAIN_1_2] = {.mul = 2, .div = 1}, in adc_gain_invert()
23 [ADC_GAIN_2_3] = {.mul = 3, .div = 2}, in adc_gain_invert()
24 [ADC_GAIN_4_5] = {.mul = 5, .div = 4}, in adc_gain_invert()
25 [ADC_GAIN_1] = {.mul = 1, .div = 1}, in adc_gain_invert()
[all …]
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_litex.c | 303 ldev->g_config.mul = 1; in litex_clk_update_global_config()
313 ldev->g_config.mul = low_time + high_time; in litex_clk_update_global_config()
327 static uint64_t litex_clk_calc_global_frequency(uint32_t mul, uint32_t div) in litex_clk_calc_global_frequency() argument
331 f = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC * (uint64_t)mul; in litex_clk_calc_global_frequency()
343 f = litex_clk_calc_global_frequency(ldev->g_config.mul, in litex_clk_get_real_global_frequency()
347 ldev->ts_g_config.mul = ldev->g_config.mul; in litex_clk_get_real_global_frequency()
473 ldev->ts_g_config.freq, ldev->ts_g_config.mul, in litex_clk_print_all_params()
477 ldev->g_config.freq, ldev->g_config.mul, ldev->g_config.div); in litex_clk_print_all_params()
618 mul = ldev->ts_g_config.mul; in litex_clk_set_mulreg() local
621 if (mul == 1) { in litex_clk_set_mulreg()
[all …]
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| /Zephyr-latest/cmake/compiler/gcc/ |
| D | target_sparc.cmake | 9 # SPARC V8, mul/div, casa
13 # SPARC V8, mul/div, no casa
|
| /Zephyr-latest/soc/atmel/sam/sam4l/ |
| D | soc.c | 90 static inline uint32_t pll_config_init(uint32_t divide, uint32_t mul) in pll_config_init() argument
114 vco_hz = XTAL_FREQ * mul; in pll_config_init()
120 if ((vco_hz < PLL_MIN_HZ * 2) && (mul <= 8)) { in pll_config_init()
121 mul *= 2; in pll_config_init()
133 pll_value |= ((mul - 1) << SCIF_PLL_PLLMUL_Pos) | in pll_config_init()
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | f4_i2s2_pll.overlay | 30 /delete-property/ mul;
59 mul-n = <336>;
67 mul-n = <384>;
|
| D | f0_i2c1_hsi.overlay | 30 /delete-property/ mul;
55 mul = <8>;
|
| D | f3_i2c1_hsi.overlay | 30 /delete-property/ mul;
55 mul = <8>;
|
| D | g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 23 /delete-property/ mul-n;
51 mul-n = <8>;
|
| D | g4_i2c1_hsi_adc1_pllp.overlay | 23 /delete-property/ mul-n;
47 mul-n = <8>;
|
| D | g0_i2c1_sysclk_lptim1_lsi.overlay | 23 /delete-property/ mul-n;
51 mul-n = <8>;
|
| D | l4_i2c1_hsi_lptim1_lse.overlay | 28 /delete-property/ mul-n;
56 mul-n = <20>;
|
| D | l4_i2c1_sysclk_lptim1_lsi.overlay | 28 /delete-property/ mul-n;
56 mul-n = <20>;
|
| /Zephyr-latest/tests/kconfig/functions/ |
| D | Kconfig | 30 default $(mul, 10)
34 default $(mul, 10, 3)
38 default $(mul, 10, 3, 2)
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/ |
| D | clear_clocks.overlay | 37 /delete-property/ mul-n;
47 /delete-property/ mul-n;
57 /delete-property/ mul-n;
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/ |
| D | core_init.overlay | 42 /delete-property/ mul-n;
52 /delete-property/ mul-n;
62 /delete-property/ mul-n;
99 mul-n = <24>;
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/ |
| D | pll_csi_100.overlay | 17 /* Test another couple of M-div N-mul to obtain 100MHz from the CSI */
20 mul-n = <50>;
|
| D | pll_csi_240.overlay | 17 /* Test another couple of M-div N-mul to obtain 240MHz from the CSI */
20 mul-n = <120>;
|
| D | clear_clocks.overlay | 40 /delete-property/ mul-n;
51 /delete-property/ mul-n;
|
| /Zephyr-latest/arch/nios2/ |
| D | CMakeLists.txt | 20 zephyr_cc_option(-mhw-mul)
22 zephyr_cc_option(-mno-hw-mul)
|
| /Zephyr-latest/boards/st/nucleo_f030r8/ |
| D | nucleo_f030r8_stm32f030x8_1.overlay | 17 mul = <12>;
|
| /Zephyr-latest/boards/shields/x_nucleo_iks02a1/boards/ |
| D | nucleo_f411re.overlay | 9 mul-n = <192>;
|
| /Zephyr-latest/drivers/ptp_clock/ |
| D | ptp_clock_nxp_enet.c | 99 int32_t mul; in ptp_clock_nxp_enet_rate_adjust() local
139 mul = 0; in ptp_clock_nxp_enet_rate_adjust()
141 mul = val; in ptp_clock_nxp_enet_rate_adjust()
146 ENET_Ptp1588AdjustTimer(data->base, corr, mul); in ptp_clock_nxp_enet_rate_adjust()
|
| /Zephyr-latest/boards/telink/tlsr9518adk80d/ |
| D | tlsr9518adk80d-pinctrl.dtsi | 10 /* Set pad-mul-sel register value.
13 pad-mul-sel = <1>;
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/ |
| D | f1_pll_64_hsi_8.overlay | 17 mul = <16>;
|
| D | pll_32_hsi_16.overlay | 18 mul = <4>;
|
