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Searched refs:level2 (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/tests/subsys/logging/log_links/src/
Dmain.c175 uint32_t level2; in test_single_runtime_level() local
178 level2 = log_filter_get(&backend2, d, s, true); in test_single_runtime_level()
182 zassert_equal(level2, MIN(*link_level, LOG_LEVEL_INF), in test_single_runtime_level()
184 d, s, level2, MIN(*link_level, LOG_LEVEL_INF)); in test_single_runtime_level()
189 level2 = log_filter_get(&backend2, d, s, true); in test_single_runtime_level()
192 zassert_equal(level2, 2, "%d:%d Unexpected compiled level (%d vs %d)", in test_single_runtime_level()
193 d, s, level2, 2); in test_single_runtime_level()
/Zephyr-latest/boards/intel/socfpga_std/cyclonev_socdk/doc/
Dindex.rst254 Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT
290 Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT
317 Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT
/Zephyr-latest/scripts/
Dcheckpatch.pl4259 my $level2 = $level;
4260 $level2 = "dbg" if ($level eq "debug");
4262 …"Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$leve…
/Zephyr-latest/doc/releases/
Drelease-notes-2.0.rst1288 * :github:`15133` - Is the level2 interrupt supported for ARM cortex-M0P core?