Searched refs:leading_clocks (Results 1 – 3 of 3) sorted by relevance
| /Zephyr-latest/drivers/fpga/ |
| D | fpga_ice40_common.h | 37 BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) >= FPGA_ICE40_LEADING_CLOCKS_MIN); \
38 BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) <= UINT8_MAX); \
51 .leading_clocks = DT_INST_PROP(inst, leading_clocks), \
71 uint8_t leading_clocks; member
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| D | fpga_ice40_spi.c | 103 LOG_DBG("Send %u clocks", config->leading_clocks); in fpga_ice40_load()
105 tx_buf.len = DIV_ROUND_UP(config->leading_clocks, BITS_PER_BYTE); in fpga_ice40_load()
108 LOG_ERR("Failed to send leading %u clocks: %d", config->leading_clocks, ret); in fpga_ice40_load()
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| D | fpga_ice40_bitbang.c | 195 LOG_DBG("Send %u clocks", config->leading_clocks); in fpga_ice40_load()
197 config_bitbang->clear, clk, config->leading_clocks); in fpga_ice40_load()
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