1 /*
2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief ARM Cortex-M interrupt management
10 *
11 *
12 * Interrupt management: enabling/disabling and dynamic ISR
13 * connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for
14 * connecting ISRs at runtime.
15 */
16
17 #include <zephyr/kernel.h>
18 #include <zephyr/arch/cpu.h>
19 #include <cmsis_core.h>
20 #include <zephyr/sys/__assert.h>
21 #include <zephyr/sys/barrier.h>
22 #include <zephyr/toolchain.h>
23 #include <zephyr/linker/sections.h>
24 #include <zephyr/sw_isr_table.h>
25 #include <zephyr/irq.h>
26 #include <zephyr/tracing/tracing.h>
27 #include <zephyr/pm/pm.h>
28
29 extern void z_arm_reserved(void);
30
31 #define NUM_IRQS_PER_REG 32
32 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
33 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
34
35 /*
36 * For Cortex-M core, the default interrupt controller is the ARM
37 * NVIC and therefore the architecture interrupt control functions
38 * are mapped to the NVIC driver interface.
39 *
40 * When NVIC is used together with other interrupt controller for
41 * multi-level interrupts support (i.e. CONFIG_MULTI_LEVEL_INTERRUPTS
42 * is enabled), the architecture interrupt control functions are mapped
43 * to the SoC layer in `include/arch/arm/irq.h`.
44 * The exported arm interrupt control functions which are wrappers of
45 * NVIC control could be used for SoC to do level 1 irq control to implement SoC
46 * layer interrupt control functions.
47 *
48 * When a custom interrupt controller is used (i.e.
49 * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture
50 * interrupt control functions are mapped to the SoC layer in
51 * `include/arch/arm/irq.h`.
52 */
53
54 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
55
arm_irq_enable(unsigned int irq)56 void arm_irq_enable(unsigned int irq)
57 {
58 NVIC_EnableIRQ((IRQn_Type)irq);
59 }
60
arm_irq_disable(unsigned int irq)61 void arm_irq_disable(unsigned int irq)
62 {
63 NVIC_DisableIRQ((IRQn_Type)irq);
64 }
65
arm_irq_is_enabled(unsigned int irq)66 int arm_irq_is_enabled(unsigned int irq)
67 {
68 return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
69 }
70
71 /**
72 * @internal
73 *
74 * @brief Set an interrupt's priority
75 *
76 * The priority is verified if ASSERT_ON is enabled. The maximum number
77 * of priority levels is a little complex, as there are some hardware
78 * priority levels which are reserved.
79 */
arm_irq_priority_set(unsigned int irq,unsigned int prio,uint32_t flags)80 void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
81 {
82 /* The kernel may reserve some of the highest priority levels.
83 * So we offset the requested priority level with the number
84 * of priority levels reserved by the kernel.
85 */
86
87 /* If we have zero latency interrupts, those interrupts will
88 * run at a priority level which is not masked by irq_lock().
89 * Our policy is to express priority levels with special properties
90 * via flags
91 */
92 if (IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) && (flags & IRQ_ZERO_LATENCY)) {
93 if (ZERO_LATENCY_LEVELS == 1) {
94 prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
95 } else {
96 /* Use caller supplied prio level as-is */
97 }
98 } else {
99 prio += _IRQ_PRIO_OFFSET;
100 }
101
102 /* The last priority level is also used by PendSV exception, but
103 * allow other interrupts to use the same level, even if it ends up
104 * affecting performance (can still be useful on systems with a
105 * reduced set of priorities, like Cortex-M0/M0+).
106 */
107 __ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
108 "invalid priority %d for %d irq! values must be less than %lu\n",
109 prio - _IRQ_PRIO_OFFSET, irq, BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
110 NVIC_SetPriority((IRQn_Type)irq, prio);
111 }
112
113 #endif /* !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) */
114
115 void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf);
116
117 /**
118 *
119 * @brief Spurious interrupt handler
120 *
121 * Installed in all _sw_isr_table slots at boot time. Throws an error if
122 * called.
123 *
124 */
z_irq_spurious(const void * unused)125 void z_irq_spurious(const void *unused)
126 {
127 ARG_UNUSED(unused);
128
129 z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
130 }
131
132 #ifdef CONFIG_PM
_arch_isr_direct_pm(void)133 void _arch_isr_direct_pm(void)
134 {
135 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
136 unsigned int key;
137
138 /* irq_lock() does what we want for this CPU */
139 key = irq_lock();
140 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
141 /* Lock all interrupts. irq_lock() will on this CPU only disable those
142 * lower than BASEPRI, which is not what we want. See comments in
143 * arch/arm/core/cortex_m/isr_wrapper.c
144 */
145 __asm__ volatile("cpsid i" : : : "memory");
146 #else
147 #error Unknown ARM architecture
148 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
149
150 if (_kernel.idle) {
151 _kernel.idle = 0;
152 pm_system_resume();
153 }
154
155 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
156 irq_unlock(key);
157 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
158 __asm__ volatile("cpsie i" : : : "memory");
159 #else
160 #error Unknown ARM architecture
161 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
162 }
163 #endif
164
165 #if defined(CONFIG_ARM_SECURE_FIRMWARE)
166 /**
167 *
168 * @brief Set the target security state for the given IRQ
169 *
170 * Function sets the security state (Secure or Non-Secure) targeted
171 * by the given irq. It requires ARMv8-M MCU.
172 * It is only compiled if ARM_SECURE_FIRMWARE is defined.
173 * It should only be called while in Secure state, otherwise, a write attempt
174 * to NVIC.ITNS register is write-ignored(WI), as the ITNS register is not
175 * banked between security states and, therefore, has no Non-Secure instance.
176 *
177 * It shall return the resulting target state of the given IRQ, indicating
178 * whether the operation has been performed successfully.
179 *
180 * @param irq IRQ line
181 * @param irq_target_state the desired IRQ target state
182 *
183 * @return The resulting target state of the given IRQ
184 */
irq_target_state_set(unsigned int irq,irq_target_state_t irq_target_state)185 irq_target_state_t irq_target_state_set(unsigned int irq, irq_target_state_t irq_target_state)
186 {
187 uint32_t result;
188
189 if (irq_target_state == IRQ_TARGET_STATE_SECURE) {
190 /* Set target to Secure */
191 result = NVIC_ClearTargetState(irq);
192 } else {
193 /* Set target to Non-Secure */
194 result = NVIC_SetTargetState(irq);
195 }
196
197 if (result) {
198 return IRQ_TARGET_STATE_NON_SECURE;
199 } else {
200 return IRQ_TARGET_STATE_SECURE;
201 }
202 }
203
204 /**
205 *
206 * @brief Determine whether the given IRQ targets the Secure state
207 *
208 * Function determines whether the given irq targets the Secure state
209 * or not (i.e. targets the Non-Secure state). It requires ARMv8-M MCU.
210 * It is only compiled if ARM_SECURE_FIRMWARE is defined.
211 * It should only be called while in Secure state, otherwise, a read attempt
212 * to NVIC.ITNS register is read-as-zero(RAZ), as the ITNS register is not
213 * banked between security states and, therefore, has no Non-Secure instance.
214 *
215 * @param irq IRQ line
216 *
217 * @return 1 if target state is Secure, 0 otherwise.
218 */
irq_target_state_is_secure(unsigned int irq)219 int irq_target_state_is_secure(unsigned int irq)
220 {
221 return NVIC_GetTargetState(irq) == 0;
222 }
223
224 /**
225 *
226 * @brief Disable and set all interrupt lines to target Non-Secure state.
227 *
228 * The function is used to set all HW NVIC interrupt lines to target the
229 * Non-Secure state. The function shall only be called fron Secure state.
230 *
231 * Notes:
232 * - All NVIC interrupts are disabled before being routed to Non-Secure.
233 * - Bits corresponding to un-implemented interrupts are RES0, so writes
234 * will be ignored.
235 *
236 */
irq_target_state_set_all_non_secure(void)237 void irq_target_state_set_all_non_secure(void)
238 {
239 int i;
240
241 /* Disable (Clear) all NVIC interrupt lines. */
242 for (i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) {
243 NVIC->ICER[i] = 0xFFFFFFFF;
244 }
245
246 barrier_dsync_fence_full();
247 barrier_isync_fence_full();
248
249 /* Set all NVIC interrupt lines to target Non-Secure */
250 for (i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) {
251 NVIC->ITNS[i] = 0xFFFFFFFF;
252 }
253 }
254
255 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
256
257 #ifdef CONFIG_DYNAMIC_INTERRUPTS
258 #ifdef CONFIG_GEN_ISR_TABLES
arch_irq_connect_dynamic(unsigned int irq,unsigned int priority,void (* routine)(const void * parameter),const void * parameter,uint32_t flags)259 int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
260 void (*routine)(const void *parameter), const void *parameter,
261 uint32_t flags)
262 {
263 z_isr_install(irq, routine, parameter);
264 z_arm_irq_priority_set(irq, priority, flags);
265 return irq;
266 }
267 #endif /* CONFIG_GEN_ISR_TABLES */
268
269 #ifdef CONFIG_DYNAMIC_DIRECT_INTERRUPTS
z_arm_irq_dynamic_direct_isr_dispatch(void)270 static inline void z_arm_irq_dynamic_direct_isr_dispatch(void)
271 {
272 uint32_t irq = __get_IPSR() - 16;
273
274 if (irq < IRQ_TABLE_SIZE) {
275 struct _isr_table_entry *isr_entry = &_sw_isr_table[irq];
276
277 isr_entry->isr(isr_entry->arg);
278 }
279 }
280
ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_reschedule)281 ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_reschedule)
282 {
283 z_arm_irq_dynamic_direct_isr_dispatch();
284
285 return 1;
286 }
287
ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_no_reschedule)288 ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_no_reschedule)
289 {
290 z_arm_irq_dynamic_direct_isr_dispatch();
291
292 return 0;
293 }
294
295 #endif /* CONFIG_DYNAMIC_DIRECT_INTERRUPTS */
296
297 #endif /* CONFIG_DYNAMIC_INTERRUPTS */
298
