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Searched refs:int_mask (Results 1 – 20 of 20) sorted by relevance

/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps.c90 uint32_t int_mask; in gpio_xlnx_ps_isr() local
94 int_mask = 0; in gpio_xlnx_ps_isr()
97 int_mask = api->get_pending_int(dev_conf->bank_devices[bank]); in gpio_xlnx_ps_isr()
99 if (int_mask) { in gpio_xlnx_ps_isr()
103 dev_conf->bank_devices[bank], int_mask); in gpio_xlnx_ps_isr()
Dgpio_pca_series.c1228 uint32_t int_mask, input_latch; in gpio_pca_series_pin_interrupt_configure_standard() local
1290 int_mask = int_fall | int_rise; in gpio_pca_series_pin_interrupt_configure_standard()
1291 input_latch = ~int_mask; in gpio_pca_series_pin_interrupt_configure_standard()
1324 int_mask = sys_cpu_to_le32(int_mask); in gpio_pca_series_pin_interrupt_configure_standard()
1326 (uint8_t *)&int_mask); in gpio_pca_series_pin_interrupt_configure_standard()
1359 uint32_t int_mask, input_latch; in gpio_pca_series_pin_interrupt_configure_extended() local
1414 (uint8_t *)&int_mask); in gpio_pca_series_pin_interrupt_configure_extended()
1418 int_mask = sys_le32_to_cpu(int_mask); in gpio_pca_series_pin_interrupt_configure_extended()
1421 int_mask |= BIT(pin); /** set 1 to disable interrupt */ in gpio_pca_series_pin_interrupt_configure_extended()
1433 int_mask &= ~BIT(pin); /** set 0 to enable interrupt */ in gpio_pca_series_pin_interrupt_configure_extended()
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Dgpio_pca95xx.c91 uint16_t int_mask; member
344 &drv_data->reg_cache.int_mask, value); in update_int_mask_reg()
706 reg_out = drv_data->reg_cache.int_mask; in gpio_pca95xx_pin_interrupt_configure()
887 .reg_cache.int_mask = 0xFFFF, \
/Zephyr-latest/drivers/sensor/adi/adxl362/
Dadxl362_trigger.c99 uint8_t int_mask, int_en, status_buf; in adxl362_trigger_set() local
111 int_mask = ADXL362_INTMAP1_ACT; in adxl362_trigger_set()
120 int_mask = ADXL362_INTMAP1_INACT; in adxl362_trigger_set()
129 int_mask = ADXL362_INTMAP1_DATA_READY; in adxl362_trigger_set()
138 int_en = int_mask; in adxl362_trigger_set()
143 return adxl362_reg_write_mask(dev, ADXL362_REG_INTMAP1, int_mask, int_en); in adxl362_trigger_set()
Dadxl362_stream.c56 uint8_t int_mask = 0; in adxl362_submit_stream() local
69 int_mask |= ADXL362_INTMAP1_FIFO_WATERMARK; in adxl362_submit_stream()
75 int_mask |= ADXL362_INTMAP1_FIFO_OVERRUN; in adxl362_submit_stream()
82 int_mask |= ADXL362_INTMAP1_FIFO_WATERMARK; in adxl362_submit_stream()
86 int_mask |= ADXL362_INTMAP1_FIFO_OVERRUN; in adxl362_submit_stream()
94 rc = adxl362_reg_write_mask(dev, ADXL362_REG_INTMAP1, int_mask, int_value); in adxl362_submit_stream()
/Zephyr-latest/drivers/sensor/ti/fdc2x1x/
Dfdc2x1x_trigger.c92 uint16_t status, int_mask, int_en; in fdc2x1x_trigger_set() local
104 int_mask = FDC2X1X_ERROR_CONFIG_DRDY_2INT_MSK; in fdc2x1x_trigger_set()
113 int_en = int_mask; in fdc2x1x_trigger_set()
114 drv_data->int_config |= int_mask; in fdc2x1x_trigger_set()
120 FDC2X1X_ERROR_CONFIG, int_mask, int_en); in fdc2x1x_trigger_set()
/Zephyr-latest/drivers/sensor/adi/adxl367/
Dadxl367_trigger.c94 uint8_t int_mask, int_en, status; in adxl367_trigger_set() local
107 int_mask = ADXL367_ACT_INT | ADXL367_INACT_INT; in adxl367_trigger_set()
112 int_mask = ADXL367_DATA_RDY; in adxl367_trigger_set()
120 int_en = int_mask; in adxl367_trigger_set()
125 ret = drv_data->hw_tf->write_reg_mask(dev, ADXL367_INTMAP1_LOWER, int_mask, int_en); in adxl367_trigger_set()
Dadxl367_stream.c80 uint8_t int_mask = 0; in adxl367_submit_stream() local
93 int_mask |= ADXL367_FIFO_WATERMARK; in adxl367_submit_stream()
99 int_mask |= ADXL367_FIFO_OVERRUN; in adxl367_submit_stream()
106 int_mask |= ADXL367_FIFO_WATERMARK; in adxl367_submit_stream()
110 int_mask |= ADXL367_FIFO_OVERRUN; in adxl367_submit_stream()
118 rc = data->hw_tf->write_reg_mask(dev, ADXL367_INTMAP1_LOWER, int_mask, int_value); in adxl367_submit_stream()
/Zephyr-latest/drivers/sensor/adi/adxl372/
Dadxl372_trigger.c108 uint8_t int_mask, int_en, status1, status2; in adxl372_trigger_set() local
121 int_mask = ADXL372_INT1_MAP_ACT_MSK | in adxl372_trigger_set()
127 int_mask = ADXL372_INT1_MAP_DATA_RDY_MSK; in adxl372_trigger_set()
135 int_en = int_mask; in adxl372_trigger_set()
140 ret = drv_data->hw_tf->write_reg_mask(dev, ADXL372_INT1_MAP, int_mask, int_en); in adxl372_trigger_set()
/Zephyr-latest/drivers/sensor/adi/adxl345/
Dadxl345_trigger.c93 uint8_t int_mask, int_en, status1; in adxl345_trigger_set() local
106 int_mask = ADXL345_INT_MAP_DATA_RDY_MSK; in adxl345_trigger_set()
114 int_en = int_mask; in adxl345_trigger_set()
119 ret = adxl345_reg_write_mask(dev, ADXL345_INT_MAP, int_mask, int_en); in adxl345_trigger_set()
/Zephyr-latest/drivers/sensor/memsic/mc3419/
Dmc3419_trigger.c105 uint8_t int_mask = MC3419_ANY_MOTION_MASK; in mc3419_configure_trigger() local
112 int_mask, handler ? int_mask : 0); in mc3419_configure_trigger()
/Zephyr-latest/drivers/i2c/
Di2c_xilinx_axi.c265 struct i2c_xilinx_axi_data *data, uint32_t int_mask) in i2c_xilinx_axi_wait_interrupt() argument
268 const uint32_t int_enable = sys_read32(config->base + REG_IER) | int_mask; in i2c_xilinx_axi_wait_interrupt()
273 k_event_clear(&data->irq_event, int_mask); in i2c_xilinx_axi_wait_interrupt()
276 events = k_event_wait(&data->irq_event, int_mask, false, K_MSEC(100)); in i2c_xilinx_axi_wait_interrupt()
280 LOG_ERR("Timeout waiting for ISR events 0x%02x, SR 0x%02x, ISR 0x%02x", int_mask, in i2c_xilinx_axi_wait_interrupt()
287 struct i2c_xilinx_axi_data *data, uint32_t int_mask) in i2c_xilinx_axi_clear_interrupt() argument
292 if (int_status & int_mask) { in i2c_xilinx_axi_clear_interrupt()
293 sys_write32(int_status & int_mask, config->base + REG_ISR); in i2c_xilinx_axi_clear_interrupt()
/Zephyr-latest/drivers/counter/
Dcounter_nrfx_timer.c236 uint32_t int_mask = nrf_timer_compare_int_get(ID_TO_CC(chan_id)); in cancel_alarm() local
238 nrf_timer_int_disable(config->timer, int_mask); in cancel_alarm()
356 uint32_t int_mask = nrf_timer_compare_int_get(cc); in alarm_irq_handle() local
359 nrf_timer_int_enable_check(reg, int_mask); in alarm_irq_handle()
368 nrf_timer_int_disable(reg, int_mask); in alarm_irq_handle()
Dcounter_nrfx_rtc.c240 uint32_t int_mask = NRF_RTC_CHANNEL_INT_MASK(chan); in set_cc() local
246 __ASSERT(nrf_rtc_int_enable_check(rtc, int_mask) == 0, in set_cc()
262 nrfy_rtc_event_enable(rtc, int_mask); in set_cc()
328 nrfy_rtc_int_enable(rtc, int_mask); in set_cc()
637 uint32_t int_mask = NRF_RTC_CHANNEL_INT_MASK(chan); in alarm_irq_handle() local
648 nrfy_rtc_int_disable(rtc, int_mask); in alarm_irq_handle()
/Zephyr-latest/drivers/virtualization/
Dvirt_ivshmem.h68 uint32_t int_mask; member
/Zephyr-latest/drivers/timer/
Dnrf_grtc_timer.c62 static atomic_t int_mask; variable
125 atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan)); in compare_int_lock()
135 atomic_or(&int_mask, BIT(chan)); in compare_int_unlock()
492 int_mask = NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK; in sys_clock_driver_init()
Dnrf_rtc_timer.c64 static atomic_t int_mask; variable
155 atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan)); in compare_int_lock()
176 atomic_or(&int_mask, BIT(chan)); in compare_int_unlock()
756 int_mask = BIT_MASK(CHAN_COUNT); in sys_clock_driver_init()
/Zephyr-latest/drivers/pwm/
Dpwm_numaker.c359 uint32_t int_mask = (BIT(st_channel) | BIT(end_channel)); in pwm_numaker_isr() local
366 int_status = epwm->AINTSTS & int_mask; in pwm_numaker_isr()
/Zephyr-latest/drivers/usb/common/nrf_usbd_common/
Dnrf_usbd_common.c1247 uint32_t int_mask = USBD_INTEN_USBRESET_Msk | USBD_INTEN_ENDEPIN0_Msk | in nrf_usbd_common_start() local
1261 int_mask |= USBD_INTEN_SOF_Msk; in nrf_usbd_common_start()
1265 NRF_USBD->INTEN = int_mask; in nrf_usbd_common_start()
/Zephyr-latest/drivers/serial/
Duart_nrfx_uarte.c1720 uint32_t int_mask, uint32_t int_en_mask) in event_check_clear() argument
1722 if (nrf_uarte_event_check(uarte, event) && (int_mask & int_en_mask)) { in event_check_clear()