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Searched refs:gpio (Results 1 – 25 of 1938) sorted by relevance

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/Zephyr-latest/soc/atmel/sam/common/
Dsoc_sam4l_gpio.c14 static void configure_common_attr(volatile Gpio *gpio, in configure_common_attr() argument
20 gpio->IERC = mask; in configure_common_attr()
24 gpio->PUERS = mask; in configure_common_attr()
26 gpio->PUERC = mask; in configure_common_attr()
31 gpio->PDERS = mask; in configure_common_attr()
33 gpio->PDERC = mask; in configure_common_attr()
38 gpio->ODMERS = mask; in configure_common_attr()
40 gpio->ODMERC = mask; in configure_common_attr()
44 static void configure_input_attr(volatile Gpio *gpio, in configure_input_attr() argument
52 gpio->GFERC = mask; in configure_input_attr()
[all …]
/Zephyr-latest/tests/drivers/gpio/gpio_reserved_ranges/boards/
Dnative_posix.overlay9 compatible = "test-gpio-reserved-ranges";
14 test_gpio_1: gpio@deadbeef {
15 compatible = "vnd,gpio-device";
16 gpio-controller;
18 #gpio-cells = < 0x2 >;
21 gpio-reserved-ranges = <0 4>, <5 3>, <9 5>, <11 2>,
26 test_gpio_2: gpio@abcd1234 {
27 compatible = "vnd,gpio-device";
28 gpio-controller;
30 #gpio-cells = < 0x2 >;
[all …]
/Zephyr-latest/boards/m5stack/m5stack_cores3/
Dm5stack_mbus_connectors.dtsi9 #gpio-cells = <2>;
10 gpio-map-mask = <0xffffffff 0xffffffc0>;
11 gpio-map-pass-thru = <0 0x3f>;
12 gpio-map = /* GND */ <1 0 &gpio 10 0>, /* ADC */
13 /* GND */ <3 0 &gpio 8 0>, /* PB_IN */
15 /* MOSI */ <6 0 &gpio 37 0>, <7 0 &gpio 5 0>, /* GPIO */
16 /* MISO */ <8 0 &gpio 35 0>, <9 0 &gpio 9 0>, /* PB_OUT */
17 /* SCK */ <10 0 &gpio 36 0>, /* 3.3V */
18 /* RXD0 */ <12 0 &gpio 44 0>, <13 0 &gpio 43 0>, /* TXD0 */
19 /* PC_RX */ <14 0 &gpio 18 0>, <15 0 &gpio 17 0>, /* PC_TX */
[all …]
/Zephyr-latest/dts/x86/intel/
Dgpio_common.dtsi9 #include <zephyr/dt-bindings/gpio/gpio.h>
14 compatible = "intel,gpio";
17 gpio-controller;
18 #gpio-cells = <2>;
23 compatible = "intel,gpio";
26 gpio-controller;
27 #gpio-cells = <2>;
32 compatible = "intel,gpio";
35 gpio-controller;
36 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/renesas/rz/rzg/
Dr9a08g045.dtsi40 gpio: gpio-common { label
41 compatible = "renesas,rz-gpio-int";
55 gpio0: gpio@0 {
56 compatible = "renesas,rz-gpio";
57 gpio-controller;
58 #gpio-cells = <2>;
64 gpio1: gpio@1000 {
65 compatible = "renesas,rz-gpio";
66 gpio-controller;
67 #gpio-cells= <2>;
[all …]
/Zephyr-latest/tests/drivers/build_all/gpio/
Dapp.overlay18 test_gpio: gpio@deadbeef {
19 compatible = "vnd,gpio";
20 gpio-controller;
22 #gpio-cells = <0x2>;
26 test_gpio_dw: gpio@c0ffee {
27 compatible = "snps,designware-gpio";
28 gpio-controller;
30 #gpio-cells = <0x2>;
45 #gpio-cells = <2>;
47 gpio-controller;
[all …]
/Zephyr-latest/drivers/gpio/
DKconfig14 module-str = gpio
29 This command provides a shell user extra information about gpio
97 source "drivers/gpio/Kconfig.ad559x"
98 source "drivers/gpio/Kconfig.adp5585"
99 source "drivers/gpio/Kconfig.ads114s0x"
100 source "drivers/gpio/Kconfig.altera"
101 source "drivers/gpio/Kconfig.ambiq"
102 source "drivers/gpio/Kconfig.andes_atcgpio100"
103 source "drivers/gpio/Kconfig.aw9523b"
104 source "drivers/gpio/Kconfig.axp192"
[all …]
Dgpio_sam4l.c45 Gpio * const gpio = cfg->regs; in gpio_sam_port_configure() local
53 gpio->IERC = mask; in gpio_sam_port_configure()
54 gpio->PUERC = mask; in gpio_sam_port_configure()
55 gpio->PDERC = mask; in gpio_sam_port_configure()
56 gpio->GPERS = mask; in gpio_sam_port_configure()
57 gpio->ODERC = mask; in gpio_sam_port_configure()
58 gpio->STERC = mask; in gpio_sam_port_configure()
67 gpio->STERS = mask; in gpio_sam_port_configure()
71 gpio->OVRS = mask; in gpio_sam_port_configure()
74 gpio->OVRC = mask; in gpio_sam_port_configure()
[all …]
Dgpio_mchp_mss.c74 volatile struct mss_gpio_t *gpio = DEV_GPIO(dev); in mss_gpio_config() local
84 gpio->gpio_cfg[pin] |= MSS_GPIO_OUTPUT_MODE; in mss_gpio_config()
87 gpio->gpio_out |= BIT(pin); in mss_gpio_config()
90 gpio->gpio_out &= ~BIT(pin); in mss_gpio_config()
95 gpio->gpio_cfg[pin] |= MSS_GPIO_INPUT_MODE; in mss_gpio_config()
107 volatile struct mss_gpio_t *gpio = DEV_GPIO(dev); in mss_gpio_port_toggle_bits() local
109 gpio->gpio_out ^= mask; in mss_gpio_port_toggle_bits()
117 volatile struct mss_gpio_t *gpio = DEV_GPIO(dev); in mss_gpio_port_get_raw() local
119 *value = gpio->gpio_in; in mss_gpio_port_get_raw()
128 volatile struct mss_gpio_t *gpio = DEV_GPIO(dev); in mss_gpio_port_set_masked_raw() local
[all …]
Dgpio_sifive.c104 volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev); in gpio_sifive_irq_handler() local
124 gpio->rise_ip = BIT(pin); in gpio_sifive_irq_handler()
125 gpio->fall_ip = BIT(pin); in gpio_sifive_irq_handler()
126 gpio->high_ip = BIT(pin); in gpio_sifive_irq_handler()
127 gpio->low_ip = BIT(pin); in gpio_sifive_irq_handler()
146 volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev); in gpio_sifive_config() local
159 WRITE_BIT(gpio->pue, pin, flags & GPIO_PULL_UP); in gpio_sifive_config()
165 gpio->out_val |= BIT(pin); in gpio_sifive_config()
168 gpio->out_val &= ~BIT(pin); in gpio_sifive_config()
172 WRITE_BIT(gpio->out_en, pin, flags & GPIO_OUTPUT); in gpio_sifive_config()
[all …]
Dgpio_b91.c30 #define GET_PORT_NUM(gpio) ((uint8_t)(((uint32_t)gpio - DT_REG_ADDR(DT_NODELABEL(gpioa))) / \ argument
34 #define IS_PORT_C(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpioc))) argument
37 #define IS_PORT_D(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpiod))) argument
99 volatile struct gpio_b91_t *gpio = GET_GPIO(dev); in gpiob_b91_irq_en_set() local
102 BM_SET(gpio->irq_en, BIT(pin)); in gpiob_b91_irq_en_set()
104 BM_SET(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin)); in gpiob_b91_irq_en_set()
106 BM_SET(reg_irq_risc1_en(GET_PORT_NUM(gpio)), BIT(pin)); in gpiob_b91_irq_en_set()
116 volatile struct gpio_b91_t *gpio = GET_GPIO(dev); in gpiob_b91_irq_en_clr() local
119 BM_CLR(gpio->irq_en, BIT(pin)); in gpiob_b91_irq_en_clr()
121 BM_CLR(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin)); in gpiob_b91_irq_en_clr()
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_04/
Dpsoc6_04.dtsi66 gpio_prt0: gpio@40310000 {
67 compatible = "infineon,cat1-gpio";
70 gpio-controller;
73 #gpio-cells = <2>;
75 gpio_prt1: gpio@40310080 {
76 compatible = "infineon,cat1-gpio";
78 gpio-controller;
81 #gpio-cells = <2>;
83 gpio_prt2: gpio@40310100 {
84 compatible = "infineon,cat1-gpio";
[all …]
/Zephyr-latest/dts/arm/nuvoton/
Dm48x.dtsi9 #include <zephyr/dt-bindings/gpio/gpio.h>
48 gpioa: gpio@40004000 {
49 compatible = "nuvoton,numicro-gpio";
53 gpio-controller;
54 #gpio-cells = <2>;
58 gpiob: gpio@40004040 {
59 compatible = "nuvoton,numicro-gpio";
63 gpio-controller;
64 #gpio-cells = <2>;
68 gpioc: gpio@40004080 {
[all …]
/Zephyr-latest/dts/arm/ti/
Dlm3s6965.dtsi74 gpio0: gpio@40004000 {
75 compatible = "ti,stellaris-gpio";
78 gpio-controller;
79 #gpio-cells = <2>;
83 gpio1: gpio@40005000 {
84 compatible = "ti,stellaris-gpio";
87 gpio-controller;
88 #gpio-cells = <2>;
92 gpio2: gpio@40006000 {
93 compatible = "ti,stellaris-gpio";
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_03/
Dpsoc6_03.dtsi66 gpio_prt0: gpio@40310000 {
67 compatible = "infineon,cat1-gpio";
70 gpio-controller;
73 #gpio-cells = <2>;
75 gpio_prt2: gpio@40310100 {
76 compatible = "infineon,cat1-gpio";
79 gpio-controller;
82 #gpio-cells = <2>;
84 gpio_prt3: gpio@40310180 {
85 compatible = "infineon,cat1-gpio";
[all …]
/Zephyr-latest/boards/snps/hsdk/doc/
Dindex.rst28 | 2:0 | GPIO_SEL_0 | RW | 0x0* | GPIO mux select for gpio[3:0] |
30 | 5:3 | GPIO_SEL_1 | RW | 0x0* | GPIO mux select for gpio[7:4] |
32 | 8:6 | GPIO_SEL_2 | RW | 0x0* | GPIO mux select for gpio[11:8] |
34 | 11:9 | GPIO_SEL_3 | RW | 0x0* | GPIO mux select for gpio[15:12] |
36 | 14:12 | GPIO_SEL_4 | RW | 0x0* | GPIO mux select for gpio[17:16] |
38 | 17:15 | GPIO_SEL_5 | RW | 0x0* | GPIO mux select for gpio[19:18] |
40 | 20:18 | GPIO_SEL_6 | RW | 0x0* | GPIO mux select for gpio[21:20] |
42 | 23:21 | GPIO_SEL_7 | RW | 0x0* | GPIO mux select for gpio[23:22] |
48 | SEL0 | 0 | gpio[0] | uart0_cts | spi1_cs[0] | gpio[0] | gpio[0] | pwm_ch[6] | pwm_c…
50 | | 1 | gpio[1] | uart0_txd | spi1_mosi | gpio[1] | pwm_ch[0] | gpio[1] | pwm_c…
[all …]
/Zephyr-latest/boards/snps/hsdk4xd/doc/
Dindex.rst25 | 2:0 | GPIO_SEL_0 | RW | 0x0 | GPIO mux select for gpio[3:0] |
27 | 5:3 | GPIO_SEL_1 | RW | 0x0 | GPIO mux select for gpio[7:4] |
29 | 8:6 | GPIO_SEL_2 | RW | 0x0 | GPIO mux select for gpio[11:8] |
31 | 11:9 | GPIO_SEL_3 | RW | 0x0 | GPIO mux select for gpio[15:12] |
33 | 14:12 | GPIO_SEL_4 | RW | 0x0 | GPIO mux select for gpio[17:16] |
35 | 17:15 | GPIO_SEL_5 | RW | 0x0 | GPIO mux select for gpio[19:18] |
37 | 20:18 | GPIO_SEL_6 | RW | 0x0 | GPIO mux select for gpio[21:20] |
39 | 23:21 | GPIO_SEL_7 | RW | 0x0 | GPIO mux select for gpio[23:22] |
45 | SEL0 | 0 | gpio[0] | uart0_cts | spi1_cs[0] | gpio[0] | gpio[0] | pwm_ch[6] | pwm_c…
47 | | 1 | gpio[1] | uart0_txd | spi1_mosi | gpio[1] | pwm_ch[0] | gpio[1] | pwm_c…
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/legacy/
Dpsoc6.dtsi9 #include <zephyr/dt-bindings/gpio/gpio.h>
83 gpio_prt0: gpio@40320000 {
84 compatible = "cypress,psoc6-gpio";
87 gpio-controller;
89 #gpio-cells = <2>;
93 gpio_prt1: gpio@40320080 {
94 compatible = "cypress,psoc6-gpio";
97 gpio-controller;
99 #gpio-cells = <2>;
103 gpio_prt2: gpio@40320100 {
[all …]
/Zephyr-latest/dts/arm/renesas/ra/
Dra4-cm4-common.dtsi11 ioport6: gpio@400400c0 {
12 compatible = "renesas,ra-gpio";
14 gpio-controller;
15 #gpio-cells = <2>;
20 ioport7: gpio@400400e0 {
21 compatible = "renesas,ra-gpio";
23 gpio-controller;
24 #gpio-cells = <2>;
29 ioport8: gpio@40040100 {
30 compatible = "renesas,ra-gpio";
[all …]
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4700_F144x2048.dtsi54 gpio-reserved-ranges = <10 2>;
59 gpio-reserved-ranges = <0 2>, <10 2>;
63 gpio3: gpio@48028300 {
64 compatible = "infineon,xmc4xxx-gpio";
65 gpio-controller;
66 #gpio-cells = <2>;
72 gpio4: gpio@48028400 {
73 compatible = "infineon,xmc4xxx-gpio";
74 gpio-controller;
75 #gpio-cells = <2>;
[all …]
Dxmc4500_F100x1024.dtsi60 gpio-reserved-ranges = <10 2>;
65 gpio-reserved-ranges = <0 2>, <10 2>;
69 gpio3: gpio@48028300 {
70 compatible = "infineon,xmc4xxx-gpio";
71 gpio-controller;
72 #gpio-cells = <2>;
78 gpio4: gpio@48028400 {
79 compatible = "infineon,xmc4xxx-gpio";
80 gpio-controller;
81 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/silabs/
Defm32hg.dtsi4 #include <zephyr/dt-bindings/gpio/gpio.h>
79 gpio@40006100 {
80 compatible = "silabs,gecko-gpio";
89 gpioa: gpio@40006000 {
90 compatible = "silabs,gecko-gpio-port";
93 gpio-controller;
94 #gpio-cells = <2>;
98 gpiob: gpio@40006024 {
99 compatible = "silabs,gecko-gpio-port";
102 gpio-controller;
[all …]
Defm32_jg_pg_12b.dtsi11 #include <zephyr/dt-bindings/gpio/gpio.h>
121 gpio: gpio@4000a400 { label
122 compatible = "silabs,gecko-gpio";
131 gpioa: gpio@4000a000 {
132 compatible = "silabs,gecko-gpio-port";
135 gpio-controller;
136 #gpio-cells = <2>;
140 gpiob: gpio@4000a030 {
141 compatible = "silabs,gecko-gpio-port";
144 gpio-controller;
[all …]
/Zephyr-latest/tests/drivers/stepper/drv8424/emul/boards/
Dnative_sim.overlay6 #include <zephyr/dt-bindings/gpio/gpio.h>
28 compatible = "zephyr,gpio-emul";
29 #gpio-cells = <0x2>;
31 gpio-controller;
35 compatible = "zephyr,gpio-emul";
36 #gpio-cells = <0x2>;
38 gpio-controller;
42 compatible = "zephyr,gpio-emul";
43 #gpio-cells = <0x2>;
45 gpio-controller;
/Zephyr-latest/tests/drivers/stepper/drv8424/api/boards/
Dnative_sim.overlay6 #include <zephyr/dt-bindings/gpio/gpio.h>
28 compatible = "zephyr,gpio-emul";
29 #gpio-cells = <0x2>;
31 gpio-controller;
35 compatible = "zephyr,gpio-emul";
36 #gpio-cells = <0x2>;
38 gpio-controller;
42 compatible = "zephyr,gpio-emul";
43 #gpio-cells = <0x2>;
45 gpio-controller;

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