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Searched refs:dma_channels (Results 1 – 25 of 48) sorted by relevance

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/Zephyr-latest/drivers/dma/
Ddma_intel_adsp_hda.c39 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_in_config()
73 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_out_config()
107 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_link_in_config()
137 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_link_out_config()
164 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_link_reload()
176 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_reload()
226 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_status()
301 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_start()
346 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_stop()
366 for (uint32_t i = 0; i < cfg->dma_channels; i++) { in intel_adsp_hda_channels_init()
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Ddma_intel_adsp_hda_link_in.c31 .dma_channels = DT_INST_PROP(inst, dma_channels), \
Ddma_intel_adsp_hda_link_out.c31 .dma_channels = DT_INST_PROP(inst, dma_channels), \
Ddma_mchp_xec.c113 uint8_t dma_channels; member
344 if (!config || (channel >= (uint32_t)devcfg->dma_channels)) { in dma_xec_configure()
459 if (channel >= (uint32_t)devcfg->dma_channels) { in dma_xec_reload()
502 if (channel >= (uint32_t)devcfg->dma_channels) { in dma_xec_start()
535 if (channel >= (uint32_t)devcfg->dma_channels) { in dma_xec_stop()
587 if ((channel >= (uint32_t)devcfg->dma_channels) || (!status)) { in dma_xec_get_status()
637 if (!filter_param && devcfg->dma_channels) { in dma_xec_chan_filter()
638 filter = GENMASK(devcfg->dma_channels-1u, 0); in dma_xec_chan_filter()
806 BUILD_ASSERT(DT_INST_PROP(i, dma_channels) <= 16, "XEC DMA dma-channels > 16"); \
810 dma_xec_ctrl##i##_chans[DT_INST_PROP(i, dma_channels)]; \
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Ddma_intel_adsp_hda_host_in.c29 .dma_channels = DT_INST_PROP(inst, dma_channels), \
Ddma_intel_adsp_hda_host_out.c33 .dma_channels = DT_INST_PROP(inst, dma_channels), \
Ddma_dw_axi.c303 if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) { in dma_dw_axi_isr()
457 if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) { in dma_dw_axi_config()
517 if (cfg->channel_priority < dw_dev_data->dma_ctx.dma_channels) { in dma_dw_axi_config()
646 if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) { in dma_dw_axi_start()
708 if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) { in dma_dw_axi_stop()
759 if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) { in dma_dw_axi_resume()
790 if (channel > (dw_dev_data->dma_ctx.dma_channels - 1)) { in dma_dw_axi_suspend()
842 for (i = 0; i < dw_dev_data->dma_ctx.dma_channels; i++) { in dma_dw_axi_init()
876 static struct dma_dw_axi_ch_data chan_##inst[DT_INST_PROP(inst, dma_channels)]; \
878 dma_desc_pool_##inst[DT_INST_PROP(inst, dma_channels) * \
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Ddma_intel_adsp_hda.h10 #define INTEL_ADSP_HDA_MAX_CHANNELS DT_PROP(DT_NODELABEL(hda_host_out), dma_channels)
28 uint32_t dma_channels; member
Ddma_nxp_sof_host_dma.c18 LISTIFY(DT_INST_PROP_OR(inst, dma_channels, 0), IDENTITY_VARGS, (,))
92 if (chan_id >= data->ctx.dma_channels) { in sof_host_dma_reload()
171 if (chan_id >= data->ctx.dma_channels) { in sof_host_dma_config()
301 .ctx.dma_channels = ARRAY_SIZE(channels),
Ddma_silabs_ldma.c287 for (chnum = 0; chnum < data->dma_ctx.dma_channels; chnum++) { in dma_silabs_irq_handler()
332 if (channel > data->dma_ctx.dma_channels) { in dma_silabs_configure()
435 if (channel > data->dma_ctx.dma_channels) { in dma_silabs_start()
451 if (channel > data->dma_ctx.dma_channels) { in dma_silabs_stop()
469 if (channel > data->dma_ctx.dma_channels) { in dma_silabs_get_status()
533 if (channel > data->dma_ctx.dma_channels) { in silabs_ldma_append_block()
598 static ATOMIC_DEFINE(dma_channels_atomic_##inst, DT_INST_PROP(inst, dma_channels)); \
601 dma_silabs_channel_##inst[DT_INST_PROP(inst, dma_channels)]; \
608 .dma_ctx.dma_channels = DT_INST_PROP(inst, dma_channels), \
Ddma_sam_xdmac.c48 struct sam_xdmac_channel_cfg dma_channels[DMA_CHANNELS_NO]; member
69 channel_cfg = &dev_data->dma_channels[channel]; in sam_xdmac_isr()
210 dev_data->dma_channels[channel].data_size = data_size; in sam_xdmac_config()
274 dev_data->dma_channels[channel].callback = cfg->dma_callback; in sam_xdmac_config()
275 dev_data->dma_channels[channel].user_data = cfg->user_data; in sam_xdmac_config()
294 .ublen = size >> dev_data->dma_channels[channel].data_size, in sam_xdmac_transfer_reload()
Ddma_renesas_rz.h24 {LISTIFY(DT_INST_PROP(inst, dma_channels), DMA_CHANNEL_DECLARE, (,), inst) }
Ddma_renesas_rz.c606 CONFIGURE_ALL_IRQS(inst, DT_INST_PROP(inst, dma_channels)); \
613 .num_channels = DT_INST_PROP(inst, dma_channels), \
617 static dmac_b_instance_ctrl_t g_transfer_ctrl[DT_INST_PROP(inst, dma_channels)]; \
618 static transfer_info_t g_transfer_info[DT_INST_PROP(inst, dma_channels)]; \
619 static dmac_b_extended_cfg_t g_transfer_extend[DT_INST_PROP(inst, dma_channels)]; \
621 dma_rz_##inst##_channels[DT_INST_PROP(inst, dma_channels)] = \
624 ATOMIC_DEFINE(dma_rz_atomic##inst, DT_INST_PROP(inst, dma_channels)); \
631 .dma_channels = DT_INST_PROP(inst, dma_channels), \
Ddma_xmc4xxx.c102 int num_dma_channels = dev_data->ctx.dma_channels; in dma_xmc4xxx_isr()
209 if (channel >= dev_data->ctx.dma_channels) { in dma_xmc4xxx_config()
501 if (channel >= dev_data->ctx.dma_channels) { in dma_xmc4xxx_reload()
537 if (channel >= dev_data->ctx.dma_channels) { in dma_xmc4xxx_get_status()
595 if (channel >= dev_data->ctx.dma_channels) { in dma_xmc4xxx_suspend()
610 if (channel >= dev_data->ctx.dma_channels) { in dma_xmc4xxx_resume()
654 dma_xmc4xxx##inst##_channels[DT_INST_PROP(inst, dma_channels)]; \
656 DT_INST_PROP(inst, dma_channels)); \
661 .dma_channels = DT_INST_PROP(inst, dma_channels), \
Ddma_mcux_edma.c41 int dma_channels; /* number of channels */ member
263 for (i = 0; i < DEV_CFG(dev)->dma_channels; i++) { in dma_mcux_edma_error_irq_handler()
326 if (channel >= DEV_CFG(dev)->dma_channels) { in dma_mcux_edma_configure()
852 for (i = 0; i < config->dma_channels / config->channels_per_mux; i++) { in dma_mcux_edma_init()
865 data->dma_ctx.dma_channels = config->dma_channels; in dma_mcux_edma_init()
890 (DT_INST_PROP(n, dma_channels) / 32)
934 {[0 ... 1] = DT_INST_PROP(n, dma_channels)}),
950 #define CHANNELS_PER_MUX(n) .channels_per_mux = DT_INST_PROP(n, dma_channels) / \
966 dma_tcdpool##n[DT_INST_PROP(n, dma_channels)][CONFIG_DMA_TCD_QUEUE_SIZE];\
971 .dma_channels = DT_INST_PROP(n, dma_channels), \
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Ddma_emul.c540 data->dma_ctx.dma_channels = config->num_channels; in dma_emul_init()
555 DMA_EMUL_INST_HAS_PROP(_inst, dma_channels) \
556 ? ((DT_INST_PROP(_inst, dma_channels) > 0) \
557 ? BIT_MASK(DT_INST_PROP_OR(_inst, dma_channels, 0)) \
562 DT_INST_PROP_OR(_inst, dma_channels, \
571 DMA_EMUL_INST_HAS_PROP(_inst, dma_channels), \
600 DT_INST_PROP_OR(_inst, dma_channels, 0)); \
Ddma_rpi_pico.c364 .channels = DT_INST_PROP(inst, dma_channels), \
371 dma_rpi_pico##inst##_channels[DT_INST_PROP(inst, dma_channels)]; \
372 ATOMIC_DEFINE(dma_rpi_pico_atomic##inst, DT_INST_PROP(inst, dma_channels)); \
378 .dma_channels = DT_INST_PROP(inst, dma_channels), \
Ddma_nxp_edma.c88 if (chan_id >= data->ctx.dma_channels) { in lookup_channel()
99 for (i = 0; i < data->ctx.dma_channels; i++) { in lookup_channel()
721 data->ctx.dma_channels = data->hal_cfg->channels; in edma_init()
738 BUILD_ASSERT(!DT_NODE_HAS_PROP(DT_INST(inst, DT_DRV_COMPAT), dma_channels) || \
742 BUILD_ASSERT(DT_INST_PROP_OR(inst, dma_channels, 0) == \
Ddma_wch.c481 .num_channels = DT_INST_PROP(idx, dma_channels), \
486 static struct dma_wch_channel dma_wch##idx##_channels[DT_INST_PROP(idx, dma_channels)]; \
487 ATOMIC_DEFINE(dma_wch_atomic##idx, DT_INST_PROP(idx, dma_channels)); \
493 .dma_channels = DT_INST_PROP(idx, dma_channels), \
Ddmamux_stm32.c376 dmamux_stm32_channels_##index[DT_INST_PROP(index, dma_channels)] = { \
377 DMAMUX_CHANNELS_INIT(index, DT_INST_PROP(index, dma_channels))\
383 .channel_nb = DT_INST_PROP(index, dma_channels), \
Ddma_stm32u5.c711 ((struct dma_stm32_data *)dev->data)->dma_ctx.dma_channels = 0; in dma_stm32_init()
773 LISTIFY(DT_INST_PROP(index, dma_channels), \
790 BUILD_ASSERT(DT_INST_PROP(index, dma_channels) \
794 LISTIFY(DT_INST_PROP(index, dma_channels), \
800 dma_stm32_streams_##index[DT_INST_PROP_OR(index, dma_channels, \
808 .max_streams = DT_INST_PROP_OR(index, dma_channels, \
Ddma_pl330.h51 #define MAX_DMA_CHANNELS DT_INST_PROP(0, dma_channels)
Ddma_ifx_cat1.c720 ifx_cat1_dma_channels##n[DT_INST_PROP(n, dma_channels)]; \
723 .num_channels = DT_INST_PROP(n, dma_channels), \
728 ATOMIC_DEFINE(ifx_cat1_dma_##n, DT_INST_PROP(n, dma_channels)); \
734 .dma_channels = DT_INST_PROP(n, dma_channels), \
Ddma_nxp_edma.h47 LISTIFY(DT_INST_PROP_OR(inst, dma_channels, 0), IDENTITY_VARGS, (,))
96 COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(inst, DT_DRV_COMPAT), dma_channels), \
106 DT_NODE_HAS_PROP(DT_INST(inst, DT_DRV_COMPAT), dma_channels)
/Zephyr-latest/include/zephyr/drivers/
Ddma.h301 int dma_channels; member
583 for (i = 0; i < dma_ctx->dma_channels; i++) { in z_impl_dma_request_channel()
625 if ((int)channel < dma_ctx->dma_channels) { in z_impl_dma_release_channel()

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