Searched refs:div0 (Results 1 – 2 of 2) sorted by relevance
790 uint32_t div0; in eth_xlnx_gem_configure_clocks() local831 for (div0 = 1; div0 < 64; div0++) { in eth_xlnx_gem_configure_clocks()833 tmp = ((dev_conf->pll_clock_frequency / div0) / div1); in eth_xlnx_gem_configure_clocks()857 clk_ctrl_reg |= ((div0 & ETH_XLNX_CRL_APB_GEMX_REF_CTRL_DIVISOR_MASK) << in eth_xlnx_gem_configure_clocks()883 clk_ctrl_reg |= ((div0 & ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR_MASK) << in eth_xlnx_gem_configure_clocks()892 "frequency %u Hz", dev->name, div0, div1, target); in eth_xlnx_gem_configure_clocks()
647 .div0 = 2, in imxrt_pre_init_display_interface()
