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Searched refs:dev_conf (Results 1 – 13 of 13) sorted by relevance

/Zephyr-latest/drivers/ethernet/
Deth_xlnx_gem.c97 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in DT_INST_FOREACH_STATUS_OKAY() local
103 if (dev_conf->init_phy) { in DT_INST_FOREACH_STATUS_OKAY()
104 __ASSERT((dev_conf->phy_mdio_addr_fix >= 0 && in DT_INST_FOREACH_STATUS_OKAY()
105 dev_conf->phy_mdio_addr_fix <= 32), in DT_INST_FOREACH_STATUS_OKAY()
108 dev->name, dev_conf->phy_mdio_addr_fix); in DT_INST_FOREACH_STATUS_OKAY()
109 __ASSERT(dev_conf->phy_poll_interval > 0, in DT_INST_FOREACH_STATUS_OKAY()
115 __ASSERT((dev_conf->max_link_speed == LINK_10MBIT || in DT_INST_FOREACH_STATUS_OKAY()
116 dev_conf->max_link_speed == LINK_100MBIT || in DT_INST_FOREACH_STATUS_OKAY()
117 dev_conf->max_link_speed == LINK_1GBIT), in DT_INST_FOREACH_STATUS_OKAY()
119 dev->name, (uint32_t)dev_conf->max_link_speed); in DT_INST_FOREACH_STATUS_OKAY()
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Dphy_xlnx_gem.c199 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_marvell_alaska_reset() local
209 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
212 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
217 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
234 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_marvell_alaska_cfg() local
247 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
250 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
267 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
271 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
274 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
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Deth_stellaris.c287 const struct eth_stellaris_config *dev_conf = dev->config; in eth_stellaris_init() local
302 dev_conf->config_func(dev); in eth_stellaris_init()
Deth_xlnx_gem_priv.h524 if (dev_conf->base_addr == DT_REG_ADDR_BY_IDX(DT_INST(port, xlnx_gem), 0)) {\
/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps_bank.h18 + ((uint32_t)dev_conf->bank_index * 0x8))
20 + ((uint32_t)dev_conf->bank_index * 0x8))
22 + ((uint32_t)dev_conf->bank_index * 0x4))
24 + ((uint32_t)dev_conf->bank_index * 0x4))
26 + ((uint32_t)dev_conf->bank_index * 0x40))
28 + ((uint32_t)dev_conf->bank_index * 0x40))
30 + ((uint32_t)dev_conf->bank_index * 0x40))
32 + ((uint32_t)dev_conf->bank_index * 0x40))
34 + ((uint32_t)dev_conf->bank_index * 0x40))
36 + ((uint32_t)dev_conf->bank_index * 0x40))
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Dgpio_xlnx_ps.c47 const struct gpio_xlnx_ps_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_init() local
57 for (bank = 0; bank < dev_conf->num_banks; bank++) { in gpio_xlnx_ps_init()
59 dev_conf->bank_devices[bank]->data; in gpio_xlnx_ps_init()
65 dev_conf->config_func(dev); in gpio_xlnx_ps_init()
84 const struct gpio_xlnx_ps_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_isr() local
92 for (bank = 0; bank < dev_conf->num_banks; bank++) { in gpio_xlnx_ps_isr()
93 api = dev_conf->bank_devices[bank]->api; in gpio_xlnx_ps_isr()
97 int_mask = api->get_pending_int(dev_conf->bank_devices[bank]); in gpio_xlnx_ps_isr()
101 dev_conf->bank_devices[bank]->data; in gpio_xlnx_ps_isr()
103 dev_conf->bank_devices[bank], int_mask); in gpio_xlnx_ps_isr()
Dgpio_xlnx_ps_bank.c53 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_pin_configure() local
134 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_get() local
167 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_set_masked() local
196 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_set_bits() local
225 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_clear_bits() local
254 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_toggle_bits() local
294 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_pin_irq_configure() local
371 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_get_int_status() local
433 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_init() local
/Zephyr-latest/drivers/sensor/st/lsm6dso16is/
Dlsm6dso16is_shub.c423 int (*dev_conf)(const struct device *dev, uint8_t i2c_addr, member
437 .dev_conf = (lsm6dso16is_lis2mdl_conf),
451 .dev_conf = (lsm6dso16is_hts221_conf),
478 .dev_conf = (lsm6dso16is_lps22hh_conf),
492 .dev_conf = (lsm6dso16is_lps22df_conf),
760 if (sp == NULL || sp->dev_conf == NULL) { in lsm6dso16is_shub_config()
765 return sp->dev_conf(dev, sp->ext_i2c_addr, chan, attr, val); in lsm6dso16is_shub_config()
/Zephyr-latest/drivers/sensor/st/lsm6dsv16x/
Dlsm6dsv16x_shub.c423 int (*dev_conf)(const struct device *dev, uint8_t i2c_addr, member
437 .dev_conf = (lsm6dsv16x_lis2mdl_conf),
451 .dev_conf = (lsm6dsv16x_hts221_conf),
478 .dev_conf = (lsm6dsv16x_lps22hh_conf),
492 .dev_conf = (lsm6dsv16x_lps22df_conf),
760 if (sp == NULL || sp->dev_conf == NULL) { in lsm6dsv16x_shub_config()
765 return sp->dev_conf(dev, sp->ext_i2c_addr, chan, attr, val); in lsm6dsv16x_shub_config()
/Zephyr-latest/drivers/sensor/st/lsm6dso/
Dlsm6dso_shub.c342 int (*dev_conf)(const struct device *dev, uint8_t i2c_addr, member
356 .dev_conf = (lsm6dso_lis2mdl_conf),
370 .dev_conf = (lsm6dso_hts221_conf),
397 .dev_conf = (lsm6dso_lps22hh_conf),
665 if (sp == NULL || sp->dev_conf == NULL) { in lsm6dso_shub_config()
670 return sp->dev_conf(dev, sp->ext_i2c_addr, chan, attr, val); in lsm6dso_shub_config()
/Zephyr-latest/drivers/sensor/st/iis2iclx/
Diis2iclx_shub.c358 int (*dev_conf)(const struct device *dev, uint8_t i2c_addr, member
372 .dev_conf = (iis2iclx_lis2mdl_conf),
386 .dev_conf = (iis2iclx_hts221_conf),
413 .dev_conf = (iis2iclx_lps22hh_conf),
740 if (sp == NULL || sp->dev_conf == NULL) { in iis2iclx_shub_config()
745 return sp->dev_conf(dev, sp->ext_i2c_addr, chan, attr, val); in iis2iclx_shub_config()
/Zephyr-latest/drivers/sensor/st/ism330dhcx/
Dism330dhcx_shub.c340 int (*dev_conf)(const struct device *dev, uint8_t i2c_addr, enum sensor_channel chan, member
353 .dev_conf = (ism330dhcx_lis2mdl_conf),
367 .dev_conf = (ism330dhcx_hts221_conf),
394 .dev_conf = (ism330dhcx_lps22hh_conf),
710 if (sp == NULL || sp->dev_conf == NULL) { in ism330dhcx_shub_config()
715 return sp->dev_conf(dev, sp->ext_i2c_addr, chan, attr, val); in ism330dhcx_shub_config()
/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac.c1070 const struct eth_dwc_xgmac_config *const dev_conf = in eth_dwc_xgmac_prefill_rx_desc() local
1073 (struct xgmac_dma_chnl_config *)&dev_conf->dma_chnl_cfg; in eth_dwc_xgmac_prefill_rx_desc()
1085 for (uint32_t dma_chnl = 0u; dma_chnl < dev_conf->num_dma_chnl; dma_chnl++) { in eth_dwc_xgmac_prefill_rx_desc()
1151 const struct eth_dwc_xgmac_config *const dev_conf = in eth_dwc_xgmac_iface_init() local
1164 dev_conf->irq_config_fn(dev); in eth_dwc_xgmac_iface_init()
1175 net_if_set_mtu(iface, dev_conf->mtu); in eth_dwc_xgmac_iface_init()
1176 LOG_DBG("%s: MTU size is set to %d", dev->name, dev_conf->mtu); in eth_dwc_xgmac_iface_init()
1177 if (device_is_ready(dev_conf->phy_dev)) { in eth_dwc_xgmac_iface_init()
1178 phy_link_callback_set(dev_conf->phy_dev, &phy_link_state_change_callback, in eth_dwc_xgmac_iface_init()
1196 const struct eth_dwc_xgmac_config *dev_conf = (struct eth_dwc_xgmac_config *)dev->config; in eth_dwc_xgmac_start_device() local
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